Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 579
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T109 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1788245260 Jun 26 06:01:16 PM PDT 24 Jun 26 06:01:20 PM PDT 24 216756349 ps
T509 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.779233098 Jun 26 06:01:04 PM PDT 24 Jun 26 06:01:07 PM PDT 24 117103453 ps
T97 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2875899091 Jun 26 06:00:52 PM PDT 24 Jun 26 06:00:55 PM PDT 24 102667215 ps
T510 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.601629999 Jun 26 06:01:16 PM PDT 24 Jun 26 06:01:19 PM PDT 24 156986768 ps
T511 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.814784209 Jun 26 06:00:59 PM PDT 24 Jun 26 06:01:02 PM PDT 24 86552677 ps
T98 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.513967447 Jun 26 06:00:54 PM PDT 24 Jun 26 06:01:00 PM PDT 24 834422062 ps
T512 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3510034459 Jun 26 06:00:54 PM PDT 24 Jun 26 06:00:58 PM PDT 24 27834429 ps
T513 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.395522183 Jun 26 06:01:06 PM PDT 24 Jun 26 06:01:09 PM PDT 24 57618521 ps
T110 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1908603061 Jun 26 06:01:00 PM PDT 24 Jun 26 06:01:04 PM PDT 24 113077315 ps
T514 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3257453644 Jun 26 06:01:17 PM PDT 24 Jun 26 06:01:21 PM PDT 24 531165995 ps
T515 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.41643324 Jun 26 06:00:55 PM PDT 24 Jun 26 06:00:58 PM PDT 24 280666717 ps
T106 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3658706146 Jun 26 06:00:58 PM PDT 24 Jun 26 06:01:01 PM PDT 24 14995438 ps
T516 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.5504772 Jun 26 06:00:55 PM PDT 24 Jun 26 06:00:58 PM PDT 24 39323376 ps
T517 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3935938873 Jun 26 06:01:25 PM PDT 24 Jun 26 06:01:27 PM PDT 24 125662522 ps
T111 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4179344349 Jun 26 06:00:58 PM PDT 24 Jun 26 06:01:01 PM PDT 24 835431874 ps
T518 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1389622526 Jun 26 06:00:59 PM PDT 24 Jun 26 06:01:04 PM PDT 24 204608121 ps
T519 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3516616689 Jun 26 06:01:15 PM PDT 24 Jun 26 06:01:18 PM PDT 24 59440187 ps
T520 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2448899277 Jun 26 06:01:14 PM PDT 24 Jun 26 06:01:16 PM PDT 24 24152697 ps
T521 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1420156278 Jun 26 06:01:00 PM PDT 24 Jun 26 06:01:04 PM PDT 24 40677897 ps
T522 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2739091283 Jun 26 06:01:07 PM PDT 24 Jun 26 06:01:10 PM PDT 24 73173192 ps
T523 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2235405089 Jun 26 06:01:15 PM PDT 24 Jun 26 06:01:18 PM PDT 24 27282574 ps
T524 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4047864270 Jun 26 06:00:59 PM PDT 24 Jun 26 06:01:03 PM PDT 24 17135468 ps
T525 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4277444277 Jun 26 06:01:17 PM PDT 24 Jun 26 06:01:19 PM PDT 24 29198368 ps
T526 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.786161044 Jun 26 06:01:15 PM PDT 24 Jun 26 06:01:18 PM PDT 24 55920376 ps
T527 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.103405061 Jun 26 06:01:01 PM PDT 24 Jun 26 06:01:07 PM PDT 24 176778842 ps
T528 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3417797255 Jun 26 06:01:08 PM PDT 24 Jun 26 06:01:11 PM PDT 24 20024352 ps
T100 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4230379671 Jun 26 06:00:50 PM PDT 24 Jun 26 06:00:53 PM PDT 24 47941620 ps
T529 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.799499742 Jun 26 06:01:05 PM PDT 24 Jun 26 06:01:08 PM PDT 24 39311126 ps
T530 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2546162375 Jun 26 06:00:52 PM PDT 24 Jun 26 06:00:56 PM PDT 24 36224677 ps
T531 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1354045711 Jun 26 06:01:04 PM PDT 24 Jun 26 06:01:07 PM PDT 24 326890925 ps
T532 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1445319208 Jun 26 06:01:07 PM PDT 24 Jun 26 06:01:10 PM PDT 24 178425471 ps
T533 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3466639786 Jun 26 06:00:59 PM PDT 24 Jun 26 06:01:01 PM PDT 24 34587994 ps
T534 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3838018025 Jun 26 06:01:24 PM PDT 24 Jun 26 06:01:27 PM PDT 24 24603024 ps
T535 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.920041105 Jun 26 06:01:13 PM PDT 24 Jun 26 06:01:15 PM PDT 24 16868320 ps
T536 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.505556611 Jun 26 06:01:27 PM PDT 24 Jun 26 06:01:30 PM PDT 24 54672045 ps
T537 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4215545201 Jun 26 06:01:04 PM PDT 24 Jun 26 06:01:07 PM PDT 24 25045259 ps
T538 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3127879009 Jun 26 06:01:23 PM PDT 24 Jun 26 06:01:25 PM PDT 24 38107609 ps
T539 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2548036959 Jun 26 06:01:16 PM PDT 24 Jun 26 06:01:19 PM PDT 24 148729410 ps
T540 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1210866633 Jun 26 06:01:01 PM PDT 24 Jun 26 06:01:04 PM PDT 24 17016345 ps
T541 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2025150066 Jun 26 06:01:01 PM PDT 24 Jun 26 06:01:04 PM PDT 24 40216874 ps
T542 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2162001672 Jun 26 06:01:03 PM PDT 24 Jun 26 06:01:07 PM PDT 24 128511875 ps
T543 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2307761914 Jun 26 06:01:06 PM PDT 24 Jun 26 06:01:10 PM PDT 24 176279668 ps
T544 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3530427554 Jun 26 06:02:44 PM PDT 24 Jun 26 06:02:46 PM PDT 24 25682442 ps
T545 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1348551782 Jun 26 06:01:26 PM PDT 24 Jun 26 06:01:29 PM PDT 24 31986954 ps
T546 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1822571835 Jun 26 06:00:58 PM PDT 24 Jun 26 06:01:00 PM PDT 24 26681922 ps
T547 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.170014758 Jun 26 06:01:24 PM PDT 24 Jun 26 06:01:25 PM PDT 24 28364470 ps
T548 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1994510576 Jun 26 06:01:25 PM PDT 24 Jun 26 06:01:28 PM PDT 24 123902235 ps
T549 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3178431130 Jun 26 06:01:21 PM PDT 24 Jun 26 06:01:23 PM PDT 24 31034929 ps
T550 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1166315676 Jun 26 06:01:25 PM PDT 24 Jun 26 06:01:28 PM PDT 24 63046796 ps
T551 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3636375607 Jun 26 06:00:58 PM PDT 24 Jun 26 06:01:00 PM PDT 24 118073122 ps
T552 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2467932644 Jun 26 06:00:51 PM PDT 24 Jun 26 06:00:56 PM PDT 24 46297008 ps
T553 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.169962264 Jun 26 06:01:00 PM PDT 24 Jun 26 06:01:04 PM PDT 24 34124873 ps
T554 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4223838710 Jun 26 06:01:16 PM PDT 24 Jun 26 06:01:18 PM PDT 24 15117825 ps
T99 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.124151652 Jun 26 06:01:07 PM PDT 24 Jun 26 06:01:10 PM PDT 24 30924525 ps
T555 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.337027198 Jun 26 06:01:18 PM PDT 24 Jun 26 06:01:21 PM PDT 24 16682863 ps
T556 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1222777900 Jun 26 06:01:06 PM PDT 24 Jun 26 06:01:10 PM PDT 24 57156463 ps
T557 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1454216365 Jun 26 06:01:03 PM PDT 24 Jun 26 06:01:06 PM PDT 24 45278903 ps
T558 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.179206283 Jun 26 06:01:16 PM PDT 24 Jun 26 06:01:19 PM PDT 24 57872446 ps
T559 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3835475989 Jun 26 06:00:57 PM PDT 24 Jun 26 06:01:02 PM PDT 24 72762392 ps
T560 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1242196620 Jun 26 06:01:26 PM PDT 24 Jun 26 06:01:30 PM PDT 24 19633721 ps
T561 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2978973470 Jun 26 06:01:23 PM PDT 24 Jun 26 06:01:25 PM PDT 24 12735604 ps
T562 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1339761503 Jun 26 06:01:08 PM PDT 24 Jun 26 06:01:11 PM PDT 24 48038838 ps
T563 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1114788179 Jun 26 06:00:52 PM PDT 24 Jun 26 06:00:55 PM PDT 24 13164105 ps
T564 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2160636130 Jun 26 06:01:06 PM PDT 24 Jun 26 06:01:10 PM PDT 24 700744798 ps
T565 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3394625387 Jun 26 06:01:06 PM PDT 24 Jun 26 06:01:09 PM PDT 24 41842699 ps
T566 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1786949106 Jun 26 06:01:08 PM PDT 24 Jun 26 06:01:11 PM PDT 24 15628276 ps
T567 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2291161336 Jun 26 06:00:59 PM PDT 24 Jun 26 06:01:03 PM PDT 24 52660537 ps
T568 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.521977231 Jun 26 06:01:29 PM PDT 24 Jun 26 06:01:31 PM PDT 24 39685197 ps
T569 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3380086228 Jun 26 06:01:05 PM PDT 24 Jun 26 06:01:08 PM PDT 24 147327944 ps
T570 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2147561539 Jun 26 06:01:14 PM PDT 24 Jun 26 06:01:18 PM PDT 24 96640074 ps
T571 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.263251590 Jun 26 06:01:26 PM PDT 24 Jun 26 06:01:29 PM PDT 24 43358998 ps
T572 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1120822855 Jun 26 06:00:59 PM PDT 24 Jun 26 06:01:03 PM PDT 24 1476386854 ps
T573 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2185714493 Jun 26 06:00:52 PM PDT 24 Jun 26 06:00:56 PM PDT 24 98783817 ps
T574 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.222866849 Jun 26 06:00:57 PM PDT 24 Jun 26 06:01:00 PM PDT 24 14720521 ps
T575 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3437169178 Jun 26 06:00:58 PM PDT 24 Jun 26 06:01:01 PM PDT 24 73276431 ps
T576 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.495469945 Jun 26 06:01:29 PM PDT 24 Jun 26 06:01:31 PM PDT 24 45581764 ps
T577 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3064295002 Jun 26 06:01:25 PM PDT 24 Jun 26 06:01:28 PM PDT 24 11741590 ps
T578 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1677962410 Jun 26 06:01:17 PM PDT 24 Jun 26 06:01:21 PM PDT 24 50383270 ps
T579 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1574952515 Jun 26 06:00:56 PM PDT 24 Jun 26 06:00:59 PM PDT 24 42451971 ps

Test location /workspace/coverage/default/197.rv_timer_random.2797071492
Short name T8
Test name
Test status
Simulation time 665397690879 ps
CPU time 333.64 seconds
Started Jun 26 06:03:40 PM PDT 24
Finished Jun 26 06:09:14 PM PDT 24
Peak memory 191168 kb
Host smart-63d8064a-c69c-4d8c-8e25-9a0fa4a1efce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797071492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2797071492
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3806917563
Short name T15
Test name
Test status
Simulation time 70186604610 ps
CPU time 341.14 seconds
Started Jun 26 06:02:01 PM PDT 24
Finished Jun 26 06:07:45 PM PDT 24
Peak memory 206036 kb
Host smart-b09a99fc-3f25-4eb2-8d9a-394c57e35330
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806917563 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3806917563
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.3635979292
Short name T11
Test name
Test status
Simulation time 322525572 ps
CPU time 0.91 seconds
Started Jun 26 06:01:27 PM PDT 24
Finished Jun 26 06:01:30 PM PDT 24
Peak memory 214496 kb
Host smart-a2b0b6b9-f2d2-473e-9667-1963afc52a2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635979292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.3635979292
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3549517216
Short name T121
Test name
Test status
Simulation time 292194691229 ps
CPU time 900.45 seconds
Started Jun 26 06:01:46 PM PDT 24
Finished Jun 26 06:16:48 PM PDT 24
Peak memory 191344 kb
Host smart-db224c6f-a0af-44bd-aea1-bf73b113d62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549517216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3549517216
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3122223417
Short name T22
Test name
Test status
Simulation time 684942878481 ps
CPU time 1880.13 seconds
Started Jun 26 06:02:07 PM PDT 24
Finished Jun 26 06:33:29 PM PDT 24
Peak memory 191368 kb
Host smart-c3c2d694-c45c-449f-9f99-091b6d02942f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122223417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3122223417
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2482512288
Short name T34
Test name
Test status
Simulation time 3657779040457 ps
CPU time 827.99 seconds
Started Jun 26 06:01:40 PM PDT 24
Finished Jun 26 06:15:30 PM PDT 24
Peak memory 191360 kb
Host smart-3f91d5d4-7fdc-44aa-9277-1df4c6da5ec4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482512288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2482512288
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.131135770
Short name T71
Test name
Test status
Simulation time 912402313598 ps
CPU time 1702.86 seconds
Started Jun 26 06:02:02 PM PDT 24
Finished Jun 26 06:30:27 PM PDT 24
Peak memory 191344 kb
Host smart-0c25eca3-4856-4897-b5d1-7fa3ba9f6e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131135770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
131135770
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.528888664
Short name T146
Test name
Test status
Simulation time 1957584746142 ps
CPU time 2205.5 seconds
Started Jun 26 06:02:05 PM PDT 24
Finished Jun 26 06:38:52 PM PDT 24
Peak memory 191156 kb
Host smart-0bfb0888-a23a-429b-bbcc-14ed1c754614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528888664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
528888664
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.4060948360
Short name T152
Test name
Test status
Simulation time 3664809893510 ps
CPU time 2185.92 seconds
Started Jun 26 06:02:01 PM PDT 24
Finished Jun 26 06:38:30 PM PDT 24
Peak memory 191344 kb
Host smart-0068fe24-7972-4b76-a60f-d1e238dc461a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060948360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.4060948360
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.768203216
Short name T166
Test name
Test status
Simulation time 2850808444997 ps
CPU time 4009.62 seconds
Started Jun 26 06:01:26 PM PDT 24
Finished Jun 26 07:08:18 PM PDT 24
Peak memory 191340 kb
Host smart-1c4465e6-e1f0-4734-8990-485091fbef5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768203216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.768203216
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3257686276
Short name T28
Test name
Test status
Simulation time 105582882 ps
CPU time 1.44 seconds
Started Jun 26 06:01:07 PM PDT 24
Finished Jun 26 06:01:11 PM PDT 24
Peak memory 195076 kb
Host smart-3de7fc1b-ad23-4d79-bc1c-c6634e651e22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257686276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3257686276
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3259610078
Short name T192
Test name
Test status
Simulation time 358607369887 ps
CPU time 895.69 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:16:45 PM PDT 24
Peak memory 191344 kb
Host smart-c73e7439-15ef-4c7b-818a-038f2e666488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259610078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3259610078
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3866387378
Short name T69
Test name
Test status
Simulation time 1297735205076 ps
CPU time 1160.68 seconds
Started Jun 26 06:01:57 PM PDT 24
Finished Jun 26 06:21:18 PM PDT 24
Peak memory 191340 kb
Host smart-dddbb28b-76ff-4276-ad06-6194b8326934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866387378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3866387378
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.866779536
Short name T40
Test name
Test status
Simulation time 87938866269 ps
CPU time 490.6 seconds
Started Jun 26 06:02:07 PM PDT 24
Finished Jun 26 06:10:19 PM PDT 24
Peak memory 197704 kb
Host smart-a9669011-3659-4243-b035-c7ebbde4385e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866779536 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.866779536
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.738967295
Short name T164
Test name
Test status
Simulation time 397769534425 ps
CPU time 1108.94 seconds
Started Jun 26 06:01:41 PM PDT 24
Finished Jun 26 06:20:12 PM PDT 24
Peak memory 191320 kb
Host smart-8923aee6-a275-41b6-942d-53c0405c339f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738967295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
738967295
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3556283620
Short name T66
Test name
Test status
Simulation time 546856874991 ps
CPU time 1112.06 seconds
Started Jun 26 06:02:02 PM PDT 24
Finished Jun 26 06:20:37 PM PDT 24
Peak memory 191324 kb
Host smart-da5a4046-f3da-45b3-8d18-1dfebd92d8ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556283620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3556283620
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random.309317138
Short name T79
Test name
Test status
Simulation time 398792213545 ps
CPU time 344.44 seconds
Started Jun 26 06:01:37 PM PDT 24
Finished Jun 26 06:07:23 PM PDT 24
Peak memory 191320 kb
Host smart-d3a5c1c1-e8a2-4b79-9be5-ea256c7c3cbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309317138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.309317138
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4234988374
Short name T245
Test name
Test status
Simulation time 248045082091 ps
CPU time 358.92 seconds
Started Jun 26 06:01:46 PM PDT 24
Finished Jun 26 06:07:46 PM PDT 24
Peak memory 191324 kb
Host smart-0d5c5736-cbd8-4115-a9fa-104fb2edc3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234988374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4234988374
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/59.rv_timer_random.4089719855
Short name T141
Test name
Test status
Simulation time 175178659076 ps
CPU time 111.16 seconds
Started Jun 26 06:02:19 PM PDT 24
Finished Jun 26 06:04:11 PM PDT 24
Peak memory 191348 kb
Host smart-ae9d660d-6d3f-419f-82b2-849b2d6ca39b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089719855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4089719855
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1682541818
Short name T67
Test name
Test status
Simulation time 512277721298 ps
CPU time 483.74 seconds
Started Jun 26 06:02:14 PM PDT 24
Finished Jun 26 06:10:19 PM PDT 24
Peak memory 191284 kb
Host smart-715b32b7-91e2-49ee-8827-761989f556ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682541818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1682541818
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/196.rv_timer_random.1736652402
Short name T252
Test name
Test status
Simulation time 290663557653 ps
CPU time 249.95 seconds
Started Jun 26 06:03:38 PM PDT 24
Finished Jun 26 06:07:48 PM PDT 24
Peak memory 191284 kb
Host smart-314f428c-d007-466e-99ab-b112458cf9dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736652402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1736652402
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3201978961
Short name T1
Test name
Test status
Simulation time 436968085772 ps
CPU time 227.23 seconds
Started Jun 26 06:02:40 PM PDT 24
Finished Jun 26 06:06:29 PM PDT 24
Peak memory 191344 kb
Host smart-a6d06c54-bbaa-41a6-8cc4-56260fddb28c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201978961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3201978961
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random.450609809
Short name T242
Test name
Test status
Simulation time 126969458421 ps
CPU time 330.19 seconds
Started Jun 26 06:02:02 PM PDT 24
Finished Jun 26 06:07:35 PM PDT 24
Peak memory 195056 kb
Host smart-873089c3-b185-4d38-923f-529aa9a0b88d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450609809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.450609809
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.2805422020
Short name T332
Test name
Test status
Simulation time 237349915092 ps
CPU time 207.3 seconds
Started Jun 26 06:01:50 PM PDT 24
Finished Jun 26 06:05:19 PM PDT 24
Peak memory 191580 kb
Host smart-785ea3ae-c373-4a7f-b98b-b56163f875df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805422020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2805422020
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3806473640
Short name T278
Test name
Test status
Simulation time 1074448766196 ps
CPU time 963.43 seconds
Started Jun 26 06:01:50 PM PDT 24
Finished Jun 26 06:17:55 PM PDT 24
Peak memory 191092 kb
Host smart-937cf0c4-09cb-477c-9a12-816a9e1900d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806473640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3806473640
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.763371454
Short name T86
Test name
Test status
Simulation time 3784694700921 ps
CPU time 2113.29 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:37:23 PM PDT 24
Peak memory 191332 kb
Host smart-d76b20aa-82f3-44c7-ad01-80ca69029efe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763371454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
763371454
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_random.2771193153
Short name T354
Test name
Test status
Simulation time 222149634188 ps
CPU time 233.08 seconds
Started Jun 26 06:01:23 PM PDT 24
Finished Jun 26 06:05:18 PM PDT 24
Peak memory 195256 kb
Host smart-f755e1b4-1821-4a5f-8ff2-4a48d52eb5e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771193153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2771193153
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.791677398
Short name T218
Test name
Test status
Simulation time 94999362920 ps
CPU time 175.34 seconds
Started Jun 26 06:02:53 PM PDT 24
Finished Jun 26 06:05:50 PM PDT 24
Peak memory 191356 kb
Host smart-a26be04e-4435-4d8f-9ec6-a98d35b968bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791677398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.791677398
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random.2853335415
Short name T44
Test name
Test status
Simulation time 150174889807 ps
CPU time 544.53 seconds
Started Jun 26 06:01:33 PM PDT 24
Finished Jun 26 06:10:39 PM PDT 24
Peak memory 193416 kb
Host smart-bc19d4c8-9e46-4dc8-b2f3-6b4f45ae3304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853335415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2853335415
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.2958665418
Short name T254
Test name
Test status
Simulation time 1256975967412 ps
CPU time 697.75 seconds
Started Jun 26 06:01:23 PM PDT 24
Finished Jun 26 06:13:02 PM PDT 24
Peak memory 191320 kb
Host smart-9f5cd0cb-3e64-4559-b5f2-3613f65cb824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958665418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2958665418
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2139602981
Short name T208
Test name
Test status
Simulation time 212291188777 ps
CPU time 2642.38 seconds
Started Jun 26 06:02:55 PM PDT 24
Finished Jun 26 06:46:59 PM PDT 24
Peak memory 191356 kb
Host smart-89489764-7dad-4402-9fb3-d94350a8daad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139602981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2139602981
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.809985744
Short name T178
Test name
Test status
Simulation time 102054914181 ps
CPU time 811.05 seconds
Started Jun 26 06:03:17 PM PDT 24
Finished Jun 26 06:16:50 PM PDT 24
Peak memory 191360 kb
Host smart-96748645-1fe2-4ecf-8cd1-d8d309a3bfff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809985744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.809985744
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3218218208
Short name T77
Test name
Test status
Simulation time 163473084400 ps
CPU time 261.97 seconds
Started Jun 26 06:02:15 PM PDT 24
Finished Jun 26 06:06:38 PM PDT 24
Peak memory 191376 kb
Host smart-2f867cdd-ed33-44e5-8b57-423606663014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218218208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3218218208
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.1393062109
Short name T74
Test name
Test status
Simulation time 385356732146 ps
CPU time 395.46 seconds
Started Jun 26 06:01:31 PM PDT 24
Finished Jun 26 06:08:08 PM PDT 24
Peak memory 191288 kb
Host smart-aaf76ba9-ce01-4ab1-b69d-ab405455b24f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393062109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1393062109
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.497280628
Short name T256
Test name
Test status
Simulation time 366092533798 ps
CPU time 207.8 seconds
Started Jun 26 06:02:34 PM PDT 24
Finished Jun 26 06:06:04 PM PDT 24
Peak memory 191328 kb
Host smart-e5119549-89fd-4aac-b396-a6c7aafe3d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497280628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.497280628
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3000279981
Short name T214
Test name
Test status
Simulation time 150897633966 ps
CPU time 393.14 seconds
Started Jun 26 06:02:34 PM PDT 24
Finished Jun 26 06:09:09 PM PDT 24
Peak memory 191364 kb
Host smart-5d1f59c6-1a13-4cc5-be3f-d25b33a8935c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000279981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3000279981
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2922092431
Short name T96
Test name
Test status
Simulation time 25553751 ps
CPU time 0.56 seconds
Started Jun 26 06:01:00 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 182324 kb
Host smart-331ffe8d-82f5-4bd7-99fd-ecb4038ce3e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922092431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2922092431
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/163.rv_timer_random.2103855664
Short name T128
Test name
Test status
Simulation time 110541662233 ps
CPU time 171.92 seconds
Started Jun 26 06:03:16 PM PDT 24
Finished Jun 26 06:06:09 PM PDT 24
Peak memory 191324 kb
Host smart-b0dc3639-3d50-4a09-9f79-b5a0285c7b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103855664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2103855664
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3873698622
Short name T236
Test name
Test status
Simulation time 1746230696809 ps
CPU time 1952.22 seconds
Started Jun 26 06:03:31 PM PDT 24
Finished Jun 26 06:36:05 PM PDT 24
Peak memory 191352 kb
Host smart-b040965e-b2d2-44ef-b551-f5bd564bdef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873698622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3873698622
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.861332738
Short name T223
Test name
Test status
Simulation time 664112001297 ps
CPU time 1708.79 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:30:31 PM PDT 24
Peak memory 191372 kb
Host smart-e5abc242-ad1d-4e98-b29e-ffc25166b354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861332738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
861332738
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3345286653
Short name T122
Test name
Test status
Simulation time 1839860664413 ps
CPU time 1011.32 seconds
Started Jun 26 06:02:06 PM PDT 24
Finished Jun 26 06:18:59 PM PDT 24
Peak memory 183136 kb
Host smart-32912aa9-f712-4ccf-a66c-a952108355b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345286653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3345286653
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/78.rv_timer_random.3112630986
Short name T174
Test name
Test status
Simulation time 259743765144 ps
CPU time 800.59 seconds
Started Jun 26 06:02:43 PM PDT 24
Finished Jun 26 06:16:06 PM PDT 24
Peak memory 191328 kb
Host smart-5997c1e2-ebea-4ee4-9d56-0861478a22a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112630986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3112630986
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1023147399
Short name T206
Test name
Test status
Simulation time 491285804823 ps
CPU time 192.64 seconds
Started Jun 26 06:01:43 PM PDT 24
Finished Jun 26 06:04:56 PM PDT 24
Peak memory 191352 kb
Host smart-b8721f2c-1c67-49d5-a523-457e449c79ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023147399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1023147399
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/119.rv_timer_random.2425090929
Short name T170
Test name
Test status
Simulation time 377107431872 ps
CPU time 479.65 seconds
Started Jun 26 06:02:47 PM PDT 24
Finished Jun 26 06:10:49 PM PDT 24
Peak memory 191264 kb
Host smart-08cab630-625e-42ea-af41-331da9009531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425090929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2425090929
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3885606589
Short name T127
Test name
Test status
Simulation time 613347249897 ps
CPU time 1273.27 seconds
Started Jun 26 06:03:06 PM PDT 24
Finished Jun 26 06:24:20 PM PDT 24
Peak memory 191176 kb
Host smart-37812bc8-000d-41a6-9ac5-c7727c9c5955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885606589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3885606589
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.722163602
Short name T299
Test name
Test status
Simulation time 149885393354 ps
CPU time 238.76 seconds
Started Jun 26 06:03:36 PM PDT 24
Finished Jun 26 06:07:36 PM PDT 24
Peak memory 194904 kb
Host smart-39763382-16c2-4c14-b01c-b2ee8d35eb62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722163602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.722163602
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.4181900834
Short name T59
Test name
Test status
Simulation time 1113530194066 ps
CPU time 1306.48 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:23:35 PM PDT 24
Peak memory 191308 kb
Host smart-61405716-4231-4601-8f3a-bd2a756ce436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181900834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.4181900834
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_random.848373330
Short name T321
Test name
Test status
Simulation time 655586100091 ps
CPU time 336.76 seconds
Started Jun 26 06:02:02 PM PDT 24
Finished Jun 26 06:07:41 PM PDT 24
Peak memory 191224 kb
Host smart-0d65694a-5ca3-4ffc-b243-ffdd13f5ee27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848373330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.848373330
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1014380667
Short name T271
Test name
Test status
Simulation time 870432991689 ps
CPU time 828.32 seconds
Started Jun 26 06:02:03 PM PDT 24
Finished Jun 26 06:15:54 PM PDT 24
Peak memory 191328 kb
Host smart-270e18a7-b2af-4ee2-8bc2-949acde9db2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014380667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1014380667
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_random.2999016423
Short name T81
Test name
Test status
Simulation time 319749245071 ps
CPU time 260.91 seconds
Started Jun 26 06:02:10 PM PDT 24
Finished Jun 26 06:06:32 PM PDT 24
Peak memory 195172 kb
Host smart-26498f60-9944-4c30-9801-bb89eec974fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999016423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2999016423
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1571783305
Short name T185
Test name
Test status
Simulation time 195590493342 ps
CPU time 541.3 seconds
Started Jun 26 06:01:37 PM PDT 24
Finished Jun 26 06:10:39 PM PDT 24
Peak memory 191288 kb
Host smart-3fc32996-ac2e-4db8-96a2-fc5773026011
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571783305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1571783305
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/113.rv_timer_random.1866967318
Short name T315
Test name
Test status
Simulation time 595620572550 ps
CPU time 242.09 seconds
Started Jun 26 06:02:46 PM PDT 24
Finished Jun 26 06:06:50 PM PDT 24
Peak memory 191244 kb
Host smart-ab3d3f31-6aa2-49ee-9e91-2b6c0221559c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866967318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1866967318
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2542198471
Short name T248
Test name
Test status
Simulation time 686878124586 ps
CPU time 341.15 seconds
Started Jun 26 06:03:05 PM PDT 24
Finished Jun 26 06:08:48 PM PDT 24
Peak memory 191176 kb
Host smart-42aa310a-7aac-442c-82a2-f2680bcd2c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542198471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2542198471
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2461498329
Short name T330
Test name
Test status
Simulation time 75475000849 ps
CPU time 111.34 seconds
Started Jun 26 06:03:03 PM PDT 24
Finished Jun 26 06:04:55 PM PDT 24
Peak memory 191264 kb
Host smart-e48d2d40-4e79-42eb-b9f0-2507e4d1f0d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461498329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2461498329
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.3814040766
Short name T235
Test name
Test status
Simulation time 114265613947 ps
CPU time 210.38 seconds
Started Jun 26 06:01:46 PM PDT 24
Finished Jun 26 06:05:17 PM PDT 24
Peak memory 191348 kb
Host smart-02ce8ccb-806f-4fa2-aa52-fcc3f32267f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814040766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3814040766
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.4273049174
Short name T282
Test name
Test status
Simulation time 498979176490 ps
CPU time 325.74 seconds
Started Jun 26 06:03:25 PM PDT 24
Finished Jun 26 06:08:52 PM PDT 24
Peak memory 191352 kb
Host smart-6a9647b5-fe07-4523-bcd9-cde1b4affee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273049174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4273049174
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1583258296
Short name T288
Test name
Test status
Simulation time 3034223644441 ps
CPU time 1257.26 seconds
Started Jun 26 06:01:54 PM PDT 24
Finished Jun 26 06:22:52 PM PDT 24
Peak memory 183148 kb
Host smart-35bf1d21-a6ff-46de-9d4f-1873414b2bc1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583258296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1583258296
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1751929863
Short name T309
Test name
Test status
Simulation time 21977074661 ps
CPU time 613.15 seconds
Started Jun 26 06:01:31 PM PDT 24
Finished Jun 26 06:11:46 PM PDT 24
Peak memory 183192 kb
Host smart-50a6165e-6d3e-4066-8ea9-9b71bd9bcbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751929863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1751929863
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.80678484
Short name T297
Test name
Test status
Simulation time 912214088148 ps
CPU time 920.62 seconds
Started Jun 26 06:01:39 PM PDT 24
Finished Jun 26 06:17:01 PM PDT 24
Peak memory 191324 kb
Host smart-77c1eb4c-8837-445d-81c0-f175440b9ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80678484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.80678484
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.461455361
Short name T93
Test name
Test status
Simulation time 70163540 ps
CPU time 0.62 seconds
Started Jun 26 06:00:51 PM PDT 24
Finished Jun 26 06:00:54 PM PDT 24
Peak memory 182332 kb
Host smart-efc84149-48d1-407e-9d03-f85c8317bb82
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461455361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.461455361
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1788245260
Short name T109
Test name
Test status
Simulation time 216756349 ps
CPU time 1.36 seconds
Started Jun 26 06:01:16 PM PDT 24
Finished Jun 26 06:01:20 PM PDT 24
Peak memory 182964 kb
Host smart-ef63d6ff-b9bc-4583-9620-687d317817a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788245260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1788245260
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/111.rv_timer_random.566535022
Short name T203
Test name
Test status
Simulation time 284330277867 ps
CPU time 325.57 seconds
Started Jun 26 06:02:47 PM PDT 24
Finished Jun 26 06:08:15 PM PDT 24
Peak memory 191364 kb
Host smart-74c1405c-fad1-42c3-877a-8fef846a240a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566535022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.566535022
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.496622990
Short name T442
Test name
Test status
Simulation time 81447273684 ps
CPU time 221.98 seconds
Started Jun 26 06:01:39 PM PDT 24
Finished Jun 26 06:05:23 PM PDT 24
Peak memory 191376 kb
Host smart-c09ef2bd-4765-4a53-8898-258b136bb431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496622990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.496622990
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2090054495
Short name T147
Test name
Test status
Simulation time 1161449913030 ps
CPU time 680.85 seconds
Started Jun 26 06:01:40 PM PDT 24
Finished Jun 26 06:13:02 PM PDT 24
Peak memory 183156 kb
Host smart-1f910246-864c-4398-9ddd-14372a870bc6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090054495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2090054495
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2294794265
Short name T284
Test name
Test status
Simulation time 591330816317 ps
CPU time 1198.18 seconds
Started Jun 26 06:01:45 PM PDT 24
Finished Jun 26 06:21:44 PM PDT 24
Peak memory 191340 kb
Host smart-2867fceb-becb-4d59-baee-3ddb3d155eca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294794265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2294794265
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/143.rv_timer_random.773429533
Short name T211
Test name
Test status
Simulation time 171335706151 ps
CPU time 94.57 seconds
Started Jun 26 06:03:03 PM PDT 24
Finished Jun 26 06:04:38 PM PDT 24
Peak memory 191248 kb
Host smart-9ce48d02-38bc-4098-a4c5-a63afb2ffbf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773429533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.773429533
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3408266310
Short name T355
Test name
Test status
Simulation time 370414385739 ps
CPU time 151.86 seconds
Started Jun 26 06:03:08 PM PDT 24
Finished Jun 26 06:05:41 PM PDT 24
Peak memory 191372 kb
Host smart-44d480ca-7f71-444a-8dc0-88c578bfdb18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408266310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3408266310
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2556795426
Short name T201
Test name
Test status
Simulation time 351141247525 ps
CPU time 442.11 seconds
Started Jun 26 06:03:17 PM PDT 24
Finished Jun 26 06:10:41 PM PDT 24
Peak memory 191284 kb
Host smart-fff2cae6-fe89-4dfb-8366-ade60a905119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556795426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2556795426
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2608850667
Short name T268
Test name
Test status
Simulation time 138059148357 ps
CPU time 296.18 seconds
Started Jun 26 06:03:24 PM PDT 24
Finished Jun 26 06:08:21 PM PDT 24
Peak memory 191356 kb
Host smart-2be73928-44b6-4432-9174-6ad7f5954b7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608850667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2608850667
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2924914068
Short name T300
Test name
Test status
Simulation time 177786376314 ps
CPU time 202.61 seconds
Started Jun 26 06:03:32 PM PDT 24
Finished Jun 26 06:06:55 PM PDT 24
Peak memory 194500 kb
Host smart-5d99219d-dfd6-42e4-b641-6364d7784ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924914068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2924914068
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.710906633
Short name T274
Test name
Test status
Simulation time 577680236806 ps
CPU time 319.55 seconds
Started Jun 26 06:01:30 PM PDT 24
Finished Jun 26 06:06:52 PM PDT 24
Peak memory 183072 kb
Host smart-f583c1a2-b05c-427a-b449-e5aa903ff3fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710906633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.710906633
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2337522402
Short name T237
Test name
Test status
Simulation time 57508334880 ps
CPU time 87.75 seconds
Started Jun 26 06:01:32 PM PDT 24
Finished Jun 26 06:03:01 PM PDT 24
Peak memory 183180 kb
Host smart-9d9769f1-fc4e-4f0a-8c8e-2f22666dbb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337522402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2337522402
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_random.2059743000
Short name T84
Test name
Test status
Simulation time 184325185492 ps
CPU time 224.93 seconds
Started Jun 26 06:01:58 PM PDT 24
Finished Jun 26 06:05:45 PM PDT 24
Peak memory 191360 kb
Host smart-eaad8c2a-2232-49e4-be8f-9c9db27718b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059743000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2059743000
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3215493724
Short name T215
Test name
Test status
Simulation time 1384393611912 ps
CPU time 1284.66 seconds
Started Jun 26 06:02:07 PM PDT 24
Finished Jun 26 06:23:33 PM PDT 24
Peak memory 191340 kb
Host smart-1bcfe6d8-e093-4f72-8629-877018c1aab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215493724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3215493724
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3547117230
Short name T294
Test name
Test status
Simulation time 1648349043437 ps
CPU time 559.2 seconds
Started Jun 26 06:02:09 PM PDT 24
Finished Jun 26 06:11:30 PM PDT 24
Peak memory 183148 kb
Host smart-0663794d-3602-4767-942e-d0b667d4a9e2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547117230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3547117230
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/77.rv_timer_random.3489739628
Short name T20
Test name
Test status
Simulation time 343245612390 ps
CPU time 1374.71 seconds
Started Jun 26 06:02:35 PM PDT 24
Finished Jun 26 06:25:31 PM PDT 24
Peak memory 191364 kb
Host smart-411aeb98-0dee-4c38-a997-a4cbef74e6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489739628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3489739628
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4179344349
Short name T111
Test name
Test status
Simulation time 835431874 ps
CPU time 1.34 seconds
Started Jun 26 06:00:58 PM PDT 24
Finished Jun 26 06:01:01 PM PDT 24
Peak memory 183004 kb
Host smart-cd9e7cee-6e3c-4ace-8a59-56c94d01e458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179344349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.4179344349
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/101.rv_timer_random.516373197
Short name T266
Test name
Test status
Simulation time 134118000055 ps
CPU time 148.35 seconds
Started Jun 26 06:02:40 PM PDT 24
Finished Jun 26 06:05:10 PM PDT 24
Peak memory 191332 kb
Host smart-c94971df-2bf0-40c8-82e3-485fd43b4272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516373197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.516373197
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2146180727
Short name T333
Test name
Test status
Simulation time 65524627889 ps
CPU time 1343.92 seconds
Started Jun 26 06:02:41 PM PDT 24
Finished Jun 26 06:25:07 PM PDT 24
Peak memory 191332 kb
Host smart-81254cb4-bc65-47c4-8a7f-65614fc390cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146180727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2146180727
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1049648015
Short name T344
Test name
Test status
Simulation time 52491535852 ps
CPU time 83.79 seconds
Started Jun 26 06:02:41 PM PDT 24
Finished Jun 26 06:04:06 PM PDT 24
Peak memory 191328 kb
Host smart-77753080-bf2e-4466-b1e7-7cb45c2f246f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049648015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1049648015
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3761562988
Short name T213
Test name
Test status
Simulation time 125710080918 ps
CPU time 99.01 seconds
Started Jun 26 06:02:47 PM PDT 24
Finished Jun 26 06:04:27 PM PDT 24
Peak memory 191352 kb
Host smart-8a2a157f-4bd5-447d-b27d-5b789fcca3bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761562988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3761562988
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.4180004286
Short name T182
Test name
Test status
Simulation time 342340724356 ps
CPU time 295.67 seconds
Started Jun 26 06:01:41 PM PDT 24
Finished Jun 26 06:06:38 PM PDT 24
Peak memory 183116 kb
Host smart-bb91fca2-01d9-4da4-b9fa-ddd0ccfd6efa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180004286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.4180004286
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/125.rv_timer_random.3371189843
Short name T210
Test name
Test status
Simulation time 290387030040 ps
CPU time 209.11 seconds
Started Jun 26 06:02:57 PM PDT 24
Finished Jun 26 06:06:27 PM PDT 24
Peak memory 191332 kb
Host smart-5e76d73a-345b-4457-9de2-201d085b6033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371189843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3371189843
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.4143392301
Short name T23
Test name
Test status
Simulation time 36309234614 ps
CPU time 71.53 seconds
Started Jun 26 06:02:57 PM PDT 24
Finished Jun 26 06:04:10 PM PDT 24
Peak memory 191360 kb
Host smart-2c043b23-a396-4359-a9f1-7280c7507629
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143392301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.4143392301
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2377432784
Short name T337
Test name
Test status
Simulation time 43007331090 ps
CPU time 79.07 seconds
Started Jun 26 06:03:01 PM PDT 24
Finished Jun 26 06:04:21 PM PDT 24
Peak memory 191332 kb
Host smart-58553baa-94d7-4208-9170-9bb8a2984fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377432784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2377432784
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.490588548
Short name T265
Test name
Test status
Simulation time 343767818253 ps
CPU time 416.35 seconds
Started Jun 26 06:03:02 PM PDT 24
Finished Jun 26 06:09:59 PM PDT 24
Peak memory 191376 kb
Host smart-ded97abe-593b-4dfa-835b-d250ed3afa93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490588548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.490588548
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1643028965
Short name T338
Test name
Test status
Simulation time 27081288467 ps
CPU time 42.76 seconds
Started Jun 26 06:01:39 PM PDT 24
Finished Jun 26 06:02:23 PM PDT 24
Peak memory 183156 kb
Host smart-1abf4f17-2ca5-4dae-851c-54126b43d1e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643028965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1643028965
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_random.1342019202
Short name T42
Test name
Test status
Simulation time 1758517538080 ps
CPU time 731.03 seconds
Started Jun 26 06:01:42 PM PDT 24
Finished Jun 26 06:13:54 PM PDT 24
Peak memory 191364 kb
Host smart-f1952362-b6ca-40bc-9fc7-daf41d6bd7b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342019202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1342019202
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2700689173
Short name T219
Test name
Test status
Simulation time 1190746557141 ps
CPU time 289.33 seconds
Started Jun 26 06:03:23 PM PDT 24
Finished Jun 26 06:08:13 PM PDT 24
Peak memory 191176 kb
Host smart-6b677b46-2e1a-4065-a9e4-75fae441526f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700689173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2700689173
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3778131855
Short name T314
Test name
Test status
Simulation time 432001064833 ps
CPU time 555.47 seconds
Started Jun 26 06:01:46 PM PDT 24
Finished Jun 26 06:11:03 PM PDT 24
Peak memory 191272 kb
Host smart-375402aa-3410-4b09-8c9d-bee22fa0270a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778131855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3778131855
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.2293448263
Short name T255
Test name
Test status
Simulation time 197345596886 ps
CPU time 664.9 seconds
Started Jun 26 06:03:25 PM PDT 24
Finished Jun 26 06:14:30 PM PDT 24
Peak memory 191280 kb
Host smart-8fab9f38-80f7-43c9-901b-776fd0185a14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293448263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2293448263
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3553137402
Short name T198
Test name
Test status
Simulation time 452733736015 ps
CPU time 284.17 seconds
Started Jun 26 06:03:33 PM PDT 24
Finished Jun 26 06:08:18 PM PDT 24
Peak memory 191568 kb
Host smart-fbc3e07d-b184-4590-8f29-5a2dbdc80849
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553137402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3553137402
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2447721802
Short name T27
Test name
Test status
Simulation time 120032331003 ps
CPU time 255.49 seconds
Started Jun 26 06:03:42 PM PDT 24
Finished Jun 26 06:07:58 PM PDT 24
Peak memory 191260 kb
Host smart-9103a157-83b6-468a-871c-0e2753c079b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447721802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2447721802
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1203222120
Short name T358
Test name
Test status
Simulation time 119586180433 ps
CPU time 84.88 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:03:13 PM PDT 24
Peak memory 191280 kb
Host smart-f4d1f904-c0d2-414a-8c35-bbe0e70143f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203222120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1203222120
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_random.342461799
Short name T153
Test name
Test status
Simulation time 272878055994 ps
CPU time 150.99 seconds
Started Jun 26 06:01:48 PM PDT 24
Finished Jun 26 06:04:21 PM PDT 24
Peak memory 191320 kb
Host smart-8134cf27-e2de-467a-9f8b-415d308b38cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342461799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.342461799
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2385972363
Short name T259
Test name
Test status
Simulation time 52706840763 ps
CPU time 109.22 seconds
Started Jun 26 06:01:48 PM PDT 24
Finished Jun 26 06:03:40 PM PDT 24
Peak memory 183052 kb
Host smart-599c1b7a-a62c-4ff5-b76b-292c77992449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385972363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2385972363
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1664600649
Short name T357
Test name
Test status
Simulation time 209348527595 ps
CPU time 112.93 seconds
Started Jun 26 06:01:48 PM PDT 24
Finished Jun 26 06:03:43 PM PDT 24
Peak memory 191352 kb
Host smart-f33906a1-a289-4934-805b-c1b8a6097507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664600649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1664600649
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1894483173
Short name T168
Test name
Test status
Simulation time 152865949216 ps
CPU time 186.88 seconds
Started Jun 26 06:02:00 PM PDT 24
Finished Jun 26 06:05:10 PM PDT 24
Peak memory 183104 kb
Host smart-7cfcd298-0aef-4c01-9551-248c5674ed1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894483173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1894483173
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2521876133
Short name T342
Test name
Test status
Simulation time 45225709093 ps
CPU time 89.3 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:03:30 PM PDT 24
Peak memory 183180 kb
Host smart-6ed2e4e6-8d48-4931-83d8-e6481e759893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521876133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2521876133
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_random.2783901818
Short name T134
Test name
Test status
Simulation time 916871809690 ps
CPU time 718.39 seconds
Started Jun 26 06:02:07 PM PDT 24
Finished Jun 26 06:14:07 PM PDT 24
Peak memory 191368 kb
Host smart-749bf1d5-0c78-45e2-82ce-dc851cf9a39c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783901818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2783901818
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2803506818
Short name T339
Test name
Test status
Simulation time 26734934907 ps
CPU time 30.14 seconds
Started Jun 26 06:01:58 PM PDT 24
Finished Jun 26 06:02:30 PM PDT 24
Peak memory 183124 kb
Host smart-b023728d-86fb-4f48-b018-65e29f9823ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803506818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2803506818
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2619715485
Short name T187
Test name
Test status
Simulation time 22087947540 ps
CPU time 99.11 seconds
Started Jun 26 06:02:10 PM PDT 24
Finished Jun 26 06:03:51 PM PDT 24
Peak memory 191300 kb
Host smart-02c529c7-e03b-4886-8e3d-4ae7f45b3c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619715485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2619715485
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3201669010
Short name T143
Test name
Test status
Simulation time 26663793813 ps
CPU time 48.26 seconds
Started Jun 26 06:02:09 PM PDT 24
Finished Jun 26 06:02:59 PM PDT 24
Peak memory 191308 kb
Host smart-1101a4e1-856e-40c3-ba7c-7e910cfebb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201669010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3201669010
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.3387711119
Short name T258
Test name
Test status
Simulation time 386159469813 ps
CPU time 317.19 seconds
Started Jun 26 06:02:23 PM PDT 24
Finished Jun 26 06:07:41 PM PDT 24
Peak memory 191364 kb
Host smart-c6fff9ec-cef3-4487-9709-e0a29923acfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387711119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3387711119
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2775122852
Short name T287
Test name
Test status
Simulation time 687325299268 ps
CPU time 130.6 seconds
Started Jun 26 06:02:26 PM PDT 24
Finished Jun 26 06:04:39 PM PDT 24
Peak memory 183176 kb
Host smart-ef10f4d0-1bf4-48aa-83c1-e8edb512d0e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775122852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2775122852
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2713262575
Short name T61
Test name
Test status
Simulation time 645153407426 ps
CPU time 737.1 seconds
Started Jun 26 06:02:37 PM PDT 24
Finished Jun 26 06:14:55 PM PDT 24
Peak memory 191336 kb
Host smart-9b415b2a-3c6d-4de3-80f0-7644896d8789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713262575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2713262575
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1933319932
Short name T202
Test name
Test status
Simulation time 500875427764 ps
CPU time 330.36 seconds
Started Jun 26 06:02:44 PM PDT 24
Finished Jun 26 06:08:16 PM PDT 24
Peak memory 191364 kb
Host smart-5698d4e4-a6cd-4d6a-b803-34d6289d5678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933319932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1933319932
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2875899091
Short name T97
Test name
Test status
Simulation time 102667215 ps
CPU time 0.71 seconds
Started Jun 26 06:00:52 PM PDT 24
Finished Jun 26 06:00:55 PM PDT 24
Peak memory 182332 kb
Host smart-2ecca792-b7e2-466e-8ef9-78cbaf17afb8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875899091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2875899091
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2515282884
Short name T481
Test name
Test status
Simulation time 37709895 ps
CPU time 1.42 seconds
Started Jun 26 06:00:51 PM PDT 24
Finished Jun 26 06:00:55 PM PDT 24
Peak memory 190688 kb
Host smart-1765fe59-385d-4d38-be6b-5593beaa195b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515282884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2515282884
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2521946517
Short name T502
Test name
Test status
Simulation time 22804449 ps
CPU time 0.6 seconds
Started Jun 26 06:00:55 PM PDT 24
Finished Jun 26 06:00:58 PM PDT 24
Peak memory 182308 kb
Host smart-21486ecc-e2f8-43e4-85d0-4b188b96df68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521946517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2521946517
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3032159612
Short name T63
Test name
Test status
Simulation time 28440154 ps
CPU time 0.63 seconds
Started Jun 26 06:00:51 PM PDT 24
Finished Jun 26 06:00:54 PM PDT 24
Peak memory 193292 kb
Host smart-dc3cd4d5-480f-4714-a407-21ea5178c97c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032159612 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3032159612
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.988657585
Short name T489
Test name
Test status
Simulation time 43601619 ps
CPU time 0.57 seconds
Started Jun 26 06:00:55 PM PDT 24
Finished Jun 26 06:00:58 PM PDT 24
Peak memory 182308 kb
Host smart-c7fd4261-ec5d-401f-a35d-11603e961da2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988657585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.988657585
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.5504772
Short name T516
Test name
Test status
Simulation time 39323376 ps
CPU time 0.57 seconds
Started Jun 26 06:00:55 PM PDT 24
Finished Jun 26 06:00:58 PM PDT 24
Peak memory 182480 kb
Host smart-69bbdcaa-d76d-4dbd-850a-a4aa0d1e4b18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5504772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.5504772
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2185714493
Short name T573
Test name
Test status
Simulation time 98783817 ps
CPU time 0.72 seconds
Started Jun 26 06:00:52 PM PDT 24
Finished Jun 26 06:00:56 PM PDT 24
Peak memory 192908 kb
Host smart-d3f998b6-c0d6-4480-ae9f-d433626c6fde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185714493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2185714493
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2467932644
Short name T552
Test name
Test status
Simulation time 46297008 ps
CPU time 2.25 seconds
Started Jun 26 06:00:51 PM PDT 24
Finished Jun 26 06:00:56 PM PDT 24
Peak memory 197128 kb
Host smart-44b209ea-1bd8-47a7-8ea6-66238a0f2a05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467932644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2467932644
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3639567808
Short name T30
Test name
Test status
Simulation time 357756952 ps
CPU time 1.11 seconds
Started Jun 26 06:01:00 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 182884 kb
Host smart-e64ec3ba-c786-45e3-aa4a-6b8314bbf5c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639567808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3639567808
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.4028146612
Short name T50
Test name
Test status
Simulation time 36516214 ps
CPU time 0.62 seconds
Started Jun 26 06:00:51 PM PDT 24
Finished Jun 26 06:00:54 PM PDT 24
Peak memory 182344 kb
Host smart-f62c6457-5181-4166-8b02-f71e2ace5eab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028146612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.4028146612
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3944683033
Short name T32
Test name
Test status
Simulation time 2085630217 ps
CPU time 3.65 seconds
Started Jun 26 06:00:57 PM PDT 24
Finished Jun 26 06:01:03 PM PDT 24
Peak memory 193320 kb
Host smart-2410200c-7338-492d-9a01-22731b6682fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944683033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3944683033
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2655463990
Short name T479
Test name
Test status
Simulation time 40433186 ps
CPU time 1.1 seconds
Started Jun 26 06:01:00 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 196960 kb
Host smart-27b2e65f-49b0-4920-abbb-403650ed50b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655463990 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2655463990
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4230379671
Short name T100
Test name
Test status
Simulation time 47941620 ps
CPU time 0.57 seconds
Started Jun 26 06:00:50 PM PDT 24
Finished Jun 26 06:00:53 PM PDT 24
Peak memory 182244 kb
Host smart-e1240bb7-2331-40b6-b3d4-bfa6e152e4ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230379671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.4230379671
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2841247492
Short name T475
Test name
Test status
Simulation time 13169246 ps
CPU time 0.54 seconds
Started Jun 26 06:00:54 PM PDT 24
Finished Jun 26 06:00:57 PM PDT 24
Peak memory 181668 kb
Host smart-315f1308-8059-43f6-94f0-195c8e8a206b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841247492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2841247492
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1574952515
Short name T579
Test name
Test status
Simulation time 42451971 ps
CPU time 0.8 seconds
Started Jun 26 06:00:56 PM PDT 24
Finished Jun 26 06:00:59 PM PDT 24
Peak memory 191248 kb
Host smart-582275d5-5103-4043-ba81-e82e55ce2bd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574952515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1574952515
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2546162375
Short name T530
Test name
Test status
Simulation time 36224677 ps
CPU time 1.48 seconds
Started Jun 26 06:00:52 PM PDT 24
Finished Jun 26 06:00:56 PM PDT 24
Peak memory 197128 kb
Host smart-71d21c42-b23a-43db-a220-6784154f56b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546162375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2546162375
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.41643324
Short name T515
Test name
Test status
Simulation time 280666717 ps
CPU time 1.07 seconds
Started Jun 26 06:00:55 PM PDT 24
Finished Jun 26 06:00:58 PM PDT 24
Peak memory 183184 kb
Host smart-55e1fcf4-8798-4f7e-9924-1d09505e4906
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41643324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_intg
_err.41643324
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3394625387
Short name T565
Test name
Test status
Simulation time 41842699 ps
CPU time 1.05 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:09 PM PDT 24
Peak memory 196868 kb
Host smart-680e8370-23e8-49d1-a2e0-b0f69a7f0d73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394625387 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3394625387
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3609313240
Short name T102
Test name
Test status
Simulation time 37615895 ps
CPU time 0.67 seconds
Started Jun 26 06:01:07 PM PDT 24
Finished Jun 26 06:01:10 PM PDT 24
Peak memory 182332 kb
Host smart-88fd88b2-7e0a-49e7-9a4d-84c20a61b3cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609313240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3609313240
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.724569339
Short name T482
Test name
Test status
Simulation time 22599512 ps
CPU time 0.58 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:08 PM PDT 24
Peak memory 182180 kb
Host smart-c2dc1fb2-5d4c-4c13-9d8f-21d68658ac1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724569339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.724569339
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2739091283
Short name T522
Test name
Test status
Simulation time 73173192 ps
CPU time 0.79 seconds
Started Jun 26 06:01:07 PM PDT 24
Finished Jun 26 06:01:10 PM PDT 24
Peak memory 191508 kb
Host smart-c1015dfd-bd9b-4740-932d-2d0eddbbf625
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739091283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2739091283
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2160636130
Short name T564
Test name
Test status
Simulation time 700744798 ps
CPU time 2.76 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:10 PM PDT 24
Peak memory 197092 kb
Host smart-a3e18b1e-947c-42b9-915b-51ac61b42c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160636130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2160636130
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1222777900
Short name T556
Test name
Test status
Simulation time 57156463 ps
CPU time 1.41 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:10 PM PDT 24
Peak memory 197068 kb
Host smart-a532d28d-aa55-4561-b212-23b2432b157a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222777900 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1222777900
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.799499742
Short name T529
Test name
Test status
Simulation time 39311126 ps
CPU time 0.57 seconds
Started Jun 26 06:01:05 PM PDT 24
Finished Jun 26 06:01:08 PM PDT 24
Peak memory 182244 kb
Host smart-aa0fcf43-e3ee-469c-8f75-0c9c929aea6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799499742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.799499742
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3029510917
Short name T461
Test name
Test status
Simulation time 46640210 ps
CPU time 0.54 seconds
Started Jun 26 06:01:08 PM PDT 24
Finished Jun 26 06:01:12 PM PDT 24
Peak memory 181872 kb
Host smart-bd5630a7-5c4e-4d25-b1d6-ec55f96a5115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029510917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3029510917
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1445319208
Short name T532
Test name
Test status
Simulation time 178425471 ps
CPU time 0.74 seconds
Started Jun 26 06:01:07 PM PDT 24
Finished Jun 26 06:01:10 PM PDT 24
Peak memory 192916 kb
Host smart-fe24cdf0-cff3-4369-a408-465b4f6d2973
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445319208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1445319208
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2209460831
Short name T470
Test name
Test status
Simulation time 88318511 ps
CPU time 1.67 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:09 PM PDT 24
Peak memory 197104 kb
Host smart-64739423-d19f-4ef4-a925-9acdea930813
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209460831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2209460831
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.779233098
Short name T509
Test name
Test status
Simulation time 117103453 ps
CPU time 0.82 seconds
Started Jun 26 06:01:04 PM PDT 24
Finished Jun 26 06:01:07 PM PDT 24
Peak memory 193336 kb
Host smart-101643b6-e91d-4fa4-b079-cf846c8e0fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779233098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.779233098
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1091202009
Short name T483
Test name
Test status
Simulation time 18919737 ps
CPU time 0.72 seconds
Started Jun 26 06:01:15 PM PDT 24
Finished Jun 26 06:01:18 PM PDT 24
Peak memory 194212 kb
Host smart-2f76f550-0705-4dbd-bd4c-e98e6683514d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091202009 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1091202009
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.395522183
Short name T513
Test name
Test status
Simulation time 57618521 ps
CPU time 0.58 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:09 PM PDT 24
Peak memory 182304 kb
Host smart-304fce70-5461-4597-85b7-8b062773a61b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395522183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.395522183
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.214206013
Short name T504
Test name
Test status
Simulation time 17176629 ps
CPU time 0.59 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:09 PM PDT 24
Peak memory 182200 kb
Host smart-80ffdc45-df32-436b-a7b0-accc552ae3c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214206013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.214206013
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3417797255
Short name T528
Test name
Test status
Simulation time 20024352 ps
CPU time 0.62 seconds
Started Jun 26 06:01:08 PM PDT 24
Finished Jun 26 06:01:11 PM PDT 24
Peak memory 191516 kb
Host smart-28521d51-1655-4b37-b91e-80d7f98d8a17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417797255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3417797255
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2307761914
Short name T543
Test name
Test status
Simulation time 176279668 ps
CPU time 1.98 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:10 PM PDT 24
Peak memory 197128 kb
Host smart-ef2fb03e-8fc9-4aad-9be9-542b4a68eb7d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307761914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2307761914
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1454216365
Short name T557
Test name
Test status
Simulation time 45278903 ps
CPU time 0.81 seconds
Started Jun 26 06:01:03 PM PDT 24
Finished Jun 26 06:01:06 PM PDT 24
Peak memory 182748 kb
Host smart-b2785227-80fb-4718-ba36-33a50ece6f92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454216365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1454216365
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.920041105
Short name T535
Test name
Test status
Simulation time 16868320 ps
CPU time 0.66 seconds
Started Jun 26 06:01:13 PM PDT 24
Finished Jun 26 06:01:15 PM PDT 24
Peak memory 192416 kb
Host smart-7af26327-4286-4cb3-9866-fb3d8fdfbe26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920041105 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.920041105
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2100268987
Short name T64
Test name
Test status
Simulation time 40215118 ps
CPU time 0.52 seconds
Started Jun 26 06:01:17 PM PDT 24
Finished Jun 26 06:01:20 PM PDT 24
Peak memory 182036 kb
Host smart-9d88d32c-8686-491b-a5e0-33d8beaf625d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100268987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2100268987
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4277444277
Short name T525
Test name
Test status
Simulation time 29198368 ps
CPU time 0.55 seconds
Started Jun 26 06:01:17 PM PDT 24
Finished Jun 26 06:01:19 PM PDT 24
Peak memory 182260 kb
Host smart-11fcd3d2-9fb9-43ce-ad08-eeead49e7aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277444277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.4277444277
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1439976533
Short name T89
Test name
Test status
Simulation time 195957752 ps
CPU time 0.75 seconds
Started Jun 26 06:01:18 PM PDT 24
Finished Jun 26 06:01:21 PM PDT 24
Peak memory 191880 kb
Host smart-19fd318a-6e68-4958-b978-81a71dda4175
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439976533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1439976533
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1420629186
Short name T65
Test name
Test status
Simulation time 182638707 ps
CPU time 2.52 seconds
Started Jun 26 06:01:20 PM PDT 24
Finished Jun 26 06:01:24 PM PDT 24
Peak memory 197080 kb
Host smart-35e97891-1132-458d-b19e-34b23cd7845d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420629186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1420629186
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3257453644
Short name T514
Test name
Test status
Simulation time 531165995 ps
CPU time 1.37 seconds
Started Jun 26 06:01:17 PM PDT 24
Finished Jun 26 06:01:21 PM PDT 24
Peak memory 194656 kb
Host smart-712ecefa-1523-469f-9038-fc77978eef98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257453644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3257453644
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1933877659
Short name T498
Test name
Test status
Simulation time 18095066 ps
CPU time 0.7 seconds
Started Jun 26 06:01:14 PM PDT 24
Finished Jun 26 06:01:16 PM PDT 24
Peak memory 194320 kb
Host smart-3c18f1d3-13a7-4013-88de-f5a0cd91d814
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933877659 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1933877659
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3181612094
Short name T88
Test name
Test status
Simulation time 43797187 ps
CPU time 0.59 seconds
Started Jun 26 06:01:15 PM PDT 24
Finished Jun 26 06:01:18 PM PDT 24
Peak memory 182336 kb
Host smart-4d03c3e9-217e-4a6e-8565-a6e85842bc29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181612094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3181612094
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2437732490
Short name T490
Test name
Test status
Simulation time 35897232 ps
CPU time 0.56 seconds
Started Jun 26 06:01:15 PM PDT 24
Finished Jun 26 06:01:18 PM PDT 24
Peak memory 182224 kb
Host smart-bfe1688e-2d91-490d-accf-b53643edf7a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437732490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2437732490
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2548036959
Short name T539
Test name
Test status
Simulation time 148729410 ps
CPU time 0.59 seconds
Started Jun 26 06:01:16 PM PDT 24
Finished Jun 26 06:01:19 PM PDT 24
Peak memory 191028 kb
Host smart-b167c811-5795-4f7f-bde4-ea8234ce3456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548036959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2548036959
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2147561539
Short name T570
Test name
Test status
Simulation time 96640074 ps
CPU time 2.39 seconds
Started Jun 26 06:01:14 PM PDT 24
Finished Jun 26 06:01:18 PM PDT 24
Peak memory 197120 kb
Host smart-22e60380-7d01-46d4-8abe-abc5567b8968
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147561539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2147561539
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2211100285
Short name T112
Test name
Test status
Simulation time 209969775 ps
CPU time 1.32 seconds
Started Jun 26 06:01:16 PM PDT 24
Finished Jun 26 06:01:20 PM PDT 24
Peak memory 195232 kb
Host smart-ba291302-e921-4259-96b6-1b9e3f263425
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211100285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2211100285
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.179206283
Short name T558
Test name
Test status
Simulation time 57872446 ps
CPU time 0.74 seconds
Started Jun 26 06:01:16 PM PDT 24
Finished Jun 26 06:01:19 PM PDT 24
Peak memory 194572 kb
Host smart-057b1bd1-4e74-4c20-b3b1-454f2affae3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179206283 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.179206283
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2448899277
Short name T520
Test name
Test status
Simulation time 24152697 ps
CPU time 0.58 seconds
Started Jun 26 06:01:14 PM PDT 24
Finished Jun 26 06:01:16 PM PDT 24
Peak memory 182332 kb
Host smart-2c5f9ff0-bc3f-45f8-b8d7-0e7bc61c627c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448899277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2448899277
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1904509921
Short name T508
Test name
Test status
Simulation time 49227879 ps
CPU time 0.59 seconds
Started Jun 26 06:01:14 PM PDT 24
Finished Jun 26 06:01:17 PM PDT 24
Peak memory 182132 kb
Host smart-e3ee4b58-61ca-4f38-9806-af5e5cd4cb4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904509921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1904509921
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2146782925
Short name T103
Test name
Test status
Simulation time 43791974 ps
CPU time 0.66 seconds
Started Jun 26 06:01:15 PM PDT 24
Finished Jun 26 06:01:17 PM PDT 24
Peak memory 191188 kb
Host smart-240b837b-08e5-48a7-b2a4-021c2d1fae0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146782925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2146782925
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.536093676
Short name T52
Test name
Test status
Simulation time 856398352 ps
CPU time 3.13 seconds
Started Jun 26 06:01:17 PM PDT 24
Finished Jun 26 06:01:22 PM PDT 24
Peak memory 197124 kb
Host smart-635c72f4-8655-40f6-81b7-028536d697a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536093676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.536093676
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.337027198
Short name T555
Test name
Test status
Simulation time 16682863 ps
CPU time 0.63 seconds
Started Jun 26 06:01:18 PM PDT 24
Finished Jun 26 06:01:21 PM PDT 24
Peak memory 192468 kb
Host smart-d17c4428-e2b8-404d-8563-79e37fe704ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337027198 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.337027198
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.786161044
Short name T526
Test name
Test status
Simulation time 55920376 ps
CPU time 0.55 seconds
Started Jun 26 06:01:15 PM PDT 24
Finished Jun 26 06:01:18 PM PDT 24
Peak memory 182028 kb
Host smart-97ec51be-f411-4b80-b113-7db3f69622a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786161044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.786161044
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.240741422
Short name T462
Test name
Test status
Simulation time 55929719 ps
CPU time 0.6 seconds
Started Jun 26 06:01:14 PM PDT 24
Finished Jun 26 06:01:15 PM PDT 24
Peak memory 182200 kb
Host smart-435c0614-d7cc-42ca-b0d6-03d776550b80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240741422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.240741422
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2235405089
Short name T523
Test name
Test status
Simulation time 27282574 ps
CPU time 0.65 seconds
Started Jun 26 06:01:15 PM PDT 24
Finished Jun 26 06:01:18 PM PDT 24
Peak memory 191276 kb
Host smart-5093a732-2c55-478c-9a8a-7b89a9c5d24c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235405089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2235405089
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.670486366
Short name T54
Test name
Test status
Simulation time 645503489 ps
CPU time 2 seconds
Started Jun 26 06:01:17 PM PDT 24
Finished Jun 26 06:01:22 PM PDT 24
Peak memory 197104 kb
Host smart-d28b7a17-2799-4541-b67a-0222d9d73ebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670486366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.670486366
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3945576014
Short name T113
Test name
Test status
Simulation time 146358207 ps
CPU time 0.84 seconds
Started Jun 26 06:01:17 PM PDT 24
Finished Jun 26 06:01:21 PM PDT 24
Peak memory 182836 kb
Host smart-1c5b0722-d7b1-44ef-901f-ce8dd231c7f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945576014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3945576014
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.1322228635
Short name T458
Test name
Test status
Simulation time 22177077 ps
CPU time 0.98 seconds
Started Jun 26 06:01:16 PM PDT 24
Finished Jun 26 06:01:19 PM PDT 24
Peak memory 196760 kb
Host smart-0195a285-08f7-40bc-8d73-663c34c0b7ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322228635 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.1322228635
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3796796953
Short name T94
Test name
Test status
Simulation time 32938578 ps
CPU time 0.56 seconds
Started Jun 26 06:01:15 PM PDT 24
Finished Jun 26 06:01:18 PM PDT 24
Peak memory 182556 kb
Host smart-5a5428a2-0365-4888-a538-485208beae58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796796953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3796796953
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3516616689
Short name T519
Test name
Test status
Simulation time 59440187 ps
CPU time 0.57 seconds
Started Jun 26 06:01:15 PM PDT 24
Finished Jun 26 06:01:18 PM PDT 24
Peak memory 182192 kb
Host smart-3bb5003c-a518-44e0-97bd-e856b56d8360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516616689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3516616689
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3482509530
Short name T91
Test name
Test status
Simulation time 52451345 ps
CPU time 0.59 seconds
Started Jun 26 06:01:15 PM PDT 24
Finished Jun 26 06:01:17 PM PDT 24
Peak memory 191532 kb
Host smart-3002de3f-857a-47a7-8e97-99b03fc829a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482509530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3482509530
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1677962410
Short name T578
Test name
Test status
Simulation time 50383270 ps
CPU time 2.29 seconds
Started Jun 26 06:01:17 PM PDT 24
Finished Jun 26 06:01:21 PM PDT 24
Peak memory 197040 kb
Host smart-be789e92-e031-4ef2-ba1a-35b6a423193c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677962410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1677962410
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3974271833
Short name T29
Test name
Test status
Simulation time 266549678 ps
CPU time 0.83 seconds
Started Jun 26 06:01:20 PM PDT 24
Finished Jun 26 06:01:22 PM PDT 24
Peak memory 182672 kb
Host smart-4d25c83b-32e9-4222-9e59-3925af992258
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974271833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3974271833
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1420368293
Short name T53
Test name
Test status
Simulation time 19896653 ps
CPU time 0.73 seconds
Started Jun 26 06:01:16 PM PDT 24
Finished Jun 26 06:01:19 PM PDT 24
Peak memory 194316 kb
Host smart-69bef656-077e-403b-a03d-770888bd839a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420368293 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1420368293
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.24892250
Short name T95
Test name
Test status
Simulation time 71569143 ps
CPU time 0.59 seconds
Started Jun 26 06:01:16 PM PDT 24
Finished Jun 26 06:01:19 PM PDT 24
Peak memory 182340 kb
Host smart-939bdded-5e44-49ae-bb63-edef5f966da3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24892250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.24892250
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4223838710
Short name T554
Test name
Test status
Simulation time 15117825 ps
CPU time 0.56 seconds
Started Jun 26 06:01:16 PM PDT 24
Finished Jun 26 06:01:18 PM PDT 24
Peak memory 181876 kb
Host smart-f8631ce2-012a-4931-9c08-29c3b6088246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223838710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.4223838710
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1619438058
Short name T104
Test name
Test status
Simulation time 66856139 ps
CPU time 0.71 seconds
Started Jun 26 06:01:19 PM PDT 24
Finished Jun 26 06:01:22 PM PDT 24
Peak memory 192856 kb
Host smart-3079104a-1bca-4188-843f-b9c6536de262
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619438058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1619438058
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4124008515
Short name T478
Test name
Test status
Simulation time 48312459 ps
CPU time 2.19 seconds
Started Jun 26 06:02:16 PM PDT 24
Finished Jun 26 06:02:18 PM PDT 24
Peak memory 197056 kb
Host smart-f080716d-5b74-43aa-8967-7a5bd24330d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124008515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.4124008515
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.601629999
Short name T510
Test name
Test status
Simulation time 156986768 ps
CPU time 0.82 seconds
Started Jun 26 06:01:16 PM PDT 24
Finished Jun 26 06:01:19 PM PDT 24
Peak memory 193152 kb
Host smart-8e33bae0-daa2-4e35-b9f8-95cec1f9b71f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601629999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.601629999
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3178431130
Short name T549
Test name
Test status
Simulation time 31034929 ps
CPU time 1.12 seconds
Started Jun 26 06:01:21 PM PDT 24
Finished Jun 26 06:01:23 PM PDT 24
Peak memory 197080 kb
Host smart-ed8e4d76-1641-4cc3-a60a-e7d38705778a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178431130 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3178431130
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.869200057
Short name T92
Test name
Test status
Simulation time 46107643 ps
CPU time 0.59 seconds
Started Jun 26 06:01:24 PM PDT 24
Finished Jun 26 06:01:26 PM PDT 24
Peak memory 182300 kb
Host smart-549c4b28-4617-4532-8c83-2565540dba27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869200057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.869200057
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3064295002
Short name T577
Test name
Test status
Simulation time 11741590 ps
CPU time 0.56 seconds
Started Jun 26 06:01:25 PM PDT 24
Finished Jun 26 06:01:28 PM PDT 24
Peak memory 182248 kb
Host smart-9ebe9765-91c3-4772-8ef0-2dec232a8817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064295002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3064295002
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3935938873
Short name T517
Test name
Test status
Simulation time 125662522 ps
CPU time 0.72 seconds
Started Jun 26 06:01:25 PM PDT 24
Finished Jun 26 06:01:27 PM PDT 24
Peak memory 191296 kb
Host smart-3e1e231a-d8bc-4c47-b5b4-568d2d20983a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935938873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3935938873
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1994510576
Short name T548
Test name
Test status
Simulation time 123902235 ps
CPU time 2.15 seconds
Started Jun 26 06:01:25 PM PDT 24
Finished Jun 26 06:01:28 PM PDT 24
Peak memory 197128 kb
Host smart-30c288da-8af4-4a76-9b93-95b4670ee910
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994510576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1994510576
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.812560317
Short name T500
Test name
Test status
Simulation time 367172211 ps
CPU time 1.27 seconds
Started Jun 26 06:01:23 PM PDT 24
Finished Jun 26 06:01:26 PM PDT 24
Peak memory 182972 kb
Host smart-eaa93642-b105-4db1-9a43-6ad0de5324c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812560317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.812560317
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3630593869
Short name T108
Test name
Test status
Simulation time 49708369 ps
CPU time 0.72 seconds
Started Jun 26 06:00:56 PM PDT 24
Finished Jun 26 06:00:59 PM PDT 24
Peak memory 182308 kb
Host smart-5beed815-b628-461a-9a9a-b3086bb07bdf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630593869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3630593869
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.513967447
Short name T98
Test name
Test status
Simulation time 834422062 ps
CPU time 3.6 seconds
Started Jun 26 06:00:54 PM PDT 24
Finished Jun 26 06:01:00 PM PDT 24
Peak memory 190664 kb
Host smart-0c721dbf-196b-4a5c-ba28-9599fa20ae10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513967447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.513967447
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2900863665
Short name T467
Test name
Test status
Simulation time 47556709 ps
CPU time 0.57 seconds
Started Jun 26 06:00:52 PM PDT 24
Finished Jun 26 06:00:55 PM PDT 24
Peak memory 182212 kb
Host smart-e92bdbeb-b124-4dad-a52d-6f34c9e58e27
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900863665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2900863665
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3437169178
Short name T575
Test name
Test status
Simulation time 73276431 ps
CPU time 1 seconds
Started Jun 26 06:00:58 PM PDT 24
Finished Jun 26 06:01:01 PM PDT 24
Peak memory 196880 kb
Host smart-99f25055-cb45-4d02-8571-8bad5ad3c3b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437169178 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3437169178
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3510034459
Short name T512
Test name
Test status
Simulation time 27834429 ps
CPU time 0.55 seconds
Started Jun 26 06:00:54 PM PDT 24
Finished Jun 26 06:00:58 PM PDT 24
Peak memory 182072 kb
Host smart-1915ae4d-c893-4de5-a549-b92bc761f0e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510034459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3510034459
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1114788179
Short name T563
Test name
Test status
Simulation time 13164105 ps
CPU time 0.57 seconds
Started Jun 26 06:00:52 PM PDT 24
Finished Jun 26 06:00:55 PM PDT 24
Peak memory 181688 kb
Host smart-acb10830-0230-406d-8324-3c8fff53e38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114788179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1114788179
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1210866633
Short name T540
Test name
Test status
Simulation time 17016345 ps
CPU time 0.69 seconds
Started Jun 26 06:01:01 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 192812 kb
Host smart-8d8ad318-72d7-4582-bc13-a7dc1a3ddec3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210866633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1210866633
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3498471001
Short name T455
Test name
Test status
Simulation time 237360366 ps
CPU time 1.86 seconds
Started Jun 26 06:00:56 PM PDT 24
Finished Jun 26 06:01:00 PM PDT 24
Peak memory 197072 kb
Host smart-ee00467f-cabc-480c-b00a-3b05a4231b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498471001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3498471001
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.814784209
Short name T511
Test name
Test status
Simulation time 86552677 ps
CPU time 0.85 seconds
Started Jun 26 06:00:59 PM PDT 24
Finished Jun 26 06:01:02 PM PDT 24
Peak memory 193052 kb
Host smart-c5520d6d-afb5-4156-a017-fc33ab6b361e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814784209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.814784209
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.263251590
Short name T571
Test name
Test status
Simulation time 43358998 ps
CPU time 0.59 seconds
Started Jun 26 06:01:26 PM PDT 24
Finished Jun 26 06:01:29 PM PDT 24
Peak memory 182208 kb
Host smart-7db1cc30-70f0-4691-b847-98c0f564f041
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263251590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.263251590
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1348551782
Short name T545
Test name
Test status
Simulation time 31986954 ps
CPU time 0.54 seconds
Started Jun 26 06:01:26 PM PDT 24
Finished Jun 26 06:01:29 PM PDT 24
Peak memory 181680 kb
Host smart-1bff00c1-9df0-4328-957f-8e3ca79edb64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348551782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1348551782
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2618165356
Short name T497
Test name
Test status
Simulation time 23232114 ps
CPU time 0.6 seconds
Started Jun 26 06:01:25 PM PDT 24
Finished Jun 26 06:01:27 PM PDT 24
Peak memory 182220 kb
Host smart-4b9ef41a-27a2-45da-abbd-6964fcf75d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618165356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2618165356
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.254204982
Short name T496
Test name
Test status
Simulation time 15212477 ps
CPU time 0.56 seconds
Started Jun 26 06:01:28 PM PDT 24
Finished Jun 26 06:01:31 PM PDT 24
Peak memory 182168 kb
Host smart-412a438e-393e-49f8-a6a3-a675b4a5044c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254204982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.254204982
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.208262331
Short name T485
Test name
Test status
Simulation time 35172848 ps
CPU time 0.55 seconds
Started Jun 26 06:01:24 PM PDT 24
Finished Jun 26 06:01:25 PM PDT 24
Peak memory 181708 kb
Host smart-92ba068e-15d7-4438-ab22-4de50971f467
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208262331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.208262331
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1996912451
Short name T463
Test name
Test status
Simulation time 40696768 ps
CPU time 0.6 seconds
Started Jun 26 06:01:23 PM PDT 24
Finished Jun 26 06:01:25 PM PDT 24
Peak memory 182208 kb
Host smart-c2c813d9-2d7e-4e6d-9fa3-2a3bafa9dbbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996912451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1996912451
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2764696336
Short name T472
Test name
Test status
Simulation time 32188193 ps
CPU time 0.6 seconds
Started Jun 26 06:01:25 PM PDT 24
Finished Jun 26 06:01:27 PM PDT 24
Peak memory 182164 kb
Host smart-f3de4477-130c-4782-9675-249e149b9979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764696336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2764696336
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2659075938
Short name T506
Test name
Test status
Simulation time 286437895 ps
CPU time 0.58 seconds
Started Jun 26 06:01:25 PM PDT 24
Finished Jun 26 06:01:28 PM PDT 24
Peak memory 182376 kb
Host smart-80dbfc63-908b-4575-8eda-28ab24ef9e8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659075938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2659075938
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3270733346
Short name T471
Test name
Test status
Simulation time 14611612 ps
CPU time 0.54 seconds
Started Jun 26 06:01:24 PM PDT 24
Finished Jun 26 06:01:26 PM PDT 24
Peak memory 181692 kb
Host smart-b3e5f679-fa48-4afe-9e17-8fbf4c99c4cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270733346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3270733346
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.170014758
Short name T547
Test name
Test status
Simulation time 28364470 ps
CPU time 0.6 seconds
Started Jun 26 06:01:24 PM PDT 24
Finished Jun 26 06:01:25 PM PDT 24
Peak memory 182240 kb
Host smart-0cb40cb9-7d37-4677-a870-f8827c2acfbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170014758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.170014758
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1822571835
Short name T546
Test name
Test status
Simulation time 26681922 ps
CPU time 0.73 seconds
Started Jun 26 06:00:58 PM PDT 24
Finished Jun 26 06:01:00 PM PDT 24
Peak memory 191808 kb
Host smart-b1862401-e63b-4eec-a724-60e1bfe908b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822571835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1822571835
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.103405061
Short name T527
Test name
Test status
Simulation time 176778842 ps
CPU time 3.12 seconds
Started Jun 26 06:01:01 PM PDT 24
Finished Jun 26 06:01:07 PM PDT 24
Peak memory 182472 kb
Host smart-4f978429-0521-43ce-be84-a4225ace2d5e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103405061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.103405061
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1420156278
Short name T521
Test name
Test status
Simulation time 40677897 ps
CPU time 0.55 seconds
Started Jun 26 06:01:00 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 181856 kb
Host smart-f7e9adb2-d33a-4e58-9cd9-c235e7b2034a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420156278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1420156278
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.851859659
Short name T486
Test name
Test status
Simulation time 40031005 ps
CPU time 0.7 seconds
Started Jun 26 06:01:02 PM PDT 24
Finished Jun 26 06:01:05 PM PDT 24
Peak memory 193596 kb
Host smart-ba98854d-a923-4614-92ad-64fb3e3844c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851859659 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.851859659
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3658706146
Short name T106
Test name
Test status
Simulation time 14995438 ps
CPU time 0.65 seconds
Started Jun 26 06:00:58 PM PDT 24
Finished Jun 26 06:01:01 PM PDT 24
Peak memory 182316 kb
Host smart-13ec8e32-fe28-46cc-92d1-01b361bcb1ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658706146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3658706146
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2052814469
Short name T491
Test name
Test status
Simulation time 33519105 ps
CPU time 0.56 seconds
Started Jun 26 06:00:58 PM PDT 24
Finished Jun 26 06:01:00 PM PDT 24
Peak memory 182264 kb
Host smart-31252a07-00ff-4a82-b1d5-893b23149ff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052814469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2052814469
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3636375607
Short name T551
Test name
Test status
Simulation time 118073122 ps
CPU time 0.77 seconds
Started Jun 26 06:00:58 PM PDT 24
Finished Jun 26 06:01:00 PM PDT 24
Peak memory 193024 kb
Host smart-509505bd-e1bf-4f61-844c-11854bd1f1f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636375607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3636375607
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3835475989
Short name T559
Test name
Test status
Simulation time 72762392 ps
CPU time 2.65 seconds
Started Jun 26 06:00:57 PM PDT 24
Finished Jun 26 06:01:02 PM PDT 24
Peak memory 196580 kb
Host smart-8a791cb1-13e3-4a13-8dea-1ecef98f9e46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835475989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3835475989
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1908603061
Short name T110
Test name
Test status
Simulation time 113077315 ps
CPU time 1.43 seconds
Started Jun 26 06:01:00 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 195012 kb
Host smart-17b254ae-22f4-43b1-ab7c-981b7c8ca002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908603061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1908603061
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3530427554
Short name T544
Test name
Test status
Simulation time 25682442 ps
CPU time 0.55 seconds
Started Jun 26 06:02:44 PM PDT 24
Finished Jun 26 06:02:46 PM PDT 24
Peak memory 182204 kb
Host smart-26a33482-13e0-45c0-9183-b2ba7d63e02b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530427554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3530427554
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3341418986
Short name T494
Test name
Test status
Simulation time 38853843 ps
CPU time 0.55 seconds
Started Jun 26 06:01:29 PM PDT 24
Finished Jun 26 06:01:31 PM PDT 24
Peak memory 182028 kb
Host smart-966ab520-2bef-43bf-b5d0-dfbbf481b926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341418986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3341418986
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.495469945
Short name T576
Test name
Test status
Simulation time 45581764 ps
CPU time 0.57 seconds
Started Jun 26 06:01:29 PM PDT 24
Finished Jun 26 06:01:31 PM PDT 24
Peak memory 182220 kb
Host smart-8498c1e4-27a9-4ce7-90fe-338da6a772df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495469945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.495469945
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3838018025
Short name T534
Test name
Test status
Simulation time 24603024 ps
CPU time 0.53 seconds
Started Jun 26 06:01:24 PM PDT 24
Finished Jun 26 06:01:27 PM PDT 24
Peak memory 181688 kb
Host smart-4bf32890-e9fc-4c43-9133-b03f1a70a724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838018025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3838018025
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.260024491
Short name T473
Test name
Test status
Simulation time 43872225 ps
CPU time 0.56 seconds
Started Jun 26 06:01:24 PM PDT 24
Finished Jun 26 06:01:26 PM PDT 24
Peak memory 182184 kb
Host smart-af8241ca-8a0f-44c5-9ed9-68dc7162a0f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260024491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.260024491
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.785797614
Short name T460
Test name
Test status
Simulation time 20746238 ps
CPU time 0.54 seconds
Started Jun 26 06:01:26 PM PDT 24
Finished Jun 26 06:01:30 PM PDT 24
Peak memory 181700 kb
Host smart-bcde1afb-a184-462b-97a1-2aa622d04f4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785797614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.785797614
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1802811540
Short name T457
Test name
Test status
Simulation time 47844282 ps
CPU time 0.58 seconds
Started Jun 26 06:01:27 PM PDT 24
Finished Jun 26 06:01:30 PM PDT 24
Peak memory 182208 kb
Host smart-f7868e03-9084-42f1-8993-ed95c80fd94c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802811540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1802811540
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3127879009
Short name T538
Test name
Test status
Simulation time 38107609 ps
CPU time 0.54 seconds
Started Jun 26 06:01:23 PM PDT 24
Finished Jun 26 06:01:25 PM PDT 24
Peak memory 182188 kb
Host smart-490cf4ed-97bb-4392-85c7-f10a8866848e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127879009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3127879009
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2032812973
Short name T465
Test name
Test status
Simulation time 15016977 ps
CPU time 0.59 seconds
Started Jun 26 06:01:27 PM PDT 24
Finished Jun 26 06:01:30 PM PDT 24
Peak memory 181648 kb
Host smart-ca2ff674-4d41-419e-b673-9a96924cf7ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032812973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2032812973
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3691196114
Short name T495
Test name
Test status
Simulation time 33443874 ps
CPU time 0.54 seconds
Started Jun 26 06:01:26 PM PDT 24
Finished Jun 26 06:01:29 PM PDT 24
Peak memory 181676 kb
Host smart-c6cffe3a-cd9c-4e1e-b8d0-c34fbc0d3a5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691196114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3691196114
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.60190612
Short name T87
Test name
Test status
Simulation time 32645281 ps
CPU time 0.82 seconds
Started Jun 26 06:01:01 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 192260 kb
Host smart-3fc6e2cd-aac8-4a5b-a286-3a6b2a0a1843
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60190612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasi
ng.60190612
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1497310799
Short name T90
Test name
Test status
Simulation time 80748823 ps
CPU time 2.39 seconds
Started Jun 26 06:01:00 PM PDT 24
Finished Jun 26 06:01:05 PM PDT 24
Peak memory 190692 kb
Host smart-669d09ea-470b-43d1-a4a3-1353849a0c5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497310799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1497310799
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2840726900
Short name T468
Test name
Test status
Simulation time 35336346 ps
CPU time 0.55 seconds
Started Jun 26 06:01:01 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 182312 kb
Host smart-9dae6a31-83fd-413f-8205-7786d7196816
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840726900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2840726900
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1775227939
Short name T505
Test name
Test status
Simulation time 263406281 ps
CPU time 0.73 seconds
Started Jun 26 06:01:01 PM PDT 24
Finished Jun 26 06:01:05 PM PDT 24
Peak memory 194440 kb
Host smart-80c66631-65e2-4c84-8fe5-9eebbbc028f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775227939 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1775227939
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.4047864270
Short name T524
Test name
Test status
Simulation time 17135468 ps
CPU time 0.66 seconds
Started Jun 26 06:00:59 PM PDT 24
Finished Jun 26 06:01:03 PM PDT 24
Peak memory 182268 kb
Host smart-88e4858e-fa27-430a-89d2-87e4185f479a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047864270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.4047864270
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.222866849
Short name T574
Test name
Test status
Simulation time 14720521 ps
CPU time 0.55 seconds
Started Jun 26 06:00:57 PM PDT 24
Finished Jun 26 06:01:00 PM PDT 24
Peak memory 181864 kb
Host smart-ca3e1c9c-dd69-4d68-876b-8e22b9f360fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222866849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.222866849
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.169962264
Short name T553
Test name
Test status
Simulation time 34124873 ps
CPU time 0.84 seconds
Started Jun 26 06:01:00 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 193040 kb
Host smart-b4fc6125-67aa-4748-a0c8-80d32abfc214
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169962264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.169962264
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1389622526
Short name T518
Test name
Test status
Simulation time 204608121 ps
CPU time 2.25 seconds
Started Jun 26 06:00:59 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 197100 kb
Host smart-2af52ff0-4de1-4cce-908c-e240a43772a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389622526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1389622526
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3894143993
Short name T480
Test name
Test status
Simulation time 28477208 ps
CPU time 0.54 seconds
Started Jun 26 06:01:25 PM PDT 24
Finished Jun 26 06:01:28 PM PDT 24
Peak memory 182244 kb
Host smart-0f86e3ae-6cf7-4471-a38a-8652c4aba49f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894143993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3894143993
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2806231801
Short name T469
Test name
Test status
Simulation time 50758399 ps
CPU time 0.56 seconds
Started Jun 26 06:01:25 PM PDT 24
Finished Jun 26 06:01:28 PM PDT 24
Peak memory 182220 kb
Host smart-62d9708e-92f9-4ff3-8406-724623558a2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806231801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2806231801
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2700063164
Short name T456
Test name
Test status
Simulation time 58735302 ps
CPU time 0.62 seconds
Started Jun 26 06:01:24 PM PDT 24
Finished Jun 26 06:01:26 PM PDT 24
Peak memory 182072 kb
Host smart-aa2b52e9-dd3f-4f14-9191-12faff0142f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700063164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2700063164
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.324632578
Short name T466
Test name
Test status
Simulation time 18352195 ps
CPU time 0.58 seconds
Started Jun 26 06:01:26 PM PDT 24
Finished Jun 26 06:01:29 PM PDT 24
Peak memory 182248 kb
Host smart-e2709544-bf46-40fc-b881-c4dc4e4da964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324632578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.324632578
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3570281392
Short name T493
Test name
Test status
Simulation time 37949020 ps
CPU time 0.59 seconds
Started Jun 26 06:01:19 PM PDT 24
Finished Jun 26 06:01:21 PM PDT 24
Peak memory 182184 kb
Host smart-51d93cb4-5dc5-4387-ba6c-502fe989e698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570281392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3570281392
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2978973470
Short name T561
Test name
Test status
Simulation time 12735604 ps
CPU time 0.59 seconds
Started Jun 26 06:01:23 PM PDT 24
Finished Jun 26 06:01:25 PM PDT 24
Peak memory 181920 kb
Host smart-8698192e-c7d9-4c35-a25b-d05628b3cb75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978973470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2978973470
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.505556611
Short name T536
Test name
Test status
Simulation time 54672045 ps
CPU time 0.57 seconds
Started Jun 26 06:01:27 PM PDT 24
Finished Jun 26 06:01:30 PM PDT 24
Peak memory 181672 kb
Host smart-997f11cc-bb7c-4b87-b3e1-e45bc880fe30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505556611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.505556611
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.521977231
Short name T568
Test name
Test status
Simulation time 39685197 ps
CPU time 0.53 seconds
Started Jun 26 06:01:29 PM PDT 24
Finished Jun 26 06:01:31 PM PDT 24
Peak memory 181572 kb
Host smart-f70bfa34-6efe-40e4-8f0c-9fb0af7431d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521977231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.521977231
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1166315676
Short name T550
Test name
Test status
Simulation time 63046796 ps
CPU time 0.55 seconds
Started Jun 26 06:01:25 PM PDT 24
Finished Jun 26 06:01:28 PM PDT 24
Peak memory 182196 kb
Host smart-e37ecf22-fc4f-4c31-af32-1d9247a1e9f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166315676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1166315676
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1242196620
Short name T560
Test name
Test status
Simulation time 19633721 ps
CPU time 0.55 seconds
Started Jun 26 06:01:26 PM PDT 24
Finished Jun 26 06:01:30 PM PDT 24
Peak memory 181696 kb
Host smart-186c345a-5708-453c-8a26-7380879fb869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242196620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1242196620
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2350971265
Short name T499
Test name
Test status
Simulation time 28460549 ps
CPU time 0.82 seconds
Started Jun 26 06:00:59 PM PDT 24
Finished Jun 26 06:01:02 PM PDT 24
Peak memory 195952 kb
Host smart-124a8454-e7e7-4676-832b-5f7fbc97bafb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350971265 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2350971265
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4215545201
Short name T537
Test name
Test status
Simulation time 25045259 ps
CPU time 0.55 seconds
Started Jun 26 06:01:04 PM PDT 24
Finished Jun 26 06:01:07 PM PDT 24
Peak memory 182232 kb
Host smart-1a5286fa-4343-49d5-a033-ab68c88cfc9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215545201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4215545201
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2025150066
Short name T541
Test name
Test status
Simulation time 40216874 ps
CPU time 0.57 seconds
Started Jun 26 06:01:01 PM PDT 24
Finished Jun 26 06:01:04 PM PDT 24
Peak memory 190780 kb
Host smart-7b852356-9abc-441b-9391-16d04cd59baf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025150066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2025150066
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2291161336
Short name T567
Test name
Test status
Simulation time 52660537 ps
CPU time 1.49 seconds
Started Jun 26 06:00:59 PM PDT 24
Finished Jun 26 06:01:03 PM PDT 24
Peak memory 197112 kb
Host smart-99b3c4d2-441c-4e63-8977-203c484a99f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291161336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2291161336
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1120822855
Short name T572
Test name
Test status
Simulation time 1476386854 ps
CPU time 1.25 seconds
Started Jun 26 06:00:59 PM PDT 24
Finished Jun 26 06:01:03 PM PDT 24
Peak memory 182800 kb
Host smart-a73335fd-e663-461b-b6e1-6e24c384c2a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120822855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1120822855
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3907359876
Short name T476
Test name
Test status
Simulation time 17108466 ps
CPU time 0.81 seconds
Started Jun 26 06:01:00 PM PDT 24
Finished Jun 26 06:01:03 PM PDT 24
Peak memory 195532 kb
Host smart-298fc15b-311f-48af-bb74-16e22e9be149
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907359876 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3907359876
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3466639786
Short name T533
Test name
Test status
Simulation time 34587994 ps
CPU time 0.54 seconds
Started Jun 26 06:00:59 PM PDT 24
Finished Jun 26 06:01:01 PM PDT 24
Peak memory 182272 kb
Host smart-f97a9fa0-6369-45b6-9fbc-347a2d35fe88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466639786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3466639786
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2069247260
Short name T488
Test name
Test status
Simulation time 43092684 ps
CPU time 0.58 seconds
Started Jun 26 06:01:00 PM PDT 24
Finished Jun 26 06:01:03 PM PDT 24
Peak memory 182220 kb
Host smart-b84b06c8-9fd8-4bd9-9574-d8384b6d0c68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069247260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2069247260
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1792473845
Short name T31
Test name
Test status
Simulation time 70753824 ps
CPU time 0.76 seconds
Started Jun 26 06:01:04 PM PDT 24
Finished Jun 26 06:01:07 PM PDT 24
Peak memory 192996 kb
Host smart-9da3e4ed-903b-4661-9b0c-6f9d075a34ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792473845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1792473845
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4075884830
Short name T459
Test name
Test status
Simulation time 36921271 ps
CPU time 1.81 seconds
Started Jun 26 06:01:01 PM PDT 24
Finished Jun 26 06:01:06 PM PDT 24
Peak memory 190740 kb
Host smart-0c572375-f8d3-467b-b9b3-576120c334b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075884830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4075884830
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2162001672
Short name T542
Test name
Test status
Simulation time 128511875 ps
CPU time 1.11 seconds
Started Jun 26 06:01:03 PM PDT 24
Finished Jun 26 06:01:07 PM PDT 24
Peak memory 182864 kb
Host smart-44adcf49-2ae2-44b9-ba4b-c357e74f3919
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162001672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2162001672
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2226147154
Short name T477
Test name
Test status
Simulation time 25752288 ps
CPU time 0.85 seconds
Started Jun 26 06:01:04 PM PDT 24
Finished Jun 26 06:01:07 PM PDT 24
Peak memory 194588 kb
Host smart-88ffcb34-2b64-4517-ad9c-4565b6af663c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226147154 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2226147154
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.738825899
Short name T487
Test name
Test status
Simulation time 11080383 ps
CPU time 0.57 seconds
Started Jun 26 06:01:08 PM PDT 24
Finished Jun 26 06:01:11 PM PDT 24
Peak memory 182308 kb
Host smart-6eac7c19-3ffe-496b-9aaa-e111346e369d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738825899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.738825899
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.4014976598
Short name T492
Test name
Test status
Simulation time 34827533 ps
CPU time 0.53 seconds
Started Jun 26 06:01:03 PM PDT 24
Finished Jun 26 06:01:06 PM PDT 24
Peak memory 181700 kb
Host smart-f15f2310-5806-4920-b308-e3ef015d18bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014976598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.4014976598
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1786949106
Short name T566
Test name
Test status
Simulation time 15628276 ps
CPU time 0.7 seconds
Started Jun 26 06:01:08 PM PDT 24
Finished Jun 26 06:01:11 PM PDT 24
Peak memory 191280 kb
Host smart-46bdea98-214f-426e-9aef-b78bf9aa64dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786949106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1786949106
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.523098602
Short name T474
Test name
Test status
Simulation time 1399906217 ps
CPU time 3.44 seconds
Started Jun 26 06:00:59 PM PDT 24
Finished Jun 26 06:01:05 PM PDT 24
Peak memory 197104 kb
Host smart-cb56dde6-940c-4f55-b832-84255ee99715
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523098602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.523098602
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2968666771
Short name T501
Test name
Test status
Simulation time 145163918 ps
CPU time 0.84 seconds
Started Jun 26 06:01:07 PM PDT 24
Finished Jun 26 06:01:10 PM PDT 24
Peak memory 193112 kb
Host smart-73860577-c65f-4119-a080-bd2f73146118
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968666771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2968666771
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1171880402
Short name T33
Test name
Test status
Simulation time 68320726 ps
CPU time 1.51 seconds
Started Jun 26 06:01:04 PM PDT 24
Finished Jun 26 06:01:08 PM PDT 24
Peak memory 197068 kb
Host smart-3be2cab1-14fb-43f8-8fc3-7864e016de69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171880402 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1171880402
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1701619524
Short name T503
Test name
Test status
Simulation time 11905475 ps
CPU time 0.55 seconds
Started Jun 26 06:01:07 PM PDT 24
Finished Jun 26 06:01:10 PM PDT 24
Peak memory 182240 kb
Host smart-c7dcc511-7df6-49e0-b8b7-211cd5352755
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701619524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1701619524
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.4041251168
Short name T464
Test name
Test status
Simulation time 20302758 ps
CPU time 0.57 seconds
Started Jun 26 06:01:08 PM PDT 24
Finished Jun 26 06:01:11 PM PDT 24
Peak memory 182220 kb
Host smart-adf95a78-43ed-4ef7-8915-039ee763bea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041251168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.4041251168
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.378726888
Short name T101
Test name
Test status
Simulation time 113034462 ps
CPU time 0.81 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:09 PM PDT 24
Peak memory 193100 kb
Host smart-19fe4789-b168-4f39-bc51-fa1e384fe55f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378726888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.378726888
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1227606372
Short name T51
Test name
Test status
Simulation time 361189877 ps
CPU time 1.2 seconds
Started Jun 26 06:01:07 PM PDT 24
Finished Jun 26 06:01:10 PM PDT 24
Peak memory 196980 kb
Host smart-898ac119-d4fd-47d1-8738-a2d7ed4f7142
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227606372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1227606372
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3380086228
Short name T569
Test name
Test status
Simulation time 147327944 ps
CPU time 0.9 seconds
Started Jun 26 06:01:05 PM PDT 24
Finished Jun 26 06:01:08 PM PDT 24
Peak memory 192964 kb
Host smart-1467947c-6d1c-44ef-a1e0-f52b6143543a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380086228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3380086228
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2021199395
Short name T507
Test name
Test status
Simulation time 136946925 ps
CPU time 0.96 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:08 PM PDT 24
Peak memory 196000 kb
Host smart-010d31a5-d09c-4b0a-bccb-9348870362d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021199395 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2021199395
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.124151652
Short name T99
Test name
Test status
Simulation time 30924525 ps
CPU time 0.59 seconds
Started Jun 26 06:01:07 PM PDT 24
Finished Jun 26 06:01:10 PM PDT 24
Peak memory 191540 kb
Host smart-6953b2cb-f09a-4a40-8d53-8aa3c5806837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124151652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.124151652
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1339761503
Short name T562
Test name
Test status
Simulation time 48038838 ps
CPU time 0.55 seconds
Started Jun 26 06:01:08 PM PDT 24
Finished Jun 26 06:01:11 PM PDT 24
Peak memory 182204 kb
Host smart-c1034a19-aadc-46f9-ab38-c145227f563d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339761503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1339761503
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2149391791
Short name T105
Test name
Test status
Simulation time 17619643 ps
CPU time 0.61 seconds
Started Jun 26 06:01:05 PM PDT 24
Finished Jun 26 06:01:08 PM PDT 24
Peak memory 191628 kb
Host smart-99e4c108-5f2b-4e43-8aa4-3f37ef8a45e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149391791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2149391791
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2045654468
Short name T484
Test name
Test status
Simulation time 95422592 ps
CPU time 2.49 seconds
Started Jun 26 06:01:06 PM PDT 24
Finished Jun 26 06:01:11 PM PDT 24
Peak memory 197132 kb
Host smart-3ab9c04c-1e07-4a22-9b13-baf26b4335a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045654468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2045654468
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1354045711
Short name T531
Test name
Test status
Simulation time 326890925 ps
CPU time 0.86 seconds
Started Jun 26 06:01:04 PM PDT 24
Finished Jun 26 06:01:07 PM PDT 24
Peak memory 182636 kb
Host smart-cca74a80-2ae5-4b1f-b575-efc9e9e1a758
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354045711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1354045711
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3539256190
Short name T190
Test name
Test status
Simulation time 1536758133617 ps
CPU time 519.48 seconds
Started Jun 26 06:01:26 PM PDT 24
Finished Jun 26 06:10:08 PM PDT 24
Peak memory 183156 kb
Host smart-8655da4a-2ffe-4139-810d-a830e3ea543e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539256190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3539256190
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3577558677
Short name T80
Test name
Test status
Simulation time 104591793544 ps
CPU time 153.62 seconds
Started Jun 26 06:03:18 PM PDT 24
Finished Jun 26 06:05:54 PM PDT 24
Peak memory 183172 kb
Host smart-fa597edb-29b2-4cdb-bdbf-da3c107ee220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577558677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3577558677
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.4104631192
Short name T171
Test name
Test status
Simulation time 31327207334 ps
CPU time 38.91 seconds
Started Jun 26 06:01:27 PM PDT 24
Finished Jun 26 06:02:08 PM PDT 24
Peak memory 183136 kb
Host smart-c8a73726-7b4d-40ce-9dcd-514b195a6cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104631192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4104631192
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.926180277
Short name T18
Test name
Test status
Simulation time 217649329 ps
CPU time 0.82 seconds
Started Jun 26 06:01:26 PM PDT 24
Finished Jun 26 06:01:29 PM PDT 24
Peak memory 213424 kb
Host smart-b57767a9-615d-42b6-832c-33e5a2983840
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926180277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.926180277
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2849389981
Short name T212
Test name
Test status
Simulation time 454250475758 ps
CPU time 262.18 seconds
Started Jun 26 06:01:29 PM PDT 24
Finished Jun 26 06:05:53 PM PDT 24
Peak memory 183140 kb
Host smart-2d9f2191-b86a-4b73-9c07-c77c8412332d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849389981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2849389981
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.4281903340
Short name T375
Test name
Test status
Simulation time 35349117003 ps
CPU time 53.46 seconds
Started Jun 26 06:01:25 PM PDT 24
Finished Jun 26 06:02:21 PM PDT 24
Peak memory 183144 kb
Host smart-36730c7b-765c-4932-991b-3c8eadb67bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281903340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.4281903340
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3744418418
Short name T316
Test name
Test status
Simulation time 45407849738 ps
CPU time 79.24 seconds
Started Jun 26 06:01:26 PM PDT 24
Finished Jun 26 06:02:48 PM PDT 24
Peak memory 191340 kb
Host smart-2e85eb07-0f21-42c3-9c00-127653448062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744418418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3744418418
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1846519364
Short name T424
Test name
Test status
Simulation time 82542844974 ps
CPU time 130.9 seconds
Started Jun 26 06:01:29 PM PDT 24
Finished Jun 26 06:03:42 PM PDT 24
Peak memory 183156 kb
Host smart-920f383f-f52c-4b2f-8987-879ec4b26801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846519364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1846519364
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.413615251
Short name T260
Test name
Test status
Simulation time 175833045790 ps
CPU time 303.25 seconds
Started Jun 26 06:01:42 PM PDT 24
Finished Jun 26 06:06:47 PM PDT 24
Peak memory 183112 kb
Host smart-a8083d56-d5dd-4be2-ad38-500b908dc50e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413615251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.413615251
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.983133137
Short name T390
Test name
Test status
Simulation time 647116627722 ps
CPU time 141.95 seconds
Started Jun 26 06:01:37 PM PDT 24
Finished Jun 26 06:04:00 PM PDT 24
Peak memory 183172 kb
Host smart-03438bea-5eff-42e2-9f7f-276e92f80b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983133137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.983133137
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1662250414
Short name T320
Test name
Test status
Simulation time 87291890003 ps
CPU time 350.08 seconds
Started Jun 26 06:01:42 PM PDT 24
Finished Jun 26 06:07:34 PM PDT 24
Peak memory 191368 kb
Host smart-158d8187-a2b3-4358-a556-f46045fbd784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662250414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1662250414
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.219429671
Short name T181
Test name
Test status
Simulation time 56420435293 ps
CPU time 84.93 seconds
Started Jun 26 06:02:40 PM PDT 24
Finished Jun 26 06:04:07 PM PDT 24
Peak memory 191940 kb
Host smart-23a60401-0f20-40b2-b571-a2bcc6fa7fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219429671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.219429671
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2945675618
Short name T267
Test name
Test status
Simulation time 306957881541 ps
CPU time 372.78 seconds
Started Jun 26 06:02:38 PM PDT 24
Finished Jun 26 06:08:52 PM PDT 24
Peak memory 191368 kb
Host smart-bfb0a685-2fbb-4609-9e5d-cd973eb4fa89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945675618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2945675618
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.258085473
Short name T365
Test name
Test status
Simulation time 28188174102 ps
CPU time 42.93 seconds
Started Jun 26 06:02:40 PM PDT 24
Finished Jun 26 06:03:24 PM PDT 24
Peak memory 183124 kb
Host smart-1f099121-9858-44c2-b0ec-62a8d0e07aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258085473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.258085473
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1812442710
Short name T225
Test name
Test status
Simulation time 575396709864 ps
CPU time 471.05 seconds
Started Jun 26 06:02:40 PM PDT 24
Finished Jun 26 06:10:33 PM PDT 24
Peak memory 191532 kb
Host smart-7686bac3-0f03-41e7-9531-27fc03a75989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812442710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1812442710
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2631316189
Short name T195
Test name
Test status
Simulation time 169444987833 ps
CPU time 133.64 seconds
Started Jun 26 06:02:43 PM PDT 24
Finished Jun 26 06:04:59 PM PDT 24
Peak memory 191352 kb
Host smart-662cf40b-4692-40d4-92d3-a9ee7d5b8a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631316189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2631316189
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1993000662
Short name T165
Test name
Test status
Simulation time 78275793210 ps
CPU time 66.92 seconds
Started Jun 26 06:02:42 PM PDT 24
Finished Jun 26 06:03:50 PM PDT 24
Peak memory 183084 kb
Host smart-121490dd-3f2f-4f91-b8fd-3807922f153f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993000662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1993000662
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2642294431
Short name T139
Test name
Test status
Simulation time 5953451903 ps
CPU time 2.43 seconds
Started Jun 26 06:01:40 PM PDT 24
Finished Jun 26 06:01:44 PM PDT 24
Peak memory 183148 kb
Host smart-c8ea37f3-af57-47fe-8b9f-51b76a64b8e8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642294431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2642294431
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.620843265
Short name T441
Test name
Test status
Simulation time 179528535619 ps
CPU time 74.86 seconds
Started Jun 26 06:01:39 PM PDT 24
Finished Jun 26 06:02:55 PM PDT 24
Peak memory 183156 kb
Host smart-efba51ad-1112-4a2a-b650-1a320ae6125e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620843265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.620843265
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.596150386
Short name T402
Test name
Test status
Simulation time 16758839035 ps
CPU time 155.59 seconds
Started Jun 26 06:01:41 PM PDT 24
Finished Jun 26 06:04:18 PM PDT 24
Peak memory 183124 kb
Host smart-83881da7-be5b-462d-8764-3b832eee4b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596150386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.596150386
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1546858623
Short name T186
Test name
Test status
Simulation time 425315762613 ps
CPU time 177.55 seconds
Started Jun 26 06:01:39 PM PDT 24
Finished Jun 26 06:04:38 PM PDT 24
Peak memory 191356 kb
Host smart-cc802eba-a4a4-4f37-9275-cfa24ffc9220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546858623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1546858623
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1506680286
Short name T347
Test name
Test status
Simulation time 469205978999 ps
CPU time 226.99 seconds
Started Jun 26 06:02:46 PM PDT 24
Finished Jun 26 06:06:35 PM PDT 24
Peak memory 191364 kb
Host smart-a626d525-793a-4467-ab3d-61513ff0e8c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506680286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1506680286
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.261412058
Short name T359
Test name
Test status
Simulation time 108679603073 ps
CPU time 676 seconds
Started Jun 26 06:02:44 PM PDT 24
Finished Jun 26 06:14:03 PM PDT 24
Peak memory 191328 kb
Host smart-210d1cd8-b07c-469a-8a6a-97b262eccaec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261412058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.261412058
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1858226110
Short name T319
Test name
Test status
Simulation time 599259397250 ps
CPU time 266.39 seconds
Started Jun 26 06:02:48 PM PDT 24
Finished Jun 26 06:07:16 PM PDT 24
Peak memory 191328 kb
Host smart-a47aa8cf-753a-48f9-b86d-3dd50080617c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858226110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1858226110
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1120562798
Short name T305
Test name
Test status
Simulation time 230581012163 ps
CPU time 90.99 seconds
Started Jun 26 06:02:48 PM PDT 24
Finished Jun 26 06:04:21 PM PDT 24
Peak memory 191372 kb
Host smart-e28f488e-7ced-4c25-8a84-f77f37792669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120562798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1120562798
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1096887972
Short name T196
Test name
Test status
Simulation time 1037658450421 ps
CPU time 1118.71 seconds
Started Jun 26 06:02:49 PM PDT 24
Finished Jun 26 06:21:29 PM PDT 24
Peak memory 191352 kb
Host smart-65ac8c39-0f09-4274-b7c3-996b14548d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096887972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1096887972
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2725951375
Short name T138
Test name
Test status
Simulation time 435579531729 ps
CPU time 442.21 seconds
Started Jun 26 06:02:47 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 191280 kb
Host smart-2777bff9-18de-45fd-a77d-0f3561931d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725951375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2725951375
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1355925002
Short name T9
Test name
Test status
Simulation time 111751670529 ps
CPU time 75.32 seconds
Started Jun 26 06:01:39 PM PDT 24
Finished Jun 26 06:02:56 PM PDT 24
Peak memory 183100 kb
Host smart-a957f288-2c27-417b-a185-24933e6c24a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355925002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1355925002
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.4216266104
Short name T239
Test name
Test status
Simulation time 293444397662 ps
CPU time 601.02 seconds
Started Jun 26 06:01:41 PM PDT 24
Finished Jun 26 06:11:43 PM PDT 24
Peak memory 191328 kb
Host smart-84c9240a-8269-4e16-b6eb-3b0457e63032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216266104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4216266104
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1696825965
Short name T56
Test name
Test status
Simulation time 8603121627 ps
CPU time 4.8 seconds
Started Jun 26 06:01:40 PM PDT 24
Finished Jun 26 06:01:46 PM PDT 24
Peak memory 183132 kb
Host smart-1c9d3018-f92e-471c-a11b-3cc2084f033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696825965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1696825965
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.549197653
Short name T261
Test name
Test status
Simulation time 83535783320 ps
CPU time 371.58 seconds
Started Jun 26 06:02:48 PM PDT 24
Finished Jun 26 06:09:02 PM PDT 24
Peak memory 191332 kb
Host smart-c9027593-2cec-409e-af10-e2456e32108a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549197653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.549197653
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2319957955
Short name T435
Test name
Test status
Simulation time 58993427443 ps
CPU time 31.94 seconds
Started Jun 26 06:02:46 PM PDT 24
Finished Jun 26 06:03:19 PM PDT 24
Peak memory 183124 kb
Host smart-841d8bcb-c91b-44de-84d0-f72c34407ad3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319957955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2319957955
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2022271080
Short name T177
Test name
Test status
Simulation time 396916920782 ps
CPU time 785.4 seconds
Started Jun 26 06:02:45 PM PDT 24
Finished Jun 26 06:15:53 PM PDT 24
Peak memory 191340 kb
Host smart-e10e46b8-da68-43aa-9339-811fe89e0a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022271080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2022271080
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3439489455
Short name T204
Test name
Test status
Simulation time 122324185535 ps
CPU time 193.35 seconds
Started Jun 26 06:02:56 PM PDT 24
Finished Jun 26 06:06:11 PM PDT 24
Peak memory 191356 kb
Host smart-3bd79939-2c1f-4dd4-b6fb-4bba038dfc87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439489455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3439489455
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.4222262830
Short name T446
Test name
Test status
Simulation time 42310660552 ps
CPU time 62.54 seconds
Started Jun 26 06:02:54 PM PDT 24
Finished Jun 26 06:03:58 PM PDT 24
Peak memory 194868 kb
Host smart-e2a2aea7-f63a-44d0-8c1d-9f783a34da26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222262830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.4222262830
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2720853464
Short name T251
Test name
Test status
Simulation time 255082196218 ps
CPU time 536.79 seconds
Started Jun 26 06:02:56 PM PDT 24
Finished Jun 26 06:11:54 PM PDT 24
Peak memory 194252 kb
Host smart-920e319a-b07f-4b7e-91a9-ad02adab0a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720853464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2720853464
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.619378077
Short name T179
Test name
Test status
Simulation time 32105302004 ps
CPU time 59.88 seconds
Started Jun 26 06:02:56 PM PDT 24
Finished Jun 26 06:03:57 PM PDT 24
Peak memory 183148 kb
Host smart-dc79fbe6-09eb-464b-96db-abc524315886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619378077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.619378077
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3420307468
Short name T286
Test name
Test status
Simulation time 528868244605 ps
CPU time 407.89 seconds
Started Jun 26 06:01:42 PM PDT 24
Finished Jun 26 06:08:31 PM PDT 24
Peak memory 183152 kb
Host smart-a0d4ac82-33ea-4621-9be0-4c44947e7d95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420307468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3420307468
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3730520924
Short name T374
Test name
Test status
Simulation time 33154883462 ps
CPU time 48.99 seconds
Started Jun 26 06:01:38 PM PDT 24
Finished Jun 26 06:02:28 PM PDT 24
Peak memory 183180 kb
Host smart-6c635fa0-cab1-4c96-b74d-4aa4ffdbf1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730520924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3730520924
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2773089877
Short name T361
Test name
Test status
Simulation time 3034827012753 ps
CPU time 512.78 seconds
Started Jun 26 06:01:37 PM PDT 24
Finished Jun 26 06:10:11 PM PDT 24
Peak memory 191288 kb
Host smart-a5390bdb-69d5-4405-9890-de4e0918ef59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773089877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2773089877
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3823120685
Short name T421
Test name
Test status
Simulation time 424024338311 ps
CPU time 314.76 seconds
Started Jun 26 06:01:41 PM PDT 24
Finished Jun 26 06:06:58 PM PDT 24
Peak memory 183120 kb
Host smart-5e7b8a05-9cdf-4480-bbc1-f48eb8ddca02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823120685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3823120685
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.3021536675
Short name T327
Test name
Test status
Simulation time 33109995704 ps
CPU time 64.03 seconds
Started Jun 26 06:02:56 PM PDT 24
Finished Jun 26 06:04:01 PM PDT 24
Peak memory 191372 kb
Host smart-9c52b91b-144f-494f-b4be-8ab665ed9d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021536675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3021536675
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1573971270
Short name T301
Test name
Test status
Simulation time 74543970106 ps
CPU time 111.64 seconds
Started Jun 26 06:02:58 PM PDT 24
Finished Jun 26 06:04:51 PM PDT 24
Peak memory 191356 kb
Host smart-6669ab0a-9409-4638-82b1-7b04e38aafd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573971270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1573971270
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3280568465
Short name T142
Test name
Test status
Simulation time 331069030223 ps
CPU time 341.41 seconds
Started Jun 26 06:02:57 PM PDT 24
Finished Jun 26 06:08:40 PM PDT 24
Peak memory 191360 kb
Host smart-090b2658-f04c-4502-96b7-566219e4f29f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280568465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3280568465
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1761672545
Short name T276
Test name
Test status
Simulation time 431685618108 ps
CPU time 300.79 seconds
Started Jun 26 06:05:41 PM PDT 24
Finished Jun 26 06:10:43 PM PDT 24
Peak memory 191364 kb
Host smart-02202150-de9d-409c-ab12-a31e05e2492d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761672545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1761672545
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.718391268
Short name T167
Test name
Test status
Simulation time 130174552561 ps
CPU time 232.05 seconds
Started Jun 26 06:03:06 PM PDT 24
Finished Jun 26 06:06:59 PM PDT 24
Peak memory 191272 kb
Host smart-1896c114-672e-436c-9510-f2313c32ec53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718391268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.718391268
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3857539105
Short name T60
Test name
Test status
Simulation time 137463906070 ps
CPU time 291.58 seconds
Started Jun 26 06:02:56 PM PDT 24
Finished Jun 26 06:07:49 PM PDT 24
Peak memory 183088 kb
Host smart-f1cb1797-efa4-4a04-abba-e015afc7045c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857539105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3857539105
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2995832135
Short name T423
Test name
Test status
Simulation time 463899690143 ps
CPU time 272.28 seconds
Started Jun 26 06:03:03 PM PDT 24
Finished Jun 26 06:07:35 PM PDT 24
Peak memory 191376 kb
Host smart-17a681e1-edb2-4198-8b54-255b4327768c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995832135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2995832135
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1297168873
Short name T85
Test name
Test status
Simulation time 463488359881 ps
CPU time 260.25 seconds
Started Jun 26 06:03:05 PM PDT 24
Finished Jun 26 06:07:26 PM PDT 24
Peak memory 191356 kb
Host smart-8abd55e4-74a8-479e-a627-2bcde8ca0965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297168873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1297168873
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3436258918
Short name T334
Test name
Test status
Simulation time 50221542831 ps
CPU time 85.83 seconds
Started Jun 26 06:03:02 PM PDT 24
Finished Jun 26 06:04:28 PM PDT 24
Peak memory 183148 kb
Host smart-8a7cdfc1-34e5-4343-afb7-24b2f27f5194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436258918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3436258918
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2745996194
Short name T397
Test name
Test status
Simulation time 447415800029 ps
CPU time 97.59 seconds
Started Jun 26 06:01:41 PM PDT 24
Finished Jun 26 06:03:20 PM PDT 24
Peak memory 183148 kb
Host smart-dbc64089-f796-449a-b0ac-d216f9dcb45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745996194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2745996194
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.586228548
Short name T369
Test name
Test status
Simulation time 32585684246 ps
CPU time 50.54 seconds
Started Jun 26 06:01:39 PM PDT 24
Finished Jun 26 06:02:31 PM PDT 24
Peak memory 191276 kb
Host smart-57780e22-43ad-4e57-a6f1-0f7b7c82c9d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586228548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.586228548
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2493236321
Short name T317
Test name
Test status
Simulation time 27924339732 ps
CPU time 315.63 seconds
Started Jun 26 06:01:41 PM PDT 24
Finished Jun 26 06:06:58 PM PDT 24
Peak memory 191388 kb
Host smart-76560d7b-dc2b-4ba1-99d2-08ca77278eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493236321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2493236321
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.562315887
Short name T209
Test name
Test status
Simulation time 222997683643 ps
CPU time 508.36 seconds
Started Jun 26 06:03:04 PM PDT 24
Finished Jun 26 06:11:34 PM PDT 24
Peak memory 191332 kb
Host smart-5950cdfb-d4a1-44a7-9941-a808a5bd3ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562315887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.562315887
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4270410242
Short name T119
Test name
Test status
Simulation time 146232968277 ps
CPU time 835.64 seconds
Started Jun 26 06:03:01 PM PDT 24
Finished Jun 26 06:16:57 PM PDT 24
Peak memory 183152 kb
Host smart-26ed6c64-a3fb-4f1e-b7dc-eb5b57d9eca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270410242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4270410242
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3634613763
Short name T46
Test name
Test status
Simulation time 350917033324 ps
CPU time 146.16 seconds
Started Jun 26 06:03:02 PM PDT 24
Finished Jun 26 06:05:29 PM PDT 24
Peak memory 191364 kb
Host smart-583ffae7-9542-4169-b632-c1b41c396942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634613763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3634613763
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3194994838
Short name T118
Test name
Test status
Simulation time 23296389824 ps
CPU time 32.97 seconds
Started Jun 26 06:03:03 PM PDT 24
Finished Jun 26 06:03:37 PM PDT 24
Peak memory 191324 kb
Host smart-1bacd298-2b6b-4001-a3ca-a2c0bef9127a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194994838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3194994838
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3416984773
Short name T412
Test name
Test status
Simulation time 247118225965 ps
CPU time 168.01 seconds
Started Jun 26 06:01:38 PM PDT 24
Finished Jun 26 06:04:28 PM PDT 24
Peak memory 183148 kb
Host smart-d1e1300b-91a8-4c3f-bf8d-c051d6383799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416984773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3416984773
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1122372881
Short name T131
Test name
Test status
Simulation time 50591802182 ps
CPU time 1556.65 seconds
Started Jun 26 06:01:38 PM PDT 24
Finished Jun 26 06:27:37 PM PDT 24
Peak memory 183164 kb
Host smart-f222acbe-5ba7-41f6-8b43-b35da440322d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122372881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1122372881
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.1452531110
Short name T35
Test name
Test status
Simulation time 63305180547 ps
CPU time 684.12 seconds
Started Jun 26 06:01:41 PM PDT 24
Finished Jun 26 06:13:06 PM PDT 24
Peak memory 206068 kb
Host smart-193a56e5-fd83-4ae6-9745-ffbb0fd62e70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452531110 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.1452531110
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.258549331
Short name T250
Test name
Test status
Simulation time 196504910375 ps
CPU time 86.27 seconds
Started Jun 26 06:03:10 PM PDT 24
Finished Jun 26 06:04:37 PM PDT 24
Peak memory 191360 kb
Host smart-b42e71b2-a1ee-4719-b239-5c7baf048016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258549331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.258549331
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3041617507
Short name T231
Test name
Test status
Simulation time 188492241325 ps
CPU time 776.07 seconds
Started Jun 26 06:03:10 PM PDT 24
Finished Jun 26 06:16:06 PM PDT 24
Peak memory 191260 kb
Host smart-6f61811d-19d3-4e0a-acfe-0538d5ce4401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041617507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3041617507
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.4048461978
Short name T144
Test name
Test status
Simulation time 95036190901 ps
CPU time 969.14 seconds
Started Jun 26 06:03:08 PM PDT 24
Finished Jun 26 06:19:18 PM PDT 24
Peak memory 191352 kb
Host smart-518a28e8-b8ff-48c5-994a-b3eb70cd157d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048461978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.4048461978
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.117174374
Short name T155
Test name
Test status
Simulation time 131473968227 ps
CPU time 1434.43 seconds
Started Jun 26 06:03:07 PM PDT 24
Finished Jun 26 06:27:02 PM PDT 24
Peak memory 191320 kb
Host smart-c33415cb-ab5f-4f6d-a2a8-f1074648fbd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117174374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.117174374
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3767871839
Short name T78
Test name
Test status
Simulation time 340803747374 ps
CPU time 270.01 seconds
Started Jun 26 06:03:10 PM PDT 24
Finished Jun 26 06:07:41 PM PDT 24
Peak memory 191332 kb
Host smart-dca88ecc-a09c-411e-9aa1-6e2bf2dbeede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767871839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3767871839
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.120506621
Short name T117
Test name
Test status
Simulation time 180495380004 ps
CPU time 418.94 seconds
Started Jun 26 06:03:10 PM PDT 24
Finished Jun 26 06:10:09 PM PDT 24
Peak memory 191360 kb
Host smart-57818b9e-544a-4eaa-9143-fef36b593844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120506621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.120506621
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2134562877
Short name T304
Test name
Test status
Simulation time 180250346807 ps
CPU time 332.76 seconds
Started Jun 26 06:03:09 PM PDT 24
Finished Jun 26 06:08:42 PM PDT 24
Peak memory 191308 kb
Host smart-acb0bc45-df19-448f-8785-e938c6fde1ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134562877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2134562877
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2836246073
Short name T313
Test name
Test status
Simulation time 361685059711 ps
CPU time 179.1 seconds
Started Jun 26 06:03:23 PM PDT 24
Finished Jun 26 06:06:23 PM PDT 24
Peak memory 191176 kb
Host smart-7ef60662-7c88-4b65-8f5f-8425d291498e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836246073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2836246073
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1263015684
Short name T230
Test name
Test status
Simulation time 10138598719 ps
CPU time 5.33 seconds
Started Jun 26 06:01:49 PM PDT 24
Finished Jun 26 06:01:56 PM PDT 24
Peak memory 183128 kb
Host smart-0ad91b9f-2cd1-4d84-9aad-249d39f73c18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263015684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1263015684
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3412948681
Short name T413
Test name
Test status
Simulation time 775121656190 ps
CPU time 296.49 seconds
Started Jun 26 06:01:46 PM PDT 24
Finished Jun 26 06:06:44 PM PDT 24
Peak memory 183340 kb
Host smart-e9595492-86e0-4e3a-a545-3fa64e4ef334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412948681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3412948681
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2103615162
Short name T197
Test name
Test status
Simulation time 321372677447 ps
CPU time 195.42 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:05:05 PM PDT 24
Peak memory 191368 kb
Host smart-99919668-a183-4f0f-b889-8247edb19652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103615162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2103615162
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2589174262
Short name T277
Test name
Test status
Simulation time 378869128269 ps
CPU time 1257.52 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:22:47 PM PDT 24
Peak memory 195960 kb
Host smart-76fe0020-227d-4d95-b488-a4fc6cc8e2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589174262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2589174262
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/162.rv_timer_random.993784860
Short name T290
Test name
Test status
Simulation time 48382046205 ps
CPU time 75.97 seconds
Started Jun 26 06:03:16 PM PDT 24
Finished Jun 26 06:04:33 PM PDT 24
Peak memory 183160 kb
Host smart-07578536-71cc-4c04-97ba-04bcea71092e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993784860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.993784860
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2812966637
Short name T82
Test name
Test status
Simulation time 40699539848 ps
CPU time 58.17 seconds
Started Jun 26 06:03:16 PM PDT 24
Finished Jun 26 06:04:15 PM PDT 24
Peak memory 183156 kb
Host smart-e4d9d736-44e6-4910-8e00-49eabad36dc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812966637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2812966637
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3123586947
Short name T3
Test name
Test status
Simulation time 190173201160 ps
CPU time 106.42 seconds
Started Jun 26 06:03:25 PM PDT 24
Finished Jun 26 06:05:12 PM PDT 24
Peak memory 183088 kb
Host smart-3992e40c-dbef-444f-b3af-b1dff2af6895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123586947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3123586947
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2325379542
Short name T289
Test name
Test status
Simulation time 89751963842 ps
CPU time 76.21 seconds
Started Jun 26 06:03:24 PM PDT 24
Finished Jun 26 06:04:41 PM PDT 24
Peak memory 191320 kb
Host smart-5def6128-b53a-48b9-bc2e-7ffcafb0b021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325379542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2325379542
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.4047782896
Short name T173
Test name
Test status
Simulation time 110890043106 ps
CPU time 171.55 seconds
Started Jun 26 06:03:24 PM PDT 24
Finished Jun 26 06:06:17 PM PDT 24
Peak memory 191360 kb
Host smart-0c2ea8f2-a017-4feb-aa1f-7cdc2e1df8aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047782896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.4047782896
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.3925332999
Short name T45
Test name
Test status
Simulation time 26350819928 ps
CPU time 937.15 seconds
Started Jun 26 06:03:26 PM PDT 24
Finished Jun 26 06:19:04 PM PDT 24
Peak memory 183152 kb
Host smart-530d7cd5-8d1d-464a-bbd3-5d34698abcd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925332999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.3925332999
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.4077176880
Short name T363
Test name
Test status
Simulation time 5334182611 ps
CPU time 8.55 seconds
Started Jun 26 06:01:45 PM PDT 24
Finished Jun 26 06:01:54 PM PDT 24
Peak memory 183152 kb
Host smart-b0cbc559-024b-4fb9-ba47-cd3a5184aaff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077176880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.4077176880
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2712502773
Short name T410
Test name
Test status
Simulation time 766499103098 ps
CPU time 115.29 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:03:44 PM PDT 24
Peak memory 183080 kb
Host smart-5fa1721f-aa4c-46ad-8b28-f0eb8eb06b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712502773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2712502773
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3572970799
Short name T452
Test name
Test status
Simulation time 43187963265 ps
CPU time 60.4 seconds
Started Jun 26 06:01:51 PM PDT 24
Finished Jun 26 06:02:53 PM PDT 24
Peak memory 183380 kb
Host smart-cc0d9f9f-1868-40c9-a732-30fb809746a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572970799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3572970799
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2830593362
Short name T176
Test name
Test status
Simulation time 13891305745 ps
CPU time 41.05 seconds
Started Jun 26 06:03:29 PM PDT 24
Finished Jun 26 06:04:11 PM PDT 24
Peak memory 182976 kb
Host smart-6d2d327a-e5e1-4dc0-a7ff-8762ec7662a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830593362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2830593362
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.220974414
Short name T329
Test name
Test status
Simulation time 43675760991 ps
CPU time 69.38 seconds
Started Jun 26 06:03:24 PM PDT 24
Finished Jun 26 06:04:34 PM PDT 24
Peak memory 183172 kb
Host smart-4ec5ab46-7b6e-47f7-a92e-0236c66c8a0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220974414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.220974414
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3858532134
Short name T311
Test name
Test status
Simulation time 266586319865 ps
CPU time 376.16 seconds
Started Jun 26 06:04:07 PM PDT 24
Finished Jun 26 06:10:24 PM PDT 24
Peak memory 191268 kb
Host smart-4c8af78e-845e-4aa2-b103-9c5a99bc5eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858532134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3858532134
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.981271502
Short name T26
Test name
Test status
Simulation time 432439173431 ps
CPU time 208.17 seconds
Started Jun 26 06:03:23 PM PDT 24
Finished Jun 26 06:06:52 PM PDT 24
Peak memory 191352 kb
Host smart-5ee38c41-733d-4526-8393-f1af6fbca878
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981271502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.981271502
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2836028282
Short name T136
Test name
Test status
Simulation time 71727749719 ps
CPU time 212.54 seconds
Started Jun 26 06:03:23 PM PDT 24
Finished Jun 26 06:06:57 PM PDT 24
Peak memory 183172 kb
Host smart-dc26c407-3656-4f76-98d3-54932b7fc533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836028282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2836028282
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2695906622
Short name T306
Test name
Test status
Simulation time 246637892875 ps
CPU time 144.4 seconds
Started Jun 26 06:03:30 PM PDT 24
Finished Jun 26 06:05:55 PM PDT 24
Peak memory 191236 kb
Host smart-14ae889f-0d8c-4dbd-af35-d3872638f22a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695906622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2695906622
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.540859671
Short name T12
Test name
Test status
Simulation time 147470517328 ps
CPU time 268.3 seconds
Started Jun 26 06:03:33 PM PDT 24
Finished Jun 26 06:08:02 PM PDT 24
Peak memory 191172 kb
Host smart-62031d81-b87a-4a1d-a014-6dd9415f62a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540859671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.540859671
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2192308617
Short name T189
Test name
Test status
Simulation time 456556752104 ps
CPU time 437.27 seconds
Started Jun 26 06:03:31 PM PDT 24
Finished Jun 26 06:10:49 PM PDT 24
Peak memory 191356 kb
Host smart-816e8c3a-73e4-48e7-af8c-d765d24fa0d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192308617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2192308617
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1894147240
Short name T115
Test name
Test status
Simulation time 1389169319966 ps
CPU time 1179.92 seconds
Started Jun 26 06:01:48 PM PDT 24
Finished Jun 26 06:21:31 PM PDT 24
Peak memory 183124 kb
Host smart-fa526ff1-13d9-4522-b7a4-824c62a25ae8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894147240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1894147240
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3705210960
Short name T378
Test name
Test status
Simulation time 161580921852 ps
CPU time 68.03 seconds
Started Jun 26 06:01:46 PM PDT 24
Finished Jun 26 06:02:56 PM PDT 24
Peak memory 183168 kb
Host smart-86980481-3a25-4168-a584-b579d02c4b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705210960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3705210960
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1276442551
Short name T430
Test name
Test status
Simulation time 296489528540 ps
CPU time 264.77 seconds
Started Jun 26 06:01:48 PM PDT 24
Finished Jun 26 06:06:15 PM PDT 24
Peak memory 183172 kb
Host smart-2fadd142-0de6-44f0-bede-b19120ce425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276442551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1276442551
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1893672569
Short name T408
Test name
Test status
Simulation time 344690528016 ps
CPU time 148.19 seconds
Started Jun 26 06:01:52 PM PDT 24
Finished Jun 26 06:04:21 PM PDT 24
Peak memory 194568 kb
Host smart-8170b35d-9476-4af7-a7d3-57b1fe04883d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893672569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1893672569
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.1607303476
Short name T39
Test name
Test status
Simulation time 16811625061 ps
CPU time 117.17 seconds
Started Jun 26 06:01:45 PM PDT 24
Finished Jun 26 06:03:43 PM PDT 24
Peak memory 197796 kb
Host smart-e93e6b63-abd9-4647-bd9e-2727d140f09e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607303476 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.1607303476
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.2248809009
Short name T205
Test name
Test status
Simulation time 388039509451 ps
CPU time 447.29 seconds
Started Jun 26 06:03:31 PM PDT 24
Finished Jun 26 06:11:00 PM PDT 24
Peak memory 191356 kb
Host smart-bb5913fe-1a13-42fb-a0d0-9cefe1a3de36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248809009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2248809009
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.9337891
Short name T343
Test name
Test status
Simulation time 996291761380 ps
CPU time 1307.5 seconds
Started Jun 26 06:03:31 PM PDT 24
Finished Jun 26 06:25:19 PM PDT 24
Peak memory 191284 kb
Host smart-353dc7be-9ce1-4fbb-8253-8bcb4d8d6c93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9337891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.9337891
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1552339033
Short name T275
Test name
Test status
Simulation time 90139272055 ps
CPU time 115.82 seconds
Started Jun 26 06:03:33 PM PDT 24
Finished Jun 26 06:05:30 PM PDT 24
Peak memory 183368 kb
Host smart-073c1f8b-b8a8-4296-a069-f9472a61dabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552339033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1552339033
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1354930129
Short name T125
Test name
Test status
Simulation time 212558262362 ps
CPU time 1656.92 seconds
Started Jun 26 06:03:31 PM PDT 24
Finished Jun 26 06:31:09 PM PDT 24
Peak memory 191372 kb
Host smart-2b1cf49b-3d13-4ae4-a719-f43f9efecf74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354930129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1354930129
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.40393387
Short name T221
Test name
Test status
Simulation time 688033768740 ps
CPU time 676.87 seconds
Started Jun 26 06:03:32 PM PDT 24
Finished Jun 26 06:14:50 PM PDT 24
Peak memory 191292 kb
Host smart-92350432-efab-430b-ab61-21ef3c002d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40393387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.40393387
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3970394641
Short name T322
Test name
Test status
Simulation time 7686050372 ps
CPU time 11.19 seconds
Started Jun 26 06:03:31 PM PDT 24
Finished Jun 26 06:03:43 PM PDT 24
Peak memory 183168 kb
Host smart-5bb4bfe4-f673-4df8-8033-18daabd23da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970394641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3970394641
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2378638972
Short name T308
Test name
Test status
Simulation time 741124929537 ps
CPU time 1317.96 seconds
Started Jun 26 06:03:41 PM PDT 24
Finished Jun 26 06:25:39 PM PDT 24
Peak memory 191360 kb
Host smart-dd79b13a-e297-4f3f-beba-20e7a5bdaa00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378638972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2378638972
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2963488175
Short name T135
Test name
Test status
Simulation time 162770420124 ps
CPU time 290.88 seconds
Started Jun 26 06:01:46 PM PDT 24
Finished Jun 26 06:06:38 PM PDT 24
Peak memory 182988 kb
Host smart-5e44c170-4492-4fe3-aee3-6b9637f2c1de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963488175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2963488175
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.327397749
Short name T10
Test name
Test status
Simulation time 105930562489 ps
CPU time 150.25 seconds
Started Jun 26 06:01:49 PM PDT 24
Finished Jun 26 06:04:22 PM PDT 24
Peak memory 183148 kb
Host smart-6a48820c-3875-4ecb-8d18-b4ee355efb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327397749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.327397749
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.156140245
Short name T253
Test name
Test status
Simulation time 122607961691 ps
CPU time 330.3 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:07:19 PM PDT 24
Peak memory 191356 kb
Host smart-9bd68bfe-a00b-4acd-bd5c-06a8fcb29870
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156140245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.156140245
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2746548879
Short name T75
Test name
Test status
Simulation time 217775624072 ps
CPU time 189.01 seconds
Started Jun 26 06:01:43 PM PDT 24
Finished Jun 26 06:04:53 PM PDT 24
Peak memory 191384 kb
Host smart-4c7551bf-16ef-4425-b1a3-b3586b060bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746548879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2746548879
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.896333108
Short name T366
Test name
Test status
Simulation time 3029382043982 ps
CPU time 1536.56 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:27:26 PM PDT 24
Peak memory 191292 kb
Host smart-e01d043f-bc6b-4dd8-8cd4-99eb950bd155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896333108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
896333108
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.4195128752
Short name T13
Test name
Test status
Simulation time 18720104518 ps
CPU time 151 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:04:19 PM PDT 24
Peak memory 197788 kb
Host smart-5e60cd42-bfe6-474b-9200-a0294c5ccd9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195128752 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.4195128752
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.48512850
Short name T224
Test name
Test status
Simulation time 41415486210 ps
CPU time 58.52 seconds
Started Jun 26 06:03:41 PM PDT 24
Finished Jun 26 06:04:40 PM PDT 24
Peak memory 191344 kb
Host smart-11db52d2-6fc1-43a8-9796-55c1852b664a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48512850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.48512850
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1257070833
Short name T283
Test name
Test status
Simulation time 199296539824 ps
CPU time 167.89 seconds
Started Jun 26 06:03:40 PM PDT 24
Finished Jun 26 06:06:28 PM PDT 24
Peak memory 193396 kb
Host smart-ec6e1424-7f1f-4fd6-9d75-e54a949b4079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257070833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1257070833
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1721348434
Short name T273
Test name
Test status
Simulation time 635750974472 ps
CPU time 1961.72 seconds
Started Jun 26 06:03:38 PM PDT 24
Finished Jun 26 06:36:20 PM PDT 24
Peak memory 191292 kb
Host smart-cd0ea55c-bcad-4ea6-b750-923fe07fb40b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721348434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1721348434
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1470000508
Short name T123
Test name
Test status
Simulation time 38826751665 ps
CPU time 56.26 seconds
Started Jun 26 06:03:39 PM PDT 24
Finished Jun 26 06:04:36 PM PDT 24
Peak memory 192388 kb
Host smart-b0efc865-1d27-4509-8a1c-90d82cd627a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470000508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1470000508
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2717684649
Short name T444
Test name
Test status
Simulation time 63683142663 ps
CPU time 63.04 seconds
Started Jun 26 06:03:39 PM PDT 24
Finished Jun 26 06:04:43 PM PDT 24
Peak memory 191352 kb
Host smart-10219ea9-a748-49c9-9fe5-d2bcf708f2e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717684649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2717684649
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2797680597
Short name T217
Test name
Test status
Simulation time 259346950436 ps
CPU time 948.02 seconds
Started Jun 26 06:03:39 PM PDT 24
Finished Jun 26 06:19:28 PM PDT 24
Peak memory 193008 kb
Host smart-c39336a5-77e9-4cec-a6a2-ec8198b40956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797680597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2797680597
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.248585908
Short name T445
Test name
Test status
Simulation time 173153416096 ps
CPU time 38.72 seconds
Started Jun 26 06:01:32 PM PDT 24
Finished Jun 26 06:02:12 PM PDT 24
Peak memory 183176 kb
Host smart-8efde22b-8132-4ba4-9fe9-fe8b41ae1f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248585908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.248585908
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3157386971
Short name T328
Test name
Test status
Simulation time 185763265610 ps
CPU time 40.89 seconds
Started Jun 26 06:01:31 PM PDT 24
Finished Jun 26 06:02:14 PM PDT 24
Peak memory 183136 kb
Host smart-587ac7b9-404a-4f95-b98f-e688c342ee82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157386971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3157386971
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1015003366
Short name T386
Test name
Test status
Simulation time 1204190905 ps
CPU time 1.27 seconds
Started Jun 26 06:01:29 PM PDT 24
Finished Jun 26 06:01:32 PM PDT 24
Peak memory 183048 kb
Host smart-40f863e0-e55f-420f-b69d-e652f47be5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015003366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1015003366
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3285188788
Short name T17
Test name
Test status
Simulation time 284805199 ps
CPU time 0.96 seconds
Started Jun 26 06:01:30 PM PDT 24
Finished Jun 26 06:01:33 PM PDT 24
Peak memory 214564 kb
Host smart-1c71e75e-af3d-4e73-b5d0-1f2a0b75884b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285188788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3285188788
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.99441422
Short name T158
Test name
Test status
Simulation time 147606913857 ps
CPU time 256.26 seconds
Started Jun 26 06:01:30 PM PDT 24
Finished Jun 26 06:05:48 PM PDT 24
Peak memory 195840 kb
Host smart-bf93e212-8300-4c95-8dbd-b76135d6e81f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99441422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.99441422
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3312167513
Short name T107
Test name
Test status
Simulation time 298402654216 ps
CPU time 564.16 seconds
Started Jun 26 06:01:33 PM PDT 24
Finished Jun 26 06:10:59 PM PDT 24
Peak memory 207084 kb
Host smart-f3b0b0ea-a7b6-49d5-b76a-98f1b4d0f673
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312167513 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3312167513
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2570026917
Short name T307
Test name
Test status
Simulation time 283933706246 ps
CPU time 263.64 seconds
Started Jun 26 06:01:49 PM PDT 24
Finished Jun 26 06:06:15 PM PDT 24
Peak memory 183140 kb
Host smart-25c553f0-0f20-41df-be97-57277d24879b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570026917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2570026917
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4146177166
Short name T4
Test name
Test status
Simulation time 217423758782 ps
CPU time 155.06 seconds
Started Jun 26 06:01:46 PM PDT 24
Finished Jun 26 06:04:23 PM PDT 24
Peak memory 183104 kb
Host smart-cc628695-43f9-44d0-bf13-c4cdfe8a343e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146177166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4146177166
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1833818570
Short name T262
Test name
Test status
Simulation time 82123893240 ps
CPU time 149.21 seconds
Started Jun 26 06:01:54 PM PDT 24
Finished Jun 26 06:04:24 PM PDT 24
Peak memory 191328 kb
Host smart-5d390278-066a-4b87-8fe5-be58bf1ca32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833818570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1833818570
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2802779453
Short name T55
Test name
Test status
Simulation time 128070395495 ps
CPU time 79.08 seconds
Started Jun 26 06:01:51 PM PDT 24
Finished Jun 26 06:03:12 PM PDT 24
Peak memory 183180 kb
Host smart-3f82e3a6-4af3-4991-906e-f6a7e4938b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802779453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2802779453
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2973957229
Short name T280
Test name
Test status
Simulation time 350407928329 ps
CPU time 305.85 seconds
Started Jun 26 06:01:49 PM PDT 24
Finished Jun 26 06:06:57 PM PDT 24
Peak memory 183136 kb
Host smart-f6b0a1a1-984b-4b52-9779-daf82f308ad4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973957229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2973957229
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2089524960
Short name T406
Test name
Test status
Simulation time 223095341071 ps
CPU time 177.16 seconds
Started Jun 26 06:01:45 PM PDT 24
Finished Jun 26 06:04:44 PM PDT 24
Peak memory 183180 kb
Host smart-94661942-cb2b-413d-b984-9863a768ea17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089524960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2089524960
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3355059087
Short name T439
Test name
Test status
Simulation time 188579759647 ps
CPU time 99.97 seconds
Started Jun 26 06:01:45 PM PDT 24
Finished Jun 26 06:03:25 PM PDT 24
Peak memory 191320 kb
Host smart-4f7cc548-e44e-4ece-b978-021aef6a2bcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355059087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3355059087
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3843281831
Short name T396
Test name
Test status
Simulation time 57382755310 ps
CPU time 70 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:03:00 PM PDT 24
Peak memory 183100 kb
Host smart-63a3b9df-9ba5-4b86-8f6c-e123cddd489a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843281831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3843281831
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3876031840
Short name T438
Test name
Test status
Simulation time 446638688 ps
CPU time 0.75 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:01:50 PM PDT 24
Peak memory 183032 kb
Host smart-deda22d7-7af8-45b3-bfef-aa37fb6bfe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876031840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3876031840
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.996758954
Short name T233
Test name
Test status
Simulation time 1952344294673 ps
CPU time 931.67 seconds
Started Jun 26 06:01:48 PM PDT 24
Finished Jun 26 06:17:22 PM PDT 24
Peak memory 191316 kb
Host smart-1701243f-7ea9-4f7b-a066-7fa8da7aff9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996758954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
996758954
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2257095591
Short name T298
Test name
Test status
Simulation time 7169875512 ps
CPU time 12.41 seconds
Started Jun 26 06:01:48 PM PDT 24
Finished Jun 26 06:02:03 PM PDT 24
Peak memory 183136 kb
Host smart-b7125acc-8997-40e5-ad04-482725cf9536
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257095591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2257095591
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2808400111
Short name T381
Test name
Test status
Simulation time 353035307570 ps
CPU time 120.96 seconds
Started Jun 26 06:01:48 PM PDT 24
Finished Jun 26 06:03:52 PM PDT 24
Peak memory 183000 kb
Host smart-52c4c5eb-696b-4584-bbda-ebd4052e04ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808400111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2808400111
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1511094283
Short name T180
Test name
Test status
Simulation time 172304896498 ps
CPU time 379.72 seconds
Started Jun 26 06:01:48 PM PDT 24
Finished Jun 26 06:08:10 PM PDT 24
Peak memory 193832 kb
Host smart-6d18f1a5-0053-464e-917f-8398cbdd355b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511094283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1511094283
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3439990953
Short name T432
Test name
Test status
Simulation time 318258393 ps
CPU time 3.1 seconds
Started Jun 26 06:01:54 PM PDT 24
Finished Jun 26 06:01:58 PM PDT 24
Peak memory 183084 kb
Host smart-01ffd9e7-e17a-4414-9043-db983580db28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439990953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3439990953
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2440341975
Short name T272
Test name
Test status
Simulation time 295904373313 ps
CPU time 242.13 seconds
Started Jun 26 06:01:46 PM PDT 24
Finished Jun 26 06:05:49 PM PDT 24
Peak memory 183128 kb
Host smart-5ed79825-05d0-4719-82c1-8a79aa1fbe53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440341975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2440341975
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4165536381
Short name T403
Test name
Test status
Simulation time 675511601395 ps
CPU time 265.04 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:06:14 PM PDT 24
Peak memory 183104 kb
Host smart-9f242ca9-76fc-471f-b95d-ab8cfe81dc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165536381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4165536381
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2080317595
Short name T137
Test name
Test status
Simulation time 230359451186 ps
CPU time 111.46 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:03:41 PM PDT 24
Peak memory 191376 kb
Host smart-63bff3df-526d-40f7-87a5-358877a33e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080317595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2080317595
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.4090652634
Short name T188
Test name
Test status
Simulation time 382578434109 ps
CPU time 649.43 seconds
Started Jun 26 06:01:54 PM PDT 24
Finished Jun 26 06:12:44 PM PDT 24
Peak memory 191332 kb
Host smart-5cf6be09-6de7-4186-a6b6-594c4d682c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090652634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.4090652634
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.3355542300
Short name T37
Test name
Test status
Simulation time 398351861147 ps
CPU time 1098.98 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:20:09 PM PDT 24
Peak memory 215568 kb
Host smart-5649f065-cf34-4301-ba6c-8e509d95d9f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355542300 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.3355542300
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.654246929
Short name T48
Test name
Test status
Simulation time 97649395805 ps
CPU time 50.35 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:02:40 PM PDT 24
Peak memory 183092 kb
Host smart-2b7cc8a5-db32-4ac7-9600-b059538b3757
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654246929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.654246929
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1729970251
Short name T393
Test name
Test status
Simulation time 21930511048 ps
CPU time 17.89 seconds
Started Jun 26 06:01:48 PM PDT 24
Finished Jun 26 06:02:08 PM PDT 24
Peak memory 183188 kb
Host smart-51a4c1d9-757d-49f0-9b6f-35fcc8b4b807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729970251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1729970251
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1692441939
Short name T57
Test name
Test status
Simulation time 248854605982 ps
CPU time 105.8 seconds
Started Jun 26 06:01:49 PM PDT 24
Finished Jun 26 06:03:37 PM PDT 24
Peak memory 191340 kb
Host smart-73c57a3c-bb7f-4a16-8cb6-c6fbe4cd3cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692441939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1692441939
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.389150629
Short name T411
Test name
Test status
Simulation time 45473419185 ps
CPU time 73.73 seconds
Started Jun 26 06:01:49 PM PDT 24
Finished Jun 26 06:03:05 PM PDT 24
Peak memory 183148 kb
Host smart-9150e48a-3026-4211-9a24-015c89e0f7bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389150629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.389150629
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1452147472
Short name T414
Test name
Test status
Simulation time 33981217150 ps
CPU time 46.35 seconds
Started Jun 26 06:01:49 PM PDT 24
Finished Jun 26 06:02:37 PM PDT 24
Peak memory 183140 kb
Host smart-9d97a5e1-0368-4de8-b7c9-84b354ef8f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452147472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1452147472
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.771776902
Short name T6
Test name
Test status
Simulation time 536338456417 ps
CPU time 1574.18 seconds
Started Jun 26 06:01:50 PM PDT 24
Finished Jun 26 06:28:06 PM PDT 24
Peak memory 191192 kb
Host smart-33b29db7-5131-44f3-ac6d-f2ea608ede79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771776902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.771776902
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3645527997
Short name T427
Test name
Test status
Simulation time 298098301 ps
CPU time 0.71 seconds
Started Jun 26 06:01:50 PM PDT 24
Finished Jun 26 06:01:53 PM PDT 24
Peak memory 183228 kb
Host smart-5bef3127-f750-4a1b-bb18-71ca89184a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645527997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3645527997
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3117230978
Short name T340
Test name
Test status
Simulation time 199405960205 ps
CPU time 383.5 seconds
Started Jun 26 06:01:51 PM PDT 24
Finished Jun 26 06:08:16 PM PDT 24
Peak memory 191572 kb
Host smart-80902e0b-4335-4979-aefc-93f1cc2b8f01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117230978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3117230978
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.3464727686
Short name T41
Test name
Test status
Simulation time 53070880933 ps
CPU time 216.98 seconds
Started Jun 26 06:01:49 PM PDT 24
Finished Jun 26 06:05:28 PM PDT 24
Peak memory 206036 kb
Host smart-36423bc1-6e73-4b98-97cd-cf891eaae4ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464727686 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.3464727686
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3249801216
Short name T292
Test name
Test status
Simulation time 486343942567 ps
CPU time 402.03 seconds
Started Jun 26 06:01:49 PM PDT 24
Finished Jun 26 06:08:33 PM PDT 24
Peak memory 183140 kb
Host smart-86636c06-1be8-49ce-8992-fce765e20391
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249801216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3249801216
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.764323185
Short name T380
Test name
Test status
Simulation time 135548799073 ps
CPU time 196.98 seconds
Started Jun 26 06:01:54 PM PDT 24
Finished Jun 26 06:05:12 PM PDT 24
Peak memory 183148 kb
Host smart-31d5ff08-7d54-463e-8095-e78b334e2c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764323185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.764323185
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2476608542
Short name T310
Test name
Test status
Simulation time 43549834204 ps
CPU time 26.07 seconds
Started Jun 26 06:01:52 PM PDT 24
Finished Jun 26 06:02:19 PM PDT 24
Peak memory 183072 kb
Host smart-df4bfa01-159e-452b-a8d2-d4dc6216ee78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476608542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2476608542
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2997063312
Short name T341
Test name
Test status
Simulation time 131078450861 ps
CPU time 655.52 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:12:56 PM PDT 24
Peak memory 183144 kb
Host smart-bfbd2f67-4c0b-4dcf-a228-4a26b6530540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997063312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2997063312
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2198609204
Short name T400
Test name
Test status
Simulation time 540254866137 ps
CPU time 191.15 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:05:01 PM PDT 24
Peak memory 183152 kb
Host smart-22b8e370-168c-4783-a04c-b1a74dc059ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198609204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2198609204
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3795937769
Short name T371
Test name
Test status
Simulation time 18187125839 ps
CPU time 28.64 seconds
Started Jun 26 06:01:47 PM PDT 24
Finished Jun 26 06:02:18 PM PDT 24
Peak memory 183152 kb
Host smart-9b703319-5d41-4f5f-8968-07a038f63d5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795937769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3795937769
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2424481593
Short name T395
Test name
Test status
Simulation time 57557165631 ps
CPU time 83.87 seconds
Started Jun 26 06:01:58 PM PDT 24
Finished Jun 26 06:03:23 PM PDT 24
Peak memory 183176 kb
Host smart-1b017edd-7c8a-4dfb-ac9b-f324b4da94ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424481593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2424481593
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3038044622
Short name T293
Test name
Test status
Simulation time 197344837125 ps
CPU time 70.69 seconds
Started Jun 26 06:02:01 PM PDT 24
Finished Jun 26 06:03:14 PM PDT 24
Peak memory 183380 kb
Host smart-bf88124a-7699-4c2d-8e38-508400929709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038044622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3038044622
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3828342581
Short name T367
Test name
Test status
Simulation time 48322187240 ps
CPU time 42.95 seconds
Started Jun 26 06:01:46 PM PDT 24
Finished Jun 26 06:02:30 PM PDT 24
Peak memory 183156 kb
Host smart-21c9c591-bba3-47e7-b441-df52d9864598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828342581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3828342581
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4081164563
Short name T416
Test name
Test status
Simulation time 205188489876 ps
CPU time 906.32 seconds
Started Jun 26 06:01:57 PM PDT 24
Finished Jun 26 06:17:05 PM PDT 24
Peak memory 191324 kb
Host smart-c83f4972-7aab-431f-a9ad-e582c0341f10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081164563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4081164563
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.445197883
Short name T49
Test name
Test status
Simulation time 304006332176 ps
CPU time 107.79 seconds
Started Jun 26 06:02:01 PM PDT 24
Finished Jun 26 06:03:52 PM PDT 24
Peak memory 183172 kb
Host smart-88a1496a-63f8-43a5-a605-161010c4b2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445197883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.445197883
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.4094905458
Short name T291
Test name
Test status
Simulation time 203563157971 ps
CPU time 84.01 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:03:25 PM PDT 24
Peak memory 183092 kb
Host smart-a638bd70-915f-4bed-b201-db928b0adb5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094905458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.4094905458
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2222122677
Short name T407
Test name
Test status
Simulation time 26621554 ps
CPU time 0.6 seconds
Started Jun 26 06:02:00 PM PDT 24
Finished Jun 26 06:02:02 PM PDT 24
Peak memory 183040 kb
Host smart-06e6e6e5-c453-4659-8a72-207e37f9267d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222122677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2222122677
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3413646286
Short name T428
Test name
Test status
Simulation time 212865822657 ps
CPU time 313.28 seconds
Started Jun 26 06:02:00 PM PDT 24
Finished Jun 26 06:07:16 PM PDT 24
Peak memory 183164 kb
Host smart-8c4bf24a-07f0-4e72-84f9-6f5a233d3c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413646286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3413646286
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1569644405
Short name T132
Test name
Test status
Simulation time 17274520698 ps
CPU time 31.82 seconds
Started Jun 26 06:01:30 PM PDT 24
Finished Jun 26 06:02:04 PM PDT 24
Peak memory 183092 kb
Host smart-2d2e3984-2efa-446d-ba67-9c5df5522236
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569644405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1569644405
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2196148914
Short name T425
Test name
Test status
Simulation time 234999549320 ps
CPU time 231.46 seconds
Started Jun 26 06:01:33 PM PDT 24
Finished Jun 26 06:05:25 PM PDT 24
Peak memory 183172 kb
Host smart-c698a331-ff7b-4518-b982-c761db3c54e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196148914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2196148914
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.752813969
Short name T200
Test name
Test status
Simulation time 517492386368 ps
CPU time 366.63 seconds
Started Jun 26 06:01:31 PM PDT 24
Finished Jun 26 06:07:40 PM PDT 24
Peak memory 191280 kb
Host smart-459e13fe-e08e-4d3b-aec5-2baeb8aa19ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752813969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.752813969
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3595951957
Short name T16
Test name
Test status
Simulation time 499084429 ps
CPU time 0.83 seconds
Started Jun 26 06:01:28 PM PDT 24
Finished Jun 26 06:01:31 PM PDT 24
Peak memory 213388 kb
Host smart-7511cfad-198f-40d9-b5b8-9d548eebe893
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595951957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3595951957
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1952302414
Short name T25
Test name
Test status
Simulation time 1838020903175 ps
CPU time 638.61 seconds
Started Jun 26 06:01:32 PM PDT 24
Finished Jun 26 06:12:12 PM PDT 24
Peak memory 191328 kb
Host smart-8fd45c3c-159c-401c-88cd-693189ea2e68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952302414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1952302414
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2270026107
Short name T73
Test name
Test status
Simulation time 2336463392100 ps
CPU time 1181.43 seconds
Started Jun 26 06:02:00 PM PDT 24
Finished Jun 26 06:21:44 PM PDT 24
Peak memory 183104 kb
Host smart-7fa8ef4d-0a5e-4747-9026-fbcab55e4949
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270026107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2270026107
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_random.1311769544
Short name T151
Test name
Test status
Simulation time 299510380656 ps
CPU time 445.82 seconds
Started Jun 26 06:02:01 PM PDT 24
Finished Jun 26 06:09:30 PM PDT 24
Peak memory 194932 kb
Host smart-c3c302a2-6af9-43db-b616-255f22fe9d00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311769544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1311769544
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2070038254
Short name T7
Test name
Test status
Simulation time 10975716631 ps
CPU time 5.94 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:02:08 PM PDT 24
Peak memory 191288 kb
Host smart-f612bc86-4499-42e8-8fd8-b221407b2f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070038254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2070038254
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1730346517
Short name T157
Test name
Test status
Simulation time 356104718631 ps
CPU time 618.05 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:12:19 PM PDT 24
Peak memory 182980 kb
Host smart-a05693d7-10ad-4227-ad28-d58589e6a22e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730346517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1730346517
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2138594826
Short name T382
Test name
Test status
Simulation time 503748946701 ps
CPU time 180.96 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:05:02 PM PDT 24
Peak memory 183172 kb
Host smart-ee4b4667-1e21-4220-8566-8e4a4e851e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138594826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2138594826
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2132571580
Short name T373
Test name
Test status
Simulation time 127925358 ps
CPU time 0.64 seconds
Started Jun 26 06:02:00 PM PDT 24
Finished Jun 26 06:02:04 PM PDT 24
Peak memory 182956 kb
Host smart-dd5410e7-e9bf-4f44-93e5-1ebeaf86b5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132571580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2132571580
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2020257322
Short name T191
Test name
Test status
Simulation time 5390433611 ps
CPU time 8.98 seconds
Started Jun 26 06:01:56 PM PDT 24
Finished Jun 26 06:02:06 PM PDT 24
Peak memory 183116 kb
Host smart-ae5cf364-f058-41d2-86c4-2ccbd8a6a020
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020257322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2020257322
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2171642622
Short name T58
Test name
Test status
Simulation time 133184232603 ps
CPU time 188.79 seconds
Started Jun 26 06:01:58 PM PDT 24
Finished Jun 26 06:05:08 PM PDT 24
Peak memory 183168 kb
Host smart-7ab8f65b-790c-4bc9-b323-f6f2706039ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171642622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2171642622
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3899283172
Short name T331
Test name
Test status
Simulation time 281496167757 ps
CPU time 816.99 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:15:38 PM PDT 24
Peak memory 194576 kb
Host smart-0a46cfca-ac76-4b5a-ab9d-573c73fb88ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899283172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3899283172
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1852015653
Short name T417
Test name
Test status
Simulation time 12110254970 ps
CPU time 5.62 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:02:07 PM PDT 24
Peak memory 183084 kb
Host smart-0ef64e60-d5a8-498d-9e66-b719c528eed6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852015653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1852015653
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3840166562
Short name T418
Test name
Test status
Simulation time 172407542850 ps
CPU time 260.06 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:06:21 PM PDT 24
Peak memory 183140 kb
Host smart-ab946044-093d-4112-9cfd-b2dc22bc0cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840166562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3840166562
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.417826523
Short name T150
Test name
Test status
Simulation time 1309954006168 ps
CPU time 701.77 seconds
Started Jun 26 06:01:58 PM PDT 24
Finished Jun 26 06:13:41 PM PDT 24
Peak memory 191352 kb
Host smart-8609b90f-ca6c-4270-a9c3-5e736198f96d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417826523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
417826523
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1018556891
Short name T36
Test name
Test status
Simulation time 67113542751 ps
CPU time 259.95 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:06:22 PM PDT 24
Peak memory 205992 kb
Host smart-8266f4a2-565f-464e-98da-5b20a59b5a26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018556891 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1018556891
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1038556128
Short name T194
Test name
Test status
Simulation time 5046692712 ps
CPU time 5.45 seconds
Started Jun 26 06:01:58 PM PDT 24
Finished Jun 26 06:02:06 PM PDT 24
Peak memory 183156 kb
Host smart-8fbd468b-5887-4287-921f-b2b93234ae84
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038556128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1038556128
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1327717459
Short name T398
Test name
Test status
Simulation time 767872354976 ps
CPU time 299.97 seconds
Started Jun 26 06:02:00 PM PDT 24
Finished Jun 26 06:07:02 PM PDT 24
Peak memory 183136 kb
Host smart-4ecaeae1-e1e7-4d96-9a1c-483352ea809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327717459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1327717459
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3685204549
Short name T72
Test name
Test status
Simulation time 194689105960 ps
CPU time 163 seconds
Started Jun 26 06:02:00 PM PDT 24
Finished Jun 26 06:04:46 PM PDT 24
Peak memory 191376 kb
Host smart-460aa1d2-d95a-4735-b96b-00b0f00fb7ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685204549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3685204549
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2012543284
Short name T437
Test name
Test status
Simulation time 316462156 ps
CPU time 0.94 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:02:01 PM PDT 24
Peak memory 182960 kb
Host smart-f117375a-3783-4377-abca-6c750dc81bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012543284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2012543284
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.897212119
Short name T154
Test name
Test status
Simulation time 807098681477 ps
CPU time 384.35 seconds
Started Jun 26 06:02:07 PM PDT 24
Finished Jun 26 06:08:33 PM PDT 24
Peak memory 183144 kb
Host smart-5f7aab1c-c310-4144-83f6-b8202271321e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897212119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.897212119
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.658499683
Short name T377
Test name
Test status
Simulation time 664198474965 ps
CPU time 156.54 seconds
Started Jun 26 06:02:01 PM PDT 24
Finished Jun 26 06:04:41 PM PDT 24
Peak memory 183172 kb
Host smart-fe079213-b85e-4e8e-b542-7eee15270038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658499683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.658499683
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.610051661
Short name T126
Test name
Test status
Simulation time 185647628816 ps
CPU time 460.23 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:09:41 PM PDT 24
Peak memory 191344 kb
Host smart-7ab9c725-fff9-4b1f-bd08-942e2e0186db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610051661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.610051661
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.678896211
Short name T140
Test name
Test status
Simulation time 148376796297 ps
CPU time 128.54 seconds
Started Jun 26 06:02:02 PM PDT 24
Finished Jun 26 06:04:13 PM PDT 24
Peak memory 191040 kb
Host smart-95320713-e11d-4b4c-8a21-a7f79f47d798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678896211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.678896211
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3409471410
Short name T447
Test name
Test status
Simulation time 2206799395121 ps
CPU time 855.25 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:16:17 PM PDT 24
Peak memory 183148 kb
Host smart-3912080f-39bb-4761-a3e5-10337a2c9662
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409471410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3409471410
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2419511212
Short name T379
Test name
Test status
Simulation time 512732524378 ps
CPU time 190.57 seconds
Started Jun 26 06:02:02 PM PDT 24
Finished Jun 26 06:05:15 PM PDT 24
Peak memory 183156 kb
Host smart-729061af-dfe5-4ecb-9e2b-7cc4396ba744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419511212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2419511212
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1055963769
Short name T222
Test name
Test status
Simulation time 90634367507 ps
CPU time 198.94 seconds
Started Jun 26 06:02:01 PM PDT 24
Finished Jun 26 06:05:23 PM PDT 24
Peak memory 193376 kb
Host smart-dd19bf5e-e37a-41d1-83de-b1485a7a4807
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055963769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1055963769
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2975782128
Short name T281
Test name
Test status
Simulation time 22495712217 ps
CPU time 182.66 seconds
Started Jun 26 06:02:03 PM PDT 24
Finished Jun 26 06:05:08 PM PDT 24
Peak memory 191352 kb
Host smart-9daff370-e507-4b20-ba16-78de630a6320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975782128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2975782128
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1263353317
Short name T348
Test name
Test status
Simulation time 777597820397 ps
CPU time 896.7 seconds
Started Jun 26 06:02:06 PM PDT 24
Finished Jun 26 06:17:04 PM PDT 24
Peak memory 195352 kb
Host smart-ec01c164-1450-4b53-ae62-e5d314dcfad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263353317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1263353317
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.3176212147
Short name T38
Test name
Test status
Simulation time 23691970674 ps
CPU time 196.52 seconds
Started Jun 26 06:02:01 PM PDT 24
Finished Jun 26 06:05:21 PM PDT 24
Peak memory 206048 kb
Host smart-0414f757-b155-4380-b537-7815e4be9983
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176212147 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.3176212147
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2174465973
Short name T257
Test name
Test status
Simulation time 656622178507 ps
CPU time 311.65 seconds
Started Jun 26 06:02:01 PM PDT 24
Finished Jun 26 06:07:16 PM PDT 24
Peak memory 183148 kb
Host smart-86aca29b-4cde-495b-a574-f8e881f1570f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174465973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2174465973
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2013326081
Short name T404
Test name
Test status
Simulation time 363555530457 ps
CPU time 126.28 seconds
Started Jun 26 06:02:03 PM PDT 24
Finished Jun 26 06:04:11 PM PDT 24
Peak memory 183340 kb
Host smart-4311fe3f-7725-4116-919d-8bab8b433bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013326081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2013326081
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3404727270
Short name T353
Test name
Test status
Simulation time 188973813327 ps
CPU time 643.13 seconds
Started Jun 26 06:02:03 PM PDT 24
Finished Jun 26 06:12:48 PM PDT 24
Peak memory 183344 kb
Host smart-81349dd0-346e-4790-b69c-107e7d92eeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404727270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3404727270
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2317054304
Short name T183
Test name
Test status
Simulation time 382166219087 ps
CPU time 641.65 seconds
Started Jun 26 06:02:02 PM PDT 24
Finished Jun 26 06:12:47 PM PDT 24
Peak memory 183128 kb
Host smart-17b2146a-c412-4ae4-9825-eb2f9e79d9a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317054304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2317054304
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.12216043
Short name T399
Test name
Test status
Simulation time 452661897334 ps
CPU time 164.71 seconds
Started Jun 26 06:02:05 PM PDT 24
Finished Jun 26 06:04:51 PM PDT 24
Peak memory 183180 kb
Host smart-f471edc1-c802-42ff-a434-35509c769c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12216043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.12216043
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2544709297
Short name T279
Test name
Test status
Simulation time 24326457283 ps
CPU time 6.83 seconds
Started Jun 26 06:02:04 PM PDT 24
Finished Jun 26 06:02:13 PM PDT 24
Peak memory 191368 kb
Host smart-f2c00b5d-0ecb-44f2-b73a-48ffe5fe8303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544709297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2544709297
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1285301976
Short name T364
Test name
Test status
Simulation time 50542284763 ps
CPU time 78.27 seconds
Started Jun 26 06:02:07 PM PDT 24
Finished Jun 26 06:03:26 PM PDT 24
Peak memory 194896 kb
Host smart-aa935ffe-3a52-4845-be93-f03d236bfd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285301976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1285301976
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.82979921
Short name T21
Test name
Test status
Simulation time 448867618894 ps
CPU time 202.16 seconds
Started Jun 26 06:02:02 PM PDT 24
Finished Jun 26 06:05:27 PM PDT 24
Peak memory 183344 kb
Host smart-1d553029-4017-42af-bd41-b9dce0986049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82979921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.82979921
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2571474696
Short name T156
Test name
Test status
Simulation time 85709453542 ps
CPU time 142.52 seconds
Started Jun 26 06:02:02 PM PDT 24
Finished Jun 26 06:04:27 PM PDT 24
Peak memory 190996 kb
Host smart-d1c211a6-9074-4e45-a75b-1b85c49a778c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571474696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2571474696
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3522977213
Short name T240
Test name
Test status
Simulation time 276724386917 ps
CPU time 897.05 seconds
Started Jun 26 06:02:03 PM PDT 24
Finished Jun 26 06:17:02 PM PDT 24
Peak memory 191352 kb
Host smart-380cf009-3693-4115-85db-e2be9fa89e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522977213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3522977213
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3997833206
Short name T302
Test name
Test status
Simulation time 546640776533 ps
CPU time 287.05 seconds
Started Jun 26 06:01:31 PM PDT 24
Finished Jun 26 06:06:20 PM PDT 24
Peak memory 183336 kb
Host smart-9e39b5ad-b415-4cd1-8dd7-345cbd15b95c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997833206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3997833206
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.180464114
Short name T249
Test name
Test status
Simulation time 138161850305 ps
CPU time 53.97 seconds
Started Jun 26 06:01:29 PM PDT 24
Finished Jun 26 06:02:25 PM PDT 24
Peak memory 191392 kb
Host smart-70b15637-1ae4-4869-9831-1dc86ba05086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180464114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.180464114
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2178954390
Short name T19
Test name
Test status
Simulation time 574327472 ps
CPU time 0.83 seconds
Started Jun 26 06:01:34 PM PDT 24
Finished Jun 26 06:01:36 PM PDT 24
Peak memory 213392 kb
Host smart-63a60fd4-6976-4069-abd5-2b2ff4c287a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178954390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2178954390
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2857707118
Short name T326
Test name
Test status
Simulation time 1500331169498 ps
CPU time 1531.72 seconds
Started Jun 26 06:01:35 PM PDT 24
Finished Jun 26 06:27:08 PM PDT 24
Peak memory 191352 kb
Host smart-eda84217-bb09-4817-b689-51181211d78e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857707118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2857707118
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3524219072
Short name T161
Test name
Test status
Simulation time 72459114642 ps
CPU time 59.35 seconds
Started Jun 26 06:02:03 PM PDT 24
Finished Jun 26 06:03:04 PM PDT 24
Peak memory 183136 kb
Host smart-50dbc261-5d04-4927-a974-513ba3ef6f85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524219072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3524219072
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1435056287
Short name T83
Test name
Test status
Simulation time 26174581788 ps
CPU time 37.15 seconds
Started Jun 26 06:01:59 PM PDT 24
Finished Jun 26 06:02:38 PM PDT 24
Peak memory 183156 kb
Host smart-8097fa62-39fd-41bd-a348-5a99ca44e167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435056287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1435056287
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2091058125
Short name T429
Test name
Test status
Simulation time 573516931569 ps
CPU time 350.64 seconds
Started Jun 26 06:02:03 PM PDT 24
Finished Jun 26 06:07:56 PM PDT 24
Peak memory 191332 kb
Host smart-a83ca539-412a-481b-9abd-078a042be43f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091058125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2091058125
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.919933499
Short name T431
Test name
Test status
Simulation time 134028985747 ps
CPU time 1177.9 seconds
Started Jun 26 06:02:04 PM PDT 24
Finished Jun 26 06:21:44 PM PDT 24
Peak memory 191324 kb
Host smart-4720c1d8-f653-4f33-a8d9-c0802cd1d924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919933499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.919933499
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1887554107
Short name T450
Test name
Test status
Simulation time 99171914685 ps
CPU time 152.27 seconds
Started Jun 26 06:02:05 PM PDT 24
Finished Jun 26 06:04:39 PM PDT 24
Peak memory 182912 kb
Host smart-1b2d78d5-56d2-4e0f-9984-cf011539ee69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887554107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1887554107
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1561454365
Short name T387
Test name
Test status
Simulation time 465769756721 ps
CPU time 179.98 seconds
Started Jun 26 06:02:05 PM PDT 24
Finished Jun 26 06:05:07 PM PDT 24
Peak memory 183188 kb
Host smart-ec9f9742-fad2-4dba-a18f-0a4209cebb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561454365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1561454365
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4139400592
Short name T346
Test name
Test status
Simulation time 25202391153 ps
CPU time 41.61 seconds
Started Jun 26 06:02:00 PM PDT 24
Finished Jun 26 06:02:44 PM PDT 24
Peak memory 183164 kb
Host smart-aa5544d9-42fa-4bab-be7c-969cd779c926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139400592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4139400592
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.802389349
Short name T453
Test name
Test status
Simulation time 14766089809 ps
CPU time 13.67 seconds
Started Jun 26 06:02:10 PM PDT 24
Finished Jun 26 06:02:25 PM PDT 24
Peak memory 191352 kb
Host smart-1a065b9e-2785-4b88-828b-e97541c70ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802389349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.802389349
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2905004048
Short name T149
Test name
Test status
Simulation time 594964498898 ps
CPU time 684.05 seconds
Started Jun 26 06:02:07 PM PDT 24
Finished Jun 26 06:13:33 PM PDT 24
Peak memory 191360 kb
Host smart-c9bdfcf8-5063-47a4-bf3d-18eacc75d5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905004048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2905004048
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.3158449108
Short name T14
Test name
Test status
Simulation time 55367309219 ps
CPU time 460.08 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:09:51 PM PDT 24
Peak memory 206028 kb
Host smart-a267a748-7bb4-40bc-a6f4-c4edd5549f31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158449108 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.3158449108
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2281574779
Short name T124
Test name
Test status
Simulation time 118910762555 ps
CPU time 199.65 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:05:30 PM PDT 24
Peak memory 183084 kb
Host smart-f7cc204c-e2fd-4c65-9452-eb2b93570914
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281574779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2281574779
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2659595976
Short name T422
Test name
Test status
Simulation time 236080496653 ps
CPU time 84.56 seconds
Started Jun 26 06:02:10 PM PDT 24
Finished Jun 26 06:03:36 PM PDT 24
Peak memory 183124 kb
Host smart-c3fd0b4d-1a0a-42b0-a402-d5e29c646480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659595976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2659595976
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1404492127
Short name T5
Test name
Test status
Simulation time 41609392825 ps
CPU time 71.98 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:03:21 PM PDT 24
Peak memory 183168 kb
Host smart-651f8a62-ae1d-4e81-9134-ffc29f4883d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404492127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1404492127
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.123929852
Short name T360
Test name
Test status
Simulation time 22154611520 ps
CPU time 149.59 seconds
Started Jun 26 06:02:07 PM PDT 24
Finished Jun 26 06:04:38 PM PDT 24
Peak memory 191280 kb
Host smart-765f9d81-934a-4e4b-9a88-e0e16c42bd0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123929852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.123929852
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3375174747
Short name T349
Test name
Test status
Simulation time 499229767170 ps
CPU time 276.17 seconds
Started Jun 26 06:02:10 PM PDT 24
Finished Jun 26 06:06:47 PM PDT 24
Peak memory 194836 kb
Host smart-a4c42cd2-e956-4af2-9e2c-5c5f32b54a54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375174747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3375174747
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1592285161
Short name T234
Test name
Test status
Simulation time 584016055540 ps
CPU time 565.81 seconds
Started Jun 26 06:02:06 PM PDT 24
Finished Jun 26 06:11:33 PM PDT 24
Peak memory 183164 kb
Host smart-632adae8-d6e6-47be-a95a-7d75f141f825
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592285161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1592285161
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2206991479
Short name T372
Test name
Test status
Simulation time 47238956806 ps
CPU time 66.7 seconds
Started Jun 26 06:02:09 PM PDT 24
Finished Jun 26 06:03:17 PM PDT 24
Peak memory 183168 kb
Host smart-7063e821-46c5-4cfe-a649-96d4cdf77ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206991479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2206991479
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1458524682
Short name T43
Test name
Test status
Simulation time 164880391381 ps
CPU time 255.49 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:06:26 PM PDT 24
Peak memory 191332 kb
Host smart-9349bfa5-cfa6-4df8-8f8d-fb0c12eddf75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458524682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1458524682
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3522546364
Short name T193
Test name
Test status
Simulation time 22512047900 ps
CPU time 133.58 seconds
Started Jun 26 06:02:09 PM PDT 24
Finished Jun 26 06:04:25 PM PDT 24
Peak memory 183172 kb
Host smart-7011be64-9608-4e12-808c-2c80de4449fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522546364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3522546364
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3314198468
Short name T426
Test name
Test status
Simulation time 842976161572 ps
CPU time 310.41 seconds
Started Jun 26 06:02:10 PM PDT 24
Finished Jun 26 06:07:22 PM PDT 24
Peak memory 183148 kb
Host smart-bde69c5c-b83f-4cfb-9d41-68c42f299b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314198468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3314198468
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3472748406
Short name T401
Test name
Test status
Simulation time 200189017702 ps
CPU time 367.82 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:08:18 PM PDT 24
Peak memory 183176 kb
Host smart-874b26d7-893b-4ff2-aa96-4eee27015b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472748406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3472748406
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.186572438
Short name T24
Test name
Test status
Simulation time 165559788897 ps
CPU time 77.59 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:03:28 PM PDT 24
Peak memory 183100 kb
Host smart-37cca9c8-72eb-43dc-ac01-102a8a913b0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186572438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.186572438
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1369192790
Short name T419
Test name
Test status
Simulation time 136288299979 ps
CPU time 54.59 seconds
Started Jun 26 06:02:09 PM PDT 24
Finished Jun 26 06:03:06 PM PDT 24
Peak memory 183340 kb
Host smart-2f947c30-ea05-40b2-8e94-493580f21306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369192790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1369192790
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2466200608
Short name T448
Test name
Test status
Simulation time 382553409316 ps
CPU time 899.39 seconds
Started Jun 26 06:02:09 PM PDT 24
Finished Jun 26 06:17:10 PM PDT 24
Peak memory 183152 kb
Host smart-c7fe1b9c-de3e-448e-b661-2922344d80ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466200608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2466200608
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2753118649
Short name T405
Test name
Test status
Simulation time 1084807762899 ps
CPU time 328.09 seconds
Started Jun 26 06:02:09 PM PDT 24
Finished Jun 26 06:07:39 PM PDT 24
Peak memory 191340 kb
Host smart-e1842077-393e-41c1-8969-a3df1f1678c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753118649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2753118649
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2819030492
Short name T163
Test name
Test status
Simulation time 78595376009 ps
CPU time 43.2 seconds
Started Jun 26 06:02:09 PM PDT 24
Finished Jun 26 06:02:54 PM PDT 24
Peak memory 183156 kb
Host smart-d7919535-36e5-4193-812b-dd8007f4a744
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819030492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2819030492
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2332831239
Short name T62
Test name
Test status
Simulation time 318162766591 ps
CPU time 258.04 seconds
Started Jun 26 06:02:11 PM PDT 24
Finished Jun 26 06:06:30 PM PDT 24
Peak memory 183164 kb
Host smart-78df2189-e515-4e17-b6dc-62cbf7edef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332831239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2332831239
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2814269625
Short name T356
Test name
Test status
Simulation time 319604291282 ps
CPU time 498.58 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:10:29 PM PDT 24
Peak memory 191356 kb
Host smart-101119ed-70a9-4cab-8b15-140f28a8b85b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814269625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2814269625
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2191720498
Short name T370
Test name
Test status
Simulation time 45844851316 ps
CPU time 286.71 seconds
Started Jun 26 06:02:06 PM PDT 24
Finished Jun 26 06:06:54 PM PDT 24
Peak memory 183184 kb
Host smart-57a155a6-50b3-49e5-8d40-0b2b87fc7463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191720498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2191720498
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.986535820
Short name T68
Test name
Test status
Simulation time 1955660236579 ps
CPU time 867.45 seconds
Started Jun 26 06:02:06 PM PDT 24
Finished Jun 26 06:16:35 PM PDT 24
Peak memory 195212 kb
Host smart-031e0f43-eef1-42ca-b825-5a9654a5a9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986535820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
986535820
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2661510486
Short name T264
Test name
Test status
Simulation time 1430075978062 ps
CPU time 716.15 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:14:06 PM PDT 24
Peak memory 183164 kb
Host smart-2ec2fead-d104-4fbb-877a-bb5cc9003366
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661510486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2661510486
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3958353785
Short name T376
Test name
Test status
Simulation time 50230422847 ps
CPU time 39.8 seconds
Started Jun 26 06:02:07 PM PDT 24
Finished Jun 26 06:02:48 PM PDT 24
Peak memory 183164 kb
Host smart-318c9b01-0c81-4e9e-a7c3-664d0647eae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958353785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3958353785
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1315161136
Short name T443
Test name
Test status
Simulation time 200958717086 ps
CPU time 194.31 seconds
Started Jun 26 06:02:10 PM PDT 24
Finished Jun 26 06:05:26 PM PDT 24
Peak memory 191348 kb
Host smart-b07b14ca-d3ba-457c-9fbe-fce96d458340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315161136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1315161136
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.225154359
Short name T325
Test name
Test status
Simulation time 158095894377 ps
CPU time 716.29 seconds
Started Jun 26 06:02:06 PM PDT 24
Finished Jun 26 06:14:04 PM PDT 24
Peak memory 191280 kb
Host smart-1437c892-98cf-41d9-841a-ad5a9c5bd809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225154359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.225154359
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3775910138
Short name T368
Test name
Test status
Simulation time 188406425984 ps
CPU time 77.24 seconds
Started Jun 26 06:02:09 PM PDT 24
Finished Jun 26 06:03:28 PM PDT 24
Peak memory 191340 kb
Host smart-b73538df-857f-4b72-b606-18c51f0f653a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775910138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3775910138
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.4131926767
Short name T145
Test name
Test status
Simulation time 140680536771 ps
CPU time 207.94 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:05:38 PM PDT 24
Peak memory 183364 kb
Host smart-be02c557-2821-4a5b-8f3c-386d247e5121
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131926767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.4131926767
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.287930138
Short name T388
Test name
Test status
Simulation time 308431445536 ps
CPU time 237.74 seconds
Started Jun 26 06:02:08 PM PDT 24
Finished Jun 26 06:06:07 PM PDT 24
Peak memory 183164 kb
Host smart-4f63f39f-8ec9-4137-ba5d-6fab4ca0828e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287930138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.287930138
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.523142826
Short name T433
Test name
Test status
Simulation time 26687553930 ps
CPU time 44.44 seconds
Started Jun 26 06:02:16 PM PDT 24
Finished Jun 26 06:03:02 PM PDT 24
Peak memory 191944 kb
Host smart-3d0bd142-76e1-4c4d-a4cc-10f6615b9557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523142826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.523142826
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3806156310
Short name T162
Test name
Test status
Simulation time 3009438928418 ps
CPU time 1414.7 seconds
Started Jun 26 06:02:15 PM PDT 24
Finished Jun 26 06:25:51 PM PDT 24
Peak memory 191372 kb
Host smart-fa3aa9ed-e5bc-4645-b48b-54d06c6440b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806156310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3806156310
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3460702073
Short name T247
Test name
Test status
Simulation time 1599801645625 ps
CPU time 543.14 seconds
Started Jun 26 06:02:13 PM PDT 24
Finished Jun 26 06:11:16 PM PDT 24
Peak memory 183164 kb
Host smart-909a63b8-3eed-4ad9-b685-54a6676a0dbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460702073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3460702073
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1085067347
Short name T383
Test name
Test status
Simulation time 863177231808 ps
CPU time 356.69 seconds
Started Jun 26 06:02:16 PM PDT 24
Finished Jun 26 06:08:14 PM PDT 24
Peak memory 183148 kb
Host smart-3c020dd4-950d-4fca-9cfb-eea32e849d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085067347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1085067347
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2738312644
Short name T199
Test name
Test status
Simulation time 390830228732 ps
CPU time 782.92 seconds
Started Jun 26 06:02:13 PM PDT 24
Finished Jun 26 06:15:17 PM PDT 24
Peak memory 191348 kb
Host smart-551dd6d1-5b2a-401f-97be-aeb2e1f4c8cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738312644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2738312644
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1792083304
Short name T303
Test name
Test status
Simulation time 26671682974 ps
CPU time 41.37 seconds
Started Jun 26 06:02:15 PM PDT 24
Finished Jun 26 06:02:57 PM PDT 24
Peak memory 191384 kb
Host smart-f75bd749-2098-45c1-bd08-1edf8392aa5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792083304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1792083304
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4035900705
Short name T241
Test name
Test status
Simulation time 501099743106 ps
CPU time 278.41 seconds
Started Jun 26 06:01:30 PM PDT 24
Finished Jun 26 06:06:10 PM PDT 24
Peak memory 183148 kb
Host smart-9bd5c23f-d5c2-463f-a253-e5123a7651d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035900705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.4035900705
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2827481787
Short name T384
Test name
Test status
Simulation time 281326054197 ps
CPU time 107.53 seconds
Started Jun 26 06:01:30 PM PDT 24
Finished Jun 26 06:03:19 PM PDT 24
Peak memory 183188 kb
Host smart-81733cf7-4ba7-4920-b9d5-3b6e2c7ae1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827481787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2827481787
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1676912877
Short name T351
Test name
Test status
Simulation time 486136956301 ps
CPU time 261.36 seconds
Started Jun 26 06:01:34 PM PDT 24
Finished Jun 26 06:05:56 PM PDT 24
Peak memory 191188 kb
Host smart-938b5b7e-2bd0-4602-8d28-eaeaf830ccc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676912877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1676912877
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.795318911
Short name T335
Test name
Test status
Simulation time 2493637990169 ps
CPU time 1057.3 seconds
Started Jun 26 06:01:30 PM PDT 24
Finished Jun 26 06:19:10 PM PDT 24
Peak memory 191368 kb
Host smart-d64b3f88-470b-4fc3-9ca8-abeb12625bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795318911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.795318911
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.297071328
Short name T270
Test name
Test status
Simulation time 77092935468 ps
CPU time 166.55 seconds
Started Jun 26 06:02:13 PM PDT 24
Finished Jun 26 06:05:01 PM PDT 24
Peak memory 191348 kb
Host smart-83316254-8d88-404a-a7ed-ef4a46f14f29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297071328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.297071328
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2256680964
Short name T296
Test name
Test status
Simulation time 228857958433 ps
CPU time 111.62 seconds
Started Jun 26 06:02:19 PM PDT 24
Finished Jun 26 06:04:11 PM PDT 24
Peak memory 191340 kb
Host smart-6e5ac555-6aaa-47fd-a955-3ddfca355b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256680964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2256680964
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1880180310
Short name T207
Test name
Test status
Simulation time 165472638162 ps
CPU time 193.58 seconds
Started Jun 26 06:02:17 PM PDT 24
Finished Jun 26 06:05:31 PM PDT 24
Peak memory 191292 kb
Host smart-ed7dc1cf-7bb0-4f5d-be54-83e552297224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880180310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1880180310
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.404204732
Short name T76
Test name
Test status
Simulation time 35544334335 ps
CPU time 53.12 seconds
Started Jun 26 06:02:19 PM PDT 24
Finished Jun 26 06:03:13 PM PDT 24
Peak memory 183032 kb
Host smart-df3faf3a-7844-4404-b671-0b3531cfa46f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404204732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.404204732
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.3507963649
Short name T323
Test name
Test status
Simulation time 237858716966 ps
CPU time 586.12 seconds
Started Jun 26 06:02:13 PM PDT 24
Finished Jun 26 06:12:00 PM PDT 24
Peak memory 191364 kb
Host smart-bd4413e0-3204-4034-82a8-e05a685c80f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507963649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3507963649
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1807868343
Short name T232
Test name
Test status
Simulation time 377557201363 ps
CPU time 370.34 seconds
Started Jun 26 06:02:14 PM PDT 24
Finished Jun 26 06:08:25 PM PDT 24
Peak memory 191332 kb
Host smart-3e1f2efc-6f19-4792-bb20-a368578460d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807868343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1807868343
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.319344611
Short name T269
Test name
Test status
Simulation time 124667575810 ps
CPU time 282.53 seconds
Started Jun 26 06:02:17 PM PDT 24
Finished Jun 26 06:07:00 PM PDT 24
Peak memory 191284 kb
Host smart-1c337ddd-0415-4af9-af72-6609464f8438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319344611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.319344611
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1005592691
Short name T345
Test name
Test status
Simulation time 1445026245900 ps
CPU time 1011.72 seconds
Started Jun 26 06:02:16 PM PDT 24
Finished Jun 26 06:19:09 PM PDT 24
Peak memory 191356 kb
Host smart-7b7ca27d-ef5d-4b1b-a768-2e6fc39ab59d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005592691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1005592691
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.312573772
Short name T226
Test name
Test status
Simulation time 43606956076 ps
CPU time 63.13 seconds
Started Jun 26 06:01:35 PM PDT 24
Finished Jun 26 06:02:39 PM PDT 24
Peak memory 183152 kb
Host smart-eec859cd-2420-4f1d-800e-c75915f1139e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312573772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.312573772
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2536253812
Short name T394
Test name
Test status
Simulation time 8782024826 ps
CPU time 2.38 seconds
Started Jun 26 06:01:30 PM PDT 24
Finished Jun 26 06:01:34 PM PDT 24
Peak memory 183060 kb
Host smart-3fe8ed9f-8814-4716-a974-9b50aa9f2c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536253812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2536253812
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3484859711
Short name T129
Test name
Test status
Simulation time 361653296272 ps
CPU time 197.12 seconds
Started Jun 26 06:01:35 PM PDT 24
Finished Jun 26 06:04:53 PM PDT 24
Peak memory 191352 kb
Host smart-4145dc7d-3917-42eb-ae74-a7ff0910fbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484859711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3484859711
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3379684133
Short name T2
Test name
Test status
Simulation time 11639815573 ps
CPU time 37.91 seconds
Started Jun 26 06:01:30 PM PDT 24
Finished Jun 26 06:02:10 PM PDT 24
Peak memory 183148 kb
Host smart-9a6058ea-b9b8-4b24-9ca7-146d7ae28695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379684133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3379684133
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2705433122
Short name T70
Test name
Test status
Simulation time 336751249907 ps
CPU time 495.01 seconds
Started Jun 26 06:01:30 PM PDT 24
Finished Jun 26 06:09:47 PM PDT 24
Peak memory 191280 kb
Host smart-84c47cda-ce27-4b77-a22b-2cb72449b706
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705433122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2705433122
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.365412101
Short name T120
Test name
Test status
Simulation time 27613164643 ps
CPU time 23.4 seconds
Started Jun 26 06:02:13 PM PDT 24
Finished Jun 26 06:02:37 PM PDT 24
Peak memory 191356 kb
Host smart-28525982-55e1-4d52-ab08-10781c69ffa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365412101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.365412101
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1196937889
Short name T263
Test name
Test status
Simulation time 1274986184555 ps
CPU time 651.66 seconds
Started Jun 26 06:02:23 PM PDT 24
Finished Jun 26 06:13:15 PM PDT 24
Peak memory 191248 kb
Host smart-c1df8def-34a0-4ce6-8293-019193402e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196937889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1196937889
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2253759347
Short name T285
Test name
Test status
Simulation time 77018494144 ps
CPU time 332.77 seconds
Started Jun 26 06:02:24 PM PDT 24
Finished Jun 26 06:07:58 PM PDT 24
Peak memory 191368 kb
Host smart-de07c208-86fb-415e-951d-9cde24098b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253759347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2253759347
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1246497370
Short name T409
Test name
Test status
Simulation time 83604642437 ps
CPU time 65.68 seconds
Started Jun 26 06:02:24 PM PDT 24
Finished Jun 26 06:03:31 PM PDT 24
Peak memory 183128 kb
Host smart-e0c84fce-ac6f-4895-9cc5-cb1bc6106de5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246497370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1246497370
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.115533735
Short name T420
Test name
Test status
Simulation time 274459767 ps
CPU time 0.99 seconds
Started Jun 26 06:02:25 PM PDT 24
Finished Jun 26 06:02:27 PM PDT 24
Peak memory 182952 kb
Host smart-be277ed7-9a7d-47e9-8eb4-bf7e76321882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115533735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.115533735
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2461842522
Short name T148
Test name
Test status
Simulation time 136186674737 ps
CPU time 460.34 seconds
Started Jun 26 06:03:01 PM PDT 24
Finished Jun 26 06:10:43 PM PDT 24
Peak memory 194916 kb
Host smart-9181e31f-2105-46df-871d-a0671ce751cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461842522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2461842522
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3862152247
Short name T228
Test name
Test status
Simulation time 181818311183 ps
CPU time 228.26 seconds
Started Jun 26 06:02:24 PM PDT 24
Finished Jun 26 06:06:14 PM PDT 24
Peak memory 191364 kb
Host smart-595af637-3d97-4439-87ca-3b82edfd1fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862152247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3862152247
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.943291203
Short name T220
Test name
Test status
Simulation time 276245478965 ps
CPU time 150.17 seconds
Started Jun 26 06:02:24 PM PDT 24
Finished Jun 26 06:04:56 PM PDT 24
Peak memory 191308 kb
Host smart-5b521d5f-b81c-4b51-b180-75c5d0fdc014
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943291203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.943291203
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1072132471
Short name T227
Test name
Test status
Simulation time 17765190890 ps
CPU time 32.06 seconds
Started Jun 26 06:01:31 PM PDT 24
Finished Jun 26 06:02:05 PM PDT 24
Peak memory 183128 kb
Host smart-5043a045-cf6a-429f-9967-9a213b44e617
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072132471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1072132471
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1965033733
Short name T434
Test name
Test status
Simulation time 43528679668 ps
CPU time 58.63 seconds
Started Jun 26 06:01:31 PM PDT 24
Finished Jun 26 06:02:31 PM PDT 24
Peak memory 183080 kb
Host smart-58ea9a99-801c-4cc8-b98a-c6f35a907ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965033733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1965033733
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.166373118
Short name T389
Test name
Test status
Simulation time 384254668 ps
CPU time 3.25 seconds
Started Jun 26 06:01:29 PM PDT 24
Finished Jun 26 06:01:34 PM PDT 24
Peak memory 183124 kb
Host smart-13354479-b87f-4768-8f8e-5219fa4d94c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166373118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.166373118
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1717735485
Short name T391
Test name
Test status
Simulation time 239309302988 ps
CPU time 162.43 seconds
Started Jun 26 06:01:40 PM PDT 24
Finished Jun 26 06:04:24 PM PDT 24
Peak memory 183104 kb
Host smart-1f8de085-6fd1-49c6-bf2a-1c3cf9e06d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717735485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1717735485
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.1975171471
Short name T336
Test name
Test status
Simulation time 722374849094 ps
CPU time 433.76 seconds
Started Jun 26 06:02:25 PM PDT 24
Finished Jun 26 06:09:40 PM PDT 24
Peak memory 191348 kb
Host smart-0c58a10c-0caf-4646-88ec-52163684c2a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975171471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1975171471
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1690869481
Short name T454
Test name
Test status
Simulation time 328078193890 ps
CPU time 1399.12 seconds
Started Jun 26 06:02:25 PM PDT 24
Finished Jun 26 06:25:45 PM PDT 24
Peak memory 191352 kb
Host smart-5c182954-02da-4fc7-a8be-c9e04be58566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690869481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1690869481
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.419812538
Short name T160
Test name
Test status
Simulation time 34660837722 ps
CPU time 59.87 seconds
Started Jun 26 06:02:34 PM PDT 24
Finished Jun 26 06:03:35 PM PDT 24
Peak memory 191312 kb
Host smart-68393d16-3963-40dc-bfa4-70740242f85e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419812538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.419812538
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2663067082
Short name T130
Test name
Test status
Simulation time 216293094376 ps
CPU time 1355.28 seconds
Started Jun 26 06:02:34 PM PDT 24
Finished Jun 26 06:25:11 PM PDT 24
Peak memory 191364 kb
Host smart-ab1051f5-6963-4323-a7c3-30141bc30a14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663067082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2663067082
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3057063253
Short name T243
Test name
Test status
Simulation time 108032721454 ps
CPU time 164.18 seconds
Started Jun 26 06:02:32 PM PDT 24
Finished Jun 26 06:05:18 PM PDT 24
Peak memory 191292 kb
Host smart-0ed96fe0-dd56-448d-ba26-62c51934e48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057063253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3057063253
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2134464318
Short name T116
Test name
Test status
Simulation time 498335273516 ps
CPU time 188.5 seconds
Started Jun 26 06:02:33 PM PDT 24
Finished Jun 26 06:05:43 PM PDT 24
Peak memory 191320 kb
Host smart-d68a6e87-9f3c-4362-abbd-91dac32efb33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134464318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2134464318
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2905225710
Short name T246
Test name
Test status
Simulation time 431464161605 ps
CPU time 165.18 seconds
Started Jun 26 06:01:44 PM PDT 24
Finished Jun 26 06:04:30 PM PDT 24
Peak memory 183140 kb
Host smart-5ee2810d-68b2-49aa-9920-d1d811f886b5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905225710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2905225710
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2988987614
Short name T392
Test name
Test status
Simulation time 47260321471 ps
CPU time 38.89 seconds
Started Jun 26 06:01:38 PM PDT 24
Finished Jun 26 06:02:18 PM PDT 24
Peak memory 183168 kb
Host smart-8bd27a1e-d35b-43b3-b848-b4aae9a69b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988987614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2988987614
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3741435134
Short name T352
Test name
Test status
Simulation time 12290352015 ps
CPU time 13.47 seconds
Started Jun 26 06:01:40 PM PDT 24
Finished Jun 26 06:01:55 PM PDT 24
Peak memory 183160 kb
Host smart-ab7fca61-b887-4ac7-86fd-50e04f08b66b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741435134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3741435134
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3987586965
Short name T159
Test name
Test status
Simulation time 19260553778 ps
CPU time 723.97 seconds
Started Jun 26 06:01:36 PM PDT 24
Finished Jun 26 06:13:41 PM PDT 24
Peak memory 183088 kb
Host smart-0d985fa4-cb7b-40b2-b0c3-792d85c7353f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987586965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3987586965
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2123883850
Short name T436
Test name
Test status
Simulation time 63624582 ps
CPU time 0.66 seconds
Started Jun 26 06:01:37 PM PDT 24
Finished Jun 26 06:01:38 PM PDT 24
Peak memory 182972 kb
Host smart-b246a8f6-8897-4d0f-b340-4bef7c0a238c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123883850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2123883850
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2991987512
Short name T175
Test name
Test status
Simulation time 25148379791 ps
CPU time 16.25 seconds
Started Jun 26 06:02:34 PM PDT 24
Finished Jun 26 06:02:52 PM PDT 24
Peak memory 183156 kb
Host smart-412974be-a4f6-4cc6-b3df-fbed6e2e8775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991987512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2991987512
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3273079442
Short name T324
Test name
Test status
Simulation time 221892489776 ps
CPU time 132.18 seconds
Started Jun 26 06:02:34 PM PDT 24
Finished Jun 26 06:04:47 PM PDT 24
Peak memory 191336 kb
Host smart-8151b961-0aba-4c72-bae4-08028092bccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273079442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3273079442
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3536708787
Short name T350
Test name
Test status
Simulation time 49823365362 ps
CPU time 79.96 seconds
Started Jun 26 06:02:37 PM PDT 24
Finished Jun 26 06:03:58 PM PDT 24
Peak memory 191328 kb
Host smart-faaefec4-2564-4fab-aad4-202c659439b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536708787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3536708787
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2918269306
Short name T295
Test name
Test status
Simulation time 215572440761 ps
CPU time 231.2 seconds
Started Jun 26 06:02:34 PM PDT 24
Finished Jun 26 06:06:26 PM PDT 24
Peak memory 191360 kb
Host smart-18aaeb05-513c-413b-b303-58a9a96bedd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918269306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2918269306
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2191568988
Short name T415
Test name
Test status
Simulation time 117693333488 ps
CPU time 103.25 seconds
Started Jun 26 06:02:33 PM PDT 24
Finished Jun 26 06:04:17 PM PDT 24
Peak memory 191340 kb
Host smart-b6034ab4-cc44-45ed-9a03-b7802ae3de4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191568988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2191568988
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.945493820
Short name T229
Test name
Test status
Simulation time 553621172957 ps
CPU time 361.27 seconds
Started Jun 26 06:02:32 PM PDT 24
Finished Jun 26 06:08:35 PM PDT 24
Peak memory 191340 kb
Host smart-77c0d7df-8989-49e7-a816-bcb7f0ce87c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945493820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.945493820
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3496217078
Short name T449
Test name
Test status
Simulation time 114964250551 ps
CPU time 117.86 seconds
Started Jun 26 06:02:34 PM PDT 24
Finished Jun 26 06:04:33 PM PDT 24
Peak memory 191260 kb
Host smart-3e787a93-c4ed-4d47-bdf0-5e0575762a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496217078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3496217078
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.4027430326
Short name T440
Test name
Test status
Simulation time 318979058250 ps
CPU time 42.47 seconds
Started Jun 26 06:02:39 PM PDT 24
Finished Jun 26 06:03:23 PM PDT 24
Peak memory 183372 kb
Host smart-b4f209be-4d59-45b6-9a9f-394bf51eb4d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027430326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4027430326
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.100815104
Short name T47
Test name
Test status
Simulation time 255818974287 ps
CPU time 101.63 seconds
Started Jun 26 06:02:37 PM PDT 24
Finished Jun 26 06:04:20 PM PDT 24
Peak memory 193552 kb
Host smart-6aa5a120-2d2a-4c87-9e3c-540a36cae0d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100815104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.100815104
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.474616506
Short name T172
Test name
Test status
Simulation time 131767449241 ps
CPU time 120.43 seconds
Started Jun 26 06:01:37 PM PDT 24
Finished Jun 26 06:03:39 PM PDT 24
Peak memory 183164 kb
Host smart-d1ed2945-db35-4184-9e92-b7f271208b4f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474616506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.474616506
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2973393549
Short name T451
Test name
Test status
Simulation time 217589318256 ps
CPU time 144.7 seconds
Started Jun 26 06:01:36 PM PDT 24
Finished Jun 26 06:04:02 PM PDT 24
Peak memory 183096 kb
Host smart-465eeccf-0263-44e3-b587-145641bc8fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973393549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2973393549
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.4272145453
Short name T184
Test name
Test status
Simulation time 180607533902 ps
CPU time 224.92 seconds
Started Jun 26 06:01:39 PM PDT 24
Finished Jun 26 06:05:26 PM PDT 24
Peak memory 193752 kb
Host smart-45c9bcc8-cfdc-4c57-b976-323cd3481a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272145453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.4272145453
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1790772022
Short name T385
Test name
Test status
Simulation time 276103757 ps
CPU time 1.11 seconds
Started Jun 26 06:01:41 PM PDT 24
Finished Jun 26 06:01:44 PM PDT 24
Peak memory 182976 kb
Host smart-173b1530-bf2f-449a-8e57-6ac1680c0959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790772022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1790772022
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.3188460066
Short name T114
Test name
Test status
Simulation time 337295413024 ps
CPU time 176.1 seconds
Started Jun 26 06:02:39 PM PDT 24
Finished Jun 26 06:05:37 PM PDT 24
Peak memory 191344 kb
Host smart-14e041f2-1d0b-4202-98ba-940906f30497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188460066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3188460066
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1984162798
Short name T312
Test name
Test status
Simulation time 216110061620 ps
CPU time 171.39 seconds
Started Jun 26 06:02:39 PM PDT 24
Finished Jun 26 06:05:31 PM PDT 24
Peak memory 191356 kb
Host smart-7c2d9033-8f42-4b75-baad-b882b93f8ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984162798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1984162798
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.270214885
Short name T133
Test name
Test status
Simulation time 221310275084 ps
CPU time 196.39 seconds
Started Jun 26 06:02:41 PM PDT 24
Finished Jun 26 06:05:59 PM PDT 24
Peak memory 193584 kb
Host smart-6e072cb7-662a-4716-b74a-dbb8698989c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270214885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.270214885
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3703515998
Short name T244
Test name
Test status
Simulation time 49192687463 ps
CPU time 87.74 seconds
Started Jun 26 06:02:41 PM PDT 24
Finished Jun 26 06:04:10 PM PDT 24
Peak memory 183112 kb
Host smart-ec1a1f9a-454f-4fd4-b593-0ee01d2f7841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703515998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3703515998
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1980795601
Short name T238
Test name
Test status
Simulation time 157843594680 ps
CPU time 237.67 seconds
Started Jun 26 06:02:40 PM PDT 24
Finished Jun 26 06:06:39 PM PDT 24
Peak memory 191336 kb
Host smart-b5f60cd1-03d7-4976-98aa-916ee8222a88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980795601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1980795601
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.17847222
Short name T169
Test name
Test status
Simulation time 294666153394 ps
CPU time 279.7 seconds
Started Jun 26 06:02:39 PM PDT 24
Finished Jun 26 06:07:21 PM PDT 24
Peak memory 191344 kb
Host smart-e23c1879-c380-422c-9996-13ca13a8b24d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17847222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.17847222
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.118474168
Short name T216
Test name
Test status
Simulation time 20582504687 ps
CPU time 30.34 seconds
Started Jun 26 06:02:42 PM PDT 24
Finished Jun 26 06:03:14 PM PDT 24
Peak memory 191292 kb
Host smart-c974366b-64ae-42f8-ba08-5d1d34c08565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118474168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.118474168
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2966521177
Short name T318
Test name
Test status
Simulation time 152602822760 ps
CPU time 68.92 seconds
Started Jun 26 06:02:39 PM PDT 24
Finished Jun 26 06:03:50 PM PDT 24
Peak memory 183136 kb
Host smart-e1f4fd76-bbab-4e16-9907-576cd640ef62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966521177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2966521177
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3744590205
Short name T362
Test name
Test status
Simulation time 409224362949 ps
CPU time 311.16 seconds
Started Jun 26 06:02:40 PM PDT 24
Finished Jun 26 06:07:53 PM PDT 24
Peak memory 183168 kb
Host smart-acd02340-c7b3-4c05-bbec-4bc9f9e3dcac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744590205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3744590205
Directory /workspace/99.rv_timer_random/latest
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