Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T504 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3665693147 Jun 27 05:58:43 PM PDT 24 Jun 27 05:58:49 PM PDT 24 561098199 ps
T505 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.58377858 Jun 27 05:58:38 PM PDT 24 Jun 27 05:58:41 PM PDT 24 1096513514 ps
T506 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4213036893 Jun 27 05:59:12 PM PDT 24 Jun 27 05:59:17 PM PDT 24 28947248 ps
T507 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.67618581 Jun 27 05:59:11 PM PDT 24 Jun 27 05:59:13 PM PDT 24 18410277 ps
T508 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1225757733 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:44 PM PDT 24 13258563 ps
T509 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1439275800 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:42 PM PDT 24 16800876 ps
T510 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1739210698 Jun 27 05:59:10 PM PDT 24 Jun 27 05:59:12 PM PDT 24 36859711 ps
T511 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.908903100 Jun 27 05:58:41 PM PDT 24 Jun 27 05:58:46 PM PDT 24 84666828 ps
T512 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1361230889 Jun 27 05:58:46 PM PDT 24 Jun 27 05:58:50 PM PDT 24 15381206 ps
T513 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.16973447 Jun 27 05:58:21 PM PDT 24 Jun 27 05:58:23 PM PDT 24 23932978 ps
T514 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3348142674 Jun 27 05:59:10 PM PDT 24 Jun 27 05:59:13 PM PDT 24 130385083 ps
T515 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.359187713 Jun 27 05:58:38 PM PDT 24 Jun 27 05:58:41 PM PDT 24 386491269 ps
T72 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.209075557 Jun 27 05:58:17 PM PDT 24 Jun 27 05:58:21 PM PDT 24 120771337 ps
T516 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1744157780 Jun 27 05:58:16 PM PDT 24 Jun 27 05:58:18 PM PDT 24 49643426 ps
T517 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2956020392 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:44 PM PDT 24 205108221 ps
T518 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1488158121 Jun 27 05:59:12 PM PDT 24 Jun 27 05:59:17 PM PDT 24 34832723 ps
T519 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2956802602 Jun 27 05:58:41 PM PDT 24 Jun 27 05:58:46 PM PDT 24 93726352 ps
T520 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.319495301 Jun 27 05:58:19 PM PDT 24 Jun 27 05:58:22 PM PDT 24 63490153 ps
T521 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2127749370 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:42 PM PDT 24 134854966 ps
T522 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3835575211 Jun 27 05:58:40 PM PDT 24 Jun 27 05:58:44 PM PDT 24 20383115 ps
T523 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1644244073 Jun 27 05:58:40 PM PDT 24 Jun 27 05:58:46 PM PDT 24 33826095 ps
T73 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2639861880 Jun 27 05:58:40 PM PDT 24 Jun 27 05:58:45 PM PDT 24 14477488 ps
T524 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1961928604 Jun 27 05:59:11 PM PDT 24 Jun 27 05:59:15 PM PDT 24 13403581 ps
T525 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1667152317 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:44 PM PDT 24 28382904 ps
T526 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2336063110 Jun 27 05:58:45 PM PDT 24 Jun 27 05:58:49 PM PDT 24 66763157 ps
T527 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3923360087 Jun 27 05:58:40 PM PDT 24 Jun 27 05:58:44 PM PDT 24 37255736 ps
T528 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.406923383 Jun 27 05:59:08 PM PDT 24 Jun 27 05:59:09 PM PDT 24 24391306 ps
T529 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2565353760 Jun 27 05:58:22 PM PDT 24 Jun 27 05:58:24 PM PDT 24 149435755 ps
T530 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3225081366 Jun 27 05:59:11 PM PDT 24 Jun 27 05:59:15 PM PDT 24 12765438 ps
T531 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2042423354 Jun 27 05:58:40 PM PDT 24 Jun 27 05:58:45 PM PDT 24 52023560 ps
T532 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3291673323 Jun 27 05:58:41 PM PDT 24 Jun 27 05:58:46 PM PDT 24 52160458 ps
T533 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2586465502 Jun 27 05:59:11 PM PDT 24 Jun 27 05:59:14 PM PDT 24 14341446 ps
T534 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.88489771 Jun 27 05:58:40 PM PDT 24 Jun 27 05:58:45 PM PDT 24 85533523 ps
T535 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.87761314 Jun 27 05:59:11 PM PDT 24 Jun 27 05:59:14 PM PDT 24 30933904 ps
T536 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2029437374 Jun 27 05:58:42 PM PDT 24 Jun 27 05:58:49 PM PDT 24 277913993 ps
T537 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3256083271 Jun 27 05:58:38 PM PDT 24 Jun 27 05:58:41 PM PDT 24 34020564 ps
T538 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4204708513 Jun 27 05:58:16 PM PDT 24 Jun 27 05:58:18 PM PDT 24 46314565 ps
T539 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2054849645 Jun 27 05:58:41 PM PDT 24 Jun 27 05:58:47 PM PDT 24 170009447 ps
T540 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.945864070 Jun 27 05:59:13 PM PDT 24 Jun 27 05:59:21 PM PDT 24 391903808 ps
T541 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1872903655 Jun 27 05:59:10 PM PDT 24 Jun 27 05:59:13 PM PDT 24 162017947 ps
T542 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.815130684 Jun 27 05:59:12 PM PDT 24 Jun 27 05:59:18 PM PDT 24 120356862 ps
T543 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.966313222 Jun 27 05:59:13 PM PDT 24 Jun 27 05:59:20 PM PDT 24 18818013 ps
T544 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4098967243 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:44 PM PDT 24 178068162 ps
T545 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.91563886 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:45 PM PDT 24 627090667 ps
T546 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4243755101 Jun 27 05:58:21 PM PDT 24 Jun 27 05:58:23 PM PDT 24 26979796 ps
T547 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1762696351 Jun 27 05:58:40 PM PDT 24 Jun 27 05:58:47 PM PDT 24 564541763 ps
T548 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3378250222 Jun 27 05:58:40 PM PDT 24 Jun 27 05:58:45 PM PDT 24 182564841 ps
T549 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1115567638 Jun 27 05:58:41 PM PDT 24 Jun 27 05:58:47 PM PDT 24 28286068 ps
T550 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3414228778 Jun 27 05:59:13 PM PDT 24 Jun 27 05:59:20 PM PDT 24 26769812 ps
T551 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1390542338 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:43 PM PDT 24 43921970 ps
T552 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3926234878 Jun 27 05:58:16 PM PDT 24 Jun 27 05:58:17 PM PDT 24 16815464 ps
T553 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3482273493 Jun 27 05:58:42 PM PDT 24 Jun 27 05:58:50 PM PDT 24 310200494 ps
T554 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1763349527 Jun 27 05:58:19 PM PDT 24 Jun 27 05:58:22 PM PDT 24 955048312 ps
T555 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.31680902 Jun 27 05:59:12 PM PDT 24 Jun 27 05:59:18 PM PDT 24 34933156 ps
T556 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2938961328 Jun 27 05:58:42 PM PDT 24 Jun 27 05:58:47 PM PDT 24 18235418 ps
T557 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.483720442 Jun 27 05:58:17 PM PDT 24 Jun 27 05:58:20 PM PDT 24 76857288 ps
T558 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3250475835 Jun 27 05:59:12 PM PDT 24 Jun 27 05:59:16 PM PDT 24 23931389 ps
T559 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3825601388 Jun 27 05:59:10 PM PDT 24 Jun 27 05:59:13 PM PDT 24 28243470 ps
T560 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2695351994 Jun 27 05:59:12 PM PDT 24 Jun 27 05:59:18 PM PDT 24 28973675 ps
T561 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1070127096 Jun 27 05:58:36 PM PDT 24 Jun 27 05:58:38 PM PDT 24 14087873 ps
T562 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2220493800 Jun 27 05:59:14 PM PDT 24 Jun 27 05:59:22 PM PDT 24 54991907 ps
T563 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1676855198 Jun 27 05:59:13 PM PDT 24 Jun 27 05:59:22 PM PDT 24 114598001 ps
T564 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1240062628 Jun 27 05:59:18 PM PDT 24 Jun 27 05:59:29 PM PDT 24 47408995 ps
T565 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1061123741 Jun 27 05:58:19 PM PDT 24 Jun 27 05:58:21 PM PDT 24 75971528 ps
T566 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1579058646 Jun 27 05:59:11 PM PDT 24 Jun 27 05:59:14 PM PDT 24 16483332 ps
T567 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2305486975 Jun 27 05:59:13 PM PDT 24 Jun 27 05:59:21 PM PDT 24 31330586 ps
T568 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1057131311 Jun 27 05:58:16 PM PDT 24 Jun 27 05:58:18 PM PDT 24 14503357 ps
T569 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2332499151 Jun 27 05:58:41 PM PDT 24 Jun 27 05:58:47 PM PDT 24 234037336 ps
T570 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3194609673 Jun 27 05:59:12 PM PDT 24 Jun 27 05:59:17 PM PDT 24 29482850 ps
T571 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.655192935 Jun 27 05:58:20 PM PDT 24 Jun 27 05:58:24 PM PDT 24 61771685 ps
T572 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.711709475 Jun 27 05:59:11 PM PDT 24 Jun 27 05:59:15 PM PDT 24 54146727 ps
T573 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2063100456 Jun 27 05:59:09 PM PDT 24 Jun 27 05:59:12 PM PDT 24 19386014 ps
T574 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.909092200 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:44 PM PDT 24 148298042 ps
T575 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3486668864 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:43 PM PDT 24 49921710 ps
T576 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2598609396 Jun 27 05:58:38 PM PDT 24 Jun 27 05:58:40 PM PDT 24 33776556 ps
T577 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1734694050 Jun 27 05:58:42 PM PDT 24 Jun 27 05:58:47 PM PDT 24 196854179 ps
T578 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2635649357 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:43 PM PDT 24 11950321 ps
T74 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2301028252 Jun 27 05:58:39 PM PDT 24 Jun 27 05:58:42 PM PDT 24 15605594 ps
T579 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3166611305 Jun 27 05:59:12 PM PDT 24 Jun 27 05:59:18 PM PDT 24 74619520 ps
T580 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.757679531 Jun 27 05:58:41 PM PDT 24 Jun 27 05:58:46 PM PDT 24 93589053 ps

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.569971699
Short name T2
Test name
Test status
Simulation time 24353353612 ps
CPU time 77.61 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:00:50 PM PDT 24
Peak memory 197824 kb
Host smart-43436219-5509-4897-ba65-b3552f32591d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569971699 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.569971699
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2703663552
Short name T10
Test name
Test status
Simulation time 298572092340 ps
CPU time 471.71 seconds
Started Jun 27 05:59:46 PM PDT 24
Finished Jun 27 06:07:43 PM PDT 24
Peak memory 191344 kb
Host smart-6bfe5d2f-bd1f-4844-b97f-29dfd21d6e87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703663552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2703663552
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2809283950
Short name T92
Test name
Test status
Simulation time 601688676814 ps
CPU time 1780.01 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:29:06 PM PDT 24
Peak memory 191196 kb
Host smart-90a3c270-7152-4e7a-afa8-cd5253f9040c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809283950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2809283950
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.357155978
Short name T25
Test name
Test status
Simulation time 129042967 ps
CPU time 1.35 seconds
Started Jun 27 05:58:17 PM PDT 24
Finished Jun 27 05:58:20 PM PDT 24
Peak memory 182856 kb
Host smart-2296ae75-33d7-4ce5-8083-94cbb43f6ab2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357155978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.357155978
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1592087566
Short name T97
Test name
Test status
Simulation time 2872744883679 ps
CPU time 1654.59 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 06:27:06 PM PDT 24
Peak memory 197412 kb
Host smart-2e45affb-3f2b-46f8-b1e3-4dd54f947ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592087566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1592087566
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.883017461
Short name T49
Test name
Test status
Simulation time 1958058130562 ps
CPU time 1506.12 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:24:38 PM PDT 24
Peak memory 196152 kb
Host smart-3c1d5b8b-0ea1-4b47-a8be-a1c34714ec78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883017461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
883017461
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.4201850035
Short name T32
Test name
Test status
Simulation time 110556764397 ps
CPU time 691.78 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:10:58 PM PDT 24
Peak memory 206056 kb
Host smart-8323c2a3-bdc7-48cd-9151-f3863edf1678
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201850035 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.4201850035
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.643401110
Short name T50
Test name
Test status
Simulation time 606658126396 ps
CPU time 1420.27 seconds
Started Jun 27 05:59:30 PM PDT 24
Finished Jun 27 06:23:20 PM PDT 24
Peak memory 191360 kb
Host smart-a3212447-fbb5-4a82-a8e3-73a34ddb2489
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643401110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
643401110
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.704701511
Short name T232
Test name
Test status
Simulation time 604453030887 ps
CPU time 4045.46 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 07:06:59 PM PDT 24
Peak memory 191348 kb
Host smart-5ca7b8fc-d75d-48f3-89f8-c5bc79e57b60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704701511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
704701511
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3986041203
Short name T57
Test name
Test status
Simulation time 787125176632 ps
CPU time 1901.09 seconds
Started Jun 27 05:59:29 PM PDT 24
Finished Jun 27 06:31:19 PM PDT 24
Peak memory 191292 kb
Host smart-7faa3793-3cc4-4c0e-847f-bf5c69649447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986041203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3986041203
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1037048884
Short name T208
Test name
Test status
Simulation time 1378551343436 ps
CPU time 1358.73 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:22:11 PM PDT 24
Peak memory 191360 kb
Host smart-9dc3a5b0-1557-4f3c-ab14-c9bd9e776067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037048884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1037048884
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1021981583
Short name T118
Test name
Test status
Simulation time 416993018089 ps
CPU time 1650.14 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 06:27:01 PM PDT 24
Peak memory 191552 kb
Host smart-9e882897-4182-430a-aa17-90554f2d0c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021981583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1021981583
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.230714830
Short name T15
Test name
Test status
Simulation time 88800446 ps
CPU time 0.91 seconds
Started Jun 27 05:59:14 PM PDT 24
Finished Jun 27 05:59:23 PM PDT 24
Peak memory 214500 kb
Host smart-b1af6aa9-5cf8-44c1-bd3c-9caec7509efc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230714830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.230714830
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/147.rv_timer_random.3608134351
Short name T138
Test name
Test status
Simulation time 125353265329 ps
CPU time 499.05 seconds
Started Jun 27 06:00:43 PM PDT 24
Finished Jun 27 06:09:04 PM PDT 24
Peak memory 194868 kb
Host smart-9366ac75-c110-44a3-a7b1-7b3ad424829c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608134351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3608134351
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.708713952
Short name T209
Test name
Test status
Simulation time 597520686613 ps
CPU time 723.43 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:12:15 PM PDT 24
Peak memory 191360 kb
Host smart-087eb2e7-1acb-4cd8-b301-60cbd9eff2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708713952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.708713952
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2464895531
Short name T224
Test name
Test status
Simulation time 823268529873 ps
CPU time 622.1 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:09:48 PM PDT 24
Peak memory 191364 kb
Host smart-28c7da86-fd12-4714-aa15-8dd9c77ec9a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464895531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2464895531
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3458934327
Short name T51
Test name
Test status
Simulation time 153134678660 ps
CPU time 435.11 seconds
Started Jun 27 05:59:28 PM PDT 24
Finished Jun 27 06:06:53 PM PDT 24
Peak memory 191100 kb
Host smart-4480ebf4-bdf7-4175-9288-58b1cd55ce35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458934327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3458934327
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/128.rv_timer_random.3825840779
Short name T19
Test name
Test status
Simulation time 532131888489 ps
CPU time 566.93 seconds
Started Jun 27 06:00:23 PM PDT 24
Finished Jun 27 06:09:52 PM PDT 24
Peak memory 191368 kb
Host smart-1c1c19c7-2e23-4887-81df-80c96e0dc76b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825840779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3825840779
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.834180122
Short name T131
Test name
Test status
Simulation time 99773837779 ps
CPU time 274.12 seconds
Started Jun 27 06:00:59 PM PDT 24
Finished Jun 27 06:05:35 PM PDT 24
Peak memory 191320 kb
Host smart-03b6b78c-fbe8-4217-a2c4-2344129f5680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834180122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.834180122
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.397488185
Short name T243
Test name
Test status
Simulation time 669090779395 ps
CPU time 2663.32 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:44:00 PM PDT 24
Peak memory 191360 kb
Host smart-d0b45a4a-c958-4ac9-8386-19447d1ccd76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397488185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
397488185
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/103.rv_timer_random.408122127
Short name T115
Test name
Test status
Simulation time 539561351440 ps
CPU time 496.77 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:08:28 PM PDT 24
Peak memory 191368 kb
Host smart-5c2b51b0-6cc4-48ac-8b91-23c73f1d4304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408122127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.408122127
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.179654753
Short name T140
Test name
Test status
Simulation time 135653187546 ps
CPU time 225.04 seconds
Started Jun 27 06:01:03 PM PDT 24
Finished Jun 27 06:04:49 PM PDT 24
Peak memory 191300 kb
Host smart-3c173dbc-2eda-4267-9c20-10aae1c74472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179654753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.179654753
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1397235868
Short name T6
Test name
Test status
Simulation time 2327320295986 ps
CPU time 1098.24 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:17:54 PM PDT 24
Peak memory 183152 kb
Host smart-cff7d091-efa5-44e2-944e-bbb41909fb6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397235868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1397235868
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2962049651
Short name T162
Test name
Test status
Simulation time 814662890757 ps
CPU time 881.34 seconds
Started Jun 27 05:59:28 PM PDT 24
Finished Jun 27 06:14:19 PM PDT 24
Peak memory 194508 kb
Host smart-2b5f0b2f-45fa-4dbd-9546-3fdea58c4511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962049651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2962049651
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.3617432425
Short name T95
Test name
Test status
Simulation time 167855279662 ps
CPU time 501.85 seconds
Started Jun 27 06:00:24 PM PDT 24
Finished Jun 27 06:08:47 PM PDT 24
Peak memory 191520 kb
Host smart-a349ed55-4a9d-4b19-a194-1c73d9722a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617432425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3617432425
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.1270586660
Short name T229
Test name
Test status
Simulation time 371568846459 ps
CPU time 2077.3 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:34:05 PM PDT 24
Peak memory 191348 kb
Host smart-29b3d294-d5af-4c63-9cdf-29c7c616e25b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270586660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1270586660
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3918316199
Short name T300
Test name
Test status
Simulation time 88820915747 ps
CPU time 265.29 seconds
Started Jun 27 06:00:41 PM PDT 24
Finished Jun 27 06:05:08 PM PDT 24
Peak memory 191384 kb
Host smart-840a6fe2-5363-4fd2-bcab-7eaeeb88f590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918316199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3918316199
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.602133595
Short name T90
Test name
Test status
Simulation time 1520556769466 ps
CPU time 1083.63 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:17:40 PM PDT 24
Peak memory 195700 kb
Host smart-49a496c3-d687-4ff4-bab9-422691cfc3c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602133595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
602133595
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.2314682016
Short name T251
Test name
Test status
Simulation time 284089673317 ps
CPU time 453.8 seconds
Started Jun 27 06:00:07 PM PDT 24
Finished Jun 27 06:07:43 PM PDT 24
Peak memory 191368 kb
Host smart-6e8fabae-e7d7-408c-8b6f-aae9f58bcb27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314682016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2314682016
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1894146652
Short name T216
Test name
Test status
Simulation time 507258793230 ps
CPU time 727.2 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:11:39 PM PDT 24
Peak memory 191364 kb
Host smart-42e15c29-0eb9-4573-ac2b-ccd98574cf6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894146652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1894146652
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.187011014
Short name T298
Test name
Test status
Simulation time 692826037873 ps
CPU time 1607.94 seconds
Started Jun 27 05:59:28 PM PDT 24
Finished Jun 27 06:26:26 PM PDT 24
Peak memory 191264 kb
Host smart-56bc1aeb-2677-4cc1-91f6-1b7f016e6207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187011014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
187011014
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_random.2668549288
Short name T145
Test name
Test status
Simulation time 535172474780 ps
CPU time 280.64 seconds
Started Jun 27 05:59:43 PM PDT 24
Finished Jun 27 06:04:26 PM PDT 24
Peak memory 191360 kb
Host smart-f3e84831-90c9-486b-bc86-a953a594056b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668549288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2668549288
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.660855127
Short name T47
Test name
Test status
Simulation time 6300616981442 ps
CPU time 1232.34 seconds
Started Jun 27 05:59:43 PM PDT 24
Finished Jun 27 06:20:18 PM PDT 24
Peak memory 190916 kb
Host smart-9a27dd52-2220-40bc-a4f2-102156a25f31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660855127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
660855127
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.971866275
Short name T132
Test name
Test status
Simulation time 797506116825 ps
CPU time 1102.16 seconds
Started Jun 27 06:00:07 PM PDT 24
Finished Jun 27 06:18:31 PM PDT 24
Peak memory 191360 kb
Host smart-443f902d-49a9-4f31-82e9-fc75fdd0ac5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971866275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.971866275
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1854136921
Short name T110
Test name
Test status
Simulation time 386813699544 ps
CPU time 586.13 seconds
Started Jun 27 05:59:14 PM PDT 24
Finished Jun 27 06:09:09 PM PDT 24
Peak memory 191288 kb
Host smart-22347627-c1fe-49e9-ab2d-96c39cd9d97e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854136921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1854136921
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.411007028
Short name T62
Test name
Test status
Simulation time 12202928 ps
CPU time 0.58 seconds
Started Jun 27 05:58:42 PM PDT 24
Finished Jun 27 05:58:48 PM PDT 24
Peak memory 191564 kb
Host smart-24be3ffc-f1e0-4c63-8935-c147d13dc1c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411007028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.411007028
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/115.rv_timer_random.3375754555
Short name T184
Test name
Test status
Simulation time 221414599404 ps
CPU time 235.92 seconds
Started Jun 27 06:00:25 PM PDT 24
Finished Jun 27 06:04:23 PM PDT 24
Peak memory 191352 kb
Host smart-2db0ee81-c688-4183-a76c-103c9f66a117
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375754555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3375754555
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.4016629561
Short name T250
Test name
Test status
Simulation time 566790272476 ps
CPU time 224.41 seconds
Started Jun 27 06:00:42 PM PDT 24
Finished Jun 27 06:04:28 PM PDT 24
Peak memory 191360 kb
Host smart-639bf83d-5ca0-4da1-a03c-83edf8a8c75b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016629561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4016629561
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2868240418
Short name T332
Test name
Test status
Simulation time 4140463959778 ps
CPU time 1743.48 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:28:40 PM PDT 24
Peak memory 191376 kb
Host smart-368813b9-b6bf-4eee-b46f-490df9de6a9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868240418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2868240418
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/64.rv_timer_random.1787425802
Short name T239
Test name
Test status
Simulation time 2193563702552 ps
CPU time 476.45 seconds
Started Jun 27 06:00:08 PM PDT 24
Finished Jun 27 06:08:06 PM PDT 24
Peak memory 191360 kb
Host smart-e9685281-691c-47c0-9e0d-0e57c888e829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787425802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1787425802
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3169922236
Short name T434
Test name
Test status
Simulation time 428816693297 ps
CPU time 207.83 seconds
Started Jun 27 06:00:07 PM PDT 24
Finished Jun 27 06:03:37 PM PDT 24
Peak memory 194724 kb
Host smart-7508f128-50bc-4df8-a6e1-42850b47ebd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169922236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3169922236
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1905694463
Short name T164
Test name
Test status
Simulation time 159794667405 ps
CPU time 495.18 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:08:27 PM PDT 24
Peak memory 191368 kb
Host smart-ae3b80e8-353b-4f23-ac4e-b3951a9849d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905694463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1905694463
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3504868086
Short name T37
Test name
Test status
Simulation time 173924964376 ps
CPU time 491.87 seconds
Started Jun 27 06:00:11 PM PDT 24
Finished Jun 27 06:08:25 PM PDT 24
Peak memory 194412 kb
Host smart-7788ff95-2b51-4780-be53-ea6cef9a87e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504868086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3504868086
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1626612701
Short name T100
Test name
Test status
Simulation time 144839213575 ps
CPU time 238.55 seconds
Started Jun 27 06:00:10 PM PDT 24
Finished Jun 27 06:04:11 PM PDT 24
Peak memory 191368 kb
Host smart-7c5c4628-5fb8-47c4-a57a-230dfc41d36b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626612701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1626612701
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.326797002
Short name T290
Test name
Test status
Simulation time 316230525785 ps
CPU time 330.98 seconds
Started Jun 27 06:00:41 PM PDT 24
Finished Jun 27 06:06:15 PM PDT 24
Peak memory 191376 kb
Host smart-43c39ae0-ab09-4629-933f-e95ca8d66cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326797002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.326797002
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4135420781
Short name T317
Test name
Test status
Simulation time 690365423182 ps
CPU time 852.69 seconds
Started Jun 27 06:00:43 PM PDT 24
Finished Jun 27 06:14:58 PM PDT 24
Peak memory 191312 kb
Host smart-681adcf8-5ad6-4680-8072-43b12bba4119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135420781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4135420781
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.4119304971
Short name T222
Test name
Test status
Simulation time 200197009457 ps
CPU time 352.51 seconds
Started Jun 27 05:59:35 PM PDT 24
Finished Jun 27 06:05:33 PM PDT 24
Peak memory 191372 kb
Host smart-07edf7c2-027d-473b-80f7-43b990495f85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119304971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.4119304971
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1804127228
Short name T225
Test name
Test status
Simulation time 1596068549066 ps
CPU time 1586.41 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:25:53 PM PDT 24
Peak memory 196052 kb
Host smart-c2ee08fa-6da4-4324-87a1-b13a00659623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804127228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1804127228
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/55.rv_timer_random.2388304892
Short name T157
Test name
Test status
Simulation time 912344413112 ps
CPU time 667.85 seconds
Started Jun 27 06:00:10 PM PDT 24
Finished Jun 27 06:11:21 PM PDT 24
Peak memory 191360 kb
Host smart-2b888602-9a9f-4ac9-8804-e3c4f121493d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388304892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2388304892
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1689036551
Short name T281
Test name
Test status
Simulation time 86925057657 ps
CPU time 459.21 seconds
Started Jun 27 06:00:07 PM PDT 24
Finished Jun 27 06:07:48 PM PDT 24
Peak memory 191360 kb
Host smart-4cb76949-1452-43f7-80a1-e143bb384666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689036551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1689036551
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3129938832
Short name T313
Test name
Test status
Simulation time 757090765617 ps
CPU time 789.95 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:13:21 PM PDT 24
Peak memory 191356 kb
Host smart-d8f348df-03e7-4296-bfde-56cc5693bf91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129938832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3129938832
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.236188553
Short name T21
Test name
Test status
Simulation time 155140459841 ps
CPU time 1992.84 seconds
Started Jun 27 06:00:11 PM PDT 24
Finished Jun 27 06:33:26 PM PDT 24
Peak memory 191332 kb
Host smart-5415332c-ae09-407d-800e-aec1bd2dfa8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236188553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.236188553
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.197623471
Short name T127
Test name
Test status
Simulation time 109048238081 ps
CPU time 916.49 seconds
Started Jun 27 06:00:24 PM PDT 24
Finished Jun 27 06:15:42 PM PDT 24
Peak memory 191324 kb
Host smart-96134ad9-94b8-4d7e-825d-7f6fdb46f2f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197623471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.197623471
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2915179689
Short name T227
Test name
Test status
Simulation time 95581019733 ps
CPU time 467.45 seconds
Started Jun 27 06:00:45 PM PDT 24
Finished Jun 27 06:08:34 PM PDT 24
Peak memory 191324 kb
Host smart-a832bfe7-683c-4f0e-8080-7ffdfbca14d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915179689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2915179689
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1010969400
Short name T306
Test name
Test status
Simulation time 135313365994 ps
CPU time 352.04 seconds
Started Jun 27 06:00:43 PM PDT 24
Finished Jun 27 06:06:37 PM PDT 24
Peak memory 191356 kb
Host smart-eb709ae2-f36b-4a05-b82b-e4b6c46b6ede
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010969400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1010969400
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.4036561282
Short name T242
Test name
Test status
Simulation time 102202367870 ps
CPU time 151.07 seconds
Started Jun 27 06:01:00 PM PDT 24
Finished Jun 27 06:03:32 PM PDT 24
Peak memory 191340 kb
Host smart-2abef1c0-e98c-424d-a2e8-a1257b8f74be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036561282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4036561282
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1824121203
Short name T211
Test name
Test status
Simulation time 155959641660 ps
CPU time 241.97 seconds
Started Jun 27 06:00:58 PM PDT 24
Finished Jun 27 06:05:02 PM PDT 24
Peak memory 191368 kb
Host smart-fe045903-ec41-41bc-9d5f-9f4bed654fda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824121203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1824121203
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.541232063
Short name T262
Test name
Test status
Simulation time 1176841617517 ps
CPU time 512.25 seconds
Started Jun 27 05:59:24 PM PDT 24
Finished Jun 27 06:08:06 PM PDT 24
Peak memory 183168 kb
Host smart-2546f4d2-24db-4186-81da-b91334476f1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541232063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.541232063
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_random.539801897
Short name T121
Test name
Test status
Simulation time 115514971309 ps
CPU time 165.67 seconds
Started Jun 27 05:59:46 PM PDT 24
Finished Jun 27 06:02:36 PM PDT 24
Peak memory 191372 kb
Host smart-6750537c-5561-4585-b10d-e8a6c1cab54d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539801897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.539801897
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2879719726
Short name T195
Test name
Test status
Simulation time 43762250798 ps
CPU time 68.02 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:01:15 PM PDT 24
Peak memory 191360 kb
Host smart-68d371b4-08c0-44db-9fd9-ead51f373d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879719726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2879719726
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1211000494
Short name T330
Test name
Test status
Simulation time 115216713674 ps
CPU time 189.19 seconds
Started Jun 27 06:00:07 PM PDT 24
Finished Jun 27 06:03:19 PM PDT 24
Peak memory 191360 kb
Host smart-f9b4e989-4cb9-4568-b8e1-eee1f6b7a508
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211000494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1211000494
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3664073871
Short name T48
Test name
Test status
Simulation time 1802067926334 ps
CPU time 571.96 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 06:08:51 PM PDT 24
Peak memory 191360 kb
Host smart-d5857811-4a30-426c-bc09-dc8c0a8fb498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664073871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3664073871
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.3188502285
Short name T256
Test name
Test status
Simulation time 411667463201 ps
CPU time 245.98 seconds
Started Jun 27 06:00:25 PM PDT 24
Finished Jun 27 06:04:33 PM PDT 24
Peak memory 191368 kb
Host smart-d5ff11f5-cce4-4900-90f9-e291edc7aaf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188502285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3188502285
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1765040981
Short name T334
Test name
Test status
Simulation time 374405843202 ps
CPU time 385.82 seconds
Started Jun 27 06:00:24 PM PDT 24
Finished Jun 27 06:06:51 PM PDT 24
Peak memory 191372 kb
Host smart-6e07a434-3e77-417e-915e-19b50f9b6e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765040981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1765040981
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.84957762
Short name T167
Test name
Test status
Simulation time 523866045822 ps
CPU time 265.52 seconds
Started Jun 27 06:00:27 PM PDT 24
Finished Jun 27 06:04:54 PM PDT 24
Peak memory 191328 kb
Host smart-f9c53066-9fcc-487f-a119-052213988fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84957762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.84957762
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2584632309
Short name T231
Test name
Test status
Simulation time 67526730237 ps
CPU time 558.28 seconds
Started Jun 27 06:00:43 PM PDT 24
Finished Jun 27 06:10:03 PM PDT 24
Peak memory 191312 kb
Host smart-379033af-1a97-42a9-a9a0-80019e95b571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584632309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2584632309
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.4035614249
Short name T91
Test name
Test status
Simulation time 2206994718848 ps
CPU time 381.74 seconds
Started Jun 27 06:00:40 PM PDT 24
Finished Jun 27 06:07:04 PM PDT 24
Peak memory 191252 kb
Host smart-6d5c8e27-7df0-40dc-ba53-d5a2da465fe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035614249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4035614249
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1424921467
Short name T303
Test name
Test status
Simulation time 138537483643 ps
CPU time 480.78 seconds
Started Jun 27 06:00:59 PM PDT 24
Finished Jun 27 06:09:02 PM PDT 24
Peak memory 194796 kb
Host smart-06829637-4ca3-4dca-b428-99c5af7f295a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424921467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1424921467
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2613627203
Short name T151
Test name
Test status
Simulation time 631253300349 ps
CPU time 360.78 seconds
Started Jun 27 06:01:04 PM PDT 24
Finished Jun 27 06:07:06 PM PDT 24
Peak memory 191320 kb
Host smart-05e0f9b3-f73a-407a-a0eb-96088de1d4c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613627203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2613627203
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3445877296
Short name T246
Test name
Test status
Simulation time 132231173508 ps
CPU time 269.76 seconds
Started Jun 27 06:01:28 PM PDT 24
Finished Jun 27 06:05:59 PM PDT 24
Peak memory 191356 kb
Host smart-d1577bd6-5c0f-4a44-a7fa-6c7ccd7d3fe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445877296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3445877296
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.4199251420
Short name T58
Test name
Test status
Simulation time 472954362795 ps
CPU time 213.27 seconds
Started Jun 27 05:59:30 PM PDT 24
Finished Jun 27 06:03:12 PM PDT 24
Peak memory 191360 kb
Host smart-6be69360-b860-4753-8aa7-cb67fd6ca7fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199251420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.4199251420
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3298916462
Short name T105
Test name
Test status
Simulation time 543295359259 ps
CPU time 233.88 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:03:43 PM PDT 24
Peak memory 191364 kb
Host smart-fbad786a-c7c0-4410-b46d-bd200b995dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298916462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3298916462
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.3828156367
Short name T163
Test name
Test status
Simulation time 179117114957 ps
CPU time 986.31 seconds
Started Jun 27 06:00:11 PM PDT 24
Finished Jun 27 06:16:40 PM PDT 24
Peak memory 191352 kb
Host smart-235386e2-2064-4c60-8558-b21b405adb8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828156367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3828156367
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3166628981
Short name T94
Test name
Test status
Simulation time 80038710252 ps
CPU time 623.44 seconds
Started Jun 27 06:00:11 PM PDT 24
Finished Jun 27 06:10:37 PM PDT 24
Peak memory 191280 kb
Host smart-e190a267-c5bb-49a9-99fe-c6cb77cd7080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166628981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3166628981
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1863357260
Short name T83
Test name
Test status
Simulation time 189658232 ps
CPU time 1.28 seconds
Started Jun 27 05:58:20 PM PDT 24
Finished Jun 27 05:58:23 PM PDT 24
Peak memory 182712 kb
Host smart-1f7d9aff-5739-4255-ab45-4dd4eeb73538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863357260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1863357260
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_random.3658433548
Short name T292
Test name
Test status
Simulation time 75558757908 ps
CPU time 28.92 seconds
Started Jun 27 05:59:14 PM PDT 24
Finished Jun 27 05:59:51 PM PDT 24
Peak memory 183080 kb
Host smart-11259bf4-fcf4-4074-9ebd-60ed0e266316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658433548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3658433548
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.2702328342
Short name T265
Test name
Test status
Simulation time 157571119090 ps
CPU time 81.75 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:01:34 PM PDT 24
Peak memory 191356 kb
Host smart-e0c2b621-cf58-4386-b7bc-578173651b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702328342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2702328342
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.292350688
Short name T323
Test name
Test status
Simulation time 681694278553 ps
CPU time 466.27 seconds
Started Jun 27 06:00:10 PM PDT 24
Finished Jun 27 06:07:59 PM PDT 24
Peak memory 191324 kb
Host smart-93067e2a-843c-48d0-ab42-b11398c43430
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292350688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.292350688
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.2072884937
Short name T196
Test name
Test status
Simulation time 140850100067 ps
CPU time 266.95 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:04:00 PM PDT 24
Peak memory 191344 kb
Host smart-ac86a467-3fdb-49f5-beb3-47a50b0180d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072884937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2072884937
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3693082847
Short name T325
Test name
Test status
Simulation time 760201169534 ps
CPU time 946.35 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:15:12 PM PDT 24
Peak memory 195656 kb
Host smart-f8e77606-4c43-4c45-877d-0160b01d0b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693082847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3693082847
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.3317218253
Short name T136
Test name
Test status
Simulation time 158150954578 ps
CPU time 745.74 seconds
Started Jun 27 06:00:24 PM PDT 24
Finished Jun 27 06:12:51 PM PDT 24
Peak memory 194172 kb
Host smart-7031c318-334d-4b17-8a40-4cfbc4b8eb86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317218253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3317218253
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3511465037
Short name T101
Test name
Test status
Simulation time 534848707933 ps
CPU time 267.95 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:03:55 PM PDT 24
Peak memory 183156 kb
Host smart-ccaee356-f6af-42a0-ad38-bacb0803f99f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511465037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3511465037
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/131.rv_timer_random.1876551624
Short name T169
Test name
Test status
Simulation time 998465160136 ps
CPU time 433.94 seconds
Started Jun 27 06:00:25 PM PDT 24
Finished Jun 27 06:07:41 PM PDT 24
Peak memory 191364 kb
Host smart-6a03e20a-bf69-4270-b2d0-f49f28c2688d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876551624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1876551624
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1518215797
Short name T141
Test name
Test status
Simulation time 397425301356 ps
CPU time 269.09 seconds
Started Jun 27 06:00:26 PM PDT 24
Finished Jun 27 06:04:57 PM PDT 24
Peak memory 191324 kb
Host smart-33061628-3957-479f-9f14-7a1edae2c785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518215797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1518215797
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1999169818
Short name T258
Test name
Test status
Simulation time 116092595587 ps
CPU time 76.91 seconds
Started Jun 27 06:00:40 PM PDT 24
Finished Jun 27 06:01:59 PM PDT 24
Peak memory 191556 kb
Host smart-84e4f167-bca1-40d7-824a-a75aaf54e603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999169818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1999169818
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.670700818
Short name T104
Test name
Test status
Simulation time 113539516844 ps
CPU time 56.61 seconds
Started Jun 27 06:00:48 PM PDT 24
Finished Jun 27 06:01:46 PM PDT 24
Peak memory 183136 kb
Host smart-c17f9291-8cd3-4db5-9362-e140c2a196a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670700818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.670700818
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.844845443
Short name T236
Test name
Test status
Simulation time 57778625810 ps
CPU time 273.01 seconds
Started Jun 27 06:00:48 PM PDT 24
Finished Jun 27 06:05:22 PM PDT 24
Peak memory 191328 kb
Host smart-53577f95-b984-4879-9369-491f647752af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844845443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.844845443
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3664990228
Short name T194
Test name
Test status
Simulation time 157309999117 ps
CPU time 241.52 seconds
Started Jun 27 06:00:58 PM PDT 24
Finished Jun 27 06:05:01 PM PDT 24
Peak memory 191332 kb
Host smart-e5130abc-8b77-4f1f-9d18-c3325ce433f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664990228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3664990228
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3210419890
Short name T235
Test name
Test status
Simulation time 76693657686 ps
CPU time 106.29 seconds
Started Jun 27 06:01:00 PM PDT 24
Finished Jun 27 06:02:47 PM PDT 24
Peak memory 191348 kb
Host smart-7f389cdb-5362-4dda-8995-5d8d2a72978f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210419890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3210419890
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.405377386
Short name T17
Test name
Test status
Simulation time 700578354428 ps
CPU time 1592.42 seconds
Started Jun 27 06:01:28 PM PDT 24
Finished Jun 27 06:28:02 PM PDT 24
Peak memory 191316 kb
Host smart-e1cdc72e-c506-4df2-a4cb-895da0419122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405377386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.405377386
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.131755714
Short name T52
Test name
Test status
Simulation time 313369011793 ps
CPU time 279.56 seconds
Started Jun 27 05:59:18 PM PDT 24
Finished Jun 27 06:04:09 PM PDT 24
Peak memory 183148 kb
Host smart-e7fd88a3-8f58-4e1e-8604-dcdc0ccc9caf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131755714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.131755714
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.243373807
Short name T278
Test name
Test status
Simulation time 331558475679 ps
CPU time 521.36 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 06:08:05 PM PDT 24
Peak memory 191356 kb
Host smart-4cd6f186-f2c3-4040-8c62-4bfd033d32bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243373807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.243373807
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2425694424
Short name T342
Test name
Test status
Simulation time 298795411044 ps
CPU time 169.8 seconds
Started Jun 27 05:59:27 PM PDT 24
Finished Jun 27 06:02:27 PM PDT 24
Peak memory 191180 kb
Host smart-9d71f09f-60bc-4204-aea9-2ed419ae9303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425694424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2425694424
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_random.1421735208
Short name T117
Test name
Test status
Simulation time 81941398809 ps
CPU time 101.04 seconds
Started Jun 27 05:59:36 PM PDT 24
Finished Jun 27 06:01:22 PM PDT 24
Peak memory 191356 kb
Host smart-a40f4752-022b-4b1b-834e-43ea48775dd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421735208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1421735208
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2942773178
Short name T149
Test name
Test status
Simulation time 2590033393388 ps
CPU time 1463.07 seconds
Started Jun 27 05:59:43 PM PDT 24
Finished Jun 27 06:24:08 PM PDT 24
Peak memory 191364 kb
Host smart-25c2c55d-b04b-4fc2-b37c-dde056c973ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942773178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2942773178
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/54.rv_timer_random.2035569608
Short name T202
Test name
Test status
Simulation time 439521449736 ps
CPU time 290.4 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:04:59 PM PDT 24
Peak memory 191352 kb
Host smart-605f152f-b53b-4510-aa6e-a0f6dcce0f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035569608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2035569608
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1074451592
Short name T87
Test name
Test status
Simulation time 125610470344 ps
CPU time 120.58 seconds
Started Jun 27 06:00:10 PM PDT 24
Finished Jun 27 06:02:13 PM PDT 24
Peak memory 191280 kb
Host smart-6aafe2ec-f069-4c61-bccf-3c615477f230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074451592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1074451592
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1737085756
Short name T302
Test name
Test status
Simulation time 44658027201 ps
CPU time 62.09 seconds
Started Jun 27 06:00:11 PM PDT 24
Finished Jun 27 06:01:15 PM PDT 24
Peak memory 194176 kb
Host smart-6fb83bf0-44a4-4a22-8f75-a72c2bbb4b7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737085756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1737085756
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.1341674697
Short name T147
Test name
Test status
Simulation time 159760422369 ps
CPU time 273.25 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:04:02 PM PDT 24
Peak memory 191548 kb
Host smart-c4e43815-c84f-43da-9df1-01efe29beb3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341674697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1341674697
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.3290061204
Short name T199
Test name
Test status
Simulation time 212888697811 ps
CPU time 161.45 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:02:52 PM PDT 24
Peak memory 191364 kb
Host smart-64b5cbb9-2152-432e-9222-1838086c6b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290061204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3290061204
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3125970170
Short name T67
Test name
Test status
Simulation time 31835167 ps
CPU time 0.84 seconds
Started Jun 27 05:58:19 PM PDT 24
Finished Jun 27 05:58:21 PM PDT 24
Peak memory 192276 kb
Host smart-867c311c-f196-4173-b6a1-024cdd19f49a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125970170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3125970170
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.209075557
Short name T72
Test name
Test status
Simulation time 120771337 ps
CPU time 2.4 seconds
Started Jun 27 05:58:17 PM PDT 24
Finished Jun 27 05:58:21 PM PDT 24
Peak memory 193448 kb
Host smart-401970fe-8d81-4aee-9232-3ea2b64979bd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209075557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.209075557
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.4204708513
Short name T538
Test name
Test status
Simulation time 46314565 ps
CPU time 0.56 seconds
Started Jun 27 05:58:16 PM PDT 24
Finished Jun 27 05:58:18 PM PDT 24
Peak memory 182240 kb
Host smart-6e748e00-4f6d-4f28-ac07-14b2171b92fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204708513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.4204708513
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3213044937
Short name T495
Test name
Test status
Simulation time 112492557 ps
CPU time 0.84 seconds
Started Jun 27 05:58:19 PM PDT 24
Finished Jun 27 05:58:22 PM PDT 24
Peak memory 196004 kb
Host smart-8667dcea-16c2-4b78-a576-cbe89037e1fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213044937 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3213044937
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.319495301
Short name T520
Test name
Test status
Simulation time 63490153 ps
CPU time 0.57 seconds
Started Jun 27 05:58:19 PM PDT 24
Finished Jun 27 05:58:22 PM PDT 24
Peak memory 182136 kb
Host smart-0eb31fb4-9273-4fdc-9bd8-2cd6035e5316
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319495301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.319495301
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1057131311
Short name T568
Test name
Test status
Simulation time 14503357 ps
CPU time 0.53 seconds
Started Jun 27 05:58:16 PM PDT 24
Finished Jun 27 05:58:18 PM PDT 24
Peak memory 181900 kb
Host smart-5d04d7c5-b474-4a7a-ba44-d9a4f29e9ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057131311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1057131311
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4243755101
Short name T546
Test name
Test status
Simulation time 26979796 ps
CPU time 0.68 seconds
Started Jun 27 05:58:21 PM PDT 24
Finished Jun 27 05:58:23 PM PDT 24
Peak memory 191844 kb
Host smart-d1d1d80a-1133-4c18-be50-20c4b9619979
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243755101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.4243755101
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1965373063
Short name T486
Test name
Test status
Simulation time 414665500 ps
CPU time 1.75 seconds
Started Jun 27 05:58:18 PM PDT 24
Finished Jun 27 05:58:21 PM PDT 24
Peak memory 197104 kb
Host smart-3949a275-8093-48cf-97d3-841ab8b027b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965373063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1965373063
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.483720442
Short name T557
Test name
Test status
Simulation time 76857288 ps
CPU time 0.71 seconds
Started Jun 27 05:58:17 PM PDT 24
Finished Jun 27 05:58:20 PM PDT 24
Peak memory 182328 kb
Host smart-926eeb52-e105-409d-b124-7adb2a454185
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483720442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.483720442
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2824538030
Short name T69
Test name
Test status
Simulation time 146618180 ps
CPU time 1.59 seconds
Started Jun 27 05:58:19 PM PDT 24
Finished Jun 27 05:58:22 PM PDT 24
Peak memory 190704 kb
Host smart-9b719800-cb24-486d-8975-a703fd86319d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824538030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2824538030
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.519941483
Short name T70
Test name
Test status
Simulation time 18797525 ps
CPU time 0.56 seconds
Started Jun 27 05:58:16 PM PDT 24
Finished Jun 27 05:58:18 PM PDT 24
Peak memory 182244 kb
Host smart-bb7b447e-e3ad-4609-b853-31775533d3db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519941483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.519941483
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1909144900
Short name T456
Test name
Test status
Simulation time 110467538 ps
CPU time 1.49 seconds
Started Jun 27 05:58:18 PM PDT 24
Finished Jun 27 05:58:21 PM PDT 24
Peak memory 197116 kb
Host smart-901e4081-28b5-4b83-a06f-3b65bf05e6e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909144900 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1909144900
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.16973447
Short name T513
Test name
Test status
Simulation time 23932978 ps
CPU time 0.63 seconds
Started Jun 27 05:58:21 PM PDT 24
Finished Jun 27 05:58:23 PM PDT 24
Peak memory 191552 kb
Host smart-7c9510c4-5222-454f-8e20-9190fd021de0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16973447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.16973447
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2180912459
Short name T483
Test name
Test status
Simulation time 19712618 ps
CPU time 0.54 seconds
Started Jun 27 05:58:21 PM PDT 24
Finished Jun 27 05:58:23 PM PDT 24
Peak memory 181708 kb
Host smart-25a920cd-95d2-48d3-9845-86e64030b08f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180912459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2180912459
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3391727371
Short name T63
Test name
Test status
Simulation time 44722347 ps
CPU time 0.74 seconds
Started Jun 27 05:58:15 PM PDT 24
Finished Jun 27 05:58:17 PM PDT 24
Peak memory 191300 kb
Host smart-3c42587b-4240-4b40-86ea-5466c11df7e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391727371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3391727371
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3693231912
Short name T472
Test name
Test status
Simulation time 150173356 ps
CPU time 2.21 seconds
Started Jun 27 05:58:17 PM PDT 24
Finished Jun 27 05:58:21 PM PDT 24
Peak memory 197124 kb
Host smart-e770d970-1fa7-444c-acc0-008dc71f9684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693231912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3693231912
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1763349527
Short name T554
Test name
Test status
Simulation time 955048312 ps
CPU time 1.3 seconds
Started Jun 27 05:58:19 PM PDT 24
Finished Jun 27 05:58:22 PM PDT 24
Peak memory 194840 kb
Host smart-bcc30fb2-8558-48e7-88f0-6bc0e7a6e3d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763349527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1763349527
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3269875714
Short name T485
Test name
Test status
Simulation time 87322227 ps
CPU time 1.16 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 197092 kb
Host smart-57b364e7-6343-4a7b-94be-df999b009448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269875714 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3269875714
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2042423354
Short name T531
Test name
Test status
Simulation time 52023560 ps
CPU time 0.63 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:45 PM PDT 24
Peak memory 182348 kb
Host smart-2a985d33-dd44-4439-b029-52d17296ad2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042423354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2042423354
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.869678658
Short name T460
Test name
Test status
Simulation time 41818950 ps
CPU time 0.54 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 181724 kb
Host smart-25de9d5f-b624-4f28-9a43-37689e6806fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869678658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.869678658
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2336063110
Short name T526
Test name
Test status
Simulation time 66763157 ps
CPU time 0.8 seconds
Started Jun 27 05:58:45 PM PDT 24
Finished Jun 27 05:58:49 PM PDT 24
Peak memory 190548 kb
Host smart-ff10829f-f771-4a18-b59f-6553a3600b8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336063110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2336063110
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1762696351
Short name T547
Test name
Test status
Simulation time 564541763 ps
CPU time 2.26 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 197056 kb
Host smart-8418f401-b991-4b42-90e5-2ef07f44dbf7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762696351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1762696351
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.148710366
Short name T502
Test name
Test status
Simulation time 165371967 ps
CPU time 0.84 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 192216 kb
Host smart-7cf69f4c-40bc-440b-8a46-f21a3c88685d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148710366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.148710366
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3665693147
Short name T504
Test name
Test status
Simulation time 561098199 ps
CPU time 0.8 seconds
Started Jun 27 05:58:43 PM PDT 24
Finished Jun 27 05:58:49 PM PDT 24
Peak memory 195516 kb
Host smart-5e5a48ed-17c4-43dd-af5e-bd8eba6caad3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665693147 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3665693147
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1584056456
Short name T500
Test name
Test status
Simulation time 105172388 ps
CPU time 0.55 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:45 PM PDT 24
Peak memory 182348 kb
Host smart-4e4094be-9686-4467-a5c9-eae245432c19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584056456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1584056456
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2635649357
Short name T578
Test name
Test status
Simulation time 11950321 ps
CPU time 0.53 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:43 PM PDT 24
Peak memory 182176 kb
Host smart-a9e7cb63-3819-4fad-8042-92ad12b32073
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635649357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2635649357
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.125812973
Short name T78
Test name
Test status
Simulation time 437991667 ps
CPU time 0.76 seconds
Started Jun 27 05:58:45 PM PDT 24
Finished Jun 27 05:58:49 PM PDT 24
Peak memory 191284 kb
Host smart-dda73478-cddb-4464-8d05-a44332aa3d17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125812973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.125812973
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.21196068
Short name T466
Test name
Test status
Simulation time 56447661 ps
CPU time 0.97 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:45 PM PDT 24
Peak memory 196764 kb
Host smart-181b289b-d8fb-476c-9a9e-63db79c8e6a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21196068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.21196068
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2815965061
Short name T85
Test name
Test status
Simulation time 746172226 ps
CPU time 1.08 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 194640 kb
Host smart-26ec1fb9-55b7-488c-876d-4a29066e282d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815965061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2815965061
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1738480710
Short name T464
Test name
Test status
Simulation time 37846288 ps
CPU time 0.9 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 196748 kb
Host smart-d31c9b57-4c51-4d97-9e84-d57ea32221f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738480710 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1738480710
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3835575211
Short name T522
Test name
Test status
Simulation time 20383115 ps
CPU time 0.59 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 182152 kb
Host smart-93d691cd-9068-4c4d-b18b-09049001b26b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835575211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3835575211
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.638409751
Short name T470
Test name
Test status
Simulation time 14802952 ps
CPU time 0.52 seconds
Started Jun 27 05:58:45 PM PDT 24
Finished Jun 27 05:58:49 PM PDT 24
Peak memory 181732 kb
Host smart-04af5459-3a3a-45b7-aa58-1000a5c51a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638409751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.638409751
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1106603212
Short name T66
Test name
Test status
Simulation time 87726428 ps
CPU time 0.79 seconds
Started Jun 27 05:58:42 PM PDT 24
Finished Jun 27 05:58:48 PM PDT 24
Peak memory 191284 kb
Host smart-9c0d15da-0545-4715-9951-32b5097b209f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106603212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1106603212
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2149105498
Short name T481
Test name
Test status
Simulation time 75124174 ps
CPU time 2.03 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 197128 kb
Host smart-7efa3ee3-2123-4218-afd1-7bc80c7bbae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149105498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2149105498
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.88489771
Short name T534
Test name
Test status
Simulation time 85533523 ps
CPU time 1.09 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:45 PM PDT 24
Peak memory 182868 kb
Host smart-c8dffb19-31e5-4e57-bea0-521fdf5306ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88489771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_int
g_err.88489771
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4170075527
Short name T463
Test name
Test status
Simulation time 22607004 ps
CPU time 1.03 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 196984 kb
Host smart-6095ebff-c089-4f6a-ad1e-8c2edc03dae2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170075527 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.4170075527
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.113665790
Short name T71
Test name
Test status
Simulation time 15925187 ps
CPU time 0.63 seconds
Started Jun 27 05:58:42 PM PDT 24
Finished Jun 27 05:58:48 PM PDT 24
Peak memory 182292 kb
Host smart-41b16a4b-2110-4813-abe4-f1b980a3d5ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113665790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.113665790
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3291673323
Short name T532
Test name
Test status
Simulation time 52160458 ps
CPU time 0.57 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 182192 kb
Host smart-d3b87e8b-4591-4b61-9935-188bdeca677d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291673323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3291673323
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.698328485
Short name T75
Test name
Test status
Simulation time 108121333 ps
CPU time 0.72 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:42 PM PDT 24
Peak memory 193056 kb
Host smart-fdaa4497-2ea1-461e-a290-8da5935f9cd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698328485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.698328485
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2332499151
Short name T569
Test name
Test status
Simulation time 234037336 ps
CPU time 1.24 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 197060 kb
Host smart-984eb9bc-73bc-4fb4-8649-5b0eaa85f947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332499151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2332499151
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2628232973
Short name T27
Test name
Test status
Simulation time 334014265 ps
CPU time 1.06 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 193704 kb
Host smart-69f7c82e-51d3-4760-bcca-347186007d96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628232973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2628232973
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.757679531
Short name T580
Test name
Test status
Simulation time 93589053 ps
CPU time 1.33 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 197136 kb
Host smart-f0cdda91-94b1-4fbe-a64f-4f915101b72b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757679531 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.757679531
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1361230889
Short name T512
Test name
Test status
Simulation time 15381206 ps
CPU time 0.59 seconds
Started Jun 27 05:58:46 PM PDT 24
Finished Jun 27 05:58:50 PM PDT 24
Peak memory 182336 kb
Host smart-f7a6c796-9911-47da-b4dd-6ac4d9e2a6d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361230889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1361230889
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1258836496
Short name T473
Test name
Test status
Simulation time 40571412 ps
CPU time 0.57 seconds
Started Jun 27 05:58:42 PM PDT 24
Finished Jun 27 05:58:48 PM PDT 24
Peak memory 182228 kb
Host smart-798c2f0e-7cb9-4de9-a898-a63993bc7d71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258836496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1258836496
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1734694050
Short name T577
Test name
Test status
Simulation time 196854179 ps
CPU time 0.62 seconds
Started Jun 27 05:58:42 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 191780 kb
Host smart-054bf4a0-ce56-4184-ad4d-63a982a80563
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734694050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1734694050
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3593500281
Short name T479
Test name
Test status
Simulation time 40353209 ps
CPU time 1.01 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 196976 kb
Host smart-9baad6bc-57c8-4d42-a6bd-043a1a2e20c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593500281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3593500281
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.359187713
Short name T515
Test name
Test status
Simulation time 386491269 ps
CPU time 1.29 seconds
Started Jun 27 05:58:38 PM PDT 24
Finished Jun 27 05:58:41 PM PDT 24
Peak memory 195164 kb
Host smart-6bc74800-8285-4bc3-a9c1-71c5340d817a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359187713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.359187713
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1644244073
Short name T523
Test name
Test status
Simulation time 33826095 ps
CPU time 0.91 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 196888 kb
Host smart-fa11aff2-7f96-412a-959c-7bfb0c76a850
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644244073 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1644244073
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2938961328
Short name T556
Test name
Test status
Simulation time 18235418 ps
CPU time 0.59 seconds
Started Jun 27 05:58:42 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 182208 kb
Host smart-a3197e87-8b44-41c8-b622-0799e740dc93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938961328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2938961328
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2956802602
Short name T519
Test name
Test status
Simulation time 93726352 ps
CPU time 0.8 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 193108 kb
Host smart-16180454-7a87-447f-b404-56b86e7e58fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956802602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2956802602
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.249714228
Short name T489
Test name
Test status
Simulation time 405619502 ps
CPU time 2.26 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 197084 kb
Host smart-6c6cb767-2f43-4781-82b1-91f1b81e4d99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249714228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.249714228
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2029437374
Short name T536
Test name
Test status
Simulation time 277913993 ps
CPU time 1.39 seconds
Started Jun 27 05:58:42 PM PDT 24
Finished Jun 27 05:58:49 PM PDT 24
Peak memory 182852 kb
Host smart-e15ec1f2-f6bf-4b74-b101-278d08b114cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029437374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2029437374
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3492049200
Short name T492
Test name
Test status
Simulation time 153991059 ps
CPU time 1.48 seconds
Started Jun 27 05:59:09 PM PDT 24
Finished Jun 27 05:59:12 PM PDT 24
Peak memory 197104 kb
Host smart-52bdc4c9-b348-4fda-8c42-8cde1d257ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492049200 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3492049200
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1739210698
Short name T510
Test name
Test status
Simulation time 36859711 ps
CPU time 0.6 seconds
Started Jun 27 05:59:10 PM PDT 24
Finished Jun 27 05:59:12 PM PDT 24
Peak memory 182212 kb
Host smart-6f545588-9021-44a8-b90f-73ae26c44476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739210698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1739210698
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3871506210
Short name T487
Test name
Test status
Simulation time 23143848 ps
CPU time 0.54 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:18 PM PDT 24
Peak memory 181688 kb
Host smart-f59a439c-243d-4707-b16d-4ec3928727ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871506210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3871506210
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1676855198
Short name T563
Test name
Test status
Simulation time 114598001 ps
CPU time 0.72 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:22 PM PDT 24
Peak memory 191984 kb
Host smart-17241ccb-5bc9-4383-a186-77a6534aaed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676855198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1676855198
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3482273493
Short name T553
Test name
Test status
Simulation time 310200494 ps
CPU time 3.37 seconds
Started Jun 27 05:58:42 PM PDT 24
Finished Jun 27 05:58:50 PM PDT 24
Peak memory 197120 kb
Host smart-8ea10a30-6452-4c60-842e-5331f6d47961
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482273493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3482273493
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.763453390
Short name T484
Test name
Test status
Simulation time 198530495 ps
CPU time 0.92 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:19 PM PDT 24
Peak memory 193044 kb
Host smart-bac9bf85-da5c-43d8-a2c0-1580f3ebb4a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763453390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.763453390
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3853042792
Short name T474
Test name
Test status
Simulation time 79611391 ps
CPU time 0.73 seconds
Started Jun 27 05:59:09 PM PDT 24
Finished Jun 27 05:59:11 PM PDT 24
Peak memory 194716 kb
Host smart-5e0841c7-cc3b-41b5-a9a7-b999bf593ba7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853042792 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3853042792
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3835728050
Short name T64
Test name
Test status
Simulation time 30387794 ps
CPU time 0.58 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:21 PM PDT 24
Peak memory 182016 kb
Host smart-9eef898f-3843-41b1-8aa3-9c3cb12a974a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835728050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3835728050
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.528310377
Short name T488
Test name
Test status
Simulation time 16918485 ps
CPU time 0.57 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:16 PM PDT 24
Peak memory 182172 kb
Host smart-f126d5a9-4e27-4106-b02d-da13d84144e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528310377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.528310377
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2762679515
Short name T501
Test name
Test status
Simulation time 18139244 ps
CPU time 0.78 seconds
Started Jun 27 05:59:14 PM PDT 24
Finished Jun 27 05:59:22 PM PDT 24
Peak memory 191228 kb
Host smart-19323b40-8fea-4b34-9faa-f6924c993283
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762679515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2762679515
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1126407001
Short name T467
Test name
Test status
Simulation time 60152175 ps
CPU time 1.55 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:19 PM PDT 24
Peak memory 197136 kb
Host smart-f86578c4-1ebb-4d2d-816d-08b7c2fc45b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126407001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1126407001
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3348142674
Short name T514
Test name
Test status
Simulation time 130385083 ps
CPU time 1.43 seconds
Started Jun 27 05:59:10 PM PDT 24
Finished Jun 27 05:59:13 PM PDT 24
Peak memory 194896 kb
Host smart-2e6b5fed-7097-40b7-82f4-2d27f3fe6ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348142674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3348142674
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.556462547
Short name T41
Test name
Test status
Simulation time 52721438 ps
CPU time 0.79 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:16 PM PDT 24
Peak memory 195376 kb
Host smart-4dcf44f2-d045-40ed-836b-004e4cad3d42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556462547 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.556462547
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1961928604
Short name T524
Test name
Test status
Simulation time 13403581 ps
CPU time 0.65 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 05:59:15 PM PDT 24
Peak memory 182336 kb
Host smart-d1503180-fbec-4d78-9938-6e1a49eac87a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961928604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1961928604
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2837807960
Short name T477
Test name
Test status
Simulation time 37144157 ps
CPU time 0.55 seconds
Started Jun 27 05:59:14 PM PDT 24
Finished Jun 27 05:59:22 PM PDT 24
Peak memory 182216 kb
Host smart-37a134d2-9625-46bf-8174-066eef2bc350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837807960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2837807960
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2006433186
Short name T76
Test name
Test status
Simulation time 34290384 ps
CPU time 0.64 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:18 PM PDT 24
Peak memory 191316 kb
Host smart-85443792-0f33-4b16-b928-4bc77ec32282
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006433186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2006433186
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.945864070
Short name T540
Test name
Test status
Simulation time 391903808 ps
CPU time 2 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:21 PM PDT 24
Peak memory 197160 kb
Host smart-fdd8bb20-1a09-4d3f-85ce-b618bb30b004
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945864070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.945864070
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2778633949
Short name T82
Test name
Test status
Simulation time 227477434 ps
CPU time 1.35 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:20 PM PDT 24
Peak memory 195008 kb
Host smart-5c3be0db-2305-498f-9312-6e2e86b8de4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778633949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2778633949
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2220493800
Short name T562
Test name
Test status
Simulation time 54991907 ps
CPU time 0.76 seconds
Started Jun 27 05:59:14 PM PDT 24
Finished Jun 27 05:59:22 PM PDT 24
Peak memory 194552 kb
Host smart-93b1acff-fd58-494b-ba8a-8cd282e12a4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220493800 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2220493800
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2812611619
Short name T81
Test name
Test status
Simulation time 14088727 ps
CPU time 0.59 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:19 PM PDT 24
Peak memory 181912 kb
Host smart-c344d9e5-ee03-4915-8914-5eadba638257
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812611619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2812611619
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2063100456
Short name T573
Test name
Test status
Simulation time 19386014 ps
CPU time 0.61 seconds
Started Jun 27 05:59:09 PM PDT 24
Finished Jun 27 05:59:12 PM PDT 24
Peak memory 182196 kb
Host smart-c37201cc-ce2b-456e-8cf2-dbf85fc50e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063100456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2063100456
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4213036893
Short name T506
Test name
Test status
Simulation time 28947248 ps
CPU time 0.76 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:17 PM PDT 24
Peak memory 193056 kb
Host smart-77319a88-c110-438c-84fc-7dc91ec4af31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213036893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.4213036893
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3414228778
Short name T550
Test name
Test status
Simulation time 26769812 ps
CPU time 1.42 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:20 PM PDT 24
Peak memory 197028 kb
Host smart-fefad77f-f445-4c2c-93d5-10462a2bd931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414228778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3414228778
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1872903655
Short name T541
Test name
Test status
Simulation time 162017947 ps
CPU time 1.07 seconds
Started Jun 27 05:59:10 PM PDT 24
Finished Jun 27 05:59:13 PM PDT 24
Peak memory 194508 kb
Host smart-1a8c55bb-3410-4fd2-923f-6cfa0a87fe83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872903655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1872903655
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2565353760
Short name T529
Test name
Test status
Simulation time 149435755 ps
CPU time 0.79 seconds
Started Jun 27 05:58:22 PM PDT 24
Finished Jun 27 05:58:24 PM PDT 24
Peak memory 182336 kb
Host smart-2a5c6915-515e-4d05-85fe-a3fdd66621c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565353760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2565353760
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.655192935
Short name T571
Test name
Test status
Simulation time 61771685 ps
CPU time 2.3 seconds
Started Jun 27 05:58:20 PM PDT 24
Finished Jun 27 05:58:24 PM PDT 24
Peak memory 192912 kb
Host smart-726bbb23-6d9d-4182-b878-8edffd81c8de
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655192935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.655192935
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3476823882
Short name T65
Test name
Test status
Simulation time 28840438 ps
CPU time 0.58 seconds
Started Jun 27 05:58:18 PM PDT 24
Finished Jun 27 05:58:20 PM PDT 24
Peak memory 182328 kb
Host smart-65bf8f18-4300-428a-b186-2e43f2686534
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476823882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3476823882
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1141780136
Short name T494
Test name
Test status
Simulation time 26874495 ps
CPU time 1.23 seconds
Started Jun 27 05:58:17 PM PDT 24
Finished Jun 27 05:58:19 PM PDT 24
Peak memory 197124 kb
Host smart-1edd0197-cc62-49f8-ab41-5d3be59abc32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141780136 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1141780136
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2573478326
Short name T68
Test name
Test status
Simulation time 44191385 ps
CPU time 0.58 seconds
Started Jun 27 05:58:18 PM PDT 24
Finished Jun 27 05:58:20 PM PDT 24
Peak memory 182304 kb
Host smart-4637bb69-bf76-4054-aa86-9fb1bc2243a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573478326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2573478326
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3926234878
Short name T552
Test name
Test status
Simulation time 16815464 ps
CPU time 0.59 seconds
Started Jun 27 05:58:16 PM PDT 24
Finished Jun 27 05:58:17 PM PDT 24
Peak memory 181692 kb
Host smart-a478b627-289f-491c-aa4f-a2ed4264347f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926234878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3926234878
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1061123741
Short name T565
Test name
Test status
Simulation time 75971528 ps
CPU time 0.86 seconds
Started Jun 27 05:58:19 PM PDT 24
Finished Jun 27 05:58:21 PM PDT 24
Peak memory 190524 kb
Host smart-f2356cce-4783-48f2-8710-08599aafbe45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061123741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1061123741
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1744157780
Short name T516
Test name
Test status
Simulation time 49643426 ps
CPU time 1.2 seconds
Started Jun 27 05:58:16 PM PDT 24
Finished Jun 27 05:58:18 PM PDT 24
Peak memory 197052 kb
Host smart-97c79cc8-ec13-4d62-888a-bbce6c145015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744157780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1744157780
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3217143198
Short name T476
Test name
Test status
Simulation time 18422661 ps
CPU time 0.6 seconds
Started Jun 27 05:59:09 PM PDT 24
Finished Jun 27 05:59:11 PM PDT 24
Peak memory 182144 kb
Host smart-3f1b80d0-81a6-4b42-b965-a89d59f5e611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217143198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3217143198
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1579058646
Short name T566
Test name
Test status
Simulation time 16483332 ps
CPU time 0.54 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 05:59:14 PM PDT 24
Peak memory 181684 kb
Host smart-b78e4905-b347-4a51-bfd6-f69059b9c63d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579058646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1579058646
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2305486975
Short name T567
Test name
Test status
Simulation time 31330586 ps
CPU time 0.55 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:21 PM PDT 24
Peak memory 182216 kb
Host smart-9481730b-ce61-4e74-8d9d-fb6f90439494
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305486975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2305486975
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.406923383
Short name T528
Test name
Test status
Simulation time 24391306 ps
CPU time 0.56 seconds
Started Jun 27 05:59:08 PM PDT 24
Finished Jun 27 05:59:09 PM PDT 24
Peak memory 181704 kb
Host smart-7c2c42e0-da95-47e2-b0ea-2d9bb0acc7cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406923383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.406923383
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2586465502
Short name T533
Test name
Test status
Simulation time 14341446 ps
CPU time 0.58 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 05:59:14 PM PDT 24
Peak memory 182172 kb
Host smart-068405e2-b8bc-4328-ab6c-7fbdb13dcfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586465502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2586465502
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3225081366
Short name T530
Test name
Test status
Simulation time 12765438 ps
CPU time 0.58 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 05:59:15 PM PDT 24
Peak memory 182228 kb
Host smart-09428ff0-8f32-41fa-88b2-0fc3ddc39424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225081366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3225081366
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.761118101
Short name T480
Test name
Test status
Simulation time 20360100 ps
CPU time 0.64 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:21 PM PDT 24
Peak memory 182216 kb
Host smart-5a3fff90-c8b6-4246-b77f-c8af16ac2cd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761118101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.761118101
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2678093330
Short name T471
Test name
Test status
Simulation time 36368049 ps
CPU time 0.55 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:19 PM PDT 24
Peak memory 182200 kb
Host smart-1fe7c292-b63f-4b40-aa04-56fe4aab4251
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678093330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2678093330
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3194609673
Short name T570
Test name
Test status
Simulation time 29482850 ps
CPU time 0.54 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:17 PM PDT 24
Peak memory 182220 kb
Host smart-fca69a0f-550f-4b46-b3b5-aec1ceef3b24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194609673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3194609673
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2695351994
Short name T560
Test name
Test status
Simulation time 28973675 ps
CPU time 0.58 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:18 PM PDT 24
Peak memory 182264 kb
Host smart-08499fe1-847a-4c4a-a6a5-50b998ecac9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695351994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2695351994
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.865728377
Short name T28
Test name
Test status
Simulation time 164103612 ps
CPU time 0.8 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:42 PM PDT 24
Peak memory 182304 kb
Host smart-9cbaa1ba-18a1-4b12-acdd-6e1b44439c3e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865728377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.865728377
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3852167314
Short name T496
Test name
Test status
Simulation time 281649895 ps
CPU time 1.47 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:45 PM PDT 24
Peak memory 182452 kb
Host smart-db76d1d0-cdbc-4ff2-8db1-df7a2e90ba69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852167314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3852167314
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2301028252
Short name T74
Test name
Test status
Simulation time 15605594 ps
CPU time 0.55 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:42 PM PDT 24
Peak memory 182216 kb
Host smart-74dbc741-8ec0-4d7b-aa25-6a58316aca6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301028252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2301028252
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2149541245
Short name T455
Test name
Test status
Simulation time 70514633 ps
CPU time 0.84 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 196416 kb
Host smart-ddfe1c63-c30b-44aa-aeb3-4c723f88dc0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149541245 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2149541245
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2639861880
Short name T73
Test name
Test status
Simulation time 14477488 ps
CPU time 0.6 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:45 PM PDT 24
Peak memory 191528 kb
Host smart-f77b0190-5711-4e27-abc4-94aca32c1231
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639861880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2639861880
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1289858296
Short name T490
Test name
Test status
Simulation time 13651770 ps
CPU time 0.57 seconds
Started Jun 27 05:58:37 PM PDT 24
Finished Jun 27 05:58:39 PM PDT 24
Peak memory 182208 kb
Host smart-0ce87a56-e21e-4193-873b-5b9481f6cd40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289858296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1289858296
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2127749370
Short name T521
Test name
Test status
Simulation time 134854966 ps
CPU time 0.8 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:42 PM PDT 24
Peak memory 193056 kb
Host smart-261aeb96-0c35-4495-bdee-a0d1b9b76d5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127749370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2127749370
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3253318447
Short name T461
Test name
Test status
Simulation time 141175907 ps
CPU time 2.41 seconds
Started Jun 27 05:58:45 PM PDT 24
Finished Jun 27 05:58:51 PM PDT 24
Peak memory 197160 kb
Host smart-ef7be481-99f0-4c47-8f4c-3629132bdf1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253318447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3253318447
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.132607284
Short name T26
Test name
Test status
Simulation time 58934579 ps
CPU time 0.82 seconds
Started Jun 27 05:58:38 PM PDT 24
Finished Jun 27 05:58:41 PM PDT 24
Peak memory 182624 kb
Host smart-510480eb-a978-4121-baf8-ce43efdaf3f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132607284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.132607284
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3250475835
Short name T558
Test name
Test status
Simulation time 23931389 ps
CPU time 0.53 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:16 PM PDT 24
Peak memory 181688 kb
Host smart-c232b297-dbcb-4643-8516-5d8ea3b83bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250475835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3250475835
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2719789509
Short name T482
Test name
Test status
Simulation time 12101534 ps
CPU time 0.53 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 05:59:15 PM PDT 24
Peak memory 181892 kb
Host smart-405e7a88-1759-4d5f-95bc-8f44a15ce1ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719789509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2719789509
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.815130684
Short name T542
Test name
Test status
Simulation time 120356862 ps
CPU time 0.58 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:18 PM PDT 24
Peak memory 182152 kb
Host smart-bfcf6432-49f3-4023-ad6e-5c37cd44e620
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815130684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.815130684
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1717604326
Short name T458
Test name
Test status
Simulation time 39143917 ps
CPU time 0.57 seconds
Started Jun 27 05:59:09 PM PDT 24
Finished Jun 27 05:59:10 PM PDT 24
Peak memory 182212 kb
Host smart-2555cb82-951b-45e6-8d07-acfe6251fa2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717604326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1717604326
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4017559425
Short name T454
Test name
Test status
Simulation time 270347436 ps
CPU time 0.57 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:21 PM PDT 24
Peak memory 182240 kb
Host smart-4f01ac75-7fe6-4332-9f68-dc970e5be28a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017559425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4017559425
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.87761314
Short name T535
Test name
Test status
Simulation time 30933904 ps
CPU time 0.58 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 05:59:14 PM PDT 24
Peak memory 182360 kb
Host smart-b5136932-8b29-4a03-adae-1e650f805728
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87761314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.87761314
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3364163467
Short name T451
Test name
Test status
Simulation time 15515369 ps
CPU time 0.58 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:20 PM PDT 24
Peak memory 182196 kb
Host smart-a3d5755f-dc58-475e-90df-cbb226fa05cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364163467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3364163467
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3358608224
Short name T478
Test name
Test status
Simulation time 19464610 ps
CPU time 0.55 seconds
Started Jun 27 05:59:10 PM PDT 24
Finished Jun 27 05:59:12 PM PDT 24
Peak memory 182216 kb
Host smart-e15ba794-08a1-4731-a151-20f39944e015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358608224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3358608224
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1488158121
Short name T518
Test name
Test status
Simulation time 34832723 ps
CPU time 0.54 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:17 PM PDT 24
Peak memory 181688 kb
Host smart-80c8292c-a5c2-4866-ac43-c94c61b210cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488158121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1488158121
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1612172789
Short name T450
Test name
Test status
Simulation time 20887720 ps
CPU time 0.58 seconds
Started Jun 27 05:59:10 PM PDT 24
Finished Jun 27 05:59:13 PM PDT 24
Peak memory 182200 kb
Host smart-4c6d33f3-4bd8-4ac8-9c1d-483785d21368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612172789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1612172789
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.4030789138
Short name T80
Test name
Test status
Simulation time 14291450 ps
CPU time 0.64 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:42 PM PDT 24
Peak memory 191564 kb
Host smart-72a08278-3acc-4ddc-a186-155a6c4facef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030789138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.4030789138
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.58377858
Short name T505
Test name
Test status
Simulation time 1096513514 ps
CPU time 2.53 seconds
Started Jun 27 05:58:38 PM PDT 24
Finished Jun 27 05:58:41 PM PDT 24
Peak memory 192272 kb
Host smart-1d1e08a0-6263-4adb-a3eb-87488668f186
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58377858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ba
sh.58377858
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.288199745
Short name T40
Test name
Test status
Simulation time 23535721 ps
CPU time 0.53 seconds
Started Jun 27 05:58:36 PM PDT 24
Finished Jun 27 05:58:37 PM PDT 24
Peak memory 182328 kb
Host smart-dbd43c4f-703e-4433-b472-2e4276f7de12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288199745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.288199745
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1326699572
Short name T459
Test name
Test status
Simulation time 26232486 ps
CPU time 0.85 seconds
Started Jun 27 05:58:45 PM PDT 24
Finished Jun 27 05:58:50 PM PDT 24
Peak memory 196436 kb
Host smart-e0121315-51f9-4a3f-91b1-d03f9610679a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326699572 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1326699572
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1390542338
Short name T551
Test name
Test status
Simulation time 43921970 ps
CPU time 0.62 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:43 PM PDT 24
Peak memory 182272 kb
Host smart-affa6dc5-33b0-465a-8a57-36f5f4c1ba4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390542338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1390542338
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2694063485
Short name T465
Test name
Test status
Simulation time 13658640 ps
CPU time 0.54 seconds
Started Jun 27 05:58:37 PM PDT 24
Finished Jun 27 05:58:39 PM PDT 24
Peak memory 181700 kb
Host smart-574b8bf7-b6ba-4171-8136-aa076de85688
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694063485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2694063485
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1439275800
Short name T509
Test name
Test status
Simulation time 16800876 ps
CPU time 0.71 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:42 PM PDT 24
Peak memory 192700 kb
Host smart-0510042e-d3fc-4da0-8fcc-aea3b5139e79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439275800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1439275800
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1531662614
Short name T468
Test name
Test status
Simulation time 490660781 ps
CPU time 2.43 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 197092 kb
Host smart-3d61f564-afdc-443b-9007-a0b3f5d8788f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531662614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1531662614
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2907260505
Short name T491
Test name
Test status
Simulation time 357026883 ps
CPU time 0.86 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 193344 kb
Host smart-e28045f1-37a4-451e-81db-990c10ff8ffc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907260505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2907260505
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.711709475
Short name T572
Test name
Test status
Simulation time 54146727 ps
CPU time 0.58 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 05:59:15 PM PDT 24
Peak memory 182260 kb
Host smart-144875fc-2f92-4f49-a92a-3ef357033dd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711709475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.711709475
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.711408266
Short name T469
Test name
Test status
Simulation time 23670864 ps
CPU time 0.59 seconds
Started Jun 27 05:59:09 PM PDT 24
Finished Jun 27 05:59:12 PM PDT 24
Peak memory 182272 kb
Host smart-b0fbe4de-efca-41cf-913d-710ab2676345
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711408266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.711408266
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1240062628
Short name T564
Test name
Test status
Simulation time 47408995 ps
CPU time 0.55 seconds
Started Jun 27 05:59:18 PM PDT 24
Finished Jun 27 05:59:29 PM PDT 24
Peak memory 182208 kb
Host smart-a87ea8b2-f3ee-465c-a283-0d0221c94520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240062628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1240062628
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3825601388
Short name T559
Test name
Test status
Simulation time 28243470 ps
CPU time 0.56 seconds
Started Jun 27 05:59:10 PM PDT 24
Finished Jun 27 05:59:13 PM PDT 24
Peak memory 181892 kb
Host smart-0025f063-5a91-4ee1-9da1-2acded61c99c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825601388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3825601388
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.718815915
Short name T499
Test name
Test status
Simulation time 14814433 ps
CPU time 0.53 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:22 PM PDT 24
Peak memory 182256 kb
Host smart-639e0948-8860-4c90-9ae6-3a25824b68d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718815915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.718815915
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.966313222
Short name T543
Test name
Test status
Simulation time 18818013 ps
CPU time 0.53 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:20 PM PDT 24
Peak memory 181656 kb
Host smart-c6257eac-a674-4f28-aad2-f71ae4fbefb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966313222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.966313222
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3166611305
Short name T579
Test name
Test status
Simulation time 74619520 ps
CPU time 0.58 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:18 PM PDT 24
Peak memory 182184 kb
Host smart-02f5b915-f18c-4a51-b8ad-d71bad311cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166611305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3166611305
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.67618581
Short name T507
Test name
Test status
Simulation time 18410277 ps
CPU time 0.57 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 05:59:13 PM PDT 24
Peak memory 182116 kb
Host smart-2a8d9749-c192-41e7-bd9e-ec56f2a26918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67618581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.67618581
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.716866281
Short name T453
Test name
Test status
Simulation time 26540968 ps
CPU time 0.54 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 05:59:14 PM PDT 24
Peak memory 181692 kb
Host smart-25acaaee-bde9-4f33-8043-31fbb436ea15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716866281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.716866281
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.31680902
Short name T555
Test name
Test status
Simulation time 34933156 ps
CPU time 0.57 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 05:59:18 PM PDT 24
Peak memory 182252 kb
Host smart-f999cb80-be38-46d1-a165-5e1bea63793a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31680902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.31680902
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2647129866
Short name T457
Test name
Test status
Simulation time 34475992 ps
CPU time 1.62 seconds
Started Jun 27 05:58:37 PM PDT 24
Finished Jun 27 05:58:40 PM PDT 24
Peak memory 197112 kb
Host smart-21229827-5b02-4545-a3cb-4207ca584042
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647129866 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2647129866
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3923360087
Short name T527
Test name
Test status
Simulation time 37255736 ps
CPU time 0.62 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 182344 kb
Host smart-343bce9f-b856-4641-9f84-70ed7b55684c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923360087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3923360087
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1070127096
Short name T561
Test name
Test status
Simulation time 14087873 ps
CPU time 0.56 seconds
Started Jun 27 05:58:36 PM PDT 24
Finished Jun 27 05:58:38 PM PDT 24
Peak memory 182092 kb
Host smart-71b5a6fd-7473-415a-91b3-0d7f3604d655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070127096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1070127096
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.908903100
Short name T511
Test name
Test status
Simulation time 84666828 ps
CPU time 0.78 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 193096 kb
Host smart-a15b8f81-1c7e-499a-a780-36ac561fc6d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908903100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.908903100
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2054849645
Short name T539
Test name
Test status
Simulation time 170009447 ps
CPU time 1.42 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 197296 kb
Host smart-5681326f-35ba-48f3-b030-acc0cd328832
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054849645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2054849645
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.901665518
Short name T84
Test name
Test status
Simulation time 86539163 ps
CPU time 1.14 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 194572 kb
Host smart-8f7b6af9-970a-42e1-9f99-eed5cd12bdd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901665518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.901665518
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1481657185
Short name T29
Test name
Test status
Simulation time 142859356 ps
CPU time 1.72 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 197304 kb
Host smart-be8aaea8-0920-46c1-8514-7517c1022f94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481657185 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1481657185
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3826377737
Short name T475
Test name
Test status
Simulation time 27436896 ps
CPU time 0.6 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:45 PM PDT 24
Peak memory 191540 kb
Host smart-72667525-0d96-4719-8401-9d3caf50b379
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826377737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3826377737
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2513722706
Short name T452
Test name
Test status
Simulation time 42809475 ps
CPU time 0.55 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:43 PM PDT 24
Peak memory 182112 kb
Host smart-be797406-4943-47dc-802d-f322a382191e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513722706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2513722706
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1938074656
Short name T79
Test name
Test status
Simulation time 22267866 ps
CPU time 0.63 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 191468 kb
Host smart-d29b6269-7838-4ab4-ad68-a707c85e6ca9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938074656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1938074656
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3256083271
Short name T537
Test name
Test status
Simulation time 34020564 ps
CPU time 1.54 seconds
Started Jun 27 05:58:38 PM PDT 24
Finished Jun 27 05:58:41 PM PDT 24
Peak memory 197124 kb
Host smart-d44fa21d-424a-49ed-a691-2bd2d8bfb541
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256083271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3256083271
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2956020392
Short name T517
Test name
Test status
Simulation time 205108221 ps
CPU time 1.49 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 195120 kb
Host smart-242e2e62-343f-4762-99a6-281e486fed49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956020392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2956020392
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.909092200
Short name T574
Test name
Test status
Simulation time 148298042 ps
CPU time 0.95 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 196816 kb
Host smart-57eba701-e66e-492a-a0ca-0633a28c808a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909092200 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.909092200
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1667152317
Short name T525
Test name
Test status
Simulation time 28382904 ps
CPU time 0.62 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 182300 kb
Host smart-305bdfc8-8f06-49d5-80c4-e839141029c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667152317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1667152317
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3486668864
Short name T575
Test name
Test status
Simulation time 49921710 ps
CPU time 0.54 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:43 PM PDT 24
Peak memory 181720 kb
Host smart-43da0570-2e8a-4cfe-8403-6ac1be7d1e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486668864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3486668864
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1867002922
Short name T77
Test name
Test status
Simulation time 24522416 ps
CPU time 0.67 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:42 PM PDT 24
Peak memory 191276 kb
Host smart-0688691d-d45d-4fd3-94ff-2a2d07640750
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867002922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1867002922
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4098967243
Short name T544
Test name
Test status
Simulation time 178068162 ps
CPU time 3.02 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 197124 kb
Host smart-e5990740-f9a3-4818-9c37-80edee5a4be7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098967243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4098967243
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3750386294
Short name T493
Test name
Test status
Simulation time 159212358 ps
CPU time 1.12 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 194500 kb
Host smart-fe139eda-ec61-4e99-8b67-324c43e6f543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750386294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3750386294
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3278878145
Short name T462
Test name
Test status
Simulation time 69270196 ps
CPU time 0.73 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:46 PM PDT 24
Peak memory 193596 kb
Host smart-d906ea87-d165-4b8a-a083-429173f81fdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278878145 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3278878145
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2598609396
Short name T576
Test name
Test status
Simulation time 33776556 ps
CPU time 0.59 seconds
Started Jun 27 05:58:38 PM PDT 24
Finished Jun 27 05:58:40 PM PDT 24
Peak memory 182320 kb
Host smart-eb9fd65a-e3df-412e-9419-85b33ef1db15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598609396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2598609396
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1225757733
Short name T508
Test name
Test status
Simulation time 13258563 ps
CPU time 0.53 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:44 PM PDT 24
Peak memory 181672 kb
Host smart-6adf5149-9720-472a-a820-a0fabdbeacf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225757733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1225757733
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.977011745
Short name T39
Test name
Test status
Simulation time 39389322 ps
CPU time 0.62 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:42 PM PDT 24
Peak memory 191272 kb
Host smart-06b2b43d-a470-4a49-afbc-691659d87c6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977011745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.977011745
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1115567638
Short name T549
Test name
Test status
Simulation time 28286068 ps
CPU time 1.35 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 197148 kb
Host smart-d7dddf83-eb91-487f-8316-caaf0d020827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115567638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1115567638
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3809557314
Short name T86
Test name
Test status
Simulation time 100800383 ps
CPU time 1.28 seconds
Started Jun 27 05:58:37 PM PDT 24
Finished Jun 27 05:58:40 PM PDT 24
Peak memory 194816 kb
Host smart-e2ccb4a8-5a0d-4c34-8bd9-10ff3fc44493
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809557314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3809557314
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1645053676
Short name T497
Test name
Test status
Simulation time 55849709 ps
CPU time 1.42 seconds
Started Jun 27 05:58:41 PM PDT 24
Finished Jun 27 05:58:47 PM PDT 24
Peak memory 197140 kb
Host smart-15250b72-5cc3-4842-bece-1d7565c1b422
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645053676 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1645053676
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1844928835
Short name T498
Test name
Test status
Simulation time 21062892 ps
CPU time 0.59 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:45 PM PDT 24
Peak memory 191548 kb
Host smart-9fd9e00c-de6c-4f12-98ec-99635751469f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844928835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1844928835
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.864971754
Short name T449
Test name
Test status
Simulation time 41494413 ps
CPU time 0.53 seconds
Started Jun 27 05:58:42 PM PDT 24
Finished Jun 27 05:58:48 PM PDT 24
Peak memory 181900 kb
Host smart-c13baf6a-4011-460b-941f-79bf0086825e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864971754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.864971754
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3085037601
Short name T503
Test name
Test status
Simulation time 61206599 ps
CPU time 0.66 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:42 PM PDT 24
Peak memory 191780 kb
Host smart-f1529550-34cb-45ee-961d-5d8501f56eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085037601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3085037601
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.91563886
Short name T545
Test name
Test status
Simulation time 627090667 ps
CPU time 3.04 seconds
Started Jun 27 05:58:39 PM PDT 24
Finished Jun 27 05:58:45 PM PDT 24
Peak memory 197120 kb
Host smart-0c17d7c5-71c8-4726-9391-427cd08639b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91563886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.91563886
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3378250222
Short name T548
Test name
Test status
Simulation time 182564841 ps
CPU time 0.89 seconds
Started Jun 27 05:58:40 PM PDT 24
Finished Jun 27 05:58:45 PM PDT 24
Peak memory 182776 kb
Host smart-78313b0b-3012-4a61-a8a8-b0f18a4476bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378250222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3378250222
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1845627511
Short name T448
Test name
Test status
Simulation time 59837741365 ps
CPU time 29.49 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:48 PM PDT 24
Peak memory 183100 kb
Host smart-251428bc-e095-4010-a01f-5fb340eb00bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845627511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1845627511
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2098230140
Short name T353
Test name
Test status
Simulation time 580653595111 ps
CPU time 221.65 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 06:02:56 PM PDT 24
Peak memory 183168 kb
Host smart-33fb964a-fc44-4aa2-86ff-57fe0a587cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098230140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2098230140
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.629262974
Short name T119
Test name
Test status
Simulation time 1658307422856 ps
CPU time 474.76 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 06:07:12 PM PDT 24
Peak memory 193712 kb
Host smart-e99dba5b-f532-482e-b115-fe28e7b557f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629262974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.629262974
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1323533080
Short name T409
Test name
Test status
Simulation time 49371503123 ps
CPU time 147.5 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 06:01:48 PM PDT 24
Peak memory 183160 kb
Host smart-d453f18e-ff22-48e0-8e2a-c4478d99cf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323533080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1323533080
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.859805922
Short name T45
Test name
Test status
Simulation time 1295820736024 ps
CPU time 490.23 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 06:07:27 PM PDT 24
Peak memory 196476 kb
Host smart-5ed3cb83-806c-4fb0-97a7-68ebff326ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859805922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.859805922
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3016179166
Short name T44
Test name
Test status
Simulation time 22861873861 ps
CPU time 22.35 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:41 PM PDT 24
Peak memory 183164 kb
Host smart-9119d536-2b76-413d-98f9-c1b403a5bb3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016179166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3016179166
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1518389529
Short name T348
Test name
Test status
Simulation time 201674557592 ps
CPU time 249.1 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 06:03:28 PM PDT 24
Peak memory 183088 kb
Host smart-57785314-77f8-4e26-8e63-e0e8bc016ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518389529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1518389529
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2158407895
Short name T186
Test name
Test status
Simulation time 236811253576 ps
CPU time 194.81 seconds
Started Jun 27 05:59:12 PM PDT 24
Finished Jun 27 06:02:32 PM PDT 24
Peak memory 191348 kb
Host smart-697bed22-35ef-4d13-aa96-aae0e6d5e457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158407895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2158407895
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.879740992
Short name T360
Test name
Test status
Simulation time 391180371 ps
CPU time 0.68 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:22 PM PDT 24
Peak memory 183032 kb
Host smart-480585eb-0e90-4eb1-93b2-718b736632de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879740992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.879740992
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.805333601
Short name T11
Test name
Test status
Simulation time 86884115 ps
CPU time 0.75 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 05:59:22 PM PDT 24
Peak memory 214268 kb
Host smart-830bf0ba-8cdf-4184-8677-30b4aed0dcf7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805333601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.805333601
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3266864506
Short name T146
Test name
Test status
Simulation time 343419313431 ps
CPU time 180.97 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:02:34 PM PDT 24
Peak memory 183136 kb
Host smart-b5c1111c-213f-448f-81c7-9f40aa93ebc2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266864506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3266864506
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.621390648
Short name T436
Test name
Test status
Simulation time 470737558276 ps
CPU time 89.64 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 06:00:53 PM PDT 24
Peak memory 183168 kb
Host smart-7318570e-a5ac-424b-ba1e-905e543cc54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621390648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.621390648
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.1284239541
Short name T356
Test name
Test status
Simulation time 78772246 ps
CPU time 0.63 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 05:59:32 PM PDT 24
Peak memory 183012 kb
Host smart-89c978e2-f8ac-4455-8e43-7398393140cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284239541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.1284239541
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1211938463
Short name T361
Test name
Test status
Simulation time 43251086305 ps
CPU time 58.34 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:00:31 PM PDT 24
Peak memory 183128 kb
Host smart-21b62554-0f0e-4b7a-8b25-55056f628ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211938463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1211938463
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/106.rv_timer_random.1727963686
Short name T431
Test name
Test status
Simulation time 57135690223 ps
CPU time 119.48 seconds
Started Jun 27 06:00:11 PM PDT 24
Finished Jun 27 06:02:13 PM PDT 24
Peak memory 191332 kb
Host smart-81408c26-7094-486a-8275-c73451f63bee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727963686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1727963686
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1363847552
Short name T297
Test name
Test status
Simulation time 175233734672 ps
CPU time 475.01 seconds
Started Jun 27 06:00:11 PM PDT 24
Finished Jun 27 06:08:08 PM PDT 24
Peak memory 194300 kb
Host smart-e8b6d8e6-88a5-4ca3-8b56-909c83955cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363847552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1363847552
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1013632746
Short name T255
Test name
Test status
Simulation time 722060777020 ps
CPU time 336.66 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:05:45 PM PDT 24
Peak memory 191348 kb
Host smart-2c406d99-c88b-4a51-8ef8-18e589b4299b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013632746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1013632746
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3921608889
Short name T205
Test name
Test status
Simulation time 79176539755 ps
CPU time 135.39 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:01:42 PM PDT 24
Peak memory 183140 kb
Host smart-10dbe58c-8fad-4e26-ac0c-0f5976fe81a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921608889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3921608889
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2153415727
Short name T371
Test name
Test status
Simulation time 371234189724 ps
CPU time 137.57 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:01:45 PM PDT 24
Peak memory 183164 kb
Host smart-3471d10a-3f58-4e68-9dfe-49041d3faf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153415727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2153415727
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1401562418
Short name T291
Test name
Test status
Simulation time 939662183723 ps
CPU time 1217.81 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:19:44 PM PDT 24
Peak memory 191232 kb
Host smart-b57cc940-4ed5-4e54-8901-7145407eff65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401562418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1401562418
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.166307179
Short name T33
Test name
Test status
Simulation time 28088773104 ps
CPU time 307.07 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:04:33 PM PDT 24
Peak memory 205888 kb
Host smart-87c441c5-3780-4bd6-b016-448a163c8522
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166307179 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.166307179
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1233103032
Short name T191
Test name
Test status
Simulation time 132308284797 ps
CPU time 67.49 seconds
Started Jun 27 06:00:11 PM PDT 24
Finished Jun 27 06:01:21 PM PDT 24
Peak memory 183164 kb
Host smart-25b54140-b3cf-4bdc-b9a7-95a074dc7587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233103032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1233103032
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1259879075
Short name T8
Test name
Test status
Simulation time 44640153685 ps
CPU time 1658.37 seconds
Started Jun 27 06:00:24 PM PDT 24
Finished Jun 27 06:28:05 PM PDT 24
Peak memory 191344 kb
Host smart-8e1b5a0d-6721-41bb-83b1-84eda97a96d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259879075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1259879075
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2721387287
Short name T161
Test name
Test status
Simulation time 316274234425 ps
CPU time 197.57 seconds
Started Jun 27 06:00:25 PM PDT 24
Finished Jun 27 06:03:44 PM PDT 24
Peak memory 191360 kb
Host smart-38101729-c7a9-406c-b566-7883c06d0e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721387287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2721387287
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1908660761
Short name T178
Test name
Test status
Simulation time 32813877012 ps
CPU time 45.39 seconds
Started Jun 27 06:00:25 PM PDT 24
Finished Jun 27 06:01:12 PM PDT 24
Peak memory 183144 kb
Host smart-2c20d548-bb51-4de3-ba92-fd3e167abd68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908660761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1908660761
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.149087394
Short name T96
Test name
Test status
Simulation time 12247689288 ps
CPU time 17.66 seconds
Started Jun 27 06:00:25 PM PDT 24
Finished Jun 27 06:00:44 PM PDT 24
Peak memory 183132 kb
Host smart-746e4c19-9f6c-4172-8d14-8217f688344e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149087394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.149087394
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.751009336
Short name T399
Test name
Test status
Simulation time 481366629058 ps
CPU time 207.63 seconds
Started Jun 27 05:59:18 PM PDT 24
Finished Jun 27 06:02:56 PM PDT 24
Peak memory 183168 kb
Host smart-88695cdb-6473-4dc5-a7d8-6b7fc3e5dec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751009336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.751009336
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.4043520550
Short name T381
Test name
Test status
Simulation time 171992849 ps
CPU time 0.71 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 05:59:29 PM PDT 24
Peak memory 183016 kb
Host smart-01dc36df-87d1-4da2-b0d4-988ff9c38e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043520550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4043520550
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.3151604784
Short name T299
Test name
Test status
Simulation time 530749855245 ps
CPU time 417.53 seconds
Started Jun 27 06:00:24 PM PDT 24
Finished Jun 27 06:07:23 PM PDT 24
Peak memory 191356 kb
Host smart-5caa118f-0e15-46cb-91e5-5f025edfedce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151604784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3151604784
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.231793959
Short name T338
Test name
Test status
Simulation time 296511666045 ps
CPU time 134.16 seconds
Started Jun 27 06:00:24 PM PDT 24
Finished Jun 27 06:02:39 PM PDT 24
Peak memory 191340 kb
Host smart-4eadb884-81a2-4b7b-affe-ca061b4fed2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231793959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.231793959
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1315820780
Short name T155
Test name
Test status
Simulation time 285418836757 ps
CPU time 270.52 seconds
Started Jun 27 06:00:24 PM PDT 24
Finished Jun 27 06:04:57 PM PDT 24
Peak memory 193896 kb
Host smart-7bb819a2-474c-4819-a3b6-5a546a9b06cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315820780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1315820780
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2332989023
Short name T322
Test name
Test status
Simulation time 106810219622 ps
CPU time 98.75 seconds
Started Jun 27 06:00:25 PM PDT 24
Finished Jun 27 06:02:05 PM PDT 24
Peak memory 183104 kb
Host smart-e23c7706-8b3c-4272-a51f-b153f29430ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332989023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2332989023
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1749615073
Short name T238
Test name
Test status
Simulation time 98062445366 ps
CPU time 410.01 seconds
Started Jun 27 06:00:24 PM PDT 24
Finished Jun 27 06:07:16 PM PDT 24
Peak memory 191352 kb
Host smart-9e6ee77e-2555-4c9e-92f4-b4eb7f046288
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749615073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1749615073
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1952229586
Short name T165
Test name
Test status
Simulation time 851828691220 ps
CPU time 792.02 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:12:39 PM PDT 24
Peak memory 183016 kb
Host smart-ef72191c-44ee-49d0-9d9a-ec62a465113a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952229586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1952229586
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1391097667
Short name T375
Test name
Test status
Simulation time 64314067100 ps
CPU time 64.42 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:00:33 PM PDT 24
Peak memory 183180 kb
Host smart-b9cad9da-7beb-41b3-b4f8-791207cf1c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391097667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1391097667
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2409877422
Short name T268
Test name
Test status
Simulation time 20593257545 ps
CPU time 34.68 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:00:02 PM PDT 24
Peak memory 183104 kb
Host smart-53ed6101-7876-4644-bae2-4385d87c4029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409877422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2409877422
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.379461933
Short name T376
Test name
Test status
Simulation time 4874488424 ps
CPU time 8.93 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 05:59:37 PM PDT 24
Peak memory 183120 kb
Host smart-1af20cbc-beee-4747-b8e1-2ef74208b925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379461933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.379461933
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3260005408
Short name T368
Test name
Test status
Simulation time 194924540726 ps
CPU time 157.02 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:02:03 PM PDT 24
Peak memory 183140 kb
Host smart-b5191fad-0d3a-4cf7-a4d3-4cfbf03fb4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260005408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3260005408
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.2312229129
Short name T36
Test name
Test status
Simulation time 41258168320 ps
CPU time 307.41 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:04:32 PM PDT 24
Peak memory 206056 kb
Host smart-c457386f-8d37-4aa6-8144-36e69b818492
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312229129 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.2312229129
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.877249192
Short name T296
Test name
Test status
Simulation time 107950918823 ps
CPU time 194.33 seconds
Started Jun 27 06:00:24 PM PDT 24
Finished Jun 27 06:03:40 PM PDT 24
Peak memory 191300 kb
Host smart-c50850fb-41df-4e3b-9797-20154eb32f2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877249192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.877249192
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2945980896
Short name T309
Test name
Test status
Simulation time 23888106073 ps
CPU time 44.76 seconds
Started Jun 27 06:00:26 PM PDT 24
Finished Jun 27 06:01:13 PM PDT 24
Peak memory 191368 kb
Host smart-1206c1dc-cf89-4515-9f19-24fa84a5583b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945980896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2945980896
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1397932738
Short name T93
Test name
Test status
Simulation time 1054841303521 ps
CPU time 370.92 seconds
Started Jun 27 06:00:26 PM PDT 24
Finished Jun 27 06:06:39 PM PDT 24
Peak memory 191360 kb
Host smart-e5e33ede-0ef3-430d-a40a-5e2074cf301d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397932738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1397932738
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3094864972
Short name T18
Test name
Test status
Simulation time 161617045974 ps
CPU time 219.81 seconds
Started Jun 27 06:00:25 PM PDT 24
Finished Jun 27 06:04:06 PM PDT 24
Peak memory 191380 kb
Host smart-e11b08c1-2ac5-4fec-9b29-d71cd4f04af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094864972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3094864972
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.768203512
Short name T261
Test name
Test status
Simulation time 288891939362 ps
CPU time 1082.89 seconds
Started Jun 27 06:00:28 PM PDT 24
Finished Jun 27 06:18:32 PM PDT 24
Peak memory 191312 kb
Host smart-d65a8a5f-1de4-462c-a5d5-ebf5dd7ea58a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768203512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.768203512
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1952197999
Short name T266
Test name
Test status
Simulation time 170484546893 ps
CPU time 347.21 seconds
Started Jun 27 06:00:27 PM PDT 24
Finished Jun 27 06:06:16 PM PDT 24
Peak memory 183160 kb
Host smart-5a99fba0-4d14-4fda-9c6d-d9a17986ea0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952197999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1952197999
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1251362989
Short name T244
Test name
Test status
Simulation time 21486580129 ps
CPU time 33.99 seconds
Started Jun 27 06:00:25 PM PDT 24
Finished Jun 27 06:01:00 PM PDT 24
Peak memory 183168 kb
Host smart-1a6ca953-c953-46f0-8ce4-2a19e01b2e19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251362989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1251362989
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2537636925
Short name T420
Test name
Test status
Simulation time 175253663964 ps
CPU time 647.64 seconds
Started Jun 27 06:00:26 PM PDT 24
Finished Jun 27 06:11:16 PM PDT 24
Peak memory 191368 kb
Host smart-610d7d9a-007b-4db3-944c-1b93d0451f2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537636925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2537636925
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.141551679
Short name T390
Test name
Test status
Simulation time 387275843998 ps
CPU time 324.1 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:05:00 PM PDT 24
Peak memory 183072 kb
Host smart-6c8d9bbb-1c5c-4399-b8e5-3f3b4747bafc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141551679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.141551679
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2766036288
Short name T385
Test name
Test status
Simulation time 878560422994 ps
CPU time 367.07 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:05:43 PM PDT 24
Peak memory 182880 kb
Host smart-9a4528e4-422a-4ae6-b166-83802bf931f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766036288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2766036288
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3344583296
Short name T89
Test name
Test status
Simulation time 43231150027 ps
CPU time 49.82 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:00:26 PM PDT 24
Peak memory 191268 kb
Host smart-6c6c6103-64d8-44ed-be15-694702829174
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344583296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3344583296
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3739261549
Short name T444
Test name
Test status
Simulation time 75098619435 ps
CPU time 29.12 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:00:02 PM PDT 24
Peak memory 194276 kb
Host smart-43b4c710-64fa-4776-b9ac-8f05dc53a087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739261549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3739261549
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.532827279
Short name T386
Test name
Test status
Simulation time 35740429 ps
CPU time 0.63 seconds
Started Jun 27 05:59:23 PM PDT 24
Finished Jun 27 05:59:34 PM PDT 24
Peak memory 182704 kb
Host smart-34105a27-e434-4f65-be41-15156cb08ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532827279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
532827279
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.2215859232
Short name T38
Test name
Test status
Simulation time 46493916940 ps
CPU time 82.98 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:00:55 PM PDT 24
Peak memory 206072 kb
Host smart-871d792b-5747-4a7b-a0c9-ade8f22199b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215859232 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.2215859232
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.229642274
Short name T173
Test name
Test status
Simulation time 125422633256 ps
CPU time 187.04 seconds
Started Jun 27 06:00:26 PM PDT 24
Finished Jun 27 06:03:35 PM PDT 24
Peak memory 191268 kb
Host smart-8e6c9b2c-7d89-41ef-9b78-ab142bb9f95a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229642274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.229642274
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3237687991
Short name T253
Test name
Test status
Simulation time 226239962342 ps
CPU time 175.87 seconds
Started Jun 27 06:00:27 PM PDT 24
Finished Jun 27 06:03:25 PM PDT 24
Peak memory 194764 kb
Host smart-d8f51ba7-5a3b-412b-8cd4-350671aaea5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237687991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3237687991
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3964258517
Short name T287
Test name
Test status
Simulation time 417371357310 ps
CPU time 180.36 seconds
Started Jun 27 06:00:28 PM PDT 24
Finished Jun 27 06:03:29 PM PDT 24
Peak memory 191312 kb
Host smart-80295030-4006-4afc-baee-0fa1fa693f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964258517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3964258517
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1589941155
Short name T285
Test name
Test status
Simulation time 217691053461 ps
CPU time 85.72 seconds
Started Jun 27 06:00:47 PM PDT 24
Finished Jun 27 06:02:14 PM PDT 24
Peak memory 191328 kb
Host smart-2829f2b2-068c-4089-aa75-bfb5e3fa752a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589941155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1589941155
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1485539634
Short name T175
Test name
Test status
Simulation time 322119112265 ps
CPU time 117.32 seconds
Started Jun 27 06:00:41 PM PDT 24
Finished Jun 27 06:02:40 PM PDT 24
Peak memory 191348 kb
Host smart-c60c541a-e080-46b4-9819-ce791da46bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485539634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1485539634
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.383461133
Short name T112
Test name
Test status
Simulation time 283552540521 ps
CPU time 444.97 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:07:01 PM PDT 24
Peak memory 183152 kb
Host smart-15262b11-6bf3-442a-9276-d279bf3f2f0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383461133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.383461133
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2057390353
Short name T424
Test name
Test status
Simulation time 67971871801 ps
CPU time 68.01 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:00:41 PM PDT 24
Peak memory 183140 kb
Host smart-a05e8cdd-a529-4fd0-b107-7d3b9229a887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057390353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2057390353
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.821676345
Short name T269
Test name
Test status
Simulation time 208129844399 ps
CPU time 1775.34 seconds
Started Jun 27 05:59:24 PM PDT 24
Finished Jun 27 06:29:10 PM PDT 24
Peak memory 191332 kb
Host smart-44ef0f51-7e7a-4789-b5bc-fa2edc80de90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821676345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.821676345
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3776389558
Short name T337
Test name
Test status
Simulation time 21743914107 ps
CPU time 30.83 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:00:07 PM PDT 24
Peak memory 191112 kb
Host smart-e9a50109-2fcd-4d4b-a760-a2fa3b96dd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776389558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3776389558
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.3265250249
Short name T192
Test name
Test status
Simulation time 543018462006 ps
CPU time 504.37 seconds
Started Jun 27 06:00:45 PM PDT 24
Finished Jun 27 06:09:10 PM PDT 24
Peak memory 191324 kb
Host smart-d78e6412-04ee-40f9-b6b5-2aae1ddc4a44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265250249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3265250249
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1917368477
Short name T277
Test name
Test status
Simulation time 121676312982 ps
CPU time 553.52 seconds
Started Jun 27 06:00:40 PM PDT 24
Finished Jun 27 06:09:55 PM PDT 24
Peak memory 194652 kb
Host smart-59a14292-e819-419f-a5d4-3170c99849be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917368477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1917368477
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.17715941
Short name T423
Test name
Test status
Simulation time 192200687796 ps
CPU time 67.25 seconds
Started Jun 27 06:00:44 PM PDT 24
Finished Jun 27 06:01:53 PM PDT 24
Peak memory 191348 kb
Host smart-8afed2d1-bd5f-4da7-b0b8-fa2a8f6ba56c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17715941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.17715941
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1322802983
Short name T295
Test name
Test status
Simulation time 78837578372 ps
CPU time 81.31 seconds
Started Jun 27 06:00:43 PM PDT 24
Finished Jun 27 06:02:06 PM PDT 24
Peak memory 191312 kb
Host smart-f2847b4f-c8a8-4c36-b819-2ddb4d43f998
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322802983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1322802983
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1285933392
Short name T336
Test name
Test status
Simulation time 101960824928 ps
CPU time 103.63 seconds
Started Jun 27 06:00:47 PM PDT 24
Finished Jun 27 06:02:32 PM PDT 24
Peak memory 183128 kb
Host smart-5785b581-b8ce-47bc-a5ea-b5143e635edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285933392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1285933392
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.937073638
Short name T411
Test name
Test status
Simulation time 74067075747 ps
CPU time 56.46 seconds
Started Jun 27 06:00:43 PM PDT 24
Finished Jun 27 06:01:41 PM PDT 24
Peak memory 183156 kb
Host smart-1fa3a600-1bb8-4407-b1a1-0fb899017fb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937073638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.937073638
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2005876789
Short name T182
Test name
Test status
Simulation time 130853434178 ps
CPU time 233.63 seconds
Started Jun 27 06:00:43 PM PDT 24
Finished Jun 27 06:04:38 PM PDT 24
Peak memory 191304 kb
Host smart-3782fe20-c6b9-47b7-92ab-1eb2d8b0aba4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005876789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2005876789
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3521065723
Short name T418
Test name
Test status
Simulation time 355833237149 ps
CPU time 195.46 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 06:02:46 PM PDT 24
Peak memory 183156 kb
Host smart-bea1311b-0ca0-4198-87e8-7f4cd80ce318
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521065723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3521065723
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1631094944
Short name T5
Test name
Test status
Simulation time 329712963392 ps
CPU time 215.07 seconds
Started Jun 27 05:59:29 PM PDT 24
Finished Jun 27 06:03:13 PM PDT 24
Peak memory 182880 kb
Host smart-a9c89743-1b4e-4756-8fde-8064b38428ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631094944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1631094944
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2483551165
Short name T116
Test name
Test status
Simulation time 89691903649 ps
CPU time 162.6 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 06:02:13 PM PDT 24
Peak memory 191352 kb
Host smart-a5cf2bf0-4d6a-4b48-8db0-198558d728ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483551165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2483551165
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.205499254
Short name T401
Test name
Test status
Simulation time 1923822477 ps
CPU time 3.15 seconds
Started Jun 27 05:59:26 PM PDT 24
Finished Jun 27 05:59:39 PM PDT 24
Peak memory 182964 kb
Host smart-8d3b8cd0-4c24-429c-97c9-85d8cfdf5b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205499254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.205499254
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1807560562
Short name T264
Test name
Test status
Simulation time 87737338579 ps
CPU time 235.49 seconds
Started Jun 27 06:00:42 PM PDT 24
Finished Jun 27 06:04:40 PM PDT 24
Peak memory 191368 kb
Host smart-4bc7b840-051b-4b97-a480-9c1c936ddd69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807560562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1807560562
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2665875539
Short name T113
Test name
Test status
Simulation time 49328533645 ps
CPU time 81.41 seconds
Started Jun 27 06:00:40 PM PDT 24
Finished Jun 27 06:02:04 PM PDT 24
Peak memory 183080 kb
Host smart-b4908abd-5f6a-445d-b81d-420fb38ed7b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665875539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2665875539
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2014400992
Short name T187
Test name
Test status
Simulation time 58556853167 ps
CPU time 101.45 seconds
Started Jun 27 06:00:40 PM PDT 24
Finished Jun 27 06:02:23 PM PDT 24
Peak memory 191260 kb
Host smart-89cef706-c7e1-4909-b375-73d51fd69db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014400992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2014400992
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2558076751
Short name T438
Test name
Test status
Simulation time 186299901009 ps
CPU time 1391.18 seconds
Started Jun 27 06:00:41 PM PDT 24
Finished Jun 27 06:23:55 PM PDT 24
Peak memory 191344 kb
Host smart-08ba16e8-6534-4ab3-9d6b-204faabbc39b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558076751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2558076751
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3482809587
Short name T213
Test name
Test status
Simulation time 113272371096 ps
CPU time 78.32 seconds
Started Jun 27 06:00:47 PM PDT 24
Finished Jun 27 06:02:07 PM PDT 24
Peak memory 194564 kb
Host smart-a2083760-ca63-4101-a25a-a49eafdd590c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482809587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3482809587
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3865006294
Short name T139
Test name
Test status
Simulation time 144673354821 ps
CPU time 1839.39 seconds
Started Jun 27 06:00:44 PM PDT 24
Finished Jun 27 06:31:25 PM PDT 24
Peak memory 191344 kb
Host smart-1a3d5ab8-9e0e-4302-9e8d-f01c505f888f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865006294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3865006294
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3308357454
Short name T142
Test name
Test status
Simulation time 148690044353 ps
CPU time 73.98 seconds
Started Jun 27 06:00:44 PM PDT 24
Finished Jun 27 06:01:59 PM PDT 24
Peak memory 183156 kb
Host smart-c695c2ea-1561-481c-bffd-006ab8a31ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308357454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3308357454
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.4268789081
Short name T152
Test name
Test status
Simulation time 94387666204 ps
CPU time 151.25 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 06:02:02 PM PDT 24
Peak memory 183336 kb
Host smart-a6e35b8e-a2cb-4a28-b46a-9cbba2a46b51
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268789081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.4268789081
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1750337297
Short name T387
Test name
Test status
Simulation time 15671805265 ps
CPU time 23.43 seconds
Started Jun 27 05:59:18 PM PDT 24
Finished Jun 27 05:59:52 PM PDT 24
Peak memory 183172 kb
Host smart-5f0fe334-418f-4c7f-866c-f0300a40105d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750337297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1750337297
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.494185458
Short name T88
Test name
Test status
Simulation time 134422632706 ps
CPU time 640.89 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:10:13 PM PDT 24
Peak memory 191352 kb
Host smart-de256d6b-0e35-45c4-95e1-6c35df67f985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494185458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.494185458
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2672069160
Short name T223
Test name
Test status
Simulation time 124972516092 ps
CPU time 133.81 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:01:45 PM PDT 24
Peak memory 194640 kb
Host smart-b4fbfaca-5693-479b-941d-3581c063fdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672069160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2672069160
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2712582565
Short name T288
Test name
Test status
Simulation time 31276261210 ps
CPU time 81.65 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 06:00:53 PM PDT 24
Peak memory 191364 kb
Host smart-7ce6c9bc-d616-483d-979f-f5bf8c733441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712582565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2712582565
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2152691312
Short name T9
Test name
Test status
Simulation time 76394684296 ps
CPU time 604.38 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:09:40 PM PDT 24
Peak memory 206064 kb
Host smart-67d42f9d-6b3c-4db7-92da-012cc4f069eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152691312 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2152691312
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.1146612245
Short name T114
Test name
Test status
Simulation time 100631558038 ps
CPU time 103.44 seconds
Started Jun 27 06:00:58 PM PDT 24
Finished Jun 27 06:02:43 PM PDT 24
Peak memory 183164 kb
Host smart-27e954e3-ba7d-4b77-a852-2fa6c558fb7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146612245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1146612245
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1430900326
Short name T234
Test name
Test status
Simulation time 188692992665 ps
CPU time 357.14 seconds
Started Jun 27 06:01:05 PM PDT 24
Finished Jun 27 06:07:03 PM PDT 24
Peak memory 191320 kb
Host smart-cce9b17a-b37d-4e52-9b53-251fb1474322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430900326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1430900326
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.4277126841
Short name T133
Test name
Test status
Simulation time 181577684280 ps
CPU time 100.69 seconds
Started Jun 27 06:00:59 PM PDT 24
Finished Jun 27 06:02:41 PM PDT 24
Peak memory 191356 kb
Host smart-bfada3e1-d7d0-4627-ba6b-4e8550e35da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277126841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.4277126841
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.600372284
Short name T304
Test name
Test status
Simulation time 40307046888 ps
CPU time 87.9 seconds
Started Jun 27 06:00:59 PM PDT 24
Finished Jun 27 06:02:28 PM PDT 24
Peak memory 191340 kb
Host smart-458a24e7-de0e-451b-8f06-ba7570ddc4b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600372284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.600372284
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.293288361
Short name T148
Test name
Test status
Simulation time 26077787538 ps
CPU time 42.73 seconds
Started Jun 27 06:01:00 PM PDT 24
Finished Jun 27 06:01:44 PM PDT 24
Peak memory 191332 kb
Host smart-1520c703-af78-4500-9512-ab7597156fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293288361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.293288361
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2961343191
Short name T433
Test name
Test status
Simulation time 254482565261 ps
CPU time 537.64 seconds
Started Jun 27 06:00:57 PM PDT 24
Finished Jun 27 06:09:56 PM PDT 24
Peak memory 191356 kb
Host smart-8334acc0-604a-463c-a3df-d500c384044a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961343191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2961343191
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3229940045
Short name T176
Test name
Test status
Simulation time 711808283194 ps
CPU time 706.81 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:11:19 PM PDT 24
Peak memory 183116 kb
Host smart-404c18e6-da25-4e52-90b5-926a82f20926
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229940045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3229940045
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1620146997
Short name T392
Test name
Test status
Simulation time 55742857709 ps
CPU time 33.23 seconds
Started Jun 27 05:59:23 PM PDT 24
Finished Jun 27 06:00:07 PM PDT 24
Peak memory 182812 kb
Host smart-14153995-1e52-4a0c-93a3-158efe4a1e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620146997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1620146997
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2904742886
Short name T252
Test name
Test status
Simulation time 466208464078 ps
CPU time 619.48 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:09:53 PM PDT 24
Peak memory 191328 kb
Host smart-3fd54ed6-6411-48f3-9bbb-c708c5d768c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904742886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2904742886
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3755796144
Short name T171
Test name
Test status
Simulation time 121029958978 ps
CPU time 70.93 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:00:47 PM PDT 24
Peak memory 191176 kb
Host smart-b330e301-69b0-4a7a-8053-8ed9c006c93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755796144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3755796144
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1186138007
Short name T413
Test name
Test status
Simulation time 16195634737 ps
CPU time 34.18 seconds
Started Jun 27 06:00:58 PM PDT 24
Finished Jun 27 06:01:34 PM PDT 24
Peak memory 183132 kb
Host smart-ca07d8fa-668d-48da-a2fe-7cc452469c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186138007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1186138007
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3607981220
Short name T430
Test name
Test status
Simulation time 188697102804 ps
CPU time 97.45 seconds
Started Jun 27 06:00:57 PM PDT 24
Finished Jun 27 06:02:36 PM PDT 24
Peak memory 191368 kb
Host smart-53783242-9e47-40bb-932d-70d47ebf302f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607981220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3607981220
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.920057079
Short name T218
Test name
Test status
Simulation time 59762944444 ps
CPU time 115.96 seconds
Started Jun 27 06:00:58 PM PDT 24
Finished Jun 27 06:02:55 PM PDT 24
Peak memory 191356 kb
Host smart-58fab85d-b2d0-47fc-8f30-bd587eca4113
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920057079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.920057079
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1036411037
Short name T237
Test name
Test status
Simulation time 249023144778 ps
CPU time 244.63 seconds
Started Jun 27 06:01:04 PM PDT 24
Finished Jun 27 06:05:10 PM PDT 24
Peak memory 191328 kb
Host smart-96115852-a49b-4d4f-a3e0-f922c5348ffb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036411037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1036411037
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.335511012
Short name T20
Test name
Test status
Simulation time 27169571132 ps
CPU time 37.53 seconds
Started Jun 27 06:01:05 PM PDT 24
Finished Jun 27 06:01:43 PM PDT 24
Peak memory 183128 kb
Host smart-b2fb9bb8-0d3a-4ef0-bb4a-7fce2f6b2ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335511012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.335511012
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1691519615
Short name T226
Test name
Test status
Simulation time 43569070329 ps
CPU time 73.18 seconds
Started Jun 27 06:00:59 PM PDT 24
Finished Jun 27 06:02:14 PM PDT 24
Peak memory 191264 kb
Host smart-301642d3-019f-4899-806c-4c0264d5b100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691519615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1691519615
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3518641119
Short name T369
Test name
Test status
Simulation time 5345793380 ps
CPU time 8.99 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 05:59:40 PM PDT 24
Peak memory 183160 kb
Host smart-69dcfc30-52cd-47bd-ab77-9ac0b8d08ce8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518641119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3518641119
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3620249585
Short name T362
Test name
Test status
Simulation time 37772996608 ps
CPU time 57.63 seconds
Started Jun 27 05:59:23 PM PDT 24
Finished Jun 27 06:00:32 PM PDT 24
Peak memory 183324 kb
Host smart-6e7dc280-6ab4-43ff-b983-c3b3a7ad988f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620249585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3620249585
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.193491577
Short name T111
Test name
Test status
Simulation time 149103776821 ps
CPU time 880.6 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 06:14:11 PM PDT 24
Peak memory 191352 kb
Host smart-ea6d321f-d882-4f28-8883-8e44cb715503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193491577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.193491577
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.4808566
Short name T425
Test name
Test status
Simulation time 219903366385 ps
CPU time 94.8 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:01:07 PM PDT 24
Peak memory 183144 kb
Host smart-f557e942-2809-4751-b82d-594fa112a4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4808566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.4808566
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.4127498050
Short name T331
Test name
Test status
Simulation time 102342330711 ps
CPU time 798.83 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 06:12:50 PM PDT 24
Peak memory 209388 kb
Host smart-40b0ceaf-d0bb-4d65-be18-d26912d27536
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127498050 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.4127498050
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.1867343681
Short name T308
Test name
Test status
Simulation time 68663857169 ps
CPU time 92.01 seconds
Started Jun 27 06:01:05 PM PDT 24
Finished Jun 27 06:02:37 PM PDT 24
Peak memory 191328 kb
Host smart-cd5543ee-1ff2-4182-99f8-383ce4fb8ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867343681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1867343681
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3915327654
Short name T24
Test name
Test status
Simulation time 49867223903 ps
CPU time 394.83 seconds
Started Jun 27 06:01:34 PM PDT 24
Finished Jun 27 06:08:09 PM PDT 24
Peak memory 183112 kb
Host smart-2ad4f82a-577e-4ac6-8d91-d024fb7189aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915327654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3915327654
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3514455101
Short name T446
Test name
Test status
Simulation time 19446297262 ps
CPU time 32.9 seconds
Started Jun 27 06:01:35 PM PDT 24
Finished Jun 27 06:02:09 PM PDT 24
Peak memory 183168 kb
Host smart-b89deb70-2d53-4f7e-8649-7659d2aee28f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514455101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3514455101
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2021326977
Short name T404
Test name
Test status
Simulation time 169514963614 ps
CPU time 105.53 seconds
Started Jun 27 06:01:27 PM PDT 24
Finished Jun 27 06:03:13 PM PDT 24
Peak memory 183152 kb
Host smart-2eec2b98-3dd2-4059-86e4-1da83c6f554a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021326977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2021326977
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1385924909
Short name T4
Test name
Test status
Simulation time 66807733838 ps
CPU time 54.63 seconds
Started Jun 27 06:01:35 PM PDT 24
Finished Jun 27 06:02:31 PM PDT 24
Peak memory 183104 kb
Host smart-e9f4fbff-6ea1-4647-851e-a8e6e80d8845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385924909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1385924909
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2999331953
Short name T159
Test name
Test status
Simulation time 179576806511 ps
CPU time 214.09 seconds
Started Jun 27 06:01:27 PM PDT 24
Finished Jun 27 06:05:02 PM PDT 24
Peak memory 191332 kb
Host smart-587f2772-9049-4100-bdc3-d5a7d8b81794
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999331953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2999331953
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2686752696
Short name T188
Test name
Test status
Simulation time 334848250468 ps
CPU time 882.06 seconds
Started Jun 27 06:01:29 PM PDT 24
Finished Jun 27 06:16:12 PM PDT 24
Peak memory 191300 kb
Host smart-c0a342ea-eea9-4e26-9626-ce1cec8105ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686752696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2686752696
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1069933476
Short name T374
Test name
Test status
Simulation time 150620179603 ps
CPU time 196.63 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:02:42 PM PDT 24
Peak memory 183180 kb
Host smart-c7d6e302-f04b-4e63-98d4-f7e7ef164148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069933476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1069933476
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3502262307
Short name T103
Test name
Test status
Simulation time 39118137772 ps
CPU time 64.66 seconds
Started Jun 27 05:59:13 PM PDT 24
Finished Jun 27 06:00:24 PM PDT 24
Peak memory 183096 kb
Host smart-b6db874e-a171-4fac-8a73-0c6dcd15d679
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502262307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3502262307
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.392720760
Short name T347
Test name
Test status
Simulation time 754392029 ps
CPU time 1.18 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 05:59:25 PM PDT 24
Peak memory 191308 kb
Host smart-cdb59282-30c7-4ef8-9a72-4f7283659d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392720760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.392720760
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.540075535
Short name T13
Test name
Test status
Simulation time 29872624 ps
CPU time 0.73 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 05:59:28 PM PDT 24
Peak memory 213364 kb
Host smart-4fb1c3fb-9d7e-47cd-b5fe-5697d4f26549
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540075535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.540075535
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.1609462496
Short name T34
Test name
Test status
Simulation time 29018805505 ps
CPU time 216.46 seconds
Started Jun 27 05:59:14 PM PDT 24
Finished Jun 27 06:02:59 PM PDT 24
Peak memory 197860 kb
Host smart-8431c67d-c479-4a38-a16e-64c832e613c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609462496 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.1609462496
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2619301622
Short name T125
Test name
Test status
Simulation time 61571496624 ps
CPU time 90.48 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:01:02 PM PDT 24
Peak memory 183140 kb
Host smart-da7257d2-a772-46c4-9eec-e94144636761
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619301622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2619301622
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.345684049
Short name T379
Test name
Test status
Simulation time 245734703895 ps
CPU time 266.98 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:04:00 PM PDT 24
Peak memory 183128 kb
Host smart-75938d8e-2dd3-4a11-a461-c2182e4f9283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345684049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.345684049
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3028649519
Short name T207
Test name
Test status
Simulation time 149266409077 ps
CPU time 333.12 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:05:09 PM PDT 24
Peak memory 191368 kb
Host smart-6d0e4eb6-9b6a-40fd-ba5e-4c8557ba2fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028649519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3028649519
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3170691799
Short name T201
Test name
Test status
Simulation time 58988768736 ps
CPU time 111.39 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:01:25 PM PDT 24
Peak memory 183100 kb
Host smart-4f3eac40-8bcc-4895-9c20-c657badce2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170691799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3170691799
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2528218288
Short name T382
Test name
Test status
Simulation time 54279926 ps
CPU time 0.6 seconds
Started Jun 27 05:59:23 PM PDT 24
Finished Jun 27 05:59:35 PM PDT 24
Peak memory 183168 kb
Host smart-bb3c80df-690c-409b-8dc7-00d7bc9cab8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528218288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2528218288
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.2764540818
Short name T35
Test name
Test status
Simulation time 18070611494 ps
CPU time 196.42 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:02:49 PM PDT 24
Peak memory 197952 kb
Host smart-b78680e5-9b85-4172-b8fd-c49af0aa926a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764540818 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.2764540818
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.137041228
Short name T378
Test name
Test status
Simulation time 216644144246 ps
CPU time 160.45 seconds
Started Jun 27 05:59:20 PM PDT 24
Finished Jun 27 06:02:11 PM PDT 24
Peak memory 183180 kb
Host smart-3ed114db-879a-426c-8486-1534dc01e68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137041228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.137041228
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2011892150
Short name T276
Test name
Test status
Simulation time 114544662849 ps
CPU time 116.24 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:01:28 PM PDT 24
Peak memory 191364 kb
Host smart-2a1412ea-66bc-461a-bad1-602a46d9a645
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011892150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2011892150
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3903410969
Short name T23
Test name
Test status
Simulation time 43840225043 ps
CPU time 152.2 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:02:08 PM PDT 24
Peak memory 191388 kb
Host smart-27002237-8f65-4138-9d98-c1d2c1973f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903410969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3903410969
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.948466279
Short name T215
Test name
Test status
Simulation time 713800784100 ps
CPU time 937.79 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:15:14 PM PDT 24
Peak memory 191324 kb
Host smart-b197cc9b-e153-42f1-9d3a-20bee5abc548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948466279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
948466279
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3802560554
Short name T1
Test name
Test status
Simulation time 59173665179 ps
CPU time 78.22 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:00:52 PM PDT 24
Peak memory 183112 kb
Host smart-06110b66-f137-430f-8564-9a83f3318d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802560554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3802560554
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3888603155
Short name T241
Test name
Test status
Simulation time 45503635631 ps
CPU time 58.59 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:00:35 PM PDT 24
Peak memory 183044 kb
Host smart-2bb93912-f15a-4bae-bec5-b641eff11696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888603155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3888603155
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.123030665
Short name T384
Test name
Test status
Simulation time 19590361680 ps
CPU time 36.31 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:00:09 PM PDT 24
Peak memory 191328 kb
Host smart-30352103-c144-4c14-912a-311ade4fb9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123030665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.123030665
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.571490068
Short name T286
Test name
Test status
Simulation time 529587457425 ps
CPU time 492.37 seconds
Started Jun 27 05:59:28 PM PDT 24
Finished Jun 27 06:07:50 PM PDT 24
Peak memory 183060 kb
Host smart-6e739521-33ae-46b1-a3af-289854dfde63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571490068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.571490068
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.151629115
Short name T388
Test name
Test status
Simulation time 400387317008 ps
CPU time 144.01 seconds
Started Jun 27 05:59:26 PM PDT 24
Finished Jun 27 06:02:00 PM PDT 24
Peak memory 183172 kb
Host smart-022556f7-6717-48ac-989b-888fa6f48daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151629115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.151629115
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3283408231
Short name T128
Test name
Test status
Simulation time 493309727891 ps
CPU time 420.33 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:06:36 PM PDT 24
Peak memory 191332 kb
Host smart-d38cded7-cde7-4c52-aa0e-7bd68fdf489d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283408231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3283408231
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.388989552
Short name T56
Test name
Test status
Simulation time 111488683588 ps
CPU time 505.85 seconds
Started Jun 27 05:59:28 PM PDT 24
Finished Jun 27 06:08:04 PM PDT 24
Peak memory 191260 kb
Host smart-fdef6ab7-da5b-425a-abc7-29de8204f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388989552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.388989552
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.823131202
Short name T335
Test name
Test status
Simulation time 29800576888 ps
CPU time 15.46 seconds
Started Jun 27 05:59:28 PM PDT 24
Finished Jun 27 05:59:53 PM PDT 24
Peak memory 182928 kb
Host smart-73b33594-e416-40e3-b6e6-7ebdd9d88f2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823131202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.823131202
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1012169653
Short name T412
Test name
Test status
Simulation time 66556466457 ps
CPU time 99.7 seconds
Started Jun 27 05:59:19 PM PDT 24
Finished Jun 27 06:01:10 PM PDT 24
Peak memory 183176 kb
Host smart-109b32e7-05cd-4a9d-b5ef-7a289132cfb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012169653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1012169653
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3084585978
Short name T333
Test name
Test status
Simulation time 69621433792 ps
CPU time 138.23 seconds
Started Jun 27 05:59:28 PM PDT 24
Finished Jun 27 06:01:56 PM PDT 24
Peak memory 183076 kb
Host smart-d8b7346a-052f-45bf-977a-ed5522bd157e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084585978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3084585978
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.4076795369
Short name T212
Test name
Test status
Simulation time 29731831376 ps
CPU time 351.4 seconds
Started Jun 27 05:59:27 PM PDT 24
Finished Jun 27 06:05:28 PM PDT 24
Peak memory 183088 kb
Host smart-ee62be49-bc96-4d1b-9946-04ac63a1f7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076795369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.4076795369
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.323036158
Short name T443
Test name
Test status
Simulation time 38010621684 ps
CPU time 58.67 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:00:33 PM PDT 24
Peak memory 183104 kb
Host smart-2fe4a307-dc3e-4fdc-9155-ae2d805fd9dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323036158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.323036158
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3185115808
Short name T42
Test name
Test status
Simulation time 134761575034 ps
CPU time 169.29 seconds
Started Jun 27 05:59:29 PM PDT 24
Finished Jun 27 06:02:28 PM PDT 24
Peak memory 183172 kb
Host smart-32dea07f-651f-477a-932a-e5b24fa53589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185115808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3185115808
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.548698609
Short name T440
Test name
Test status
Simulation time 43309667466 ps
CPU time 70.67 seconds
Started Jun 27 05:59:22 PM PDT 24
Finished Jun 27 06:00:44 PM PDT 24
Peak memory 183180 kb
Host smart-5fb40546-f781-42d2-b768-52a02628d3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548698609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.548698609
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.703396057
Short name T55
Test name
Test status
Simulation time 14237525785 ps
CPU time 24.88 seconds
Started Jun 27 05:59:30 PM PDT 24
Finished Jun 27 06:00:04 PM PDT 24
Peak memory 183152 kb
Host smart-596642ae-0767-4c20-8db8-1c7b0709809d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703396057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.703396057
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_random.231502314
Short name T340
Test name
Test status
Simulation time 386175176153 ps
CPU time 1483.57 seconds
Started Jun 27 05:59:23 PM PDT 24
Finished Jun 27 06:24:17 PM PDT 24
Peak memory 191524 kb
Host smart-c513cf50-22b4-4571-8a6e-b889cf3932cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231502314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.231502314
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.387200448
Short name T59
Test name
Test status
Simulation time 147258114291 ps
CPU time 381.47 seconds
Started Jun 27 05:59:29 PM PDT 24
Finished Jun 27 06:06:00 PM PDT 24
Peak memory 183168 kb
Host smart-e2aaa762-752a-4ea2-ba9f-9e8644a6e4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387200448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.387200448
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2020712186
Short name T343
Test name
Test status
Simulation time 486699003831 ps
CPU time 456.16 seconds
Started Jun 27 05:59:26 PM PDT 24
Finished Jun 27 06:07:12 PM PDT 24
Peak memory 183128 kb
Host smart-b25237ef-f7d1-4650-906a-abae6a6b0f6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020712186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2020712186
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2797724785
Short name T366
Test name
Test status
Simulation time 345006352120 ps
CPU time 145.08 seconds
Started Jun 27 05:59:23 PM PDT 24
Finished Jun 27 06:01:59 PM PDT 24
Peak memory 183180 kb
Host smart-e32af657-a642-4801-977d-3a8c0c2fcf7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797724785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2797724785
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1979110147
Short name T294
Test name
Test status
Simulation time 297356620707 ps
CPU time 198.56 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:02:53 PM PDT 24
Peak memory 191360 kb
Host smart-5cb79c7f-4a8d-4fc6-906d-674330af7d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979110147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1979110147
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.4268022064
Short name T228
Test name
Test status
Simulation time 825059647087 ps
CPU time 526.49 seconds
Started Jun 27 05:59:26 PM PDT 24
Finished Jun 27 06:08:23 PM PDT 24
Peak memory 191352 kb
Host smart-3cea6224-c50b-4a9a-9bac-49e2fd4ceb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268022064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4268022064
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1863740357
Short name T122
Test name
Test status
Simulation time 169169001953 ps
CPU time 66.76 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:00:43 PM PDT 24
Peak memory 183168 kb
Host smart-c425e5b2-4e04-441f-949c-a013c464fc3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863740357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1863740357
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random.3073404028
Short name T314
Test name
Test status
Simulation time 4645281961 ps
CPU time 8.76 seconds
Started Jun 27 05:59:24 PM PDT 24
Finished Jun 27 05:59:43 PM PDT 24
Peak memory 183136 kb
Host smart-9dfa40d0-c151-4908-af12-7c4f72b86703
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073404028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3073404028
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2277585857
Short name T279
Test name
Test status
Simulation time 22427386838 ps
CPU time 42.52 seconds
Started Jun 27 05:59:21 PM PDT 24
Finished Jun 27 06:00:14 PM PDT 24
Peak memory 183176 kb
Host smart-288c1c82-89d1-4810-b4cd-8c1ba5add169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277585857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2277585857
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1886024483
Short name T179
Test name
Test status
Simulation time 564256696362 ps
CPU time 477.82 seconds
Started Jun 27 05:59:29 PM PDT 24
Finished Jun 27 06:07:36 PM PDT 24
Peak memory 183148 kb
Host smart-1daa4ac9-b826-4f00-885d-36301d3e054d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886024483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1886024483
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3284663210
Short name T357
Test name
Test status
Simulation time 396102129632 ps
CPU time 166.57 seconds
Started Jun 27 05:59:27 PM PDT 24
Finished Jun 27 06:02:23 PM PDT 24
Peak memory 183144 kb
Host smart-dfb6da16-6a37-4544-9e8b-b96b819ad7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284663210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3284663210
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1161355976
Short name T249
Test name
Test status
Simulation time 131357796418 ps
CPU time 168.72 seconds
Started Jun 27 05:59:24 PM PDT 24
Finished Jun 27 06:02:23 PM PDT 24
Peak memory 191380 kb
Host smart-66ffc40e-2bf1-41a6-8347-804cb86e93eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161355976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1161355976
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.997352832
Short name T447
Test name
Test status
Simulation time 293647412 ps
CPU time 0.61 seconds
Started Jun 27 05:59:30 PM PDT 24
Finished Jun 27 05:59:39 PM PDT 24
Peak memory 183020 kb
Host smart-fbd84106-2320-40d1-8f73-9f275d67d7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997352832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.997352832
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3253786248
Short name T61
Test name
Test status
Simulation time 395859340595 ps
CPU time 479.55 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 06:07:24 PM PDT 24
Peak memory 183136 kb
Host smart-172285d6-bce1-484e-8252-72894bbc7d67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253786248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3253786248
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2396446633
Short name T415
Test name
Test status
Simulation time 325773489472 ps
CPU time 128.43 seconds
Started Jun 27 05:59:18 PM PDT 24
Finished Jun 27 06:01:37 PM PDT 24
Peak memory 183112 kb
Host smart-1d505c65-0a18-4278-82ac-eaafe038ec8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396446633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2396446633
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.995796990
Short name T150
Test name
Test status
Simulation time 211292360150 ps
CPU time 654.79 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:10:21 PM PDT 24
Peak memory 191344 kb
Host smart-67fccf52-48c9-488d-98b4-cc553a2f7c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995796990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.995796990
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3268086899
Short name T217
Test name
Test status
Simulation time 224759463874 ps
CPU time 123.83 seconds
Started Jun 27 05:59:18 PM PDT 24
Finished Jun 27 06:01:33 PM PDT 24
Peak memory 191376 kb
Host smart-fe3026f4-5893-454a-abcd-8cc61584834e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268086899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3268086899
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1624292882
Short name T12
Test name
Test status
Simulation time 91066982 ps
CPU time 0.89 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 05:59:28 PM PDT 24
Peak memory 214552 kb
Host smart-b62d036d-81c6-40d9-9481-2a402e4188cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624292882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1624292882
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3347928011
Short name T198
Test name
Test status
Simulation time 425456978720 ps
CPU time 221.17 seconds
Started Jun 27 05:59:31 PM PDT 24
Finished Jun 27 06:03:21 PM PDT 24
Peak memory 183116 kb
Host smart-c48623fe-fad0-48fb-b717-8c4bfda6c7cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347928011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3347928011
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1717316921
Short name T395
Test name
Test status
Simulation time 32073293993 ps
CPU time 48.88 seconds
Started Jun 27 05:59:30 PM PDT 24
Finished Jun 27 06:00:27 PM PDT 24
Peak memory 183136 kb
Host smart-8c4090ee-f73f-4764-a7d6-3bc17e348368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717316921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1717316921
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1653609753
Short name T315
Test name
Test status
Simulation time 83858611129 ps
CPU time 71.81 seconds
Started Jun 27 05:59:29 PM PDT 24
Finished Jun 27 06:00:50 PM PDT 24
Peak memory 183132 kb
Host smart-cfa444ca-f51d-4829-8ebf-164a0f9640fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653609753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1653609753
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3403003976
Short name T328
Test name
Test status
Simulation time 42133589733 ps
CPU time 231.72 seconds
Started Jun 27 05:59:30 PM PDT 24
Finished Jun 27 06:03:31 PM PDT 24
Peak memory 191344 kb
Host smart-1cf92b7c-fab5-40fe-90ea-149f0e166cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403003976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3403003976
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2542317885
Short name T99
Test name
Test status
Simulation time 159924922784 ps
CPU time 131.01 seconds
Started Jun 27 05:59:27 PM PDT 24
Finished Jun 27 06:01:48 PM PDT 24
Peak memory 182984 kb
Host smart-19f27147-785f-4bc6-b39a-7d7a2595d96f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542317885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2542317885
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3334586625
Short name T355
Test name
Test status
Simulation time 315986856984 ps
CPU time 202.01 seconds
Started Jun 27 05:59:26 PM PDT 24
Finished Jun 27 06:02:58 PM PDT 24
Peak memory 183116 kb
Host smart-7baa1779-4ed5-41a6-968b-d8de25cf4e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334586625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3334586625
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2482438963
Short name T143
Test name
Test status
Simulation time 444370467502 ps
CPU time 298.2 seconds
Started Jun 27 05:59:30 PM PDT 24
Finished Jun 27 06:04:37 PM PDT 24
Peak memory 191332 kb
Host smart-8591dfca-95cd-4b0c-ab16-a6d397b827d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482438963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2482438963
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.401599092
Short name T120
Test name
Test status
Simulation time 244155754911 ps
CPU time 387.6 seconds
Started Jun 27 05:59:24 PM PDT 24
Finished Jun 27 06:06:02 PM PDT 24
Peak memory 183156 kb
Host smart-b0bde603-6dfe-435b-8938-b1ce6da484a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401599092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.401599092
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3021425432
Short name T367
Test name
Test status
Simulation time 74950437875 ps
CPU time 32.72 seconds
Started Jun 27 05:59:28 PM PDT 24
Finished Jun 27 06:00:10 PM PDT 24
Peak memory 183144 kb
Host smart-06c08628-995e-4cb8-a110-59c325835684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021425432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3021425432
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1967931614
Short name T439
Test name
Test status
Simulation time 1674203367 ps
CPU time 2.19 seconds
Started Jun 27 05:59:28 PM PDT 24
Finished Jun 27 05:59:40 PM PDT 24
Peak memory 182680 kb
Host smart-0bf7adea-2f3f-488e-9c4d-4286156c799f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967931614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1967931614
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2675443384
Short name T421
Test name
Test status
Simulation time 20410980 ps
CPU time 0.54 seconds
Started Jun 27 05:59:23 PM PDT 24
Finished Jun 27 05:59:35 PM PDT 24
Peak memory 182988 kb
Host smart-d0c1a05c-1a1a-45aa-ad18-ed7224288a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675443384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2675443384
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1455941949
Short name T158
Test name
Test status
Simulation time 352549576193 ps
CPU time 2305.2 seconds
Started Jun 27 05:59:43 PM PDT 24
Finished Jun 27 06:38:10 PM PDT 24
Peak memory 194908 kb
Host smart-2b40d447-1d08-4512-a4c3-62be203feb7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455941949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1455941949
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2215497024
Short name T327
Test name
Test status
Simulation time 193187944082 ps
CPU time 177.56 seconds
Started Jun 27 05:59:44 PM PDT 24
Finished Jun 27 06:02:44 PM PDT 24
Peak memory 183092 kb
Host smart-600a7f83-326d-41b1-93cb-1188df2b4ab0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215497024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2215497024
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3626063142
Short name T441
Test name
Test status
Simulation time 134951418274 ps
CPU time 170 seconds
Started Jun 27 05:59:36 PM PDT 24
Finished Jun 27 06:02:31 PM PDT 24
Peak memory 183164 kb
Host smart-37d02ecd-8459-4d56-820e-7ff7bfaf31bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626063142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3626063142
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1274924415
Short name T432
Test name
Test status
Simulation time 100924607471 ps
CPU time 281.71 seconds
Started Jun 27 05:59:34 PM PDT 24
Finished Jun 27 06:04:22 PM PDT 24
Peak memory 183080 kb
Host smart-708c9bc8-3982-4513-b91f-afeb6765d951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274924415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1274924415
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1042076577
Short name T130
Test name
Test status
Simulation time 327429997079 ps
CPU time 133.02 seconds
Started Jun 27 05:59:42 PM PDT 24
Finished Jun 27 06:01:58 PM PDT 24
Peak memory 191352 kb
Host smart-e75057ab-6612-4a42-8b59-f80c7f1ff0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042076577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1042076577
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3195692140
Short name T46
Test name
Test status
Simulation time 521953525769 ps
CPU time 779.65 seconds
Started Jun 27 05:59:37 PM PDT 24
Finished Jun 27 06:12:41 PM PDT 24
Peak memory 191360 kb
Host smart-fdf5c66c-c1cb-4481-a070-0c8d9751ba79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195692140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3195692140
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1204368129
Short name T219
Test name
Test status
Simulation time 1281960337959 ps
CPU time 645.05 seconds
Started Jun 27 05:59:36 PM PDT 24
Finished Jun 27 06:10:26 PM PDT 24
Peak memory 182992 kb
Host smart-a279e997-879b-4b1b-9fd0-6fcc7e4de597
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204368129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1204368129
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2460102596
Short name T429
Test name
Test status
Simulation time 323985203886 ps
CPU time 73.47 seconds
Started Jun 27 05:59:35 PM PDT 24
Finished Jun 27 06:00:54 PM PDT 24
Peak memory 183180 kb
Host smart-af2b38f3-fb50-4134-a521-9d44caba019e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460102596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2460102596
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3994126895
Short name T174
Test name
Test status
Simulation time 130441495403 ps
CPU time 213.04 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:03:22 PM PDT 24
Peak memory 194860 kb
Host smart-96c2c5d8-f1ca-462f-bfea-3f4d65a3cf5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994126895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3994126895
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1637048280
Short name T397
Test name
Test status
Simulation time 964028640444 ps
CPU time 331.24 seconds
Started Jun 27 05:59:42 PM PDT 24
Finished Jun 27 06:05:16 PM PDT 24
Peak memory 191324 kb
Host smart-d1c48d0b-3082-432f-80d7-0c09c4cbb3a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637048280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1637048280
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1878286875
Short name T259
Test name
Test status
Simulation time 128748505755 ps
CPU time 214.27 seconds
Started Jun 27 05:59:42 PM PDT 24
Finished Jun 27 06:03:18 PM PDT 24
Peak memory 183152 kb
Host smart-ae231788-9fea-4700-a0c7-9000b2ffd2a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878286875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1878286875
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3441139969
Short name T391
Test name
Test status
Simulation time 125463967344 ps
CPU time 185.39 seconds
Started Jun 27 05:59:44 PM PDT 24
Finished Jun 27 06:02:52 PM PDT 24
Peak memory 183184 kb
Host smart-0d504a2f-0cdd-4c48-bd1f-3f3f0ae27d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441139969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3441139969
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2115785942
Short name T398
Test name
Test status
Simulation time 43660201908 ps
CPU time 63.87 seconds
Started Jun 27 05:59:36 PM PDT 24
Finished Jun 27 06:00:45 PM PDT 24
Peak memory 183088 kb
Host smart-87424e97-22bf-45ed-b82a-948ff30ba95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115785942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2115785942
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1968808443
Short name T426
Test name
Test status
Simulation time 474722005411 ps
CPU time 334.64 seconds
Started Jun 27 05:59:44 PM PDT 24
Finished Jun 27 06:05:21 PM PDT 24
Peak memory 191316 kb
Host smart-8af5b3e8-a1a7-4638-9ef6-3b65f1187ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968808443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1968808443
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1530158776
Short name T126
Test name
Test status
Simulation time 711781354121 ps
CPU time 308.3 seconds
Started Jun 27 05:59:42 PM PDT 24
Finished Jun 27 06:04:52 PM PDT 24
Peak memory 183124 kb
Host smart-ede6dab2-335d-4b17-a83c-179295099fb9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530158776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1530158776
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3248257870
Short name T358
Test name
Test status
Simulation time 450140757523 ps
CPU time 186.64 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:03:01 PM PDT 24
Peak memory 183064 kb
Host smart-5f2b5c7c-94d8-4e9b-8642-e51fa09580af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248257870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3248257870
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3472581474
Short name T170
Test name
Test status
Simulation time 165348872326 ps
CPU time 149.95 seconds
Started Jun 27 05:59:39 PM PDT 24
Finished Jun 27 06:02:12 PM PDT 24
Peak memory 191356 kb
Host smart-fc4a01d4-17b9-4714-a9be-b232d0d57e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472581474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3472581474
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3769147425
Short name T247
Test name
Test status
Simulation time 1187199984595 ps
CPU time 453.12 seconds
Started Jun 27 05:59:48 PM PDT 24
Finished Jun 27 06:07:26 PM PDT 24
Peak memory 183040 kb
Host smart-c34d3d50-2f23-4a19-99df-212a21595efd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769147425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3769147425
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1044429942
Short name T435
Test name
Test status
Simulation time 127450627358 ps
CPU time 84.03 seconds
Started Jun 27 05:59:42 PM PDT 24
Finished Jun 27 06:01:08 PM PDT 24
Peak memory 183180 kb
Host smart-917dd9b8-79ab-4344-ba8a-884f63056b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044429942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1044429942
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2201996753
Short name T124
Test name
Test status
Simulation time 192945525518 ps
CPU time 86.6 seconds
Started Jun 27 05:59:44 PM PDT 24
Finished Jun 27 06:01:15 PM PDT 24
Peak memory 191396 kb
Host smart-a7e18a00-48c4-4840-a30c-4eaffa25d16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201996753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2201996753
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.4275856833
Short name T267
Test name
Test status
Simulation time 487010798720 ps
CPU time 1015.41 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:16:45 PM PDT 24
Peak memory 194756 kb
Host smart-55215e2f-ba5c-46e7-818b-b35eec673ce6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275856833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.4275856833
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.1544276120
Short name T31
Test name
Test status
Simulation time 55654199446 ps
CPU time 571.46 seconds
Started Jun 27 05:59:44 PM PDT 24
Finished Jun 27 06:09:18 PM PDT 24
Peak memory 206080 kb
Host smart-7d0b749d-ade5-4044-be59-83b2ccc8ab87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544276120 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.1544276120
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2672836624
Short name T248
Test name
Test status
Simulation time 2303152943292 ps
CPU time 1169.96 seconds
Started Jun 27 05:59:43 PM PDT 24
Finished Jun 27 06:19:15 PM PDT 24
Peak memory 183144 kb
Host smart-78dc47dd-9a54-43f9-89ab-54e834caa74c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672836624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2672836624
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.448355687
Short name T370
Test name
Test status
Simulation time 307190285983 ps
CPU time 117.25 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:01:47 PM PDT 24
Peak memory 183156 kb
Host smart-9446a7e4-76c7-41fd-8645-ba680806aa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448355687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.448355687
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1704067600
Short name T311
Test name
Test status
Simulation time 69100301106 ps
CPU time 395.98 seconds
Started Jun 27 05:59:50 PM PDT 24
Finished Jun 27 06:06:31 PM PDT 24
Peak memory 191252 kb
Host smart-8bedfd1d-3f4b-41a4-aedf-26e7af0421cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704067600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1704067600
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2691891661
Short name T204
Test name
Test status
Simulation time 112489175873 ps
CPU time 211.31 seconds
Started Jun 27 05:59:43 PM PDT 24
Finished Jun 27 06:03:17 PM PDT 24
Peak memory 190916 kb
Host smart-d66d0dcc-462a-459c-946e-10580c5b6feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691891661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2691891661
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4282079495
Short name T365
Test name
Test status
Simulation time 275065985551 ps
CPU time 395.32 seconds
Started Jun 27 05:59:44 PM PDT 24
Finished Jun 27 06:06:22 PM PDT 24
Peak memory 191368 kb
Host smart-5e9de81c-fff3-44fa-984a-e0c9cb777729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282079495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4282079495
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3969679433
Short name T233
Test name
Test status
Simulation time 395570549481 ps
CPU time 207.19 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:03:22 PM PDT 24
Peak memory 183144 kb
Host smart-2c986970-4092-41d0-9ca2-88dd3373d52a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969679433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3969679433
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.227204456
Short name T389
Test name
Test status
Simulation time 443971467207 ps
CPU time 120.97 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:01:50 PM PDT 24
Peak memory 183148 kb
Host smart-d1f38b30-749b-4be7-911b-4addfc0f9a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227204456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.227204456
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1615247876
Short name T60
Test name
Test status
Simulation time 254589818940 ps
CPU time 117.6 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:01:48 PM PDT 24
Peak memory 191376 kb
Host smart-53e92f8e-1ec2-406c-aeaa-6a061b7f4faf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615247876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1615247876
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1242456256
Short name T230
Test name
Test status
Simulation time 290708301673 ps
CPU time 792.56 seconds
Started Jun 27 05:59:46 PM PDT 24
Finished Jun 27 06:13:03 PM PDT 24
Peak memory 194624 kb
Host smart-72e908d6-c7e0-45f1-a32e-11d777bf5ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242456256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1242456256
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1235991188
Short name T319
Test name
Test status
Simulation time 276251084722 ps
CPU time 409.9 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:06:17 PM PDT 24
Peak memory 183140 kb
Host smart-bbf29ee0-4959-4ea8-9c92-f52eee3f33a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235991188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1235991188
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2011110668
Short name T377
Test name
Test status
Simulation time 15017164564 ps
CPU time 10.31 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 05:59:37 PM PDT 24
Peak memory 183164 kb
Host smart-0f829826-e414-406f-8cb9-4697b65cc47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011110668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2011110668
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3600982432
Short name T203
Test name
Test status
Simulation time 267560531022 ps
CPU time 249.91 seconds
Started Jun 27 05:59:11 PM PDT 24
Finished Jun 27 06:03:23 PM PDT 24
Peak memory 191380 kb
Host smart-3fc4efb2-0c8e-443c-b024-b456755cee55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600982432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3600982432
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3881411488
Short name T394
Test name
Test status
Simulation time 1081180377 ps
CPU time 1.11 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 05:59:28 PM PDT 24
Peak memory 182872 kb
Host smart-3ee402db-42b7-428a-8590-9f8b40d971a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881411488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3881411488
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3365119028
Short name T14
Test name
Test status
Simulation time 84308960 ps
CPU time 0.86 seconds
Started Jun 27 05:59:18 PM PDT 24
Finished Jun 27 05:59:30 PM PDT 24
Peak memory 214492 kb
Host smart-9ffe74fb-f266-49c1-8817-7057c1ef34cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365119028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3365119028
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2844512897
Short name T289
Test name
Test status
Simulation time 92314793130 ps
CPU time 143.79 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:02:18 PM PDT 24
Peak memory 183036 kb
Host smart-d0166be0-7745-421b-bc6d-36a856040db8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844512897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2844512897
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.472353418
Short name T414
Test name
Test status
Simulation time 137944344025 ps
CPU time 103.17 seconds
Started Jun 27 05:59:36 PM PDT 24
Finished Jun 27 06:01:24 PM PDT 24
Peak memory 183168 kb
Host smart-74533c0c-d75e-4393-a1cc-b078b2be5241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472353418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.472353418
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3716602920
Short name T123
Test name
Test status
Simulation time 77823582354 ps
CPU time 302.37 seconds
Started Jun 27 05:59:48 PM PDT 24
Finished Jun 27 06:04:56 PM PDT 24
Peak memory 192272 kb
Host smart-cdf6e547-a8c8-4c79-9472-e57d2493092e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716602920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3716602920
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3063368084
Short name T407
Test name
Test status
Simulation time 164879479 ps
CPU time 1.16 seconds
Started Jun 27 05:59:42 PM PDT 24
Finished Jun 27 05:59:46 PM PDT 24
Peak memory 183124 kb
Host smart-d4f19002-c2a8-4d0f-9f81-ef24d4993672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063368084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3063368084
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3499294235
Short name T445
Test name
Test status
Simulation time 22102034 ps
CPU time 0.55 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 05:59:55 PM PDT 24
Peak memory 182468 kb
Host smart-01af636d-4f78-407f-9eb8-2ace92860e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499294235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3499294235
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1153411379
Short name T318
Test name
Test status
Simulation time 297635508990 ps
CPU time 137.24 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:02:07 PM PDT 24
Peak memory 183164 kb
Host smart-354f17f9-7154-4aa5-99aa-31c20721693f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153411379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1153411379
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.672748147
Short name T349
Test name
Test status
Simulation time 400252282117 ps
CPU time 109.73 seconds
Started Jun 27 05:59:46 PM PDT 24
Finished Jun 27 06:01:41 PM PDT 24
Peak memory 183148 kb
Host smart-ac33515d-2604-4c00-93df-68e8e797e98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672748147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.672748147
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4028353989
Short name T221
Test name
Test status
Simulation time 734347404985 ps
CPU time 226.7 seconds
Started Jun 27 05:59:46 PM PDT 24
Finished Jun 27 06:03:38 PM PDT 24
Peak memory 191344 kb
Host smart-01b0a53d-db02-4b34-891c-7e89cf4a344d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028353989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4028353989
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2864647095
Short name T274
Test name
Test status
Simulation time 698142985655 ps
CPU time 232.6 seconds
Started Jun 27 05:59:42 PM PDT 24
Finished Jun 27 06:03:37 PM PDT 24
Peak memory 191388 kb
Host smart-f652688a-1886-4273-ac12-0d81e78c9a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864647095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2864647095
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1548248826
Short name T257
Test name
Test status
Simulation time 261792258125 ps
CPU time 432.76 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:07:07 PM PDT 24
Peak memory 195476 kb
Host smart-c70538b2-12bb-43d5-a39c-e2e4ed3efc7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548248826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1548248826
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1438683554
Short name T185
Test name
Test status
Simulation time 91236546838 ps
CPU time 53.83 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:00:48 PM PDT 24
Peak memory 183108 kb
Host smart-4ee885d0-1a6d-4128-a530-2a6bff8c59bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438683554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1438683554
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2217550395
Short name T405
Test name
Test status
Simulation time 342045609872 ps
CPU time 134.85 seconds
Started Jun 27 05:59:48 PM PDT 24
Finished Jun 27 06:02:08 PM PDT 24
Peak memory 183124 kb
Host smart-fe77d5c4-58cd-4166-a0ff-39eab15f69ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217550395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2217550395
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.490098872
Short name T316
Test name
Test status
Simulation time 7721598783 ps
CPU time 11.78 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:00:00 PM PDT 24
Peak memory 183192 kb
Host smart-4ca1f173-38b8-44e6-aa8d-c05193801f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490098872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.490098872
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1652476821
Short name T293
Test name
Test status
Simulation time 791744241640 ps
CPU time 835.87 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:13:51 PM PDT 24
Peak memory 195896 kb
Host smart-49522e8b-7657-41e5-a793-4ff93f3a8d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652476821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1652476821
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3428049565
Short name T272
Test name
Test status
Simulation time 787761906781 ps
CPU time 367.25 seconds
Started Jun 27 05:59:48 PM PDT 24
Finished Jun 27 06:06:00 PM PDT 24
Peak memory 183108 kb
Host smart-d15b9781-fb72-4e59-b434-ed47e76965c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428049565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3428049565
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1113107791
Short name T372
Test name
Test status
Simulation time 545849169025 ps
CPU time 199.37 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:03:14 PM PDT 24
Peak memory 183064 kb
Host smart-78e63fd0-8913-49a5-8361-e1e32dd21972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113107791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1113107791
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.1887433976
Short name T442
Test name
Test status
Simulation time 394891123270 ps
CPU time 427.55 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:06:57 PM PDT 24
Peak memory 190764 kb
Host smart-9c93f9d5-c8de-4067-a54f-3a00f29c101c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887433976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1887433976
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.839814606
Short name T320
Test name
Test status
Simulation time 31176402760 ps
CPU time 22.86 seconds
Started Jun 27 05:59:48 PM PDT 24
Finished Jun 27 06:00:16 PM PDT 24
Peak memory 183104 kb
Host smart-faa1182b-f1cd-478a-a6d1-f8a6fec7b75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839814606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.839814606
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2819998570
Short name T359
Test name
Test status
Simulation time 661138728850 ps
CPU time 237.91 seconds
Started Jun 27 05:59:46 PM PDT 24
Finished Jun 27 06:03:50 PM PDT 24
Peak memory 183120 kb
Host smart-ea76ed33-2a7d-438c-bcd8-2fc6f12c5d15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819998570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2819998570
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1462784795
Short name T43
Test name
Test status
Simulation time 2427627277077 ps
CPU time 1413.98 seconds
Started Jun 27 05:59:48 PM PDT 24
Finished Jun 27 06:23:28 PM PDT 24
Peak memory 183104 kb
Host smart-da4da2e9-2d32-417b-a191-6627c21bbcf9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462784795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1462784795
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.213014870
Short name T419
Test name
Test status
Simulation time 275990737498 ps
CPU time 44.21 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:00:35 PM PDT 24
Peak memory 183136 kb
Host smart-ff2e5955-5e20-4f68-986c-8442ec397e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213014870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.213014870
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.230419038
Short name T240
Test name
Test status
Simulation time 154352666775 ps
CPU time 487.51 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:07:56 PM PDT 24
Peak memory 191320 kb
Host smart-b83b46f5-e5d8-44d9-aa18-22da75039e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230419038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.230419038
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.642350096
Short name T351
Test name
Test status
Simulation time 760189743 ps
CPU time 1.64 seconds
Started Jun 27 05:59:46 PM PDT 24
Finished Jun 27 05:59:53 PM PDT 24
Peak memory 193528 kb
Host smart-4563eec2-c125-4c30-8f8a-17634049e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642350096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.642350096
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.4177214494
Short name T400
Test name
Test status
Simulation time 146457794420 ps
CPU time 216.22 seconds
Started Jun 27 05:59:46 PM PDT 24
Finished Jun 27 06:03:28 PM PDT 24
Peak memory 191316 kb
Host smart-59cb8448-13e3-4e5f-9ee7-75e4337d3086
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177214494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.4177214494
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.629370961
Short name T30
Test name
Test status
Simulation time 11894805616 ps
CPU time 87.69 seconds
Started Jun 27 05:59:48 PM PDT 24
Finished Jun 27 06:01:21 PM PDT 24
Peak memory 197824 kb
Host smart-71f70ba3-feea-4444-938b-079bb0ce6610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629370961 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.629370961
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.959353696
Short name T102
Test name
Test status
Simulation time 318580885332 ps
CPU time 306.39 seconds
Started Jun 27 05:59:46 PM PDT 24
Finished Jun 27 06:04:57 PM PDT 24
Peak memory 183152 kb
Host smart-6e6abab0-f2c7-461d-a4e0-bdadc1c411a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959353696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.959353696
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2141399098
Short name T417
Test name
Test status
Simulation time 36274374114 ps
CPU time 19.29 seconds
Started Jun 27 05:59:48 PM PDT 24
Finished Jun 27 06:00:12 PM PDT 24
Peak memory 183132 kb
Host smart-b6d33477-4cd3-43bb-beb6-ad14e377ef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141399098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2141399098
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3215080339
Short name T310
Test name
Test status
Simulation time 219692201037 ps
CPU time 1494.86 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:24:45 PM PDT 24
Peak memory 191324 kb
Host smart-b31c4576-fcc9-4fa1-9e7b-9f82428642cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215080339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3215080339
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.456097992
Short name T346
Test name
Test status
Simulation time 56866492 ps
CPU time 0.62 seconds
Started Jun 27 05:59:46 PM PDT 24
Finished Jun 27 05:59:51 PM PDT 24
Peak memory 183016 kb
Host smart-35629a41-f085-475e-be99-388d45ad028f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456097992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.456097992
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1471127037
Short name T275
Test name
Test status
Simulation time 50582841788 ps
CPU time 29.62 seconds
Started Jun 27 05:59:42 PM PDT 24
Finished Jun 27 06:00:13 PM PDT 24
Peak memory 183024 kb
Host smart-a7f53828-c34b-49b2-bcdd-35c14422ac1f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471127037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1471127037
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.4141529706
Short name T396
Test name
Test status
Simulation time 173004962459 ps
CPU time 242.54 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:03:57 PM PDT 24
Peak memory 183132 kb
Host smart-9c1af6f9-b011-4148-a43c-f00394f2bb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141529706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4141529706
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2993519972
Short name T416
Test name
Test status
Simulation time 23105782573 ps
CPU time 743.62 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:12:18 PM PDT 24
Peak memory 183120 kb
Host smart-05d24bc3-1d49-4332-9369-c22c24a0c670
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993519972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2993519972
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1475935734
Short name T408
Test name
Test status
Simulation time 65851916442 ps
CPU time 51.06 seconds
Started Jun 27 05:59:42 PM PDT 24
Finished Jun 27 06:00:35 PM PDT 24
Peak memory 183060 kb
Host smart-1b34784f-85ad-41a8-b598-390519190c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475935734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1475935734
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2044565576
Short name T284
Test name
Test status
Simulation time 33704076516 ps
CPU time 57.18 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:00:46 PM PDT 24
Peak memory 194728 kb
Host smart-cf8edd40-037c-4d15-8822-92d19087effc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044565576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2044565576
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2299669492
Short name T135
Test name
Test status
Simulation time 36810509610 ps
CPU time 65.25 seconds
Started Jun 27 05:59:41 PM PDT 24
Finished Jun 27 06:00:48 PM PDT 24
Peak memory 183024 kb
Host smart-addbf105-ca58-417e-9386-32c9383d3041
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299669492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2299669492
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2104290225
Short name T406
Test name
Test status
Simulation time 63302406026 ps
CPU time 79.04 seconds
Started Jun 27 05:59:38 PM PDT 24
Finished Jun 27 06:01:01 PM PDT 24
Peak memory 183112 kb
Host smart-619f9891-5a0c-490e-b7aa-4f664fb44035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104290225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2104290225
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.4190111929
Short name T422
Test name
Test status
Simulation time 221864302861 ps
CPU time 656.5 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:10:45 PM PDT 24
Peak memory 191352 kb
Host smart-3673c6ef-2c1b-4c5c-aee3-0dd56e8b0c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190111929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4190111929
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1741368999
Short name T410
Test name
Test status
Simulation time 26233900350 ps
CPU time 146.61 seconds
Started Jun 27 05:59:43 PM PDT 24
Finished Jun 27 06:02:12 PM PDT 24
Peak memory 191260 kb
Host smart-80c8a601-1195-4fba-b1f3-76ba407fa5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741368999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1741368999
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3512554436
Short name T263
Test name
Test status
Simulation time 200145449286 ps
CPU time 575.62 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:09:24 PM PDT 24
Peak memory 195972 kb
Host smart-43eff68a-9c93-46f6-9e3a-7145a9e77440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512554436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3512554436
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3591522524
Short name T324
Test name
Test status
Simulation time 342293710094 ps
CPU time 149.01 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:02:23 PM PDT 24
Peak memory 183152 kb
Host smart-50c942ef-2bee-4931-89ca-b8899ebd4c51
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591522524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3591522524
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1879336681
Short name T363
Test name
Test status
Simulation time 25579511327 ps
CPU time 13.23 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:00:08 PM PDT 24
Peak memory 183128 kb
Host smart-6a1bc36b-7068-447e-b12d-0fc427dec657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879336681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1879336681
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2976179487
Short name T190
Test name
Test status
Simulation time 123716419817 ps
CPU time 1347.51 seconds
Started Jun 27 05:59:45 PM PDT 24
Finished Jun 27 06:22:18 PM PDT 24
Peak memory 191352 kb
Host smart-31f309c2-bc85-4249-940f-dfbb6f1c163c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976179487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2976179487
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1137609871
Short name T344
Test name
Test status
Simulation time 59469534093 ps
CPU time 88.1 seconds
Started Jun 27 05:59:50 PM PDT 24
Finished Jun 27 06:01:23 PM PDT 24
Peak memory 191384 kb
Host smart-a0d06cc4-b8ad-444e-bb68-25a2ddddbe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137609871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1137609871
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3626078189
Short name T144
Test name
Test status
Simulation time 1817261444276 ps
CPU time 908.62 seconds
Started Jun 27 05:59:50 PM PDT 24
Finished Jun 27 06:15:03 PM PDT 24
Peak memory 191520 kb
Host smart-50a09e1d-8b34-42ee-a225-3c227a4eb7fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626078189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3626078189
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1481342533
Short name T254
Test name
Test status
Simulation time 507263624693 ps
CPU time 454.93 seconds
Started Jun 27 05:59:50 PM PDT 24
Finished Jun 27 06:07:30 PM PDT 24
Peak memory 183164 kb
Host smart-de5b9f55-b910-4f31-8cb9-1f29e9b7542f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481342533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1481342533
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.859027696
Short name T373
Test name
Test status
Simulation time 786085439681 ps
CPU time 121.67 seconds
Started Jun 27 05:59:50 PM PDT 24
Finished Jun 27 06:01:57 PM PDT 24
Peak memory 183116 kb
Host smart-df0b6d68-618a-4bcd-9b26-c365c07b0301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859027696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.859027696
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2637720033
Short name T156
Test name
Test status
Simulation time 447596119896 ps
CPU time 491.22 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 06:08:06 PM PDT 24
Peak memory 191356 kb
Host smart-bfc1fd47-e742-4070-bf07-34293b1abd0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637720033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2637720033
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1022228345
Short name T383
Test name
Test status
Simulation time 282981601 ps
CPU time 0.97 seconds
Started Jun 27 05:59:49 PM PDT 24
Finished Jun 27 05:59:55 PM PDT 24
Peak memory 183024 kb
Host smart-283beb6e-a7ce-492b-9a1e-7055ace22ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022228345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1022228345
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.44937059
Short name T270
Test name
Test status
Simulation time 618371821453 ps
CPU time 249.27 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:04:21 PM PDT 24
Peak memory 195276 kb
Host smart-4380126f-638e-4407-9390-a9b2f2aa997d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44937059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.44937059
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2255937923
Short name T3
Test name
Test status
Simulation time 90490157607 ps
CPU time 208.49 seconds
Started Jun 27 05:59:50 PM PDT 24
Finished Jun 27 06:03:23 PM PDT 24
Peak memory 206072 kb
Host smart-66ebc684-1e28-4599-a44b-fbaf246961c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255937923 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2255937923
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2235035298
Short name T210
Test name
Test status
Simulation time 321962533442 ps
CPU time 532.49 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:08:20 PM PDT 24
Peak memory 183100 kb
Host smart-59f7d8ef-5bcc-47c6-9591-34953bcd0570
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235035298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2235035298
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.4121202357
Short name T354
Test name
Test status
Simulation time 203795137865 ps
CPU time 152.85 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:02:00 PM PDT 24
Peak memory 183108 kb
Host smart-193b0c64-0c86-48d4-a729-6e5cd8d7c08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121202357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.4121202357
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1319583063
Short name T197
Test name
Test status
Simulation time 74119621185 ps
CPU time 292.87 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:04:19 PM PDT 24
Peak memory 183156 kb
Host smart-6628dfe7-0bc8-477e-8749-b66c66a7ea8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319583063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1319583063
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3133669304
Short name T273
Test name
Test status
Simulation time 66550598936 ps
CPU time 318.05 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 06:04:41 PM PDT 24
Peak memory 191364 kb
Host smart-db8f9cb9-8390-407b-8918-03da4341a31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133669304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3133669304
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2713163465
Short name T168
Test name
Test status
Simulation time 431656081967 ps
CPU time 791.75 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:12:48 PM PDT 24
Peak memory 191084 kb
Host smart-4f0be054-f227-42cf-9616-4f5f1cb38f76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713163465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2713163465
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.1900371585
Short name T183
Test name
Test status
Simulation time 312184283514 ps
CPU time 309.52 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:05:18 PM PDT 24
Peak memory 191324 kb
Host smart-e83d9dfb-8394-48ec-b7b1-6227e05e7df6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900371585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1900371585
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.506477349
Short name T189
Test name
Test status
Simulation time 184904691064 ps
CPU time 478.58 seconds
Started Jun 27 06:00:10 PM PDT 24
Finished Jun 27 06:08:11 PM PDT 24
Peak memory 191328 kb
Host smart-acf43fba-ede2-405e-9e41-e9be383f1c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506477349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.506477349
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3468506594
Short name T245
Test name
Test status
Simulation time 188241686694 ps
CPU time 480.29 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:08:08 PM PDT 24
Peak memory 191304 kb
Host smart-2f245311-e638-45c8-9a0e-d64603d75c8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468506594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3468506594
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.252976869
Short name T341
Test name
Test status
Simulation time 89989607905 ps
CPU time 170.82 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:03:02 PM PDT 24
Peak memory 191324 kb
Host smart-c3e7252b-4a7f-4036-b7e8-a5c368b99848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252976869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.252976869
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.4278543892
Short name T326
Test name
Test status
Simulation time 108038108178 ps
CPU time 158.7 seconds
Started Jun 27 06:00:11 PM PDT 24
Finished Jun 27 06:02:52 PM PDT 24
Peak memory 191280 kb
Host smart-b9ddeb5e-0e52-4877-b6b0-5cdc2fabba38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278543892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.4278543892
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.551918576
Short name T214
Test name
Test status
Simulation time 61059855786 ps
CPU time 31.54 seconds
Started Jun 27 06:00:05 PM PDT 24
Finished Jun 27 06:00:38 PM PDT 24
Peak memory 183144 kb
Host smart-02feb4b2-e475-4f5e-b4b9-3c78cf7b1147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551918576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.551918576
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2894615837
Short name T282
Test name
Test status
Simulation time 126901431470 ps
CPU time 40.72 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:00:49 PM PDT 24
Peak memory 191348 kb
Host smart-71f51c84-2a80-4fad-9d39-42802c8857cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894615837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2894615837
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.880331536
Short name T329
Test name
Test status
Simulation time 7427756417 ps
CPU time 4.54 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 05:59:29 PM PDT 24
Peak memory 183140 kb
Host smart-cf7c7181-32b0-4d92-bb93-15ee82bb6712
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880331536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.880331536
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.4156543048
Short name T428
Test name
Test status
Simulation time 119201281299 ps
CPU time 39.77 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:00:07 PM PDT 24
Peak memory 183068 kb
Host smart-e27155ff-0119-44bc-bc3b-89fc72eb9ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156543048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.4156543048
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.679538188
Short name T280
Test name
Test status
Simulation time 201302112460 ps
CPU time 310.91 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:04:37 PM PDT 24
Peak memory 183148 kb
Host smart-6c8b4153-7992-450a-a430-c55ad5dbc4fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679538188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.679538188
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2540486215
Short name T54
Test name
Test status
Simulation time 33820971392 ps
CPU time 178.37 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:02:34 PM PDT 24
Peak memory 182684 kb
Host smart-9e0abb7c-97f2-4d3a-a441-9c51815b043a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540486215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2540486215
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.4178616750
Short name T181
Test name
Test status
Simulation time 4923870062720 ps
CPU time 1961.33 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 06:32:06 PM PDT 24
Peak memory 191288 kb
Host smart-318a2dd9-a385-400d-a731-512c92ba986e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178616750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
4178616750
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.911367728
Short name T7
Test name
Test status
Simulation time 45302642528 ps
CPU time 220.7 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:03:49 PM PDT 24
Peak memory 183160 kb
Host smart-226c77df-c6da-4976-9501-0bbfc383b536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911367728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.911367728
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.1487094651
Short name T166
Test name
Test status
Simulation time 217049439938 ps
CPU time 660.12 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:11:11 PM PDT 24
Peak memory 191356 kb
Host smart-450b6f01-c2b2-4f6d-a25b-c0166a26c332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487094651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1487094651
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.297164481
Short name T16
Test name
Test status
Simulation time 39361787567 ps
CPU time 182.74 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:03:10 PM PDT 24
Peak memory 191364 kb
Host smart-e8038c0e-1bad-4678-8405-a22e4be71833
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297164481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.297164481
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.768335430
Short name T180
Test name
Test status
Simulation time 43268154563 ps
CPU time 53.42 seconds
Started Jun 27 06:00:08 PM PDT 24
Finished Jun 27 06:01:04 PM PDT 24
Peak memory 191352 kb
Host smart-1d652f46-9317-4918-8bd5-10ad658286af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768335430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.768335430
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.86444265
Short name T402
Test name
Test status
Simulation time 98943575957 ps
CPU time 62.19 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:01:10 PM PDT 24
Peak memory 183168 kb
Host smart-be6ac4b4-c38d-4368-ad09-51320e79a523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86444265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.86444265
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2391527462
Short name T172
Test name
Test status
Simulation time 464473408439 ps
CPU time 227.95 seconds
Started Jun 27 06:00:07 PM PDT 24
Finished Jun 27 06:03:57 PM PDT 24
Peak memory 191360 kb
Host smart-04245fd3-1d6f-41e4-81ba-3a244153bd30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391527462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2391527462
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3976266938
Short name T206
Test name
Test status
Simulation time 180011343625 ps
CPU time 426.6 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:07:19 PM PDT 24
Peak memory 191328 kb
Host smart-c6455bd5-910f-453b-9f41-f053f8aa4ea5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976266938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3976266938
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2038284248
Short name T106
Test name
Test status
Simulation time 472269251958 ps
CPU time 416.63 seconds
Started Jun 27 06:00:07 PM PDT 24
Finished Jun 27 06:07:05 PM PDT 24
Peak memory 191356 kb
Host smart-6dcb2526-e14b-4d26-b97c-39d47e3d7d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038284248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2038284248
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.4038882089
Short name T107
Test name
Test status
Simulation time 640433223282 ps
CPU time 999.22 seconds
Started Jun 27 05:59:17 PM PDT 24
Finished Jun 27 06:16:07 PM PDT 24
Peak memory 183348 kb
Host smart-b5e658c0-dac3-4457-a526-481c074764de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038882089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.4038882089
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1051653795
Short name T364
Test name
Test status
Simulation time 157880274783 ps
CPU time 206.4 seconds
Started Jun 27 05:59:25 PM PDT 24
Finished Jun 27 06:03:02 PM PDT 24
Peak memory 183144 kb
Host smart-766f49dc-4cd5-4180-9ad6-0cc37db672ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051653795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1051653795
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.1799808580
Short name T193
Test name
Test status
Simulation time 86189054433 ps
CPU time 152.02 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 06:01:56 PM PDT 24
Peak memory 191300 kb
Host smart-88274502-4584-411d-ad2e-edf93c049bed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799808580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.1799808580
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.174711744
Short name T393
Test name
Test status
Simulation time 3832925425 ps
CPU time 31.41 seconds
Started Jun 27 05:59:19 PM PDT 24
Finished Jun 27 06:00:01 PM PDT 24
Peak memory 191548 kb
Host smart-52790e1c-6bf1-4dfe-b325-cb7721e446f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174711744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.174711744
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/72.rv_timer_random.3036364560
Short name T200
Test name
Test status
Simulation time 56721442310 ps
CPU time 105.27 seconds
Started Jun 27 06:00:11 PM PDT 24
Finished Jun 27 06:01:58 PM PDT 24
Peak memory 191332 kb
Host smart-211422c2-eacf-4133-99a2-607ab3138af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036364560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3036364560
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2978624077
Short name T22
Test name
Test status
Simulation time 1032059512678 ps
CPU time 171.36 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:02:59 PM PDT 24
Peak memory 191372 kb
Host smart-714b66d7-601c-4904-a022-fdce3171184f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978624077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2978624077
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.238110350
Short name T312
Test name
Test status
Simulation time 270864095452 ps
CPU time 418.88 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:07:07 PM PDT 24
Peak memory 191344 kb
Host smart-45805b78-0435-46da-bbfd-963b0fa76608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238110350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.238110350
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3609201386
Short name T177
Test name
Test status
Simulation time 572809020433 ps
CPU time 250.3 seconds
Started Jun 27 06:00:10 PM PDT 24
Finished Jun 27 06:04:23 PM PDT 24
Peak memory 193608 kb
Host smart-20e45476-1db2-4c61-bfe1-e26557563b9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609201386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3609201386
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3628967613
Short name T134
Test name
Test status
Simulation time 113258306545 ps
CPU time 173.62 seconds
Started Jun 27 06:00:05 PM PDT 24
Finished Jun 27 06:03:00 PM PDT 24
Peak memory 191332 kb
Host smart-a6f949cf-d8dd-4c11-9385-3aa40b145fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628967613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3628967613
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2425166805
Short name T137
Test name
Test status
Simulation time 5041259251916 ps
CPU time 1796.26 seconds
Started Jun 27 05:59:18 PM PDT 24
Finished Jun 27 06:29:26 PM PDT 24
Peak memory 183344 kb
Host smart-ca1986fe-7817-4509-8ac2-cf4519a03614
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425166805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2425166805
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2464989031
Short name T380
Test name
Test status
Simulation time 63697680597 ps
CPU time 97.77 seconds
Started Jun 27 05:59:18 PM PDT 24
Finished Jun 27 06:01:07 PM PDT 24
Peak memory 183344 kb
Host smart-a708a29e-e4ca-45fb-a798-ca7b9f54ee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464989031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2464989031
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2397217769
Short name T437
Test name
Test status
Simulation time 101982459 ps
CPU time 0.67 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 05:59:24 PM PDT 24
Peak memory 182744 kb
Host smart-f9c02809-5e49-47ff-8718-8e2a8602857e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397217769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2397217769
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3500021584
Short name T98
Test name
Test status
Simulation time 292388838931 ps
CPU time 460.23 seconds
Started Jun 27 05:59:14 PM PDT 24
Finished Jun 27 06:07:03 PM PDT 24
Peak memory 191360 kb
Host smart-1b85175d-e80a-4d40-9d6c-c5160eed732a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500021584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3500021584
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.2948988317
Short name T283
Test name
Test status
Simulation time 17199300342 ps
CPU time 31.1 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:00:42 PM PDT 24
Peak memory 183148 kb
Host smart-f7719449-ac3a-4056-924f-e9bdb84422d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948988317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2948988317
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2457816246
Short name T345
Test name
Test status
Simulation time 432803519593 ps
CPU time 476.34 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:08:08 PM PDT 24
Peak memory 194968 kb
Host smart-f53ec0ef-5a8a-4116-a67d-48846d0325bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457816246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2457816246
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3933865336
Short name T53
Test name
Test status
Simulation time 435168179823 ps
CPU time 377.48 seconds
Started Jun 27 06:00:10 PM PDT 24
Finished Jun 27 06:06:30 PM PDT 24
Peak memory 191352 kb
Host smart-bcb255dc-8c86-442b-af7d-2a18e9c1e32c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933865336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3933865336
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2987159814
Short name T109
Test name
Test status
Simulation time 24322173924 ps
CPU time 36.87 seconds
Started Jun 27 06:00:10 PM PDT 24
Finished Jun 27 06:00:49 PM PDT 24
Peak memory 182728 kb
Host smart-4fee07e1-9882-459c-9d82-01feb34159e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987159814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2987159814
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3012661787
Short name T153
Test name
Test status
Simulation time 655781805420 ps
CPU time 728.33 seconds
Started Jun 27 06:00:07 PM PDT 24
Finished Jun 27 06:12:17 PM PDT 24
Peak memory 191344 kb
Host smart-9ae08ef6-51ca-4837-a4cf-a425e007cc12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012661787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3012661787
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3982575168
Short name T271
Test name
Test status
Simulation time 733168837907 ps
CPU time 850.1 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:14:22 PM PDT 24
Peak memory 191312 kb
Host smart-78d9c615-f079-45c7-9b35-01eb0bbbbb66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982575168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3982575168
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2555125170
Short name T321
Test name
Test status
Simulation time 11865920599 ps
CPU time 22.03 seconds
Started Jun 27 06:00:05 PM PDT 24
Finished Jun 27 06:00:29 PM PDT 24
Peak memory 183144 kb
Host smart-248cda81-8888-4079-ad46-678ebc2cd8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555125170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2555125170
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3330717924
Short name T260
Test name
Test status
Simulation time 220705843927 ps
CPU time 88.99 seconds
Started Jun 27 06:00:05 PM PDT 24
Finished Jun 27 06:01:36 PM PDT 24
Peak memory 193496 kb
Host smart-63c4eb2f-a671-4503-b039-79fc23b29990
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330717924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3330717924
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.888200338
Short name T129
Test name
Test status
Simulation time 1072077809430 ps
CPU time 474.53 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 06:07:18 PM PDT 24
Peak memory 182912 kb
Host smart-a7de5950-66fe-4318-a9c7-89b555d40bc4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888200338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.888200338
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1747896865
Short name T352
Test name
Test status
Simulation time 119529242908 ps
CPU time 169.48 seconds
Started Jun 27 05:59:16 PM PDT 24
Finished Jun 27 06:02:14 PM PDT 24
Peak memory 183160 kb
Host smart-c49fb648-da4a-41f5-8643-f146dd87b35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747896865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1747896865
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.885619204
Short name T307
Test name
Test status
Simulation time 158060599989 ps
CPU time 453.78 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 06:06:57 PM PDT 24
Peak memory 191352 kb
Host smart-d7bfc67e-fbaf-4f93-9b36-731871535a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885619204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.885619204
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2121878637
Short name T350
Test name
Test status
Simulation time 80339762 ps
CPU time 0.64 seconds
Started Jun 27 05:59:15 PM PDT 24
Finished Jun 27 05:59:24 PM PDT 24
Peak memory 182992 kb
Host smart-46f875f4-f9aa-4171-a5f6-f6a7acfd55e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121878637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2121878637
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.4080258531
Short name T403
Test name
Test status
Simulation time 488591044402 ps
CPU time 190.37 seconds
Started Jun 27 05:59:14 PM PDT 24
Finished Jun 27 06:02:32 PM PDT 24
Peak memory 191356 kb
Host smart-361fdb6b-5175-40cf-b8ad-558cde47518a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080258531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
4080258531
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.4164937868
Short name T154
Test name
Test status
Simulation time 96874300823 ps
CPU time 1209.88 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:20:21 PM PDT 24
Peak memory 193864 kb
Host smart-698dd21e-690a-48fd-9bd9-5ac66e67991d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164937868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4164937868
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.929912954
Short name T339
Test name
Test status
Simulation time 57173485210 ps
CPU time 55.17 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:01:07 PM PDT 24
Peak memory 183128 kb
Host smart-3d8086b9-4713-49ac-a837-7b4e409fb459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929912954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.929912954
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3294811794
Short name T305
Test name
Test status
Simulation time 12254256468 ps
CPU time 23.99 seconds
Started Jun 27 06:00:10 PM PDT 24
Finished Jun 27 06:00:36 PM PDT 24
Peak memory 182708 kb
Host smart-a200fd58-4b9a-46e9-8c33-557fda240466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294811794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3294811794
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.60489784
Short name T108
Test name
Test status
Simulation time 141221108412 ps
CPU time 287.42 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:04:56 PM PDT 24
Peak memory 191352 kb
Host smart-0db3fdfd-6699-4e01-832b-977759d3b653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60489784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.60489784
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3598116559
Short name T301
Test name
Test status
Simulation time 63076959494 ps
CPU time 1637.29 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:27:25 PM PDT 24
Peak memory 191384 kb
Host smart-03237fd4-08f1-423a-88b6-891e35eb2c13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598116559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3598116559
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1333663442
Short name T220
Test name
Test status
Simulation time 217208205335 ps
CPU time 437.79 seconds
Started Jun 27 06:00:09 PM PDT 24
Finished Jun 27 06:07:29 PM PDT 24
Peak memory 191356 kb
Host smart-130fbc1a-8bb4-46b1-86fc-26438295526a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333663442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1333663442
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2241112530
Short name T427
Test name
Test status
Simulation time 283871838216 ps
CPU time 180.73 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:03:09 PM PDT 24
Peak memory 183160 kb
Host smart-95baf366-6eea-48a4-a420-15ac8f58cb91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241112530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2241112530
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1299661367
Short name T160
Test name
Test status
Simulation time 542532684743 ps
CPU time 1422.81 seconds
Started Jun 27 06:00:06 PM PDT 24
Finished Jun 27 06:23:51 PM PDT 24
Peak memory 191348 kb
Host smart-f8978aa1-004d-4267-8fb5-4e04a8d8fd0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299661367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1299661367
Directory /workspace/99.rv_timer_random/latest
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