Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
1275 |
1 |
|
T2 |
14 |
|
T3 |
48 |
|
T5 |
28 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
663 |
1 |
|
T2 |
9 |
|
T3 |
21 |
|
T5 |
15 |
auto[1] |
612 |
1 |
|
T2 |
5 |
|
T3 |
27 |
|
T5 |
13 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
467 |
1 |
|
T2 |
7 |
|
T3 |
31 |
|
T5 |
16 |
auto[1] |
808 |
1 |
|
T2 |
7 |
|
T3 |
17 |
|
T5 |
12 |
Summary for Variable cp_intr_test
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_test
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
728 |
1 |
|
T2 |
7 |
|
T3 |
35 |
|
T5 |
19 |
auto[1] |
547 |
1 |
|
T2 |
7 |
|
T3 |
13 |
|
T5 |
9 |
Summary for Cross intr_test_cg_cc
Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for intr_test_cg_cc
Bins
cp_intr | cp_intr_test | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
auto[0] |
240 |
1 |
|
T2 |
6 |
|
T3 |
14 |
|
T5 |
9 |
all_values[0] |
auto[0] |
auto[0] |
auto[1] |
138 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T40 |
1 |
all_values[0] |
auto[0] |
auto[1] |
auto[0] |
227 |
1 |
|
T2 |
1 |
|
T3 |
17 |
|
T5 |
7 |
all_values[0] |
auto[0] |
auto[1] |
auto[1] |
123 |
1 |
|
T3 |
3 |
|
T5 |
2 |
|
T40 |
3 |
all_values[0] |
auto[1] |
auto[0] |
auto[1] |
285 |
1 |
|
T2 |
3 |
|
T3 |
6 |
|
T5 |
5 |
all_values[0] |
auto[1] |
auto[1] |
auto[1] |
262 |
1 |
|
T2 |
4 |
|
T3 |
7 |
|
T5 |
4 |
User Defined Cross Bins for intr_test_cg_cc
Excluded/Illegal bins
NAME | COUNT | STATUS |
test_1_state_0 |
0 |
Illegal |