Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 579
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T74 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1285453910 Jun 29 04:52:58 PM PDT 24 Jun 29 04:52:59 PM PDT 24 66966671 ps
T506 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3150019553 Jun 29 04:53:07 PM PDT 24 Jun 29 04:53:08 PM PDT 24 15159694 ps
T507 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2781240016 Jun 29 04:53:11 PM PDT 24 Jun 29 04:53:13 PM PDT 24 15009390 ps
T508 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1007830534 Jun 29 04:53:10 PM PDT 24 Jun 29 04:53:12 PM PDT 24 677191425 ps
T509 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1712428258 Jun 29 04:53:28 PM PDT 24 Jun 29 04:53:30 PM PDT 24 16814179 ps
T510 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.734459127 Jun 29 04:53:20 PM PDT 24 Jun 29 04:53:22 PM PDT 24 34035824 ps
T511 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2253892691 Jun 29 04:53:15 PM PDT 24 Jun 29 04:53:17 PM PDT 24 127157754 ps
T512 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2931842336 Jun 29 04:53:21 PM PDT 24 Jun 29 04:53:22 PM PDT 24 16221240 ps
T513 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.981107611 Jun 29 04:53:25 PM PDT 24 Jun 29 04:53:27 PM PDT 24 766881389 ps
T75 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2603381311 Jun 29 04:53:11 PM PDT 24 Jun 29 04:53:12 PM PDT 24 106729171 ps
T514 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2394956696 Jun 29 04:53:14 PM PDT 24 Jun 29 04:53:15 PM PDT 24 24433282 ps
T515 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.921769948 Jun 29 04:53:03 PM PDT 24 Jun 29 04:53:05 PM PDT 24 18930966 ps
T516 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2722029035 Jun 29 04:53:15 PM PDT 24 Jun 29 04:53:16 PM PDT 24 466789480 ps
T517 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1752420882 Jun 29 04:53:04 PM PDT 24 Jun 29 04:53:06 PM PDT 24 29235478 ps
T518 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1782015614 Jun 29 04:53:15 PM PDT 24 Jun 29 04:53:16 PM PDT 24 28249505 ps
T519 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1541401057 Jun 29 04:52:55 PM PDT 24 Jun 29 04:52:57 PM PDT 24 379499077 ps
T520 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2493251163 Jun 29 04:53:23 PM PDT 24 Jun 29 04:53:25 PM PDT 24 82127696 ps
T521 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1368574994 Jun 29 04:53:28 PM PDT 24 Jun 29 04:53:30 PM PDT 24 51033073 ps
T522 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3930065899 Jun 29 04:53:13 PM PDT 24 Jun 29 04:53:14 PM PDT 24 163373615 ps
T523 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3271522097 Jun 29 04:53:04 PM PDT 24 Jun 29 04:53:06 PM PDT 24 236760347 ps
T524 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1439833434 Jun 29 04:53:10 PM PDT 24 Jun 29 04:53:11 PM PDT 24 92494949 ps
T525 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2643039964 Jun 29 04:53:17 PM PDT 24 Jun 29 04:53:18 PM PDT 24 29951345 ps
T526 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4177255403 Jun 29 04:53:20 PM PDT 24 Jun 29 04:53:21 PM PDT 24 43642593 ps
T527 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.883426235 Jun 29 04:53:25 PM PDT 24 Jun 29 04:53:26 PM PDT 24 63188612 ps
T528 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.544891405 Jun 29 04:53:22 PM PDT 24 Jun 29 04:53:24 PM PDT 24 37278139 ps
T529 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2644821281 Jun 29 04:53:18 PM PDT 24 Jun 29 04:53:19 PM PDT 24 19593534 ps
T530 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2938704519 Jun 29 04:53:23 PM PDT 24 Jun 29 04:53:25 PM PDT 24 14538304 ps
T531 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2878559648 Jun 29 04:52:55 PM PDT 24 Jun 29 04:52:56 PM PDT 24 14710504 ps
T532 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.388928950 Jun 29 04:53:06 PM PDT 24 Jun 29 04:53:07 PM PDT 24 53400784 ps
T533 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3252176550 Jun 29 04:53:04 PM PDT 24 Jun 29 04:53:07 PM PDT 24 278348803 ps
T534 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1087958657 Jun 29 04:53:12 PM PDT 24 Jun 29 04:53:14 PM PDT 24 12180863 ps
T535 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2677321990 Jun 29 04:53:22 PM PDT 24 Jun 29 04:53:23 PM PDT 24 15666956 ps
T536 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1304597580 Jun 29 04:53:20 PM PDT 24 Jun 29 04:53:21 PM PDT 24 48456676 ps
T537 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3786908778 Jun 29 04:53:20 PM PDT 24 Jun 29 04:53:22 PM PDT 24 19863695 ps
T538 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3485125125 Jun 29 04:53:09 PM PDT 24 Jun 29 04:53:11 PM PDT 24 78611630 ps
T539 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2883581506 Jun 29 04:53:02 PM PDT 24 Jun 29 04:53:02 PM PDT 24 14489805 ps
T540 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4223516940 Jun 29 04:53:03 PM PDT 24 Jun 29 04:53:05 PM PDT 24 570027838 ps
T541 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2944952004 Jun 29 04:53:24 PM PDT 24 Jun 29 04:53:25 PM PDT 24 26089575 ps
T542 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1088649880 Jun 29 04:52:58 PM PDT 24 Jun 29 04:53:00 PM PDT 24 70088527 ps
T543 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2586585203 Jun 29 04:53:12 PM PDT 24 Jun 29 04:53:13 PM PDT 24 22083583 ps
T544 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1872226376 Jun 29 04:53:20 PM PDT 24 Jun 29 04:53:21 PM PDT 24 49569543 ps
T545 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.457672780 Jun 29 04:53:05 PM PDT 24 Jun 29 04:53:07 PM PDT 24 110130710 ps
T546 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2833689751 Jun 29 04:53:14 PM PDT 24 Jun 29 04:53:16 PM PDT 24 79967265 ps
T547 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3065015838 Jun 29 04:53:24 PM PDT 24 Jun 29 04:53:25 PM PDT 24 27683052 ps
T548 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1165619757 Jun 29 04:53:04 PM PDT 24 Jun 29 04:53:06 PM PDT 24 104549329 ps
T549 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2863598977 Jun 29 04:53:21 PM PDT 24 Jun 29 04:53:23 PM PDT 24 280994290 ps
T78 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1548207132 Jun 29 04:53:02 PM PDT 24 Jun 29 04:53:06 PM PDT 24 2401981636 ps
T550 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4121014373 Jun 29 04:53:11 PM PDT 24 Jun 29 04:53:12 PM PDT 24 13992638 ps
T551 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.142096952 Jun 29 04:53:09 PM PDT 24 Jun 29 04:53:11 PM PDT 24 125017672 ps
T552 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1429086413 Jun 29 04:53:19 PM PDT 24 Jun 29 04:53:20 PM PDT 24 15346272 ps
T553 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.415328053 Jun 29 04:53:05 PM PDT 24 Jun 29 04:53:07 PM PDT 24 127122600 ps
T554 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4183998785 Jun 29 04:53:02 PM PDT 24 Jun 29 04:53:03 PM PDT 24 75626602 ps
T555 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1575670867 Jun 29 04:53:21 PM PDT 24 Jun 29 04:53:23 PM PDT 24 55570737 ps
T556 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.45344688 Jun 29 04:52:56 PM PDT 24 Jun 29 04:52:57 PM PDT 24 22123360 ps
T557 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3145283494 Jun 29 04:53:20 PM PDT 24 Jun 29 04:53:21 PM PDT 24 20217822 ps
T558 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.525371242 Jun 29 04:53:28 PM PDT 24 Jun 29 04:53:30 PM PDT 24 10898533 ps
T559 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2419100373 Jun 29 04:53:04 PM PDT 24 Jun 29 04:53:06 PM PDT 24 217897364 ps
T76 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.230215589 Jun 29 04:52:55 PM PDT 24 Jun 29 04:52:56 PM PDT 24 28316434 ps
T560 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2998117664 Jun 29 04:52:59 PM PDT 24 Jun 29 04:53:01 PM PDT 24 33625457 ps
T561 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2465897824 Jun 29 04:53:02 PM PDT 24 Jun 29 04:53:03 PM PDT 24 159830119 ps
T562 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3576436095 Jun 29 04:52:58 PM PDT 24 Jun 29 04:53:00 PM PDT 24 17438028 ps
T563 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.815926048 Jun 29 04:52:57 PM PDT 24 Jun 29 04:52:59 PM PDT 24 101345664 ps
T564 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.480772852 Jun 29 04:53:19 PM PDT 24 Jun 29 04:53:20 PM PDT 24 84068927 ps
T77 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.85119170 Jun 29 04:52:57 PM PDT 24 Jun 29 04:52:58 PM PDT 24 14530795 ps
T565 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3928400999 Jun 29 04:53:07 PM PDT 24 Jun 29 04:53:08 PM PDT 24 45765642 ps
T566 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2365905974 Jun 29 04:53:10 PM PDT 24 Jun 29 04:53:11 PM PDT 24 50733266 ps
T567 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3565240451 Jun 29 04:53:19 PM PDT 24 Jun 29 04:53:20 PM PDT 24 83490782 ps
T568 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1346695005 Jun 29 04:53:05 PM PDT 24 Jun 29 04:53:08 PM PDT 24 130809767 ps
T569 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3884981830 Jun 29 04:53:20 PM PDT 24 Jun 29 04:53:22 PM PDT 24 61880837 ps
T570 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.516789586 Jun 29 04:53:21 PM PDT 24 Jun 29 04:53:22 PM PDT 24 53136964 ps
T571 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3359669393 Jun 29 04:53:24 PM PDT 24 Jun 29 04:53:26 PM PDT 24 35580978 ps
T572 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1168356901 Jun 29 04:53:04 PM PDT 24 Jun 29 04:53:06 PM PDT 24 20169624 ps
T573 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.934210419 Jun 29 04:53:06 PM PDT 24 Jun 29 04:53:10 PM PDT 24 177547037 ps
T574 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1501447793 Jun 29 04:53:06 PM PDT 24 Jun 29 04:53:08 PM PDT 24 65690187 ps
T575 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3915644597 Jun 29 04:52:56 PM PDT 24 Jun 29 04:52:58 PM PDT 24 1965733316 ps
T576 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2495723939 Jun 29 04:53:19 PM PDT 24 Jun 29 04:53:20 PM PDT 24 158334087 ps
T577 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.591685842 Jun 29 04:53:13 PM PDT 24 Jun 29 04:53:14 PM PDT 24 105443966 ps
T578 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1339061774 Jun 29 04:53:29 PM PDT 24 Jun 29 04:53:31 PM PDT 24 34757765 ps
T579 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3087325711 Jun 29 04:52:57 PM PDT 24 Jun 29 04:52:59 PM PDT 24 83921271 ps

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.897655376
Short name T3
Test name
Test status
Simulation time 160896809962 ps
CPU time 319.42 seconds
Started Jun 29 04:54:03 PM PDT 24
Finished Jun 29 04:59:23 PM PDT 24
Peak memory 205856 kb
Host smart-78729943-3555-42d2-83e8-6bc90911b8ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897655376 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.897655376
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1793416351
Short name T40
Test name
Test status
Simulation time 2666138439296 ps
CPU time 1086.66 seconds
Started Jun 29 04:53:59 PM PDT 24
Finished Jun 29 05:12:06 PM PDT 24
Peak memory 191332 kb
Host smart-a9a3f7be-3511-460e-8247-eb58a6d8bbda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793416351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1793416351
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3152881706
Short name T26
Test name
Test status
Simulation time 97873033 ps
CPU time 1.1 seconds
Started Jun 29 04:53:03 PM PDT 24
Finished Jun 29 04:53:05 PM PDT 24
Peak memory 194644 kb
Host smart-109c293c-6241-490b-976f-78cf9e49fc6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152881706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3152881706
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4025241617
Short name T102
Test name
Test status
Simulation time 1978004655874 ps
CPU time 992.83 seconds
Started Jun 29 04:53:35 PM PDT 24
Finished Jun 29 05:10:09 PM PDT 24
Peak memory 191300 kb
Host smart-4a6768ef-7026-40a7-be1e-1293a694a4ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025241617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4025241617
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2993652002
Short name T164
Test name
Test status
Simulation time 475529863825 ps
CPU time 2458.2 seconds
Started Jun 29 04:54:09 PM PDT 24
Finished Jun 29 05:35:08 PM PDT 24
Peak memory 191336 kb
Host smart-ef1f468b-d9af-45c5-9286-7bfe573c7106
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993652002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2993652002
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.590636241
Short name T101
Test name
Test status
Simulation time 370236423639 ps
CPU time 915.78 seconds
Started Jun 29 04:53:56 PM PDT 24
Finished Jun 29 05:09:13 PM PDT 24
Peak memory 191336 kb
Host smart-eefdaf36-1e5a-48cb-a9f0-d6a0f70a1f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590636241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
590636241
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3616801760
Short name T145
Test name
Test status
Simulation time 8430819513992 ps
CPU time 4117.25 seconds
Started Jun 29 04:53:34 PM PDT 24
Finished Jun 29 06:02:12 PM PDT 24
Peak memory 191328 kb
Host smart-78df7e60-6268-4b47-920c-3286be393df2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616801760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3616801760
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2578214680
Short name T17
Test name
Test status
Simulation time 2855044631352 ps
CPU time 1465.41 seconds
Started Jun 29 04:54:14 PM PDT 24
Finished Jun 29 05:18:40 PM PDT 24
Peak memory 191332 kb
Host smart-84ef782b-33a3-44bf-9189-fd5b355b407d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578214680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2578214680
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.241718867
Short name T90
Test name
Test status
Simulation time 1610270456158 ps
CPU time 1222.3 seconds
Started Jun 29 04:53:42 PM PDT 24
Finished Jun 29 05:14:05 PM PDT 24
Peak memory 191340 kb
Host smart-d77496e2-1d3d-43e6-8168-c045edaa72cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241718867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
241718867
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3502022938
Short name T243
Test name
Test status
Simulation time 867959622187 ps
CPU time 1737.32 seconds
Started Jun 29 04:54:09 PM PDT 24
Finished Jun 29 05:23:06 PM PDT 24
Peak memory 191332 kb
Host smart-c26f85dc-4263-4c24-ac6b-302e71660808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502022938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3502022938
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.262592722
Short name T53
Test name
Test status
Simulation time 626622564066 ps
CPU time 1259.06 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 05:14:36 PM PDT 24
Peak memory 191336 kb
Host smart-a764d675-94a2-4bee-925c-80ef0f92dc59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262592722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
262592722
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1659235673
Short name T69
Test name
Test status
Simulation time 11215091 ps
CPU time 0.55 seconds
Started Jun 29 04:53:12 PM PDT 24
Finished Jun 29 04:53:14 PM PDT 24
Peak memory 182284 kb
Host smart-caf2bc4c-b67b-41d8-9716-1227e7d4a4f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659235673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1659235673
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3674968466
Short name T54
Test name
Test status
Simulation time 1544625791895 ps
CPU time 1592.69 seconds
Started Jun 29 04:54:18 PM PDT 24
Finished Jun 29 05:20:52 PM PDT 24
Peak memory 191332 kb
Host smart-6dd3122c-21a7-43e6-9428-8e6c05fdfb05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674968466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3674968466
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.974209109
Short name T107
Test name
Test status
Simulation time 370961981389 ps
CPU time 873.98 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 05:08:03 PM PDT 24
Peak memory 191336 kb
Host smart-36fa98fe-1ea5-4197-85fb-e506b4675d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974209109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.974209109
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2029197046
Short name T16
Test name
Test status
Simulation time 303938837 ps
CPU time 0.78 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:53:29 PM PDT 24
Peak memory 213284 kb
Host smart-012b78cb-24c6-44d9-a1a7-f37e573ba081
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029197046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2029197046
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3174424994
Short name T224
Test name
Test status
Simulation time 1092938498887 ps
CPU time 1126.83 seconds
Started Jun 29 04:53:30 PM PDT 24
Finished Jun 29 05:12:18 PM PDT 24
Peak memory 191228 kb
Host smart-7be77e55-6c05-4334-aaf7-e34de76f65e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174424994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3174424994
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.4180007159
Short name T299
Test name
Test status
Simulation time 713274499725 ps
CPU time 1439.36 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 05:17:36 PM PDT 24
Peak memory 191236 kb
Host smart-58f1c598-3542-4830-835c-c0f5a48f7f26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180007159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
4180007159
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1427961158
Short name T109
Test name
Test status
Simulation time 743756280878 ps
CPU time 685.84 seconds
Started Jun 29 04:53:55 PM PDT 24
Finished Jun 29 05:05:22 PM PDT 24
Peak memory 191332 kb
Host smart-c4ab2fbf-9f98-41f2-a422-4c46eda56b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427961158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1427961158
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.2982312096
Short name T46
Test name
Test status
Simulation time 26277768824 ps
CPU time 190.04 seconds
Started Jun 29 04:55:31 PM PDT 24
Finished Jun 29 04:58:42 PM PDT 24
Peak memory 191300 kb
Host smart-e2e7ab86-04f8-45f7-b679-f925a9d8b841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982312096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2982312096
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1668076341
Short name T146
Test name
Test status
Simulation time 323533647588 ps
CPU time 590.38 seconds
Started Jun 29 04:53:51 PM PDT 24
Finished Jun 29 05:03:42 PM PDT 24
Peak memory 195704 kb
Host smart-872f5281-6af2-464e-ba55-08cb4e932bc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668076341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1668076341
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3672320020
Short name T308
Test name
Test status
Simulation time 1276903375532 ps
CPU time 965.12 seconds
Started Jun 29 04:53:27 PM PDT 24
Finished Jun 29 05:09:33 PM PDT 24
Peak memory 191228 kb
Host smart-112c93bf-273c-4f15-86f9-47052b1a29c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672320020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3672320020
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/135.rv_timer_random.814504879
Short name T132
Test name
Test status
Simulation time 134755690873 ps
CPU time 224.53 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 04:59:04 PM PDT 24
Peak memory 191332 kb
Host smart-7d42b838-955d-460c-b3fa-a9a732ef1c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814504879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.814504879
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3450294057
Short name T47
Test name
Test status
Simulation time 892239308804 ps
CPU time 399.45 seconds
Started Jun 29 04:53:52 PM PDT 24
Finished Jun 29 05:00:33 PM PDT 24
Peak memory 191332 kb
Host smart-4af5e5c0-e336-4af7-a426-3216cc5182cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450294057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3450294057
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/67.rv_timer_random.3144074364
Short name T167
Test name
Test status
Simulation time 146768201806 ps
CPU time 756.3 seconds
Started Jun 29 04:54:37 PM PDT 24
Finished Jun 29 05:07:14 PM PDT 24
Peak memory 191268 kb
Host smart-e72d700c-85df-4c1c-b92d-935a8e035bdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144074364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3144074364
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.1317697334
Short name T136
Test name
Test status
Simulation time 669587697065 ps
CPU time 1574.57 seconds
Started Jun 29 04:53:27 PM PDT 24
Finished Jun 29 05:19:43 PM PDT 24
Peak memory 191292 kb
Host smart-00644b52-63f3-4b6a-9919-b87b88af758a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317697334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1317697334
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2998075912
Short name T178
Test name
Test status
Simulation time 179042518251 ps
CPU time 387.77 seconds
Started Jun 29 04:54:04 PM PDT 24
Finished Jun 29 05:00:32 PM PDT 24
Peak memory 191332 kb
Host smart-5fb0ae44-c7b5-4a8e-8ed5-e42a577ae57c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998075912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2998075912
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3620620998
Short name T250
Test name
Test status
Simulation time 1268989355191 ps
CPU time 1389.02 seconds
Started Jun 29 04:54:05 PM PDT 24
Finished Jun 29 05:17:14 PM PDT 24
Peak memory 191236 kb
Host smart-d1abaa0b-4275-40f2-9ba3-d7907c030832
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620620998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3620620998
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/105.rv_timer_random.3766449171
Short name T25
Test name
Test status
Simulation time 115207223512 ps
CPU time 1367.19 seconds
Started Jun 29 04:54:58 PM PDT 24
Finished Jun 29 05:17:46 PM PDT 24
Peak memory 191320 kb
Host smart-b8e54102-80d1-4ae5-b42c-839c85522da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766449171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3766449171
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.256051594
Short name T204
Test name
Test status
Simulation time 340500161288 ps
CPU time 155.35 seconds
Started Jun 29 04:55:00 PM PDT 24
Finished Jun 29 04:57:35 PM PDT 24
Peak memory 191336 kb
Host smart-88af60a1-cff4-48c2-96be-149b834a83fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256051594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.256051594
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1935119688
Short name T248
Test name
Test status
Simulation time 564007044114 ps
CPU time 2472 seconds
Started Jun 29 04:53:33 PM PDT 24
Finished Jun 29 05:34:46 PM PDT 24
Peak memory 191236 kb
Host smart-70a55a08-a702-4f51-971d-73420abb82ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935119688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1935119688
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.4217963762
Short name T229
Test name
Test status
Simulation time 457690065175 ps
CPU time 205.88 seconds
Started Jun 29 04:55:00 PM PDT 24
Finished Jun 29 04:58:26 PM PDT 24
Peak memory 191144 kb
Host smart-c2991fbe-8a12-4dbb-82d3-f0e507388eca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217963762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4217963762
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.96779136
Short name T264
Test name
Test status
Simulation time 549682825450 ps
CPU time 540.14 seconds
Started Jun 29 04:54:42 PM PDT 24
Finished Jun 29 05:03:43 PM PDT 24
Peak memory 191332 kb
Host smart-db057ada-bd1f-4980-bf30-27e4a19eca13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96779136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.96779136
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3224351819
Short name T68
Test name
Test status
Simulation time 46951386 ps
CPU time 0.63 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:03 PM PDT 24
Peak memory 182232 kb
Host smart-8d0c13bf-870a-46d4-bd8e-e81d63031ed6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224351819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3224351819
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/155.rv_timer_random.3230340185
Short name T208
Test name
Test status
Simulation time 400704523427 ps
CPU time 304.09 seconds
Started Jun 29 04:55:28 PM PDT 24
Finished Jun 29 05:00:32 PM PDT 24
Peak memory 191336 kb
Host smart-3ab8ff27-681d-46de-aad9-fe1f83236dc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230340185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3230340185
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.131903699
Short name T159
Test name
Test status
Simulation time 165641345276 ps
CPU time 1162.57 seconds
Started Jun 29 04:53:27 PM PDT 24
Finished Jun 29 05:12:51 PM PDT 24
Peak memory 194020 kb
Host smart-ab2171d5-01fa-41ab-ad01-b80130030b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131903699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.131903699
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.1275586531
Short name T223
Test name
Test status
Simulation time 78391152532 ps
CPU time 288.33 seconds
Started Jun 29 04:54:04 PM PDT 24
Finished Jun 29 04:58:53 PM PDT 24
Peak memory 191340 kb
Host smart-ccbf11d3-24f9-42a1-b6c3-75761fdfe612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275586531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1275586531
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/50.rv_timer_random.4084785119
Short name T309
Test name
Test status
Simulation time 505147310224 ps
CPU time 421.46 seconds
Started Jun 29 04:54:18 PM PDT 24
Finished Jun 29 05:01:20 PM PDT 24
Peak memory 191340 kb
Host smart-8e18fd1c-dc1f-470e-962d-763c157bf95e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084785119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.4084785119
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1062398170
Short name T176
Test name
Test status
Simulation time 82460177516 ps
CPU time 537.38 seconds
Started Jun 29 04:54:58 PM PDT 24
Finished Jun 29 05:03:56 PM PDT 24
Peak memory 191336 kb
Host smart-f3be8e73-8e9a-4802-872d-50427b8f5a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062398170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1062398170
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2411244370
Short name T215
Test name
Test status
Simulation time 92171004443 ps
CPU time 159.97 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 04:57:58 PM PDT 24
Peak memory 191328 kb
Host smart-f87a1303-7e92-4247-98fb-5aec550ebdbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411244370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2411244370
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2393379274
Short name T244
Test name
Test status
Simulation time 244933837948 ps
CPU time 1172.86 seconds
Started Jun 29 04:55:37 PM PDT 24
Finished Jun 29 05:15:10 PM PDT 24
Peak memory 183132 kb
Host smart-f19aace0-fdb4-45a8-8607-e7925dde51a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393379274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2393379274
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3492133278
Short name T141
Test name
Test status
Simulation time 168013360407 ps
CPU time 311.62 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 04:58:52 PM PDT 24
Peak memory 191328 kb
Host smart-139619c7-72e9-4656-ab90-8918dfb36586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492133278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3492133278
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/186.rv_timer_random.2905431749
Short name T152
Test name
Test status
Simulation time 482329545982 ps
CPU time 222.54 seconds
Started Jun 29 04:55:54 PM PDT 24
Finished Jun 29 04:59:36 PM PDT 24
Peak memory 193744 kb
Host smart-1fa4a443-5d22-4eb3-9dcb-a6bdb7735f9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905431749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2905431749
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2918131453
Short name T294
Test name
Test status
Simulation time 48304189876 ps
CPU time 43.01 seconds
Started Jun 29 04:53:44 PM PDT 24
Finished Jun 29 04:54:28 PM PDT 24
Peak memory 183100 kb
Host smart-315a1229-b345-4486-b5c4-d6d1eefea89b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918131453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2918131453
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/196.rv_timer_random.1976480585
Short name T261
Test name
Test status
Simulation time 137297444574 ps
CPU time 877.74 seconds
Started Jun 29 04:55:56 PM PDT 24
Finished Jun 29 05:10:35 PM PDT 24
Peak memory 191336 kb
Host smart-4542e14f-9c42-4143-b3b6-16f9456e1b35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976480585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1976480585
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1888904676
Short name T234
Test name
Test status
Simulation time 242603163391 ps
CPU time 425.53 seconds
Started Jun 29 04:53:51 PM PDT 24
Finished Jun 29 05:00:57 PM PDT 24
Peak memory 183024 kb
Host smart-e300df67-b575-42bf-b363-55288cd46888
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888904676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1888904676
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3366953121
Short name T50
Test name
Test status
Simulation time 3015652533773 ps
CPU time 1490.2 seconds
Started Jun 29 04:53:59 PM PDT 24
Finished Jun 29 05:18:50 PM PDT 24
Peak memory 191332 kb
Host smart-7ecd5114-6ef1-41ad-b060-c086c7319285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366953121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3366953121
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_random.2255879748
Short name T314
Test name
Test status
Simulation time 94928786369 ps
CPU time 272.56 seconds
Started Jun 29 04:53:25 PM PDT 24
Finished Jun 29 04:57:58 PM PDT 24
Peak memory 191332 kb
Host smart-f1594811-9201-44be-8532-da194c602262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255879748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2255879748
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3046792003
Short name T251
Test name
Test status
Simulation time 135747736232 ps
CPU time 225.21 seconds
Started Jun 29 04:54:42 PM PDT 24
Finished Jun 29 04:58:27 PM PDT 24
Peak memory 194984 kb
Host smart-8786ace3-6e1d-4b2b-a545-24a4a1d5f256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046792003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3046792003
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1710648092
Short name T88
Test name
Test status
Simulation time 2375419480 ps
CPU time 1.39 seconds
Started Jun 29 04:53:00 PM PDT 24
Finished Jun 29 04:53:02 PM PDT 24
Peak memory 182828 kb
Host smart-b1ad5cda-1c14-4b20-9239-98db5175b416
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710648092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1710648092
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/102.rv_timer_random.1947098577
Short name T200
Test name
Test status
Simulation time 191138115030 ps
CPU time 212.07 seconds
Started Jun 29 04:54:50 PM PDT 24
Finished Jun 29 04:58:23 PM PDT 24
Peak memory 191336 kb
Host smart-830161a9-786e-442d-9d14-839ced85affd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947098577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1947098577
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3543431453
Short name T322
Test name
Test status
Simulation time 362693009909 ps
CPU time 306.35 seconds
Started Jun 29 04:55:29 PM PDT 24
Finished Jun 29 05:00:35 PM PDT 24
Peak memory 191328 kb
Host smart-8ad7ed6d-3908-45e5-be71-37178a42680f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543431453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3543431453
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1206545176
Short name T139
Test name
Test status
Simulation time 104771472682 ps
CPU time 267.02 seconds
Started Jun 29 04:55:55 PM PDT 24
Finished Jun 29 05:00:22 PM PDT 24
Peak memory 191336 kb
Host smart-4281ad39-4e77-4e6c-93b2-3216ab45fade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206545176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1206545176
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4112091761
Short name T227
Test name
Test status
Simulation time 158443314145 ps
CPU time 165.66 seconds
Started Jun 29 04:56:03 PM PDT 24
Finished Jun 29 04:58:49 PM PDT 24
Peak memory 191336 kb
Host smart-d7b1e273-e0f0-486d-a0d9-0e0b6054a122
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112091761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4112091761
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2457738547
Short name T173
Test name
Test status
Simulation time 1444256654677 ps
CPU time 1582.02 seconds
Started Jun 29 04:53:48 PM PDT 24
Finished Jun 29 05:20:10 PM PDT 24
Peak memory 191332 kb
Host smart-5b85781c-c02a-4de2-872d-4e36069d908c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457738547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2457738547
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_random.3492023383
Short name T18
Test name
Test status
Simulation time 308511368249 ps
CPU time 587.81 seconds
Started Jun 29 04:53:58 PM PDT 24
Finished Jun 29 05:03:47 PM PDT 24
Peak memory 191340 kb
Host smart-b57fe812-98f2-4f22-8c5e-9b6d8b5bee98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492023383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3492023383
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3103301459
Short name T332
Test name
Test status
Simulation time 196857435268 ps
CPU time 310.91 seconds
Started Jun 29 04:54:06 PM PDT 24
Finished Jun 29 04:59:17 PM PDT 24
Peak memory 183124 kb
Host smart-a4ab7ad4-09c1-4ff8-8aba-0efcaa8c5d8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103301459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3103301459
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.452223681
Short name T117
Test name
Test status
Simulation time 8359394244533 ps
CPU time 2148.78 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 05:29:18 PM PDT 24
Peak memory 183036 kb
Host smart-3c864f59-2afd-497d-9bca-217732d940fc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452223681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.452223681
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/74.rv_timer_random.3204343691
Short name T177
Test name
Test status
Simulation time 631419184615 ps
CPU time 1003.85 seconds
Started Jun 29 04:54:32 PM PDT 24
Finished Jun 29 05:11:16 PM PDT 24
Peak memory 191340 kb
Host smart-6725dc5b-fcd7-4425-ad04-5c62aeab8bd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204343691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3204343691
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.89918149
Short name T161
Test name
Test status
Simulation time 275669933866 ps
CPU time 201.64 seconds
Started Jun 29 04:54:35 PM PDT 24
Finished Jun 29 04:57:58 PM PDT 24
Peak memory 195096 kb
Host smart-4dbcfe29-ba73-4074-b42c-45a606a1d070
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89918149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.89918149
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3832320271
Short name T105
Test name
Test status
Simulation time 71473576086 ps
CPU time 438.42 seconds
Started Jun 29 04:54:42 PM PDT 24
Finished Jun 29 05:02:01 PM PDT 24
Peak memory 191236 kb
Host smart-a4a30e28-daf7-4747-8bbb-5b401bd0e566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832320271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3832320271
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.3808830060
Short name T256
Test name
Test status
Simulation time 159244946588 ps
CPU time 460.5 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 05:01:17 PM PDT 24
Peak memory 191308 kb
Host smart-3970bdaa-20c6-4118-a74b-fc66794eded5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808830060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3808830060
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2152841653
Short name T218
Test name
Test status
Simulation time 174561026082 ps
CPU time 2220.72 seconds
Started Jun 29 04:54:41 PM PDT 24
Finished Jun 29 05:31:43 PM PDT 24
Peak memory 191332 kb
Host smart-71e90eee-e209-41b2-ab27-c216c953b58b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152841653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2152841653
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.9531132
Short name T120
Test name
Test status
Simulation time 5506393951879 ps
CPU time 2233.27 seconds
Started Jun 29 04:53:29 PM PDT 24
Finished Jun 29 05:30:44 PM PDT 24
Peak memory 191332 kb
Host smart-bb7d565f-cfe5-42b8-a0fa-241d8035ea89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9531132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.9531132
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/109.rv_timer_random.3960758790
Short name T184
Test name
Test status
Simulation time 105709266923 ps
CPU time 251.21 seconds
Started Jun 29 04:54:59 PM PDT 24
Finished Jun 29 04:59:11 PM PDT 24
Peak memory 183128 kb
Host smart-3bcc647b-d7fc-4cbd-8557-c83a1f9eebee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960758790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3960758790
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.549936837
Short name T149
Test name
Test status
Simulation time 235479856318 ps
CPU time 206.22 seconds
Started Jun 29 04:53:32 PM PDT 24
Finished Jun 29 04:56:59 PM PDT 24
Peak memory 191356 kb
Host smart-b96474c9-449c-4d32-bf54-45e7d69a3d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549936837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.549936837
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/139.rv_timer_random.1523778649
Short name T326
Test name
Test status
Simulation time 12670203206 ps
CPU time 14.79 seconds
Started Jun 29 04:55:17 PM PDT 24
Finished Jun 29 04:55:32 PM PDT 24
Peak memory 193636 kb
Host smart-12499190-bba3-413c-952c-fc41ff9cd41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523778649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1523778649
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3616806192
Short name T307
Test name
Test status
Simulation time 222165400281 ps
CPU time 183.61 seconds
Started Jun 29 04:55:20 PM PDT 24
Finished Jun 29 04:58:23 PM PDT 24
Peak memory 191144 kb
Host smart-54f4d30f-2df0-45bc-b3fe-b36caa8f1c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616806192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3616806192
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.2603503655
Short name T148
Test name
Test status
Simulation time 125875633647 ps
CPU time 308.53 seconds
Started Jun 29 04:53:48 PM PDT 24
Finished Jun 29 04:58:57 PM PDT 24
Peak memory 191256 kb
Host smart-04a08fec-36d8-48f6-b38d-7ecbea2dd43d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603503655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2603503655
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2206963205
Short name T213
Test name
Test status
Simulation time 184046727717 ps
CPU time 359.29 seconds
Started Jun 29 04:54:24 PM PDT 24
Finished Jun 29 05:00:24 PM PDT 24
Peak memory 193672 kb
Host smart-656c960e-4351-4120-8a47-64e8ae7fa408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206963205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2206963205
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.259660791
Short name T151
Test name
Test status
Simulation time 74189802044 ps
CPU time 665.95 seconds
Started Jun 29 04:54:34 PM PDT 24
Finished Jun 29 05:05:41 PM PDT 24
Peak memory 191344 kb
Host smart-843a0559-6251-41d2-b60a-bf8eed47ece0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259660791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.259660791
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3503956091
Short name T4
Test name
Test status
Simulation time 162044275172 ps
CPU time 172.29 seconds
Started Jun 29 04:54:42 PM PDT 24
Finished Jun 29 04:57:35 PM PDT 24
Peak memory 191340 kb
Host smart-cc62ac71-5be7-437c-ad33-f74224d92f88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503956091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3503956091
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1809248168
Short name T241
Test name
Test status
Simulation time 859195660164 ps
CPU time 400.19 seconds
Started Jun 29 04:53:29 PM PDT 24
Finished Jun 29 05:00:11 PM PDT 24
Peak memory 183132 kb
Host smart-d2a9fb53-d001-4023-9571-3f9b89cec310
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809248168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1809248168
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.4271200239
Short name T125
Test name
Test status
Simulation time 329512272800 ps
CPU time 924.9 seconds
Started Jun 29 04:54:50 PM PDT 24
Finished Jun 29 05:10:15 PM PDT 24
Peak memory 191324 kb
Host smart-36f654ae-877a-4a9a-9d63-60e297a8879e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271200239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4271200239
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2865851289
Short name T126
Test name
Test status
Simulation time 127044615159 ps
CPU time 58.93 seconds
Started Jun 29 04:54:50 PM PDT 24
Finished Jun 29 04:55:49 PM PDT 24
Peak memory 191336 kb
Host smart-e7be8ea7-aa8a-4e4e-95bc-acd85361109f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865851289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2865851289
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3404083278
Short name T340
Test name
Test status
Simulation time 127386322038 ps
CPU time 52.31 seconds
Started Jun 29 04:53:34 PM PDT 24
Finished Jun 29 04:54:27 PM PDT 24
Peak memory 191352 kb
Host smart-85227235-6b2d-4dbc-8f88-33c4a4dc0917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404083278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3404083278
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/119.rv_timer_random.4171702024
Short name T246
Test name
Test status
Simulation time 47436494081 ps
CPU time 60.48 seconds
Started Jun 29 04:55:09 PM PDT 24
Finished Jun 29 04:56:10 PM PDT 24
Peak memory 194868 kb
Host smart-6ed49561-b2a9-4d5b-ab9c-ba0f89636dd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171702024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4171702024
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.655523887
Short name T153
Test name
Test status
Simulation time 63125631634 ps
CPU time 89.07 seconds
Started Jun 29 04:55:09 PM PDT 24
Finished Jun 29 04:56:38 PM PDT 24
Peak memory 183140 kb
Host smart-2e7942c8-546d-4f3d-90c6-14946254ad15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655523887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.655523887
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1260330900
Short name T133
Test name
Test status
Simulation time 70644395144 ps
CPU time 95.03 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 04:56:54 PM PDT 24
Peak memory 191308 kb
Host smart-0d58a6e3-a284-45c9-99da-8835a68f7325
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260330900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1260330900
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2419401699
Short name T182
Test name
Test status
Simulation time 556705197135 ps
CPU time 234.67 seconds
Started Jun 29 04:55:17 PM PDT 24
Finished Jun 29 04:59:12 PM PDT 24
Peak memory 191332 kb
Host smart-60bcfc6f-4b21-43f0-adc2-935e14ef05ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419401699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2419401699
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2601157064
Short name T324
Test name
Test status
Simulation time 348060220745 ps
CPU time 218.81 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 04:58:58 PM PDT 24
Peak memory 191336 kb
Host smart-af434dc0-9d45-409d-873d-59f61ff685ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601157064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2601157064
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.11206920
Short name T273
Test name
Test status
Simulation time 137269651165 ps
CPU time 227.5 seconds
Started Jun 29 04:53:44 PM PDT 24
Finished Jun 29 04:57:32 PM PDT 24
Peak memory 183136 kb
Host smart-c760d54e-38e5-4242-bf12-56c018a2ca7c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11206920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.rv_timer_cfg_update_on_fly.11206920
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3243849524
Short name T2
Test name
Test status
Simulation time 924747711610 ps
CPU time 919.85 seconds
Started Jun 29 04:53:42 PM PDT 24
Finished Jun 29 05:09:02 PM PDT 24
Peak memory 191336 kb
Host smart-0e929ea7-1e33-4af0-a064-72078c4df05a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243849524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3243849524
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/164.rv_timer_random.573495494
Short name T221
Test name
Test status
Simulation time 288613950951 ps
CPU time 258.64 seconds
Started Jun 29 04:55:31 PM PDT 24
Finished Jun 29 04:59:50 PM PDT 24
Peak memory 193836 kb
Host smart-47f0ca24-53b6-4269-90d0-6fd40b412dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573495494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.573495494
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.794793566
Short name T343
Test name
Test status
Simulation time 125577931796 ps
CPU time 180.71 seconds
Started Jun 29 04:55:37 PM PDT 24
Finished Jun 29 04:58:38 PM PDT 24
Peak memory 191200 kb
Host smart-7947612a-7153-4663-b88f-17f0c34662b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794793566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.794793566
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.87638589
Short name T288
Test name
Test status
Simulation time 471648985362 ps
CPU time 548.71 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 05:02:50 PM PDT 24
Peak memory 191268 kb
Host smart-1ead8e98-63ab-480a-b226-d081edf77729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87638589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.87638589
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.1669065594
Short name T297
Test name
Test status
Simulation time 55151813449 ps
CPU time 39.53 seconds
Started Jun 29 04:55:39 PM PDT 24
Finished Jun 29 04:56:19 PM PDT 24
Peak memory 191340 kb
Host smart-48e189fa-7e47-4407-91e2-af40cb47bf25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669065594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1669065594
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.776921113
Short name T321
Test name
Test status
Simulation time 353771891792 ps
CPU time 247.91 seconds
Started Jun 29 04:55:45 PM PDT 24
Finished Jun 29 04:59:54 PM PDT 24
Peak memory 191332 kb
Host smart-4bc7de62-0775-4c14-b36b-f6d8d5c45505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776921113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.776921113
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2968474978
Short name T258
Test name
Test status
Simulation time 237725839390 ps
CPU time 159.89 seconds
Started Jun 29 04:55:55 PM PDT 24
Finished Jun 29 04:58:35 PM PDT 24
Peak memory 191328 kb
Host smart-04a33bc0-6830-4484-8b2c-e7443ba6847b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968474978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2968474978
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.101768851
Short name T112
Test name
Test status
Simulation time 638235269388 ps
CPU time 1786.15 seconds
Started Jun 29 04:55:53 PM PDT 24
Finished Jun 29 05:25:40 PM PDT 24
Peak memory 191308 kb
Host smart-5c8ef04d-fe13-4d75-ac1a-399223e0acc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101768851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.101768851
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.708830614
Short name T190
Test name
Test status
Simulation time 384563226244 ps
CPU time 590.08 seconds
Started Jun 29 04:55:54 PM PDT 24
Finished Jun 29 05:05:45 PM PDT 24
Peak memory 191304 kb
Host smart-86758d67-f2d7-4b8b-8dd8-d6ad5f3ae4ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708830614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.708830614
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.535392890
Short name T180
Test name
Test status
Simulation time 652778237528 ps
CPU time 438.34 seconds
Started Jun 29 04:55:55 PM PDT 24
Finished Jun 29 05:03:14 PM PDT 24
Peak memory 191244 kb
Host smart-582fcfd4-426a-4f5d-ac2f-88aa35e3b5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535392890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.535392890
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.3493321575
Short name T236
Test name
Test status
Simulation time 120896660383 ps
CPU time 743.5 seconds
Started Jun 29 04:53:45 PM PDT 24
Finished Jun 29 05:06:09 PM PDT 24
Peak memory 191340 kb
Host smart-a436ca79-54b0-4c12-ac8d-e91511f63407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493321575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3493321575
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2070660478
Short name T116
Test name
Test status
Simulation time 23543413568 ps
CPU time 10.44 seconds
Started Jun 29 04:53:48 PM PDT 24
Finished Jun 29 04:53:59 PM PDT 24
Peak memory 183128 kb
Host smart-187be778-751d-4fed-b021-72ead0ed25e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070660478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2070660478
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2663560606
Short name T118
Test name
Test status
Simulation time 549720976879 ps
CPU time 276.29 seconds
Started Jun 29 04:53:48 PM PDT 24
Finished Jun 29 04:58:25 PM PDT 24
Peak memory 183120 kb
Host smart-eeba46a1-b5b2-45f3-b711-22a33d23b759
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663560606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2663560606
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.254968598
Short name T242
Test name
Test status
Simulation time 67922301848 ps
CPU time 191.3 seconds
Started Jun 29 04:53:55 PM PDT 24
Finished Jun 29 04:57:07 PM PDT 24
Peak memory 194368 kb
Host smart-d1cf6231-7720-4090-9aed-2fdfae3bb1f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254968598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.254968598
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.146975358
Short name T154
Test name
Test status
Simulation time 3504572404509 ps
CPU time 853.98 seconds
Started Jun 29 04:54:11 PM PDT 24
Finished Jun 29 05:08:25 PM PDT 24
Peak memory 183136 kb
Host smart-93fbe0ff-0b1b-463a-be5b-701e446a7400
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146975358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.146975358
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1155803485
Short name T494
Test name
Test status
Simulation time 49110737 ps
CPU time 0.59 seconds
Started Jun 29 04:52:56 PM PDT 24
Finished Jun 29 04:52:57 PM PDT 24
Peak memory 182292 kb
Host smart-7bf62a4a-7a50-4f89-b642-69d215cea4ad
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155803485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1155803485
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1088649880
Short name T542
Test name
Test status
Simulation time 70088527 ps
CPU time 1.49 seconds
Started Jun 29 04:52:58 PM PDT 24
Finished Jun 29 04:53:00 PM PDT 24
Peak memory 190640 kb
Host smart-b2f5fe2b-ddc2-4143-acad-de8723862a87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088649880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1088649880
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.230215589
Short name T76
Test name
Test status
Simulation time 28316434 ps
CPU time 0.59 seconds
Started Jun 29 04:52:55 PM PDT 24
Finished Jun 29 04:52:56 PM PDT 24
Peak memory 182324 kb
Host smart-266b2cf6-00da-433e-9070-5ce87630ffb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230215589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.230215589
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2998117664
Short name T560
Test name
Test status
Simulation time 33625457 ps
CPU time 0.92 seconds
Started Jun 29 04:52:59 PM PDT 24
Finished Jun 29 04:53:01 PM PDT 24
Peak memory 196504 kb
Host smart-a72cfbd8-09af-49a9-95f7-c10310691f8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998117664 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2998117664
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2694202791
Short name T497
Test name
Test status
Simulation time 48460286 ps
CPU time 0.54 seconds
Started Jun 29 04:53:10 PM PDT 24
Finished Jun 29 04:53:11 PM PDT 24
Peak memory 182116 kb
Host smart-3dd0756f-f88e-4996-9b8a-980ac7fdfbc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694202791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2694202791
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1739842283
Short name T469
Test name
Test status
Simulation time 19652846 ps
CPU time 0.59 seconds
Started Jun 29 04:52:58 PM PDT 24
Finished Jun 29 04:52:59 PM PDT 24
Peak memory 181832 kb
Host smart-124a0e9c-793a-45f0-8d6f-3c372db67993
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739842283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1739842283
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.4175731113
Short name T72
Test name
Test status
Simulation time 28256704 ps
CPU time 0.63 seconds
Started Jun 29 04:52:58 PM PDT 24
Finished Jun 29 04:53:00 PM PDT 24
Peak memory 191712 kb
Host smart-280b2d4a-666b-4dff-8a77-1050b1f47f6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175731113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.4175731113
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2906677171
Short name T463
Test name
Test status
Simulation time 58031857 ps
CPU time 1.29 seconds
Started Jun 29 04:52:58 PM PDT 24
Finished Jun 29 04:53:00 PM PDT 24
Peak memory 197320 kb
Host smart-11b77470-b20c-48b8-83bf-6a2760610834
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906677171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2906677171
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1285453910
Short name T74
Test name
Test status
Simulation time 66966671 ps
CPU time 0.62 seconds
Started Jun 29 04:52:58 PM PDT 24
Finished Jun 29 04:52:59 PM PDT 24
Peak memory 182328 kb
Host smart-6b01878b-1210-4e89-9c5e-308e88432af7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285453910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1285453910
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1541401057
Short name T519
Test name
Test status
Simulation time 379499077 ps
CPU time 1.54 seconds
Started Jun 29 04:52:55 PM PDT 24
Finished Jun 29 04:52:57 PM PDT 24
Peak memory 192172 kb
Host smart-58291b23-6856-4f2b-9853-a0336ff2c410
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541401057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1541401057
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2987367876
Short name T31
Test name
Test status
Simulation time 15893110 ps
CPU time 0.52 seconds
Started Jun 29 04:52:56 PM PDT 24
Finished Jun 29 04:52:58 PM PDT 24
Peak memory 181872 kb
Host smart-e30961e2-fb87-4649-bdd1-2ad75cca50b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987367876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2987367876
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1439833434
Short name T524
Test name
Test status
Simulation time 92494949 ps
CPU time 1.2 seconds
Started Jun 29 04:53:10 PM PDT 24
Finished Jun 29 04:53:11 PM PDT 24
Peak memory 196792 kb
Host smart-0b508fd9-bbe5-4de8-bdb0-a870f63d57f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439833434 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1439833434
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4051629403
Short name T472
Test name
Test status
Simulation time 24057052 ps
CPU time 0.54 seconds
Started Jun 29 04:52:56 PM PDT 24
Finished Jun 29 04:52:58 PM PDT 24
Peak memory 182096 kb
Host smart-2dac1fed-d56e-42e7-8205-24b7511540c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051629403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.4051629403
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.45344688
Short name T556
Test name
Test status
Simulation time 22123360 ps
CPU time 0.53 seconds
Started Jun 29 04:52:56 PM PDT 24
Finished Jun 29 04:52:57 PM PDT 24
Peak memory 182124 kb
Host smart-d4a921f9-c7fe-491d-886c-3fae0b8c3874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45344688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.45344688
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1136342660
Short name T79
Test name
Test status
Simulation time 56240660 ps
CPU time 0.62 seconds
Started Jun 29 04:52:56 PM PDT 24
Finished Jun 29 04:52:57 PM PDT 24
Peak memory 191556 kb
Host smart-9b6dbc62-336c-4943-a3f3-beaad2020660
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136342660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1136342660
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1333069130
Short name T496
Test name
Test status
Simulation time 85594559 ps
CPU time 1.84 seconds
Started Jun 29 04:53:00 PM PDT 24
Finished Jun 29 04:53:02 PM PDT 24
Peak memory 197044 kb
Host smart-5a6fcc05-7f19-4361-8dcc-6f4dd3965b9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333069130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1333069130
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3915644597
Short name T575
Test name
Test status
Simulation time 1965733316 ps
CPU time 1.38 seconds
Started Jun 29 04:52:56 PM PDT 24
Finished Jun 29 04:52:58 PM PDT 24
Peak memory 195012 kb
Host smart-86971457-5b5f-4b76-9d66-dbb68cc18387
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915644597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3915644597
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.698008365
Short name T457
Test name
Test status
Simulation time 22832650 ps
CPU time 0.74 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:05 PM PDT 24
Peak memory 194368 kb
Host smart-6294129e-09f9-461e-b24d-af4dd416831d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698008365 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.698008365
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3928400999
Short name T565
Test name
Test status
Simulation time 45765642 ps
CPU time 0.6 seconds
Started Jun 29 04:53:07 PM PDT 24
Finished Jun 29 04:53:08 PM PDT 24
Peak memory 182320 kb
Host smart-f3b1fed7-65e6-4add-a94f-cec4b25d5158
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928400999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3928400999
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.826932999
Short name T476
Test name
Test status
Simulation time 44675083 ps
CPU time 0.57 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:05 PM PDT 24
Peak memory 182120 kb
Host smart-8eef0cd3-afe1-4b6d-ae7f-fe83e66fa6f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826932999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.826932999
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2627871490
Short name T29
Test name
Test status
Simulation time 20180823 ps
CPU time 0.63 seconds
Started Jun 29 04:53:05 PM PDT 24
Finished Jun 29 04:53:06 PM PDT 24
Peak memory 191192 kb
Host smart-526d06d2-f325-4be6-a3dd-1f8e37b89e34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627871490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2627871490
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1501447793
Short name T574
Test name
Test status
Simulation time 65690187 ps
CPU time 1.45 seconds
Started Jun 29 04:53:06 PM PDT 24
Finished Jun 29 04:53:08 PM PDT 24
Peak memory 196984 kb
Host smart-d1358ac6-300a-4961-93b8-8f8dc8223eec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501447793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1501447793
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2419100373
Short name T559
Test name
Test status
Simulation time 217897364 ps
CPU time 1.39 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:06 PM PDT 24
Peak memory 194544 kb
Host smart-a0bb10d5-c986-4ffa-b5cb-22b325fdbd3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419100373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2419100373
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2722029035
Short name T516
Test name
Test status
Simulation time 466789480 ps
CPU time 1.01 seconds
Started Jun 29 04:53:15 PM PDT 24
Finished Jun 29 04:53:16 PM PDT 24
Peak memory 196972 kb
Host smart-c9ee8909-dbe8-4b3f-9b7c-e08a252f51c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722029035 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2722029035
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2603381311
Short name T75
Test name
Test status
Simulation time 106729171 ps
CPU time 0.55 seconds
Started Jun 29 04:53:11 PM PDT 24
Finished Jun 29 04:53:12 PM PDT 24
Peak memory 182320 kb
Host smart-c018b926-8488-4216-9437-0e398a3d7935
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603381311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2603381311
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.517958280
Short name T462
Test name
Test status
Simulation time 14598731 ps
CPU time 0.56 seconds
Started Jun 29 04:53:17 PM PDT 24
Finished Jun 29 04:53:18 PM PDT 24
Peak memory 182072 kb
Host smart-46eba6df-4002-46b4-91b9-f18262304b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517958280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.517958280
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3208581353
Short name T66
Test name
Test status
Simulation time 46838024 ps
CPU time 0.66 seconds
Started Jun 29 04:53:15 PM PDT 24
Finished Jun 29 04:53:16 PM PDT 24
Peak memory 191256 kb
Host smart-3dc28e9d-36d6-48fb-9e02-561d44d58556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208581353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3208581353
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2603394836
Short name T459
Test name
Test status
Simulation time 125896772 ps
CPU time 2.29 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:07 PM PDT 24
Peak memory 197072 kb
Host smart-23f9785b-8662-4a10-ae50-7fbc26263eac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603394836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2603394836
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3485125125
Short name T538
Test name
Test status
Simulation time 78611630 ps
CPU time 1.16 seconds
Started Jun 29 04:53:09 PM PDT 24
Finished Jun 29 04:53:11 PM PDT 24
Peak memory 183012 kb
Host smart-7e639855-6580-47f4-a28c-8124ee3367a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485125125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3485125125
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3930065899
Short name T522
Test name
Test status
Simulation time 163373615 ps
CPU time 0.74 seconds
Started Jun 29 04:53:13 PM PDT 24
Finished Jun 29 04:53:14 PM PDT 24
Peak memory 194732 kb
Host smart-346a2740-9b26-4c4f-8abe-1a900776086e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930065899 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3930065899
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2643039964
Short name T525
Test name
Test status
Simulation time 29951345 ps
CPU time 0.57 seconds
Started Jun 29 04:53:17 PM PDT 24
Finished Jun 29 04:53:18 PM PDT 24
Peak memory 182184 kb
Host smart-e166198e-9f80-47ee-8120-5804855678ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643039964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2643039964
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2723484246
Short name T458
Test name
Test status
Simulation time 18322737 ps
CPU time 0.54 seconds
Started Jun 29 04:53:11 PM PDT 24
Finished Jun 29 04:53:12 PM PDT 24
Peak memory 181628 kb
Host smart-2b5e57db-8234-4838-8eb8-68800370845c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723484246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2723484246
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3664712486
Short name T67
Test name
Test status
Simulation time 17669707 ps
CPU time 0.62 seconds
Started Jun 29 04:53:12 PM PDT 24
Finished Jun 29 04:53:14 PM PDT 24
Peak memory 191120 kb
Host smart-6ed0d574-3fc9-4f2b-84cf-f79f6f028a37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664712486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3664712486
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2253892691
Short name T511
Test name
Test status
Simulation time 127157754 ps
CPU time 1.49 seconds
Started Jun 29 04:53:15 PM PDT 24
Finished Jun 29 04:53:17 PM PDT 24
Peak memory 197116 kb
Host smart-682aeafb-2fa9-4377-938d-03f56d483f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253892691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2253892691
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3673076514
Short name T85
Test name
Test status
Simulation time 250784013 ps
CPU time 1.1 seconds
Started Jun 29 04:53:15 PM PDT 24
Finished Jun 29 04:53:16 PM PDT 24
Peak memory 194628 kb
Host smart-8a9f97c6-a238-4757-9e9c-c85618d51a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673076514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3673076514
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2207104606
Short name T468
Test name
Test status
Simulation time 109846956 ps
CPU time 1.49 seconds
Started Jun 29 04:53:12 PM PDT 24
Finished Jun 29 04:53:15 PM PDT 24
Peak memory 197116 kb
Host smart-cad09798-7c69-4262-8d63-cf824d0edcf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207104606 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2207104606
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1915667973
Short name T499
Test name
Test status
Simulation time 22842017 ps
CPU time 0.58 seconds
Started Jun 29 04:53:14 PM PDT 24
Finished Jun 29 04:53:15 PM PDT 24
Peak memory 182272 kb
Host smart-bc7635cf-9f5e-4aee-896f-a9afdc50cee2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915667973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1915667973
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1087958657
Short name T534
Test name
Test status
Simulation time 12180863 ps
CPU time 0.55 seconds
Started Jun 29 04:53:12 PM PDT 24
Finished Jun 29 04:53:14 PM PDT 24
Peak memory 181888 kb
Host smart-85a3d2a7-ef48-4574-9f45-da021ff55524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087958657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1087958657
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1782015614
Short name T518
Test name
Test status
Simulation time 28249505 ps
CPU time 0.76 seconds
Started Jun 29 04:53:15 PM PDT 24
Finished Jun 29 04:53:16 PM PDT 24
Peak memory 191264 kb
Host smart-9e623f75-05ad-4c98-adad-d5b346d1781d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782015614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1782015614
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1007830534
Short name T508
Test name
Test status
Simulation time 677191425 ps
CPU time 1.88 seconds
Started Jun 29 04:53:10 PM PDT 24
Finished Jun 29 04:53:12 PM PDT 24
Peak memory 197112 kb
Host smart-9525df4c-ca8d-4165-964b-ef4f612e0326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007830534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1007830534
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2073716854
Short name T87
Test name
Test status
Simulation time 1679398713 ps
CPU time 1.32 seconds
Started Jun 29 04:53:10 PM PDT 24
Finished Jun 29 04:53:12 PM PDT 24
Peak memory 195116 kb
Host smart-21ee90a5-0c5a-4cef-8a2c-80a74681678c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073716854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2073716854
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.591685842
Short name T577
Test name
Test status
Simulation time 105443966 ps
CPU time 0.83 seconds
Started Jun 29 04:53:13 PM PDT 24
Finished Jun 29 04:53:14 PM PDT 24
Peak memory 195176 kb
Host smart-21f4ac61-caa6-4d29-be30-e389ac1dce6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591685842 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.591685842
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2394956696
Short name T514
Test name
Test status
Simulation time 24433282 ps
CPU time 0.54 seconds
Started Jun 29 04:53:14 PM PDT 24
Finished Jun 29 04:53:15 PM PDT 24
Peak memory 181884 kb
Host smart-cff93a03-ef73-417e-8489-3485499187b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394956696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2394956696
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3791368650
Short name T490
Test name
Test status
Simulation time 43037184 ps
CPU time 0.8 seconds
Started Jun 29 04:53:10 PM PDT 24
Finished Jun 29 04:53:11 PM PDT 24
Peak memory 193004 kb
Host smart-bbf375e8-2598-440f-812c-658265ecb672
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791368650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3791368650
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.547430605
Short name T452
Test name
Test status
Simulation time 116568408 ps
CPU time 2.35 seconds
Started Jun 29 04:53:11 PM PDT 24
Finished Jun 29 04:53:14 PM PDT 24
Peak memory 197148 kb
Host smart-f93e5269-ae55-4c40-8b64-2910c5f1e842
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547430605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.547430605
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4132210967
Short name T89
Test name
Test status
Simulation time 83414456 ps
CPU time 1.19 seconds
Started Jun 29 04:53:16 PM PDT 24
Finished Jun 29 04:53:18 PM PDT 24
Peak memory 194820 kb
Host smart-4de1f742-476a-4b8c-9a37-370f87825a03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132210967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4132210967
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2833689751
Short name T546
Test name
Test status
Simulation time 79967265 ps
CPU time 0.76 seconds
Started Jun 29 04:53:14 PM PDT 24
Finished Jun 29 04:53:16 PM PDT 24
Peak memory 194156 kb
Host smart-7db4a80d-198f-4fff-af00-244462aa5037
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833689751 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2833689751
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2781240016
Short name T507
Test name
Test status
Simulation time 15009390 ps
CPU time 0.57 seconds
Started Jun 29 04:53:11 PM PDT 24
Finished Jun 29 04:53:13 PM PDT 24
Peak memory 182284 kb
Host smart-968ef68f-d3a4-4cf6-bc0e-4c9334e93974
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781240016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2781240016
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3164505387
Short name T475
Test name
Test status
Simulation time 46204274 ps
CPU time 0.58 seconds
Started Jun 29 04:53:15 PM PDT 24
Finished Jun 29 04:53:16 PM PDT 24
Peak memory 182208 kb
Host smart-3c5a188e-1178-49dc-b99c-a627bbc06ff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164505387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3164505387
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3549308306
Short name T82
Test name
Test status
Simulation time 23715706 ps
CPU time 0.62 seconds
Started Jun 29 04:53:16 PM PDT 24
Finished Jun 29 04:53:17 PM PDT 24
Peak memory 191560 kb
Host smart-d7e65552-cba7-428a-b345-ae5479e1be9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549308306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3549308306
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2586585203
Short name T543
Test name
Test status
Simulation time 22083583 ps
CPU time 1.06 seconds
Started Jun 29 04:53:12 PM PDT 24
Finished Jun 29 04:53:13 PM PDT 24
Peak memory 196944 kb
Host smart-2b303ea9-57ba-42a8-9e8d-042c9fc63922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586585203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2586585203
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3574498775
Short name T28
Test name
Test status
Simulation time 144152259 ps
CPU time 1.37 seconds
Started Jun 29 04:53:16 PM PDT 24
Finished Jun 29 04:53:18 PM PDT 24
Peak memory 194840 kb
Host smart-930e9b0f-5e84-492f-8e35-a9eebc173512
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574498775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3574498775
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.393316920
Short name T45
Test name
Test status
Simulation time 37350338 ps
CPU time 0.89 seconds
Started Jun 29 04:53:20 PM PDT 24
Finished Jun 29 04:53:22 PM PDT 24
Peak memory 196428 kb
Host smart-b8986001-037d-43af-9010-157e215042d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393316920 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.393316920
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4027055974
Short name T498
Test name
Test status
Simulation time 14240466 ps
CPU time 0.57 seconds
Started Jun 29 04:53:17 PM PDT 24
Finished Jun 29 04:53:18 PM PDT 24
Peak memory 182244 kb
Host smart-3daba3a1-f7a4-4fc4-8757-fe5c759e139f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027055974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4027055974
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2644821281
Short name T529
Test name
Test status
Simulation time 19593534 ps
CPU time 0.55 seconds
Started Jun 29 04:53:18 PM PDT 24
Finished Jun 29 04:53:19 PM PDT 24
Peak memory 181612 kb
Host smart-659d43c6-7082-4b22-a862-44415b40a784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644821281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2644821281
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.20109777
Short name T83
Test name
Test status
Simulation time 14566468 ps
CPU time 0.65 seconds
Started Jun 29 04:53:21 PM PDT 24
Finished Jun 29 04:53:22 PM PDT 24
Peak memory 191548 kb
Host smart-955ed257-ac67-4f9f-be94-41e5c8abe00c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20109777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_tim
er_same_csr_outstanding.20109777
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.142096952
Short name T551
Test name
Test status
Simulation time 125017672 ps
CPU time 1.19 seconds
Started Jun 29 04:53:09 PM PDT 24
Finished Jun 29 04:53:11 PM PDT 24
Peak memory 197092 kb
Host smart-3b2080a5-d701-481b-8539-299509d1413c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142096952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.142096952
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4001532075
Short name T27
Test name
Test status
Simulation time 352747594 ps
CPU time 0.81 seconds
Started Jun 29 04:53:13 PM PDT 24
Finished Jun 29 04:53:14 PM PDT 24
Peak memory 193064 kb
Host smart-9a03adfc-8571-4545-982b-73f07253459a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001532075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.4001532075
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.734459127
Short name T510
Test name
Test status
Simulation time 34035824 ps
CPU time 0.69 seconds
Started Jun 29 04:53:20 PM PDT 24
Finished Jun 29 04:53:22 PM PDT 24
Peak memory 194304 kb
Host smart-6f40bd90-8ffd-41a5-ab67-559120ed8e85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734459127 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.734459127
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2938704519
Short name T530
Test name
Test status
Simulation time 14538304 ps
CPU time 0.58 seconds
Started Jun 29 04:53:23 PM PDT 24
Finished Jun 29 04:53:25 PM PDT 24
Peak memory 182324 kb
Host smart-4bd105b2-f2bc-47ec-975b-3a70e5657b03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938704519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2938704519
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2725680596
Short name T455
Test name
Test status
Simulation time 113947492 ps
CPU time 0.58 seconds
Started Jun 29 04:53:20 PM PDT 24
Finished Jun 29 04:53:22 PM PDT 24
Peak memory 182216 kb
Host smart-78dde2cd-d002-40c6-8506-46b86d192b9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725680596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2725680596
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.544891405
Short name T528
Test name
Test status
Simulation time 37278139 ps
CPU time 0.84 seconds
Started Jun 29 04:53:22 PM PDT 24
Finished Jun 29 04:53:24 PM PDT 24
Peak memory 193164 kb
Host smart-cb744c44-349f-49ff-bcf9-3d8806b48053
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544891405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.544891405
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3565240451
Short name T567
Test name
Test status
Simulation time 83490782 ps
CPU time 1.02 seconds
Started Jun 29 04:53:19 PM PDT 24
Finished Jun 29 04:53:20 PM PDT 24
Peak memory 196860 kb
Host smart-0b05d143-f353-4432-9ae6-35307336ee0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565240451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3565240451
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2863598977
Short name T549
Test name
Test status
Simulation time 280994290 ps
CPU time 1.13 seconds
Started Jun 29 04:53:21 PM PDT 24
Finished Jun 29 04:53:23 PM PDT 24
Peak memory 182708 kb
Host smart-eaf270f9-12a6-44e3-82ad-a9a826886a22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863598977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2863598977
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4045309922
Short name T495
Test name
Test status
Simulation time 34053812 ps
CPU time 0.76 seconds
Started Jun 29 04:53:22 PM PDT 24
Finished Jun 29 04:53:24 PM PDT 24
Peak memory 195264 kb
Host smart-45d71392-3fb5-49d0-8d45-cdd482d91629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045309922 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4045309922
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3617962466
Short name T480
Test name
Test status
Simulation time 48003973 ps
CPU time 0.58 seconds
Started Jun 29 04:53:23 PM PDT 24
Finished Jun 29 04:53:24 PM PDT 24
Peak memory 182316 kb
Host smart-fdb94b12-dd9d-43e9-820a-fd38c06cf670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617962466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3617962466
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2794062722
Short name T453
Test name
Test status
Simulation time 154798842 ps
CPU time 0.56 seconds
Started Jun 29 04:53:19 PM PDT 24
Finished Jun 29 04:53:20 PM PDT 24
Peak memory 182188 kb
Host smart-10d4d6de-3d4c-414c-8645-89bfc150e2d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794062722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2794062722
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2495723939
Short name T576
Test name
Test status
Simulation time 158334087 ps
CPU time 0.85 seconds
Started Jun 29 04:53:19 PM PDT 24
Finished Jun 29 04:53:20 PM PDT 24
Peak memory 192972 kb
Host smart-322d23cf-4f27-4d57-a864-ca15c655ae69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495723939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2495723939
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1671200260
Short name T49
Test name
Test status
Simulation time 106117383 ps
CPU time 1.21 seconds
Started Jun 29 04:53:24 PM PDT 24
Finished Jun 29 04:53:26 PM PDT 24
Peak memory 190760 kb
Host smart-1bc93176-2950-4916-9fd9-a07b96bdd511
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671200260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1671200260
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.981107611
Short name T513
Test name
Test status
Simulation time 766881389 ps
CPU time 1.18 seconds
Started Jun 29 04:53:25 PM PDT 24
Finished Jun 29 04:53:27 PM PDT 24
Peak memory 194828 kb
Host smart-a0873f35-1ff2-4e3a-a807-9cc0bbfbb398
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981107611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.981107611
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2360941800
Short name T500
Test name
Test status
Simulation time 48019486 ps
CPU time 0.77 seconds
Started Jun 29 04:53:25 PM PDT 24
Finished Jun 29 04:53:26 PM PDT 24
Peak memory 194848 kb
Host smart-a3aad978-c226-479d-a46a-0aad8ed1cfc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360941800 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2360941800
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1429086413
Short name T552
Test name
Test status
Simulation time 15346272 ps
CPU time 0.54 seconds
Started Jun 29 04:53:19 PM PDT 24
Finished Jun 29 04:53:20 PM PDT 24
Peak memory 182156 kb
Host smart-cb2cf110-57df-465b-aa7b-d5c6f5a6678b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429086413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1429086413
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1575670867
Short name T555
Test name
Test status
Simulation time 55570737 ps
CPU time 0.62 seconds
Started Jun 29 04:53:21 PM PDT 24
Finished Jun 29 04:53:23 PM PDT 24
Peak memory 182176 kb
Host smart-e168f68b-75d0-4cec-976a-648cf3924b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575670867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1575670867
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3359669393
Short name T571
Test name
Test status
Simulation time 35580978 ps
CPU time 0.8 seconds
Started Jun 29 04:53:24 PM PDT 24
Finished Jun 29 04:53:26 PM PDT 24
Peak memory 192868 kb
Host smart-efec888d-13ff-46ed-b8be-bf1130a3034d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359669393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3359669393
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1284707745
Short name T484
Test name
Test status
Simulation time 308240063 ps
CPU time 2.49 seconds
Started Jun 29 04:53:23 PM PDT 24
Finished Jun 29 04:53:26 PM PDT 24
Peak memory 190736 kb
Host smart-4a033704-bada-463d-a5d6-72298547d46d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284707745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1284707745
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.883426235
Short name T527
Test name
Test status
Simulation time 63188612 ps
CPU time 0.89 seconds
Started Jun 29 04:53:25 PM PDT 24
Finished Jun 29 04:53:26 PM PDT 24
Peak memory 193548 kb
Host smart-7c069188-e8d1-4bc4-ad0f-b85866a1e7fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883426235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.883426235
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3377409182
Short name T84
Test name
Test status
Simulation time 14189176 ps
CPU time 0.6 seconds
Started Jun 29 04:52:59 PM PDT 24
Finished Jun 29 04:53:00 PM PDT 24
Peak memory 182320 kb
Host smart-7a6156bb-c1fd-4daf-a0c9-408c94465e71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377409182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3377409182
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.78022084
Short name T481
Test name
Test status
Simulation time 147063035 ps
CPU time 1.61 seconds
Started Jun 29 04:52:56 PM PDT 24
Finished Jun 29 04:52:58 PM PDT 24
Peak memory 190676 kb
Host smart-736d2b37-d6d0-4da7-8a55-d67b6589b9af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78022084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_ba
sh.78022084
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2546411457
Short name T477
Test name
Test status
Simulation time 50369948 ps
CPU time 0.56 seconds
Started Jun 29 04:52:56 PM PDT 24
Finished Jun 29 04:52:57 PM PDT 24
Peak memory 182328 kb
Host smart-a329b848-e039-47d5-9441-ce59c8b62884
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546411457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2546411457
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2878559648
Short name T531
Test name
Test status
Simulation time 14710504 ps
CPU time 0.65 seconds
Started Jun 29 04:52:55 PM PDT 24
Finished Jun 29 04:52:56 PM PDT 24
Peak memory 193804 kb
Host smart-2d5eeede-3a62-4365-af74-33664747e531
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878559648 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2878559648
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.85119170
Short name T77
Test name
Test status
Simulation time 14530795 ps
CPU time 0.6 seconds
Started Jun 29 04:52:57 PM PDT 24
Finished Jun 29 04:52:58 PM PDT 24
Peak memory 182300 kb
Host smart-b3a7a4af-ec98-4e14-a446-1cea185b9e51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85119170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.85119170
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3576436095
Short name T562
Test name
Test status
Simulation time 17438028 ps
CPU time 0.55 seconds
Started Jun 29 04:52:58 PM PDT 24
Finished Jun 29 04:53:00 PM PDT 24
Peak memory 182168 kb
Host smart-dd408c29-df2f-4d1d-8224-fd998e1e15b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576436095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3576436095
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.473056322
Short name T80
Test name
Test status
Simulation time 18667840 ps
CPU time 0.73 seconds
Started Jun 29 04:52:55 PM PDT 24
Finished Jun 29 04:52:57 PM PDT 24
Peak memory 191228 kb
Host smart-4621e670-3c22-43ca-9e8d-29a7d573e851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473056322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_tim
er_same_csr_outstanding.473056322
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.721851400
Short name T451
Test name
Test status
Simulation time 57186520 ps
CPU time 1.34 seconds
Started Jun 29 04:52:57 PM PDT 24
Finished Jun 29 04:52:59 PM PDT 24
Peak memory 197100 kb
Host smart-18ffc80a-3791-49d3-9507-eb1ff544d65b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721851400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.721851400
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3087325711
Short name T579
Test name
Test status
Simulation time 83921271 ps
CPU time 1.15 seconds
Started Jun 29 04:52:57 PM PDT 24
Finished Jun 29 04:52:59 PM PDT 24
Peak memory 193688 kb
Host smart-ab10757e-dda8-4e02-b89c-1baafc2f4e53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087325711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3087325711
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2931842336
Short name T512
Test name
Test status
Simulation time 16221240 ps
CPU time 0.55 seconds
Started Jun 29 04:53:21 PM PDT 24
Finished Jun 29 04:53:22 PM PDT 24
Peak memory 181688 kb
Host smart-80ca0cfb-79b2-482f-9aab-42d3bfcb2bbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931842336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2931842336
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.480772852
Short name T564
Test name
Test status
Simulation time 84068927 ps
CPU time 0.56 seconds
Started Jun 29 04:53:19 PM PDT 24
Finished Jun 29 04:53:20 PM PDT 24
Peak memory 182244 kb
Host smart-555f5964-3678-4dac-abfb-f67f74907eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480772852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.480772852
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2944952004
Short name T541
Test name
Test status
Simulation time 26089575 ps
CPU time 0.55 seconds
Started Jun 29 04:53:24 PM PDT 24
Finished Jun 29 04:53:25 PM PDT 24
Peak memory 182104 kb
Host smart-47411c81-adab-426a-bd0f-f282806dcc26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944952004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2944952004
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1133741857
Short name T464
Test name
Test status
Simulation time 11630611 ps
CPU time 0.57 seconds
Started Jun 29 04:53:20 PM PDT 24
Finished Jun 29 04:53:21 PM PDT 24
Peak memory 182236 kb
Host smart-bb887ca5-6443-439d-a6ad-603b4fd3b4e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133741857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1133741857
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3145283494
Short name T557
Test name
Test status
Simulation time 20217822 ps
CPU time 0.59 seconds
Started Jun 29 04:53:20 PM PDT 24
Finished Jun 29 04:53:21 PM PDT 24
Peak memory 182180 kb
Host smart-25b73e27-bb7f-4379-8755-c9126722583c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145283494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3145283494
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3884981830
Short name T569
Test name
Test status
Simulation time 61880837 ps
CPU time 0.59 seconds
Started Jun 29 04:53:20 PM PDT 24
Finished Jun 29 04:53:22 PM PDT 24
Peak memory 182192 kb
Host smart-6acd62b3-2304-47ae-b429-e4bda08c9d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884981830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3884981830
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1466227074
Short name T489
Test name
Test status
Simulation time 11999386 ps
CPU time 0.56 seconds
Started Jun 29 04:53:25 PM PDT 24
Finished Jun 29 04:53:26 PM PDT 24
Peak memory 181840 kb
Host smart-f91af168-b28e-43a4-aa98-b25aa60a92b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466227074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1466227074
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1872226376
Short name T544
Test name
Test status
Simulation time 49569543 ps
CPU time 0.57 seconds
Started Jun 29 04:53:20 PM PDT 24
Finished Jun 29 04:53:21 PM PDT 24
Peak memory 182204 kb
Host smart-389f729f-ca27-4de4-9101-b572de718cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872226376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1872226376
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3786908778
Short name T537
Test name
Test status
Simulation time 19863695 ps
CPU time 0.54 seconds
Started Jun 29 04:53:20 PM PDT 24
Finished Jun 29 04:53:22 PM PDT 24
Peak memory 182192 kb
Host smart-abe83b99-d593-47f6-95de-b3181284d20a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786908778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3786908778
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.516789586
Short name T570
Test name
Test status
Simulation time 53136964 ps
CPU time 0.57 seconds
Started Jun 29 04:53:21 PM PDT 24
Finished Jun 29 04:53:22 PM PDT 24
Peak memory 182244 kb
Host smart-e6e230f3-e715-4efa-b69b-ee3689e2b5a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516789586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.516789586
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3271522097
Short name T523
Test name
Test status
Simulation time 236760347 ps
CPU time 0.77 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:06 PM PDT 24
Peak memory 192192 kb
Host smart-5994c3ae-7f01-4791-8191-2de4368797d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271522097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3271522097
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.109135409
Short name T460
Test name
Test status
Simulation time 394494983 ps
CPU time 1.54 seconds
Started Jun 29 04:52:56 PM PDT 24
Finished Jun 29 04:52:58 PM PDT 24
Peak memory 182476 kb
Host smart-f4899e97-81e3-45fe-9583-9899e0d37986
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109135409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.109135409
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1971372129
Short name T48
Test name
Test status
Simulation time 68349312 ps
CPU time 0.54 seconds
Started Jun 29 04:53:10 PM PDT 24
Finished Jun 29 04:53:11 PM PDT 24
Peak memory 182108 kb
Host smart-3f6ca5a7-32c1-4a59-a9a3-b654715af2da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971372129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1971372129
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4183998785
Short name T554
Test name
Test status
Simulation time 75626602 ps
CPU time 1.03 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:03 PM PDT 24
Peak memory 196484 kb
Host smart-081738f5-f747-4416-86cf-262829ba243c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183998785 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.4183998785
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.65887275
Short name T30
Test name
Test status
Simulation time 13713752 ps
CPU time 0.58 seconds
Started Jun 29 04:52:55 PM PDT 24
Finished Jun 29 04:52:56 PM PDT 24
Peak memory 182256 kb
Host smart-1f4525ea-2970-4f29-8284-03c1087d041b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65887275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.65887275
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1916978615
Short name T478
Test name
Test status
Simulation time 79691187 ps
CPU time 0.56 seconds
Started Jun 29 04:53:10 PM PDT 24
Finished Jun 29 04:53:11 PM PDT 24
Peak memory 182032 kb
Host smart-090ed77f-52f6-4e7b-8c79-ac73a8b1bb5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916978615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1916978615
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1458976470
Short name T501
Test name
Test status
Simulation time 31392441 ps
CPU time 0.77 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:05 PM PDT 24
Peak memory 193072 kb
Host smart-9456b752-c321-4d37-9026-31954777f87b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458976470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1458976470
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3321778940
Short name T483
Test name
Test status
Simulation time 74498119 ps
CPU time 1.15 seconds
Started Jun 29 04:52:58 PM PDT 24
Finished Jun 29 04:53:00 PM PDT 24
Peak memory 197100 kb
Host smart-fdec0c10-c745-4f99-a141-dd7ddc267f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321778940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3321778940
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.815926048
Short name T563
Test name
Test status
Simulation time 101345664 ps
CPU time 1.33 seconds
Started Jun 29 04:52:57 PM PDT 24
Finished Jun 29 04:52:59 PM PDT 24
Peak memory 182768 kb
Host smart-9838bc93-6423-4ebb-9783-226e473dd3d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815926048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.815926048
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3065015838
Short name T547
Test name
Test status
Simulation time 27683052 ps
CPU time 0.54 seconds
Started Jun 29 04:53:24 PM PDT 24
Finished Jun 29 04:53:25 PM PDT 24
Peak memory 181624 kb
Host smart-2e301801-f76f-4e39-bb1e-e03198405af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065015838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3065015838
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2677321990
Short name T535
Test name
Test status
Simulation time 15666956 ps
CPU time 0.57 seconds
Started Jun 29 04:53:22 PM PDT 24
Finished Jun 29 04:53:23 PM PDT 24
Peak memory 182104 kb
Host smart-924af731-9865-4f37-83e6-201988a8d66b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677321990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2677321990
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4177255403
Short name T526
Test name
Test status
Simulation time 43642593 ps
CPU time 0.53 seconds
Started Jun 29 04:53:20 PM PDT 24
Finished Jun 29 04:53:21 PM PDT 24
Peak memory 182092 kb
Host smart-4f46eb67-e7f8-42c5-b80d-9743e59d6026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177255403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4177255403
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.553495101
Short name T473
Test name
Test status
Simulation time 40908448 ps
CPU time 0.59 seconds
Started Jun 29 04:53:21 PM PDT 24
Finished Jun 29 04:53:23 PM PDT 24
Peak memory 181884 kb
Host smart-5a052ea7-edb8-4e8e-8df5-c4c60e7892fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553495101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.553495101
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1407749732
Short name T502
Test name
Test status
Simulation time 12158577 ps
CPU time 0.54 seconds
Started Jun 29 04:53:22 PM PDT 24
Finished Jun 29 04:53:23 PM PDT 24
Peak memory 181616 kb
Host smart-b85f28c8-6eb1-4fbf-9e5a-a7ee05dff3a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407749732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1407749732
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1189676831
Short name T493
Test name
Test status
Simulation time 20258368 ps
CPU time 0.56 seconds
Started Jun 29 04:53:25 PM PDT 24
Finished Jun 29 04:53:26 PM PDT 24
Peak memory 181684 kb
Host smart-85580f15-170b-401a-b779-1482f0b057d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189676831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1189676831
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2680889795
Short name T467
Test name
Test status
Simulation time 48767132 ps
CPU time 0.57 seconds
Started Jun 29 04:53:22 PM PDT 24
Finished Jun 29 04:53:23 PM PDT 24
Peak memory 182240 kb
Host smart-6123c5db-1985-4c03-9312-813bb6e47f80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680889795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2680889795
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2493251163
Short name T520
Test name
Test status
Simulation time 82127696 ps
CPU time 0.53 seconds
Started Jun 29 04:53:23 PM PDT 24
Finished Jun 29 04:53:25 PM PDT 24
Peak memory 181676 kb
Host smart-7b655ff2-44be-4364-b064-919a6c2122fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493251163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2493251163
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1304597580
Short name T536
Test name
Test status
Simulation time 48456676 ps
CPU time 0.56 seconds
Started Jun 29 04:53:20 PM PDT 24
Finished Jun 29 04:53:21 PM PDT 24
Peak memory 182188 kb
Host smart-5e11ddff-2011-4b33-9983-9e4247e36541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304597580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1304597580
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2612098615
Short name T479
Test name
Test status
Simulation time 17562959 ps
CPU time 0.57 seconds
Started Jun 29 04:53:19 PM PDT 24
Finished Jun 29 04:53:21 PM PDT 24
Peak memory 182172 kb
Host smart-61bb43ee-f682-4328-85e4-39a7ad9ffebd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612098615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2612098615
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.584158304
Short name T70
Test name
Test status
Simulation time 20775389 ps
CPU time 0.78 seconds
Started Jun 29 04:53:11 PM PDT 24
Finished Jun 29 04:53:12 PM PDT 24
Peak memory 182112 kb
Host smart-72f25b4f-503b-49df-a8cf-8b8f437bddc9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584158304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.584158304
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1548207132
Short name T78
Test name
Test status
Simulation time 2401981636 ps
CPU time 3.7 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:06 PM PDT 24
Peak memory 190736 kb
Host smart-46df89b9-633b-4ac5-8fb8-5c80210ba1c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548207132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1548207132
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2876833648
Short name T44
Test name
Test status
Simulation time 70239480 ps
CPU time 0.76 seconds
Started Jun 29 04:53:10 PM PDT 24
Finished Jun 29 04:53:11 PM PDT 24
Peak memory 194652 kb
Host smart-a025bab8-f7dc-49ac-ae60-2d70cb9a94df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876833648 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2876833648
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2883581506
Short name T539
Test name
Test status
Simulation time 14489805 ps
CPU time 0.61 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:02 PM PDT 24
Peak memory 182324 kb
Host smart-3109ce07-43aa-4d72-b5e5-916242ec4790
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883581506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2883581506
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3234254138
Short name T487
Test name
Test status
Simulation time 13981938 ps
CPU time 0.58 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:03 PM PDT 24
Peak memory 182200 kb
Host smart-ddbdd03d-cbf8-4989-aca2-587f01b40ff7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234254138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3234254138
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.544121026
Short name T81
Test name
Test status
Simulation time 60956006 ps
CPU time 0.71 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:05 PM PDT 24
Peak memory 192900 kb
Host smart-c01314c2-4547-46aa-8414-39a61805314f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544121026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.544121026
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3462109482
Short name T488
Test name
Test status
Simulation time 114643499 ps
CPU time 1.5 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:07 PM PDT 24
Peak memory 197036 kb
Host smart-3cd9a4ff-4b4a-4be5-b2a9-efeeb0b14cad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462109482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3462109482
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1877620267
Short name T486
Test name
Test status
Simulation time 43414156 ps
CPU time 0.86 seconds
Started Jun 29 04:53:05 PM PDT 24
Finished Jun 29 04:53:06 PM PDT 24
Peak memory 193392 kb
Host smart-aec3d28b-92e1-474b-9181-21d808c6d80f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877620267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1877620267
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.220210073
Short name T470
Test name
Test status
Simulation time 40324849 ps
CPU time 0.56 seconds
Started Jun 29 04:53:29 PM PDT 24
Finished Jun 29 04:53:30 PM PDT 24
Peak memory 182176 kb
Host smart-c6d3881b-160a-4b2c-b313-69d43b6ba1ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220210073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.220210073
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1501444571
Short name T466
Test name
Test status
Simulation time 28942626 ps
CPU time 0.57 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:53:30 PM PDT 24
Peak memory 182232 kb
Host smart-889c89d9-f8dd-44ec-a3d2-1de4e3383dde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501444571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1501444571
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1339061774
Short name T578
Test name
Test status
Simulation time 34757765 ps
CPU time 0.54 seconds
Started Jun 29 04:53:29 PM PDT 24
Finished Jun 29 04:53:31 PM PDT 24
Peak memory 182172 kb
Host smart-4339d3cc-a189-442c-8110-47cf4143bb26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339061774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1339061774
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1712428258
Short name T509
Test name
Test status
Simulation time 16814179 ps
CPU time 0.56 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:53:30 PM PDT 24
Peak memory 182212 kb
Host smart-3b0ba1c7-0b45-4619-aa08-b652310d402c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712428258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1712428258
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2307418604
Short name T504
Test name
Test status
Simulation time 16661679 ps
CPU time 0.58 seconds
Started Jun 29 04:53:30 PM PDT 24
Finished Jun 29 04:53:31 PM PDT 24
Peak memory 182160 kb
Host smart-690d0f5c-fa7b-42bd-99a0-1a0d32173769
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307418604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2307418604
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.525371242
Short name T558
Test name
Test status
Simulation time 10898533 ps
CPU time 0.56 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:53:30 PM PDT 24
Peak memory 182168 kb
Host smart-834b91a7-aa30-477d-8d9f-76dd26beb341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525371242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.525371242
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1224588628
Short name T465
Test name
Test status
Simulation time 25751897 ps
CPU time 0.56 seconds
Started Jun 29 04:53:33 PM PDT 24
Finished Jun 29 04:53:34 PM PDT 24
Peak memory 182236 kb
Host smart-a5791de6-38c0-4ce4-b1be-1c031a25dbd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224588628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1224588628
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2407190530
Short name T456
Test name
Test status
Simulation time 11283833 ps
CPU time 0.52 seconds
Started Jun 29 04:53:32 PM PDT 24
Finished Jun 29 04:53:33 PM PDT 24
Peak memory 181676 kb
Host smart-b73d5bde-318f-45c8-9490-f19cb5eea877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407190530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2407190530
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1536507246
Short name T454
Test name
Test status
Simulation time 15595821 ps
CPU time 0.53 seconds
Started Jun 29 04:53:27 PM PDT 24
Finished Jun 29 04:53:28 PM PDT 24
Peak memory 181696 kb
Host smart-c9d1da40-fd19-4a6a-806c-6dc7f60b8493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536507246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1536507246
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1368574994
Short name T521
Test name
Test status
Simulation time 51033073 ps
CPU time 0.54 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:53:30 PM PDT 24
Peak memory 182172 kb
Host smart-e0f82f00-7935-47da-ac7f-1751aff47874
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368574994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1368574994
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.921769948
Short name T515
Test name
Test status
Simulation time 18930966 ps
CPU time 0.81 seconds
Started Jun 29 04:53:03 PM PDT 24
Finished Jun 29 04:53:05 PM PDT 24
Peak memory 195528 kb
Host smart-2ad353a1-0917-4ac1-a69c-b722be03e911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921769948 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.921769948
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3646795821
Short name T491
Test name
Test status
Simulation time 135277987 ps
CPU time 0.55 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:03 PM PDT 24
Peak memory 182008 kb
Host smart-c41bea47-4a70-48da-941a-1e5199ec2ae1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646795821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3646795821
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2365905974
Short name T566
Test name
Test status
Simulation time 50733266 ps
CPU time 0.55 seconds
Started Jun 29 04:53:10 PM PDT 24
Finished Jun 29 04:53:11 PM PDT 24
Peak memory 182028 kb
Host smart-8c1f22d5-f02d-4af5-a22c-3366ea939059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365905974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2365905974
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2614123642
Short name T482
Test name
Test status
Simulation time 14828268 ps
CPU time 0.67 seconds
Started Jun 29 04:53:12 PM PDT 24
Finished Jun 29 04:53:14 PM PDT 24
Peak memory 191192 kb
Host smart-825b361f-8d8f-41d1-a113-aba8f74ecfd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614123642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2614123642
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3252176550
Short name T533
Test name
Test status
Simulation time 278348803 ps
CPU time 2.06 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:07 PM PDT 24
Peak memory 197108 kb
Host smart-83d3b312-a01e-4b48-9028-39f0090e6947
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252176550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3252176550
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1715096877
Short name T86
Test name
Test status
Simulation time 2191490445 ps
CPU time 1.32 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:04 PM PDT 24
Peak memory 182748 kb
Host smart-2facd0c9-e028-4d70-8885-47ccef58d896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715096877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1715096877
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1346695005
Short name T568
Test name
Test status
Simulation time 130809767 ps
CPU time 1.57 seconds
Started Jun 29 04:53:05 PM PDT 24
Finished Jun 29 04:53:08 PM PDT 24
Peak memory 197120 kb
Host smart-5803769b-dac9-45c2-af64-4b2a11298c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346695005 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1346695005
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1234332176
Short name T492
Test name
Test status
Simulation time 14709214 ps
CPU time 0.58 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:03 PM PDT 24
Peak memory 182288 kb
Host smart-76d7a04b-3183-4729-9c83-241cc939ca3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234332176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1234332176
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1957263251
Short name T461
Test name
Test status
Simulation time 30197932 ps
CPU time 0.53 seconds
Started Jun 29 04:53:07 PM PDT 24
Finished Jun 29 04:53:08 PM PDT 24
Peak memory 181876 kb
Host smart-2e6e6056-32f9-4368-a327-a6b0c07b3396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957263251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1957263251
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1168356901
Short name T572
Test name
Test status
Simulation time 20169624 ps
CPU time 0.86 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:06 PM PDT 24
Peak memory 193068 kb
Host smart-f5d83a2b-3cf6-403a-9494-b60053be0cb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168356901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1168356901
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.934210419
Short name T573
Test name
Test status
Simulation time 177547037 ps
CPU time 3.07 seconds
Started Jun 29 04:53:06 PM PDT 24
Finished Jun 29 04:53:10 PM PDT 24
Peak memory 197148 kb
Host smart-b4839f05-d0cb-416b-9499-fcbe79d58f76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934210419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.934210419
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.415328053
Short name T553
Test name
Test status
Simulation time 127122600 ps
CPU time 1.09 seconds
Started Jun 29 04:53:05 PM PDT 24
Finished Jun 29 04:53:07 PM PDT 24
Peak memory 194624 kb
Host smart-08b5b176-7ea6-414c-807f-895acfbfaeac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415328053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.415328053
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.4223516940
Short name T540
Test name
Test status
Simulation time 570027838 ps
CPU time 1.53 seconds
Started Jun 29 04:53:03 PM PDT 24
Finished Jun 29 04:53:05 PM PDT 24
Peak memory 197116 kb
Host smart-3e2261ac-c7b6-4c9c-9c69-f3ebbcb6718a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223516940 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.4223516940
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3669946537
Short name T71
Test name
Test status
Simulation time 14028432 ps
CPU time 0.53 seconds
Started Jun 29 04:53:03 PM PDT 24
Finished Jun 29 04:53:04 PM PDT 24
Peak memory 182024 kb
Host smart-431cdf4e-cc4d-4eb8-8109-a5b9515d4ef2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669946537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3669946537
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.296183583
Short name T471
Test name
Test status
Simulation time 49978439 ps
CPU time 0.53 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:04 PM PDT 24
Peak memory 182240 kb
Host smart-24b6d827-72dc-4cf7-b451-30f860279ac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296183583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.296183583
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1165619757
Short name T548
Test name
Test status
Simulation time 104549329 ps
CPU time 0.74 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:06 PM PDT 24
Peak memory 191248 kb
Host smart-9e2e769d-f414-46dc-b5db-28451ea9c5dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165619757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1165619757
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1752420882
Short name T517
Test name
Test status
Simulation time 29235478 ps
CPU time 1.38 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:06 PM PDT 24
Peak memory 197040 kb
Host smart-630f1370-fa8a-4c6d-8fd8-6bc9298b1c06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752420882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1752420882
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.457672780
Short name T545
Test name
Test status
Simulation time 110130710 ps
CPU time 1.34 seconds
Started Jun 29 04:53:05 PM PDT 24
Finished Jun 29 04:53:07 PM PDT 24
Peak memory 183036 kb
Host smart-62d602f7-b5ed-42db-8582-60b1304f6126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457672780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.457672780
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2465897824
Short name T561
Test name
Test status
Simulation time 159830119 ps
CPU time 0.69 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:03 PM PDT 24
Peak memory 193964 kb
Host smart-87c113c8-8508-4045-a1b8-5fda8bd683f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465897824 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2465897824
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2217375673
Short name T505
Test name
Test status
Simulation time 11286691 ps
CPU time 0.6 seconds
Started Jun 29 04:53:07 PM PDT 24
Finished Jun 29 04:53:08 PM PDT 24
Peak memory 191528 kb
Host smart-3f393861-98e5-44a0-ad9e-d251ed24b9c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217375673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2217375673
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.388928950
Short name T532
Test name
Test status
Simulation time 53400784 ps
CPU time 0.57 seconds
Started Jun 29 04:53:06 PM PDT 24
Finished Jun 29 04:53:07 PM PDT 24
Peak memory 182192 kb
Host smart-c32ff71f-1694-4f8a-882f-8fc906a1e952
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388928950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.388928950
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3150019553
Short name T506
Test name
Test status
Simulation time 15159694 ps
CPU time 0.65 seconds
Started Jun 29 04:53:07 PM PDT 24
Finished Jun 29 04:53:08 PM PDT 24
Peak memory 190872 kb
Host smart-62d786ff-29e7-419a-a427-aa41740ee664
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150019553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3150019553
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1900105062
Short name T474
Test name
Test status
Simulation time 104531115 ps
CPU time 1.28 seconds
Started Jun 29 04:53:04 PM PDT 24
Finished Jun 29 04:53:06 PM PDT 24
Peak memory 196780 kb
Host smart-e86e771c-4376-46cd-85ca-a48dd555df73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900105062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1900105062
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3686049211
Short name T42
Test name
Test status
Simulation time 33260628 ps
CPU time 0.83 seconds
Started Jun 29 04:53:03 PM PDT 24
Finished Jun 29 04:53:04 PM PDT 24
Peak memory 195648 kb
Host smart-a6fad34a-0dbe-4916-ae18-18b55f3016d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686049211 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3686049211
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.4118262660
Short name T73
Test name
Test status
Simulation time 56072354 ps
CPU time 0.57 seconds
Started Jun 29 04:53:03 PM PDT 24
Finished Jun 29 04:53:04 PM PDT 24
Peak memory 182324 kb
Host smart-6935faae-7dd6-4c59-88d7-8219c1885785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118262660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.4118262660
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4121014373
Short name T550
Test name
Test status
Simulation time 13992638 ps
CPU time 0.53 seconds
Started Jun 29 04:53:11 PM PDT 24
Finished Jun 29 04:53:12 PM PDT 24
Peak memory 181472 kb
Host smart-50c45a26-dd51-4e16-8c77-4ef5149cca16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121014373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4121014373
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.944642648
Short name T503
Test name
Test status
Simulation time 124103000 ps
CPU time 0.75 seconds
Started Jun 29 04:53:07 PM PDT 24
Finished Jun 29 04:53:08 PM PDT 24
Peak memory 191804 kb
Host smart-4b1d09c4-b3cf-4fe5-aabb-f45154f1fb6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944642648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.944642648
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3303766173
Short name T485
Test name
Test status
Simulation time 165519365 ps
CPU time 2.37 seconds
Started Jun 29 04:53:06 PM PDT 24
Finished Jun 29 04:53:09 PM PDT 24
Peak memory 197040 kb
Host smart-8126fae9-7ac5-4566-8aae-b757e31aa9a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303766173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3303766173
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4203764048
Short name T43
Test name
Test status
Simulation time 49369202 ps
CPU time 0.91 seconds
Started Jun 29 04:53:02 PM PDT 24
Finished Jun 29 04:53:03 PM PDT 24
Peak memory 182640 kb
Host smart-f8a0994e-fed6-491a-9edb-a0b52a0bb640
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203764048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4203764048
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.212082016
Short name T378
Test name
Test status
Simulation time 50738645722 ps
CPU time 37.34 seconds
Started Jun 29 04:53:30 PM PDT 24
Finished Jun 29 04:54:08 PM PDT 24
Peak memory 183096 kb
Host smart-c8b9c79d-b863-4387-9124-9a1b43e2d33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212082016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.212082016
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3615564491
Short name T172
Test name
Test status
Simulation time 257962218811 ps
CPU time 135.19 seconds
Started Jun 29 04:53:26 PM PDT 24
Finished Jun 29 04:55:42 PM PDT 24
Peak memory 191348 kb
Host smart-ee1fa18b-40c3-4144-b283-737ecaf757ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615564491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3615564491
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3311394134
Short name T341
Test name
Test status
Simulation time 18752594127 ps
CPU time 17.35 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:53:46 PM PDT 24
Peak memory 183136 kb
Host smart-70dcd190-779e-4ad0-b15f-e7e39ef390b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311394134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3311394134
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3483960817
Short name T365
Test name
Test status
Simulation time 370265609062 ps
CPU time 144.97 seconds
Started Jun 29 04:53:33 PM PDT 24
Finished Jun 29 04:55:59 PM PDT 24
Peak memory 183060 kb
Host smart-68a6080a-a685-4ece-ac50-609b9431c72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483960817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3483960817
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3357379667
Short name T222
Test name
Test status
Simulation time 708623045677 ps
CPU time 510.21 seconds
Started Jun 29 04:53:33 PM PDT 24
Finished Jun 29 05:02:04 PM PDT 24
Peak memory 191312 kb
Host smart-78583c74-3b7d-4f18-b3e0-2b5adec56c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357379667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3357379667
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2456961733
Short name T323
Test name
Test status
Simulation time 46417011036 ps
CPU time 93.64 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:55:02 PM PDT 24
Peak memory 191560 kb
Host smart-f0b684ae-1caa-43a0-9017-f12560eb8edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456961733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2456961733
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.91358787
Short name T14
Test name
Test status
Simulation time 909147694 ps
CPU time 0.93 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:53:30 PM PDT 24
Peak memory 214556 kb
Host smart-d325545f-a7db-4fd5-a0b9-f33bff51be1a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91358787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.91358787
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.307827065
Short name T6
Test name
Test status
Simulation time 22695564711 ps
CPU time 40.5 seconds
Started Jun 29 04:53:43 PM PDT 24
Finished Jun 29 04:54:24 PM PDT 24
Peak memory 183128 kb
Host smart-64245454-e319-4df7-92ed-b1f40f0823a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307827065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.307827065
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3706218977
Short name T441
Test name
Test status
Simulation time 168630236006 ps
CPU time 230.82 seconds
Started Jun 29 04:53:42 PM PDT 24
Finished Jun 29 04:57:33 PM PDT 24
Peak memory 183148 kb
Host smart-b838506a-bd62-4509-b85f-9c27b08f7739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706218977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3706218977
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3390338748
Short name T214
Test name
Test status
Simulation time 202494566210 ps
CPU time 98.41 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 04:55:15 PM PDT 24
Peak memory 191300 kb
Host smart-a0f903b5-ec04-410a-b57d-6958245d2aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390338748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3390338748
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.4022304128
Short name T158
Test name
Test status
Simulation time 362559543262 ps
CPU time 163.17 seconds
Started Jun 29 04:53:35 PM PDT 24
Finished Jun 29 04:56:19 PM PDT 24
Peak memory 191332 kb
Host smart-3030465b-452d-454f-a147-c85651041870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022304128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.4022304128
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2327195331
Short name T41
Test name
Test status
Simulation time 18474685805 ps
CPU time 140.11 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 04:55:57 PM PDT 24
Peak memory 197208 kb
Host smart-0ae2e01d-af2c-419f-b71c-b78d119d0f86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327195331 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2327195331
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.4074317160
Short name T64
Test name
Test status
Simulation time 279701260003 ps
CPU time 200.21 seconds
Started Jun 29 04:54:50 PM PDT 24
Finished Jun 29 04:58:11 PM PDT 24
Peak memory 191312 kb
Host smart-5a0e5268-860b-4270-90bd-6af7622ca804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074317160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4074317160
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2011923641
Short name T140
Test name
Test status
Simulation time 140599992613 ps
CPU time 171.02 seconds
Started Jun 29 04:55:00 PM PDT 24
Finished Jun 29 04:57:51 PM PDT 24
Peak memory 191312 kb
Host smart-09397ca0-73a8-4fc6-a73a-8594f3111eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011923641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2011923641
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1008589057
Short name T185
Test name
Test status
Simulation time 24158856382 ps
CPU time 34.96 seconds
Started Jun 29 04:55:00 PM PDT 24
Finished Jun 29 04:55:35 PM PDT 24
Peak memory 182856 kb
Host smart-e7c2ffe0-04de-4c4b-a535-947a49d0de43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008589057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1008589057
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3718978570
Short name T347
Test name
Test status
Simulation time 29414711196 ps
CPU time 49.59 seconds
Started Jun 29 04:53:35 PM PDT 24
Finished Jun 29 04:54:25 PM PDT 24
Peak memory 183124 kb
Host smart-70dff997-3a76-4d76-91dd-542320294f10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718978570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3718978570
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1469819019
Short name T395
Test name
Test status
Simulation time 548786515530 ps
CPU time 213.52 seconds
Started Jun 29 04:53:37 PM PDT 24
Finished Jun 29 04:57:11 PM PDT 24
Peak memory 183144 kb
Host smart-302aa414-1413-49b6-bd41-388237664783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469819019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1469819019
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.3636442437
Short name T61
Test name
Test status
Simulation time 117993132260 ps
CPU time 442.84 seconds
Started Jun 29 04:53:35 PM PDT 24
Finished Jun 29 05:00:59 PM PDT 24
Peak memory 191288 kb
Host smart-bc392505-4518-4349-9fa7-2807ba018e5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636442437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3636442437
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2101928862
Short name T292
Test name
Test status
Simulation time 63834945545 ps
CPU time 149.95 seconds
Started Jun 29 04:54:59 PM PDT 24
Finished Jun 29 04:57:29 PM PDT 24
Peak memory 191336 kb
Host smart-07e4bf72-0afb-4a81-a51a-9070f90fb418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101928862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2101928862
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.560653458
Short name T1
Test name
Test status
Simulation time 411771514211 ps
CPU time 292.2 seconds
Started Jun 29 04:54:59 PM PDT 24
Finished Jun 29 04:59:51 PM PDT 24
Peak memory 192360 kb
Host smart-cb26f337-fc5a-45d3-9444-c6515f645be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560653458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.560653458
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1625487646
Short name T346
Test name
Test status
Simulation time 623583309873 ps
CPU time 444.99 seconds
Started Jun 29 04:54:58 PM PDT 24
Finished Jun 29 05:02:24 PM PDT 24
Peak memory 191336 kb
Host smart-2311e20a-fcc9-4de4-993f-a50a4dccb09a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625487646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1625487646
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3542231785
Short name T335
Test name
Test status
Simulation time 1402162454129 ps
CPU time 357.53 seconds
Started Jun 29 04:55:11 PM PDT 24
Finished Jun 29 05:01:09 PM PDT 24
Peak memory 191300 kb
Host smart-9d65ed40-1986-461d-a70d-baaf7919dbfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542231785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3542231785
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2723448676
Short name T235
Test name
Test status
Simulation time 24343082371 ps
CPU time 40.19 seconds
Started Jun 29 04:55:08 PM PDT 24
Finished Jun 29 04:55:49 PM PDT 24
Peak memory 191332 kb
Host smart-17cb85f3-39d5-401b-a13a-013bd9d9d52b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723448676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2723448676
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3845978008
Short name T249
Test name
Test status
Simulation time 110711648455 ps
CPU time 785.87 seconds
Started Jun 29 04:55:10 PM PDT 24
Finished Jun 29 05:08:16 PM PDT 24
Peak memory 191332 kb
Host smart-44b4fe80-1afa-4bf0-b910-c97e3e3f20be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845978008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3845978008
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.2907945951
Short name T103
Test name
Test status
Simulation time 1282230652074 ps
CPU time 373.11 seconds
Started Jun 29 04:55:08 PM PDT 24
Finished Jun 29 05:01:21 PM PDT 24
Peak memory 191336 kb
Host smart-3c3439c7-0806-4749-8930-a5bdbd88c6f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907945951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2907945951
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1983501954
Short name T237
Test name
Test status
Simulation time 22082551385 ps
CPU time 73.67 seconds
Started Jun 29 04:55:08 PM PDT 24
Finished Jun 29 04:56:22 PM PDT 24
Peak memory 191328 kb
Host smart-342f0a5d-492d-4995-8adc-40a8957109c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983501954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1983501954
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2352561970
Short name T130
Test name
Test status
Simulation time 713240923240 ps
CPU time 568.8 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 05:03:06 PM PDT 24
Peak memory 183088 kb
Host smart-85102d71-020a-4683-a810-0f93443768b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352561970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2352561970
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.780410422
Short name T407
Test name
Test status
Simulation time 138473441605 ps
CPU time 166.17 seconds
Started Jun 29 04:53:34 PM PDT 24
Finished Jun 29 04:56:21 PM PDT 24
Peak memory 183148 kb
Host smart-b0fbdc4d-81f5-4b6c-bc7d-04fed4019e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780410422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.780410422
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1857812493
Short name T115
Test name
Test status
Simulation time 695008728741 ps
CPU time 423.21 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 05:00:40 PM PDT 24
Peak memory 191340 kb
Host smart-07c05677-c92f-48aa-bf67-3b14b83e47e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857812493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1857812493
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1629828571
Short name T62
Test name
Test status
Simulation time 997945254961 ps
CPU time 1440.47 seconds
Started Jun 29 04:53:37 PM PDT 24
Finished Jun 29 05:17:38 PM PDT 24
Peak memory 194712 kb
Host smart-c29aadef-f6eb-432a-b90c-660fa78e5709
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629828571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1629828571
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.375642867
Short name T37
Test name
Test status
Simulation time 25337139106 ps
CPU time 201.45 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 04:56:58 PM PDT 24
Peak memory 197228 kb
Host smart-913f9b22-9576-4005-a22b-889c02daa31a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375642867 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.375642867
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.2047827040
Short name T131
Test name
Test status
Simulation time 243308534537 ps
CPU time 193.03 seconds
Started Jun 29 04:55:07 PM PDT 24
Finished Jun 29 04:58:21 PM PDT 24
Peak memory 191336 kb
Host smart-04a57682-f9e7-429c-a316-e43b0a4e2221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047827040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2047827040
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.165208670
Short name T271
Test name
Test status
Simulation time 888651173 ps
CPU time 1.9 seconds
Started Jun 29 04:55:09 PM PDT 24
Finished Jun 29 04:55:11 PM PDT 24
Peak memory 182980 kb
Host smart-07e7e99b-aafd-4527-aaac-221c9ca8f540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165208670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.165208670
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3874303568
Short name T254
Test name
Test status
Simulation time 121935773355 ps
CPU time 189.21 seconds
Started Jun 29 04:55:09 PM PDT 24
Finished Jun 29 04:58:18 PM PDT 24
Peak memory 194128 kb
Host smart-8f7e79b7-db58-4685-9c6c-d740f35186c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874303568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3874303568
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3644566918
Short name T266
Test name
Test status
Simulation time 10336528854 ps
CPU time 16.28 seconds
Started Jun 29 04:55:09 PM PDT 24
Finished Jun 29 04:55:25 PM PDT 24
Peak memory 183136 kb
Host smart-fa9deb2c-6fba-4945-83a4-0450eaba02c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644566918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3644566918
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1843621083
Short name T325
Test name
Test status
Simulation time 32805830547 ps
CPU time 82.22 seconds
Started Jun 29 04:55:10 PM PDT 24
Finished Jun 29 04:56:33 PM PDT 24
Peak memory 191336 kb
Host smart-60b3333a-eb3a-43a0-99fd-7f9f7fa5487c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843621083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1843621083
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3199048172
Short name T226
Test name
Test status
Simulation time 722429046988 ps
CPU time 333.35 seconds
Started Jun 29 04:55:10 PM PDT 24
Finished Jun 29 05:00:43 PM PDT 24
Peak memory 191336 kb
Host smart-07efb3aa-9e96-4ca6-be94-37c3430eb9f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199048172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3199048172
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3694326578
Short name T318
Test name
Test status
Simulation time 655153040171 ps
CPU time 275.69 seconds
Started Jun 29 04:55:08 PM PDT 24
Finished Jun 29 04:59:44 PM PDT 24
Peak memory 191336 kb
Host smart-5e807802-025a-4c47-b0db-d2e3c8cbbecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694326578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3694326578
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.765535416
Short name T268
Test name
Test status
Simulation time 137650036601 ps
CPU time 164.14 seconds
Started Jun 29 04:55:09 PM PDT 24
Finished Jun 29 04:57:54 PM PDT 24
Peak memory 183140 kb
Host smart-e8314c7d-3bb5-4dc5-9289-c22f9ae617dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765535416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.765535416
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.345253595
Short name T414
Test name
Test status
Simulation time 28847977270 ps
CPU time 26.22 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 04:55:45 PM PDT 24
Peak memory 191316 kb
Host smart-a0ec92ac-b8e3-4001-badb-a392a77822cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345253595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.345253595
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1771537355
Short name T444
Test name
Test status
Simulation time 212967556891 ps
CPU time 111.1 seconds
Started Jun 29 04:53:35 PM PDT 24
Finished Jun 29 04:55:27 PM PDT 24
Peak memory 183128 kb
Host smart-4775f7e1-4348-4b6c-bd88-e7d454601984
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771537355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1771537355
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2939184241
Short name T400
Test name
Test status
Simulation time 650557798617 ps
CPU time 246.12 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 04:57:43 PM PDT 24
Peak memory 183156 kb
Host smart-515f4413-4283-40ec-9916-3096b343f43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939184241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2939184241
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.579188716
Short name T291
Test name
Test status
Simulation time 679180956448 ps
CPU time 595.31 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 05:03:32 PM PDT 24
Peak memory 191300 kb
Host smart-703392dd-bf0c-4063-ba82-526c2ca397ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579188716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.579188716
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2862881597
Short name T384
Test name
Test status
Simulation time 219659073 ps
CPU time 0.62 seconds
Started Jun 29 04:53:34 PM PDT 24
Finished Jun 29 04:53:35 PM PDT 24
Peak memory 182976 kb
Host smart-76c9b9e1-962a-403b-bce3-70a8087088b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862881597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2862881597
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.828354210
Short name T32
Test name
Test status
Simulation time 124313963294 ps
CPU time 1174.85 seconds
Started Jun 29 04:53:37 PM PDT 24
Finished Jun 29 05:13:12 PM PDT 24
Peak memory 213660 kb
Host smart-f9266834-ee6c-44cb-90f3-c68599179219
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828354210 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.828354210
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.1061024210
Short name T396
Test name
Test status
Simulation time 5189507949 ps
CPU time 45.36 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 04:56:04 PM PDT 24
Peak memory 183136 kb
Host smart-c3722ab4-32c8-4b48-b491-68dd8c9b49cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061024210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1061024210
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1645476575
Short name T137
Test name
Test status
Simulation time 119106373586 ps
CPU time 1233.88 seconds
Started Jun 29 04:55:17 PM PDT 24
Finished Jun 29 05:15:51 PM PDT 24
Peak memory 191332 kb
Host smart-23966b63-fa3e-4220-81c6-57b2e2267c15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645476575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1645476575
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1716685856
Short name T217
Test name
Test status
Simulation time 147204798170 ps
CPU time 86.11 seconds
Started Jun 29 04:55:17 PM PDT 24
Finished Jun 29 04:56:44 PM PDT 24
Peak memory 183004 kb
Host smart-082629f1-a121-47e3-88f5-ff3b3323e599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716685856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1716685856
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2859282043
Short name T394
Test name
Test status
Simulation time 120761067539 ps
CPU time 773.73 seconds
Started Jun 29 04:55:19 PM PDT 24
Finished Jun 29 05:08:13 PM PDT 24
Peak memory 183136 kb
Host smart-36a4aa40-dc08-4453-b929-f18860a749dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859282043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2859282043
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.316197851
Short name T450
Test name
Test status
Simulation time 58489316672 ps
CPU time 43.88 seconds
Started Jun 29 04:55:17 PM PDT 24
Finished Jun 29 04:56:01 PM PDT 24
Peak memory 183036 kb
Host smart-a0c44e4e-ccf4-442d-a98f-6de67087ef36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316197851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.316197851
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3236167323
Short name T304
Test name
Test status
Simulation time 1238312476142 ps
CPU time 651.07 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 05:04:32 PM PDT 24
Peak memory 183116 kb
Host smart-b2a86087-71f9-4914-b18f-c4b778316d5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236167323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3236167323
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3425916252
Short name T406
Test name
Test status
Simulation time 95155473723 ps
CPU time 118.71 seconds
Started Jun 29 04:53:37 PM PDT 24
Finished Jun 29 04:55:36 PM PDT 24
Peak memory 183156 kb
Host smart-1429d8c3-c810-481d-ab0d-019a11e49d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425916252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3425916252
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2906835706
Short name T111
Test name
Test status
Simulation time 180719715251 ps
CPU time 1088.02 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 05:11:45 PM PDT 24
Peak memory 191292 kb
Host smart-b944b1a8-9bce-4dd1-b344-d55f1a703a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906835706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2906835706
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.836373884
Short name T430
Test name
Test status
Simulation time 224892484141 ps
CPU time 66.01 seconds
Started Jun 29 04:53:38 PM PDT 24
Finished Jun 29 04:54:44 PM PDT 24
Peak memory 183156 kb
Host smart-d0ea3481-20b5-4aed-a5f6-7abb2c1d2beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836373884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.836373884
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1418318880
Short name T225
Test name
Test status
Simulation time 1335948374642 ps
CPU time 2000.96 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 05:27:01 PM PDT 24
Peak memory 191328 kb
Host smart-09826564-0170-4e3d-8505-aa9643a4df5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418318880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1418318880
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.317112091
Short name T302
Test name
Test status
Simulation time 103507087528 ps
CPU time 406.36 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 05:02:05 PM PDT 24
Peak memory 194396 kb
Host smart-d4f876ea-aeb7-4676-ae27-e263dec05bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317112091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.317112091
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2481262336
Short name T195
Test name
Test status
Simulation time 14666363133 ps
CPU time 24.81 seconds
Started Jun 29 04:55:16 PM PDT 24
Finished Jun 29 04:55:42 PM PDT 24
Peak memory 183136 kb
Host smart-d7ce50e0-5c7d-43ee-b8ba-b118b0ba7cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481262336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2481262336
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2001961904
Short name T216
Test name
Test status
Simulation time 123394029740 ps
CPU time 192.26 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 04:58:30 PM PDT 24
Peak memory 191292 kb
Host smart-de526cb0-deef-49cf-9599-3c52f88daf37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001961904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2001961904
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1027840558
Short name T405
Test name
Test status
Simulation time 30729743666 ps
CPU time 48.9 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 04:56:08 PM PDT 24
Peak memory 183132 kb
Host smart-645487f8-4998-409d-aa35-26e65f522059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027840558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1027840558
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.53059203
Short name T338
Test name
Test status
Simulation time 106313267809 ps
CPU time 127.36 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 04:57:26 PM PDT 24
Peak memory 191236 kb
Host smart-e1db515f-2db9-42d7-8a4c-06bf524a9c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53059203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.53059203
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.56663892
Short name T263
Test name
Test status
Simulation time 299397798891 ps
CPU time 135.35 seconds
Started Jun 29 04:55:17 PM PDT 24
Finished Jun 29 04:57:33 PM PDT 24
Peak memory 191336 kb
Host smart-19d38ac0-a4f7-4da5-a2de-c73526816a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56663892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.56663892
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.89007610
Short name T447
Test name
Test status
Simulation time 537100821613 ps
CPU time 252.56 seconds
Started Jun 29 04:55:19 PM PDT 24
Finished Jun 29 04:59:32 PM PDT 24
Peak memory 191340 kb
Host smart-d36ce21a-e0e7-46f1-9618-f1271e803a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89007610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.89007610
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2901307902
Short name T296
Test name
Test status
Simulation time 207587659616 ps
CPU time 80.61 seconds
Started Jun 29 04:55:18 PM PDT 24
Finished Jun 29 04:56:39 PM PDT 24
Peak memory 191336 kb
Host smart-6c18a693-77f3-4ded-8d87-882134cfab2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901307902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2901307902
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1883056867
Short name T416
Test name
Test status
Simulation time 176539179981 ps
CPU time 74.95 seconds
Started Jun 29 04:53:43 PM PDT 24
Finished Jun 29 04:54:59 PM PDT 24
Peak memory 183156 kb
Host smart-ae606136-b4e6-4d19-b45a-c0a31dc205dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883056867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1883056867
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3413210520
Short name T238
Test name
Test status
Simulation time 356072065896 ps
CPU time 200.35 seconds
Started Jun 29 04:53:41 PM PDT 24
Finished Jun 29 04:57:02 PM PDT 24
Peak memory 191340 kb
Host smart-fcb7d56d-0a03-459d-b446-2d127265f446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413210520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3413210520
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1260469454
Short name T290
Test name
Test status
Simulation time 112263800465 ps
CPU time 113.67 seconds
Started Jun 29 04:53:41 PM PDT 24
Finished Jun 29 04:55:36 PM PDT 24
Peak memory 191360 kb
Host smart-9de74b03-df3e-4cc6-a031-8bbfafafaffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260469454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1260469454
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.42863481
Short name T156
Test name
Test status
Simulation time 482143600541 ps
CPU time 1187.23 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 05:13:28 PM PDT 24
Peak memory 191236 kb
Host smart-b4b99f1f-e4cf-4e3b-9fff-a2264df13b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42863481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.42863481
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.2242546910
Short name T122
Test name
Test status
Simulation time 720138261130 ps
CPU time 685.07 seconds
Started Jun 29 04:55:29 PM PDT 24
Finished Jun 29 05:06:54 PM PDT 24
Peak memory 191232 kb
Host smart-8a4f236d-a847-4640-a024-78c174a7b4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242546910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2242546910
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1225499372
Short name T135
Test name
Test status
Simulation time 286022344781 ps
CPU time 238.55 seconds
Started Jun 29 04:55:30 PM PDT 24
Finished Jun 29 04:59:29 PM PDT 24
Peak memory 191308 kb
Host smart-c696c3cd-f8cd-45d6-8383-69a6a279c51c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225499372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1225499372
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.488203075
Short name T315
Test name
Test status
Simulation time 7732738496 ps
CPU time 12.31 seconds
Started Jun 29 04:55:28 PM PDT 24
Finished Jun 29 04:55:41 PM PDT 24
Peak memory 191244 kb
Host smart-13cc83ca-f5c5-45bc-8c2a-32eb3e874abe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488203075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.488203075
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.605539974
Short name T281
Test name
Test status
Simulation time 158203385368 ps
CPU time 181.26 seconds
Started Jun 29 04:55:29 PM PDT 24
Finished Jun 29 04:58:30 PM PDT 24
Peak memory 183140 kb
Host smart-0d173096-b35f-4e46-b33b-6b6e503e8172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605539974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.605539974
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.571935027
Short name T344
Test name
Test status
Simulation time 170398885451 ps
CPU time 80.35 seconds
Started Jun 29 04:55:27 PM PDT 24
Finished Jun 29 04:56:48 PM PDT 24
Peak memory 183132 kb
Host smart-5fc739e2-0e99-413f-8809-828a9a7758a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571935027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.571935027
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.307842404
Short name T114
Test name
Test status
Simulation time 102424106616 ps
CPU time 98.26 seconds
Started Jun 29 04:55:30 PM PDT 24
Finished Jun 29 04:57:08 PM PDT 24
Peak memory 191332 kb
Host smart-e4c066e0-02a3-423a-9493-ef78f5f438aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307842404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.307842404
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.545982263
Short name T336
Test name
Test status
Simulation time 122322642815 ps
CPU time 905.49 seconds
Started Jun 29 04:55:30 PM PDT 24
Finished Jun 29 05:10:36 PM PDT 24
Peak memory 191336 kb
Host smart-84ae48c1-a9e0-483f-9cee-f73a0af11fa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545982263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.545982263
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3232854652
Short name T198
Test name
Test status
Simulation time 63082626536 ps
CPU time 99.28 seconds
Started Jun 29 04:55:30 PM PDT 24
Finished Jun 29 04:57:09 PM PDT 24
Peak memory 191320 kb
Host smart-6560e497-4e8a-4f80-a994-d19a69df9526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232854652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3232854652
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4205122334
Short name T202
Test name
Test status
Simulation time 257749328279 ps
CPU time 426.25 seconds
Started Jun 29 04:53:42 PM PDT 24
Finished Jun 29 05:00:49 PM PDT 24
Peak memory 183128 kb
Host smart-93c061af-216b-48dc-b400-65b33f01cc7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205122334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.4205122334
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3645661442
Short name T398
Test name
Test status
Simulation time 86815720593 ps
CPU time 37.71 seconds
Started Jun 29 04:53:42 PM PDT 24
Finished Jun 29 04:54:21 PM PDT 24
Peak memory 183120 kb
Host smart-fc126d34-9833-483f-b5dd-33704fac5137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645661442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3645661442
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.951938165
Short name T206
Test name
Test status
Simulation time 102354688017 ps
CPU time 336.09 seconds
Started Jun 29 04:53:54 PM PDT 24
Finished Jun 29 04:59:30 PM PDT 24
Peak memory 191120 kb
Host smart-6ff93a86-fe67-4236-ac3e-a83a334775e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951938165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.951938165
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1489249269
Short name T417
Test name
Test status
Simulation time 7822109836 ps
CPU time 13.22 seconds
Started Jun 29 04:53:43 PM PDT 24
Finished Jun 29 04:53:58 PM PDT 24
Peak memory 191360 kb
Host smart-d8cf3fed-ab07-476c-9df5-d7053aa8f7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489249269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1489249269
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1240144061
Short name T333
Test name
Test status
Simulation time 733613240501 ps
CPU time 491.2 seconds
Started Jun 29 04:55:30 PM PDT 24
Finished Jun 29 05:03:42 PM PDT 24
Peak memory 191336 kb
Host smart-86e727bd-20de-4725-a789-fc009b98d65c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240144061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1240144061
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.293362689
Short name T231
Test name
Test status
Simulation time 181671114181 ps
CPU time 268.1 seconds
Started Jun 29 04:55:27 PM PDT 24
Finished Jun 29 04:59:55 PM PDT 24
Peak memory 191244 kb
Host smart-49b00dbd-ec8c-43b1-8ddf-a35ceed9744b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293362689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.293362689
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2963604239
Short name T437
Test name
Test status
Simulation time 143525083919 ps
CPU time 69.83 seconds
Started Jun 29 04:55:29 PM PDT 24
Finished Jun 29 04:56:39 PM PDT 24
Peak memory 183128 kb
Host smart-4fafab84-faf0-4c63-beff-8ca8da7fd0be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963604239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2963604239
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2316687678
Short name T275
Test name
Test status
Simulation time 26522636876 ps
CPU time 206.98 seconds
Started Jun 29 04:55:29 PM PDT 24
Finished Jun 29 04:58:56 PM PDT 24
Peak memory 183112 kb
Host smart-77d45596-6896-402b-a55e-0c85f4e80084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316687678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2316687678
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2841978185
Short name T253
Test name
Test status
Simulation time 561778043644 ps
CPU time 304.96 seconds
Started Jun 29 04:55:37 PM PDT 24
Finished Jun 29 05:00:43 PM PDT 24
Peak memory 191244 kb
Host smart-70c4b934-cf86-4e67-a258-307683f4959b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841978185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2841978185
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2129031424
Short name T284
Test name
Test status
Simulation time 27170675757 ps
CPU time 41.24 seconds
Started Jun 29 04:55:41 PM PDT 24
Finished Jun 29 04:56:23 PM PDT 24
Peak memory 191328 kb
Host smart-934f1706-a3c1-4bfe-80de-498cb84f604e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129031424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2129031424
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.950030407
Short name T162
Test name
Test status
Simulation time 74525996909 ps
CPU time 142.29 seconds
Started Jun 29 04:55:38 PM PDT 24
Finished Jun 29 04:58:01 PM PDT 24
Peak memory 191340 kb
Host smart-23dfeed5-1eaa-4c51-b62c-662869a271a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950030407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.950030407
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3157767743
Short name T339
Test name
Test status
Simulation time 871316671687 ps
CPU time 456.81 seconds
Started Jun 29 04:53:42 PM PDT 24
Finished Jun 29 05:01:19 PM PDT 24
Peak memory 183124 kb
Host smart-7c4b9241-95bb-4b5d-9443-8f217b812adc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157767743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3157767743
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1236255652
Short name T389
Test name
Test status
Simulation time 614394592621 ps
CPU time 255.97 seconds
Started Jun 29 04:53:42 PM PDT 24
Finished Jun 29 04:57:59 PM PDT 24
Peak memory 183148 kb
Host smart-063ba99d-11b6-4dae-b7d5-dc6f49229364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236255652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1236255652
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2571043416
Short name T355
Test name
Test status
Simulation time 106230159943 ps
CPU time 49.32 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 04:54:30 PM PDT 24
Peak memory 191360 kb
Host smart-0b5c9313-3d05-4f4e-a488-70b2c564416e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571043416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2571043416
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.110776106
Short name T97
Test name
Test status
Simulation time 199398574277 ps
CPU time 285.93 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 04:58:27 PM PDT 24
Peak memory 191328 kb
Host smart-111333a2-deca-4fa8-baa8-5e77efb770fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110776106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
110776106
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/171.rv_timer_random.736872784
Short name T280
Test name
Test status
Simulation time 610658142355 ps
CPU time 377.72 seconds
Started Jun 29 04:55:41 PM PDT 24
Finished Jun 29 05:02:00 PM PDT 24
Peak memory 191324 kb
Host smart-22653a2b-8cc8-4cee-afa7-a7ce6a10dbd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736872784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.736872784
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1947753532
Short name T197
Test name
Test status
Simulation time 68262270097 ps
CPU time 264.16 seconds
Started Jun 29 04:55:39 PM PDT 24
Finished Jun 29 05:00:04 PM PDT 24
Peak memory 191336 kb
Host smart-1dae58a6-3afd-41fa-bec0-b74ce12f8882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947753532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1947753532
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3765911197
Short name T306
Test name
Test status
Simulation time 299848234863 ps
CPU time 922.74 seconds
Started Jun 29 04:55:38 PM PDT 24
Finished Jun 29 05:11:01 PM PDT 24
Peak memory 191336 kb
Host smart-4463c22f-b0a1-4c96-a931-ac3afbc6ceb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765911197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3765911197
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.35297317
Short name T183
Test name
Test status
Simulation time 5299821063 ps
CPU time 8.27 seconds
Started Jun 29 04:55:37 PM PDT 24
Finished Jun 29 04:55:45 PM PDT 24
Peak memory 191148 kb
Host smart-d6a54be2-552a-4331-b4e9-4d86482c0906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35297317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.35297317
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2520789359
Short name T354
Test name
Test status
Simulation time 221354437813 ps
CPU time 374.67 seconds
Started Jun 29 04:55:38 PM PDT 24
Finished Jun 29 05:01:53 PM PDT 24
Peak memory 191328 kb
Host smart-9bfda39b-46a2-4ad4-b072-a4fed1c51a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520789359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2520789359
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3494809676
Short name T23
Test name
Test status
Simulation time 601708896876 ps
CPU time 394.95 seconds
Started Jun 29 04:55:41 PM PDT 24
Finished Jun 29 05:02:17 PM PDT 24
Peak memory 191332 kb
Host smart-ae588820-17a4-47f7-afc8-92eb39d0aa00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494809676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3494809676
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2231861363
Short name T169
Test name
Test status
Simulation time 359051024070 ps
CPU time 1050.87 seconds
Started Jun 29 04:55:37 PM PDT 24
Finished Jun 29 05:13:08 PM PDT 24
Peak memory 192604 kb
Host smart-08d3c13f-fbbf-4c55-92e0-efcaf4884867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231861363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2231861363
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.87015482
Short name T425
Test name
Test status
Simulation time 529177645852 ps
CPU time 480.79 seconds
Started Jun 29 04:55:45 PM PDT 24
Finished Jun 29 05:03:47 PM PDT 24
Peak memory 191340 kb
Host smart-1cc62ed2-81fc-4f44-8305-31192c9e91e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87015482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.87015482
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3916530300
Short name T274
Test name
Test status
Simulation time 1570999519983 ps
CPU time 543.35 seconds
Started Jun 29 04:53:43 PM PDT 24
Finished Jun 29 05:02:47 PM PDT 24
Peak memory 183128 kb
Host smart-617c341f-ba01-4a4d-9780-1e53345d41a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916530300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3916530300
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.4210811390
Short name T421
Test name
Test status
Simulation time 161916034472 ps
CPU time 54.93 seconds
Started Jun 29 04:53:44 PM PDT 24
Finished Jun 29 04:54:40 PM PDT 24
Peak memory 183156 kb
Host smart-73685422-ff55-4491-8feb-16aa7e31f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210811390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.4210811390
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.410903726
Short name T348
Test name
Test status
Simulation time 63288910271 ps
CPU time 161.25 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 04:56:21 PM PDT 24
Peak memory 191336 kb
Host smart-f87fffb5-ca42-4c55-a035-c2d4af64b7fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410903726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.410903726
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.949199969
Short name T310
Test name
Test status
Simulation time 129077968715 ps
CPU time 266.7 seconds
Started Jun 29 04:53:43 PM PDT 24
Finished Jun 29 04:58:11 PM PDT 24
Peak memory 182884 kb
Host smart-eaf2dc00-3616-473b-b8fe-d4aabbbed238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949199969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.949199969
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.403947358
Short name T259
Test name
Test status
Simulation time 140718118240 ps
CPU time 188.79 seconds
Started Jun 29 04:55:49 PM PDT 24
Finished Jun 29 04:58:58 PM PDT 24
Peak memory 194044 kb
Host smart-d8e7bc20-4be4-4702-9264-54625fb74b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403947358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.403947358
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3856927824
Short name T129
Test name
Test status
Simulation time 45485656185 ps
CPU time 65.84 seconds
Started Jun 29 04:55:44 PM PDT 24
Finished Jun 29 04:56:51 PM PDT 24
Peak memory 183088 kb
Host smart-eeafdabc-0e8a-43b1-8684-ce48f4a527c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856927824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3856927824
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.4012304755
Short name T212
Test name
Test status
Simulation time 65856871459 ps
CPU time 1310.7 seconds
Started Jun 29 04:55:45 PM PDT 24
Finished Jun 29 05:17:37 PM PDT 24
Peak memory 192568 kb
Host smart-31b4f633-2204-4c8e-a443-57cd05a9b7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012304755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.4012304755
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1544938927
Short name T286
Test name
Test status
Simulation time 96888882159 ps
CPU time 39.27 seconds
Started Jun 29 04:55:45 PM PDT 24
Finished Jun 29 04:56:25 PM PDT 24
Peak memory 191336 kb
Host smart-b3fcd41b-6e98-4e89-9201-bd48b4aeec71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544938927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1544938927
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3188724066
Short name T170
Test name
Test status
Simulation time 152535358874 ps
CPU time 103.97 seconds
Started Jun 29 04:55:54 PM PDT 24
Finished Jun 29 04:57:39 PM PDT 24
Peak memory 191328 kb
Host smart-ad89a6a4-e32e-4fe4-b6de-074f58de1c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188724066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3188724066
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.4085156339
Short name T438
Test name
Test status
Simulation time 173425335963 ps
CPU time 88.82 seconds
Started Jun 29 04:55:54 PM PDT 24
Finished Jun 29 04:57:23 PM PDT 24
Peak memory 183136 kb
Host smart-7fe0bc38-6b49-4192-af22-1d032f3aa26d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085156339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.4085156339
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.813455010
Short name T39
Test name
Test status
Simulation time 295902302912 ps
CPU time 174.24 seconds
Started Jun 29 04:53:43 PM PDT 24
Finished Jun 29 04:56:39 PM PDT 24
Peak memory 183104 kb
Host smart-0b399b07-de2a-431e-9e99-95d1673669c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813455010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.813455010
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1656648251
Short name T168
Test name
Test status
Simulation time 63502990785 ps
CPU time 268.61 seconds
Started Jun 29 04:53:43 PM PDT 24
Finished Jun 29 04:58:13 PM PDT 24
Peak memory 191340 kb
Host smart-c2544911-f9dc-4c5f-be2c-58275f2d6e6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656648251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1656648251
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3969590363
Short name T446
Test name
Test status
Simulation time 28894597966 ps
CPU time 57.41 seconds
Started Jun 29 04:53:41 PM PDT 24
Finished Jun 29 04:54:39 PM PDT 24
Peak memory 191336 kb
Host smart-eeee2000-35eb-4ca4-8e7c-c74d52e679fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969590363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3969590363
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2527488480
Short name T93
Test name
Test status
Simulation time 461521689098 ps
CPU time 2432.12 seconds
Started Jun 29 04:55:56 PM PDT 24
Finished Jun 29 05:36:29 PM PDT 24
Peak memory 191236 kb
Host smart-63f1b8e3-b220-45bc-bb26-6779639f89dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527488480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2527488480
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1340621540
Short name T311
Test name
Test status
Simulation time 70430711399 ps
CPU time 1383.07 seconds
Started Jun 29 04:55:54 PM PDT 24
Finished Jun 29 05:18:57 PM PDT 24
Peak memory 183128 kb
Host smart-5d8f1d73-d339-4358-a978-fe8eb970ec71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340621540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1340621540
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1375236043
Short name T239
Test name
Test status
Simulation time 92188625208 ps
CPU time 167.16 seconds
Started Jun 29 04:55:56 PM PDT 24
Finished Jun 29 04:58:44 PM PDT 24
Peak memory 191336 kb
Host smart-0890214c-c503-4493-8f2b-f20535644e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375236043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1375236043
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3674788417
Short name T165
Test name
Test status
Simulation time 301512989140 ps
CPU time 723.22 seconds
Started Jun 29 04:55:57 PM PDT 24
Finished Jun 29 05:08:00 PM PDT 24
Peak memory 191236 kb
Host smart-1422a4d3-2101-4190-b996-b861ee9d6a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674788417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3674788417
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.419471679
Short name T94
Test name
Test status
Simulation time 192580276860 ps
CPU time 679.66 seconds
Started Jun 29 04:56:03 PM PDT 24
Finished Jun 29 05:07:23 PM PDT 24
Peak memory 191340 kb
Host smart-bcd81343-837d-47ad-a537-ea7bae9a423f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419471679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.419471679
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2278785951
Short name T334
Test name
Test status
Simulation time 54227539911 ps
CPU time 85.57 seconds
Started Jun 29 04:53:26 PM PDT 24
Finished Jun 29 04:54:52 PM PDT 24
Peak memory 183136 kb
Host smart-23394861-fa3e-4f4c-b76a-5511e8202929
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278785951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2278785951
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.153254120
Short name T401
Test name
Test status
Simulation time 54683766383 ps
CPU time 73 seconds
Started Jun 29 04:53:34 PM PDT 24
Finished Jun 29 04:54:47 PM PDT 24
Peak memory 183036 kb
Host smart-917740f9-f958-4cdd-8dca-869695b2d8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153254120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.153254120
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.4144384861
Short name T372
Test name
Test status
Simulation time 19339621897 ps
CPU time 15.51 seconds
Started Jun 29 04:53:29 PM PDT 24
Finished Jun 29 04:53:45 PM PDT 24
Peak memory 183124 kb
Host smart-1c94c840-35f9-41b3-ab5c-2d3c87f5654f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144384861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.4144384861
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.555058756
Short name T12
Test name
Test status
Simulation time 119707942 ps
CPU time 0.74 seconds
Started Jun 29 04:53:27 PM PDT 24
Finished Jun 29 04:53:29 PM PDT 24
Peak memory 213316 kb
Host smart-724339b0-186f-4013-bb5b-9958aa821817
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555058756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.555058756
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.849678056
Short name T381
Test name
Test status
Simulation time 190660757 ps
CPU time 0.6 seconds
Started Jun 29 04:53:30 PM PDT 24
Finished Jun 29 04:53:31 PM PDT 24
Peak memory 182968 kb
Host smart-33051bb0-893d-4528-b870-b60a36cea177
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849678056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.849678056
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2608992169
Short name T21
Test name
Test status
Simulation time 141486845692 ps
CPU time 64.66 seconds
Started Jun 29 04:53:41 PM PDT 24
Finished Jun 29 04:54:46 PM PDT 24
Peak memory 183096 kb
Host smart-4b051aae-3516-407d-9bb6-e90b88814b64
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608992169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2608992169
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4185018046
Short name T397
Test name
Test status
Simulation time 699379053046 ps
CPU time 313.13 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 04:58:54 PM PDT 24
Peak memory 183156 kb
Host smart-c03c24da-9f02-4957-90bc-3b619de315f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185018046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4185018046
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3193261630
Short name T413
Test name
Test status
Simulation time 62403221477 ps
CPU time 30.91 seconds
Started Jun 29 04:53:44 PM PDT 24
Finished Jun 29 04:54:16 PM PDT 24
Peak memory 191332 kb
Host smart-f4eb1a50-a289-4aa9-803e-c4394da3fafb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193261630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3193261630
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1450824153
Short name T404
Test name
Test status
Simulation time 408411255 ps
CPU time 1.56 seconds
Started Jun 29 04:53:44 PM PDT 24
Finished Jun 29 04:53:46 PM PDT 24
Peak memory 183096 kb
Host smart-7d2725e2-f007-4cde-9952-5ef970ae8344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450824153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1450824153
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1369726383
Short name T300
Test name
Test status
Simulation time 981476599566 ps
CPU time 420.5 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 05:00:42 PM PDT 24
Peak memory 191236 kb
Host smart-c10a953d-4876-46af-9d04-394cf6fbebe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369726383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1369726383
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.4052732475
Short name T436
Test name
Test status
Simulation time 9808645726 ps
CPU time 16.61 seconds
Started Jun 29 04:53:40 PM PDT 24
Finished Jun 29 04:53:58 PM PDT 24
Peak memory 183124 kb
Host smart-a7b64a75-a7c5-4b66-8710-6a431f634673
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052732475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.4052732475
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1783655701
Short name T440
Test name
Test status
Simulation time 89142888764 ps
CPU time 131.43 seconds
Started Jun 29 04:53:44 PM PDT 24
Finished Jun 29 04:55:56 PM PDT 24
Peak memory 183128 kb
Host smart-162a6879-a2cb-4df7-840b-541f49ae9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783655701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1783655701
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.357284621
Short name T166
Test name
Test status
Simulation time 147870401664 ps
CPU time 274.66 seconds
Started Jun 29 04:53:51 PM PDT 24
Finished Jun 29 04:58:26 PM PDT 24
Peak memory 190972 kb
Host smart-ab32c833-45e4-47b0-b277-5a8ec2874901
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357284621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.357284621
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1000536121
Short name T427
Test name
Test status
Simulation time 69831221229 ps
CPU time 38.34 seconds
Started Jun 29 04:53:41 PM PDT 24
Finished Jun 29 04:54:20 PM PDT 24
Peak memory 183160 kb
Host smart-67557524-a8fb-40e3-b554-d70138249c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000536121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1000536121
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3313381749
Short name T393
Test name
Test status
Simulation time 150484615071 ps
CPU time 195.23 seconds
Started Jun 29 04:53:41 PM PDT 24
Finished Jun 29 04:56:57 PM PDT 24
Peak memory 183128 kb
Host smart-51d6f178-ceb5-4f3f-abb0-afee10239736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313381749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3313381749
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4223604119
Short name T303
Test name
Test status
Simulation time 573506016461 ps
CPU time 1012.41 seconds
Started Jun 29 04:53:43 PM PDT 24
Finished Jun 29 05:10:37 PM PDT 24
Peak memory 183128 kb
Host smart-ccd65986-ba90-4daa-8ec3-ca30d1b1b3bc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223604119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4223604119
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.351371559
Short name T386
Test name
Test status
Simulation time 117919930705 ps
CPU time 84.56 seconds
Started Jun 29 04:53:45 PM PDT 24
Finished Jun 29 04:55:10 PM PDT 24
Peak memory 183156 kb
Host smart-47eccec4-52b6-4ccb-ab9a-f768c4608e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351371559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.351371559
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3609905086
Short name T228
Test name
Test status
Simulation time 587810365695 ps
CPU time 1015.19 seconds
Started Jun 29 04:53:43 PM PDT 24
Finished Jun 29 05:10:40 PM PDT 24
Peak memory 191296 kb
Host smart-0d5fdd72-75fb-4cd3-bf1e-e24f2523dcd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609905086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3609905086
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2006662622
Short name T312
Test name
Test status
Simulation time 173300048191 ps
CPU time 153.13 seconds
Started Jun 29 04:53:51 PM PDT 24
Finished Jun 29 04:56:25 PM PDT 24
Peak memory 191132 kb
Host smart-a634c61a-6047-4ebf-8c1f-eb24f9a610be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006662622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2006662622
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3555600503
Short name T35
Test name
Test status
Simulation time 45053912347 ps
CPU time 358.92 seconds
Started Jun 29 04:53:45 PM PDT 24
Finished Jun 29 04:59:45 PM PDT 24
Peak memory 197816 kb
Host smart-81ab92fa-3cfe-4a2f-8416-3cd91dfa0b0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555600503 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3555600503
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.270886680
Short name T410
Test name
Test status
Simulation time 70889011385 ps
CPU time 121.24 seconds
Started Jun 29 04:53:46 PM PDT 24
Finished Jun 29 04:55:48 PM PDT 24
Peak memory 182944 kb
Host smart-c801318d-f1d5-4b19-ac23-938d68a48b75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270886680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.270886680
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1962530136
Short name T364
Test name
Test status
Simulation time 78214548062 ps
CPU time 99.21 seconds
Started Jun 29 04:53:48 PM PDT 24
Finished Jun 29 04:55:28 PM PDT 24
Peak memory 183128 kb
Host smart-f4aa61b8-1f13-4a3e-8cf1-2f6d3d19bbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962530136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1962530136
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2557465709
Short name T351
Test name
Test status
Simulation time 1085924990616 ps
CPU time 645.5 seconds
Started Jun 29 04:53:52 PM PDT 24
Finished Jun 29 05:04:38 PM PDT 24
Peak memory 191332 kb
Host smart-26c66b3e-19bb-4dc2-9db3-79df04c5f8c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557465709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2557465709
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1299011098
Short name T443
Test name
Test status
Simulation time 1290492337324 ps
CPU time 709.51 seconds
Started Jun 29 04:53:51 PM PDT 24
Finished Jun 29 05:05:41 PM PDT 24
Peak memory 183096 kb
Host smart-5c39186a-2bd1-482b-8ae8-d28ddf07a553
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299011098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1299011098
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2114667731
Short name T22
Test name
Test status
Simulation time 60931184179 ps
CPU time 44.77 seconds
Started Jun 29 04:53:51 PM PDT 24
Finished Jun 29 04:54:37 PM PDT 24
Peak memory 183012 kb
Host smart-ff05ab51-82d3-4af2-a074-7ba1c4463614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114667731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2114667731
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.4068852219
Short name T257
Test name
Test status
Simulation time 130157493919 ps
CPU time 160.19 seconds
Started Jun 29 04:53:47 PM PDT 24
Finished Jun 29 04:56:28 PM PDT 24
Peak memory 191264 kb
Host smart-97b57310-74b4-4724-bc1d-a3a80330fb3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068852219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.4068852219
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2848504572
Short name T283
Test name
Test status
Simulation time 1653162797189 ps
CPU time 638.87 seconds
Started Jun 29 04:53:51 PM PDT 24
Finished Jun 29 05:04:31 PM PDT 24
Peak memory 183124 kb
Host smart-e72e4b81-1c37-4771-8a13-d7bfd4f9ce42
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848504572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2848504572
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3120033725
Short name T366
Test name
Test status
Simulation time 128356647596 ps
CPU time 197.93 seconds
Started Jun 29 04:53:49 PM PDT 24
Finished Jun 29 04:57:08 PM PDT 24
Peak memory 183108 kb
Host smart-9adc8ce6-e6cb-4905-b87f-6ec8798a33a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120033725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3120033725
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3095303330
Short name T317
Test name
Test status
Simulation time 865569573130 ps
CPU time 678.96 seconds
Started Jun 29 04:53:52 PM PDT 24
Finished Jun 29 05:05:12 PM PDT 24
Peak memory 193384 kb
Host smart-d681f104-475b-460c-a3c8-1e5ef2694eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095303330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3095303330
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3754809263
Short name T449
Test name
Test status
Simulation time 189232446882 ps
CPU time 90.46 seconds
Started Jun 29 04:53:47 PM PDT 24
Finished Jun 29 04:55:18 PM PDT 24
Peak memory 191236 kb
Host smart-bd6c67f9-6589-4af6-a1ad-c0f1da35de94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754809263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3754809263
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2637627917
Short name T144
Test name
Test status
Simulation time 909535637880 ps
CPU time 1103.08 seconds
Started Jun 29 04:53:49 PM PDT 24
Finished Jun 29 05:12:13 PM PDT 24
Peak memory 191332 kb
Host smart-6d606fa8-4466-4dd8-b8ca-e8a31c5689b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637627917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2637627917
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3192396086
Short name T33
Test name
Test status
Simulation time 268719066435 ps
CPU time 498.49 seconds
Started Jun 29 04:53:50 PM PDT 24
Finished Jun 29 05:02:09 PM PDT 24
Peak memory 205948 kb
Host smart-35831c8f-f885-4aa0-a08f-31a2b4822897
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192396086 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.3192396086
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2858622030
Short name T388
Test name
Test status
Simulation time 117317677757 ps
CPU time 173.2 seconds
Started Jun 29 04:53:54 PM PDT 24
Finished Jun 29 04:56:48 PM PDT 24
Peak memory 182920 kb
Host smart-ae810019-7ab8-438d-8936-496077c9b838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858622030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2858622030
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2495054771
Short name T189
Test name
Test status
Simulation time 548976652889 ps
CPU time 412.16 seconds
Started Jun 29 04:53:49 PM PDT 24
Finished Jun 29 05:00:42 PM PDT 24
Peak memory 191232 kb
Host smart-e073fdb4-81e9-43ad-8f20-78e329657ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495054771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2495054771
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.628558214
Short name T424
Test name
Test status
Simulation time 74804104270 ps
CPU time 31.86 seconds
Started Jun 29 04:53:52 PM PDT 24
Finished Jun 29 04:54:24 PM PDT 24
Peak memory 183060 kb
Host smart-ad2662d0-ab06-49d1-81aa-5ca7444e5529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628558214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.628558214
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.2268530621
Short name T34
Test name
Test status
Simulation time 89694162956 ps
CPU time 510.51 seconds
Started Jun 29 04:53:47 PM PDT 24
Finished Jun 29 05:02:18 PM PDT 24
Peak memory 206024 kb
Host smart-d0b6505b-5112-4efe-84b2-7e617076e0e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268530621 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.2268530621
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1011853763
Short name T426
Test name
Test status
Simulation time 28880657654 ps
CPU time 49.03 seconds
Started Jun 29 04:53:50 PM PDT 24
Finished Jun 29 04:54:39 PM PDT 24
Peak memory 183024 kb
Host smart-4e999944-f4ed-4422-945c-b68b3180203a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011853763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1011853763
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2785221734
Short name T363
Test name
Test status
Simulation time 134991077804 ps
CPU time 168.51 seconds
Started Jun 29 04:53:48 PM PDT 24
Finished Jun 29 04:56:37 PM PDT 24
Peak memory 183144 kb
Host smart-6494ccd8-005a-4196-aa9d-02dd3f9b1699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785221734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2785221734
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.589431750
Short name T342
Test name
Test status
Simulation time 128880502155 ps
CPU time 128.72 seconds
Started Jun 29 04:53:48 PM PDT 24
Finished Jun 29 04:55:58 PM PDT 24
Peak memory 191240 kb
Host smart-faa3390f-3852-4191-8536-49fee6a2256d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589431750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.589431750
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3372356311
Short name T390
Test name
Test status
Simulation time 196977649576 ps
CPU time 266.19 seconds
Started Jun 29 04:53:48 PM PDT 24
Finished Jun 29 04:58:15 PM PDT 24
Peak memory 191332 kb
Host smart-92f264ae-ffcd-400f-8c20-5dc632a157ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372356311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3372356311
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.1247388443
Short name T36
Test name
Test status
Simulation time 33111896242 ps
CPU time 275.37 seconds
Started Jun 29 04:53:50 PM PDT 24
Finished Jun 29 04:58:26 PM PDT 24
Peak memory 206040 kb
Host smart-67e90375-95c8-44c2-8c32-59c1593a7167
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247388443 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.1247388443
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.4150599891
Short name T175
Test name
Test status
Simulation time 478330146093 ps
CPU time 415.94 seconds
Started Jun 29 04:53:47 PM PDT 24
Finished Jun 29 05:00:44 PM PDT 24
Peak memory 183100 kb
Host smart-493ffd69-1a87-4345-bf35-1e2935e5b035
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150599891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.4150599891
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.661856527
Short name T360
Test name
Test status
Simulation time 477829209997 ps
CPU time 182.82 seconds
Started Jun 29 04:53:52 PM PDT 24
Finished Jun 29 04:56:55 PM PDT 24
Peak memory 183148 kb
Host smart-e9dcbf08-bb3e-4259-9296-2275adc5e59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661856527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.661856527
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2266418210
Short name T327
Test name
Test status
Simulation time 717986449500 ps
CPU time 225.42 seconds
Started Jun 29 04:53:49 PM PDT 24
Finished Jun 29 04:57:35 PM PDT 24
Peak memory 191292 kb
Host smart-6a574277-2ec3-4694-a649-5fb84f03e304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266418210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2266418210
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3606803859
Short name T104
Test name
Test status
Simulation time 30079990495 ps
CPU time 48.33 seconds
Started Jun 29 04:53:51 PM PDT 24
Finished Jun 29 04:54:40 PM PDT 24
Peak memory 183152 kb
Host smart-4b230a45-6f45-4ff7-9304-97ceab478a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606803859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3606803859
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1293008191
Short name T399
Test name
Test status
Simulation time 125293724409 ps
CPU time 179.1 seconds
Started Jun 29 04:53:51 PM PDT 24
Finished Jun 29 04:56:50 PM PDT 24
Peak memory 191328 kb
Host smart-6484b300-b6f6-426b-ac15-d5983b347211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293008191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1293008191
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3826679611
Short name T402
Test name
Test status
Simulation time 652412208926 ps
CPU time 252.42 seconds
Started Jun 29 04:53:48 PM PDT 24
Finished Jun 29 04:58:00 PM PDT 24
Peak memory 183156 kb
Host smart-3638f3be-de5d-488b-a84f-99e73b6b000c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826679611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3826679611
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2458247918
Short name T92
Test name
Test status
Simulation time 240543830411 ps
CPU time 239.09 seconds
Started Jun 29 04:53:48 PM PDT 24
Finished Jun 29 04:57:48 PM PDT 24
Peak memory 191340 kb
Host smart-6c522b1d-b428-4967-861f-4f2bd2cc4bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458247918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2458247918
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2456802590
Short name T57
Test name
Test status
Simulation time 325029634 ps
CPU time 0.89 seconds
Started Jun 29 04:53:52 PM PDT 24
Finished Jun 29 04:53:54 PM PDT 24
Peak memory 183008 kb
Host smart-5c666de2-5fcf-4b66-9fce-a3e267e70567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456802590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2456802590
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1587011312
Short name T411
Test name
Test status
Simulation time 652738277808 ps
CPU time 256.31 seconds
Started Jun 29 04:53:51 PM PDT 24
Finished Jun 29 04:58:08 PM PDT 24
Peak memory 183136 kb
Host smart-fe0fce35-685e-4093-97b2-774cbf7e4456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587011312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1587011312
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4060366113
Short name T99
Test name
Test status
Simulation time 219066911846 ps
CPU time 218.14 seconds
Started Jun 29 04:53:27 PM PDT 24
Finished Jun 29 04:57:06 PM PDT 24
Peak memory 183100 kb
Host smart-5c8a2199-2466-4bbd-854b-7aa356190371
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060366113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4060366113
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3665638562
Short name T420
Test name
Test status
Simulation time 322075322019 ps
CPU time 42.87 seconds
Started Jun 29 04:53:29 PM PDT 24
Finished Jun 29 04:54:13 PM PDT 24
Peak memory 183128 kb
Host smart-99351161-3de9-4bdd-80eb-d5ab3d13d7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665638562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3665638562
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.303033348
Short name T277
Test name
Test status
Simulation time 159492806134 ps
CPU time 124.42 seconds
Started Jun 29 04:53:27 PM PDT 24
Finished Jun 29 04:55:33 PM PDT 24
Peak memory 191240 kb
Host smart-1cc24969-0a23-40a4-8384-ab4afc867d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303033348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.303033348
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1534065962
Short name T419
Test name
Test status
Simulation time 126813306303 ps
CPU time 113.49 seconds
Started Jun 29 04:53:34 PM PDT 24
Finished Jun 29 04:55:28 PM PDT 24
Peak memory 191124 kb
Host smart-d5981ba5-c954-494f-96c3-8401407200e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534065962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1534065962
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3906509311
Short name T15
Test name
Test status
Simulation time 383163932 ps
CPU time 0.89 seconds
Started Jun 29 04:53:32 PM PDT 24
Finished Jun 29 04:53:33 PM PDT 24
Peak memory 213440 kb
Host smart-f0afda6f-a67c-4c7b-91c3-4ede9906e0b7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906509311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3906509311
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1746881675
Short name T91
Test name
Test status
Simulation time 1727398978006 ps
CPU time 857.4 seconds
Started Jun 29 04:53:50 PM PDT 24
Finished Jun 29 05:08:09 PM PDT 24
Peak memory 183056 kb
Host smart-a29c3cae-fb6a-4bff-a3fa-99714343e7f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746881675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1746881675
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.4024959080
Short name T375
Test name
Test status
Simulation time 53369186712 ps
CPU time 43.13 seconds
Started Jun 29 04:53:52 PM PDT 24
Finished Jun 29 04:54:36 PM PDT 24
Peak memory 183156 kb
Host smart-2bbab52f-cbde-42eb-83f9-e6142c1ba3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024959080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.4024959080
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3338887851
Short name T319
Test name
Test status
Simulation time 195143939669 ps
CPU time 94.71 seconds
Started Jun 29 04:53:50 PM PDT 24
Finished Jun 29 04:55:26 PM PDT 24
Peak memory 183140 kb
Host smart-1bcb81f7-af75-4ae8-9d13-ab529acf3fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338887851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3338887851
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2190621233
Short name T434
Test name
Test status
Simulation time 149182855029 ps
CPU time 1877.8 seconds
Started Jun 29 04:53:52 PM PDT 24
Finished Jun 29 05:25:11 PM PDT 24
Peak memory 191360 kb
Host smart-549a86f1-59de-43c6-b881-349a98939e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190621233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2190621233
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1439250489
Short name T58
Test name
Test status
Simulation time 97058809133 ps
CPU time 113.81 seconds
Started Jun 29 04:53:57 PM PDT 24
Finished Jun 29 04:55:52 PM PDT 24
Peak memory 191328 kb
Host smart-767eaa03-5689-47ba-b2f9-fc8e5b1fafe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439250489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1439250489
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1543502892
Short name T191
Test name
Test status
Simulation time 29165149247 ps
CPU time 16.29 seconds
Started Jun 29 04:53:57 PM PDT 24
Finished Jun 29 04:54:14 PM PDT 24
Peak memory 183128 kb
Host smart-3aeb78ba-914c-4075-9283-b3ecdd11beec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543502892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1543502892
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.550204901
Short name T377
Test name
Test status
Simulation time 151651662693 ps
CPU time 189.83 seconds
Started Jun 29 04:53:57 PM PDT 24
Finished Jun 29 04:57:08 PM PDT 24
Peak memory 183360 kb
Host smart-c43ba358-e2c6-4e45-b421-83c11928eef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550204901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.550204901
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3292932022
Short name T278
Test name
Test status
Simulation time 31056649286 ps
CPU time 344.65 seconds
Started Jun 29 04:53:57 PM PDT 24
Finished Jun 29 04:59:43 PM PDT 24
Peak memory 183160 kb
Host smart-5c4f4fb2-8474-43ef-8def-0efc3b3f3056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292932022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3292932022
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.2222755358
Short name T5
Test name
Test status
Simulation time 21510101168 ps
CPU time 159.32 seconds
Started Jun 29 04:53:55 PM PDT 24
Finished Jun 29 04:56:36 PM PDT 24
Peak memory 197808 kb
Host smart-4b84b9e0-866e-4212-b284-81b95b87fb8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222755358 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.2222755358
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.517161128
Short name T138
Test name
Test status
Simulation time 387700639823 ps
CPU time 188.61 seconds
Started Jun 29 04:53:55 PM PDT 24
Finished Jun 29 04:57:04 PM PDT 24
Peak memory 183124 kb
Host smart-a7ca1fd3-8446-4fe5-a5e9-10cb557db174
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517161128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.517161128
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1926093967
Short name T362
Test name
Test status
Simulation time 113043929013 ps
CPU time 83.84 seconds
Started Jun 29 04:53:55 PM PDT 24
Finished Jun 29 04:55:20 PM PDT 24
Peak memory 183048 kb
Host smart-ae854b9f-593d-43f9-a3b7-c42b6f919e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926093967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1926093967
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.546695025
Short name T150
Test name
Test status
Simulation time 218477662384 ps
CPU time 259.14 seconds
Started Jun 29 04:53:58 PM PDT 24
Finished Jun 29 04:58:18 PM PDT 24
Peak memory 191344 kb
Host smart-6476a219-c18e-4235-b7dc-0bbef4fd75dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546695025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.546695025
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.111859753
Short name T349
Test name
Test status
Simulation time 32636109340 ps
CPU time 172.27 seconds
Started Jun 29 04:53:55 PM PDT 24
Finished Jun 29 04:56:49 PM PDT 24
Peak memory 183156 kb
Host smart-dd3a5e13-71e6-4a74-86ae-91f39e220163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111859753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.111859753
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3271259427
Short name T100
Test name
Test status
Simulation time 355976547692 ps
CPU time 543.29 seconds
Started Jun 29 04:53:55 PM PDT 24
Finished Jun 29 05:02:59 PM PDT 24
Peak memory 195904 kb
Host smart-89b81334-f292-4fb1-8347-47fcfb795ca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271259427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3271259427
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3464924635
Short name T188
Test name
Test status
Simulation time 728033192479 ps
CPU time 384.56 seconds
Started Jun 29 04:53:59 PM PDT 24
Finished Jun 29 05:00:24 PM PDT 24
Peak memory 183124 kb
Host smart-9c828d3c-ce51-4b4f-bee8-fda969457b10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464924635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3464924635
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3737540543
Short name T392
Test name
Test status
Simulation time 220980163492 ps
CPU time 180.34 seconds
Started Jun 29 04:53:57 PM PDT 24
Finished Jun 29 04:56:58 PM PDT 24
Peak memory 183156 kb
Host smart-34a1af59-451d-4598-81e2-6ac1bb15f75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737540543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3737540543
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1771528317
Short name T205
Test name
Test status
Simulation time 841777504387 ps
CPU time 680.86 seconds
Started Jun 29 04:53:59 PM PDT 24
Finished Jun 29 05:05:21 PM PDT 24
Peak memory 194704 kb
Host smart-3267342a-eb01-47ab-a301-3ab8fa3d879a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771528317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1771528317
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2651867735
Short name T313
Test name
Test status
Simulation time 12267754695 ps
CPU time 11.73 seconds
Started Jun 29 04:53:56 PM PDT 24
Finished Jun 29 04:54:09 PM PDT 24
Peak memory 183152 kb
Host smart-4b915faa-9b93-4a77-9eea-ec4fa1aa9698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651867735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2651867735
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2779671223
Short name T435
Test name
Test status
Simulation time 4868611580 ps
CPU time 7.43 seconds
Started Jun 29 04:53:56 PM PDT 24
Finished Jun 29 04:54:04 PM PDT 24
Peak memory 183132 kb
Host smart-c992691e-37f8-431b-9a50-427c228f481d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779671223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2779671223
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1567372532
Short name T380
Test name
Test status
Simulation time 97977327529 ps
CPU time 90 seconds
Started Jun 29 04:53:57 PM PDT 24
Finished Jun 29 04:55:28 PM PDT 24
Peak memory 183132 kb
Host smart-0e9e15c0-4b46-4e89-9f0c-a344a08fb9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567372532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1567372532
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3840267693
Short name T433
Test name
Test status
Simulation time 70112396799 ps
CPU time 46.2 seconds
Started Jun 29 04:53:58 PM PDT 24
Finished Jun 29 04:54:45 PM PDT 24
Peak memory 183152 kb
Host smart-84b2450c-5d8e-48c6-8121-bfd86c3cdaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840267693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3840267693
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2390889462
Short name T128
Test name
Test status
Simulation time 150622553796 ps
CPU time 119.24 seconds
Started Jun 29 04:53:57 PM PDT 24
Finished Jun 29 04:55:58 PM PDT 24
Peak memory 183128 kb
Host smart-ffb36566-4220-41d5-9118-358ced2d0c5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390889462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2390889462
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3754461973
Short name T374
Test name
Test status
Simulation time 175525548314 ps
CPU time 241.59 seconds
Started Jun 29 04:53:57 PM PDT 24
Finished Jun 29 04:58:00 PM PDT 24
Peak memory 183156 kb
Host smart-ccade0b8-6a1a-4be5-bfdf-469466708b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754461973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3754461973
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.4092910537
Short name T108
Test name
Test status
Simulation time 62169398913 ps
CPU time 110.34 seconds
Started Jun 29 04:53:57 PM PDT 24
Finished Jun 29 04:55:49 PM PDT 24
Peak memory 191296 kb
Host smart-0b5aa005-59a0-4edb-89d1-1bd9aaa3209b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092910537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4092910537
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2366964544
Short name T113
Test name
Test status
Simulation time 585446768763 ps
CPU time 1430.37 seconds
Started Jun 29 04:54:00 PM PDT 24
Finished Jun 29 05:17:51 PM PDT 24
Peak memory 195084 kb
Host smart-b72fe9c2-24a9-4c28-9a0e-0f3b844a5d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366964544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2366964544
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2210411423
Short name T147
Test name
Test status
Simulation time 224823384279 ps
CPU time 155.84 seconds
Started Jun 29 04:54:06 PM PDT 24
Finished Jun 29 04:56:42 PM PDT 24
Peak memory 183056 kb
Host smart-f07fa11a-851c-42df-b280-1953a4e7fb40
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210411423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2210411423
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3068690860
Short name T20
Test name
Test status
Simulation time 423135901437 ps
CPU time 264.48 seconds
Started Jun 29 04:53:54 PM PDT 24
Finished Jun 29 04:58:19 PM PDT 24
Peak memory 183092 kb
Host smart-b1b49bf1-add5-4c04-ae9f-a92f3267abcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068690860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3068690860
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1407764607
Short name T143
Test name
Test status
Simulation time 1720991124205 ps
CPU time 617.2 seconds
Started Jun 29 04:53:58 PM PDT 24
Finished Jun 29 05:04:16 PM PDT 24
Peak memory 191312 kb
Host smart-9ef22e07-d9cc-4560-9696-3759ebee1186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407764607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1407764607
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.4042633294
Short name T124
Test name
Test status
Simulation time 95228347579 ps
CPU time 41.49 seconds
Started Jun 29 04:54:06 PM PDT 24
Finished Jun 29 04:54:48 PM PDT 24
Peak memory 191256 kb
Host smart-b60656a8-4e8d-4b4e-86e1-13cc212cffcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042633294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.4042633294
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2205269132
Short name T448
Test name
Test status
Simulation time 217645534450 ps
CPU time 332.27 seconds
Started Jun 29 04:54:13 PM PDT 24
Finished Jun 29 04:59:46 PM PDT 24
Peak memory 182908 kb
Host smart-17601bf7-5e9c-4a04-a7a4-64199ac996f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205269132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2205269132
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1715394104
Short name T418
Test name
Test status
Simulation time 132021105747 ps
CPU time 48.21 seconds
Started Jun 29 04:54:04 PM PDT 24
Finished Jun 29 04:54:53 PM PDT 24
Peak memory 183144 kb
Host smart-dcd45bd7-5c6c-411c-84bd-ca50be91c42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715394104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1715394104
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.4127598515
Short name T409
Test name
Test status
Simulation time 30084383618 ps
CPU time 238.14 seconds
Started Jun 29 04:54:12 PM PDT 24
Finished Jun 29 04:58:11 PM PDT 24
Peak memory 194056 kb
Host smart-deee709e-ff31-4a7a-b885-d8d19eae1d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127598515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.4127598515
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3067373301
Short name T52
Test name
Test status
Simulation time 485265648964 ps
CPU time 488.56 seconds
Started Jun 29 04:54:07 PM PDT 24
Finished Jun 29 05:02:16 PM PDT 24
Peak memory 195376 kb
Host smart-65072778-40c6-4ea1-b458-60ce4c252775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067373301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3067373301
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1705742930
Short name T8
Test name
Test status
Simulation time 151720863496 ps
CPU time 191.98 seconds
Started Jun 29 04:54:05 PM PDT 24
Finished Jun 29 04:57:18 PM PDT 24
Peak memory 183148 kb
Host smart-137e18ab-0b5f-47cd-bc07-7522d4bbca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705742930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1705742930
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1450893285
Short name T209
Test name
Test status
Simulation time 50378455014 ps
CPU time 83.54 seconds
Started Jun 29 04:54:02 PM PDT 24
Finished Jun 29 04:55:26 PM PDT 24
Peak memory 191336 kb
Host smart-c41a5a1c-c6a0-487c-be27-4d5dc33e26c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450893285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1450893285
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3557933859
Short name T357
Test name
Test status
Simulation time 76841781 ps
CPU time 0.64 seconds
Started Jun 29 04:54:04 PM PDT 24
Finished Jun 29 04:54:06 PM PDT 24
Peak memory 183004 kb
Host smart-50fdf055-c0e7-49bd-8ff6-ad8e0591b503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557933859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3557933859
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3660337799
Short name T423
Test name
Test status
Simulation time 231703202195 ps
CPU time 371.55 seconds
Started Jun 29 04:54:03 PM PDT 24
Finished Jun 29 05:00:15 PM PDT 24
Peak memory 195512 kb
Host smart-a74e1066-9d45-401b-8711-0c9729d54144
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660337799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3660337799
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1471580006
Short name T210
Test name
Test status
Simulation time 256175891288 ps
CPU time 211.97 seconds
Started Jun 29 04:54:12 PM PDT 24
Finished Jun 29 04:57:44 PM PDT 24
Peak memory 182908 kb
Host smart-e62341f7-33e2-43b3-9b74-0fac2fb4aca4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471580006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1471580006
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2785847262
Short name T358
Test name
Test status
Simulation time 105782314737 ps
CPU time 163.48 seconds
Started Jun 29 04:54:03 PM PDT 24
Finished Jun 29 04:56:47 PM PDT 24
Peak memory 183132 kb
Host smart-ced9c1d3-dfb1-4d22-b6ff-4de74a4350f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785847262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2785847262
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1396853676
Short name T345
Test name
Test status
Simulation time 81809192371 ps
CPU time 202.57 seconds
Started Jun 29 04:54:07 PM PDT 24
Finished Jun 29 04:57:30 PM PDT 24
Peak memory 183132 kb
Host smart-c97eb40c-f0e1-4eb7-bd18-c686e502283e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396853676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1396853676
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1345178029
Short name T429
Test name
Test status
Simulation time 573542073679 ps
CPU time 70.87 seconds
Started Jun 29 04:54:06 PM PDT 24
Finished Jun 29 04:55:18 PM PDT 24
Peak memory 191248 kb
Host smart-a36f222b-ef51-420d-bc10-e1146bed0dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345178029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1345178029
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1638429469
Short name T65
Test name
Test status
Simulation time 845470013682 ps
CPU time 456.13 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 05:01:05 PM PDT 24
Peak memory 183136 kb
Host smart-797680d9-eca0-4e33-82dd-7412d4e6f56e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638429469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1638429469
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1081632584
Short name T367
Test name
Test status
Simulation time 18106884750 ps
CPU time 29.01 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:53:58 PM PDT 24
Peak memory 183156 kb
Host smart-8a2f8a64-bbc3-4a30-9e45-711c4a6fcc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081632584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1081632584
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2945330282
Short name T260
Test name
Test status
Simulation time 246270317776 ps
CPU time 131.12 seconds
Started Jun 29 04:53:29 PM PDT 24
Finished Jun 29 04:55:41 PM PDT 24
Peak memory 183148 kb
Host smart-b6dc3ba3-77a2-42ac-95c4-8a7b5b30db6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945330282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2945330282
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2066125682
Short name T13
Test name
Test status
Simulation time 38407741 ps
CPU time 0.75 seconds
Started Jun 29 04:53:29 PM PDT 24
Finished Jun 29 04:53:31 PM PDT 24
Peak memory 213360 kb
Host smart-110c64c9-7393-4456-b0b5-50a2992bfe9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066125682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2066125682
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3981491020
Short name T38
Test name
Test status
Simulation time 57406734630 ps
CPU time 245.87 seconds
Started Jun 29 04:53:29 PM PDT 24
Finished Jun 29 04:57:36 PM PDT 24
Peak memory 206096 kb
Host smart-9cc73f95-bee4-47f8-8106-08c2bb6dd4fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981491020 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3981491020
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1583162545
Short name T119
Test name
Test status
Simulation time 1602744641795 ps
CPU time 827.81 seconds
Started Jun 29 04:54:03 PM PDT 24
Finished Jun 29 05:07:51 PM PDT 24
Peak memory 183080 kb
Host smart-7e27c398-6b40-4e44-8208-a1c3bf9d4a1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583162545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1583162545
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1802910031
Short name T442
Test name
Test status
Simulation time 116352630366 ps
CPU time 87.61 seconds
Started Jun 29 04:54:08 PM PDT 24
Finished Jun 29 04:55:36 PM PDT 24
Peak memory 183152 kb
Host smart-a1499a8c-32b9-4c1e-8c31-6219d7cb7c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802910031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1802910031
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.969560908
Short name T270
Test name
Test status
Simulation time 355778435552 ps
CPU time 481.42 seconds
Started Jun 29 04:54:13 PM PDT 24
Finished Jun 29 05:02:14 PM PDT 24
Peak memory 191124 kb
Host smart-629ea3d0-84ed-4ec5-bead-f9935d59d03f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969560908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.969560908
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1565968635
Short name T201
Test name
Test status
Simulation time 217019592642 ps
CPU time 160.24 seconds
Started Jun 29 04:54:04 PM PDT 24
Finished Jun 29 04:56:45 PM PDT 24
Peak memory 191328 kb
Host smart-92e0d426-0cbc-4411-b897-f5997e5923c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565968635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1565968635
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1808151604
Short name T187
Test name
Test status
Simulation time 853721390 ps
CPU time 2.03 seconds
Started Jun 29 04:54:03 PM PDT 24
Finished Jun 29 04:54:05 PM PDT 24
Peak memory 182976 kb
Host smart-334b4bdc-b015-4b50-8e33-fede69bada2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808151604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1808151604
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3683457768
Short name T7
Test name
Test status
Simulation time 568796025311 ps
CPU time 230.29 seconds
Started Jun 29 04:54:07 PM PDT 24
Finished Jun 29 04:57:57 PM PDT 24
Peak memory 183156 kb
Host smart-0e4e10ff-cd08-4930-b8dc-48886a0ea56b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683457768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3683457768
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4283661561
Short name T121
Test name
Test status
Simulation time 905527042930 ps
CPU time 215.48 seconds
Started Jun 29 04:54:05 PM PDT 24
Finished Jun 29 04:57:41 PM PDT 24
Peak memory 191340 kb
Host smart-8ba6550d-2ba6-4ed7-86e0-458c161bad11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283661561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4283661561
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.654898694
Short name T329
Test name
Test status
Simulation time 42077995060 ps
CPU time 33.62 seconds
Started Jun 29 04:54:08 PM PDT 24
Finished Jun 29 04:54:42 PM PDT 24
Peak memory 183132 kb
Host smart-bd0643d8-bbf5-47f4-8b40-7b44beaaef39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654898694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.654898694
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.741331977
Short name T171
Test name
Test status
Simulation time 2371985002797 ps
CPU time 782.19 seconds
Started Jun 29 04:54:04 PM PDT 24
Finished Jun 29 05:07:07 PM PDT 24
Peak memory 183136 kb
Host smart-37891370-89c6-4786-bfee-b4af75bd7d00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741331977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.741331977
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1058136179
Short name T379
Test name
Test status
Simulation time 125897214587 ps
CPU time 176.56 seconds
Started Jun 29 04:54:12 PM PDT 24
Finished Jun 29 04:57:09 PM PDT 24
Peak memory 182936 kb
Host smart-d0a16860-8969-44e8-8ede-69145c0d2a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058136179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1058136179
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.341964275
Short name T63
Test name
Test status
Simulation time 54495976134 ps
CPU time 79.75 seconds
Started Jun 29 04:54:04 PM PDT 24
Finished Jun 29 04:55:24 PM PDT 24
Peak memory 191344 kb
Host smart-1c9dc248-a31f-41b8-8176-e62089ddf87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341964275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.341964275
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.618402704
Short name T265
Test name
Test status
Simulation time 2500011057868 ps
CPU time 3234.54 seconds
Started Jun 29 04:54:04 PM PDT 24
Finished Jun 29 05:48:00 PM PDT 24
Peak memory 191328 kb
Host smart-41e602d9-017c-448c-88b2-63c98e940c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618402704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
618402704
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2719489747
Short name T95
Test name
Test status
Simulation time 396835538498 ps
CPU time 612.77 seconds
Started Jun 29 04:54:03 PM PDT 24
Finished Jun 29 05:04:16 PM PDT 24
Peak memory 183028 kb
Host smart-e7eaf01d-00e9-4fb3-b3e0-6137b0f3333a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719489747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2719489747
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3236549811
Short name T368
Test name
Test status
Simulation time 43594584504 ps
CPU time 57.98 seconds
Started Jun 29 04:54:03 PM PDT 24
Finished Jun 29 04:55:02 PM PDT 24
Peak memory 183156 kb
Host smart-e838fb50-48e5-414a-9645-15aa7c072673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236549811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3236549811
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2647957256
Short name T163
Test name
Test status
Simulation time 1592335001731 ps
CPU time 855.5 seconds
Started Jun 29 04:54:07 PM PDT 24
Finished Jun 29 05:08:23 PM PDT 24
Peak memory 191340 kb
Host smart-603e41d6-4d7a-436c-be6d-7967483c7b11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647957256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2647957256
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1824518927
Short name T369
Test name
Test status
Simulation time 62471158 ps
CPU time 0.58 seconds
Started Jun 29 04:54:07 PM PDT 24
Finished Jun 29 04:54:08 PM PDT 24
Peak memory 183000 kb
Host smart-5fc362b6-7eee-4565-9299-0b493c358d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824518927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1824518927
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.266975257
Short name T51
Test name
Test status
Simulation time 751578211471 ps
CPU time 426.99 seconds
Started Jun 29 04:54:05 PM PDT 24
Finished Jun 29 05:01:13 PM PDT 24
Peak memory 191336 kb
Host smart-0d15571c-ca6d-4dff-b353-029c4d20becb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266975257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
266975257
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.596843113
Short name T269
Test name
Test status
Simulation time 29907877241 ps
CPU time 46.82 seconds
Started Jun 29 04:54:04 PM PDT 24
Finished Jun 29 04:54:51 PM PDT 24
Peak memory 183136 kb
Host smart-1c122ab9-38cf-4a96-a79c-2e386c33ee3f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596843113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.596843113
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.958658064
Short name T383
Test name
Test status
Simulation time 237064994972 ps
CPU time 101.09 seconds
Started Jun 29 04:54:05 PM PDT 24
Finished Jun 29 04:55:47 PM PDT 24
Peak memory 183088 kb
Host smart-de9cc0f7-0fea-4671-a274-dc6dfae018f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958658064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.958658064
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.4009037159
Short name T96
Test name
Test status
Simulation time 654546088287 ps
CPU time 345.39 seconds
Started Jun 29 04:54:06 PM PDT 24
Finished Jun 29 04:59:52 PM PDT 24
Peak memory 191244 kb
Host smart-19f16840-0217-4012-b1bf-8112d8c59e8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009037159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.4009037159
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2869534259
Short name T59
Test name
Test status
Simulation time 84635888801 ps
CPU time 46.94 seconds
Started Jun 29 04:54:05 PM PDT 24
Finished Jun 29 04:54:52 PM PDT 24
Peak memory 183152 kb
Host smart-1dc38b05-a1fe-4916-a0ac-3123efdc6712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869534259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2869534259
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3450111125
Short name T56
Test name
Test status
Simulation time 445855402347 ps
CPU time 670.64 seconds
Started Jun 29 04:54:11 PM PDT 24
Finished Jun 29 05:05:22 PM PDT 24
Peak memory 195160 kb
Host smart-45cc89b3-3324-41e8-bc87-fb7e05b9c03d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450111125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3450111125
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1886911374
Short name T272
Test name
Test status
Simulation time 28096215719 ps
CPU time 25.79 seconds
Started Jun 29 04:54:18 PM PDT 24
Finished Jun 29 04:54:45 PM PDT 24
Peak memory 183128 kb
Host smart-fd919791-6e5a-4703-9693-d6df82580877
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886911374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1886911374
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3246022613
Short name T370
Test name
Test status
Simulation time 375306610143 ps
CPU time 130.18 seconds
Started Jun 29 04:54:11 PM PDT 24
Finished Jun 29 04:56:21 PM PDT 24
Peak memory 183100 kb
Host smart-9699feec-a17c-433c-91f1-17acdb1c1dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246022613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3246022613
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3879328823
Short name T134
Test name
Test status
Simulation time 120078034445 ps
CPU time 302.06 seconds
Started Jun 29 04:54:16 PM PDT 24
Finished Jun 29 04:59:19 PM PDT 24
Peak memory 191340 kb
Host smart-07aa1e10-14d6-4cdf-ab43-f91436f77751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879328823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3879328823
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.962381051
Short name T385
Test name
Test status
Simulation time 50387722756 ps
CPU time 20.4 seconds
Started Jun 29 04:54:21 PM PDT 24
Finished Jun 29 04:54:41 PM PDT 24
Peak memory 194836 kb
Host smart-ac2ccd27-4c2c-4562-9de6-e070f4aec411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962381051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.962381051
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3564792811
Short name T55
Test name
Test status
Simulation time 43137164206 ps
CPU time 69.42 seconds
Started Jun 29 04:54:16 PM PDT 24
Finished Jun 29 04:55:26 PM PDT 24
Peak memory 183136 kb
Host smart-5e231a17-3161-41a0-a70d-7a7e7d1b52e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564792811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3564792811
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.659777267
Short name T267
Test name
Test status
Simulation time 260821536313 ps
CPU time 388.02 seconds
Started Jun 29 04:54:12 PM PDT 24
Finished Jun 29 05:00:40 PM PDT 24
Peak memory 183136 kb
Host smart-83bc4126-d885-4332-8749-6e1a8160d7db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659777267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.659777267
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.662052701
Short name T376
Test name
Test status
Simulation time 66057783645 ps
CPU time 101.78 seconds
Started Jun 29 04:54:19 PM PDT 24
Finished Jun 29 04:56:01 PM PDT 24
Peak memory 183156 kb
Host smart-34eff70b-86c5-40ba-a97d-e7b92546c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662052701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.662052701
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.134084658
Short name T415
Test name
Test status
Simulation time 271781877381 ps
CPU time 1889.97 seconds
Started Jun 29 04:54:13 PM PDT 24
Finished Jun 29 05:25:43 PM PDT 24
Peak memory 191332 kb
Host smart-f99893fe-00ea-4efc-960f-5641ba12e00c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134084658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.134084658
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.4064278882
Short name T350
Test name
Test status
Simulation time 201340266003 ps
CPU time 91.47 seconds
Started Jun 29 04:54:10 PM PDT 24
Finished Jun 29 04:55:42 PM PDT 24
Peak memory 195656 kb
Host smart-7177d5f9-4f42-4338-a8e8-08993e52ce3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064278882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4064278882
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3946221540
Short name T9
Test name
Test status
Simulation time 161062603335 ps
CPU time 114.24 seconds
Started Jun 29 04:54:19 PM PDT 24
Finished Jun 29 04:56:14 PM PDT 24
Peak memory 183156 kb
Host smart-1257d49b-a3bc-4fe1-a218-c73529cd3cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946221540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3946221540
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2728904319
Short name T276
Test name
Test status
Simulation time 655768019464 ps
CPU time 521.52 seconds
Started Jun 29 04:54:19 PM PDT 24
Finished Jun 29 05:03:01 PM PDT 24
Peak memory 193628 kb
Host smart-e64b356d-4410-480e-bbf8-c08a79a63ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728904319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2728904319
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2598002823
Short name T295
Test name
Test status
Simulation time 65536774035 ps
CPU time 52.33 seconds
Started Jun 29 04:54:18 PM PDT 24
Finished Jun 29 04:55:10 PM PDT 24
Peak memory 183132 kb
Host smart-d800fd83-b6e9-483b-a999-170120286ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598002823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2598002823
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.54157435
Short name T371
Test name
Test status
Simulation time 32559290 ps
CPU time 0.52 seconds
Started Jun 29 04:54:18 PM PDT 24
Finished Jun 29 04:54:19 PM PDT 24
Peak memory 182936 kb
Host smart-7c2234cd-073f-4108-ad1c-fcc12e821b55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54157435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.54157435
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1565500965
Short name T174
Test name
Test status
Simulation time 69688663415 ps
CPU time 25.74 seconds
Started Jun 29 04:54:10 PM PDT 24
Finished Jun 29 04:54:36 PM PDT 24
Peak memory 182932 kb
Host smart-6c733b86-3fa6-4c5d-b4ca-283259a2f939
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565500965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1565500965
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2739560658
Short name T382
Test name
Test status
Simulation time 138902714706 ps
CPU time 196.31 seconds
Started Jun 29 04:54:14 PM PDT 24
Finished Jun 29 04:57:31 PM PDT 24
Peak memory 183156 kb
Host smart-239ccd15-7624-49df-9de7-1daf4b7dd464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739560658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2739560658
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.385699166
Short name T337
Test name
Test status
Simulation time 362710584260 ps
CPU time 453.92 seconds
Started Jun 29 04:54:11 PM PDT 24
Finished Jun 29 05:01:45 PM PDT 24
Peak memory 191300 kb
Host smart-d6301b94-1dff-44fd-bb1c-24b1ee24415b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385699166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.385699166
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3763894350
Short name T123
Test name
Test status
Simulation time 65109121794 ps
CPU time 98.26 seconds
Started Jun 29 04:54:12 PM PDT 24
Finished Jun 29 04:55:50 PM PDT 24
Peak memory 191360 kb
Host smart-0f4ad9df-1ca6-483c-9437-c5bb9024d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763894350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3763894350
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3869578945
Short name T186
Test name
Test status
Simulation time 548001422120 ps
CPU time 262.7 seconds
Started Jun 29 04:54:20 PM PDT 24
Finished Jun 29 04:58:43 PM PDT 24
Peak memory 183120 kb
Host smart-38812522-c3bb-4c04-9534-52f83a4c6f1c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869578945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3869578945
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3292680306
Short name T408
Test name
Test status
Simulation time 583389050617 ps
CPU time 217.89 seconds
Started Jun 29 04:54:20 PM PDT 24
Finished Jun 29 04:57:59 PM PDT 24
Peak memory 183124 kb
Host smart-6441a557-dc92-4fa6-87e6-731865b5a408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292680306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3292680306
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3390232346
Short name T320
Test name
Test status
Simulation time 122007884206 ps
CPU time 95.94 seconds
Started Jun 29 04:54:20 PM PDT 24
Finished Jun 29 04:55:56 PM PDT 24
Peak memory 183124 kb
Host smart-0cdc047e-db03-4baa-9f2e-70b5feb3d093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390232346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3390232346
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3470880640
Short name T387
Test name
Test status
Simulation time 2162452741 ps
CPU time 1.74 seconds
Started Jun 29 04:54:19 PM PDT 24
Finished Jun 29 04:54:21 PM PDT 24
Peak memory 194336 kb
Host smart-6ed3d695-6249-4eb8-9343-15c78314ebf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470880640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3470880640
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2956430224
Short name T431
Test name
Test status
Simulation time 82239295 ps
CPU time 0.56 seconds
Started Jun 29 04:54:20 PM PDT 24
Finished Jun 29 04:54:21 PM PDT 24
Peak memory 182952 kb
Host smart-a26576c2-efe8-499a-820a-df1ef107518c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956430224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2956430224
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3096996088
Short name T211
Test name
Test status
Simulation time 254581127479 ps
CPU time 134.42 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:55:43 PM PDT 24
Peak memory 183132 kb
Host smart-1bbb1f7e-174a-4c9f-8620-e4e2d7aa30b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096996088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3096996088
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.633850476
Short name T361
Test name
Test status
Simulation time 111265255941 ps
CPU time 172.34 seconds
Started Jun 29 04:53:34 PM PDT 24
Finished Jun 29 04:56:27 PM PDT 24
Peak memory 182860 kb
Host smart-a51ab824-f42c-425f-8b34-7c83530ac423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633850476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.633850476
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3739954286
Short name T352
Test name
Test status
Simulation time 217254111125 ps
CPU time 104.44 seconds
Started Jun 29 04:53:29 PM PDT 24
Finished Jun 29 04:55:15 PM PDT 24
Peak memory 191332 kb
Host smart-e8e78433-6569-4590-b2ea-4907d06b6d77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739954286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3739954286
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2234506348
Short name T373
Test name
Test status
Simulation time 100070595646 ps
CPU time 407.04 seconds
Started Jun 29 04:53:30 PM PDT 24
Finished Jun 29 05:00:18 PM PDT 24
Peak memory 183148 kb
Host smart-685cc162-8eb8-42d4-bfc7-fa16db8ca37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234506348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2234506348
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3695498218
Short name T179
Test name
Test status
Simulation time 659974854095 ps
CPU time 2290.63 seconds
Started Jun 29 04:53:34 PM PDT 24
Finished Jun 29 05:31:45 PM PDT 24
Peak memory 195616 kb
Host smart-39d2264a-c5a9-41a5-8e68-277f0f9263d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695498218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3695498218
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.1218194341
Short name T157
Test name
Test status
Simulation time 75528542070 ps
CPU time 139.86 seconds
Started Jun 29 04:54:17 PM PDT 24
Finished Jun 29 04:56:37 PM PDT 24
Peak memory 191308 kb
Host smart-55640b46-17fc-4e7d-8693-6c6057aee015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218194341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1218194341
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2766509101
Short name T289
Test name
Test status
Simulation time 74932280734 ps
CPU time 167.54 seconds
Started Jun 29 04:54:17 PM PDT 24
Finished Jun 29 04:57:05 PM PDT 24
Peak memory 191200 kb
Host smart-11362fe0-49e6-4228-99c1-ed66d7a9e9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766509101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2766509101
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2187421465
Short name T220
Test name
Test status
Simulation time 614484486154 ps
CPU time 321.92 seconds
Started Jun 29 04:54:18 PM PDT 24
Finished Jun 29 04:59:41 PM PDT 24
Peak memory 191308 kb
Host smart-3e360bc2-2160-4e92-a6de-805b90346073
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187421465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2187421465
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2212030586
Short name T262
Test name
Test status
Simulation time 69020334247 ps
CPU time 122.58 seconds
Started Jun 29 04:54:19 PM PDT 24
Finished Jun 29 04:56:22 PM PDT 24
Peak memory 191340 kb
Host smart-0c51d358-ca0b-4017-aa73-2aa16b7b3250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212030586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2212030586
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1647781619
Short name T247
Test name
Test status
Simulation time 451250584603 ps
CPU time 515.82 seconds
Started Jun 29 04:54:19 PM PDT 24
Finished Jun 29 05:02:55 PM PDT 24
Peak memory 191340 kb
Host smart-01bec5ec-2bde-4eeb-8a6b-9975c1e1fcd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647781619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1647781619
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.4266949916
Short name T293
Test name
Test status
Simulation time 338881195285 ps
CPU time 589.76 seconds
Started Jun 29 04:54:18 PM PDT 24
Finished Jun 29 05:04:08 PM PDT 24
Peak memory 191340 kb
Host smart-e7712fd5-c184-49e1-8503-4a6470cd7eda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266949916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.4266949916
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1826785060
Short name T181
Test name
Test status
Simulation time 753143896864 ps
CPU time 513.92 seconds
Started Jun 29 04:54:18 PM PDT 24
Finished Jun 29 05:02:52 PM PDT 24
Peak memory 191332 kb
Host smart-45e8057e-2363-4270-a6d1-79329379c17b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826785060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1826785060
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3597757666
Short name T106
Test name
Test status
Simulation time 2088253381322 ps
CPU time 2479.09 seconds
Started Jun 29 04:54:25 PM PDT 24
Finished Jun 29 05:35:44 PM PDT 24
Peak memory 193384 kb
Host smart-dbd67e4b-d155-47f0-8a5a-03d64e4be887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597757666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3597757666
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.4020124456
Short name T60
Test name
Test status
Simulation time 81651033840 ps
CPU time 438.04 seconds
Started Jun 29 04:54:24 PM PDT 24
Finished Jun 29 05:01:42 PM PDT 24
Peak memory 191340 kb
Host smart-b4748248-a58f-4d4e-91e7-ce7b597608e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020124456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4020124456
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3743179096
Short name T298
Test name
Test status
Simulation time 807025890129 ps
CPU time 618.56 seconds
Started Jun 29 04:53:30 PM PDT 24
Finished Jun 29 05:03:50 PM PDT 24
Peak memory 183132 kb
Host smart-510d312c-86e0-4421-8300-f8dc2a2e38c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743179096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3743179096
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.345093571
Short name T403
Test name
Test status
Simulation time 221681041321 ps
CPU time 258.67 seconds
Started Jun 29 04:53:33 PM PDT 24
Finished Jun 29 04:57:53 PM PDT 24
Peak memory 183120 kb
Host smart-4d278e0a-777b-4a39-a8f8-1690c2ce41e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345093571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.345093571
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3524398917
Short name T10
Test name
Test status
Simulation time 127325376167 ps
CPU time 262.41 seconds
Started Jun 29 04:53:27 PM PDT 24
Finished Jun 29 04:57:50 PM PDT 24
Peak memory 191308 kb
Host smart-20afc388-78c7-499a-ac45-a1a8e39f22f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524398917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3524398917
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.882462302
Short name T330
Test name
Test status
Simulation time 38782390718 ps
CPU time 39.31 seconds
Started Jun 29 04:53:32 PM PDT 24
Finished Jun 29 04:54:12 PM PDT 24
Peak memory 194848 kb
Host smart-2b045e63-21d0-4f54-a84b-e940b2c99f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882462302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.882462302
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3022385449
Short name T219
Test name
Test status
Simulation time 273969360111 ps
CPU time 112.7 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:55:22 PM PDT 24
Peak memory 191332 kb
Host smart-249cffb2-293c-4d40-a1dd-db075dde9f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022385449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3022385449
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.2105550751
Short name T428
Test name
Test status
Simulation time 64685426689 ps
CPU time 53.64 seconds
Started Jun 29 04:54:26 PM PDT 24
Finished Jun 29 04:55:20 PM PDT 24
Peak memory 183132 kb
Host smart-da4661ce-7811-424b-a9ad-7065825664d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105550751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2105550751
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2649459057
Short name T422
Test name
Test status
Simulation time 207031291871 ps
CPU time 149.05 seconds
Started Jun 29 04:54:26 PM PDT 24
Finished Jun 29 04:56:55 PM PDT 24
Peak memory 183140 kb
Host smart-f36ad33f-1ba7-42b3-a939-2d19b45acb6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649459057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2649459057
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3797303041
Short name T282
Test name
Test status
Simulation time 256404686824 ps
CPU time 1248.72 seconds
Started Jun 29 04:54:26 PM PDT 24
Finished Jun 29 05:15:15 PM PDT 24
Peak memory 191332 kb
Host smart-672084a4-2bae-4cb1-b7bb-8624bf288426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797303041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3797303041
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2744749980
Short name T192
Test name
Test status
Simulation time 175061241621 ps
CPU time 295.8 seconds
Started Jun 29 04:54:25 PM PDT 24
Finished Jun 29 04:59:21 PM PDT 24
Peak memory 191340 kb
Host smart-47e66a25-aa88-44c3-b7a5-3b880c25f00c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744749980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2744749980
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3844189912
Short name T203
Test name
Test status
Simulation time 1790935117949 ps
CPU time 641.84 seconds
Started Jun 29 04:54:24 PM PDT 24
Finished Jun 29 05:05:06 PM PDT 24
Peak memory 191332 kb
Host smart-545f0e36-acfa-476b-85a3-d9921511f69f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844189912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3844189912
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3225354725
Short name T110
Test name
Test status
Simulation time 168718905374 ps
CPU time 83.32 seconds
Started Jun 29 04:54:35 PM PDT 24
Finished Jun 29 04:55:58 PM PDT 24
Peak memory 183132 kb
Host smart-3cc6b583-8d1f-4a11-a11c-833daf425e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225354725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3225354725
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1478422106
Short name T439
Test name
Test status
Simulation time 26257431177 ps
CPU time 53.94 seconds
Started Jun 29 04:54:34 PM PDT 24
Finished Jun 29 04:55:28 PM PDT 24
Peak memory 183132 kb
Host smart-6ae71a3a-b24e-4ae8-af96-26fe2bbe80f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478422106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1478422106
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.768261863
Short name T305
Test name
Test status
Simulation time 388485407971 ps
CPU time 222.22 seconds
Started Jun 29 04:54:34 PM PDT 24
Finished Jun 29 04:58:16 PM PDT 24
Peak memory 191336 kb
Host smart-7269fa43-85e1-476f-90bd-ec5772d6872f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768261863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.768261863
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2232065211
Short name T391
Test name
Test status
Simulation time 90010978329 ps
CPU time 111.59 seconds
Started Jun 29 04:53:32 PM PDT 24
Finished Jun 29 04:55:24 PM PDT 24
Peak memory 183156 kb
Host smart-84d84828-afeb-4b43-97b1-aef87629e398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232065211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2232065211
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.777326154
Short name T245
Test name
Test status
Simulation time 1099400523101 ps
CPU time 347.73 seconds
Started Jun 29 04:53:28 PM PDT 24
Finished Jun 29 04:59:17 PM PDT 24
Peak memory 193556 kb
Host smart-738d54a1-14bf-48c5-9a94-0409479e92f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777326154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.777326154
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.878211733
Short name T301
Test name
Test status
Simulation time 43608012217 ps
CPU time 72.47 seconds
Started Jun 29 04:53:33 PM PDT 24
Finished Jun 29 04:54:46 PM PDT 24
Peak memory 182980 kb
Host smart-ae51b32e-2df3-416e-9131-811cd46968e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878211733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.878211733
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1520368879
Short name T193
Test name
Test status
Simulation time 239983210114 ps
CPU time 367.51 seconds
Started Jun 29 04:53:34 PM PDT 24
Finished Jun 29 04:59:42 PM PDT 24
Peak memory 191332 kb
Host smart-4a687fa0-a80e-46ed-a6fb-030e798711ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520368879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1520368879
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1191117864
Short name T11
Test name
Test status
Simulation time 26272517774 ps
CPU time 294.46 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 04:58:31 PM PDT 24
Peak memory 206048 kb
Host smart-bcc08cd9-5657-40d7-931b-9903d298e212
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191117864 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1191117864
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.rv_timer_random.2879735922
Short name T287
Test name
Test status
Simulation time 82518396802 ps
CPU time 135.49 seconds
Started Jun 29 04:54:33 PM PDT 24
Finished Jun 29 04:56:49 PM PDT 24
Peak memory 191332 kb
Host smart-398407df-2a87-4d66-b585-f9a56f0642e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879735922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2879735922
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2977274295
Short name T155
Test name
Test status
Simulation time 165182933095 ps
CPU time 394.79 seconds
Started Jun 29 04:54:38 PM PDT 24
Finished Jun 29 05:01:13 PM PDT 24
Peak memory 192328 kb
Host smart-d1aa3987-1541-471b-a8b7-74ad239c1cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977274295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2977274295
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1388527410
Short name T207
Test name
Test status
Simulation time 169032837280 ps
CPU time 2121.51 seconds
Started Jun 29 04:54:36 PM PDT 24
Finished Jun 29 05:29:58 PM PDT 24
Peak memory 191340 kb
Host smart-e0062f09-572b-489e-aef8-db12a7529e27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388527410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1388527410
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1220967211
Short name T331
Test name
Test status
Simulation time 1979743063889 ps
CPU time 2495.02 seconds
Started Jun 29 04:54:34 PM PDT 24
Finished Jun 29 05:36:10 PM PDT 24
Peak memory 191308 kb
Host smart-51ba66d7-5c86-43f8-944e-498a87e6b7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220967211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1220967211
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2878844523
Short name T127
Test name
Test status
Simulation time 195260235132 ps
CPU time 102.32 seconds
Started Jun 29 04:54:43 PM PDT 24
Finished Jun 29 04:56:25 PM PDT 24
Peak memory 183140 kb
Host smart-9fb9e437-07a4-4817-ac7c-042c7d6c63ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878844523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2878844523
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1435671398
Short name T285
Test name
Test status
Simulation time 1386550519281 ps
CPU time 718.06 seconds
Started Jun 29 04:53:36 PM PDT 24
Finished Jun 29 05:05:35 PM PDT 24
Peak memory 183036 kb
Host smart-2daaa8ae-bcae-449f-926a-d60f35aeb50d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435671398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1435671398
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2683285010
Short name T359
Test name
Test status
Simulation time 390631394065 ps
CPU time 161.35 seconds
Started Jun 29 04:53:42 PM PDT 24
Finished Jun 29 04:56:23 PM PDT 24
Peak memory 183148 kb
Host smart-b3c9f68f-2489-49c5-b2f1-eeb3a7ab79ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683285010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2683285010
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2817687288
Short name T279
Test name
Test status
Simulation time 685908729829 ps
CPU time 171.16 seconds
Started Jun 29 04:53:35 PM PDT 24
Finished Jun 29 04:56:26 PM PDT 24
Peak memory 191324 kb
Host smart-5dae28f7-941a-444d-ba1e-88a1f479a0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817687288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2817687288
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.2309560355
Short name T160
Test name
Test status
Simulation time 77607093959 ps
CPU time 490.53 seconds
Started Jun 29 04:54:42 PM PDT 24
Finished Jun 29 05:02:53 PM PDT 24
Peak memory 191296 kb
Host smart-35e0635d-294c-42e7-84ce-4abdbc829c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309560355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2309560355
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.156380523
Short name T98
Test name
Test status
Simulation time 123179616617 ps
CPU time 136.06 seconds
Started Jun 29 04:54:42 PM PDT 24
Finished Jun 29 04:56:59 PM PDT 24
Peak memory 191336 kb
Host smart-3d7d9895-f1eb-497e-8b9b-7e347aa39d59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156380523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.156380523
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.754640817
Short name T233
Test name
Test status
Simulation time 297683775580 ps
CPU time 91.32 seconds
Started Jun 29 04:54:41 PM PDT 24
Finished Jun 29 04:56:13 PM PDT 24
Peak memory 191344 kb
Host smart-dbdd7276-c06b-4ab2-8cc7-d6caa32f3c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754640817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.754640817
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1092979440
Short name T232
Test name
Test status
Simulation time 587155167751 ps
CPU time 752.4 seconds
Started Jun 29 04:54:43 PM PDT 24
Finished Jun 29 05:07:15 PM PDT 24
Peak memory 191244 kb
Host smart-0209b720-6591-4205-a9b3-51ffa25e7180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092979440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1092979440
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2931232071
Short name T255
Test name
Test status
Simulation time 104082283911 ps
CPU time 167.88 seconds
Started Jun 29 04:54:42 PM PDT 24
Finished Jun 29 04:57:31 PM PDT 24
Peak memory 194968 kb
Host smart-d385236f-ef3f-459e-867e-8fa164e28d06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931232071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2931232071
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2030197961
Short name T19
Test name
Test status
Simulation time 148320208612 ps
CPU time 82.8 seconds
Started Jun 29 04:54:41 PM PDT 24
Finished Jun 29 04:56:05 PM PDT 24
Peak memory 183136 kb
Host smart-e5b4016c-22fc-4efc-8604-dcd67b8d46fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030197961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2030197961
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.792254561
Short name T142
Test name
Test status
Simulation time 276373879652 ps
CPU time 139.05 seconds
Started Jun 29 04:54:42 PM PDT 24
Finished Jun 29 04:57:02 PM PDT 24
Peak memory 191344 kb
Host smart-c25905d3-769b-41fb-9151-7dbed9c7c1a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792254561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.792254561
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2821481850
Short name T24
Test name
Test status
Simulation time 129719008645 ps
CPU time 201.17 seconds
Started Jun 29 04:53:35 PM PDT 24
Finished Jun 29 04:56:56 PM PDT 24
Peak memory 183024 kb
Host smart-6e30002c-f05c-4fd1-970c-0b7ed8b164c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821481850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2821481850
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.968359662
Short name T412
Test name
Test status
Simulation time 20693317180 ps
CPU time 12.56 seconds
Started Jun 29 04:53:43 PM PDT 24
Finished Jun 29 04:53:57 PM PDT 24
Peak memory 183124 kb
Host smart-52913685-e656-4965-a0f3-2f4e78b3a6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968359662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.968359662
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1137423934
Short name T196
Test name
Test status
Simulation time 507201159586 ps
CPU time 684.03 seconds
Started Jun 29 04:53:38 PM PDT 24
Finished Jun 29 05:05:02 PM PDT 24
Peak memory 191340 kb
Host smart-41bffcf9-0464-4ca3-9b7b-a5f50ca27474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137423934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1137423934
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3094203263
Short name T356
Test name
Test status
Simulation time 1130451073 ps
CPU time 2.27 seconds
Started Jun 29 04:53:34 PM PDT 24
Finished Jun 29 04:53:37 PM PDT 24
Peak memory 182996 kb
Host smart-375745e1-ad57-4f7e-a0c9-ba86ca07ab96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094203263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3094203263
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2615104907
Short name T445
Test name
Test status
Simulation time 68195703212 ps
CPU time 45.64 seconds
Started Jun 29 04:54:50 PM PDT 24
Finished Jun 29 04:55:36 PM PDT 24
Peak memory 191256 kb
Host smart-f4d7c4f5-6833-49ec-959b-3e07c30a8df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615104907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2615104907
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3784154059
Short name T353
Test name
Test status
Simulation time 64310388742 ps
CPU time 106.84 seconds
Started Jun 29 04:54:53 PM PDT 24
Finished Jun 29 04:56:40 PM PDT 24
Peak memory 191260 kb
Host smart-f1560a59-4acd-439a-be65-86baaad0c83d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784154059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3784154059
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.533964928
Short name T316
Test name
Test status
Simulation time 9901183525 ps
CPU time 4.22 seconds
Started Jun 29 04:54:50 PM PDT 24
Finished Jun 29 04:54:55 PM PDT 24
Peak memory 183012 kb
Host smart-a4995360-9e5f-49fd-988b-c41c4d62f88e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533964928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.533964928
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1536317827
Short name T252
Test name
Test status
Simulation time 397516626584 ps
CPU time 1631.66 seconds
Started Jun 29 04:54:52 PM PDT 24
Finished Jun 29 05:22:04 PM PDT 24
Peak memory 191328 kb
Host smart-d5d1df97-ea91-46f8-a96e-2b9540e2ef4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536317827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1536317827
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.36362626
Short name T194
Test name
Test status
Simulation time 218207869566 ps
CPU time 191.71 seconds
Started Jun 29 04:54:52 PM PDT 24
Finished Jun 29 04:58:04 PM PDT 24
Peak memory 191268 kb
Host smart-474a77e7-e509-4d86-a1cd-e8b92120860b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36362626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.36362626
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.765290342
Short name T432
Test name
Test status
Simulation time 95615921031 ps
CPU time 1070.25 seconds
Started Jun 29 04:54:52 PM PDT 24
Finished Jun 29 05:12:42 PM PDT 24
Peak memory 195044 kb
Host smart-80ecd6ed-6b72-47e7-aaf5-ea9660422d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765290342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.765290342
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3981497809
Short name T199
Test name
Test status
Simulation time 158285911722 ps
CPU time 262.52 seconds
Started Jun 29 04:54:51 PM PDT 24
Finished Jun 29 04:59:13 PM PDT 24
Peak memory 191308 kb
Host smart-d1f5add1-3ce2-4312-9c56-cbfe0ef1fd57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981497809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3981497809
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.695685432
Short name T328
Test name
Test status
Simulation time 40702502060 ps
CPU time 89.72 seconds
Started Jun 29 04:54:49 PM PDT 24
Finished Jun 29 04:56:20 PM PDT 24
Peak memory 191344 kb
Host smart-72a3e71d-6d07-4ccf-9c6c-eba0bd7b4f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695685432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.695685432
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2943993024
Short name T240
Test name
Test status
Simulation time 46571369268 ps
CPU time 86.92 seconds
Started Jun 29 04:54:50 PM PDT 24
Finished Jun 29 04:56:17 PM PDT 24
Peak memory 191340 kb
Host smart-d6e87382-3afa-4ae5-bcb3-7cd17133b5c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943993024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2943993024
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.220702165
Short name T230
Test name
Test status
Simulation time 1200221976010 ps
CPU time 835.82 seconds
Started Jun 29 04:54:49 PM PDT 24
Finished Jun 29 05:08:46 PM PDT 24
Peak memory 191316 kb
Host smart-57ebb2f2-83e6-4879-aeb7-aa45caa93b4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220702165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.220702165
Directory /workspace/99.rv_timer_random/latest
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