Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.36 98.73 100.00 100.00 100.00 99.55


Total test records in report: 586
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T73 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.973225623 Jun 30 04:51:57 PM PDT 24 Jun 30 04:51:59 PM PDT 24 12750363 ps
T507 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.488410147 Jun 30 04:51:57 PM PDT 24 Jun 30 04:51:59 PM PDT 24 29956218 ps
T508 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3543688270 Jun 30 04:51:36 PM PDT 24 Jun 30 04:51:38 PM PDT 24 185849167 ps
T509 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2302684933 Jun 30 04:51:23 PM PDT 24 Jun 30 04:51:24 PM PDT 24 12214609 ps
T510 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2129294443 Jun 30 04:52:08 PM PDT 24 Jun 30 04:52:11 PM PDT 24 83190531 ps
T511 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.40350680 Jun 30 04:52:09 PM PDT 24 Jun 30 04:52:12 PM PDT 24 34911060 ps
T512 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1882594031 Jun 30 04:52:14 PM PDT 24 Jun 30 04:52:16 PM PDT 24 29240362 ps
T513 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.997231313 Jun 30 04:51:56 PM PDT 24 Jun 30 04:51:58 PM PDT 24 77896881 ps
T514 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1026190557 Jun 30 04:51:34 PM PDT 24 Jun 30 04:51:35 PM PDT 24 14304090 ps
T515 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1696882144 Jun 30 04:51:18 PM PDT 24 Jun 30 04:51:22 PM PDT 24 562771078 ps
T78 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1263391621 Jun 30 04:51:21 PM PDT 24 Jun 30 04:51:22 PM PDT 24 25162291 ps
T516 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.879889519 Jun 30 04:51:56 PM PDT 24 Jun 30 04:51:57 PM PDT 24 25504040 ps
T517 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2910728933 Jun 30 04:51:55 PM PDT 24 Jun 30 04:51:57 PM PDT 24 153438431 ps
T518 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2584411437 Jun 30 04:52:14 PM PDT 24 Jun 30 04:52:16 PM PDT 24 12557307 ps
T519 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3055500000 Jun 30 04:52:06 PM PDT 24 Jun 30 04:52:08 PM PDT 24 19353828 ps
T520 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3796776373 Jun 30 04:51:37 PM PDT 24 Jun 30 04:51:39 PM PDT 24 588695070 ps
T521 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.957754938 Jun 30 04:51:30 PM PDT 24 Jun 30 04:51:31 PM PDT 24 60421795 ps
T522 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3542860902 Jun 30 04:52:09 PM PDT 24 Jun 30 04:52:12 PM PDT 24 100536390 ps
T523 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.395331669 Jun 30 04:52:07 PM PDT 24 Jun 30 04:52:08 PM PDT 24 14442339 ps
T524 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2902389361 Jun 30 04:51:35 PM PDT 24 Jun 30 04:51:37 PM PDT 24 80640994 ps
T525 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.237400183 Jun 30 04:51:29 PM PDT 24 Jun 30 04:51:31 PM PDT 24 51872374 ps
T526 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4283427659 Jun 30 04:51:33 PM PDT 24 Jun 30 04:51:34 PM PDT 24 14490689 ps
T527 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1594995739 Jun 30 04:51:28 PM PDT 24 Jun 30 04:51:32 PM PDT 24 773657252 ps
T528 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3031041676 Jun 30 04:51:56 PM PDT 24 Jun 30 04:51:59 PM PDT 24 774267593 ps
T529 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2915641418 Jun 30 04:52:09 PM PDT 24 Jun 30 04:52:12 PM PDT 24 14397036 ps
T530 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3896340233 Jun 30 04:52:07 PM PDT 24 Jun 30 04:52:08 PM PDT 24 29592378 ps
T531 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3170926314 Jun 30 04:51:33 PM PDT 24 Jun 30 04:51:34 PM PDT 24 17972580 ps
T532 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2191390923 Jun 30 04:51:27 PM PDT 24 Jun 30 04:51:30 PM PDT 24 338928506 ps
T533 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2146300747 Jun 30 04:51:27 PM PDT 24 Jun 30 04:51:29 PM PDT 24 18130297 ps
T534 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2860502272 Jun 30 04:51:23 PM PDT 24 Jun 30 04:51:24 PM PDT 24 33547787 ps
T535 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2220429642 Jun 30 04:52:08 PM PDT 24 Jun 30 04:52:11 PM PDT 24 48676316 ps
T536 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2209143529 Jun 30 04:52:08 PM PDT 24 Jun 30 04:52:10 PM PDT 24 79328538 ps
T537 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.744168793 Jun 30 04:51:20 PM PDT 24 Jun 30 04:51:22 PM PDT 24 824621976 ps
T538 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2218141182 Jun 30 04:51:56 PM PDT 24 Jun 30 04:51:58 PM PDT 24 15602841 ps
T74 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3786973209 Jun 30 04:51:21 PM PDT 24 Jun 30 04:51:23 PM PDT 24 25937272 ps
T539 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.893434389 Jun 30 04:51:28 PM PDT 24 Jun 30 04:51:31 PM PDT 24 391911079 ps
T540 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1693824273 Jun 30 04:51:32 PM PDT 24 Jun 30 04:51:33 PM PDT 24 517406547 ps
T541 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1228959706 Jun 30 04:51:36 PM PDT 24 Jun 30 04:51:38 PM PDT 24 108435921 ps
T542 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.410639437 Jun 30 04:52:08 PM PDT 24 Jun 30 04:52:10 PM PDT 24 14044478 ps
T543 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.807483044 Jun 30 04:52:09 PM PDT 24 Jun 30 04:52:11 PM PDT 24 74693016 ps
T544 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3239557713 Jun 30 04:51:28 PM PDT 24 Jun 30 04:51:32 PM PDT 24 570548294 ps
T545 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2375439983 Jun 30 04:51:27 PM PDT 24 Jun 30 04:51:28 PM PDT 24 25261531 ps
T546 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3232725781 Jun 30 04:51:20 PM PDT 24 Jun 30 04:51:22 PM PDT 24 436671759 ps
T547 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2856723349 Jun 30 04:51:28 PM PDT 24 Jun 30 04:51:30 PM PDT 24 40342902 ps
T548 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3444137930 Jun 30 04:51:21 PM PDT 24 Jun 30 04:51:22 PM PDT 24 129429356 ps
T549 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3684170147 Jun 30 04:51:38 PM PDT 24 Jun 30 04:51:39 PM PDT 24 341803171 ps
T550 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1413700176 Jun 30 04:51:36 PM PDT 24 Jun 30 04:51:37 PM PDT 24 128783976 ps
T77 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2310826610 Jun 30 04:51:35 PM PDT 24 Jun 30 04:51:37 PM PDT 24 42238070 ps
T551 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3594014714 Jun 30 04:51:34 PM PDT 24 Jun 30 04:51:36 PM PDT 24 304185628 ps
T552 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1696898937 Jun 30 04:51:54 PM PDT 24 Jun 30 04:51:56 PM PDT 24 42547231 ps
T553 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.879883719 Jun 30 04:52:07 PM PDT 24 Jun 30 04:52:09 PM PDT 24 43828731 ps
T554 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3668590417 Jun 30 04:51:31 PM PDT 24 Jun 30 04:51:32 PM PDT 24 135956392 ps
T75 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.49723109 Jun 30 04:51:27 PM PDT 24 Jun 30 04:51:28 PM PDT 24 29574963 ps
T555 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3153755791 Jun 30 04:51:57 PM PDT 24 Jun 30 04:51:59 PM PDT 24 147364531 ps
T556 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1920274921 Jun 30 04:51:54 PM PDT 24 Jun 30 04:51:55 PM PDT 24 20034147 ps
T557 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2884720618 Jun 30 04:51:35 PM PDT 24 Jun 30 04:51:36 PM PDT 24 41567781 ps
T558 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3654583379 Jun 30 04:51:35 PM PDT 24 Jun 30 04:51:36 PM PDT 24 119337974 ps
T559 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1665886968 Jun 30 04:51:24 PM PDT 24 Jun 30 04:51:25 PM PDT 24 15873434 ps
T560 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3411904803 Jun 30 04:52:06 PM PDT 24 Jun 30 04:52:07 PM PDT 24 78077687 ps
T561 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2362267877 Jun 30 04:51:28 PM PDT 24 Jun 30 04:51:30 PM PDT 24 83798793 ps
T562 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3361020744 Jun 30 04:52:09 PM PDT 24 Jun 30 04:52:11 PM PDT 24 26749107 ps
T563 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3081297501 Jun 30 04:52:06 PM PDT 24 Jun 30 04:52:08 PM PDT 24 63127802 ps
T564 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1958931716 Jun 30 04:51:33 PM PDT 24 Jun 30 04:51:35 PM PDT 24 74731482 ps
T565 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3381957325 Jun 30 04:51:28 PM PDT 24 Jun 30 04:51:30 PM PDT 24 146318491 ps
T566 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3456804945 Jun 30 04:51:55 PM PDT 24 Jun 30 04:51:57 PM PDT 24 131612624 ps
T76 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3589647473 Jun 30 04:51:29 PM PDT 24 Jun 30 04:51:31 PM PDT 24 57164287 ps
T567 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3727019283 Jun 30 04:52:09 PM PDT 24 Jun 30 04:52:12 PM PDT 24 36549254 ps
T568 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1940128660 Jun 30 04:51:20 PM PDT 24 Jun 30 04:51:22 PM PDT 24 649600941 ps
T569 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.881537998 Jun 30 04:51:33 PM PDT 24 Jun 30 04:51:35 PM PDT 24 815320779 ps
T570 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1422127193 Jun 30 04:51:35 PM PDT 24 Jun 30 04:51:37 PM PDT 24 193280927 ps
T571 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.741764318 Jun 30 04:51:56 PM PDT 24 Jun 30 04:51:59 PM PDT 24 131426272 ps
T572 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.983557709 Jun 30 04:52:06 PM PDT 24 Jun 30 04:52:08 PM PDT 24 18455925 ps
T573 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.559957016 Jun 30 04:52:10 PM PDT 24 Jun 30 04:52:13 PM PDT 24 160817061 ps
T574 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3534483733 Jun 30 04:52:03 PM PDT 24 Jun 30 04:52:04 PM PDT 24 94470436 ps
T575 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1540363490 Jun 30 04:51:35 PM PDT 24 Jun 30 04:51:39 PM PDT 24 855022277 ps
T576 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1674525901 Jun 30 04:52:06 PM PDT 24 Jun 30 04:52:08 PM PDT 24 49128693 ps
T577 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.182727665 Jun 30 04:51:56 PM PDT 24 Jun 30 04:51:58 PM PDT 24 88139791 ps
T578 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2987682898 Jun 30 04:52:06 PM PDT 24 Jun 30 04:52:07 PM PDT 24 27309974 ps
T579 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1341985121 Jun 30 04:51:21 PM PDT 24 Jun 30 04:51:24 PM PDT 24 445459616 ps
T580 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.744335992 Jun 30 04:52:06 PM PDT 24 Jun 30 04:52:08 PM PDT 24 75199001 ps
T581 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2499095706 Jun 30 04:51:35 PM PDT 24 Jun 30 04:51:36 PM PDT 24 195405814 ps
T582 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.353126865 Jun 30 04:51:35 PM PDT 24 Jun 30 04:51:37 PM PDT 24 58323677 ps
T583 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2679369210 Jun 30 04:52:06 PM PDT 24 Jun 30 04:52:08 PM PDT 24 117356277 ps
T584 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1788872234 Jun 30 04:52:12 PM PDT 24 Jun 30 04:52:14 PM PDT 24 10638772 ps
T585 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1570677825 Jun 30 04:51:56 PM PDT 24 Jun 30 04:51:58 PM PDT 24 29085999 ps
T586 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3809417338 Jun 30 04:51:27 PM PDT 24 Jun 30 04:51:29 PM PDT 24 20242476 ps

Test location /workspace/coverage/default/2.rv_timer_stress_all.3344661408
Short name T3
Test name
Test status
Simulation time 786084733580 ps
CPU time 1519.69 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 05:17:30 PM PDT 24
Peak memory 191272 kb
Host smart-53893c36-8875-42d4-92f6-0315b09387d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344661408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3344661408
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.1679209628
Short name T32
Test name
Test status
Simulation time 53428102948 ps
CPU time 333.61 seconds
Started Jun 30 04:52:23 PM PDT 24
Finished Jun 30 04:57:57 PM PDT 24
Peak memory 205844 kb
Host smart-d1f6fcd4-3dae-45cf-aec5-8328c4c3155c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679209628 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.1679209628
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3201473018
Short name T39
Test name
Test status
Simulation time 2714285427111 ps
CPU time 2027.23 seconds
Started Jun 30 04:52:32 PM PDT 24
Finished Jun 30 05:26:20 PM PDT 24
Peak memory 191256 kb
Host smart-17d283cd-856b-469f-8935-db00bd9ac52f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201473018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3201473018
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1363669540
Short name T25
Test name
Test status
Simulation time 104591678 ps
CPU time 1.34 seconds
Started Jun 30 04:52:05 PM PDT 24
Finished Jun 30 04:52:07 PM PDT 24
Peak memory 195032 kb
Host smart-ce90c337-ba00-4d22-89c6-df203058e9a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363669540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1363669540
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3313192972
Short name T95
Test name
Test status
Simulation time 590336633591 ps
CPU time 1210.72 seconds
Started Jun 30 04:52:20 PM PDT 24
Finished Jun 30 05:12:31 PM PDT 24
Peak memory 191172 kb
Host smart-ff342c0d-8eda-4a35-aff4-6c69d1a21265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313192972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3313192972
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2648108906
Short name T142
Test name
Test status
Simulation time 7507649501670 ps
CPU time 2702.06 seconds
Started Jun 30 04:52:40 PM PDT 24
Finished Jun 30 05:37:43 PM PDT 24
Peak memory 190744 kb
Host smart-fd30cfb0-7aba-4d25-a620-52ef48a3c7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648108906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2648108906
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2128648691
Short name T180
Test name
Test status
Simulation time 706577967702 ps
CPU time 2675.25 seconds
Started Jun 30 04:52:17 PM PDT 24
Finished Jun 30 05:36:53 PM PDT 24
Peak memory 191276 kb
Host smart-9f03aa0c-d45a-41e6-a807-c603830ea2d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128648691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2128648691
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3229566516
Short name T103
Test name
Test status
Simulation time 644590923115 ps
CPU time 1875.99 seconds
Started Jun 30 04:52:20 PM PDT 24
Finished Jun 30 05:23:37 PM PDT 24
Peak memory 191052 kb
Host smart-a90ad5c1-290b-4c67-871e-061f8167e95b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229566516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3229566516
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.965913535
Short name T239
Test name
Test status
Simulation time 2187586032607 ps
CPU time 1331.45 seconds
Started Jun 30 04:52:39 PM PDT 24
Finished Jun 30 05:14:51 PM PDT 24
Peak memory 196428 kb
Host smart-503e299f-0907-4f4b-82db-d379db100116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965913535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
965913535
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2354126791
Short name T194
Test name
Test status
Simulation time 523943440156 ps
CPU time 2110.49 seconds
Started Jun 30 04:52:21 PM PDT 24
Finished Jun 30 05:27:33 PM PDT 24
Peak memory 191280 kb
Host smart-491b2d9d-fa81-4490-8834-f3fe81016f78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354126791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2354126791
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1973576405
Short name T127
Test name
Test status
Simulation time 692429136150 ps
CPU time 2280.35 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 05:30:26 PM PDT 24
Peak memory 191168 kb
Host smart-dd5921ef-4667-44dd-8869-b17b47cff9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973576405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1973576405
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2263351966
Short name T15
Test name
Test status
Simulation time 96115795 ps
CPU time 0.76 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 04:52:09 PM PDT 24
Peak memory 213376 kb
Host smart-8e9d54c5-2074-411b-abc5-1389bed82b2a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263351966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2263351966
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/100.rv_timer_random.4055646841
Short name T195
Test name
Test status
Simulation time 523423874541 ps
CPU time 415.52 seconds
Started Jun 30 04:53:31 PM PDT 24
Finished Jun 30 05:00:27 PM PDT 24
Peak memory 191284 kb
Host smart-bfbde05b-0f50-4951-ba11-54f82b5edbe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055646841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.4055646841
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3566094139
Short name T174
Test name
Test status
Simulation time 446272806095 ps
CPU time 1250.13 seconds
Started Jun 30 04:52:28 PM PDT 24
Finished Jun 30 05:13:19 PM PDT 24
Peak memory 191280 kb
Host smart-4ec0515d-76b7-440f-bef2-c79a83b6be1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566094139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3566094139
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1901970965
Short name T262
Test name
Test status
Simulation time 2852233786336 ps
CPU time 1701.47 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 05:20:47 PM PDT 24
Peak memory 195928 kb
Host smart-c9924a75-80b8-4f1b-959e-c1308e805e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901970965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1901970965
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.1577394072
Short name T90
Test name
Test status
Simulation time 239084527764 ps
CPU time 737.04 seconds
Started Jun 30 04:53:53 PM PDT 24
Finished Jun 30 05:06:10 PM PDT 24
Peak memory 191252 kb
Host smart-388b85bb-e430-42ec-b6bb-b536e92dbcc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577394072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1577394072
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2159063586
Short name T1
Test name
Test status
Simulation time 408781675538 ps
CPU time 720.69 seconds
Started Jun 30 04:52:48 PM PDT 24
Finished Jun 30 05:04:49 PM PDT 24
Peak memory 195400 kb
Host smart-9aa00e3d-5ebc-4188-963b-21c7f7bde0f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159063586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2159063586
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.733812860
Short name T306
Test name
Test status
Simulation time 386266384645 ps
CPU time 2698.02 seconds
Started Jun 30 04:53:03 PM PDT 24
Finished Jun 30 05:38:02 PM PDT 24
Peak memory 191248 kb
Host smart-2d510aae-f7a9-48ff-abea-7001e5f6e40b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733812860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.733812860
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2533428620
Short name T199
Test name
Test status
Simulation time 4707299222453 ps
CPU time 2895.38 seconds
Started Jun 30 04:52:21 PM PDT 24
Finished Jun 30 05:40:37 PM PDT 24
Peak memory 191284 kb
Host smart-d8a4626f-da98-49c2-adb2-7fcd544b1970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533428620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2533428620
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1067879644
Short name T206
Test name
Test status
Simulation time 636352425831 ps
CPU time 560.69 seconds
Started Jun 30 04:52:51 PM PDT 24
Finished Jun 30 05:02:12 PM PDT 24
Peak memory 191288 kb
Host smart-9af30d8e-e921-49fa-8953-9496662a09a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067879644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1067879644
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2904550198
Short name T61
Test name
Test status
Simulation time 79423670 ps
CPU time 0.53 seconds
Started Jun 30 04:51:19 PM PDT 24
Finished Jun 30 04:51:21 PM PDT 24
Peak memory 181776 kb
Host smart-1e819219-0c24-47b6-abdd-34a35ed4251d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904550198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2904550198
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/118.rv_timer_random.1234151949
Short name T155
Test name
Test status
Simulation time 204028914875 ps
CPU time 341.38 seconds
Started Jun 30 04:53:47 PM PDT 24
Finished Jun 30 04:59:29 PM PDT 24
Peak memory 191240 kb
Host smart-688e4c74-346b-4517-ba58-73f1724e3e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234151949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1234151949
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.3590396411
Short name T303
Test name
Test status
Simulation time 305623028852 ps
CPU time 802.4 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 05:05:48 PM PDT 24
Peak memory 191256 kb
Host smart-6db30a6c-ff64-4a86-bc98-c7eb41e56c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590396411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3590396411
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.875712491
Short name T108
Test name
Test status
Simulation time 68156273703 ps
CPU time 101.77 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:53:53 PM PDT 24
Peak memory 191292 kb
Host smart-afdc9e90-0122-4be4-910d-c0d837ae07d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875712491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.875712491
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2386463338
Short name T252
Test name
Test status
Simulation time 870371692977 ps
CPU time 1520.88 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 05:18:11 PM PDT 24
Peak memory 191280 kb
Host smart-080ba77a-7f6c-48f3-a2ad-f12d6f8a3766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386463338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2386463338
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/197.rv_timer_random.1725993353
Short name T19
Test name
Test status
Simulation time 354211065139 ps
CPU time 535.34 seconds
Started Jun 30 04:54:50 PM PDT 24
Finished Jun 30 05:03:45 PM PDT 24
Peak memory 191288 kb
Host smart-f72c96cf-4885-4726-a7db-b241facaa12d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725993353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1725993353
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1094400694
Short name T137
Test name
Test status
Simulation time 152399120698 ps
CPU time 1261.26 seconds
Started Jun 30 04:54:01 PM PDT 24
Finished Jun 30 05:15:03 PM PDT 24
Peak memory 191256 kb
Host smart-1531f3b1-5e28-47fd-ab6b-3b74a22efe07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094400694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1094400694
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2345853010
Short name T231
Test name
Test status
Simulation time 641576839068 ps
CPU time 325.68 seconds
Started Jun 30 04:54:18 PM PDT 24
Finished Jun 30 04:59:44 PM PDT 24
Peak memory 191288 kb
Host smart-84c6aed7-b897-413e-ba83-9e506da0ac3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345853010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2345853010
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3056443625
Short name T277
Test name
Test status
Simulation time 1408411398928 ps
CPU time 489.85 seconds
Started Jun 30 04:54:27 PM PDT 24
Finished Jun 30 05:02:37 PM PDT 24
Peak memory 191288 kb
Host smart-a323c8fa-2c43-46ba-9185-e1700b9b56aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056443625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3056443625
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1714729684
Short name T268
Test name
Test status
Simulation time 263704119039 ps
CPU time 297.98 seconds
Started Jun 30 04:54:43 PM PDT 24
Finished Jun 30 04:59:42 PM PDT 24
Peak memory 190404 kb
Host smart-536faf66-28ba-4549-8970-b6f41fff292f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714729684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1714729684
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2695637186
Short name T153
Test name
Test status
Simulation time 1451872041370 ps
CPU time 609.67 seconds
Started Jun 30 04:52:55 PM PDT 24
Finished Jun 30 05:03:05 PM PDT 24
Peak memory 195184 kb
Host smart-0197c99e-1820-4e33-a19a-a9e6600cece8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695637186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2695637186
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.1612070944
Short name T324
Test name
Test status
Simulation time 760215023022 ps
CPU time 396.98 seconds
Started Jun 30 04:53:53 PM PDT 24
Finished Jun 30 05:00:31 PM PDT 24
Peak memory 191228 kb
Host smart-8aedb786-2cb7-46f2-92a2-614d9cd8e588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612070944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1612070944
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2723766215
Short name T343
Test name
Test status
Simulation time 114434286233 ps
CPU time 209.81 seconds
Started Jun 30 04:54:37 PM PDT 24
Finished Jun 30 04:58:07 PM PDT 24
Peak memory 183092 kb
Host smart-0274d965-f73e-45b4-b040-662db8948279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723766215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2723766215
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2119303787
Short name T318
Test name
Test status
Simulation time 1395806356274 ps
CPU time 1076.27 seconds
Started Jun 30 04:52:25 PM PDT 24
Finished Jun 30 05:10:22 PM PDT 24
Peak memory 191288 kb
Host smart-fcff9f96-5287-4250-85ff-097124bd2f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119303787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2119303787
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2403861256
Short name T106
Test name
Test status
Simulation time 662346481800 ps
CPU time 569.44 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 05:01:38 PM PDT 24
Peak memory 191248 kb
Host smart-79f497eb-f342-4dd5-b558-885c2932e2c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403861256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2403861256
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_random.1747031712
Short name T197
Test name
Test status
Simulation time 146116700184 ps
CPU time 325.02 seconds
Started Jun 30 04:52:58 PM PDT 24
Finished Jun 30 04:58:23 PM PDT 24
Peak memory 191228 kb
Host smart-c0d82e1c-f9c2-41df-9020-5abcf5f6b016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747031712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1747031712
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.3952076068
Short name T346
Test name
Test status
Simulation time 59343186024 ps
CPU time 122.62 seconds
Started Jun 30 04:53:09 PM PDT 24
Finished Jun 30 04:55:12 PM PDT 24
Peak memory 191256 kb
Host smart-d16f1d8b-7bbd-443e-b905-46da7f19b038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952076068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3952076068
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.377144667
Short name T210
Test name
Test status
Simulation time 128810881840 ps
CPU time 189.03 seconds
Started Jun 30 04:53:15 PM PDT 24
Finished Jun 30 04:56:25 PM PDT 24
Peak memory 183044 kb
Host smart-dbae3fb8-ed05-4afc-9d32-e14835f9fca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377144667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.377144667
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.211853508
Short name T109
Test name
Test status
Simulation time 592858001235 ps
CPU time 286.33 seconds
Started Jun 30 04:53:33 PM PDT 24
Finished Jun 30 04:58:20 PM PDT 24
Peak memory 191268 kb
Host smart-59185248-6028-4077-99f4-2831f7ae93c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211853508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.211853508
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3245298043
Short name T163
Test name
Test status
Simulation time 609142534401 ps
CPU time 296.1 seconds
Started Jun 30 04:53:38 PM PDT 24
Finished Jun 30 04:58:35 PM PDT 24
Peak memory 191540 kb
Host smart-1cc28ad9-d3b8-4797-a4c3-6333690ad0af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245298043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3245298043
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.1866459168
Short name T133
Test name
Test status
Simulation time 1112307647569 ps
CPU time 1721.96 seconds
Started Jun 30 04:52:38 PM PDT 24
Finished Jun 30 05:21:20 PM PDT 24
Peak memory 195976 kb
Host smart-a3f114da-5ec8-4ca9-bacd-c8981b56e217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866459168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.1866459168
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3691178100
Short name T91
Test name
Test status
Simulation time 352372113480 ps
CPU time 571.63 seconds
Started Jun 30 04:52:47 PM PDT 24
Finished Jun 30 05:02:20 PM PDT 24
Peak memory 183016 kb
Host smart-47ca3ec1-d68a-4dbc-a493-7e570d3a6cbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691178100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3691178100
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/86.rv_timer_random.4072196645
Short name T189
Test name
Test status
Simulation time 549441806502 ps
CPU time 220.51 seconds
Started Jun 30 04:53:24 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 191284 kb
Host smart-4ca34314-80ac-4fc7-98dd-4987d209c607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072196645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4072196645
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1116312047
Short name T99
Test name
Test status
Simulation time 509534103182 ps
CPU time 413.11 seconds
Started Jun 30 04:53:47 PM PDT 24
Finished Jun 30 05:00:40 PM PDT 24
Peak memory 191288 kb
Host smart-409d6812-93dc-4f63-8070-9b26cd3e8586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116312047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1116312047
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.254833817
Short name T6
Test name
Test status
Simulation time 606466803431 ps
CPU time 2588.28 seconds
Started Jun 30 04:53:47 PM PDT 24
Finished Jun 30 05:36:56 PM PDT 24
Peak memory 191284 kb
Host smart-9a564349-2f62-4733-9434-51476f49122b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254833817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.254833817
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1010655093
Short name T320
Test name
Test status
Simulation time 78610390841 ps
CPU time 64.05 seconds
Started Jun 30 04:54:12 PM PDT 24
Finished Jun 30 04:55:16 PM PDT 24
Peak memory 191196 kb
Host smart-1c3d4b73-5d45-467d-bbab-dd65b371e354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010655093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1010655093
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.3095087288
Short name T117
Test name
Test status
Simulation time 229213957662 ps
CPU time 211.39 seconds
Started Jun 30 04:52:20 PM PDT 24
Finished Jun 30 04:55:52 PM PDT 24
Peak memory 191164 kb
Host smart-22b273c4-49e9-4845-915d-1fca8891475c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095087288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3095087288
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/50.rv_timer_random.271127369
Short name T100
Test name
Test status
Simulation time 234249899920 ps
CPU time 264.2 seconds
Started Jun 30 04:53:03 PM PDT 24
Finished Jun 30 04:57:28 PM PDT 24
Peak memory 191296 kb
Host smart-531f0ac2-ee1b-41ac-81bc-2dc7ef63be14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271127369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.271127369
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.537307716
Short name T192
Test name
Test status
Simulation time 125978041914 ps
CPU time 205.54 seconds
Started Jun 30 04:53:03 PM PDT 24
Finished Jun 30 04:56:29 PM PDT 24
Peak memory 191280 kb
Host smart-1068cc51-6cb2-410e-bc6e-ea43d5c34a93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537307716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.537307716
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2781848053
Short name T284
Test name
Test status
Simulation time 953514352011 ps
CPU time 123.53 seconds
Started Jun 30 04:53:07 PM PDT 24
Finished Jun 30 04:55:11 PM PDT 24
Peak memory 193548 kb
Host smart-4392c193-729b-4658-afc4-d409636a6004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781848053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2781848053
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.3385571506
Short name T275
Test name
Test status
Simulation time 479396014609 ps
CPU time 2523.59 seconds
Started Jun 30 04:52:11 PM PDT 24
Finished Jun 30 05:34:16 PM PDT 24
Peak memory 191288 kb
Host smart-9da1466f-d199-4647-a3de-07dc39149c18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385571506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3385571506
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3786973209
Short name T74
Test name
Test status
Simulation time 25937272 ps
CPU time 0.74 seconds
Started Jun 30 04:51:21 PM PDT 24
Finished Jun 30 04:51:23 PM PDT 24
Peak memory 192176 kb
Host smart-648d405f-3508-41aa-ba65-1474fa09c0da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786973209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3786973209
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4055047054
Short name T29
Test name
Test status
Simulation time 30560749 ps
CPU time 0.72 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 191596 kb
Host smart-782ef1e0-e5e8-48cb-861f-3779dd4855f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055047054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4055047054
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/102.rv_timer_random.3904835566
Short name T188
Test name
Test status
Simulation time 217067451194 ps
CPU time 193.21 seconds
Started Jun 30 04:53:31 PM PDT 24
Finished Jun 30 04:56:45 PM PDT 24
Peak memory 194492 kb
Host smart-345a47fc-38ad-47ad-82ff-e0b419d27d71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904835566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3904835566
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1566438405
Short name T244
Test name
Test status
Simulation time 621979158435 ps
CPU time 1386.98 seconds
Started Jun 30 04:53:38 PM PDT 24
Finished Jun 30 05:16:46 PM PDT 24
Peak memory 191188 kb
Host smart-506f2fb4-9810-4604-94b1-0c89d80d2149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566438405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1566438405
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3425287918
Short name T212
Test name
Test status
Simulation time 441469109218 ps
CPU time 230.45 seconds
Started Jun 30 04:52:18 PM PDT 24
Finished Jun 30 04:56:09 PM PDT 24
Peak memory 183076 kb
Host smart-cb9853f0-e508-43d3-9f1d-48718aad7fcc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425287918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3425287918
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2921622956
Short name T167
Test name
Test status
Simulation time 252475912440 ps
CPU time 374.16 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 04:58:31 PM PDT 24
Peak memory 182796 kb
Host smart-745232dd-8e56-4ccc-af50-9fc24e027cae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921622956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2921622956
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/140.rv_timer_random.973569604
Short name T104
Test name
Test status
Simulation time 532606380263 ps
CPU time 164.79 seconds
Started Jun 30 04:54:08 PM PDT 24
Finished Jun 30 04:56:53 PM PDT 24
Peak memory 193560 kb
Host smart-a2fd209f-34fa-4361-af2f-eec230437c81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973569604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.973569604
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3534325851
Short name T166
Test name
Test status
Simulation time 151927095339 ps
CPU time 252.57 seconds
Started Jun 30 04:54:18 PM PDT 24
Finished Jun 30 04:58:31 PM PDT 24
Peak memory 191188 kb
Host smart-5876e448-97b9-4783-940c-d84bf3fcdb91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534325851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3534325851
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2838281836
Short name T97
Test name
Test status
Simulation time 200276433825 ps
CPU time 259.6 seconds
Started Jun 30 04:54:34 PM PDT 24
Finished Jun 30 04:58:54 PM PDT 24
Peak memory 193856 kb
Host smart-90169341-7a83-403f-b949-a42c3bf2eced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838281836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2838281836
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2812514079
Short name T57
Test name
Test status
Simulation time 173268785617 ps
CPU time 286.79 seconds
Started Jun 30 04:54:34 PM PDT 24
Finished Jun 30 04:59:21 PM PDT 24
Peak memory 191248 kb
Host smart-f7f71d78-96d4-4ed8-b0e8-bc8e468003a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812514079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2812514079
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2438898676
Short name T322
Test name
Test status
Simulation time 2159014793295 ps
CPU time 1169.2 seconds
Started Jun 30 04:52:15 PM PDT 24
Finished Jun 30 05:11:45 PM PDT 24
Peak memory 191264 kb
Host smart-9bbaa6c6-8f35-445a-a2d8-e42de01e1a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438898676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2438898676
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_random.2585004754
Short name T2
Test name
Test status
Simulation time 159027467898 ps
CPU time 817.11 seconds
Started Jun 30 04:52:38 PM PDT 24
Finished Jun 30 05:06:16 PM PDT 24
Peak memory 191184 kb
Host smart-40d3f13a-d0c6-499a-906d-f40ad0e3142f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585004754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2585004754
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2268484583
Short name T138
Test name
Test status
Simulation time 15893453526 ps
CPU time 26.82 seconds
Started Jun 30 04:52:47 PM PDT 24
Finished Jun 30 04:53:15 PM PDT 24
Peak memory 183108 kb
Host smart-519a46ce-38a4-45f8-8396-524687638018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268484583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2268484583
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_random.970820271
Short name T234
Test name
Test status
Simulation time 149034052689 ps
CPU time 200.85 seconds
Started Jun 30 04:52:51 PM PDT 24
Finished Jun 30 04:56:12 PM PDT 24
Peak memory 191284 kb
Host smart-a9665d0f-628c-4fe2-ba7d-50f513602fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970820271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.970820271
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3182292077
Short name T255
Test name
Test status
Simulation time 437212450816 ps
CPU time 243.5 seconds
Started Jun 30 04:53:03 PM PDT 24
Finished Jun 30 04:57:08 PM PDT 24
Peak memory 183072 kb
Host smart-4ae9270e-4146-46b7-bbd2-7f85bb3c1ca4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182292077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3182292077
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.36193284
Short name T129
Test name
Test status
Simulation time 135768279040 ps
CPU time 198.07 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:55:30 PM PDT 24
Peak memory 182980 kb
Host smart-82f0aa6a-8a56-46a2-8490-e7441742c3d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36193284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
rv_timer_cfg_update_on_fly.36193284
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/75.rv_timer_random.2515320182
Short name T21
Test name
Test status
Simulation time 113842359173 ps
CPU time 146.99 seconds
Started Jun 30 04:53:18 PM PDT 24
Finished Jun 30 04:55:45 PM PDT 24
Peak memory 191284 kb
Host smart-9734934a-fcfa-4ea0-805c-c99187b972da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515320182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2515320182
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1617069180
Short name T238
Test name
Test status
Simulation time 394094812316 ps
CPU time 1049.18 seconds
Started Jun 30 04:53:17 PM PDT 24
Finished Jun 30 05:10:47 PM PDT 24
Peak memory 191256 kb
Host smart-e9069d7c-baa1-4575-9953-1ecce0289eb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617069180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1617069180
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3466783987
Short name T170
Test name
Test status
Simulation time 3976241623412 ps
CPU time 1101.53 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 05:10:32 PM PDT 24
Peak memory 183088 kb
Host smart-15abef5b-9753-4c2b-ba1c-a9116faaee31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466783987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3466783987
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1358956484
Short name T40
Test name
Test status
Simulation time 26930703179 ps
CPU time 318.43 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:57:26 PM PDT 24
Peak memory 183096 kb
Host smart-9826bd6c-0569-43fa-ad29-e454a660cd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358956484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1358956484
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.3789058676
Short name T304
Test name
Test status
Simulation time 125599988963 ps
CPU time 1602.31 seconds
Started Jun 30 04:53:31 PM PDT 24
Finished Jun 30 05:20:14 PM PDT 24
Peak memory 191236 kb
Host smart-b85a3794-aa60-4198-ade1-f2511c6dc348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789058676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3789058676
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.4050643008
Short name T232
Test name
Test status
Simulation time 169579839372 ps
CPU time 250.87 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 04:56:26 PM PDT 24
Peak memory 191180 kb
Host smart-25b73228-5b04-4492-a2c1-475ca357dd2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050643008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.4050643008
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3610967410
Short name T120
Test name
Test status
Simulation time 46496775203 ps
CPU time 67.7 seconds
Started Jun 30 04:53:47 PM PDT 24
Finished Jun 30 04:54:55 PM PDT 24
Peak memory 194716 kb
Host smart-172ff0d7-8544-4cc6-b414-b5ad740aeb7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610967410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3610967410
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1155920402
Short name T22
Test name
Test status
Simulation time 111792953622 ps
CPU time 137.27 seconds
Started Jun 30 04:53:46 PM PDT 24
Finished Jun 30 04:56:04 PM PDT 24
Peak memory 191288 kb
Host smart-35f2d30b-af1d-463b-b91b-1bbb336ef32a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155920402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1155920402
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.4037326526
Short name T339
Test name
Test status
Simulation time 856626266535 ps
CPU time 717.39 seconds
Started Jun 30 04:53:53 PM PDT 24
Finished Jun 30 05:05:51 PM PDT 24
Peak memory 191260 kb
Host smart-f5b7b223-1231-4d4e-9d61-d16f7766287c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037326526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.4037326526
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.3461711546
Short name T271
Test name
Test status
Simulation time 2228950345726 ps
CPU time 1082.46 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 05:10:19 PM PDT 24
Peak memory 182960 kb
Host smart-13c0b66f-6060-48bc-b5e6-da255ba84e88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461711546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.3461711546
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/134.rv_timer_random.1851140290
Short name T354
Test name
Test status
Simulation time 164190472826 ps
CPU time 996.78 seconds
Started Jun 30 04:54:02 PM PDT 24
Finished Jun 30 05:10:39 PM PDT 24
Peak memory 191244 kb
Host smart-81ea2ffb-a2ac-4ac6-9a6d-0318ffc7bc37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851140290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1851140290
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3317722468
Short name T249
Test name
Test status
Simulation time 183170935064 ps
CPU time 216.2 seconds
Started Jun 30 04:54:10 PM PDT 24
Finished Jun 30 04:57:47 PM PDT 24
Peak memory 191256 kb
Host smart-86301dfd-7a99-4439-9374-9b89200b0258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317722468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3317722468
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2179782915
Short name T107
Test name
Test status
Simulation time 135384334112 ps
CPU time 658.24 seconds
Started Jun 30 04:54:26 PM PDT 24
Finished Jun 30 05:05:25 PM PDT 24
Peak memory 191284 kb
Host smart-f775391e-9a49-4233-b755-9cd1ee2fa131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179782915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2179782915
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1001874166
Short name T125
Test name
Test status
Simulation time 188959728969 ps
CPU time 798.6 seconds
Started Jun 30 04:54:32 PM PDT 24
Finished Jun 30 05:07:51 PM PDT 24
Peak memory 191236 kb
Host smart-87580c0d-499b-4c16-a52a-61cacbfe1021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001874166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1001874166
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1606415392
Short name T310
Test name
Test status
Simulation time 773810960269 ps
CPU time 604.03 seconds
Started Jun 30 04:54:40 PM PDT 24
Finished Jun 30 05:04:45 PM PDT 24
Peak memory 191196 kb
Host smart-5feee600-7c5b-4a50-b133-35eaeffa5d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606415392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1606415392
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.250967483
Short name T301
Test name
Test status
Simulation time 5143501991 ps
CPU time 2.99 seconds
Started Jun 30 04:54:41 PM PDT 24
Finished Jun 30 04:54:44 PM PDT 24
Peak memory 183076 kb
Host smart-d6ed4f55-f50d-43f0-8f18-867bf2559a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250967483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.250967483
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.729358181
Short name T319
Test name
Test status
Simulation time 47517505222 ps
CPU time 68.2 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:53:20 PM PDT 24
Peak memory 183060 kb
Host smart-748c2abf-db12-4beb-a7f6-42f53f67c98e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729358181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.729358181
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_random.2083831075
Short name T94
Test name
Test status
Simulation time 65403458290 ps
CPU time 103.64 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:53:55 PM PDT 24
Peak memory 191300 kb
Host smart-48994526-5f66-4288-949a-b6c5c40ba5c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083831075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2083831075
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.2787088700
Short name T131
Test name
Test status
Simulation time 108611401758 ps
CPU time 148.56 seconds
Started Jun 30 04:52:12 PM PDT 24
Finished Jun 30 04:54:42 PM PDT 24
Peak memory 191276 kb
Host smart-c0cfc031-ff5a-4beb-80ae-661e41365e8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787088700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2787088700
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.415386964
Short name T352
Test name
Test status
Simulation time 231051643 ps
CPU time 0.9 seconds
Started Jun 30 04:52:20 PM PDT 24
Finished Jun 30 04:52:22 PM PDT 24
Peak memory 182924 kb
Host smart-bb37e08f-02ac-4092-a379-abaa54a46249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415386964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.415386964
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3106417804
Short name T344
Test name
Test status
Simulation time 68169661772 ps
CPU time 112.01 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:54:16 PM PDT 24
Peak memory 182876 kb
Host smart-2092984d-409d-42de-bd4f-a0f66f84ab27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106417804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3106417804
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.198521893
Short name T361
Test name
Test status
Simulation time 248486824858 ps
CPU time 312.68 seconds
Started Jun 30 04:52:26 PM PDT 24
Finished Jun 30 04:57:39 PM PDT 24
Peak memory 191200 kb
Host smart-c91a811e-1360-4378-8cdc-a5f4cdd3eb08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198521893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
198521893
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1492658304
Short name T200
Test name
Test status
Simulation time 4424307616 ps
CPU time 8.56 seconds
Started Jun 30 04:52:26 PM PDT 24
Finished Jun 30 04:52:35 PM PDT 24
Peak memory 183068 kb
Host smart-a6f68bef-a597-4b89-a230-5d967d1b2c3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492658304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1492658304
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1473229245
Short name T236
Test name
Test status
Simulation time 40293669428 ps
CPU time 390.96 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:58:39 PM PDT 24
Peak memory 191304 kb
Host smart-221ba2ce-a30c-492e-9aa4-b69443ade6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473229245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1473229245
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.4156222048
Short name T154
Test name
Test status
Simulation time 112103562190 ps
CPU time 63.02 seconds
Started Jun 30 04:52:52 PM PDT 24
Finished Jun 30 04:53:56 PM PDT 24
Peak memory 183348 kb
Host smart-78d022d2-436e-4e14-90b9-d451e3b7ec5b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156222048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.4156222048
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.151325396
Short name T296
Test name
Test status
Simulation time 41122558621 ps
CPU time 31.41 seconds
Started Jun 30 04:52:58 PM PDT 24
Finished Jun 30 04:53:30 PM PDT 24
Peak memory 183036 kb
Host smart-8f8e976c-a9f2-4a5c-a200-ee311b02880a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151325396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.151325396
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3975820976
Short name T240
Test name
Test status
Simulation time 304951946265 ps
CPU time 409.54 seconds
Started Jun 30 04:52:11 PM PDT 24
Finished Jun 30 04:59:02 PM PDT 24
Peak memory 182984 kb
Host smart-d31ef457-c5e5-464a-96ed-8aaa073f8b69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975820976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3975820976
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/91.rv_timer_random.3863555122
Short name T273
Test name
Test status
Simulation time 60857861910 ps
CPU time 460.33 seconds
Started Jun 30 04:53:24 PM PDT 24
Finished Jun 30 05:01:05 PM PDT 24
Peak memory 191188 kb
Host smart-30d4d789-ca27-45df-a1a9-7f47eaabff7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863555122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3863555122
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2845658134
Short name T469
Test name
Test status
Simulation time 617307105 ps
CPU time 1.6 seconds
Started Jun 30 04:51:23 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 191668 kb
Host smart-9ed3c015-9c7e-4ad8-8c5b-f9331b924cad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845658134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2845658134
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3033406817
Short name T489
Test name
Test status
Simulation time 103640911 ps
CPU time 0.67 seconds
Started Jun 30 04:51:26 PM PDT 24
Finished Jun 30 04:51:27 PM PDT 24
Peak memory 194328 kb
Host smart-dc441cd4-1f58-45f9-b8b4-334b1c1d7a28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033406817 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3033406817
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1263391621
Short name T78
Test name
Test status
Simulation time 25162291 ps
CPU time 0.54 seconds
Started Jun 30 04:51:21 PM PDT 24
Finished Jun 30 04:51:22 PM PDT 24
Peak memory 181956 kb
Host smart-801c6aeb-6915-4efd-855b-f32c9f353b1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263391621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1263391621
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1335905087
Short name T472
Test name
Test status
Simulation time 26179161 ps
CPU time 0.56 seconds
Started Jun 30 04:51:22 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 181632 kb
Host smart-443ce37d-116f-40e9-ad45-5adad7f6a473
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335905087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1335905087
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.968835636
Short name T497
Test name
Test status
Simulation time 173809662 ps
CPU time 0.78 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 192464 kb
Host smart-d56cdf83-219b-4382-959b-01b1870e3abc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968835636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.968835636
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3098883538
Short name T502
Test name
Test status
Simulation time 104246592 ps
CPU time 2.08 seconds
Started Jun 30 04:51:20 PM PDT 24
Finished Jun 30 04:51:23 PM PDT 24
Peak memory 197028 kb
Host smart-a32b837e-4d1c-4727-b23c-0055062ac57d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098883538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3098883538
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3232725781
Short name T546
Test name
Test status
Simulation time 436671759 ps
CPU time 1.12 seconds
Started Jun 30 04:51:20 PM PDT 24
Finished Jun 30 04:51:22 PM PDT 24
Peak memory 194620 kb
Host smart-2cddf6f9-cabc-484d-b3ec-4f9d83dada4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232725781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3232725781
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3193362438
Short name T64
Test name
Test status
Simulation time 55430218 ps
CPU time 0.79 seconds
Started Jun 30 04:51:20 PM PDT 24
Finished Jun 30 04:51:21 PM PDT 24
Peak memory 192176 kb
Host smart-ff31eb6d-358f-4099-98d2-56dc8daad419
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193362438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3193362438
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2348076336
Short name T70
Test name
Test status
Simulation time 336397136 ps
CPU time 2.9 seconds
Started Jun 30 04:51:26 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 191784 kb
Host smart-1b0c5ee0-1c1f-4114-8221-c6bf2df6f883
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348076336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2348076336
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1229700170
Short name T66
Test name
Test status
Simulation time 14852669 ps
CPU time 0.54 seconds
Started Jun 30 04:51:19 PM PDT 24
Finished Jun 30 04:51:21 PM PDT 24
Peak memory 181756 kb
Host smart-b4a36c14-be23-4d21-9520-03066154fab2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229700170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1229700170
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3229646097
Short name T493
Test name
Test status
Simulation time 46825792 ps
CPU time 0.72 seconds
Started Jun 30 04:51:22 PM PDT 24
Finished Jun 30 04:51:23 PM PDT 24
Peak memory 194268 kb
Host smart-f501d39a-496c-40c8-b388-3f08d89c4b90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229646097 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3229646097
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4116456144
Short name T486
Test name
Test status
Simulation time 11153294 ps
CPU time 0.55 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 182188 kb
Host smart-868046b5-661b-474f-99b1-0025a64d046f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116456144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.4116456144
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4203461679
Short name T467
Test name
Test status
Simulation time 36238757 ps
CPU time 0.55 seconds
Started Jun 30 04:51:24 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 182096 kb
Host smart-f3208630-2971-4d68-9b0b-99487d2cdc48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203461679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4203461679
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2798622339
Short name T479
Test name
Test status
Simulation time 89291758 ps
CPU time 2.06 seconds
Started Jun 30 04:51:21 PM PDT 24
Finished Jun 30 04:51:23 PM PDT 24
Peak memory 196980 kb
Host smart-07b10bb6-6369-45d8-9903-2f2d308861a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798622339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2798622339
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.719897803
Short name T491
Test name
Test status
Simulation time 472644639 ps
CPU time 1.33 seconds
Started Jun 30 04:51:23 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 195028 kb
Host smart-f45b53ae-310c-4a2e-95eb-afa6d9ddd3a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719897803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.719897803
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2521179472
Short name T28
Test name
Test status
Simulation time 100257796 ps
CPU time 0.89 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:37 PM PDT 24
Peak memory 196636 kb
Host smart-4caf97f8-451b-4db0-978c-a64b3e48dd14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521179472 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2521179472
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.76234814
Short name T79
Test name
Test status
Simulation time 11485426 ps
CPU time 0.54 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:36 PM PDT 24
Peak memory 182240 kb
Host smart-8b2d4ec0-c7e2-41f4-b69b-50cc499538d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76234814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.76234814
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3904529989
Short name T487
Test name
Test status
Simulation time 16375232 ps
CPU time 0.56 seconds
Started Jun 30 04:51:36 PM PDT 24
Finished Jun 30 04:51:38 PM PDT 24
Peak memory 182132 kb
Host smart-04c18a3e-7973-411d-b246-88eff10b8764
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904529989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3904529989
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2499095706
Short name T581
Test name
Test status
Simulation time 195405814 ps
CPU time 0.82 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:36 PM PDT 24
Peak memory 193068 kb
Host smart-7bcb9978-624d-48d9-8a75-3ac49a132dec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499095706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2499095706
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3594014714
Short name T551
Test name
Test status
Simulation time 304185628 ps
CPU time 1.46 seconds
Started Jun 30 04:51:34 PM PDT 24
Finished Jun 30 04:51:36 PM PDT 24
Peak memory 196964 kb
Host smart-b8754baf-c76d-4c1f-96b4-b1a85d26ce28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594014714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3594014714
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1228959706
Short name T541
Test name
Test status
Simulation time 108435921 ps
CPU time 0.84 seconds
Started Jun 30 04:51:36 PM PDT 24
Finished Jun 30 04:51:38 PM PDT 24
Peak memory 192664 kb
Host smart-bedeeb86-74ed-4c04-92ca-d20a7236583f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228959706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1228959706
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2884720618
Short name T557
Test name
Test status
Simulation time 41567781 ps
CPU time 0.72 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:36 PM PDT 24
Peak memory 194488 kb
Host smart-c493da59-af21-499d-8b7b-20b5723333a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884720618 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2884720618
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2310826610
Short name T77
Test name
Test status
Simulation time 42238070 ps
CPU time 0.57 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:37 PM PDT 24
Peak memory 182252 kb
Host smart-652b2435-8492-4275-9f05-d71c584aa713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310826610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2310826610
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.711027946
Short name T458
Test name
Test status
Simulation time 23651587 ps
CPU time 0.53 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:37 PM PDT 24
Peak memory 182132 kb
Host smart-74faccbe-390b-4b9a-be96-44dad46a7146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711027946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.711027946
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3654583379
Short name T558
Test name
Test status
Simulation time 119337974 ps
CPU time 0.72 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:36 PM PDT 24
Peak memory 192948 kb
Host smart-6d5095c7-aade-4aab-8009-e80ecfbd498b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654583379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3654583379
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3543688270
Short name T508
Test name
Test status
Simulation time 185849167 ps
CPU time 1.16 seconds
Started Jun 30 04:51:36 PM PDT 24
Finished Jun 30 04:51:38 PM PDT 24
Peak memory 196944 kb
Host smart-336d796f-0ebd-448d-afdd-3af3fb7b8bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543688270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3543688270
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.730977537
Short name T88
Test name
Test status
Simulation time 1386045903 ps
CPU time 1.29 seconds
Started Jun 30 04:51:37 PM PDT 24
Finished Jun 30 04:51:39 PM PDT 24
Peak memory 194924 kb
Host smart-04ac6a84-2639-4135-b570-761c1c182cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730977537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.730977537
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.488410147
Short name T507
Test name
Test status
Simulation time 29956218 ps
CPU time 0.77 seconds
Started Jun 30 04:51:57 PM PDT 24
Finished Jun 30 04:51:59 PM PDT 24
Peak memory 194056 kb
Host smart-174b593b-8556-4b44-a63d-8a8882ab2a59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488410147 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.488410147
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.469933635
Short name T68
Test name
Test status
Simulation time 13196062 ps
CPU time 0.57 seconds
Started Jun 30 04:51:36 PM PDT 24
Finished Jun 30 04:51:38 PM PDT 24
Peak memory 182544 kb
Host smart-98484b87-0da0-4ebf-ba0b-18006e886ed5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469933635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.469933635
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.353126865
Short name T582
Test name
Test status
Simulation time 58323677 ps
CPU time 0.59 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:37 PM PDT 24
Peak memory 182124 kb
Host smart-301955ba-c736-4880-be93-2b716b4f7fae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353126865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.353126865
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2407365830
Short name T84
Test name
Test status
Simulation time 112859255 ps
CPU time 0.74 seconds
Started Jun 30 04:51:57 PM PDT 24
Finished Jun 30 04:51:59 PM PDT 24
Peak memory 192940 kb
Host smart-0210f2bd-5adb-448a-b877-700653320436
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407365830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2407365830
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1540363490
Short name T575
Test name
Test status
Simulation time 855022277 ps
CPU time 2.72 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:39 PM PDT 24
Peak memory 196928 kb
Host smart-cdc4d558-1c06-4a5b-bfd5-62c93beeeb69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540363490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1540363490
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1422127193
Short name T570
Test name
Test status
Simulation time 193280927 ps
CPU time 1.3 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:37 PM PDT 24
Peak memory 194880 kb
Host smart-d6690188-28aa-4832-8048-c8aac7b04235
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422127193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1422127193
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3327281011
Short name T466
Test name
Test status
Simulation time 126790360 ps
CPU time 1.57 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:58 PM PDT 24
Peak memory 197028 kb
Host smart-9b0dee62-f610-4eac-94cb-6e07c60959a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327281011 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3327281011
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1358636465
Short name T470
Test name
Test status
Simulation time 55520310 ps
CPU time 0.59 seconds
Started Jun 30 04:51:55 PM PDT 24
Finished Jun 30 04:51:56 PM PDT 24
Peak memory 182228 kb
Host smart-8665f79c-4a59-4e2c-ac87-e5ec5d0a0a70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358636465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1358636465
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1570677825
Short name T585
Test name
Test status
Simulation time 29085999 ps
CPU time 0.58 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:58 PM PDT 24
Peak memory 182196 kb
Host smart-0db558b1-2c13-413a-bb52-0a50478a2f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570677825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1570677825
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2494407264
Short name T82
Test name
Test status
Simulation time 22140167 ps
CPU time 0.61 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:57 PM PDT 24
Peak memory 191456 kb
Host smart-4d8a980f-85a1-4029-82dc-31f7510f3a3b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494407264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2494407264
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3456804945
Short name T566
Test name
Test status
Simulation time 131612624 ps
CPU time 1.92 seconds
Started Jun 30 04:51:55 PM PDT 24
Finished Jun 30 04:51:57 PM PDT 24
Peak memory 197024 kb
Host smart-fe7b257c-28e5-462a-b4ff-b8e04014a94d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456804945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3456804945
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.997231313
Short name T513
Test name
Test status
Simulation time 77896881 ps
CPU time 1.06 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:58 PM PDT 24
Peak memory 193696 kb
Host smart-cfd12914-3316-48bf-a091-a965755805e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997231313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.997231313
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.879889519
Short name T516
Test name
Test status
Simulation time 25504040 ps
CPU time 0.8 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:57 PM PDT 24
Peak memory 195052 kb
Host smart-e26a5afc-a4df-4370-8f95-e9d298227522
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879889519 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.879889519
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1982505499
Short name T492
Test name
Test status
Simulation time 21914875 ps
CPU time 0.56 seconds
Started Jun 30 04:51:55 PM PDT 24
Finished Jun 30 04:51:56 PM PDT 24
Peak memory 182052 kb
Host smart-c7936a72-0763-4d72-b264-93a1d6edebd7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982505499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1982505499
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2218141182
Short name T538
Test name
Test status
Simulation time 15602841 ps
CPU time 0.59 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:58 PM PDT 24
Peak memory 181812 kb
Host smart-1f142b4c-7c6f-4d6e-ab66-ad309b738db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218141182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2218141182
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4102508845
Short name T483
Test name
Test status
Simulation time 19059575 ps
CPU time 0.72 seconds
Started Jun 30 04:51:55 PM PDT 24
Finished Jun 30 04:51:57 PM PDT 24
Peak memory 192856 kb
Host smart-d95babe7-661b-4a2a-953e-a0a29396ef90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102508845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.4102508845
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.182727665
Short name T577
Test name
Test status
Simulation time 88139791 ps
CPU time 1.18 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:58 PM PDT 24
Peak memory 197044 kb
Host smart-2ca51a20-a465-4837-b242-32956894946b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182727665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.182727665
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2910728933
Short name T517
Test name
Test status
Simulation time 153438431 ps
CPU time 1.27 seconds
Started Jun 30 04:51:55 PM PDT 24
Finished Jun 30 04:51:57 PM PDT 24
Peak memory 194776 kb
Host smart-9dcdecc8-d446-4b94-abda-24818cb8a5fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910728933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2910728933
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.4119571017
Short name T499
Test name
Test status
Simulation time 28438607 ps
CPU time 0.83 seconds
Started Jun 30 04:51:57 PM PDT 24
Finished Jun 30 04:51:59 PM PDT 24
Peak memory 194904 kb
Host smart-a72103bf-8f0b-41be-8a1f-c1bfbe47086f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119571017 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.4119571017
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.667850434
Short name T481
Test name
Test status
Simulation time 52267631 ps
CPU time 0.59 seconds
Started Jun 30 04:51:57 PM PDT 24
Finished Jun 30 04:51:58 PM PDT 24
Peak memory 182176 kb
Host smart-317c179a-a54d-483f-95e6-b111d234f300
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667850434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.667850434
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1265727586
Short name T471
Test name
Test status
Simulation time 18061020 ps
CPU time 0.57 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:58 PM PDT 24
Peak memory 182024 kb
Host smart-ad7d0d73-914c-4ea7-9534-6ceab2c11c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265727586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1265727586
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2324721803
Short name T80
Test name
Test status
Simulation time 17191953 ps
CPU time 0.73 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:57 PM PDT 24
Peak memory 192868 kb
Host smart-f1a84f09-f138-44ff-bb8b-adab34030727
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324721803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2324721803
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.741764318
Short name T571
Test name
Test status
Simulation time 131426272 ps
CPU time 2.15 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:59 PM PDT 24
Peak memory 197080 kb
Host smart-15185276-204b-4d5b-beb5-1ef22f504095
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741764318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.741764318
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.717130460
Short name T48
Test name
Test status
Simulation time 84940752 ps
CPU time 1.15 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:58 PM PDT 24
Peak memory 194788 kb
Host smart-7ccdd9ff-2f28-4110-a8a2-2dd6e25c0e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717130460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.717130460
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1920274921
Short name T556
Test name
Test status
Simulation time 20034147 ps
CPU time 0.69 seconds
Started Jun 30 04:51:54 PM PDT 24
Finished Jun 30 04:51:55 PM PDT 24
Peak memory 194076 kb
Host smart-37511448-c5fe-4a1c-b34c-ab1b0d9d0677
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920274921 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1920274921
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.973225623
Short name T73
Test name
Test status
Simulation time 12750363 ps
CPU time 0.56 seconds
Started Jun 30 04:51:57 PM PDT 24
Finished Jun 30 04:51:59 PM PDT 24
Peak memory 181708 kb
Host smart-7b888483-d43d-49f4-8d40-69d2f569563d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973225623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.973225623
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.1269754440
Short name T498
Test name
Test status
Simulation time 20232593 ps
CPU time 0.55 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:57 PM PDT 24
Peak memory 181720 kb
Host smart-35fbfb8c-c083-405c-a9ac-d6d532a50371
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269754440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.1269754440
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1485913276
Short name T81
Test name
Test status
Simulation time 24519991 ps
CPU time 0.67 seconds
Started Jun 30 04:51:55 PM PDT 24
Finished Jun 30 04:51:57 PM PDT 24
Peak memory 191092 kb
Host smart-cb5a3ad9-945a-4a6d-be22-96cd405cb5e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485913276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1485913276
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3357427549
Short name T482
Test name
Test status
Simulation time 702972349 ps
CPU time 3.15 seconds
Started Jun 30 04:51:55 PM PDT 24
Finished Jun 30 04:51:59 PM PDT 24
Peak memory 197044 kb
Host smart-7bb3c4bb-a2f0-4172-8684-216d0ae82de4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357427549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3357427549
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2841411449
Short name T26
Test name
Test status
Simulation time 472987720 ps
CPU time 1.33 seconds
Started Jun 30 04:51:54 PM PDT 24
Finished Jun 30 04:51:56 PM PDT 24
Peak memory 194336 kb
Host smart-d85ebf26-7cbf-49b1-b1cf-03c9defae34c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841411449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2841411449
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3542860902
Short name T522
Test name
Test status
Simulation time 100536390 ps
CPU time 0.77 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:52:12 PM PDT 24
Peak memory 194624 kb
Host smart-f37947f7-5981-4ce9-9fc4-8208e9a20db8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542860902 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3542860902
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1900539813
Short name T71
Test name
Test status
Simulation time 22158653 ps
CPU time 0.6 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 04:52:09 PM PDT 24
Peak memory 182540 kb
Host smart-63de017e-606f-49ea-95e0-2311905cf643
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900539813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1900539813
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1696898937
Short name T552
Test name
Test status
Simulation time 42547231 ps
CPU time 0.51 seconds
Started Jun 30 04:51:54 PM PDT 24
Finished Jun 30 04:51:56 PM PDT 24
Peak memory 181612 kb
Host smart-1a1607c6-9c54-4671-b58c-52932ed8e9d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696898937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1696898937
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3490877539
Short name T63
Test name
Test status
Simulation time 111188786 ps
CPU time 0.69 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:52:13 PM PDT 24
Peak memory 191568 kb
Host smart-80d39a39-2581-42e2-b6df-0ae25ee121b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490877539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3490877539
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3031041676
Short name T528
Test name
Test status
Simulation time 774267593 ps
CPU time 1.43 seconds
Started Jun 30 04:51:56 PM PDT 24
Finished Jun 30 04:51:59 PM PDT 24
Peak memory 197044 kb
Host smart-3e4a74a8-199b-431d-b1bf-29c7d2c5990d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031041676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3031041676
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3153755791
Short name T555
Test name
Test status
Simulation time 147364531 ps
CPU time 1.36 seconds
Started Jun 30 04:51:57 PM PDT 24
Finished Jun 30 04:51:59 PM PDT 24
Peak memory 195076 kb
Host smart-f10783e3-6fd3-4e04-a5c7-5d98d253660a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153755791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3153755791
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2220429642
Short name T535
Test name
Test status
Simulation time 48676316 ps
CPU time 1.27 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:52:11 PM PDT 24
Peak memory 197332 kb
Host smart-e41dfec3-5f6d-443b-9097-f7bdd15f47f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220429642 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2220429642
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.186743726
Short name T72
Test name
Test status
Simulation time 11795682 ps
CPU time 0.6 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:52:11 PM PDT 24
Peak memory 182520 kb
Host smart-a25f9a67-0016-4187-8653-fdb306afb40e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186743726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.186743726
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3896340233
Short name T530
Test name
Test status
Simulation time 29592378 ps
CPU time 0.52 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 04:52:08 PM PDT 24
Peak memory 181812 kb
Host smart-61efb5c9-7542-44dd-9853-7e59aeea6e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896340233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3896340233
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.2987682898
Short name T578
Test name
Test status
Simulation time 27309974 ps
CPU time 0.76 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:07 PM PDT 24
Peak memory 193588 kb
Host smart-18d0dd7b-5b0e-41fe-ac08-f7776596de20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987682898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.2987682898
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3727019283
Short name T567
Test name
Test status
Simulation time 36549254 ps
CPU time 1.08 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:52:12 PM PDT 24
Peak memory 195996 kb
Host smart-d15c8a5c-fe47-44d9-892e-41b04fd19f2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727019283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3727019283
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2129294443
Short name T510
Test name
Test status
Simulation time 83190531 ps
CPU time 1.08 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:52:11 PM PDT 24
Peak memory 182868 kb
Host smart-e9f3815a-ef2e-4e5a-a6a5-c8ab85ef9d7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129294443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2129294443
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3254673489
Short name T485
Test name
Test status
Simulation time 71939195 ps
CPU time 0.85 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:52:13 PM PDT 24
Peak memory 196868 kb
Host smart-311fabb1-2a5c-4220-ae9a-54becb520ceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254673489 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3254673489
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1060471556
Short name T67
Test name
Test status
Simulation time 24512321 ps
CPU time 0.55 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:52:11 PM PDT 24
Peak memory 182140 kb
Host smart-d8085140-1b39-4deb-88c6-5765da226728
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060471556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1060471556
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3361020744
Short name T562
Test name
Test status
Simulation time 26749107 ps
CPU time 0.57 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:52:11 PM PDT 24
Peak memory 182156 kb
Host smart-df089f5d-716b-4cd2-af7e-5c13a169dfdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361020744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3361020744
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3411904803
Short name T560
Test name
Test status
Simulation time 78077687 ps
CPU time 0.69 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:07 PM PDT 24
Peak memory 191040 kb
Host smart-d47710ad-c0bf-47f4-ad0c-5eee69f24b56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411904803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3411904803
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.513893921
Short name T460
Test name
Test status
Simulation time 183255931 ps
CPU time 1.89 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 04:52:10 PM PDT 24
Peak memory 197048 kb
Host smart-ec11bdf0-632c-43f2-9dea-80a2420583b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513893921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.513893921
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2860502272
Short name T534
Test name
Test status
Simulation time 33547787 ps
CPU time 0.84 seconds
Started Jun 30 04:51:23 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 192552 kb
Host smart-01402a69-c8f1-4f5d-8686-87c414b2acb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860502272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2860502272
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1696882144
Short name T515
Test name
Test status
Simulation time 562771078 ps
CPU time 3.42 seconds
Started Jun 30 04:51:18 PM PDT 24
Finished Jun 30 04:51:22 PM PDT 24
Peak memory 191796 kb
Host smart-39591107-5562-40f1-a2e2-13e50254e368
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696882144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1696882144
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1665886968
Short name T559
Test name
Test status
Simulation time 15873434 ps
CPU time 0.57 seconds
Started Jun 30 04:51:24 PM PDT 24
Finished Jun 30 04:51:25 PM PDT 24
Peak memory 182176 kb
Host smart-41b69a5d-fb7c-4cf5-a2c2-7c42fb8ee767
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665886968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1665886968
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2652288780
Short name T473
Test name
Test status
Simulation time 30824261 ps
CPU time 0.81 seconds
Started Jun 30 04:51:19 PM PDT 24
Finished Jun 30 04:51:21 PM PDT 24
Peak memory 196056 kb
Host smart-d9ba8269-d70b-42f7-a2fc-c415bf198c2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652288780 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2652288780
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.85941225
Short name T69
Test name
Test status
Simulation time 43038566 ps
CPU time 0.55 seconds
Started Jun 30 04:51:21 PM PDT 24
Finished Jun 30 04:51:22 PM PDT 24
Peak memory 182228 kb
Host smart-9d04f206-b891-4d69-8c64-df9683f3b086
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85941225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.85941225
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2302684933
Short name T509
Test name
Test status
Simulation time 12214609 ps
CPU time 0.54 seconds
Started Jun 30 04:51:23 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 181836 kb
Host smart-605cce9f-ac67-4601-88f3-84c17ca1db95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302684933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2302684933
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3444137930
Short name T548
Test name
Test status
Simulation time 129429356 ps
CPU time 0.79 seconds
Started Jun 30 04:51:21 PM PDT 24
Finished Jun 30 04:51:22 PM PDT 24
Peak memory 193036 kb
Host smart-aebd2d7f-6777-419e-b0f4-a8887bb14edc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444137930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3444137930
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1581243978
Short name T49
Test name
Test status
Simulation time 454286574 ps
CPU time 1.6 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 196916 kb
Host smart-7adeff97-d7b8-4f9a-b603-30897e2c3b59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581243978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1581243978
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.744168793
Short name T537
Test name
Test status
Simulation time 824621976 ps
CPU time 0.82 seconds
Started Jun 30 04:51:20 PM PDT 24
Finished Jun 30 04:51:22 PM PDT 24
Peak memory 182552 kb
Host smart-d364c367-81bd-4ba6-983b-cf7ff0e9d96b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744168793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.744168793
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.879883719
Short name T553
Test name
Test status
Simulation time 43828731 ps
CPU time 0.56 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 04:52:09 PM PDT 24
Peak memory 182092 kb
Host smart-eb99bde2-17a4-4ea3-8655-0fd63ad84d1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879883719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.879883719
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2679369210
Short name T583
Test name
Test status
Simulation time 117356277 ps
CPU time 0.56 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:08 PM PDT 24
Peak memory 182152 kb
Host smart-a7d99478-4217-4676-a0ca-1da05aaaf45e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679369210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2679369210
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1667160656
Short name T478
Test name
Test status
Simulation time 69056464 ps
CPU time 0.54 seconds
Started Jun 30 04:52:05 PM PDT 24
Finished Jun 30 04:52:06 PM PDT 24
Peak memory 181556 kb
Host smart-ea6c9396-6c39-4a2d-b905-eeaede44463e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667160656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1667160656
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2584411437
Short name T518
Test name
Test status
Simulation time 12557307 ps
CPU time 0.54 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 04:52:16 PM PDT 24
Peak memory 181604 kb
Host smart-ec6abbeb-c6ed-46c8-8d6a-299a4895f5e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584411437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2584411437
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1756634881
Short name T477
Test name
Test status
Simulation time 16182946 ps
CPU time 0.54 seconds
Started Jun 30 04:52:05 PM PDT 24
Finished Jun 30 04:52:06 PM PDT 24
Peak memory 182136 kb
Host smart-3dbd5090-fb8a-496d-91f3-6efbb982228d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756634881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1756634881
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.410639437
Short name T542
Test name
Test status
Simulation time 14044478 ps
CPU time 0.59 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:52:10 PM PDT 24
Peak memory 182168 kb
Host smart-827ff851-403c-47bd-890a-227fb45c8b51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410639437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.410639437
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1582842369
Short name T504
Test name
Test status
Simulation time 23466750 ps
CPU time 0.55 seconds
Started Jun 30 04:52:04 PM PDT 24
Finished Jun 30 04:52:04 PM PDT 24
Peak memory 182096 kb
Host smart-65fb60d9-adaa-4c0d-9121-69fe7941b60a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582842369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1582842369
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1788872234
Short name T584
Test name
Test status
Simulation time 10638772 ps
CPU time 0.55 seconds
Started Jun 30 04:52:12 PM PDT 24
Finished Jun 30 04:52:14 PM PDT 24
Peak memory 182096 kb
Host smart-9eedd201-97ad-4bca-8695-cd5eadc058c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788872234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1788872234
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.559957016
Short name T573
Test name
Test status
Simulation time 160817061 ps
CPU time 0.56 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:52:13 PM PDT 24
Peak memory 182028 kb
Host smart-dc1b2f13-4eef-4252-9844-7916876ca6f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559957016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.559957016
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3081297501
Short name T563
Test name
Test status
Simulation time 63127802 ps
CPU time 0.58 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:08 PM PDT 24
Peak memory 181812 kb
Host smart-64bb1719-7b7f-4f6e-98e5-9116687759d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081297501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3081297501
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2191390923
Short name T532
Test name
Test status
Simulation time 338928506 ps
CPU time 0.79 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 182180 kb
Host smart-549ce5e2-1962-4883-a2f9-f0870643ca7e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191390923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2191390923
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.893434389
Short name T539
Test name
Test status
Simulation time 391911079 ps
CPU time 2.48 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:31 PM PDT 24
Peak memory 190540 kb
Host smart-785a6f77-34f4-4ab3-936a-960627dab971
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893434389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.893434389
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2146300747
Short name T533
Test name
Test status
Simulation time 18130297 ps
CPU time 0.56 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:29 PM PDT 24
Peak memory 182144 kb
Host smart-a3982d65-7fac-4f4f-9c90-b4fcb443952f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146300747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2146300747
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4000204443
Short name T465
Test name
Test status
Simulation time 20167469 ps
CPU time 1.02 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 196900 kb
Host smart-e298edfa-9b44-4ddb-9c3b-148e1040b324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000204443 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.4000204443
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2375439983
Short name T545
Test name
Test status
Simulation time 25261531 ps
CPU time 0.59 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 182232 kb
Host smart-63995387-397c-4a5f-b47b-4c633350047e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375439983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2375439983
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.202335977
Short name T456
Test name
Test status
Simulation time 37669078 ps
CPU time 0.53 seconds
Started Jun 30 04:51:22 PM PDT 24
Finished Jun 30 04:51:23 PM PDT 24
Peak memory 181616 kb
Host smart-c3011d33-acea-4570-9279-20cf1a0d4459
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202335977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.202335977
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3668590417
Short name T554
Test name
Test status
Simulation time 135956392 ps
CPU time 0.75 seconds
Started Jun 30 04:51:31 PM PDT 24
Finished Jun 30 04:51:32 PM PDT 24
Peak memory 192848 kb
Host smart-6160eedd-3815-49a4-84cb-3336f29318ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668590417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3668590417
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1341985121
Short name T579
Test name
Test status
Simulation time 445459616 ps
CPU time 2.26 seconds
Started Jun 30 04:51:21 PM PDT 24
Finished Jun 30 04:51:24 PM PDT 24
Peak memory 197044 kb
Host smart-19f6223f-b4ac-46d5-bb8c-c1b3d1981884
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341985121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1341985121
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1940128660
Short name T568
Test name
Test status
Simulation time 649600941 ps
CPU time 0.78 seconds
Started Jun 30 04:51:20 PM PDT 24
Finished Jun 30 04:51:22 PM PDT 24
Peak memory 192900 kb
Host smart-60b140a2-1c30-43be-af75-b46a11ef33c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940128660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1940128660
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.532286776
Short name T505
Test name
Test status
Simulation time 11803052 ps
CPU time 0.56 seconds
Started Jun 30 04:52:05 PM PDT 24
Finished Jun 30 04:52:06 PM PDT 24
Peak memory 182092 kb
Host smart-c4ae6352-2783-493c-93b0-7c249cb1f1f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532286776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.532286776
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1674525901
Short name T576
Test name
Test status
Simulation time 49128693 ps
CPU time 0.53 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:08 PM PDT 24
Peak memory 181592 kb
Host smart-91652b28-d21d-4e0c-854b-1dca37344aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674525901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1674525901
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.766119161
Short name T461
Test name
Test status
Simulation time 11024143 ps
CPU time 0.52 seconds
Started Jun 30 04:52:04 PM PDT 24
Finished Jun 30 04:52:05 PM PDT 24
Peak memory 181540 kb
Host smart-f6b7b12a-3340-4820-835a-e7957739ba4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766119161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.766119161
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3534483733
Short name T574
Test name
Test status
Simulation time 94470436 ps
CPU time 0.55 seconds
Started Jun 30 04:52:03 PM PDT 24
Finished Jun 30 04:52:04 PM PDT 24
Peak memory 181524 kb
Host smart-03c44d3a-05ab-4993-9ac5-48cc6b560269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534483733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3534483733
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2915641418
Short name T529
Test name
Test status
Simulation time 14397036 ps
CPU time 0.54 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:52:12 PM PDT 24
Peak memory 181840 kb
Host smart-1c037b2f-87ab-42ad-b8a8-ad40313a0f39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915641418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2915641418
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.24069773
Short name T462
Test name
Test status
Simulation time 13326768 ps
CPU time 0.56 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:07 PM PDT 24
Peak memory 182116 kb
Host smart-49fc637e-7491-4185-a5ff-ffc4dd61ed6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24069773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.24069773
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.744335992
Short name T580
Test name
Test status
Simulation time 75199001 ps
CPU time 0.51 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:08 PM PDT 24
Peak memory 181616 kb
Host smart-e1725990-23c9-4440-aa41-3e4854739f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744335992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.744335992
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2209143529
Short name T536
Test name
Test status
Simulation time 79328538 ps
CPU time 0.55 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:52:10 PM PDT 24
Peak memory 181608 kb
Host smart-5bfe0857-c6a1-4fd9-a546-3ed4f0f804a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209143529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2209143529
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4103220704
Short name T480
Test name
Test status
Simulation time 38457875 ps
CPU time 0.58 seconds
Started Jun 30 04:52:05 PM PDT 24
Finished Jun 30 04:52:06 PM PDT 24
Peak memory 182124 kb
Host smart-b99f99d7-0979-423d-a2c2-4e5938f825f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103220704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4103220704
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.914669793
Short name T457
Test name
Test status
Simulation time 37685982 ps
CPU time 0.61 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:52:12 PM PDT 24
Peak memory 182172 kb
Host smart-960e993e-abe1-4c74-9653-e45732c2bb7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914669793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.914669793
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.49723109
Short name T75
Test name
Test status
Simulation time 29574963 ps
CPU time 0.73 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 191476 kb
Host smart-9d20c913-0a51-4e10-9a8a-d2d4b195c44e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49723109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasi
ng.49723109
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1594995739
Short name T527
Test name
Test status
Simulation time 773657252 ps
CPU time 2.42 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:32 PM PDT 24
Peak memory 193332 kb
Host smart-3c5aa5d5-38b8-4db2-a774-faef41ff56c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594995739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1594995739
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.518232461
Short name T65
Test name
Test status
Simulation time 35384914 ps
CPU time 0.59 seconds
Started Jun 30 04:51:29 PM PDT 24
Finished Jun 30 04:51:31 PM PDT 24
Peak memory 191440 kb
Host smart-67465edd-31c6-4eb6-bb84-8928a3064eda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518232461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.518232461
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.237400183
Short name T525
Test name
Test status
Simulation time 51872374 ps
CPU time 0.61 seconds
Started Jun 30 04:51:29 PM PDT 24
Finished Jun 30 04:51:31 PM PDT 24
Peak memory 193104 kb
Host smart-2d71431b-6eec-459a-ac88-ab29ab237338
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237400183 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.237400183
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3809417338
Short name T586
Test name
Test status
Simulation time 20242476 ps
CPU time 0.55 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:29 PM PDT 24
Peak memory 182424 kb
Host smart-bf1f0f66-bdc2-41a5-a2e1-b14c5b4810e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809417338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3809417338
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2856723349
Short name T547
Test name
Test status
Simulation time 40342902 ps
CPU time 0.55 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 182128 kb
Host smart-f019af8d-9560-49c5-9f72-dad1536e28a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856723349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2856723349
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1387442600
Short name T83
Test name
Test status
Simulation time 71614456 ps
CPU time 0.75 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 192796 kb
Host smart-4d0ad2c4-1cc5-4aec-b04e-d7076585915b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387442600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1387442600
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3239557713
Short name T544
Test name
Test status
Simulation time 570548294 ps
CPU time 2.95 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:32 PM PDT 24
Peak memory 196848 kb
Host smart-f66e7d95-5828-406b-a0d1-3523b8afda6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239557713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3239557713
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2362267877
Short name T561
Test name
Test status
Simulation time 83798793 ps
CPU time 1.08 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 194552 kb
Host smart-ad105d37-1d07-490e-a3cd-527a5092540c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362267877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2362267877
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.983557709
Short name T572
Test name
Test status
Simulation time 18455925 ps
CPU time 0.56 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:08 PM PDT 24
Peak memory 182176 kb
Host smart-ab1deef4-98f6-46e5-a8d4-a8bfe4be43f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983557709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.983557709
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3685727846
Short name T484
Test name
Test status
Simulation time 43538700 ps
CPU time 0.53 seconds
Started Jun 30 04:52:05 PM PDT 24
Finished Jun 30 04:52:06 PM PDT 24
Peak memory 181812 kb
Host smart-353d1c8e-8ebc-4301-8712-11e6fb2eecfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685727846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3685727846
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3610833816
Short name T459
Test name
Test status
Simulation time 16737047 ps
CPU time 0.54 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:07 PM PDT 24
Peak memory 182120 kb
Host smart-707fbc42-7419-44e5-b581-728939a6bfa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610833816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3610833816
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1882594031
Short name T512
Test name
Test status
Simulation time 29240362 ps
CPU time 0.63 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 04:52:16 PM PDT 24
Peak memory 182148 kb
Host smart-8d98a368-abc6-4317-973f-581e8379eb03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882594031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1882594031
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.40350680
Short name T511
Test name
Test status
Simulation time 34911060 ps
CPU time 0.57 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:52:12 PM PDT 24
Peak memory 181880 kb
Host smart-095073fd-ef9a-4868-9fb8-fdd1af5fcde8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40350680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.40350680
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3055500000
Short name T519
Test name
Test status
Simulation time 19353828 ps
CPU time 0.64 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:08 PM PDT 24
Peak memory 182168 kb
Host smart-550fbd0f-bae8-49c9-b67e-78478fcc62aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055500000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3055500000
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.395331669
Short name T523
Test name
Test status
Simulation time 14442339 ps
CPU time 0.54 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 04:52:08 PM PDT 24
Peak memory 181788 kb
Host smart-6c92d46a-7f97-42c1-b8f5-248a567e578b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395331669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.395331669
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3595190635
Short name T494
Test name
Test status
Simulation time 13192435 ps
CPU time 0.56 seconds
Started Jun 30 04:52:05 PM PDT 24
Finished Jun 30 04:52:06 PM PDT 24
Peak memory 182040 kb
Host smart-e0615723-bc0a-4484-84c9-99e037c5f8b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595190635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3595190635
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.807483044
Short name T543
Test name
Test status
Simulation time 74693016 ps
CPU time 0.51 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:52:11 PM PDT 24
Peak memory 181724 kb
Host smart-643a8dae-c23b-4b98-95fa-d86324485758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807483044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.807483044
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3907275080
Short name T495
Test name
Test status
Simulation time 18336325 ps
CPU time 0.57 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:52:11 PM PDT 24
Peak memory 182024 kb
Host smart-ad2d83f2-5524-482b-b2b7-a93a60e7f708
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907275080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3907275080
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3381957325
Short name T565
Test name
Test status
Simulation time 146318491 ps
CPU time 0.85 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 196608 kb
Host smart-9ef84be9-74ba-4bdf-8a12-7137d475e160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381957325 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3381957325
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3589647473
Short name T76
Test name
Test status
Simulation time 57164287 ps
CPU time 0.59 seconds
Started Jun 30 04:51:29 PM PDT 24
Finished Jun 30 04:51:31 PM PDT 24
Peak memory 182220 kb
Host smart-c0b389cb-172b-422d-aeb9-ef8aaab1eea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589647473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3589647473
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1254860121
Short name T496
Test name
Test status
Simulation time 18135915 ps
CPU time 0.55 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 182156 kb
Host smart-d8e5fc98-f53f-4487-8810-5de46b2bd627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254860121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1254860121
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1693824273
Short name T540
Test name
Test status
Simulation time 517406547 ps
CPU time 0.77 seconds
Started Jun 30 04:51:32 PM PDT 24
Finished Jun 30 04:51:33 PM PDT 24
Peak memory 192852 kb
Host smart-697b5494-2040-4af8-9361-c215be2e3a65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693824273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1693824273
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4057956588
Short name T476
Test name
Test status
Simulation time 44329854 ps
CPU time 2 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:32 PM PDT 24
Peak memory 197052 kb
Host smart-8a322352-fb81-44c0-9b5d-b0a4e48da637
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057956588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4057956588
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3475980538
Short name T87
Test name
Test status
Simulation time 177499184 ps
CPU time 0.85 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:29 PM PDT 24
Peak memory 193160 kb
Host smart-b61eddbe-d8c9-4119-bb55-1b31f29cbe70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475980538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3475980538
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3796201072
Short name T474
Test name
Test status
Simulation time 98498802 ps
CPU time 0.68 seconds
Started Jun 30 04:51:26 PM PDT 24
Finished Jun 30 04:51:27 PM PDT 24
Peak memory 194232 kb
Host smart-39d08a2d-8882-4d2c-996b-c2de56c2b337
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796201072 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3796201072
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.957754938
Short name T521
Test name
Test status
Simulation time 60421795 ps
CPU time 0.64 seconds
Started Jun 30 04:51:30 PM PDT 24
Finished Jun 30 04:51:31 PM PDT 24
Peak memory 182228 kb
Host smart-a8b256d5-d611-475b-9480-54055d08643a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957754938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.957754938
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2463417293
Short name T501
Test name
Test status
Simulation time 20468416 ps
CPU time 0.53 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 181620 kb
Host smart-367f40ac-27f3-413b-958b-bd73892eee50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463417293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2463417293
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2832781129
Short name T503
Test name
Test status
Simulation time 77945880 ps
CPU time 0.83 seconds
Started Jun 30 04:51:30 PM PDT 24
Finished Jun 30 04:51:31 PM PDT 24
Peak memory 191124 kb
Host smart-19a54205-ac9f-4782-af61-087b7dc6c92e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832781129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2832781129
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.449488958
Short name T463
Test name
Test status
Simulation time 96764195 ps
CPU time 1.31 seconds
Started Jun 30 04:51:29 PM PDT 24
Finished Jun 30 04:51:32 PM PDT 24
Peak memory 196984 kb
Host smart-6bcfbc41-12d4-45d3-a6c6-f1d1bd023aee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449488958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.449488958
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.297970594
Short name T27
Test name
Test status
Simulation time 161190177 ps
CPU time 0.8 seconds
Started Jun 30 04:51:29 PM PDT 24
Finished Jun 30 04:51:31 PM PDT 24
Peak memory 193008 kb
Host smart-f6a5b63c-7327-42d9-8f59-555225f69430
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297970594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.297970594
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1413700176
Short name T550
Test name
Test status
Simulation time 128783976 ps
CPU time 0.72 seconds
Started Jun 30 04:51:36 PM PDT 24
Finished Jun 30 04:51:37 PM PDT 24
Peak memory 193980 kb
Host smart-a65b637e-facb-4b28-8408-64e51dc59150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413700176 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1413700176
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1107064377
Short name T62
Test name
Test status
Simulation time 19364385 ps
CPU time 0.57 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 182264 kb
Host smart-3067f8cf-2bd4-4ae4-bf88-d0f4e99b22c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107064377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1107064377
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3704493472
Short name T490
Test name
Test status
Simulation time 18186931 ps
CPU time 0.54 seconds
Started Jun 30 04:51:27 PM PDT 24
Finished Jun 30 04:51:28 PM PDT 24
Peak memory 182048 kb
Host smart-5ba0ebf3-5e9d-4508-a60d-b3fa7ecfe636
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704493472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3704493472
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3170926314
Short name T531
Test name
Test status
Simulation time 17972580 ps
CPU time 0.63 seconds
Started Jun 30 04:51:33 PM PDT 24
Finished Jun 30 04:51:34 PM PDT 24
Peak memory 191016 kb
Host smart-017da22f-8b42-4ff7-a374-938b4ea60ed7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170926314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3170926314
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2710754993
Short name T475
Test name
Test status
Simulation time 54289918 ps
CPU time 1.22 seconds
Started Jun 30 04:51:28 PM PDT 24
Finished Jun 30 04:51:30 PM PDT 24
Peak memory 196992 kb
Host smart-a54750cd-e985-48fb-816b-ec71f9731ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710754993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2710754993
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1955065986
Short name T86
Test name
Test status
Simulation time 613280210 ps
CPU time 1.13 seconds
Started Jun 30 04:51:32 PM PDT 24
Finished Jun 30 04:51:34 PM PDT 24
Peak memory 194624 kb
Host smart-b184efeb-3313-4fe8-9106-4f4035a41be8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955065986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1955065986
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1958931716
Short name T564
Test name
Test status
Simulation time 74731482 ps
CPU time 1.01 seconds
Started Jun 30 04:51:33 PM PDT 24
Finished Jun 30 04:51:35 PM PDT 24
Peak memory 196904 kb
Host smart-4d5dd68a-96fc-4351-869b-b6c2dc61762c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958931716 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1958931716
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.4283427659
Short name T526
Test name
Test status
Simulation time 14490689 ps
CPU time 0.54 seconds
Started Jun 30 04:51:33 PM PDT 24
Finished Jun 30 04:51:34 PM PDT 24
Peak memory 182232 kb
Host smart-0ac18872-aace-4834-a283-734345bfbe2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283427659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.4283427659
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2902389361
Short name T524
Test name
Test status
Simulation time 80640994 ps
CPU time 0.53 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:37 PM PDT 24
Peak memory 181612 kb
Host smart-619d403f-4571-4cd4-b87f-35b38a95ed7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902389361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2902389361
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3684170147
Short name T549
Test name
Test status
Simulation time 341803171 ps
CPU time 0.81 seconds
Started Jun 30 04:51:38 PM PDT 24
Finished Jun 30 04:51:39 PM PDT 24
Peak memory 191200 kb
Host smart-cc187865-e5f4-484e-9fd9-e651dccdd2e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684170147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3684170147
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.4044891284
Short name T488
Test name
Test status
Simulation time 30817792 ps
CPU time 1.39 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:37 PM PDT 24
Peak memory 197048 kb
Host smart-e028d438-0648-4092-a603-dddfcc0642a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044891284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.4044891284
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3796776373
Short name T520
Test name
Test status
Simulation time 588695070 ps
CPU time 1.1 seconds
Started Jun 30 04:51:37 PM PDT 24
Finished Jun 30 04:51:39 PM PDT 24
Peak memory 182908 kb
Host smart-06c728c7-0a39-403f-811e-5f2ab23a8249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796776373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3796776373
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3717520287
Short name T464
Test name
Test status
Simulation time 30616117 ps
CPU time 1.42 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:38 PM PDT 24
Peak memory 197040 kb
Host smart-98618cc4-a7d8-4bfc-84f2-86ac2a1ddb1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717520287 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3717520287
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.213432721
Short name T506
Test name
Test status
Simulation time 12784508 ps
CPU time 0.56 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:36 PM PDT 24
Peak memory 182196 kb
Host smart-d85cb223-5acb-4fa7-a40e-d0e5a675a6d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213432721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.213432721
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1026190557
Short name T514
Test name
Test status
Simulation time 14304090 ps
CPU time 0.57 seconds
Started Jun 30 04:51:34 PM PDT 24
Finished Jun 30 04:51:35 PM PDT 24
Peak memory 182136 kb
Host smart-8de1f075-7b6a-4ff3-bd4c-261da27a2d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026190557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1026190557
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.759255506
Short name T500
Test name
Test status
Simulation time 29963937 ps
CPU time 0.74 seconds
Started Jun 30 04:51:35 PM PDT 24
Finished Jun 30 04:51:37 PM PDT 24
Peak memory 191136 kb
Host smart-cbb19409-0eb1-4d1d-a14c-6ec628c5fb1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759255506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.759255506
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.36986012
Short name T468
Test name
Test status
Simulation time 613417916 ps
CPU time 2.69 seconds
Started Jun 30 04:51:36 PM PDT 24
Finished Jun 30 04:51:40 PM PDT 24
Peak memory 196680 kb
Host smart-df9934e6-af9c-4459-902b-5d5e122ba1d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36986012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.36986012
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.881537998
Short name T569
Test name
Test status
Simulation time 815320779 ps
CPU time 1.42 seconds
Started Jun 30 04:51:33 PM PDT 24
Finished Jun 30 04:51:35 PM PDT 24
Peak memory 194736 kb
Host smart-01f6ac8a-2758-4e1e-b1af-d286e4bc45cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881537998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.881537998
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2432743150
Short name T386
Test name
Test status
Simulation time 126991912308 ps
CPU time 189.73 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 04:55:18 PM PDT 24
Peak memory 183080 kb
Host smart-56735e41-c870-4275-9836-4b0a369d098b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432743150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2432743150
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3760012243
Short name T336
Test name
Test status
Simulation time 66011461999 ps
CPU time 407.18 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 04:58:56 PM PDT 24
Peak memory 191576 kb
Host smart-7a805ef7-7f96-455f-bf56-4ca86c778c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760012243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3760012243
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3578010002
Short name T362
Test name
Test status
Simulation time 42369386271 ps
CPU time 31.41 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:52:43 PM PDT 24
Peak memory 183000 kb
Host smart-4f905a53-6831-4c14-86bd-4824a3e654cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578010002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3578010002
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2453277756
Short name T334
Test name
Test status
Simulation time 249848207164 ps
CPU time 787.53 seconds
Started Jun 30 04:52:11 PM PDT 24
Finished Jun 30 05:05:20 PM PDT 24
Peak memory 191168 kb
Host smart-4ec9384f-36e6-4419-ac57-fd74356d50a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453277756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2453277756
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.311512943
Short name T247
Test name
Test status
Simulation time 1559621046361 ps
CPU time 853.35 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 05:06:24 PM PDT 24
Peak memory 182872 kb
Host smart-fe71dbff-30b9-4ab6-b0c3-efc045d429c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311512943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.311512943
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3883410847
Short name T419
Test name
Test status
Simulation time 21154808730 ps
CPU time 29.8 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:52:36 PM PDT 24
Peak memory 183000 kb
Host smart-52232fdb-f38e-40e9-80f6-c317aed57427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883410847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3883410847
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3326866602
Short name T256
Test name
Test status
Simulation time 187495517826 ps
CPU time 81.16 seconds
Started Jun 30 04:52:12 PM PDT 24
Finished Jun 30 04:53:34 PM PDT 24
Peak memory 191264 kb
Host smart-d29392a8-24dc-44be-a976-fe8b71a4748f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326866602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3326866602
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.576752035
Short name T8
Test name
Test status
Simulation time 299174961 ps
CPU time 0.9 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:52:13 PM PDT 24
Peak memory 213980 kb
Host smart-36585182-a8f0-4bf3-b871-d047c85d6952
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576752035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.576752035
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.997501819
Short name T287
Test name
Test status
Simulation time 87383706008 ps
CPU time 109.57 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:54:02 PM PDT 24
Peak memory 191256 kb
Host smart-bd05946e-2f67-41af-873d-2fa5b2ca0e7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997501819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.997501819
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.703762354
Short name T300
Test name
Test status
Simulation time 951493351869 ps
CPU time 891.68 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 05:07:08 PM PDT 24
Peak memory 183084 kb
Host smart-4b437ff4-156a-4bca-bd24-aaf73526e2b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703762354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.703762354
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3024215862
Short name T434
Test name
Test status
Simulation time 12202062633 ps
CPU time 13.81 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:52:39 PM PDT 24
Peak memory 183008 kb
Host smart-7a9c4177-f741-4c66-a63d-d79df1597f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024215862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3024215862
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3349529673
Short name T335
Test name
Test status
Simulation time 136340122737 ps
CPU time 65.73 seconds
Started Jun 30 04:52:11 PM PDT 24
Finished Jun 30 04:53:19 PM PDT 24
Peak memory 194420 kb
Host smart-6616d8da-6d86-438a-b89d-934b5270b66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349529673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3349529673
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3736194798
Short name T272
Test name
Test status
Simulation time 67449189179 ps
CPU time 103.91 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:53:56 PM PDT 24
Peak memory 183088 kb
Host smart-b243e442-5cf6-4dea-b57e-8f4fe75dfc9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736194798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3736194798
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.829995195
Short name T139
Test name
Test status
Simulation time 186513868170 ps
CPU time 372.17 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 04:58:29 PM PDT 24
Peak memory 191276 kb
Host smart-809d040f-9f11-4715-b05f-82b0bc1c4f2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829995195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
829995195
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/103.rv_timer_random.4602877
Short name T226
Test name
Test status
Simulation time 399395913690 ps
CPU time 1568.53 seconds
Started Jun 30 04:53:31 PM PDT 24
Finished Jun 30 05:19:40 PM PDT 24
Peak memory 191272 kb
Host smart-388470ee-85aa-4cb0-b411-ab762e5ccb46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4602877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.4602877
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1582039526
Short name T184
Test name
Test status
Simulation time 22423765477 ps
CPU time 250.7 seconds
Started Jun 30 04:53:30 PM PDT 24
Finished Jun 30 04:57:41 PM PDT 24
Peak memory 183036 kb
Host smart-77bd2efb-db8f-4087-a28e-72e435a989b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582039526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1582039526
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1389359267
Short name T150
Test name
Test status
Simulation time 560469686968 ps
CPU time 616.45 seconds
Started Jun 30 04:53:33 PM PDT 24
Finished Jun 30 05:03:50 PM PDT 24
Peak memory 191264 kb
Host smart-a339f29c-9907-4754-bc08-ac53ad6fe5b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389359267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1389359267
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2803071281
Short name T353
Test name
Test status
Simulation time 263841864237 ps
CPU time 330.48 seconds
Started Jun 30 04:53:38 PM PDT 24
Finished Jun 30 04:59:09 PM PDT 24
Peak memory 191288 kb
Host smart-5eb4a18c-d2b4-4f8f-ae1f-4c7064409665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803071281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2803071281
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1773077347
Short name T254
Test name
Test status
Simulation time 136097757364 ps
CPU time 231.33 seconds
Started Jun 30 04:53:38 PM PDT 24
Finished Jun 30 04:57:30 PM PDT 24
Peak memory 193352 kb
Host smart-df2820f3-c6fc-44b2-83c4-183a384138eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773077347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1773077347
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.153338847
Short name T297
Test name
Test status
Simulation time 179030516307 ps
CPU time 1612.02 seconds
Started Jun 30 04:53:37 PM PDT 24
Finished Jun 30 05:20:29 PM PDT 24
Peak memory 191276 kb
Host smart-ad354ec0-b8e7-44fe-a281-100feb75ddfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153338847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.153338847
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2476298891
Short name T422
Test name
Test status
Simulation time 764462323373 ps
CPU time 274.65 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 04:56:52 PM PDT 24
Peak memory 182900 kb
Host smart-d40bc9f9-09bc-4fbb-a090-4f0bbd2d6d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476298891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2476298891
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.513029461
Short name T450
Test name
Test status
Simulation time 14596482504 ps
CPU time 13.94 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 04:52:29 PM PDT 24
Peak memory 183072 kb
Host smart-e90950f1-1a2a-4648-a7da-e8e61480af4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513029461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.513029461
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1488942231
Short name T56
Test name
Test status
Simulation time 23572535165 ps
CPU time 10.76 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:52:36 PM PDT 24
Peak memory 194620 kb
Host smart-1166eae2-a104-4a38-8b98-4acb570a1135
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488942231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1488942231
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.3198573617
Short name T321
Test name
Test status
Simulation time 17125636054 ps
CPU time 161.94 seconds
Started Jun 30 04:53:39 PM PDT 24
Finished Jun 30 04:56:21 PM PDT 24
Peak memory 183056 kb
Host smart-29cd6081-1b96-437f-9d2a-07f34919aafe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198573617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3198573617
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1001670075
Short name T24
Test name
Test status
Simulation time 133529970264 ps
CPU time 366.45 seconds
Started Jun 30 04:53:39 PM PDT 24
Finished Jun 30 04:59:45 PM PDT 24
Peak memory 191280 kb
Host smart-ec0367db-494c-4d1e-a64b-e1d0a602af8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001670075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1001670075
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1252859761
Short name T207
Test name
Test status
Simulation time 3863696195596 ps
CPU time 972.54 seconds
Started Jun 30 04:53:38 PM PDT 24
Finished Jun 30 05:09:51 PM PDT 24
Peak memory 191284 kb
Host smart-9c6a4955-e339-4d01-9d5e-b98d5e243345
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252859761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1252859761
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3160747792
Short name T143
Test name
Test status
Simulation time 250665057946 ps
CPU time 125.75 seconds
Started Jun 30 04:53:38 PM PDT 24
Finished Jun 30 04:55:44 PM PDT 24
Peak memory 191196 kb
Host smart-8504b461-7796-4b04-b7fc-fea851288754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160747792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3160747792
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.474338223
Short name T340
Test name
Test status
Simulation time 114987201568 ps
CPU time 61.29 seconds
Started Jun 30 04:53:38 PM PDT 24
Finished Jun 30 04:54:40 PM PDT 24
Peak memory 182988 kb
Host smart-8085e606-a9f8-4992-a445-c4615fe107c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474338223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.474338223
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3857549293
Short name T257
Test name
Test status
Simulation time 617910825160 ps
CPU time 220.94 seconds
Started Jun 30 04:53:37 PM PDT 24
Finished Jun 30 04:57:18 PM PDT 24
Peak memory 194724 kb
Host smart-a9a109a0-a3b3-4b8d-82f2-f0097170449e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857549293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3857549293
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3284297682
Short name T379
Test name
Test status
Simulation time 7296550636 ps
CPU time 2.89 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:52:28 PM PDT 24
Peak memory 182980 kb
Host smart-48210126-5237-4f25-8236-7acf198e174a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284297682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3284297682
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.490155260
Short name T161
Test name
Test status
Simulation time 202303943107 ps
CPU time 195.01 seconds
Started Jun 30 04:52:17 PM PDT 24
Finished Jun 30 04:55:33 PM PDT 24
Peak memory 191280 kb
Host smart-791ba6e2-c2a5-4f6b-8aa7-5368690da7d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490155260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.490155260
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2681471955
Short name T162
Test name
Test status
Simulation time 58589335031 ps
CPU time 23.22 seconds
Started Jun 30 04:52:17 PM PDT 24
Finished Jun 30 04:52:41 PM PDT 24
Peak memory 194916 kb
Host smart-b2cf7060-487f-4d4a-9c51-7c8c6394e668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681471955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2681471955
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3906368966
Short name T132
Test name
Test status
Simulation time 194729220225 ps
CPU time 167.4 seconds
Started Jun 30 04:52:15 PM PDT 24
Finished Jun 30 04:55:04 PM PDT 24
Peak memory 191184 kb
Host smart-ae59d4f9-8cd0-4b00-a012-020a8285b9b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906368966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3906368966
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/122.rv_timer_random.3980992729
Short name T118
Test name
Test status
Simulation time 1014870828516 ps
CPU time 173.32 seconds
Started Jun 30 04:53:47 PM PDT 24
Finished Jun 30 04:56:40 PM PDT 24
Peak memory 191288 kb
Host smart-c40743bd-2994-4d38-832b-4599b76e6726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980992729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3980992729
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1885950211
Short name T141
Test name
Test status
Simulation time 741814905899 ps
CPU time 642.84 seconds
Started Jun 30 04:53:46 PM PDT 24
Finished Jun 30 05:04:30 PM PDT 24
Peak memory 191268 kb
Host smart-ddb75575-90a1-4238-b035-32fdc9e4656a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885950211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1885950211
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3860282864
Short name T229
Test name
Test status
Simulation time 287329881963 ps
CPU time 680.12 seconds
Started Jun 30 04:53:55 PM PDT 24
Finished Jun 30 05:05:15 PM PDT 24
Peak memory 191232 kb
Host smart-140855df-e659-44b9-8dcc-b8cf41312875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860282864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3860282864
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1752105914
Short name T59
Test name
Test status
Simulation time 27860063665 ps
CPU time 41.35 seconds
Started Jun 30 04:53:53 PM PDT 24
Finished Jun 30 04:54:35 PM PDT 24
Peak memory 183056 kb
Host smart-045121a4-7a58-4f4c-a3af-ce0976f8ee1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752105914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1752105914
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1349069563
Short name T294
Test name
Test status
Simulation time 13583767339 ps
CPU time 15.42 seconds
Started Jun 30 04:53:54 PM PDT 24
Finished Jun 30 04:54:09 PM PDT 24
Peak memory 183096 kb
Host smart-f49adbf1-0ad7-4a97-9fd8-d017d2fc2c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349069563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1349069563
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1746166375
Short name T183
Test name
Test status
Simulation time 372606413288 ps
CPU time 2811.16 seconds
Started Jun 30 04:53:53 PM PDT 24
Finished Jun 30 05:40:45 PM PDT 24
Peak memory 191196 kb
Host smart-69455b56-537b-4f49-af79-5ffd61a1363b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746166375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1746166375
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1003075141
Short name T93
Test name
Test status
Simulation time 201349602064 ps
CPU time 133.23 seconds
Started Jun 30 04:53:54 PM PDT 24
Finished Jun 30 04:56:07 PM PDT 24
Peak memory 191284 kb
Host smart-406d40e0-bb8b-4985-a0a3-ea3f55601a2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003075141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1003075141
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3514852672
Short name T23
Test name
Test status
Simulation time 369348933798 ps
CPU time 256.18 seconds
Started Jun 30 04:52:13 PM PDT 24
Finished Jun 30 04:56:30 PM PDT 24
Peak memory 183072 kb
Host smart-67b5e9d2-b034-4846-b4ff-14d132af4316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514852672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3514852672
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2690433129
Short name T136
Test name
Test status
Simulation time 72529013161 ps
CPU time 113.6 seconds
Started Jun 30 04:52:18 PM PDT 24
Finished Jun 30 04:54:12 PM PDT 24
Peak memory 191284 kb
Host smart-85bbc5ea-da1d-4010-af49-99fd8f96cf2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690433129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2690433129
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1219376172
Short name T415
Test name
Test status
Simulation time 301021428 ps
CPU time 0.6 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:52:25 PM PDT 24
Peak memory 182856 kb
Host smart-ad412e58-c739-4deb-b725-7edf440afae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219376172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1219376172
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.475927186
Short name T381
Test name
Test status
Simulation time 55282616624 ps
CPU time 74.19 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 04:53:29 PM PDT 24
Peak memory 183084 kb
Host smart-82b4e0f7-a6b6-477e-8f37-f50a95a5789b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475927186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
475927186
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/131.rv_timer_random.3900484019
Short name T124
Test name
Test status
Simulation time 17429612241 ps
CPU time 30.01 seconds
Started Jun 30 04:53:55 PM PDT 24
Finished Jun 30 04:54:25 PM PDT 24
Peak memory 183088 kb
Host smart-97abbbb2-80a1-4aac-90c8-dd8fe9b342be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900484019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3900484019
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2075610082
Short name T182
Test name
Test status
Simulation time 284440515363 ps
CPU time 854.73 seconds
Started Jun 30 04:54:11 PM PDT 24
Finished Jun 30 05:08:26 PM PDT 24
Peak memory 191280 kb
Host smart-5c483e78-9b77-442d-9780-78265002f90f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075610082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2075610082
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2322327092
Short name T193
Test name
Test status
Simulation time 717058769096 ps
CPU time 578.17 seconds
Started Jun 30 04:54:09 PM PDT 24
Finished Jun 30 05:03:48 PM PDT 24
Peak memory 191276 kb
Host smart-812f6e77-5fa8-422d-8080-7dd720b499ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322327092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2322327092
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3897226057
Short name T217
Test name
Test status
Simulation time 184029558447 ps
CPU time 466.48 seconds
Started Jun 30 04:54:08 PM PDT 24
Finished Jun 30 05:01:55 PM PDT 24
Peak memory 191300 kb
Host smart-a0b8b1c9-838b-4e1d-85a9-626ffeb209fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897226057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3897226057
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1358740112
Short name T123
Test name
Test status
Simulation time 127288819521 ps
CPU time 96.57 seconds
Started Jun 30 04:54:12 PM PDT 24
Finished Jun 30 04:55:49 PM PDT 24
Peak memory 182996 kb
Host smart-9a747a3d-9e01-48df-b1bb-742848f5043b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358740112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1358740112
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2170721423
Short name T181
Test name
Test status
Simulation time 69332050926 ps
CPU time 275.43 seconds
Started Jun 30 04:54:02 PM PDT 24
Finished Jun 30 04:58:38 PM PDT 24
Peak memory 191188 kb
Host smart-f3278276-0e3f-4596-86de-7b1dd21e14c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170721423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2170721423
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2737685489
Short name T265
Test name
Test status
Simulation time 4308525633 ps
CPU time 7.06 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:52:31 PM PDT 24
Peak memory 182964 kb
Host smart-bdfd1383-e7dc-42f8-9355-53c404eb3c12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737685489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2737685489
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1545181296
Short name T368
Test name
Test status
Simulation time 151886617468 ps
CPU time 42.34 seconds
Started Jun 30 04:52:17 PM PDT 24
Finished Jun 30 04:53:01 PM PDT 24
Peak memory 183096 kb
Host smart-1f146969-ea02-480f-abc7-3ad1e8620dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545181296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1545181296
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1251794271
Short name T196
Test name
Test status
Simulation time 17170989721 ps
CPU time 100.67 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:54:06 PM PDT 24
Peak memory 190876 kb
Host smart-6126a752-2513-4999-a881-961a36d4b061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251794271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1251794271
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1968967665
Short name T4
Test name
Test status
Simulation time 153492965710 ps
CPU time 545.26 seconds
Started Jun 30 04:52:23 PM PDT 24
Finished Jun 30 05:01:29 PM PDT 24
Peak memory 191172 kb
Host smart-72ab770b-c046-4e80-a36d-2eace0c57bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968967665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1968967665
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.3763885583
Short name T11
Test name
Test status
Simulation time 118877210761 ps
CPU time 291.62 seconds
Started Jun 30 04:54:10 PM PDT 24
Finished Jun 30 04:59:02 PM PDT 24
Peak memory 191276 kb
Host smart-c72aa778-a4b0-42dd-917a-e66a51747298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763885583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3763885583
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3246504814
Short name T341
Test name
Test status
Simulation time 1520803772067 ps
CPU time 470.36 seconds
Started Jun 30 04:54:10 PM PDT 24
Finished Jun 30 05:02:00 PM PDT 24
Peak memory 191268 kb
Host smart-ac2f0a3b-613f-45f0-8191-85444d185242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246504814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3246504814
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1246231712
Short name T433
Test name
Test status
Simulation time 54574887301 ps
CPU time 50.95 seconds
Started Jun 30 04:54:10 PM PDT 24
Finished Jun 30 04:55:01 PM PDT 24
Peak memory 191280 kb
Host smart-1cdff929-069f-43c4-9456-0df098928889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246231712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1246231712
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1655246204
Short name T126
Test name
Test status
Simulation time 971439394302 ps
CPU time 1651.17 seconds
Started Jun 30 04:54:08 PM PDT 24
Finished Jun 30 05:21:40 PM PDT 24
Peak memory 191264 kb
Host smart-08384885-d34a-49eb-939a-b888819f4e9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655246204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1655246204
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1339650230
Short name T307
Test name
Test status
Simulation time 534431574800 ps
CPU time 827.11 seconds
Started Jun 30 04:54:17 PM PDT 24
Finished Jun 30 05:08:04 PM PDT 24
Peak memory 191280 kb
Host smart-cc749c40-a697-47b2-ac59-ef98f0dc72b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339650230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1339650230
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1172210808
Short name T246
Test name
Test status
Simulation time 151146644912 ps
CPU time 244.63 seconds
Started Jun 30 04:54:18 PM PDT 24
Finished Jun 30 04:58:23 PM PDT 24
Peak memory 191292 kb
Host smart-8cdb36b0-415d-4d39-93d7-5c95c909a4a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172210808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1172210808
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1726999648
Short name T437
Test name
Test status
Simulation time 23252264726 ps
CPU time 20.03 seconds
Started Jun 30 04:54:19 PM PDT 24
Finished Jun 30 04:54:39 PM PDT 24
Peak memory 183376 kb
Host smart-6563d34c-b871-403b-9d41-2a9631d89928
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726999648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1726999648
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1976945016
Short name T208
Test name
Test status
Simulation time 238872011514 ps
CPU time 351.21 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:58:16 PM PDT 24
Peak memory 182964 kb
Host smart-83a6d3ac-641c-43b2-b5b3-d27d782344ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976945016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1976945016
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.274863888
Short name T370
Test name
Test status
Simulation time 224785911828 ps
CPU time 92.47 seconds
Started Jun 30 04:52:18 PM PDT 24
Finished Jun 30 04:53:51 PM PDT 24
Peak memory 183092 kb
Host smart-edf29abf-c1bc-4876-b7a1-62d5acdbce5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274863888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.274863888
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2571247025
Short name T157
Test name
Test status
Simulation time 215932381442 ps
CPU time 177.01 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:55:23 PM PDT 24
Peak memory 191176 kb
Host smart-6d4bb61b-29d7-4c16-8acd-a7ed1a4f7d1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571247025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2571247025
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3161130474
Short name T202
Test name
Test status
Simulation time 232180485130 ps
CPU time 335.21 seconds
Started Jun 30 04:52:18 PM PDT 24
Finished Jun 30 04:57:54 PM PDT 24
Peak memory 183108 kb
Host smart-5feac4cf-1b6d-42b2-8b14-2f5671d5472e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161130474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3161130474
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.431909596
Short name T283
Test name
Test status
Simulation time 375856424710 ps
CPU time 1750.73 seconds
Started Jun 30 04:54:18 PM PDT 24
Finished Jun 30 05:23:29 PM PDT 24
Peak memory 191152 kb
Host smart-0b99bed8-eb47-4ecd-b169-c0aae1c7b0f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431909596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.431909596
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3556016765
Short name T176
Test name
Test status
Simulation time 50382215747 ps
CPU time 77.78 seconds
Started Jun 30 04:54:17 PM PDT 24
Finished Jun 30 04:55:36 PM PDT 24
Peak memory 191268 kb
Host smart-24c51214-955d-4cd6-bb6d-8efbaa67312f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556016765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3556016765
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.601371773
Short name T235
Test name
Test status
Simulation time 108112061786 ps
CPU time 69.84 seconds
Started Jun 30 04:54:17 PM PDT 24
Finished Jun 30 04:55:28 PM PDT 24
Peak memory 183088 kb
Host smart-90479688-672d-4295-920a-aca9892cadbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601371773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.601371773
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2227803408
Short name T169
Test name
Test status
Simulation time 106849897205 ps
CPU time 291.91 seconds
Started Jun 30 04:54:28 PM PDT 24
Finished Jun 30 04:59:20 PM PDT 24
Peak memory 191288 kb
Host smart-b343cf9f-4a2f-4229-82c9-c9d335a3a01a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227803408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2227803408
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.4148251272
Short name T230
Test name
Test status
Simulation time 44697311190 ps
CPU time 42.1 seconds
Started Jun 30 04:54:28 PM PDT 24
Finished Jun 30 04:55:10 PM PDT 24
Peak memory 183080 kb
Host smart-73c75aad-ac86-4768-bb52-75b5bbc383e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148251272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.4148251272
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1988524096
Short name T267
Test name
Test status
Simulation time 150049081910 ps
CPU time 127.59 seconds
Started Jun 30 04:54:26 PM PDT 24
Finished Jun 30 04:56:35 PM PDT 24
Peak memory 191164 kb
Host smart-621c6fd3-0e2f-4f29-ba19-59c51b7ba5e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988524096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1988524096
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3104525543
Short name T5
Test name
Test status
Simulation time 139968628492 ps
CPU time 115.35 seconds
Started Jun 30 04:54:26 PM PDT 24
Finished Jun 30 04:56:22 PM PDT 24
Peak memory 191176 kb
Host smart-1234cd02-97e9-4d1d-8b2b-aef6703b36bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104525543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3104525543
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4276176249
Short name T270
Test name
Test status
Simulation time 307352700626 ps
CPU time 507.41 seconds
Started Jun 30 04:52:23 PM PDT 24
Finished Jun 30 05:00:51 PM PDT 24
Peak memory 182964 kb
Host smart-179fdd67-10ef-4571-962f-7c4430c06879
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276176249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.4276176249
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.556773145
Short name T380
Test name
Test status
Simulation time 366610052240 ps
CPU time 252.71 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 04:56:30 PM PDT 24
Peak memory 183096 kb
Host smart-7d957a98-d88e-4697-a8d7-d7d22af7bf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556773145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.556773145
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2201727614
Short name T168
Test name
Test status
Simulation time 550857206465 ps
CPU time 320.73 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 04:57:37 PM PDT 24
Peak memory 191276 kb
Host smart-65274e55-34b6-4898-8fb4-980e40f3bcbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201727614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2201727614
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2265906780
Short name T390
Test name
Test status
Simulation time 446915209 ps
CPU time 0.69 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 04:52:18 PM PDT 24
Peak memory 191352 kb
Host smart-ca6db4e4-c2d7-4835-9a6a-2b1a44b6a748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265906780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2265906780
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3384894223
Short name T443
Test name
Test status
Simulation time 434394177273 ps
CPU time 223.07 seconds
Started Jun 30 04:54:26 PM PDT 24
Finished Jun 30 04:58:10 PM PDT 24
Peak memory 183032 kb
Host smart-ed785bdc-dd2f-4c33-8bba-9d5ce88f6555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384894223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3384894223
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3539405824
Short name T215
Test name
Test status
Simulation time 323205667372 ps
CPU time 635.32 seconds
Started Jun 30 04:54:25 PM PDT 24
Finished Jun 30 05:05:01 PM PDT 24
Peak memory 191284 kb
Host smart-4f8665a1-2aa3-45a0-a7f3-88fcbdf63f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539405824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3539405824
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3797728140
Short name T305
Test name
Test status
Simulation time 99597844460 ps
CPU time 352.67 seconds
Started Jun 30 04:54:26 PM PDT 24
Finished Jun 30 05:00:19 PM PDT 24
Peak memory 191188 kb
Host smart-813e1713-3345-49ff-9888-8626d652b2da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797728140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3797728140
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.152281125
Short name T177
Test name
Test status
Simulation time 435674348275 ps
CPU time 475.29 seconds
Started Jun 30 04:54:27 PM PDT 24
Finished Jun 30 05:02:22 PM PDT 24
Peak memory 191272 kb
Host smart-3bcbba7e-7810-40c9-8795-ae22ecb5e65a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152281125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.152281125
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3019134750
Short name T427
Test name
Test status
Simulation time 60542239047 ps
CPU time 96.77 seconds
Started Jun 30 04:54:26 PM PDT 24
Finished Jun 30 04:56:03 PM PDT 24
Peak memory 191288 kb
Host smart-25ddaaa2-bba9-4b53-bf33-f54a360bcbf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019134750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3019134750
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2324459594
Short name T274
Test name
Test status
Simulation time 54742112928 ps
CPU time 85.46 seconds
Started Jun 30 04:54:34 PM PDT 24
Finished Jun 30 04:56:00 PM PDT 24
Peak memory 191232 kb
Host smart-50cb8fb0-fc3a-4e3c-90d0-11a67161f787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324459594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2324459594
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2714592530
Short name T314
Test name
Test status
Simulation time 157495443801 ps
CPU time 1652.77 seconds
Started Jun 30 04:54:37 PM PDT 24
Finished Jun 30 05:22:10 PM PDT 24
Peak memory 191300 kb
Host smart-60ff988c-c8d1-4968-a4f7-3f80980cace2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714592530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2714592530
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.620335981
Short name T429
Test name
Test status
Simulation time 218104777089 ps
CPU time 210.73 seconds
Started Jun 30 04:54:33 PM PDT 24
Finished Jun 30 04:58:04 PM PDT 24
Peak memory 191292 kb
Host smart-cdd7c9b8-fc79-4320-9070-d50f47ccd3f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620335981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.620335981
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3404243959
Short name T351
Test name
Test status
Simulation time 947676120303 ps
CPU time 529.39 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 05:01:07 PM PDT 24
Peak memory 182960 kb
Host smart-34ad2204-5dc1-49b9-977f-f4a62d848e0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404243959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3404243959
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2066063342
Short name T375
Test name
Test status
Simulation time 152385525375 ps
CPU time 194.12 seconds
Started Jun 30 04:52:17 PM PDT 24
Finished Jun 30 04:55:32 PM PDT 24
Peak memory 182924 kb
Host smart-2b248650-14b9-4c87-b051-6196273b046c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066063342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2066063342
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.1510415471
Short name T278
Test name
Test status
Simulation time 114031857646 ps
CPU time 182.1 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 04:55:19 PM PDT 24
Peak memory 191288 kb
Host smart-795b7073-7fc3-4d64-b5a4-cf60f84c2225
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510415471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1510415471
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3320178052
Short name T328
Test name
Test status
Simulation time 19756632200 ps
CPU time 37.81 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 04:52:55 PM PDT 24
Peak memory 183104 kb
Host smart-0e1e97b7-a0ba-4641-9dcc-2f19da094739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320178052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3320178052
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.410746825
Short name T105
Test name
Test status
Simulation time 598140318992 ps
CPU time 637.43 seconds
Started Jun 30 04:52:17 PM PDT 24
Finished Jun 30 05:02:56 PM PDT 24
Peak memory 191276 kb
Host smart-8abb836b-c594-43a5-9d82-d2ef56ece3df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410746825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
410746825
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2149477756
Short name T211
Test name
Test status
Simulation time 368313187770 ps
CPU time 785.81 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 05:05:31 PM PDT 24
Peak memory 208960 kb
Host smart-1a8828d2-2f6e-45c8-8441-09c5a0482107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149477756 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2149477756
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.35388702
Short name T251
Test name
Test status
Simulation time 71002639319 ps
CPU time 408.13 seconds
Started Jun 30 04:54:33 PM PDT 24
Finished Jun 30 05:01:22 PM PDT 24
Peak memory 191272 kb
Host smart-f2c7edbb-9875-490e-9989-e3b1e4326bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35388702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.35388702
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1024937972
Short name T179
Test name
Test status
Simulation time 387549731476 ps
CPU time 149.82 seconds
Started Jun 30 04:54:34 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 191568 kb
Host smart-698f300c-e45c-421f-a2ee-8eb4aac34b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024937972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1024937972
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.427448558
Short name T7
Test name
Test status
Simulation time 124576994160 ps
CPU time 194.38 seconds
Started Jun 30 04:54:34 PM PDT 24
Finished Jun 30 04:57:50 PM PDT 24
Peak memory 191264 kb
Host smart-e907084e-403f-44bb-bd92-596bb462ed26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427448558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.427448558
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.774896127
Short name T261
Test name
Test status
Simulation time 359824449464 ps
CPU time 228.97 seconds
Started Jun 30 04:54:34 PM PDT 24
Finished Jun 30 04:58:24 PM PDT 24
Peak memory 193596 kb
Host smart-b8dd3337-744e-4c38-a9db-b01d6dff2f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774896127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.774896127
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3163965146
Short name T323
Test name
Test status
Simulation time 52761672562 ps
CPU time 390.48 seconds
Started Jun 30 04:54:35 PM PDT 24
Finished Jun 30 05:01:06 PM PDT 24
Peak memory 191180 kb
Host smart-7ba4351b-7fb6-405c-b376-7756a48bfa11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163965146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3163965146
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.625446559
Short name T401
Test name
Test status
Simulation time 280620147955 ps
CPU time 346.44 seconds
Started Jun 30 04:54:34 PM PDT 24
Finished Jun 30 05:00:21 PM PDT 24
Peak memory 191172 kb
Host smart-6b752db2-d414-45c3-9d68-9b12ee918ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625446559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.625446559
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2477440407
Short name T331
Test name
Test status
Simulation time 152560687281 ps
CPU time 158.34 seconds
Started Jun 30 04:54:34 PM PDT 24
Finished Jun 30 04:57:13 PM PDT 24
Peak memory 191276 kb
Host smart-bd801f76-1c44-46ec-be0f-c8565dcc7687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477440407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2477440407
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3316056327
Short name T204
Test name
Test status
Simulation time 15451970507 ps
CPU time 9.07 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:52:34 PM PDT 24
Peak memory 183044 kb
Host smart-c2154993-f3f7-411e-b4f1-78d2563686a6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316056327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3316056327
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.79677203
Short name T409
Test name
Test status
Simulation time 40678339250 ps
CPU time 54.53 seconds
Started Jun 30 04:52:17 PM PDT 24
Finished Jun 30 04:53:13 PM PDT 24
Peak memory 182960 kb
Host smart-8ad8011e-5630-4144-8d41-384892ae5bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79677203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.79677203
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2023924802
Short name T289
Test name
Test status
Simulation time 684291001684 ps
CPU time 271.57 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:56:57 PM PDT 24
Peak memory 191180 kb
Host smart-1f478a26-2902-4200-932e-1643e580f01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023924802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2023924802
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.691568166
Short name T140
Test name
Test status
Simulation time 46894151855 ps
CPU time 24.18 seconds
Started Jun 30 04:52:15 PM PDT 24
Finished Jun 30 04:52:40 PM PDT 24
Peak memory 191292 kb
Host smart-918678b7-ff55-4e53-8c3b-c57e351e892a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691568166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.691568166
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.218138396
Short name T205
Test name
Test status
Simulation time 252978718858 ps
CPU time 428.61 seconds
Started Jun 30 04:54:34 PM PDT 24
Finished Jun 30 05:01:43 PM PDT 24
Peak memory 195124 kb
Host smart-0a051236-84ec-45d2-b585-24709279a6ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218138396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.218138396
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1414995923
Short name T203
Test name
Test status
Simulation time 172643405641 ps
CPU time 54.03 seconds
Started Jun 30 04:54:34 PM PDT 24
Finished Jun 30 04:55:28 PM PDT 24
Peak memory 191260 kb
Host smart-48ea3ffb-fdbb-4e76-b415-13eb30743dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414995923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1414995923
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2417486108
Short name T356
Test name
Test status
Simulation time 43252209428 ps
CPU time 96.6 seconds
Started Jun 30 04:54:40 PM PDT 24
Finished Jun 30 04:56:17 PM PDT 24
Peak memory 183064 kb
Host smart-79a77db1-1e97-469e-b7d1-7fb62c96eac6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417486108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2417486108
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3241809523
Short name T165
Test name
Test status
Simulation time 193068837857 ps
CPU time 541.81 seconds
Started Jun 30 04:54:41 PM PDT 24
Finished Jun 30 05:03:43 PM PDT 24
Peak memory 191260 kb
Host smart-59a264e9-16ca-48d9-b508-5bbaf0e53dd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241809523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3241809523
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2557580693
Short name T218
Test name
Test status
Simulation time 23600469164 ps
CPU time 31.68 seconds
Started Jun 30 04:55:14 PM PDT 24
Finished Jun 30 04:55:46 PM PDT 24
Peak memory 182668 kb
Host smart-b0f409fd-e4b0-400f-a845-41020ee6970b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557580693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2557580693
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.958969472
Short name T359
Test name
Test status
Simulation time 340868582244 ps
CPU time 1313.02 seconds
Started Jun 30 04:54:42 PM PDT 24
Finished Jun 30 05:16:35 PM PDT 24
Peak memory 191288 kb
Host smart-ac350dc5-4175-4b05-aa6d-a56f4d7c5d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958969472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.958969472
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3429993543
Short name T42
Test name
Test status
Simulation time 89009715413 ps
CPU time 668.23 seconds
Started Jun 30 04:54:44 PM PDT 24
Finished Jun 30 05:05:54 PM PDT 24
Peak memory 191196 kb
Host smart-7ce73d1c-9f71-4ee1-a04c-6e838dfa478e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429993543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3429993543
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.44968957
Short name T191
Test name
Test status
Simulation time 104890427795 ps
CPU time 1747.66 seconds
Started Jun 30 04:54:45 PM PDT 24
Finished Jun 30 05:23:53 PM PDT 24
Peak memory 191192 kb
Host smart-5a1cb1cc-deb9-47d7-ab61-9cfc0b3f9ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44968957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.44968957
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2913494208
Short name T43
Test name
Test status
Simulation time 117197203299 ps
CPU time 182.16 seconds
Started Jun 30 04:52:15 PM PDT 24
Finished Jun 30 04:55:18 PM PDT 24
Peak memory 183072 kb
Host smart-58d99183-1057-4152-ad0f-705c11e1e9db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913494208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2913494208
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.457072587
Short name T394
Test name
Test status
Simulation time 272368695355 ps
CPU time 95.55 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 04:53:53 PM PDT 24
Peak memory 183088 kb
Host smart-d8e12fbd-7718-4468-b196-81ad0844a378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457072587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.457072587
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.20697667
Short name T53
Test name
Test status
Simulation time 74869798169 ps
CPU time 135.03 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 04:54:32 PM PDT 24
Peak memory 191184 kb
Host smart-3bd885a7-645b-4b72-89b6-6792361bf577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20697667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.20697667
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.329163106
Short name T52
Test name
Test status
Simulation time 47210256843 ps
CPU time 69.57 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:53:35 PM PDT 24
Peak memory 191272 kb
Host smart-20b759ff-3269-4e97-a953-89b8ee4d61de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329163106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.329163106
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2201929595
Short name T51
Test name
Test status
Simulation time 70063323 ps
CPU time 0.56 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:52:25 PM PDT 24
Peak memory 182828 kb
Host smart-1146e1ef-bc34-4607-9833-68efa4d36a01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201929595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2201929595
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.2756554745
Short name T116
Test name
Test status
Simulation time 219854286536 ps
CPU time 1710.75 seconds
Started Jun 30 04:54:44 PM PDT 24
Finished Jun 30 05:23:15 PM PDT 24
Peak memory 191196 kb
Host smart-122ebbcb-3649-40f8-9dcc-b22758205ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756554745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2756554745
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.521747128
Short name T144
Test name
Test status
Simulation time 713897379226 ps
CPU time 750.65 seconds
Started Jun 30 04:54:41 PM PDT 24
Finished Jun 30 05:07:12 PM PDT 24
Peak memory 191284 kb
Host smart-11c187da-f72a-469f-952c-04c97cf536e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521747128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.521747128
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2123727247
Short name T347
Test name
Test status
Simulation time 108601328130 ps
CPU time 230.53 seconds
Started Jun 30 04:55:20 PM PDT 24
Finished Jun 30 04:59:11 PM PDT 24
Peak memory 190868 kb
Host smart-6b199de0-1f58-47cc-8e30-1dbe0b34cb51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123727247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2123727247
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3466179741
Short name T286
Test name
Test status
Simulation time 59259556423 ps
CPU time 95.34 seconds
Started Jun 30 04:54:48 PM PDT 24
Finished Jun 30 04:56:24 PM PDT 24
Peak memory 191284 kb
Host smart-cb3795c6-dadb-4317-8205-1084ee208043
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466179741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3466179741
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3112093715
Short name T185
Test name
Test status
Simulation time 170144777068 ps
CPU time 616.11 seconds
Started Jun 30 04:54:47 PM PDT 24
Finished Jun 30 05:05:04 PM PDT 24
Peak memory 194604 kb
Host smart-6168a79e-31f0-40c5-99af-c588bac460d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112093715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3112093715
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1232172565
Short name T242
Test name
Test status
Simulation time 1327781528205 ps
CPU time 383.05 seconds
Started Jun 30 04:54:50 PM PDT 24
Finished Jun 30 05:01:13 PM PDT 24
Peak memory 191288 kb
Host smart-544b2124-351f-4f87-9a48-02f09d9110c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232172565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1232172565
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.458544302
Short name T446
Test name
Test status
Simulation time 13304554462 ps
CPU time 20.33 seconds
Started Jun 30 04:54:48 PM PDT 24
Finished Jun 30 04:55:08 PM PDT 24
Peak memory 183124 kb
Host smart-4041052b-1060-4360-8cc3-6b90f282e531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458544302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.458544302
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3148076801
Short name T392
Test name
Test status
Simulation time 134726643973 ps
CPU time 176.49 seconds
Started Jun 30 04:52:11 PM PDT 24
Finished Jun 30 04:55:09 PM PDT 24
Peak memory 183088 kb
Host smart-7bc52b16-8712-44eb-b1ec-d586e92293ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148076801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3148076801
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1894897617
Short name T145
Test name
Test status
Simulation time 324451566529 ps
CPU time 2508.06 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 05:33:59 PM PDT 24
Peak memory 194564 kb
Host smart-df3df111-261a-4aa7-b252-f9e5596d9a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894897617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1894897617
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3626567531
Short name T18
Test name
Test status
Simulation time 529940226 ps
CPU time 0.93 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:52:14 PM PDT 24
Peak memory 214384 kb
Host smart-4b5c904e-ad3c-4c98-a08c-7b8e6295fbb3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626567531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3626567531
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.883649708
Short name T85
Test name
Test status
Simulation time 25896126995 ps
CPU time 222.78 seconds
Started Jun 30 04:52:11 PM PDT 24
Finished Jun 30 04:55:56 PM PDT 24
Peak memory 197772 kb
Host smart-ab3c77de-053d-4f7c-8715-967749cc40c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883649708 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.883649708
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.193149482
Short name T355
Test name
Test status
Simulation time 1095597565137 ps
CPU time 526.58 seconds
Started Jun 30 04:52:13 PM PDT 24
Finished Jun 30 05:01:00 PM PDT 24
Peak memory 183056 kb
Host smart-11d5e549-cd25-43ae-9b57-59390bc412cf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193149482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.193149482
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2709533502
Short name T367
Test name
Test status
Simulation time 48184434624 ps
CPU time 35.89 seconds
Started Jun 30 04:52:13 PM PDT 24
Finished Jun 30 04:52:50 PM PDT 24
Peak memory 183048 kb
Host smart-eb54773e-e6e3-423f-80af-6f764987c11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709533502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2709533502
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3963020268
Short name T263
Test name
Test status
Simulation time 57581883401 ps
CPU time 102.42 seconds
Started Jun 30 04:52:20 PM PDT 24
Finished Jun 30 04:54:03 PM PDT 24
Peak memory 191048 kb
Host smart-064b9034-3598-465e-9f80-00e530cdae8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963020268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3963020268
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.915537239
Short name T449
Test name
Test status
Simulation time 74634161972 ps
CPU time 153.03 seconds
Started Jun 30 04:52:18 PM PDT 24
Finished Jun 30 04:54:52 PM PDT 24
Peak memory 194652 kb
Host smart-6e436952-6dd4-4439-ac78-0a7759a83020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915537239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.915537239
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2155853728
Short name T406
Test name
Test status
Simulation time 219092047853 ps
CPU time 305.35 seconds
Started Jun 30 04:52:13 PM PDT 24
Finished Jun 30 04:57:19 PM PDT 24
Peak memory 182976 kb
Host smart-a082bb39-9fa1-4d82-8bb3-43df85f8b82d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155853728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2155853728
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.390768162
Short name T432
Test name
Test status
Simulation time 70365371530 ps
CPU time 91.78 seconds
Started Jun 30 04:52:20 PM PDT 24
Finished Jun 30 04:53:53 PM PDT 24
Peak memory 182860 kb
Host smart-d0807674-2b1c-4b1b-b6f1-5a78118e7b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390768162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.390768162
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.4066675093
Short name T404
Test name
Test status
Simulation time 17291925 ps
CPU time 0.54 seconds
Started Jun 30 04:52:13 PM PDT 24
Finished Jun 30 04:52:14 PM PDT 24
Peak memory 182904 kb
Host smart-ec287592-5d22-4ecb-8009-9849d894d199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066675093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.4066675093
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.2208410030
Short name T46
Test name
Test status
Simulation time 58755570539 ps
CPU time 421.41 seconds
Started Jun 30 04:52:13 PM PDT 24
Finished Jun 30 04:59:15 PM PDT 24
Peak memory 197792 kb
Host smart-ac9ce42c-da81-445c-baaf-feada00d7525
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208410030 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.2208410030
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3211232642
Short name T325
Test name
Test status
Simulation time 312757561744 ps
CPU time 284.19 seconds
Started Jun 30 04:52:21 PM PDT 24
Finished Jun 30 04:57:06 PM PDT 24
Peak memory 183072 kb
Host smart-b094ddb8-e12f-4ce0-bf0f-3de63eab368f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211232642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3211232642
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2089978357
Short name T428
Test name
Test status
Simulation time 106846218987 ps
CPU time 139.78 seconds
Started Jun 30 04:52:22 PM PDT 24
Finished Jun 30 04:54:42 PM PDT 24
Peak memory 183052 kb
Host smart-b99acf26-02db-4ee8-80c3-5ad561f4baeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089978357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2089978357
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.942640868
Short name T291
Test name
Test status
Simulation time 1450699729403 ps
CPU time 737.65 seconds
Started Jun 30 04:52:16 PM PDT 24
Finished Jun 30 05:04:34 PM PDT 24
Peak memory 191252 kb
Host smart-aaba83dc-9ef5-4683-8fb1-e64c859f9e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942640868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.942640868
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3481051845
Short name T290
Test name
Test status
Simulation time 156034370128 ps
CPU time 348.67 seconds
Started Jun 30 04:52:19 PM PDT 24
Finished Jun 30 04:58:08 PM PDT 24
Peak memory 191276 kb
Host smart-8bf70d9c-d1b1-45c2-a497-b1bd1c49d3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481051845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3481051845
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3892103824
Short name T173
Test name
Test status
Simulation time 5130461311584 ps
CPU time 1173.69 seconds
Started Jun 30 04:52:18 PM PDT 24
Finished Jun 30 05:11:52 PM PDT 24
Peak memory 183060 kb
Host smart-f913ac04-a723-4824-b77c-2ba0d8ea71b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892103824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3892103824
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1320189992
Short name T399
Test name
Test status
Simulation time 61467102241 ps
CPU time 24.04 seconds
Started Jun 30 04:52:18 PM PDT 24
Finished Jun 30 04:52:43 PM PDT 24
Peak memory 183068 kb
Host smart-4da1b840-73bb-4580-8bdb-4f7d2dbb4dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320189992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1320189992
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.87362557
Short name T20
Test name
Test status
Simulation time 307419766761 ps
CPU time 282.58 seconds
Started Jun 30 04:52:18 PM PDT 24
Finished Jun 30 04:57:02 PM PDT 24
Peak memory 191284 kb
Host smart-e618e0be-41f6-49e8-b5f8-3603b84965e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87362557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.87362557
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1506223080
Short name T445
Test name
Test status
Simulation time 34565627043 ps
CPU time 109.97 seconds
Started Jun 30 04:52:23 PM PDT 24
Finished Jun 30 04:54:13 PM PDT 24
Peak memory 183092 kb
Host smart-d5984a8a-d1d3-48fe-b604-689b09bd0d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506223080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1506223080
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.3469914655
Short name T60
Test name
Test status
Simulation time 108800079713 ps
CPU time 223.01 seconds
Started Jun 30 04:52:19 PM PDT 24
Finished Jun 30 04:56:03 PM PDT 24
Peak memory 205964 kb
Host smart-e564040f-d440-4dc5-ac88-1caf74ec9e3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469914655 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.3469914655
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.491512865
Short name T213
Test name
Test status
Simulation time 471591236490 ps
CPU time 765.66 seconds
Started Jun 30 04:52:22 PM PDT 24
Finished Jun 30 05:05:09 PM PDT 24
Peak memory 182852 kb
Host smart-2a127748-c783-4b97-af95-01da4d78affe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491512865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.491512865
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.827353695
Short name T393
Test name
Test status
Simulation time 252001740899 ps
CPU time 75.79 seconds
Started Jun 30 04:52:20 PM PDT 24
Finished Jun 30 04:53:37 PM PDT 24
Peak memory 183380 kb
Host smart-81257927-f15e-4bf0-855c-9441845f30d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827353695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.827353695
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2140386197
Short name T178
Test name
Test status
Simulation time 193111324727 ps
CPU time 111.58 seconds
Started Jun 30 04:52:18 PM PDT 24
Finished Jun 30 04:54:11 PM PDT 24
Peak memory 183100 kb
Host smart-81dbe4a1-267b-48ca-a015-b0546f1ad872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140386197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2140386197
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.873280570
Short name T172
Test name
Test status
Simulation time 440485076116 ps
CPU time 384.57 seconds
Started Jun 30 04:52:21 PM PDT 24
Finished Jun 30 04:58:46 PM PDT 24
Peak memory 191200 kb
Host smart-096aa1c6-bb51-4445-a1c6-b8045a278468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873280570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
873280570
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2080544204
Short name T35
Test name
Test status
Simulation time 8955087795 ps
CPU time 95.64 seconds
Started Jun 30 04:52:22 PM PDT 24
Finished Jun 30 04:53:58 PM PDT 24
Peak memory 197776 kb
Host smart-f3f65682-9389-4e6f-9b2e-8050d0a13de8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080544204 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2080544204
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1144059238
Short name T134
Test name
Test status
Simulation time 53139109281 ps
CPU time 80.45 seconds
Started Jun 30 04:52:19 PM PDT 24
Finished Jun 30 04:53:40 PM PDT 24
Peak memory 183080 kb
Host smart-b257240a-b08c-4f9f-9434-e1de797beeba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144059238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1144059238
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2923141736
Short name T373
Test name
Test status
Simulation time 622912144778 ps
CPU time 250.62 seconds
Started Jun 30 04:52:23 PM PDT 24
Finished Jun 30 04:56:34 PM PDT 24
Peak memory 183084 kb
Host smart-e146bda3-63de-4674-b2de-4674a321ef18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923141736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2923141736
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.3280201769
Short name T412
Test name
Test status
Simulation time 193063122414 ps
CPU time 294.44 seconds
Started Jun 30 04:52:20 PM PDT 24
Finished Jun 30 04:57:14 PM PDT 24
Peak memory 205900 kb
Host smart-55aca41c-48dd-4730-9d90-b37024ccc273
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280201769 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.3280201769
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.729433164
Short name T329
Test name
Test status
Simulation time 374948524048 ps
CPU time 196.17 seconds
Started Jun 30 04:52:21 PM PDT 24
Finished Jun 30 04:55:38 PM PDT 24
Peak memory 183076 kb
Host smart-ff2c575b-50b1-41fa-b2fe-6f860857b45c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729433164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.729433164
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.4286773765
Short name T384
Test name
Test status
Simulation time 13265876683 ps
CPU time 18.38 seconds
Started Jun 30 04:52:22 PM PDT 24
Finished Jun 30 04:52:41 PM PDT 24
Peak memory 183108 kb
Host smart-763296c2-fc7e-4927-9df8-39083c364972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286773765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.4286773765
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.4192588776
Short name T260
Test name
Test status
Simulation time 788262398969 ps
CPU time 906.01 seconds
Started Jun 30 04:52:20 PM PDT 24
Finished Jun 30 05:07:27 PM PDT 24
Peak memory 191296 kb
Host smart-c8b5e498-978a-4166-9e0b-2d7e1dd4cdb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192588776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.4192588776
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3215102812
Short name T112
Test name
Test status
Simulation time 15379273981 ps
CPU time 28.28 seconds
Started Jun 30 04:52:20 PM PDT 24
Finished Jun 30 04:52:49 PM PDT 24
Peak memory 183024 kb
Host smart-d983398d-d0bf-4cce-a56f-9ca61a47b59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215102812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3215102812
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3904005756
Short name T416
Test name
Test status
Simulation time 742888591687 ps
CPU time 118.57 seconds
Started Jun 30 04:52:18 PM PDT 24
Finished Jun 30 04:54:18 PM PDT 24
Peak memory 183080 kb
Host smart-3affd4c9-03a3-4cb3-9900-16f254507023
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904005756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3904005756
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.3172645977
Short name T36
Test name
Test status
Simulation time 88396721176 ps
CPU time 480.17 seconds
Started Jun 30 04:52:19 PM PDT 24
Finished Jun 30 05:00:20 PM PDT 24
Peak memory 207020 kb
Host smart-5c1c101f-d159-42cf-bf83-524829df0441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172645977 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.3172645977
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3740643101
Short name T332
Test name
Test status
Simulation time 2028937574186 ps
CPU time 1052.41 seconds
Started Jun 30 04:52:23 PM PDT 24
Finished Jun 30 05:09:56 PM PDT 24
Peak memory 182848 kb
Host smart-1113837a-435a-4c59-a9a9-ddbec65d0b77
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740643101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3740643101
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random.1791682636
Short name T122
Test name
Test status
Simulation time 84795432598 ps
CPU time 259.58 seconds
Started Jun 30 04:52:19 PM PDT 24
Finished Jun 30 04:56:39 PM PDT 24
Peak memory 191288 kb
Host smart-65e33275-1f7d-463e-a3eb-c4f0fa00e9fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791682636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1791682636
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3967539701
Short name T348
Test name
Test status
Simulation time 3403453488 ps
CPU time 2.78 seconds
Started Jun 30 04:52:21 PM PDT 24
Finished Jun 30 04:52:25 PM PDT 24
Peak memory 182988 kb
Host smart-f67bd9e2-4769-4dd2-9384-00182ffe9aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967539701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3967539701
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3461443064
Short name T295
Test name
Test status
Simulation time 1091921295912 ps
CPU time 1000.69 seconds
Started Jun 30 04:52:25 PM PDT 24
Finished Jun 30 05:09:07 PM PDT 24
Peak memory 183348 kb
Host smart-7b47729d-77a3-4f7d-b95b-b931bdb024c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461443064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3461443064
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2131475878
Short name T395
Test name
Test status
Simulation time 14397548403 ps
CPU time 9.49 seconds
Started Jun 30 04:52:27 PM PDT 24
Finished Jun 30 04:52:36 PM PDT 24
Peak memory 183104 kb
Host smart-e22a520f-7ff5-476a-8023-eaba0c0d8d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131475878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2131475878
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1710317815
Short name T342
Test name
Test status
Simulation time 35626450637 ps
CPU time 14.81 seconds
Started Jun 30 04:52:30 PM PDT 24
Finished Jun 30 04:52:45 PM PDT 24
Peak memory 182856 kb
Host smart-9ad37cb2-e460-4df9-97fc-07d090f15615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710317815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1710317815
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.3911041260
Short name T259
Test name
Test status
Simulation time 176941545670 ps
CPU time 125.93 seconds
Started Jun 30 04:52:29 PM PDT 24
Finished Jun 30 04:54:35 PM PDT 24
Peak memory 191232 kb
Host smart-dd03239c-fcda-47b0-bf2b-2670ca8f90f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911041260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.3911041260
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3224230030
Short name T441
Test name
Test status
Simulation time 418419419057 ps
CPU time 156.62 seconds
Started Jun 30 04:52:28 PM PDT 24
Finished Jun 30 04:55:05 PM PDT 24
Peak memory 183076 kb
Host smart-3474a24b-36ff-483c-9120-2509b6c9a5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224230030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3224230030
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3968485888
Short name T253
Test name
Test status
Simulation time 215460343415 ps
CPU time 385.07 seconds
Started Jun 30 04:52:24 PM PDT 24
Finished Jun 30 04:58:50 PM PDT 24
Peak memory 191248 kb
Host smart-eec00bb1-fdc0-40a8-bf83-8824d1784704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968485888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3968485888
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1918949293
Short name T423
Test name
Test status
Simulation time 434186963 ps
CPU time 0.74 seconds
Started Jun 30 04:52:29 PM PDT 24
Finished Jun 30 04:52:30 PM PDT 24
Peak memory 182880 kb
Host smart-e093b35f-894d-40a9-9fa4-3055167895ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918949293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1918949293
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.776972392
Short name T151
Test name
Test status
Simulation time 139212216286 ps
CPU time 246.92 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 04:56:14 PM PDT 24
Peak memory 183048 kb
Host smart-6e0772e2-039a-436b-ac15-373c214c5fd2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776972392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.776972392
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2084923488
Short name T376
Test name
Test status
Simulation time 141037777276 ps
CPU time 202.5 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:55:33 PM PDT 24
Peak memory 183084 kb
Host smart-f2e9588c-089b-4277-a0c5-323a67231f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084923488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2084923488
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.38138487
Short name T17
Test name
Test status
Simulation time 432205587 ps
CPU time 0.72 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:52:12 PM PDT 24
Peak memory 213312 kb
Host smart-3c26e790-cdc9-4ea8-a788-0782be0ba3dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38138487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.38138487
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2990329938
Short name T363
Test name
Test status
Simulation time 472764316173 ps
CPU time 848.39 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 05:06:16 PM PDT 24
Peak memory 191216 kb
Host smart-f0058370-6663-4b25-8f57-fb9e0bf023e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990329938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2990329938
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2588231430
Short name T33
Test name
Test status
Simulation time 63299914903 ps
CPU time 1392.92 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 05:15:25 PM PDT 24
Peak memory 198248 kb
Host smart-66255a5c-956b-436d-bac4-30afa5ebf956
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588231430 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.2588231430
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.748799927
Short name T281
Test name
Test status
Simulation time 454891726233 ps
CPU time 239.09 seconds
Started Jun 30 04:52:31 PM PDT 24
Finished Jun 30 04:56:31 PM PDT 24
Peak memory 183068 kb
Host smart-80ed1905-1b21-4a88-9b33-124da28db5b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748799927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.748799927
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3901633874
Short name T387
Test name
Test status
Simulation time 184372991486 ps
CPU time 70.3 seconds
Started Jun 30 04:52:34 PM PDT 24
Finished Jun 30 04:53:45 PM PDT 24
Peak memory 183088 kb
Host smart-e6266a24-4ed9-413b-9305-aa9bad499411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901633874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3901633874
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2973017703
Short name T452
Test name
Test status
Simulation time 5901507519 ps
CPU time 51.52 seconds
Started Jun 30 04:52:34 PM PDT 24
Finished Jun 30 04:53:26 PM PDT 24
Peak memory 182952 kb
Host smart-5c863eee-84d6-4801-a651-69925f9fd33d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973017703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2973017703
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.4292996899
Short name T285
Test name
Test status
Simulation time 9530224480 ps
CPU time 8.69 seconds
Started Jun 30 04:52:41 PM PDT 24
Finished Jun 30 04:52:50 PM PDT 24
Peak memory 191256 kb
Host smart-2a4aee8c-6c79-4065-8721-60eb98d2d398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292996899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.4292996899
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1376593637
Short name T55
Test name
Test status
Simulation time 383702850574 ps
CPU time 748.25 seconds
Started Jun 30 04:52:32 PM PDT 24
Finished Jun 30 05:05:01 PM PDT 24
Peak memory 182980 kb
Host smart-37ff5480-ecc2-4d75-bb9d-efdc1bef7252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376593637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1376593637
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2729912528
Short name T13
Test name
Test status
Simulation time 85922558651 ps
CPU time 456.79 seconds
Started Jun 30 04:52:35 PM PDT 24
Finished Jun 30 05:00:12 PM PDT 24
Peak memory 206008 kb
Host smart-daa9a5ca-05d5-495a-89bb-593d7a11b210
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729912528 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2729912528
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2731064918
Short name T58
Test name
Test status
Simulation time 628973580486 ps
CPU time 362.29 seconds
Started Jun 30 04:52:36 PM PDT 24
Finished Jun 30 04:58:39 PM PDT 24
Peak memory 183348 kb
Host smart-86073b20-c599-456e-8217-4c0de4796f44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731064918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2731064918
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.59267148
Short name T413
Test name
Test status
Simulation time 14754138419 ps
CPU time 19.55 seconds
Started Jun 30 04:52:34 PM PDT 24
Finished Jun 30 04:52:54 PM PDT 24
Peak memory 183052 kb
Host smart-e050918a-71de-4372-91d0-7bfaeb9e88b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59267148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.59267148
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3512200273
Short name T146
Test name
Test status
Simulation time 236909221448 ps
CPU time 101.3 seconds
Started Jun 30 04:52:41 PM PDT 24
Finished Jun 30 04:54:23 PM PDT 24
Peak memory 191236 kb
Host smart-ec4b289e-c827-4455-81f5-6d0c32284cfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512200273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3512200273
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1613641465
Short name T54
Test name
Test status
Simulation time 278092808 ps
CPU time 0.83 seconds
Started Jun 30 04:52:41 PM PDT 24
Finished Jun 30 04:52:42 PM PDT 24
Peak memory 182896 kb
Host smart-8ca4bd20-e354-4e72-a7b2-37917b7f5129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613641465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1613641465
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3564244270
Short name T292
Test name
Test status
Simulation time 353671636091 ps
CPU time 539.44 seconds
Started Jun 30 04:52:32 PM PDT 24
Finished Jun 30 05:01:32 PM PDT 24
Peak memory 183060 kb
Host smart-fea79f72-0506-4a39-9581-ee69992ed1a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564244270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3564244270
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.160028137
Short name T453
Test name
Test status
Simulation time 195973547894 ps
CPU time 272.42 seconds
Started Jun 30 04:52:32 PM PDT 24
Finished Jun 30 04:57:05 PM PDT 24
Peak memory 183100 kb
Host smart-8666740f-5bc1-4557-80fd-20571fd28606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160028137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.160028137
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2902655932
Short name T9
Test name
Test status
Simulation time 179446968239 ps
CPU time 146.83 seconds
Started Jun 30 04:52:33 PM PDT 24
Finished Jun 30 04:55:00 PM PDT 24
Peak memory 191228 kb
Host smart-6d1cdfcc-2e28-4c39-9409-251b0639caae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902655932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2902655932
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3125957014
Short name T41
Test name
Test status
Simulation time 5458712752 ps
CPU time 8.96 seconds
Started Jun 30 04:52:34 PM PDT 24
Finished Jun 30 04:52:43 PM PDT 24
Peak memory 183088 kb
Host smart-9d280324-d0b1-4bab-a829-ed778ae7a2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125957014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3125957014
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1341418046
Short name T451
Test name
Test status
Simulation time 1799798925095 ps
CPU time 1038.91 seconds
Started Jun 30 04:52:33 PM PDT 24
Finished Jun 30 05:09:52 PM PDT 24
Peak memory 194432 kb
Host smart-faf542e3-d0e1-46f0-9e98-9c92e4b373c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341418046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1341418046
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1004171070
Short name T338
Test name
Test status
Simulation time 837795572189 ps
CPU time 436.86 seconds
Started Jun 30 04:52:33 PM PDT 24
Finished Jun 30 04:59:50 PM PDT 24
Peak memory 183076 kb
Host smart-613bb7ef-c134-43a3-b3e8-727eb5cbafcb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004171070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1004171070
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3130885034
Short name T421
Test name
Test status
Simulation time 412724703909 ps
CPU time 123.06 seconds
Started Jun 30 04:52:34 PM PDT 24
Finished Jun 30 04:54:38 PM PDT 24
Peak memory 183072 kb
Host smart-044b013e-06ef-4b61-a49a-eaabfb04608a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130885034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3130885034
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1761903044
Short name T110
Test name
Test status
Simulation time 62776330755 ps
CPU time 96.93 seconds
Started Jun 30 04:52:40 PM PDT 24
Finished Jun 30 04:54:18 PM PDT 24
Peak memory 191236 kb
Host smart-9aefab01-7360-4fc2-9394-9ad5c4706b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761903044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1761903044
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2293616623
Short name T280
Test name
Test status
Simulation time 66024095635 ps
CPU time 113.99 seconds
Started Jun 30 04:52:35 PM PDT 24
Finished Jun 30 04:54:29 PM PDT 24
Peak memory 191312 kb
Host smart-503b44d3-f0bb-4fc9-b1a5-1faa255ee5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293616623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2293616623
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.746998396
Short name T221
Test name
Test status
Simulation time 273688842582 ps
CPU time 263.55 seconds
Started Jun 30 04:52:32 PM PDT 24
Finished Jun 30 04:56:56 PM PDT 24
Peak memory 191288 kb
Host smart-6a0c6912-bbe9-47fb-89db-eb5324d9ad5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746998396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
746998396
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3649047046
Short name T345
Test name
Test status
Simulation time 354164217478 ps
CPU time 611.62 seconds
Started Jun 30 04:52:33 PM PDT 24
Finished Jun 30 05:02:45 PM PDT 24
Peak memory 183048 kb
Host smart-5149f615-e506-43ea-8be5-639928be702e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649047046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3649047046
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3674636779
Short name T424
Test name
Test status
Simulation time 30139148663 ps
CPU time 20.07 seconds
Started Jun 30 04:52:38 PM PDT 24
Finished Jun 30 04:52:59 PM PDT 24
Peak memory 183008 kb
Host smart-8a272ec7-ba00-409a-97f4-8efc9f0ccb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674636779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3674636779
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.279656988
Short name T425
Test name
Test status
Simulation time 352834609404 ps
CPU time 171.76 seconds
Started Jun 30 04:52:32 PM PDT 24
Finished Jun 30 04:55:25 PM PDT 24
Peak memory 191260 kb
Host smart-04d75719-dfeb-45e3-908a-1342f350a837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279656988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.279656988
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3189511792
Short name T102
Test name
Test status
Simulation time 34987588091 ps
CPU time 59.23 seconds
Started Jun 30 04:52:39 PM PDT 24
Finished Jun 30 04:53:39 PM PDT 24
Peak memory 191308 kb
Host smart-5e5275f8-d4d4-4f36-a695-964a991e7988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189511792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3189511792
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.2692361369
Short name T45
Test name
Test status
Simulation time 50578738326 ps
CPU time 174.41 seconds
Started Jun 30 04:52:38 PM PDT 24
Finished Jun 30 04:55:33 PM PDT 24
Peak memory 205944 kb
Host smart-b626b7e4-70a9-4e74-925d-bde24f5394c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692361369 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.2692361369
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3688574263
Short name T440
Test name
Test status
Simulation time 1216137273205 ps
CPU time 676.7 seconds
Started Jun 30 04:52:40 PM PDT 24
Finished Jun 30 05:03:57 PM PDT 24
Peak memory 182492 kb
Host smart-1b471dc5-8518-42d1-8c80-3adcaf35562a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688574263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3688574263
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3134105585
Short name T369
Test name
Test status
Simulation time 114268150634 ps
CPU time 144.89 seconds
Started Jun 30 04:52:39 PM PDT 24
Finished Jun 30 04:55:04 PM PDT 24
Peak memory 183084 kb
Host smart-362ba90f-c400-4638-82e7-34c0c0afb646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134105585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3134105585
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1427075883
Short name T312
Test name
Test status
Simulation time 145269798891 ps
CPU time 426.59 seconds
Started Jun 30 04:52:39 PM PDT 24
Finished Jun 30 04:59:46 PM PDT 24
Peak memory 191316 kb
Host smart-a61915ac-0d99-4cf3-b206-e25dc005631f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427075883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1427075883
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4012139768
Short name T228
Test name
Test status
Simulation time 21757949473 ps
CPU time 36.04 seconds
Started Jun 30 04:52:38 PM PDT 24
Finished Jun 30 04:53:15 PM PDT 24
Peak memory 183084 kb
Host smart-a0064c39-d9ad-4c39-a3fa-ed36e287f95f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012139768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.4012139768
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1565112040
Short name T436
Test name
Test status
Simulation time 102986032997 ps
CPU time 126.25 seconds
Started Jun 30 04:52:40 PM PDT 24
Finished Jun 30 04:54:47 PM PDT 24
Peak memory 183080 kb
Host smart-b980e48c-06ff-4308-a913-ef3e1d1fe1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565112040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1565112040
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2601919201
Short name T442
Test name
Test status
Simulation time 159890668741 ps
CPU time 123.31 seconds
Started Jun 30 04:52:39 PM PDT 24
Finished Jun 30 04:54:43 PM PDT 24
Peak memory 191288 kb
Host smart-52d60b01-49ec-468c-8d0a-c11c2da12c0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601919201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2601919201
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2000351330
Short name T156
Test name
Test status
Simulation time 34916997304 ps
CPU time 159.09 seconds
Started Jun 30 04:52:40 PM PDT 24
Finished Jun 30 04:55:20 PM PDT 24
Peak memory 183104 kb
Host smart-5f83bf83-699f-458e-ba40-50a08e75f51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000351330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2000351330
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.4102991890
Short name T455
Test name
Test status
Simulation time 88352480058 ps
CPU time 341.29 seconds
Started Jun 30 04:52:37 PM PDT 24
Finished Jun 30 04:58:19 PM PDT 24
Peak memory 205880 kb
Host smart-77e1cba4-cba8-44bb-bc91-f3960e46a876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102991890 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.4102991890
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.881462170
Short name T279
Test name
Test status
Simulation time 962118188655 ps
CPU time 513.53 seconds
Started Jun 30 04:52:39 PM PDT 24
Finished Jun 30 05:01:13 PM PDT 24
Peak memory 183084 kb
Host smart-e5e6a1ce-e4e2-42fd-99c6-ac5d0caee3e6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881462170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.881462170
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.70343032
Short name T430
Test name
Test status
Simulation time 686976759196 ps
CPU time 124.35 seconds
Started Jun 30 04:52:38 PM PDT 24
Finished Jun 30 04:54:44 PM PDT 24
Peak memory 183100 kb
Host smart-747d53ad-1b7c-433d-96a5-a2114e40666a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70343032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.70343032
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.339303741
Short name T225
Test name
Test status
Simulation time 45881283624 ps
CPU time 93.13 seconds
Started Jun 30 04:52:39 PM PDT 24
Finished Jun 30 04:54:12 PM PDT 24
Peak memory 183096 kb
Host smart-823eaada-b6db-468b-ad44-4b056a65f4f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339303741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.339303741
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3948138361
Short name T114
Test name
Test status
Simulation time 118557623909 ps
CPU time 58.37 seconds
Started Jun 30 04:52:48 PM PDT 24
Finished Jun 30 04:53:47 PM PDT 24
Peak memory 183108 kb
Host smart-789ec0b3-3738-4f41-acad-595a569dfa22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948138361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3948138361
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.591636923
Short name T414
Test name
Test status
Simulation time 1220932966804 ps
CPU time 400.14 seconds
Started Jun 30 04:52:52 PM PDT 24
Finished Jun 30 04:59:32 PM PDT 24
Peak memory 191552 kb
Host smart-aba014a2-f173-4db8-8b3b-9c819bd7963d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591636923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
591636923
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3564722442
Short name T397
Test name
Test status
Simulation time 125274638159 ps
CPU time 180.51 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 04:55:50 PM PDT 24
Peak memory 183096 kb
Host smart-688607c1-2091-406e-9e39-62c654b4359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564722442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3564722442
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1749529805
Short name T241
Test name
Test status
Simulation time 173718614974 ps
CPU time 692.13 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 05:04:22 PM PDT 24
Peak memory 191252 kb
Host smart-ad307b2e-1c40-4133-b545-f54c9911560a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749529805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1749529805
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1263792803
Short name T316
Test name
Test status
Simulation time 8787934761 ps
CPU time 7.4 seconds
Started Jun 30 04:52:46 PM PDT 24
Finished Jun 30 04:52:54 PM PDT 24
Peak memory 183008 kb
Host smart-20e122e0-5ce5-42bc-b933-59186ad23265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263792803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1263792803
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.768476665
Short name T315
Test name
Test status
Simulation time 388481342523 ps
CPU time 1994.82 seconds
Started Jun 30 04:52:46 PM PDT 24
Finished Jun 30 05:26:02 PM PDT 24
Peak memory 195972 kb
Host smart-cca6723f-e8c2-4f27-a832-35dc3050ffbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768476665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
768476665
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.195500822
Short name T311
Test name
Test status
Simulation time 404973087011 ps
CPU time 336.67 seconds
Started Jun 30 04:52:46 PM PDT 24
Finished Jun 30 04:58:24 PM PDT 24
Peak memory 182988 kb
Host smart-fd031987-fa6b-4a9e-b729-6aeb3870e92f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195500822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.rv_timer_cfg_update_on_fly.195500822
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.823773056
Short name T435
Test name
Test status
Simulation time 172298910721 ps
CPU time 65.28 seconds
Started Jun 30 04:52:47 PM PDT 24
Finished Jun 30 04:53:53 PM PDT 24
Peak memory 182992 kb
Host smart-c90a8336-c564-4775-8aaa-8f000dca3635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823773056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.823773056
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3543150559
Short name T186
Test name
Test status
Simulation time 100805044915 ps
CPU time 156.92 seconds
Started Jun 30 04:52:47 PM PDT 24
Finished Jun 30 04:55:25 PM PDT 24
Peak memory 191232 kb
Host smart-54ad3340-a8cb-4b88-83a1-75685fffa546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543150559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3543150559
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1163280144
Short name T411
Test name
Test status
Simulation time 94287842423 ps
CPU time 319.05 seconds
Started Jun 30 04:52:48 PM PDT 24
Finished Jun 30 04:58:07 PM PDT 24
Peak memory 183084 kb
Host smart-f87ed370-5132-4854-a874-7d6d498ca486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163280144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1163280144
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3832894979
Short name T438
Test name
Test status
Simulation time 10002664009 ps
CPU time 5.9 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:52:15 PM PDT 24
Peak memory 183088 kb
Host smart-e06c9cd9-d39d-4ba2-ae2c-4e0b0ac7e619
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832894979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3832894979
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1965943511
Short name T403
Test name
Test status
Simulation time 258033806748 ps
CPU time 196.13 seconds
Started Jun 30 04:52:09 PM PDT 24
Finished Jun 30 04:55:26 PM PDT 24
Peak memory 183000 kb
Host smart-1db0826d-9bb0-4d55-8187-6e13178025c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965943511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1965943511
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.104794282
Short name T101
Test name
Test status
Simulation time 22957000041 ps
CPU time 68.88 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:53:19 PM PDT 24
Peak memory 191288 kb
Host smart-d16fbafa-d5b3-4f4d-a6d0-c59cf81a30af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104794282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.104794282
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2069416629
Short name T371
Test name
Test status
Simulation time 2295558393 ps
CPU time 11.1 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:52:20 PM PDT 24
Peak memory 182872 kb
Host smart-5bf7f7bc-90d1-4823-9380-73c3f2e12517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069416629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2069416629
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2648604424
Short name T16
Test name
Test status
Simulation time 94947853 ps
CPU time 0.87 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 04:52:09 PM PDT 24
Peak memory 215812 kb
Host smart-4e3bae42-7391-4fee-9a9d-321d4dfd36d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648604424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2648604424
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.907571269
Short name T431
Test name
Test status
Simulation time 584843270205 ps
CPU time 104.96 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 04:54:35 PM PDT 24
Peak memory 183072 kb
Host smart-81c9cdb7-e173-490f-a2b0-785ae1bfe996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907571269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.907571269
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1072458579
Short name T337
Test name
Test status
Simulation time 87893129095 ps
CPU time 42.11 seconds
Started Jun 30 04:52:47 PM PDT 24
Finished Jun 30 04:53:30 PM PDT 24
Peak memory 194672 kb
Host smart-497284c6-a269-4cd1-ac4c-a23fd772a07f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072458579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1072458579
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2814155767
Short name T377
Test name
Test status
Simulation time 138976654 ps
CPU time 0.75 seconds
Started Jun 30 04:52:48 PM PDT 24
Finished Jun 30 04:52:50 PM PDT 24
Peak memory 182952 kb
Host smart-f890907d-e0d3-481f-8f82-3ca6801a89be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814155767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2814155767
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.643221094
Short name T269
Test name
Test status
Simulation time 135997088208 ps
CPU time 126.01 seconds
Started Jun 30 04:52:57 PM PDT 24
Finished Jun 30 04:55:04 PM PDT 24
Peak memory 183032 kb
Host smart-640ed61b-c55a-4b74-85d9-240790cae0ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643221094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.643221094
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3843508860
Short name T383
Test name
Test status
Simulation time 12078441543 ps
CPU time 17.54 seconds
Started Jun 30 04:52:47 PM PDT 24
Finished Jun 30 04:53:05 PM PDT 24
Peak memory 183100 kb
Host smart-dede583a-2076-41d8-b6b5-7ea713681e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843508860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3843508860
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.4116097009
Short name T113
Test name
Test status
Simulation time 77723950564 ps
CPU time 405.49 seconds
Started Jun 30 04:52:50 PM PDT 24
Finished Jun 30 04:59:36 PM PDT 24
Peak memory 191248 kb
Host smart-bbfe0273-a962-4ea6-a72a-c6bb6ba5f623
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116097009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.4116097009
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2713431245
Short name T119
Test name
Test status
Simulation time 363480827875 ps
CPU time 292.22 seconds
Started Jun 30 04:52:48 PM PDT 24
Finished Jun 30 04:57:41 PM PDT 24
Peak memory 191268 kb
Host smart-3ba50d55-686a-44cc-a22f-668f17483980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713431245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2713431245
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2121102217
Short name T333
Test name
Test status
Simulation time 1401287729637 ps
CPU time 2181.79 seconds
Started Jun 30 04:52:46 PM PDT 24
Finished Jun 30 05:29:09 PM PDT 24
Peak memory 182940 kb
Host smart-60774cb2-0feb-4431-a75b-647f70939771
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121102217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2121102217
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2296458416
Short name T407
Test name
Test status
Simulation time 559847797872 ps
CPU time 238.74 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 04:56:49 PM PDT 24
Peak memory 183096 kb
Host smart-ee3a2a5b-3e7c-4d65-a417-fc0930582bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296458416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2296458416
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3200799252
Short name T350
Test name
Test status
Simulation time 165588320238 ps
CPU time 138.4 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 04:55:08 PM PDT 24
Peak memory 190128 kb
Host smart-63188142-62ae-4b72-b4b4-fbaa7f3e3ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200799252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3200799252
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2501717614
Short name T282
Test name
Test status
Simulation time 241570319410 ps
CPU time 123.37 seconds
Started Jun 30 04:52:48 PM PDT 24
Finished Jun 30 04:54:52 PM PDT 24
Peak memory 195132 kb
Host smart-e964d99b-1b47-4329-aeea-3749417d3e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501717614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2501717614
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.201501051
Short name T365
Test name
Test status
Simulation time 732263025696 ps
CPU time 283.19 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 04:57:33 PM PDT 24
Peak memory 183080 kb
Host smart-a02adc94-8647-4a55-abd9-0e2d71621992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201501051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
201501051
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2040459222
Short name T12
Test name
Test status
Simulation time 48902169409 ps
CPU time 204.86 seconds
Started Jun 30 04:52:51 PM PDT 24
Finished Jun 30 04:56:16 PM PDT 24
Peak memory 205996 kb
Host smart-1690aeae-8ba6-45e8-ba5c-df6b6f4fa4b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040459222 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2040459222
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1177244471
Short name T266
Test name
Test status
Simulation time 1833630587010 ps
CPU time 583.1 seconds
Started Jun 30 04:52:48 PM PDT 24
Finished Jun 30 05:02:32 PM PDT 24
Peak memory 183080 kb
Host smart-730e3105-0c5b-4707-9f61-263646bb2fa7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177244471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1177244471
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.4076020096
Short name T382
Test name
Test status
Simulation time 61558174777 ps
CPU time 33.46 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 04:53:24 PM PDT 24
Peak memory 183060 kb
Host smart-9023c926-011d-4a1d-bee6-c6d0e56ef4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076020096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.4076020096
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.973903654
Short name T248
Test name
Test status
Simulation time 508962516049 ps
CPU time 150.44 seconds
Started Jun 30 04:52:57 PM PDT 24
Finished Jun 30 04:55:28 PM PDT 24
Peak memory 191228 kb
Host smart-ad2b7655-9b8f-416b-a94e-7dee66712dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973903654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.973903654
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2406556216
Short name T220
Test name
Test status
Simulation time 273510491865 ps
CPU time 158.37 seconds
Started Jun 30 04:52:46 PM PDT 24
Finished Jun 30 04:55:26 PM PDT 24
Peak memory 183040 kb
Host smart-b789b055-3e19-4729-b473-8b4fdd7000de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406556216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2406556216
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2577719282
Short name T420
Test name
Test status
Simulation time 101076480296 ps
CPU time 154.82 seconds
Started Jun 30 04:52:48 PM PDT 24
Finished Jun 30 04:55:24 PM PDT 24
Peak memory 183100 kb
Host smart-9ed028f7-4014-4746-8aa6-715e99af75c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577719282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2577719282
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.2801796557
Short name T216
Test name
Test status
Simulation time 367078112761 ps
CPU time 238.37 seconds
Started Jun 30 04:52:52 PM PDT 24
Finished Jun 30 04:56:51 PM PDT 24
Peak memory 191532 kb
Host smart-a7a87f41-e9d7-42bf-8265-df6470502a74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801796557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2801796557
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3769452670
Short name T302
Test name
Test status
Simulation time 99506184479 ps
CPU time 1729.05 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 05:21:39 PM PDT 24
Peak memory 182104 kb
Host smart-07351150-bf24-4d28-b50d-e79dc9cfb240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769452670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3769452670
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3040579642
Short name T147
Test name
Test status
Simulation time 418656620429 ps
CPU time 608.83 seconds
Started Jun 30 04:52:52 PM PDT 24
Finished Jun 30 05:03:01 PM PDT 24
Peak memory 191556 kb
Host smart-a327e097-2647-4844-9b65-69d736c76e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040579642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3040579642
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.1843169764
Short name T34
Test name
Test status
Simulation time 32837136229 ps
CPU time 262.85 seconds
Started Jun 30 04:52:46 PM PDT 24
Finished Jun 30 04:57:10 PM PDT 24
Peak memory 205992 kb
Host smart-03d50883-1771-4f5c-a3e7-3259d3cd0faf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843169764 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.1843169764
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2300690769
Short name T201
Test name
Test status
Simulation time 8163028605 ps
CPU time 12.65 seconds
Started Jun 30 04:52:53 PM PDT 24
Finished Jun 30 04:53:07 PM PDT 24
Peak memory 183076 kb
Host smart-3383e692-a497-44e7-a1bc-798d5b719a54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300690769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2300690769
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1327284242
Short name T405
Test name
Test status
Simulation time 821167058150 ps
CPU time 274.36 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 04:57:25 PM PDT 24
Peak memory 183060 kb
Host smart-e15d2f09-61cc-4c4a-921b-10695e6e7ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327284242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1327284242
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1670595379
Short name T327
Test name
Test status
Simulation time 118322776836 ps
CPU time 252.03 seconds
Started Jun 30 04:52:49 PM PDT 24
Finished Jun 30 04:57:02 PM PDT 24
Peak memory 191268 kb
Host smart-d7792348-13bd-4864-9b98-2e2dbd85495b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670595379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1670595379
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3748482492
Short name T372
Test name
Test status
Simulation time 1268687176 ps
CPU time 1.05 seconds
Started Jun 30 04:52:54 PM PDT 24
Finished Jun 30 04:52:56 PM PDT 24
Peak memory 191856 kb
Host smart-bac5c299-51dd-4119-8d09-f068822c0b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748482492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3748482492
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.635712926
Short name T38
Test name
Test status
Simulation time 1250031740377 ps
CPU time 242.6 seconds
Started Jun 30 04:52:54 PM PDT 24
Finished Jun 30 04:56:58 PM PDT 24
Peak memory 182988 kb
Host smart-5d2b2184-db11-4a3e-bb6c-e7573bb93148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635712926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all.
635712926
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.4261372519
Short name T374
Test name
Test status
Simulation time 396781401544 ps
CPU time 100.44 seconds
Started Jun 30 04:52:53 PM PDT 24
Finished Jun 30 04:54:35 PM PDT 24
Peak memory 183100 kb
Host smart-4696e25d-bd30-4411-88cf-e0ff45a6f08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261372519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4261372519
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2221438047
Short name T148
Test name
Test status
Simulation time 35862956079 ps
CPU time 112.14 seconds
Started Jun 30 04:52:55 PM PDT 24
Finished Jun 30 04:54:48 PM PDT 24
Peak memory 194056 kb
Host smart-5233f259-3780-45a6-9325-ad4c99560008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221438047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2221438047
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.114471096
Short name T444
Test name
Test status
Simulation time 687993732628 ps
CPU time 521.83 seconds
Started Jun 30 04:52:54 PM PDT 24
Finished Jun 30 05:01:36 PM PDT 24
Peak memory 183080 kb
Host smart-cdbdbc0a-4ae3-4051-85b0-eee2c1adfa52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114471096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.114471096
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3421915695
Short name T98
Test name
Test status
Simulation time 14374877427 ps
CPU time 24.31 seconds
Started Jun 30 04:52:56 PM PDT 24
Finished Jun 30 04:53:21 PM PDT 24
Peak memory 183044 kb
Host smart-00e896b8-7548-416e-845e-e4029a89af81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421915695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3421915695
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.487043038
Short name T391
Test name
Test status
Simulation time 123490228612 ps
CPU time 173.7 seconds
Started Jun 30 04:52:55 PM PDT 24
Finished Jun 30 04:55:50 PM PDT 24
Peak memory 182992 kb
Host smart-10b4f56f-2597-479b-b685-a3c74c4b282f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487043038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.487043038
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.34589590
Short name T313
Test name
Test status
Simulation time 348093877483 ps
CPU time 197.89 seconds
Started Jun 30 04:52:54 PM PDT 24
Finished Jun 30 04:56:13 PM PDT 24
Peak memory 191232 kb
Host smart-64c8f1ee-3134-4765-9e73-e95b0d1d07aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34589590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.34589590
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3676308983
Short name T298
Test name
Test status
Simulation time 74822122536 ps
CPU time 66.65 seconds
Started Jun 30 04:52:53 PM PDT 24
Finished Jun 30 04:54:01 PM PDT 24
Peak memory 191216 kb
Host smart-48b335da-4de4-47b8-920f-e012de771cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676308983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3676308983
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.4263413139
Short name T37
Test name
Test status
Simulation time 71285517 ps
CPU time 0.68 seconds
Started Jun 30 04:52:54 PM PDT 24
Finished Jun 30 04:52:55 PM PDT 24
Peak memory 182928 kb
Host smart-b2255d24-4b62-480b-a0b8-ba9a7962600b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263413139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.4263413139
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.135601992
Short name T89
Test name
Test status
Simulation time 161563751836 ps
CPU time 270.89 seconds
Started Jun 30 04:52:59 PM PDT 24
Finished Jun 30 04:57:30 PM PDT 24
Peak memory 183092 kb
Host smart-539bb78a-62ee-4436-9253-381618d87814
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135601992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.135601992
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.339946362
Short name T366
Test name
Test status
Simulation time 286470782476 ps
CPU time 180.41 seconds
Started Jun 30 04:52:55 PM PDT 24
Finished Jun 30 04:55:56 PM PDT 24
Peak memory 183000 kb
Host smart-fe062d19-db92-4516-a154-244bc80cd24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339946362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.339946362
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.331471903
Short name T400
Test name
Test status
Simulation time 13128258 ps
CPU time 0.52 seconds
Started Jun 30 04:52:55 PM PDT 24
Finished Jun 30 04:52:56 PM PDT 24
Peak memory 182932 kb
Host smart-b37cebbf-9e74-4f12-8144-74215690a344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331471903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.331471903
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1836030616
Short name T223
Test name
Test status
Simulation time 120042978603 ps
CPU time 359.3 seconds
Started Jun 30 04:52:58 PM PDT 24
Finished Jun 30 04:58:58 PM PDT 24
Peak memory 195792 kb
Host smart-0b49a002-e53e-4b49-a95e-e0e09a49710c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836030616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1836030616
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.4014183986
Short name T396
Test name
Test status
Simulation time 60411443873 ps
CPU time 47.96 seconds
Started Jun 30 04:53:03 PM PDT 24
Finished Jun 30 04:53:52 PM PDT 24
Peak memory 182984 kb
Host smart-e0f4d601-868f-4366-b9ee-67e40c51faa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014183986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.4014183986
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3483619884
Short name T219
Test name
Test status
Simulation time 614919999461 ps
CPU time 72.86 seconds
Started Jun 30 04:52:59 PM PDT 24
Finished Jun 30 04:54:12 PM PDT 24
Peak memory 182904 kb
Host smart-18fd69f6-8c12-4e50-bacc-886d3677c01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483619884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3483619884
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1085902206
Short name T388
Test name
Test status
Simulation time 35145575531 ps
CPU time 69.11 seconds
Started Jun 30 04:53:03 PM PDT 24
Finished Jun 30 04:54:13 PM PDT 24
Peak memory 194712 kb
Host smart-5883c697-9785-4a81-9345-68a36f612f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085902206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1085902206
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2624683907
Short name T160
Test name
Test status
Simulation time 478230430446 ps
CPU time 3219.82 seconds
Started Jun 30 04:53:02 PM PDT 24
Finished Jun 30 05:46:42 PM PDT 24
Peak memory 195164 kb
Host smart-955743bc-96ac-49d9-9769-3dd33db166a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624683907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2624683907
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.638141895
Short name T448
Test name
Test status
Simulation time 114507454234 ps
CPU time 158.56 seconds
Started Jun 30 04:52:07 PM PDT 24
Finished Jun 30 04:54:47 PM PDT 24
Peak memory 183100 kb
Host smart-e0b60616-e8fd-4e12-9cfe-59c130c72695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638141895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.638141895
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.783936072
Short name T128
Test name
Test status
Simulation time 32191672007 ps
CPU time 1238.28 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 05:12:54 PM PDT 24
Peak memory 183064 kb
Host smart-8dc033a9-524b-437a-a956-b9154d9cd2db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783936072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.783936072
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.1873105228
Short name T187
Test name
Test status
Simulation time 81704902152 ps
CPU time 130.92 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:54:20 PM PDT 24
Peak memory 191036 kb
Host smart-20696bc3-b747-401d-a9ae-36c2a28ee8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873105228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.1873105228
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3023145811
Short name T454
Test name
Test status
Simulation time 667840198127 ps
CPU time 250.36 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:56:22 PM PDT 24
Peak memory 191180 kb
Host smart-d375fd73-ada4-4952-9560-5e677b29ff29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023145811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3023145811
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1227985306
Short name T14
Test name
Test status
Simulation time 108387487432 ps
CPU time 898.08 seconds
Started Jun 30 04:52:06 PM PDT 24
Finished Jun 30 05:07:06 PM PDT 24
Peak memory 205980 kb
Host smart-e3abe3c0-07ad-44be-9523-c8b6101496d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227985306 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1227985306
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.rv_timer_random.2900949811
Short name T135
Test name
Test status
Simulation time 1027741796215 ps
CPU time 319.03 seconds
Started Jun 30 04:53:04 PM PDT 24
Finished Jun 30 04:58:23 PM PDT 24
Peak memory 191256 kb
Host smart-d88fdad9-ed2a-4a67-927f-4b8d0f23d5a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900949811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2900949811
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.78783740
Short name T308
Test name
Test status
Simulation time 271446001318 ps
CPU time 244.71 seconds
Started Jun 30 04:53:03 PM PDT 24
Finished Jun 30 04:57:09 PM PDT 24
Peak memory 191232 kb
Host smart-99c8a53f-f136-47ea-afd6-a824d179799c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78783740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.78783740
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1912056516
Short name T222
Test name
Test status
Simulation time 160721321982 ps
CPU time 271.39 seconds
Started Jun 30 04:53:02 PM PDT 24
Finished Jun 30 04:57:33 PM PDT 24
Peak memory 191272 kb
Host smart-43bfdee9-3b22-42cc-9399-d62f21dfa41d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912056516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1912056516
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3293574934
Short name T209
Test name
Test status
Simulation time 178252012615 ps
CPU time 213.36 seconds
Started Jun 30 04:53:02 PM PDT 24
Finished Jun 30 04:56:35 PM PDT 24
Peak memory 191188 kb
Host smart-a48c82c0-b1ef-4591-b8f5-db37abc23328
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293574934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3293574934
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3528772221
Short name T115
Test name
Test status
Simulation time 23834692535 ps
CPU time 45.44 seconds
Started Jun 30 04:53:02 PM PDT 24
Finished Jun 30 04:53:48 PM PDT 24
Peak memory 183072 kb
Host smart-0168e3a6-829b-4010-a87e-d86005d16f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528772221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3528772221
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1076562009
Short name T349
Test name
Test status
Simulation time 276236175212 ps
CPU time 144.09 seconds
Started Jun 30 04:53:00 PM PDT 24
Finished Jun 30 04:55:25 PM PDT 24
Peak memory 191288 kb
Host smart-e63767f3-4b93-4ea1-9b3f-6867d39758be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076562009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1076562009
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2974591626
Short name T171
Test name
Test status
Simulation time 2905425130 ps
CPU time 2.69 seconds
Started Jun 30 04:53:03 PM PDT 24
Finished Jun 30 04:53:06 PM PDT 24
Peak memory 182992 kb
Host smart-5fe3e72f-e42e-4f12-9f19-4b4dc06f6afe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974591626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2974591626
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3892519797
Short name T398
Test name
Test status
Simulation time 34374376690 ps
CPU time 49.89 seconds
Started Jun 30 04:52:11 PM PDT 24
Finished Jun 30 04:53:03 PM PDT 24
Peak memory 183088 kb
Host smart-e410c3b2-053a-4b2a-a928-593658a14360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892519797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3892519797
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.508823770
Short name T198
Test name
Test status
Simulation time 385572250310 ps
CPU time 559.23 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 05:01:29 PM PDT 24
Peak memory 194920 kb
Host smart-a04520b8-46ad-4ac6-b6aa-755f00e8f1a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508823770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.508823770
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4033213669
Short name T233
Test name
Test status
Simulation time 88881571750 ps
CPU time 80.18 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:53:30 PM PDT 24
Peak memory 195272 kb
Host smart-5284ad4e-00e0-47f0-9a71-58989836529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033213669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4033213669
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.504287406
Short name T50
Test name
Test status
Simulation time 1737921944268 ps
CPU time 658.25 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 05:03:08 PM PDT 24
Peak memory 191156 kb
Host smart-ed030fd4-eca6-425b-8e17-131a625477ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504287406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.504287406
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.3564266233
Short name T47
Test name
Test status
Simulation time 35045142770 ps
CPU time 143.22 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:54:35 PM PDT 24
Peak memory 197796 kb
Host smart-92516cec-a07e-4d62-bb5b-19c6bbc8e5c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564266233 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.3564266233
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3791973083
Short name T358
Test name
Test status
Simulation time 39663724822 ps
CPU time 64.24 seconds
Started Jun 30 04:53:09 PM PDT 24
Finished Jun 30 04:54:14 PM PDT 24
Peak memory 183060 kb
Host smart-d07386df-c59f-4616-aaa7-c542cfdde905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791973083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3791973083
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.680508399
Short name T264
Test name
Test status
Simulation time 91156879478 ps
CPU time 101.52 seconds
Started Jun 30 04:53:09 PM PDT 24
Finished Jun 30 04:54:52 PM PDT 24
Peak memory 191184 kb
Host smart-d1629ae9-7022-4591-96fe-a3dd59d35181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680508399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.680508399
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.517280197
Short name T288
Test name
Test status
Simulation time 45139674282 ps
CPU time 45.47 seconds
Started Jun 30 04:53:08 PM PDT 24
Finished Jun 30 04:53:54 PM PDT 24
Peak memory 191568 kb
Host smart-cd7321d9-ba90-457e-a7cd-e93e6f642a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517280197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.517280197
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.996342777
Short name T276
Test name
Test status
Simulation time 20407358294 ps
CPU time 33.56 seconds
Started Jun 30 04:53:10 PM PDT 24
Finished Jun 30 04:53:44 PM PDT 24
Peak memory 183084 kb
Host smart-869ff214-8cfd-42ef-80a6-7ec9aee53767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996342777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.996342777
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1979623188
Short name T258
Test name
Test status
Simulation time 1477185723075 ps
CPU time 1641.6 seconds
Started Jun 30 04:53:09 PM PDT 24
Finished Jun 30 05:20:31 PM PDT 24
Peak memory 191276 kb
Host smart-f8616e07-189d-42a9-8665-a25a3bec1a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979623188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1979623188
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2153459653
Short name T293
Test name
Test status
Simulation time 159788650169 ps
CPU time 150.8 seconds
Started Jun 30 04:53:08 PM PDT 24
Finished Jun 30 04:55:40 PM PDT 24
Peak memory 191180 kb
Host smart-6016244d-e5d0-4ccd-8003-66cd14b09994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153459653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2153459653
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1446623911
Short name T175
Test name
Test status
Simulation time 145381254896 ps
CPU time 304.38 seconds
Started Jun 30 04:53:09 PM PDT 24
Finished Jun 30 04:58:14 PM PDT 24
Peak memory 191268 kb
Host smart-4450ba25-3f1d-492f-b859-6240a16bdbdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446623911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1446623911
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2048664660
Short name T317
Test name
Test status
Simulation time 71449105942 ps
CPU time 1370.29 seconds
Started Jun 30 04:53:11 PM PDT 24
Finished Jun 30 05:16:01 PM PDT 24
Peak memory 183056 kb
Host smart-c3ede24e-bb88-46b2-b9dd-5f966bd4c7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048664660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2048664660
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1624959496
Short name T158
Test name
Test status
Simulation time 645034958827 ps
CPU time 340.03 seconds
Started Jun 30 04:53:09 PM PDT 24
Finished Jun 30 04:58:50 PM PDT 24
Peak memory 191176 kb
Host smart-f831b788-045d-4fea-8782-a9cab08bd2c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624959496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1624959496
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3975621455
Short name T224
Test name
Test status
Simulation time 737857329163 ps
CPU time 624.71 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 05:02:37 PM PDT 24
Peak memory 182992 kb
Host smart-2f444125-adb7-4f7d-b3a1-64b7e6179e26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975621455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3975621455
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4029647452
Short name T385
Test name
Test status
Simulation time 176245488399 ps
CPU time 132.26 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:54:24 PM PDT 24
Peak memory 183008 kb
Host smart-25f601c9-7322-4b51-91fe-31eda0d4676c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029647452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4029647452
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3285617185
Short name T417
Test name
Test status
Simulation time 9234050310 ps
CPU time 3.48 seconds
Started Jun 30 04:52:12 PM PDT 24
Finished Jun 30 04:52:17 PM PDT 24
Peak memory 182984 kb
Host smart-d321c993-e1aa-453e-b077-039f1f28fe64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285617185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3285617185
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.304648350
Short name T227
Test name
Test status
Simulation time 1905858953 ps
CPU time 3.74 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:52:13 PM PDT 24
Peak memory 192068 kb
Host smart-5a51c234-9d91-465a-bd97-c8a4a55d008c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304648350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.304648350
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.533254996
Short name T447
Test name
Test status
Simulation time 303489618176 ps
CPU time 126.55 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 04:54:21 PM PDT 24
Peak memory 182992 kb
Host smart-bc99bb15-a0f3-4f26-8a3f-63e5f6c27e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533254996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.533254996
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1618146108
Short name T30
Test name
Test status
Simulation time 14473134776 ps
CPU time 155.91 seconds
Started Jun 30 04:52:08 PM PDT 24
Finished Jun 30 04:54:45 PM PDT 24
Peak memory 196820 kb
Host smart-5f68a1ab-207e-41d8-ba95-44fd6ea73d07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618146108 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1618146108
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.rv_timer_random.1375425764
Short name T164
Test name
Test status
Simulation time 471506284001 ps
CPU time 2032 seconds
Started Jun 30 04:53:09 PM PDT 24
Finished Jun 30 05:27:02 PM PDT 24
Peak memory 191284 kb
Host smart-ef0cae6c-495f-4034-8934-a733156f6522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375425764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1375425764
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3687836134
Short name T159
Test name
Test status
Simulation time 130613239900 ps
CPU time 215.54 seconds
Started Jun 30 04:53:15 PM PDT 24
Finished Jun 30 04:56:52 PM PDT 24
Peak memory 191188 kb
Host smart-1f68ea74-359c-4766-bf21-64335f7cc8e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687836134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3687836134
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1444725435
Short name T111
Test name
Test status
Simulation time 98014433114 ps
CPU time 81.69 seconds
Started Jun 30 04:53:16 PM PDT 24
Finished Jun 30 04:54:38 PM PDT 24
Peak memory 191176 kb
Host smart-ee26ff95-d6c0-439b-9103-6eceae4a2469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444725435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1444725435
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.208498460
Short name T214
Test name
Test status
Simulation time 132444584611 ps
CPU time 2029.27 seconds
Started Jun 30 04:53:15 PM PDT 24
Finished Jun 30 05:27:06 PM PDT 24
Peak memory 193020 kb
Host smart-f6ac31ec-9682-4087-a21c-d5bd523312d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208498460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.208498460
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3906771080
Short name T410
Test name
Test status
Simulation time 201288634428 ps
CPU time 115.95 seconds
Started Jun 30 04:53:18 PM PDT 24
Finished Jun 30 04:55:14 PM PDT 24
Peak memory 183092 kb
Host smart-0046a5fb-0849-4d5a-857a-89571ff607d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906771080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3906771080
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1204252777
Short name T245
Test name
Test status
Simulation time 313360716759 ps
CPU time 236.27 seconds
Started Jun 30 04:53:18 PM PDT 24
Finished Jun 30 04:57:15 PM PDT 24
Peak memory 191248 kb
Host smart-b96a9d09-388a-49ab-8f3a-ce82f2d43bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204252777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1204252777
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2968856390
Short name T243
Test name
Test status
Simulation time 248990572963 ps
CPU time 598.92 seconds
Started Jun 30 04:53:16 PM PDT 24
Finished Jun 30 05:03:16 PM PDT 24
Peak memory 193768 kb
Host smart-fdb7967d-fc24-4ac3-b765-2d81f33e8caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968856390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2968856390
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3886981500
Short name T149
Test name
Test status
Simulation time 267185322226 ps
CPU time 391.81 seconds
Started Jun 30 04:52:10 PM PDT 24
Finished Jun 30 04:58:44 PM PDT 24
Peak memory 183028 kb
Host smart-144ce310-57f6-4da9-bc79-d8089384fa52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886981500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3886981500
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.3186763978
Short name T402
Test name
Test status
Simulation time 77143759299 ps
CPU time 66.06 seconds
Started Jun 30 04:52:11 PM PDT 24
Finished Jun 30 04:53:19 PM PDT 24
Peak memory 183064 kb
Host smart-fa06b569-64c9-4b29-afd0-bf6139083f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186763978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.3186763978
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3418067403
Short name T152
Test name
Test status
Simulation time 673256705746 ps
CPU time 645.22 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 05:03:00 PM PDT 24
Peak memory 191196 kb
Host smart-c1a922b1-ccea-4079-b5e7-b87f28ffa9c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418067403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3418067403
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2060430769
Short name T408
Test name
Test status
Simulation time 25532777 ps
CPU time 0.53 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 04:52:15 PM PDT 24
Peak memory 182788 kb
Host smart-ff0e3172-d736-404e-b3d7-5c37ad81c778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060430769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2060430769
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3188731215
Short name T364
Test name
Test status
Simulation time 185164623655 ps
CPU time 121.95 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 04:54:17 PM PDT 24
Peak memory 182972 kb
Host smart-f5a97dbd-e26c-4a67-9132-37a1f47a22ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188731215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3188731215
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3839539368
Short name T92
Test name
Test status
Simulation time 332874499434 ps
CPU time 284.57 seconds
Started Jun 30 04:53:15 PM PDT 24
Finished Jun 30 04:58:01 PM PDT 24
Peak memory 191296 kb
Host smart-9310f314-4e10-4500-8cc5-404ee196306b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839539368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3839539368
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1183800778
Short name T439
Test name
Test status
Simulation time 210744104353 ps
CPU time 244.21 seconds
Started Jun 30 04:53:15 PM PDT 24
Finished Jun 30 04:57:20 PM PDT 24
Peak memory 191284 kb
Host smart-d5f95e03-00c4-49f8-9fbd-4b3e0c28291a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183800778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1183800778
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.281001141
Short name T130
Test name
Test status
Simulation time 270250463613 ps
CPU time 428.17 seconds
Started Jun 30 04:53:23 PM PDT 24
Finished Jun 30 05:00:32 PM PDT 24
Peak memory 191268 kb
Host smart-032f5126-4d98-4324-95ee-892fc9c1506e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281001141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.281001141
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1914802118
Short name T360
Test name
Test status
Simulation time 80994082655 ps
CPU time 127.48 seconds
Started Jun 30 04:53:24 PM PDT 24
Finished Jun 30 04:55:32 PM PDT 24
Peak memory 191256 kb
Host smart-47b82900-7a0b-4610-a2d2-4a06969b7681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914802118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1914802118
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1952568273
Short name T426
Test name
Test status
Simulation time 30433437759 ps
CPU time 54.19 seconds
Started Jun 30 04:53:23 PM PDT 24
Finished Jun 30 04:54:18 PM PDT 24
Peak memory 183088 kb
Host smart-c3c0256b-bcad-49cc-8899-fd581467d62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952568273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1952568273
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.223659122
Short name T121
Test name
Test status
Simulation time 133428531966 ps
CPU time 52.31 seconds
Started Jun 30 04:53:22 PM PDT 24
Finished Jun 30 04:54:15 PM PDT 24
Peak memory 192412 kb
Host smart-9be536e0-166e-41c5-a4e1-89610a28968b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223659122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.223659122
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2144189112
Short name T299
Test name
Test status
Simulation time 40082923054 ps
CPU time 407.4 seconds
Started Jun 30 04:53:22 PM PDT 24
Finished Jun 30 05:00:10 PM PDT 24
Peak memory 183068 kb
Host smart-c3c7c2a9-7809-4c8b-8cc1-59926ac6c468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144189112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2144189112
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1780888694
Short name T10
Test name
Test status
Simulation time 51029810292 ps
CPU time 250.83 seconds
Started Jun 30 04:53:25 PM PDT 24
Finished Jun 30 04:57:36 PM PDT 24
Peak memory 183084 kb
Host smart-a3206511-2c50-4a30-88e3-4f346b4205df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780888694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1780888694
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3767081241
Short name T237
Test name
Test status
Simulation time 1226769214506 ps
CPU time 481.1 seconds
Started Jun 30 04:52:15 PM PDT 24
Finished Jun 30 05:00:17 PM PDT 24
Peak memory 182984 kb
Host smart-641331e0-d2af-4608-a496-a0df240da673
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767081241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3767081241
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.743802298
Short name T389
Test name
Test status
Simulation time 33134113505 ps
CPU time 45.48 seconds
Started Jun 30 04:52:11 PM PDT 24
Finished Jun 30 04:52:58 PM PDT 24
Peak memory 183100 kb
Host smart-caad4bd1-27c7-4a55-96ae-2d77e2f2acf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743802298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.743802298
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2995935104
Short name T378
Test name
Test status
Simulation time 921163876 ps
CPU time 1.75 seconds
Started Jun 30 04:52:11 PM PDT 24
Finished Jun 30 04:52:15 PM PDT 24
Peak memory 191184 kb
Host smart-897f6a01-a973-40a0-a03f-ba074a935e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995935104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2995935104
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.851534467
Short name T330
Test name
Test status
Simulation time 379133953559 ps
CPU time 287.61 seconds
Started Jun 30 04:52:14 PM PDT 24
Finished Jun 30 04:57:02 PM PDT 24
Peak memory 191256 kb
Host smart-6700268c-82c9-40a4-91b4-a4692400415e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851534467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.851534467
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.3240109511
Short name T31
Test name
Test status
Simulation time 121208744533 ps
CPU time 894.35 seconds
Started Jun 30 04:52:12 PM PDT 24
Finished Jun 30 05:07:07 PM PDT 24
Peak memory 210732 kb
Host smart-29bbe319-87ef-43d6-b165-1f01f96602aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240109511 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.3240109511
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.13172335
Short name T418
Test name
Test status
Simulation time 71917865491 ps
CPU time 85.17 seconds
Started Jun 30 04:53:25 PM PDT 24
Finished Jun 30 04:54:50 PM PDT 24
Peak memory 191280 kb
Host smart-8fa9289d-846b-48eb-8127-c6b34351e8dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13172335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.13172335
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2266252532
Short name T326
Test name
Test status
Simulation time 23396052813 ps
CPU time 260.89 seconds
Started Jun 30 04:53:24 PM PDT 24
Finished Jun 30 04:57:45 PM PDT 24
Peak memory 182996 kb
Host smart-9a014932-1347-4de2-a8e5-02b1d97c9ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266252532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2266252532
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1120487387
Short name T309
Test name
Test status
Simulation time 352274786933 ps
CPU time 244.87 seconds
Started Jun 30 04:53:24 PM PDT 24
Finished Jun 30 04:57:29 PM PDT 24
Peak memory 191264 kb
Host smart-1aa79412-9d91-43e1-9109-a2bb3a96d77c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120487387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1120487387
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2665421273
Short name T357
Test name
Test status
Simulation time 107469134776 ps
CPU time 300.09 seconds
Started Jun 30 04:53:32 PM PDT 24
Finished Jun 30 04:58:32 PM PDT 24
Peak memory 191284 kb
Host smart-b6b3d432-bc1f-400c-8184-d331bb98653b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665421273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2665421273
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1253459318
Short name T44
Test name
Test status
Simulation time 1388862461060 ps
CPU time 454.41 seconds
Started Jun 30 04:53:33 PM PDT 24
Finished Jun 30 05:01:07 PM PDT 24
Peak memory 191280 kb
Host smart-de92fb1c-eeba-4647-8392-1bc959626d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253459318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1253459318
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2045759993
Short name T190
Test name
Test status
Simulation time 195256218211 ps
CPU time 321.34 seconds
Started Jun 30 04:53:33 PM PDT 24
Finished Jun 30 04:58:54 PM PDT 24
Peak memory 191284 kb
Host smart-244ed6a4-e2b4-402b-959d-cd8543cc2e4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045759993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2045759993
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1704574526
Short name T250
Test name
Test status
Simulation time 96516753503 ps
CPU time 137.8 seconds
Started Jun 30 04:53:32 PM PDT 24
Finished Jun 30 04:55:50 PM PDT 24
Peak memory 193936 kb
Host smart-fa527e36-e5ee-4cda-9e56-3551b9eeb6b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704574526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1704574526
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1230596853
Short name T96
Test name
Test status
Simulation time 48008621340 ps
CPU time 267.14 seconds
Started Jun 30 04:53:31 PM PDT 24
Finished Jun 30 04:57:58 PM PDT 24
Peak memory 183004 kb
Host smart-8d865fed-6d7a-46c5-9330-a3a85b8850b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230596853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1230596853
Directory /workspace/99.rv_timer_random/latest
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