Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 583
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2372968080 Jul 01 10:33:55 AM PDT 24 Jul 01 10:33:58 AM PDT 24 381967276 ps
T509 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1709354685 Jul 01 10:33:58 AM PDT 24 Jul 01 10:34:01 AM PDT 24 348502538 ps
T510 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3321579965 Jul 01 10:33:43 AM PDT 24 Jul 01 10:33:44 AM PDT 24 111992236 ps
T511 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2957424669 Jul 01 10:33:45 AM PDT 24 Jul 01 10:33:48 AM PDT 24 36268130 ps
T512 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2380323364 Jul 01 10:34:03 AM PDT 24 Jul 01 10:34:05 AM PDT 24 48827775 ps
T513 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4145154468 Jul 01 10:34:04 AM PDT 24 Jul 01 10:34:06 AM PDT 24 59654507 ps
T514 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.29246229 Jul 01 10:33:45 AM PDT 24 Jul 01 10:33:47 AM PDT 24 91611296 ps
T515 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3568015958 Jul 01 10:33:36 AM PDT 24 Jul 01 10:33:37 AM PDT 24 15762620 ps
T516 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3566497986 Jul 01 10:33:40 AM PDT 24 Jul 01 10:33:44 AM PDT 24 729001193 ps
T517 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2252232257 Jul 01 10:33:42 AM PDT 24 Jul 01 10:33:44 AM PDT 24 73692583 ps
T518 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1826293714 Jul 01 10:33:47 AM PDT 24 Jul 01 10:33:50 AM PDT 24 13300253 ps
T519 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3676346467 Jul 01 10:33:44 AM PDT 24 Jul 01 10:33:46 AM PDT 24 117950823 ps
T520 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1188382779 Jul 01 10:33:46 AM PDT 24 Jul 01 10:33:49 AM PDT 24 21578360 ps
T521 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3360283920 Jul 01 10:33:47 AM PDT 24 Jul 01 10:33:50 AM PDT 24 15110864 ps
T522 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3695005251 Jul 01 10:34:06 AM PDT 24 Jul 01 10:34:09 AM PDT 24 42181180 ps
T523 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.376808772 Jul 01 10:33:50 AM PDT 24 Jul 01 10:33:53 AM PDT 24 27085216 ps
T524 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3020130787 Jul 01 10:33:46 AM PDT 24 Jul 01 10:33:49 AM PDT 24 17675761 ps
T525 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.194734378 Jul 01 10:33:49 AM PDT 24 Jul 01 10:33:52 AM PDT 24 81621802 ps
T526 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.789076893 Jul 01 10:33:58 AM PDT 24 Jul 01 10:34:00 AM PDT 24 25202214 ps
T527 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3917605031 Jul 01 10:33:50 AM PDT 24 Jul 01 10:33:54 AM PDT 24 14566036 ps
T528 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.630268577 Jul 01 10:34:10 AM PDT 24 Jul 01 10:34:13 AM PDT 24 41924286 ps
T529 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1622512712 Jul 01 10:33:46 AM PDT 24 Jul 01 10:33:50 AM PDT 24 42419254 ps
T530 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.168336859 Jul 01 10:33:47 AM PDT 24 Jul 01 10:33:51 AM PDT 24 32186914 ps
T531 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4176332325 Jul 01 10:34:02 AM PDT 24 Jul 01 10:34:04 AM PDT 24 17770347 ps
T532 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2183124642 Jul 01 10:33:44 AM PDT 24 Jul 01 10:33:48 AM PDT 24 249272598 ps
T533 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2724005139 Jul 01 10:33:50 AM PDT 24 Jul 01 10:33:54 AM PDT 24 18314597 ps
T534 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3550974996 Jul 01 10:33:59 AM PDT 24 Jul 01 10:34:00 AM PDT 24 13800428 ps
T535 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2585221553 Jul 01 10:34:04 AM PDT 24 Jul 01 10:34:07 AM PDT 24 74304120 ps
T536 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2934757099 Jul 01 10:34:02 AM PDT 24 Jul 01 10:34:04 AM PDT 24 22172566 ps
T537 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1969464920 Jul 01 10:33:51 AM PDT 24 Jul 01 10:33:56 AM PDT 24 1254225373 ps
T538 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1415369888 Jul 01 10:33:48 AM PDT 24 Jul 01 10:33:51 AM PDT 24 33851119 ps
T539 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2614497052 Jul 01 10:33:45 AM PDT 24 Jul 01 10:33:48 AM PDT 24 50009664 ps
T540 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.833371437 Jul 01 10:33:50 AM PDT 24 Jul 01 10:33:55 AM PDT 24 103945783 ps
T541 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1753150360 Jul 01 10:33:46 AM PDT 24 Jul 01 10:33:48 AM PDT 24 23146806 ps
T542 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.747208627 Jul 01 10:34:02 AM PDT 24 Jul 01 10:34:04 AM PDT 24 45985524 ps
T543 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3355957331 Jul 01 10:33:44 AM PDT 24 Jul 01 10:33:46 AM PDT 24 39903491 ps
T544 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.777356098 Jul 01 10:33:42 AM PDT 24 Jul 01 10:33:44 AM PDT 24 22488788 ps
T84 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2423960634 Jul 01 10:33:48 AM PDT 24 Jul 01 10:33:51 AM PDT 24 138739351 ps
T85 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3735583008 Jul 01 10:33:52 AM PDT 24 Jul 01 10:33:57 AM PDT 24 13120097 ps
T545 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1476193515 Jul 01 10:33:47 AM PDT 24 Jul 01 10:33:50 AM PDT 24 24927405 ps
T546 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3154653274 Jul 01 10:34:02 AM PDT 24 Jul 01 10:34:04 AM PDT 24 55868356 ps
T547 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.131595562 Jul 01 10:34:05 AM PDT 24 Jul 01 10:34:08 AM PDT 24 33160030 ps
T548 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.972931308 Jul 01 10:33:39 AM PDT 24 Jul 01 10:33:41 AM PDT 24 24476290 ps
T549 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2535464959 Jul 01 10:33:54 AM PDT 24 Jul 01 10:33:58 AM PDT 24 47043936 ps
T86 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1756064977 Jul 01 10:33:50 AM PDT 24 Jul 01 10:33:53 AM PDT 24 18843194 ps
T550 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.533680090 Jul 01 10:33:45 AM PDT 24 Jul 01 10:33:49 AM PDT 24 241970862 ps
T551 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1929811786 Jul 01 10:33:54 AM PDT 24 Jul 01 10:33:57 AM PDT 24 13294386 ps
T552 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3827050485 Jul 01 10:33:41 AM PDT 24 Jul 01 10:33:42 AM PDT 24 127986382 ps
T553 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2144336789 Jul 01 10:33:41 AM PDT 24 Jul 01 10:33:44 AM PDT 24 505114349 ps
T554 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3778573902 Jul 01 10:33:46 AM PDT 24 Jul 01 10:33:51 AM PDT 24 192425866 ps
T555 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1320822702 Jul 01 10:34:00 AM PDT 24 Jul 01 10:34:02 AM PDT 24 17464487 ps
T556 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4056124042 Jul 01 10:34:26 AM PDT 24 Jul 01 10:34:27 AM PDT 24 28006848 ps
T557 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.167116703 Jul 01 10:33:51 AM PDT 24 Jul 01 10:33:59 AM PDT 24 350847184 ps
T558 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.72470097 Jul 01 10:34:17 AM PDT 24 Jul 01 10:34:21 AM PDT 24 81846481 ps
T559 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.170629486 Jul 01 10:33:49 AM PDT 24 Jul 01 10:33:52 AM PDT 24 21755495 ps
T560 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3240521586 Jul 01 10:33:39 AM PDT 24 Jul 01 10:33:41 AM PDT 24 15811112 ps
T87 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.4107162871 Jul 01 10:33:39 AM PDT 24 Jul 01 10:33:40 AM PDT 24 15356805 ps
T561 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2834118621 Jul 01 10:34:07 AM PDT 24 Jul 01 10:34:10 AM PDT 24 15656038 ps
T562 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3366895709 Jul 01 10:33:32 AM PDT 24 Jul 01 10:33:34 AM PDT 24 80146056 ps
T563 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4079109347 Jul 01 10:34:03 AM PDT 24 Jul 01 10:34:05 AM PDT 24 15109798 ps
T564 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1940836871 Jul 01 10:33:58 AM PDT 24 Jul 01 10:34:00 AM PDT 24 180451232 ps
T565 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1426788407 Jul 01 10:33:50 AM PDT 24 Jul 01 10:33:54 AM PDT 24 200900546 ps
T566 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3948933412 Jul 01 10:33:46 AM PDT 24 Jul 01 10:33:49 AM PDT 24 295766497 ps
T88 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.906861693 Jul 01 10:33:42 AM PDT 24 Jul 01 10:33:43 AM PDT 24 73259184 ps
T567 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4049890676 Jul 01 10:33:43 AM PDT 24 Jul 01 10:33:44 AM PDT 24 45664687 ps
T568 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3418446095 Jul 01 10:34:02 AM PDT 24 Jul 01 10:34:05 AM PDT 24 1633585476 ps
T569 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2366447223 Jul 01 10:34:09 AM PDT 24 Jul 01 10:34:12 AM PDT 24 99903826 ps
T89 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1399081835 Jul 01 10:34:01 AM PDT 24 Jul 01 10:34:03 AM PDT 24 110815950 ps
T90 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1350029371 Jul 01 10:33:47 AM PDT 24 Jul 01 10:33:50 AM PDT 24 29642248 ps
T570 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2262683184 Jul 01 10:33:39 AM PDT 24 Jul 01 10:33:41 AM PDT 24 84472757 ps
T571 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2079324295 Jul 01 10:33:41 AM PDT 24 Jul 01 10:33:42 AM PDT 24 30450772 ps
T572 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1139613106 Jul 01 10:33:57 AM PDT 24 Jul 01 10:34:00 AM PDT 24 74363039 ps
T573 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.663548576 Jul 01 10:33:52 AM PDT 24 Jul 01 10:33:57 AM PDT 24 98310846 ps
T574 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3240265731 Jul 01 10:33:53 AM PDT 24 Jul 01 10:33:57 AM PDT 24 15632048 ps
T575 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.940922301 Jul 01 10:34:00 AM PDT 24 Jul 01 10:34:03 AM PDT 24 54343617 ps
T576 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.507916012 Jul 01 10:34:03 AM PDT 24 Jul 01 10:34:05 AM PDT 24 24202388 ps
T577 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1321412921 Jul 01 10:33:44 AM PDT 24 Jul 01 10:33:46 AM PDT 24 44192715 ps
T578 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2459093691 Jul 01 10:33:48 AM PDT 24 Jul 01 10:33:51 AM PDT 24 555206395 ps
T579 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1059351737 Jul 01 10:33:54 AM PDT 24 Jul 01 10:33:58 AM PDT 24 44721865 ps
T580 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2146515246 Jul 01 10:34:01 AM PDT 24 Jul 01 10:34:02 AM PDT 24 24108879 ps
T581 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.450011298 Jul 01 10:34:00 AM PDT 24 Jul 01 10:34:01 AM PDT 24 24476233 ps
T582 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.475703310 Jul 01 10:33:58 AM PDT 24 Jul 01 10:34:00 AM PDT 24 17978794 ps
T583 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1567386578 Jul 01 10:33:47 AM PDT 24 Jul 01 10:33:50 AM PDT 24 108143903 ps

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.465613596
Short name T3
Test name
Test status
Simulation time 72836233274 ps
CPU time 324.25 seconds
Started Jul 01 10:53:29 AM PDT 24
Finished Jul 01 10:58:55 AM PDT 24
Peak memory 205996 kb
Host smart-7caf1229-0a54-4366-b75c-912f15ffcd31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465613596 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.465613596
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1203732576
Short name T33
Test name
Test status
Simulation time 1314638231516 ps
CPU time 2323.68 seconds
Started Jul 01 10:53:42 AM PDT 24
Finished Jul 01 11:32:27 AM PDT 24
Peak memory 195188 kb
Host smart-05c80326-02f7-485b-a120-fa6caed1342c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203732576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1203732576
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1171074216
Short name T27
Test name
Test status
Simulation time 249885502 ps
CPU time 1.09 seconds
Started Jul 01 10:33:51 AM PDT 24
Finished Jul 01 10:33:56 AM PDT 24
Peak memory 194712 kb
Host smart-d18e5e84-ff33-4170-b7eb-1013c17462f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171074216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1171074216
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/79.rv_timer_random.333996066
Short name T123
Test name
Test status
Simulation time 111229262508 ps
CPU time 417.71 seconds
Started Jul 01 10:53:50 AM PDT 24
Finished Jul 01 11:00:49 AM PDT 24
Peak memory 191276 kb
Host smart-9b94c561-8a2b-4d65-ba0e-0e4eca29d5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333996066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.333996066
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1346024820
Short name T62
Test name
Test status
Simulation time 2096317213615 ps
CPU time 1637.88 seconds
Started Jul 01 10:52:52 AM PDT 24
Finished Jul 01 11:20:15 AM PDT 24
Peak memory 196860 kb
Host smart-159980f1-6475-471a-9f4b-89d49af482bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346024820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1346024820
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2452384910
Short name T185
Test name
Test status
Simulation time 3727971329479 ps
CPU time 2200.95 seconds
Started Jul 01 10:52:41 AM PDT 24
Finished Jul 01 11:29:25 AM PDT 24
Peak memory 191256 kb
Host smart-e60592f6-c72f-4744-9ffe-ebdcb9b5a29f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452384910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2452384910
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2977564394
Short name T204
Test name
Test status
Simulation time 2699086171128 ps
CPU time 1548.08 seconds
Started Jul 01 10:52:51 AM PDT 24
Finished Jul 01 11:18:44 AM PDT 24
Peak memory 191284 kb
Host smart-d42c7f7f-3488-4dc5-8608-9495bfa9f33e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977564394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2977564394
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1138945312
Short name T181
Test name
Test status
Simulation time 1196752164709 ps
CPU time 795.44 seconds
Started Jul 01 10:53:15 AM PDT 24
Finished Jul 01 11:06:34 AM PDT 24
Peak memory 191236 kb
Host smart-b7770f73-27b1-4905-b89a-3b92c1093dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138945312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1138945312
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.242183285
Short name T45
Test name
Test status
Simulation time 30665847447 ps
CPU time 88.63 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:54:23 AM PDT 24
Peak memory 197816 kb
Host smart-eba8a98a-947a-4d29-b845-6f06d3bf9b0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242183285 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.242183285
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.137744981
Short name T64
Test name
Test status
Simulation time 1628977898910 ps
CPU time 729.23 seconds
Started Jul 01 10:52:59 AM PDT 24
Finished Jul 01 11:05:12 AM PDT 24
Peak memory 196268 kb
Host smart-114d85c2-ba3f-484c-a570-c63917d65ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137744981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
137744981
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1702168417
Short name T67
Test name
Test status
Simulation time 2287659714438 ps
CPU time 1017.37 seconds
Started Jul 01 10:53:17 AM PDT 24
Finished Jul 01 11:10:19 AM PDT 24
Peak memory 195684 kb
Host smart-9bc99df5-13de-4307-a958-2999ee20ee53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702168417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1702168417
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3899087556
Short name T347
Test name
Test status
Simulation time 499776646500 ps
CPU time 1195.17 seconds
Started Jul 01 10:53:04 AM PDT 24
Finished Jul 01 11:13:02 AM PDT 24
Peak memory 191188 kb
Host smart-820ec88d-5217-493d-87d2-af3cf4c2e337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899087556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3899087556
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2091610461
Short name T173
Test name
Test status
Simulation time 864703353262 ps
CPU time 1774.62 seconds
Started Jul 01 10:53:35 AM PDT 24
Finished Jul 01 11:23:11 AM PDT 24
Peak memory 191248 kb
Host smart-7fa822ff-19e7-4371-91cb-8d417e10302c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091610461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2091610461
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.898355644
Short name T61
Test name
Test status
Simulation time 1247352308858 ps
CPU time 678.8 seconds
Started Jul 01 10:53:31 AM PDT 24
Finished Jul 01 11:04:51 AM PDT 24
Peak memory 191236 kb
Host smart-6949bdb5-47fc-48fd-a165-c392d1e3c2e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898355644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
898355644
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3272445560
Short name T14
Test name
Test status
Simulation time 121992119 ps
CPU time 0.7 seconds
Started Jul 01 10:52:44 AM PDT 24
Finished Jul 01 10:52:48 AM PDT 24
Peak memory 213320 kb
Host smart-6672bcc7-3b43-4236-9616-3f2342b95251
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272445560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3272445560
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1238498797
Short name T328
Test name
Test status
Simulation time 1236287912039 ps
CPU time 2316.94 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 11:31:26 AM PDT 24
Peak memory 191304 kb
Host smart-e1cc6a94-05dc-4036-8de0-4c97edb3b48a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238498797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1238498797
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1780114175
Short name T26
Test name
Test status
Simulation time 3846311366368 ps
CPU time 1341.84 seconds
Started Jul 01 10:53:22 AM PDT 24
Finished Jul 01 11:15:47 AM PDT 24
Peak memory 191316 kb
Host smart-0b331378-4495-4a82-9473-687dc2052c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780114175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1780114175
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_random.1522616260
Short name T108
Test name
Test status
Simulation time 84027556307 ps
CPU time 333.53 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:58:29 AM PDT 24
Peak memory 191300 kb
Host smart-234d1130-1317-4490-9bbf-3b20bb803ef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522616260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1522616260
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.687482364
Short name T299
Test name
Test status
Simulation time 451665492156 ps
CPU time 4298 seconds
Started Jul 01 10:53:27 AM PDT 24
Finished Jul 01 12:05:07 PM PDT 24
Peak memory 191320 kb
Host smart-23548893-27f1-499a-8b6b-7689f7698cea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687482364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
687482364
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/142.rv_timer_random.1438042453
Short name T245
Test name
Test status
Simulation time 175396602303 ps
CPU time 740.28 seconds
Started Jul 01 10:54:31 AM PDT 24
Finished Jul 01 11:06:52 AM PDT 24
Peak memory 191316 kb
Host smart-d5b3f945-65ef-484e-96c2-c697255665ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438042453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1438042453
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3169541394
Short name T157
Test name
Test status
Simulation time 3188874297858 ps
CPU time 1385.19 seconds
Started Jul 01 10:53:34 AM PDT 24
Finished Jul 01 11:16:41 AM PDT 24
Peak memory 191124 kb
Host smart-1390e801-8d20-4cb9-a282-f198b6d39a9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169541394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3169541394
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3191168374
Short name T290
Test name
Test status
Simulation time 2215311872449 ps
CPU time 1514.01 seconds
Started Jul 01 10:52:45 AM PDT 24
Finished Jul 01 11:18:03 AM PDT 24
Peak memory 191280 kb
Host smart-ba4612a0-6027-4bfe-ba9f-d67caacf62e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191168374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3191168374
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.376998215
Short name T258
Test name
Test status
Simulation time 440482173602 ps
CPU time 2450.91 seconds
Started Jul 01 10:53:10 AM PDT 24
Finished Jul 01 11:34:04 AM PDT 24
Peak memory 194860 kb
Host smart-8cd8cd3c-c729-4f57-a194-c6dd80a6c382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376998215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
376998215
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.437829378
Short name T194
Test name
Test status
Simulation time 677793216662 ps
CPU time 1256.69 seconds
Started Jul 01 10:53:10 AM PDT 24
Finished Jul 01 11:14:09 AM PDT 24
Peak memory 191292 kb
Host smart-4cccdd51-c24d-4b1f-a32b-6cee9a7d2317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437829378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
437829378
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1603768219
Short name T246
Test name
Test status
Simulation time 1402073742233 ps
CPU time 3394.88 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 11:49:30 AM PDT 24
Peak memory 195376 kb
Host smart-db5454ce-9f5f-47c8-95f5-d3a5b365cc47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603768219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1603768219
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.50547032
Short name T255
Test name
Test status
Simulation time 163185334667 ps
CPU time 411.76 seconds
Started Jul 01 10:54:27 AM PDT 24
Finished Jul 01 11:01:19 AM PDT 24
Peak memory 191196 kb
Host smart-8c1ad14e-2237-4f69-9005-3febb82c0896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50547032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.50547032
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2256375073
Short name T230
Test name
Test status
Simulation time 261870129479 ps
CPU time 210.5 seconds
Started Jul 01 10:54:46 AM PDT 24
Finished Jul 01 10:58:17 AM PDT 24
Peak memory 191324 kb
Host smart-7b6111cb-ffac-43c8-931e-8ff45e333b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256375073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2256375073
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2376343862
Short name T215
Test name
Test status
Simulation time 100619266486 ps
CPU time 2546.84 seconds
Started Jul 01 10:53:56 AM PDT 24
Finished Jul 01 11:36:23 AM PDT 24
Peak memory 191212 kb
Host smart-9a551db7-01cd-41eb-b439-8573c43d005e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376343862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2376343862
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.607674159
Short name T229
Test name
Test status
Simulation time 1457058631223 ps
CPU time 1999.14 seconds
Started Jul 01 10:54:25 AM PDT 24
Finished Jul 01 11:27:45 AM PDT 24
Peak memory 191312 kb
Host smart-a5d4d105-a0c4-400f-833a-c431c95be975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607674159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.607674159
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2311248982
Short name T187
Test name
Test status
Simulation time 600372644952 ps
CPU time 293.58 seconds
Started Jul 01 10:55:01 AM PDT 24
Finished Jul 01 10:59:56 AM PDT 24
Peak memory 191280 kb
Host smart-e062fa71-6fd8-4414-9290-4884c04176be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311248982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2311248982
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.3461800205
Short name T306
Test name
Test status
Simulation time 69603781904 ps
CPU time 439.67 seconds
Started Jul 01 10:54:08 AM PDT 24
Finished Jul 01 11:01:30 AM PDT 24
Peak memory 191236 kb
Host smart-fd884d63-3f70-4d6e-a849-17e4d8dcc637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461800205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3461800205
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2132134295
Short name T196
Test name
Test status
Simulation time 116397094179 ps
CPU time 1292.32 seconds
Started Jul 01 10:54:52 AM PDT 24
Finished Jul 01 11:16:25 AM PDT 24
Peak memory 194948 kb
Host smart-00da075c-7874-43f3-9562-6e7cc56f1f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132134295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2132134295
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random.2785229479
Short name T270
Test name
Test status
Simulation time 387885130935 ps
CPU time 538.84 seconds
Started Jul 01 10:53:23 AM PDT 24
Finished Jul 01 11:02:24 AM PDT 24
Peak memory 194624 kb
Host smart-ddca5064-4681-42dc-a1ea-0bacb0be66ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785229479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2785229479
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1163705403
Short name T286
Test name
Test status
Simulation time 1460166948083 ps
CPU time 2143.11 seconds
Started Jul 01 10:53:27 AM PDT 24
Finished Jul 01 11:29:12 AM PDT 24
Peak memory 191320 kb
Host smart-e68e9f0c-451a-40fd-b653-40777ac67ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163705403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1163705403
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/66.rv_timer_random.3957390156
Short name T256
Test name
Test status
Simulation time 508246169486 ps
CPU time 568.86 seconds
Started Jul 01 10:53:41 AM PDT 24
Finished Jul 01 11:03:11 AM PDT 24
Peak memory 191284 kb
Host smart-9ec4b9ce-eac7-4259-a0b2-7f6263baaea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957390156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3957390156
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.1101006236
Short name T72
Test name
Test status
Simulation time 122343218198 ps
CPU time 187.71 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 10:55:57 AM PDT 24
Peak memory 191256 kb
Host smart-81e9d2ea-10c3-4a9b-9347-49d09e3a85ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101006236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1101006236
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2670023440
Short name T66
Test name
Test status
Simulation time 448291400287 ps
CPU time 909.07 seconds
Started Jul 01 10:52:55 AM PDT 24
Finished Jul 01 11:08:09 AM PDT 24
Peak memory 195716 kb
Host smart-c1a96d26-5bdb-4144-9ca9-2ff0677cdf52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670023440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2670023440
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_random.1151609210
Short name T133
Test name
Test status
Simulation time 236022990827 ps
CPU time 197.85 seconds
Started Jul 01 10:53:34 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 193468 kb
Host smart-2c9b4b1b-6c8a-4215-8a09-8dc3675ab804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151609210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1151609210
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2405051060
Short name T208
Test name
Test status
Simulation time 406174783804 ps
CPU time 310.04 seconds
Started Jul 01 10:53:27 AM PDT 24
Finished Jul 01 10:58:39 AM PDT 24
Peak memory 183048 kb
Host smart-e78fa195-32d9-44e4-9fd2-f73f3b405b42
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405051060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2405051060
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/136.rv_timer_random.482935750
Short name T210
Test name
Test status
Simulation time 473524113419 ps
CPU time 1371.26 seconds
Started Jul 01 10:54:29 AM PDT 24
Finished Jul 01 11:17:21 AM PDT 24
Peak memory 191316 kb
Host smart-8a7f06a5-8b5f-42db-954f-facf5b0ade9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482935750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.482935750
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3519271192
Short name T248
Test name
Test status
Simulation time 281605681208 ps
CPU time 484.46 seconds
Started Jul 01 10:53:23 AM PDT 24
Finished Jul 01 11:01:30 AM PDT 24
Peak memory 191288 kb
Host smart-a07d589c-ed81-469e-8ca3-d5d7bcf6a7ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519271192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3519271192
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random.1337839352
Short name T199
Test name
Test status
Simulation time 76400334930 ps
CPU time 145.31 seconds
Started Jul 01 10:53:31 AM PDT 24
Finished Jul 01 10:55:58 AM PDT 24
Peak memory 191316 kb
Host smart-92bc3748-1562-43fd-8edb-b8febfdd3c38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337839352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1337839352
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1645045215
Short name T116
Test name
Test status
Simulation time 151394267007 ps
CPU time 259.74 seconds
Started Jul 01 10:53:44 AM PDT 24
Finished Jul 01 10:58:04 AM PDT 24
Peak memory 191284 kb
Host smart-8b5eae7e-91b2-4694-932c-3e429708c458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645045215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1645045215
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.16287457
Short name T213
Test name
Test status
Simulation time 224953784322 ps
CPU time 472.68 seconds
Started Jul 01 10:54:01 AM PDT 24
Finished Jul 01 11:01:54 AM PDT 24
Peak memory 191304 kb
Host smart-679ec112-b9a7-44b0-9542-17610e481db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16287457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.16287457
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.2715651603
Short name T322
Test name
Test status
Simulation time 89764998631 ps
CPU time 138.44 seconds
Started Jul 01 10:54:17 AM PDT 24
Finished Jul 01 10:56:36 AM PDT 24
Peak memory 191240 kb
Host smart-4b2b424b-3bc1-422f-8d23-10a0a07450e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715651603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.2715651603
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3951781692
Short name T212
Test name
Test status
Simulation time 109706626368 ps
CPU time 255.95 seconds
Started Jul 01 10:54:19 AM PDT 24
Finished Jul 01 10:58:36 AM PDT 24
Peak memory 191276 kb
Host smart-69b4d77b-ca7a-437f-b700-0bd2e39779f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951781692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3951781692
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3247979586
Short name T292
Test name
Test status
Simulation time 225502471254 ps
CPU time 194.06 seconds
Started Jul 01 10:54:26 AM PDT 24
Finished Jul 01 10:57:40 AM PDT 24
Peak memory 194620 kb
Host smart-ab7a2480-7420-4223-bf2d-4aeb39fd947e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247979586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3247979586
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2732950322
Short name T283
Test name
Test status
Simulation time 468658635759 ps
CPU time 277.83 seconds
Started Jul 01 10:54:36 AM PDT 24
Finished Jul 01 10:59:14 AM PDT 24
Peak memory 191208 kb
Host smart-de0c8a6a-a81a-4274-9afe-75b03dc7315e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732950322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2732950322
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.878328600
Short name T211
Test name
Test status
Simulation time 640175254642 ps
CPU time 260.23 seconds
Started Jul 01 10:54:36 AM PDT 24
Finished Jul 01 10:58:57 AM PDT 24
Peak memory 191312 kb
Host smart-56aaa9e0-5133-4632-bd6d-cf59d20e53ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878328600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.878328600
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3608682110
Short name T184
Test name
Test status
Simulation time 63608529346 ps
CPU time 269.26 seconds
Started Jul 01 10:54:51 AM PDT 24
Finished Jul 01 10:59:21 AM PDT 24
Peak memory 191288 kb
Host smart-d17cd730-3bfc-4c41-9192-72b05643c27b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608682110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3608682110
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2593507207
Short name T52
Test name
Test status
Simulation time 450614752761 ps
CPU time 437.3 seconds
Started Jul 01 10:55:08 AM PDT 24
Finished Jul 01 11:02:26 AM PDT 24
Peak memory 191420 kb
Host smart-9c378e1a-2fa2-478a-b308-943f4107e0d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593507207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2593507207
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1592869619
Short name T247
Test name
Test status
Simulation time 181126693486 ps
CPU time 81.34 seconds
Started Jul 01 10:52:58 AM PDT 24
Finished Jul 01 10:54:23 AM PDT 24
Peak memory 191312 kb
Host smart-690894e7-9f27-4b4f-b04b-71a332c30561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592869619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1592869619
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2921180936
Short name T263
Test name
Test status
Simulation time 8488057956697 ps
CPU time 1886.09 seconds
Started Jul 01 10:53:33 AM PDT 24
Finished Jul 01 11:25:00 AM PDT 24
Peak memory 183076 kb
Host smart-c06e3b04-7c97-46b8-9711-c16cf9a5046a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921180936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2921180936
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.933133374
Short name T79
Test name
Test status
Simulation time 173681177 ps
CPU time 0.87 seconds
Started Jul 01 10:33:43 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 193156 kb
Host smart-a8858f7d-58eb-4f6c-8ec0-c9a0fcc4717e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933133374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.933133374
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1726625100
Short name T32
Test name
Test status
Simulation time 13333572 ps
CPU time 0.55 seconds
Started Jul 01 10:33:45 AM PDT 24
Finished Jul 01 10:33:47 AM PDT 24
Peak memory 182108 kb
Host smart-5e25591b-4d6e-4b0e-8844-e0f06bfe7fdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726625100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1726625100
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3948933412
Short name T566
Test name
Test status
Simulation time 295766497 ps
CPU time 1.13 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 194540 kb
Host smart-cb8dc52d-e510-4ef5-b454-588b39eca5ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948933412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3948933412
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/108.rv_timer_random.3265634559
Short name T335
Test name
Test status
Simulation time 730796626789 ps
CPU time 365.41 seconds
Started Jul 01 10:54:10 AM PDT 24
Finished Jul 01 11:00:18 AM PDT 24
Peak memory 191260 kb
Host smart-88162a20-0768-4f5b-8639-696fa2a160f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265634559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3265634559
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.3249820514
Short name T312
Test name
Test status
Simulation time 84925360409 ps
CPU time 467.59 seconds
Started Jul 01 10:54:08 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 191312 kb
Host smart-d814cba4-376d-4f34-9440-d6c2314563c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249820514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3249820514
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2456318005
Short name T260
Test name
Test status
Simulation time 138261553640 ps
CPU time 1971.29 seconds
Started Jul 01 10:54:19 AM PDT 24
Finished Jul 01 11:27:11 AM PDT 24
Peak memory 182984 kb
Host smart-58c6110b-fb5e-44c3-a9a4-e42744e9e521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456318005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2456318005
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2442672043
Short name T295
Test name
Test status
Simulation time 379303056894 ps
CPU time 778.8 seconds
Started Jul 01 10:54:19 AM PDT 24
Finished Jul 01 11:07:19 AM PDT 24
Peak memory 191332 kb
Host smart-63b14b81-2343-46c0-9376-83fbc48a62f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442672043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2442672043
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2773412486
Short name T228
Test name
Test status
Simulation time 88932833153 ps
CPU time 975.52 seconds
Started Jul 01 10:54:34 AM PDT 24
Finished Jul 01 11:10:51 AM PDT 24
Peak memory 191260 kb
Host smart-83e35a7a-9167-4ded-bf3c-9aabe009d2aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773412486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2773412486
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3688179399
Short name T200
Test name
Test status
Simulation time 91084052091 ps
CPU time 152.36 seconds
Started Jul 01 10:54:40 AM PDT 24
Finished Jul 01 10:57:13 AM PDT 24
Peak memory 191324 kb
Host smart-5227847e-1929-4af6-b4a1-ff6edf79a59c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688179399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3688179399
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3186407319
Short name T168
Test name
Test status
Simulation time 100627984231 ps
CPU time 163.78 seconds
Started Jul 01 10:54:40 AM PDT 24
Finished Jul 01 10:57:24 AM PDT 24
Peak memory 191288 kb
Host smart-81eabf14-b3b0-42a4-bfa4-0c185b3e75ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186407319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3186407319
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.2308259231
Short name T446
Test name
Test status
Simulation time 475602605386 ps
CPU time 528.21 seconds
Started Jul 01 10:54:43 AM PDT 24
Finished Jul 01 11:03:31 AM PDT 24
Peak memory 191288 kb
Host smart-1cd9adef-1715-4ef1-9856-d729b078b32e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308259231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2308259231
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2281209596
Short name T162
Test name
Test status
Simulation time 114458338947 ps
CPU time 212.99 seconds
Started Jul 01 10:54:52 AM PDT 24
Finished Jul 01 10:58:26 AM PDT 24
Peak memory 191324 kb
Host smart-3f363d5f-4281-4be7-9650-ca52709cbedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281209596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2281209596
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2871412434
Short name T232
Test name
Test status
Simulation time 45488583327 ps
CPU time 71.38 seconds
Started Jul 01 10:52:56 AM PDT 24
Finished Jul 01 10:54:11 AM PDT 24
Peak memory 191288 kb
Host smart-c9a89d70-8b38-4034-b087-c281053f6599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871412434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2871412434
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/186.rv_timer_random.2984082819
Short name T224
Test name
Test status
Simulation time 62639541501 ps
CPU time 415.01 seconds
Started Jul 01 10:55:01 AM PDT 24
Finished Jul 01 11:01:57 AM PDT 24
Peak memory 182984 kb
Host smart-be0b5ea4-99a9-482e-99fd-3905c6855330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984082819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2984082819
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2066884870
Short name T220
Test name
Test status
Simulation time 510529879360 ps
CPU time 278.62 seconds
Started Jul 01 10:55:08 AM PDT 24
Finished Jul 01 10:59:47 AM PDT 24
Peak memory 191268 kb
Host smart-0f517f70-afb4-41d9-b00c-afe1c277f094
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066884870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2066884870
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1130792715
Short name T54
Test name
Test status
Simulation time 2069615327011 ps
CPU time 1275.54 seconds
Started Jul 01 10:53:07 AM PDT 24
Finished Jul 01 11:14:25 AM PDT 24
Peak memory 183024 kb
Host smart-be54a0f7-da07-4a35-9c7a-8658d6ea0e3d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130792715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1130792715
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_random.3350438467
Short name T148
Test name
Test status
Simulation time 66371944774 ps
CPU time 62.83 seconds
Started Jul 01 10:53:21 AM PDT 24
Finished Jul 01 10:54:27 AM PDT 24
Peak memory 183060 kb
Host smart-9c2fe4f1-833d-4b57-b233-3b680996fb84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350438467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3350438467
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.2920508975
Short name T189
Test name
Test status
Simulation time 297528535514 ps
CPU time 561.17 seconds
Started Jul 01 10:53:25 AM PDT 24
Finished Jul 01 11:02:48 AM PDT 24
Peak memory 191184 kb
Host smart-55833974-97ab-4906-8ab2-6956a17ae57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920508975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2920508975
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3967641610
Short name T281
Test name
Test status
Simulation time 1271175877171 ps
CPU time 1827.37 seconds
Started Jul 01 10:53:27 AM PDT 24
Finished Jul 01 11:23:56 AM PDT 24
Peak memory 191324 kb
Host smart-851947d6-4036-4d4b-bc8c-97295914d6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967641610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3967641610
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/89.rv_timer_random.2471439265
Short name T315
Test name
Test status
Simulation time 102846130254 ps
CPU time 663.55 seconds
Started Jul 01 10:54:00 AM PDT 24
Finished Jul 01 11:05:04 AM PDT 24
Peak memory 194800 kb
Host smart-a38a3d9f-f8ec-4f03-b143-09c7bff99bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471439265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2471439265
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1307183927
Short name T285
Test name
Test status
Simulation time 364635669616 ps
CPU time 175.6 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:55:37 AM PDT 24
Peak memory 183056 kb
Host smart-546ecb02-5ba5-447b-bc16-0cd7a41228c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307183927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1307183927
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3923271735
Short name T223
Test name
Test status
Simulation time 1018104850367 ps
CPU time 1170.1 seconds
Started Jul 01 10:52:43 AM PDT 24
Finished Jul 01 11:12:17 AM PDT 24
Peak memory 191280 kb
Host smart-afda28a7-57de-40af-8bf8-e03e580cab17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923271735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3923271735
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2571124907
Short name T324
Test name
Test status
Simulation time 359548243191 ps
CPU time 468.17 seconds
Started Jul 01 10:52:45 AM PDT 24
Finished Jul 01 11:00:37 AM PDT 24
Peak memory 195796 kb
Host smart-d9bb42b4-2f9e-4f46-a137-d2de2b1bcb23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571124907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2571124907
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/104.rv_timer_random.816174463
Short name T183
Test name
Test status
Simulation time 1422213040491 ps
CPU time 589.2 seconds
Started Jul 01 10:54:09 AM PDT 24
Finished Jul 01 11:04:01 AM PDT 24
Peak memory 191328 kb
Host smart-21ce6a31-7648-4df2-a54a-869bd7f28b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816174463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.816174463
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1248057056
Short name T344
Test name
Test status
Simulation time 221983580293 ps
CPU time 212.47 seconds
Started Jul 01 10:54:10 AM PDT 24
Finished Jul 01 10:57:45 AM PDT 24
Peak memory 191252 kb
Host smart-c003ed0e-f2b7-4a66-bec1-4b0e7197bd99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248057056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1248057056
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1366970894
Short name T357
Test name
Test status
Simulation time 123962949470 ps
CPU time 193.68 seconds
Started Jul 01 10:52:51 AM PDT 24
Finished Jul 01 10:56:10 AM PDT 24
Peak memory 183104 kb
Host smart-6bc6bf22-b9ba-407d-9ede-6bf1e7e25ef6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366970894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1366970894
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.705831428
Short name T365
Test name
Test status
Simulation time 101567544864 ps
CPU time 47.94 seconds
Started Jul 01 10:52:52 AM PDT 24
Finished Jul 01 10:53:45 AM PDT 24
Peak memory 194056 kb
Host smart-2dea6511-8975-46c3-bbb8-1f98e523465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705831428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.705831428
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/122.rv_timer_random.331388227
Short name T298
Test name
Test status
Simulation time 129441486952 ps
CPU time 133.41 seconds
Started Jul 01 10:54:17 AM PDT 24
Finished Jul 01 10:56:31 AM PDT 24
Peak memory 191272 kb
Host smart-85d52dd8-d897-4b7a-a30f-c890edeae027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331388227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.331388227
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3109788984
Short name T120
Test name
Test status
Simulation time 694447134625 ps
CPU time 460.78 seconds
Started Jul 01 10:54:19 AM PDT 24
Finished Jul 01 11:02:01 AM PDT 24
Peak memory 191324 kb
Host smart-2c74a8a1-02b5-469e-b8e4-c38ef389de16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109788984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3109788984
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2737942907
Short name T129
Test name
Test status
Simulation time 317757884321 ps
CPU time 203.66 seconds
Started Jul 01 10:54:20 AM PDT 24
Finished Jul 01 10:57:44 AM PDT 24
Peak memory 194460 kb
Host smart-83a3d785-b5e7-4ba4-8153-6c509fd88a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737942907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2737942907
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.1671566674
Short name T332
Test name
Test status
Simulation time 92395087495 ps
CPU time 134.58 seconds
Started Jul 01 10:52:52 AM PDT 24
Finished Jul 01 10:55:12 AM PDT 24
Peak memory 191164 kb
Host smart-24aadf7a-bed5-4edb-aa2e-63384bd8fd8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671566674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1671566674
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3000606973
Short name T325
Test name
Test status
Simulation time 267916374505 ps
CPU time 93.53 seconds
Started Jul 01 10:54:39 AM PDT 24
Finished Jul 01 10:56:13 AM PDT 24
Peak memory 191312 kb
Host smart-d345dabe-0771-4825-9207-a54e3ad29ded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000606973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3000606973
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.597064324
Short name T69
Test name
Test status
Simulation time 164796865603 ps
CPU time 76.1 seconds
Started Jul 01 10:54:40 AM PDT 24
Finished Jul 01 10:55:57 AM PDT 24
Peak memory 191296 kb
Host smart-b432e9a1-b01d-4d37-a9ed-ab5ad36335d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597064324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.597064324
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1389504552
Short name T272
Test name
Test status
Simulation time 60434809128 ps
CPU time 22.32 seconds
Started Jul 01 10:53:05 AM PDT 24
Finished Jul 01 10:53:31 AM PDT 24
Peak memory 183084 kb
Host smart-0806b011-d00a-4192-8726-ea7ec7587d6e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389504552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1389504552
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_random.3231220200
Short name T177
Test name
Test status
Simulation time 1013502020011 ps
CPU time 382.69 seconds
Started Jul 01 10:53:00 AM PDT 24
Finished Jul 01 10:59:26 AM PDT 24
Peak memory 191296 kb
Host smart-e09ba841-8fcc-45cb-9ab7-18a9bac262a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231220200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3231220200
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.294386542
Short name T169
Test name
Test status
Simulation time 533386263462 ps
CPU time 920.35 seconds
Started Jul 01 10:53:06 AM PDT 24
Finished Jul 01 11:08:29 AM PDT 24
Peak memory 195620 kb
Host smart-f0fb21bc-20e2-4566-9227-e0a0eb24bed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294386542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
294386542
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/167.rv_timer_random.1311172188
Short name T178
Test name
Test status
Simulation time 512143329394 ps
CPU time 732.52 seconds
Started Jul 01 10:54:45 AM PDT 24
Finished Jul 01 11:06:58 AM PDT 24
Peak memory 191284 kb
Host smart-fca8df0d-73ac-433b-90e0-93d146bf83eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311172188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1311172188
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1600086120
Short name T233
Test name
Test status
Simulation time 53855379216 ps
CPU time 521.74 seconds
Started Jul 01 10:52:56 AM PDT 24
Finished Jul 01 11:01:42 AM PDT 24
Peak memory 191336 kb
Host smart-68d0691d-c5c3-4e51-8659-cfacd0f1f70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600086120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1600086120
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/176.rv_timer_random.2463125337
Short name T289
Test name
Test status
Simulation time 66952740565 ps
CPU time 506.66 seconds
Started Jul 01 10:54:56 AM PDT 24
Finished Jul 01 11:03:24 AM PDT 24
Peak memory 191292 kb
Host smart-50f6f3e0-0fcc-4b27-bfec-a01dd95ad967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463125337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2463125337
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.4271790785
Short name T339
Test name
Test status
Simulation time 768370609739 ps
CPU time 579.88 seconds
Started Jul 01 10:52:56 AM PDT 24
Finished Jul 01 11:02:40 AM PDT 24
Peak memory 193640 kb
Host smart-429810d2-0d7f-4ea1-99a7-e667818a9d92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271790785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.4271790785
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.4189733560
Short name T303
Test name
Test status
Simulation time 94747735694 ps
CPU time 155.5 seconds
Started Jul 01 10:55:01 AM PDT 24
Finished Jul 01 10:57:37 AM PDT 24
Peak memory 194680 kb
Host smart-2ad66c1f-1517-44a5-9bf0-31e1dc29fb59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189733560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.4189733560
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1126326787
Short name T304
Test name
Test status
Simulation time 579684810519 ps
CPU time 406.74 seconds
Started Jul 01 10:55:00 AM PDT 24
Finished Jul 01 11:01:48 AM PDT 24
Peak memory 191312 kb
Host smart-7d9689ac-6513-4927-a4ac-db7a35937c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126326787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1126326787
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.566550369
Short name T121
Test name
Test status
Simulation time 1624359483849 ps
CPU time 1524.23 seconds
Started Jul 01 10:53:16 AM PDT 24
Finished Jul 01 11:18:45 AM PDT 24
Peak memory 191224 kb
Host smart-77e35f69-ba9b-4b18-b2ed-50249daddff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566550369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.566550369
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2772044506
Short name T265
Test name
Test status
Simulation time 26365969980 ps
CPU time 41.81 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 10:54:15 AM PDT 24
Peak memory 183076 kb
Host smart-d81b1eea-8697-4a7e-857c-fbf38b028a18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772044506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2772044506
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.397187577
Short name T249
Test name
Test status
Simulation time 111159554926 ps
CPU time 154.27 seconds
Started Jul 01 10:53:33 AM PDT 24
Finished Jul 01 10:56:08 AM PDT 24
Peak memory 183040 kb
Host smart-48de29db-6768-42e9-a58f-718d30b689e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397187577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.397187577
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_random.2329398549
Short name T115
Test name
Test status
Simulation time 85424300315 ps
CPU time 138.42 seconds
Started Jul 01 10:53:17 AM PDT 24
Finished Jul 01 10:55:40 AM PDT 24
Peak memory 191304 kb
Host smart-832d8d73-c550-478f-a414-72ae0b430324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329398549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2329398549
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3981638817
Short name T114
Test name
Test status
Simulation time 71036135042 ps
CPU time 74.01 seconds
Started Jul 01 10:53:27 AM PDT 24
Finished Jul 01 10:54:42 AM PDT 24
Peak memory 183116 kb
Host smart-d408b5e0-f27f-4ff8-9ce8-c850e8a6e29b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981638817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3981638817
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/69.rv_timer_random.37019709
Short name T360
Test name
Test status
Simulation time 32865492401 ps
CPU time 54.64 seconds
Started Jul 01 10:53:45 AM PDT 24
Finished Jul 01 10:54:40 AM PDT 24
Peak memory 191300 kb
Host smart-b93686e9-b023-4327-accc-3358abcf026f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37019709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.37019709
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2748063296
Short name T153
Test name
Test status
Simulation time 29695727211 ps
CPU time 104.94 seconds
Started Jul 01 10:54:03 AM PDT 24
Finished Jul 01 10:55:48 AM PDT 24
Peak memory 191292 kb
Host smart-209211fc-a047-47a6-abf0-7868faf3e772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748063296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2748063296
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2834118621
Short name T561
Test name
Test status
Simulation time 15656038 ps
CPU time 0.6 seconds
Started Jul 01 10:34:07 AM PDT 24
Finished Jul 01 10:34:10 AM PDT 24
Peak memory 182152 kb
Host smart-5a8b0a4a-fd23-42fd-a5d7-6ec4394ef36b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834118621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2834118621
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3778573902
Short name T554
Test name
Test status
Simulation time 192425866 ps
CPU time 2.56 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 190524 kb
Host smart-d9165467-81a1-455a-ad06-18414075958a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778573902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3778573902
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.777356098
Short name T544
Test name
Test status
Simulation time 22488788 ps
CPU time 0.56 seconds
Started Jul 01 10:33:42 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 182080 kb
Host smart-b0915351-ee70-4a9e-ad22-ba656ec04ce0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777356098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.777356098
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1059351737
Short name T579
Test name
Test status
Simulation time 44721865 ps
CPU time 0.79 seconds
Started Jul 01 10:33:54 AM PDT 24
Finished Jul 01 10:33:58 AM PDT 24
Peak memory 194536 kb
Host smart-74d5eba6-3325-4bde-8cfc-204eb1d385c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059351737 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1059351737
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.4107162871
Short name T87
Test name
Test status
Simulation time 15356805 ps
CPU time 0.56 seconds
Started Jul 01 10:33:39 AM PDT 24
Finished Jul 01 10:33:40 AM PDT 24
Peak memory 182168 kb
Host smart-6cc4eac5-ce2e-41f3-98a8-c1a363e18499
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107162871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.4107162871
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3361071576
Short name T495
Test name
Test status
Simulation time 58375350 ps
CPU time 0.56 seconds
Started Jul 01 10:33:42 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 182068 kb
Host smart-4320217b-2995-4836-b77c-bfac083782a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361071576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3361071576
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2144336789
Short name T553
Test name
Test status
Simulation time 505114349 ps
CPU time 2.37 seconds
Started Jul 01 10:33:41 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 196924 kb
Host smart-66310e89-6113-4cf2-9a56-cf033d8b4a36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144336789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2144336789
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3321579965
Short name T510
Test name
Test status
Simulation time 111992236 ps
CPU time 0.7 seconds
Started Jul 01 10:33:43 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 182136 kb
Host smart-ae07965c-a090-4f04-bab4-061b85fb50e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321579965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3321579965
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.136161094
Short name T30
Test name
Test status
Simulation time 203198772 ps
CPU time 1.42 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 190520 kb
Host smart-3790f753-19da-455a-a13e-29df1133e106
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136161094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.136161094
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2737810685
Short name T31
Test name
Test status
Simulation time 19688196 ps
CPU time 0.58 seconds
Started Jul 01 10:33:38 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 182012 kb
Host smart-844f645c-a7da-4fbe-8147-4ecd5a682426
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737810685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2737810685
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.972931308
Short name T548
Test name
Test status
Simulation time 24476290 ps
CPU time 0.7 seconds
Started Jul 01 10:33:39 AM PDT 24
Finished Jul 01 10:33:41 AM PDT 24
Peak memory 194432 kb
Host smart-e56fa184-fedc-421d-be46-53e53ed4cd28
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972931308 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.972931308
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2079324295
Short name T571
Test name
Test status
Simulation time 30450772 ps
CPU time 0.54 seconds
Started Jul 01 10:33:41 AM PDT 24
Finished Jul 01 10:33:42 AM PDT 24
Peak memory 182144 kb
Host smart-4441046e-8934-4977-94e6-9923eca7979a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079324295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2079324295
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2368333325
Short name T503
Test name
Test status
Simulation time 40911562 ps
CPU time 0.57 seconds
Started Jul 01 10:33:50 AM PDT 24
Finished Jul 01 10:33:53 AM PDT 24
Peak memory 182028 kb
Host smart-429eea37-c99b-4f79-8d92-316d1c8ef022
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368333325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2368333325
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1681696570
Short name T501
Test name
Test status
Simulation time 61156844 ps
CPU time 0.63 seconds
Started Jul 01 10:33:47 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 191432 kb
Host smart-31e86c82-ecc4-4f55-bbaf-9038aa878b9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681696570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1681696570
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3566497986
Short name T516
Test name
Test status
Simulation time 729001193 ps
CPU time 2.87 seconds
Started Jul 01 10:33:40 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 196964 kb
Host smart-cb8ab394-53b8-48d4-8603-501722e98868
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566497986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3566497986
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2585221553
Short name T535
Test name
Test status
Simulation time 74304120 ps
CPU time 0.82 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 196300 kb
Host smart-3fc2ee08-8b7b-4429-a26d-de8cd59db317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585221553 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2585221553
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1352090814
Short name T82
Test name
Test status
Simulation time 31864710 ps
CPU time 0.59 seconds
Started Jul 01 10:34:01 AM PDT 24
Finished Jul 01 10:34:03 AM PDT 24
Peak memory 182108 kb
Host smart-cf135ede-2a82-47bb-a7b8-a7e10c2cbfc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352090814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1352090814
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1476193515
Short name T545
Test name
Test status
Simulation time 24927405 ps
CPU time 0.57 seconds
Started Jul 01 10:33:47 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 181532 kb
Host smart-bf8521ad-ce3b-4e98-8d07-7b96f47b6b4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476193515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1476193515
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3239674112
Short name T77
Test name
Test status
Simulation time 111601620 ps
CPU time 0.72 seconds
Started Jul 01 10:33:48 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 193468 kb
Host smart-9b205394-94e2-4d66-a95c-a0fab03b20de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239674112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3239674112
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.170629486
Short name T559
Test name
Test status
Simulation time 21755495 ps
CPU time 1.09 seconds
Started Jul 01 10:33:49 AM PDT 24
Finished Jul 01 10:33:52 AM PDT 24
Peak memory 195424 kb
Host smart-dea1495f-2010-4f6a-a0b8-886f04f10133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170629486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.170629486
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1391866774
Short name T29
Test name
Test status
Simulation time 115435224 ps
CPU time 1.41 seconds
Started Jul 01 10:33:57 AM PDT 24
Finished Jul 01 10:34:00 AM PDT 24
Peak memory 194884 kb
Host smart-b88d5835-101b-4756-91a9-6fc213d077cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391866774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1391866774
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.346959710
Short name T492
Test name
Test status
Simulation time 37298208 ps
CPU time 0.88 seconds
Started Jul 01 10:33:47 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 195788 kb
Host smart-1e2485eb-4349-4c89-aa04-3b9b11e42ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346959710 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.346959710
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.507916012
Short name T576
Test name
Test status
Simulation time 24202388 ps
CPU time 0.51 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:05 AM PDT 24
Peak memory 181952 kb
Host smart-8479758d-147d-4bde-89cf-c77b7345cd73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507916012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.507916012
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1146585163
Short name T488
Test name
Test status
Simulation time 43254301 ps
CPU time 0.52 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:09 AM PDT 24
Peak memory 181440 kb
Host smart-e7b34bab-12b2-487f-bd00-51d73edbce04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146585163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1146585163
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3552878737
Short name T92
Test name
Test status
Simulation time 102966951 ps
CPU time 0.75 seconds
Started Jul 01 10:33:45 AM PDT 24
Finished Jul 01 10:33:47 AM PDT 24
Peak memory 192936 kb
Host smart-d286c4c6-a07d-4de4-8737-1fe6b504a8ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552878737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3552878737
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3031027044
Short name T466
Test name
Test status
Simulation time 232095633 ps
CPU time 2.57 seconds
Started Jul 01 10:34:00 AM PDT 24
Finished Jul 01 10:34:03 AM PDT 24
Peak memory 196896 kb
Host smart-abe7acdf-ec33-48b5-a91b-599c63bb29ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031027044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3031027044
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1969464920
Short name T537
Test name
Test status
Simulation time 1254225373 ps
CPU time 1.32 seconds
Started Jul 01 10:33:51 AM PDT 24
Finished Jul 01 10:33:56 AM PDT 24
Peak memory 182868 kb
Host smart-e72bac4b-5ebb-497b-b39a-67168d4c1fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969464920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1969464920
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.376808772
Short name T523
Test name
Test status
Simulation time 27085216 ps
CPU time 1.23 seconds
Started Jul 01 10:33:50 AM PDT 24
Finished Jul 01 10:33:53 AM PDT 24
Peak memory 196936 kb
Host smart-af6d7b47-9262-4623-bc60-9632d10ed6b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376808772 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.376808772
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3834879094
Short name T83
Test name
Test status
Simulation time 46276309 ps
CPU time 0.51 seconds
Started Jul 01 10:33:45 AM PDT 24
Finished Jul 01 10:33:47 AM PDT 24
Peak memory 181920 kb
Host smart-f36b67f4-b6bc-447a-8d53-f50c5cb361db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834879094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3834879094
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.285746395
Short name T463
Test name
Test status
Simulation time 32951871 ps
CPU time 0.52 seconds
Started Jul 01 10:33:44 AM PDT 24
Finished Jul 01 10:33:45 AM PDT 24
Peak memory 182048 kb
Host smart-2ed2da16-58a9-4d94-8597-f6c0dea46afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285746395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.285746395
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.475703310
Short name T582
Test name
Test status
Simulation time 17978794 ps
CPU time 0.69 seconds
Started Jul 01 10:33:58 AM PDT 24
Finished Jul 01 10:34:00 AM PDT 24
Peak memory 192676 kb
Host smart-b53a1703-8823-439c-aedc-1a6fcee09a80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475703310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.475703310
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1032863402
Short name T486
Test name
Test status
Simulation time 522739613 ps
CPU time 1.85 seconds
Started Jul 01 10:34:01 AM PDT 24
Finished Jul 01 10:34:03 AM PDT 24
Peak memory 196960 kb
Host smart-4100b86c-a038-4fad-91a0-e121cec9553e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032863402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1032863402
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3665516326
Short name T484
Test name
Test status
Simulation time 73492291 ps
CPU time 0.89 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:56 AM PDT 24
Peak memory 193532 kb
Host smart-7b1b0380-d320-4def-a9fc-af91b0bb3077
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665516326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3665516326
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2957424669
Short name T511
Test name
Test status
Simulation time 36268130 ps
CPU time 0.91 seconds
Started Jul 01 10:33:45 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 196748 kb
Host smart-99064c51-34d1-41f8-ad59-8cac94c8cead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957424669 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2957424669
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1481110405
Short name T81
Test name
Test status
Simulation time 28049801 ps
CPU time 0.59 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 182164 kb
Host smart-3c6b98e5-b82f-4e75-8fdf-036080e43445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481110405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1481110405
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1637707006
Short name T502
Test name
Test status
Simulation time 44227039 ps
CPU time 0.56 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:06 AM PDT 24
Peak memory 182092 kb
Host smart-c3b616fe-7e8a-40b5-bfc1-60bcd7af6627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637707006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1637707006
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1491300597
Short name T94
Test name
Test status
Simulation time 13827620 ps
CPU time 0.68 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 191684 kb
Host smart-4f789218-696d-46e9-99d9-f79948457c6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491300597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1491300597
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2535464959
Short name T549
Test name
Test status
Simulation time 47043936 ps
CPU time 1.09 seconds
Started Jul 01 10:33:54 AM PDT 24
Finished Jul 01 10:33:58 AM PDT 24
Peak memory 196772 kb
Host smart-53409e62-4292-4ee2-b7c9-e75d99836334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535464959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2535464959
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1716568492
Short name T506
Test name
Test status
Simulation time 142639467 ps
CPU time 0.88 seconds
Started Jul 01 10:33:52 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 192216 kb
Host smart-044f7bb1-5d23-466f-aac8-503577cf76f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716568492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1716568492
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.544427754
Short name T48
Test name
Test status
Simulation time 96564930 ps
CPU time 0.77 seconds
Started Jul 01 10:33:53 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 195076 kb
Host smart-a0830900-0343-4198-bb43-c13ff8283f9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544427754 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.544427754
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3832420592
Short name T471
Test name
Test status
Simulation time 12158792 ps
CPU time 0.56 seconds
Started Jul 01 10:33:48 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 182100 kb
Host smart-2e55a5f7-098f-44cf-8d55-3659d1c65f61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832420592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3832420592
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.168336859
Short name T530
Test name
Test status
Simulation time 32186914 ps
CPU time 0.78 seconds
Started Jul 01 10:33:47 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 192944 kb
Host smart-7cbce141-f446-4c1d-94c0-9313613e3d3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168336859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.168336859
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1709354685
Short name T509
Test name
Test status
Simulation time 348502538 ps
CPU time 1.21 seconds
Started Jul 01 10:33:58 AM PDT 24
Finished Jul 01 10:34:01 AM PDT 24
Peak memory 196948 kb
Host smart-2e84e6af-feed-42c5-bcd8-e564568ffd25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709354685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1709354685
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2459093691
Short name T578
Test name
Test status
Simulation time 555206395 ps
CPU time 1.02 seconds
Started Jul 01 10:33:48 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 182592 kb
Host smart-37baf15a-8fec-4c5e-9ed4-dbe6e18e0c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459093691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2459093691
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3243242782
Short name T467
Test name
Test status
Simulation time 113541736 ps
CPU time 1.48 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:06 AM PDT 24
Peak memory 197000 kb
Host smart-33e08a96-9b77-415c-8651-94b2546d27e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243242782 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3243242782
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3154653274
Short name T546
Test name
Test status
Simulation time 55868356 ps
CPU time 0.55 seconds
Started Jul 01 10:34:02 AM PDT 24
Finished Jul 01 10:34:04 AM PDT 24
Peak memory 182172 kb
Host smart-d7e363a8-b3f6-4918-ac85-529dd8c3b29e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154653274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3154653274
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1242637613
Short name T455
Test name
Test status
Simulation time 38033505 ps
CPU time 0.54 seconds
Started Jul 01 10:33:49 AM PDT 24
Finished Jul 01 10:33:52 AM PDT 24
Peak memory 181668 kb
Host smart-8898fa02-d40b-40d6-9bbf-c7b6d878c8a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242637613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1242637613
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3360283920
Short name T521
Test name
Test status
Simulation time 15110864 ps
CPU time 0.6 seconds
Started Jul 01 10:33:47 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 191348 kb
Host smart-139666c0-a8e9-4820-bb0a-7959a1267509
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360283920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3360283920
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1670122400
Short name T475
Test name
Test status
Simulation time 1151374404 ps
CPU time 2.12 seconds
Started Jul 01 10:33:53 AM PDT 24
Finished Jul 01 10:33:58 AM PDT 24
Peak memory 196968 kb
Host smart-976c84e8-67cc-4a96-8cd6-d30a4b092302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670122400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1670122400
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4049890676
Short name T567
Test name
Test status
Simulation time 45664687 ps
CPU time 0.82 seconds
Started Jul 01 10:33:43 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 193084 kb
Host smart-abf43904-7918-4927-997a-db33b399b5fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049890676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.4049890676
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.663548576
Short name T573
Test name
Test status
Simulation time 98310846 ps
CPU time 0.74 seconds
Started Jul 01 10:33:52 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 194432 kb
Host smart-036c28b4-4f87-4e49-978d-26b9f58ecab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663548576 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.663548576
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1350029371
Short name T90
Test name
Test status
Simulation time 29642248 ps
CPU time 0.56 seconds
Started Jul 01 10:33:47 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 182124 kb
Host smart-d8dae4b5-adf8-4116-8361-b0398ee7e662
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350029371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1350029371
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2628520594
Short name T465
Test name
Test status
Simulation time 45196986 ps
CPU time 0.55 seconds
Started Jul 01 10:33:50 AM PDT 24
Finished Jul 01 10:33:54 AM PDT 24
Peak memory 181996 kb
Host smart-d7947bab-a3e7-4f59-9f43-33bb8b8b9117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628520594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2628520594
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.4266241950
Short name T80
Test name
Test status
Simulation time 38695602 ps
CPU time 0.8 seconds
Started Jul 01 10:34:01 AM PDT 24
Finished Jul 01 10:34:03 AM PDT 24
Peak memory 192684 kb
Host smart-317c6df6-5a6e-4658-9199-906eabf76fe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266241950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.4266241950
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4201133180
Short name T460
Test name
Test status
Simulation time 220880336 ps
CPU time 1.3 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 196232 kb
Host smart-328a10d6-16e3-420a-bee9-d493c3f36250
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201133180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4201133180
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.4204922515
Short name T101
Test name
Test status
Simulation time 235211090 ps
CPU time 1.27 seconds
Started Jul 01 10:33:49 AM PDT 24
Finished Jul 01 10:33:52 AM PDT 24
Peak memory 193856 kb
Host smart-f0791026-ad03-44bc-8f1e-08abbe8f8742
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204922515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.4204922515
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4145154468
Short name T513
Test name
Test status
Simulation time 59654507 ps
CPU time 0.88 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:06 AM PDT 24
Peak memory 195904 kb
Host smart-25f356a3-235f-4935-99c1-107fa7e0427e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145154468 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.4145154468
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2563083784
Short name T477
Test name
Test status
Simulation time 54806692 ps
CPU time 0.59 seconds
Started Jul 01 10:33:58 AM PDT 24
Finished Jul 01 10:34:00 AM PDT 24
Peak memory 182164 kb
Host smart-1910f68b-1879-464d-b086-86e5e7196c36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563083784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2563083784
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3236569215
Short name T459
Test name
Test status
Simulation time 13147668 ps
CPU time 0.51 seconds
Started Jul 01 10:33:54 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 181512 kb
Host smart-f28a6dbc-f353-489c-a965-19f6e9d309a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236569215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3236569215
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.131595562
Short name T547
Test name
Test status
Simulation time 33160030 ps
CPU time 0.79 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:08 AM PDT 24
Peak memory 191036 kb
Host smart-14bc3f44-2432-4813-abb4-b404eaddc09d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131595562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.131595562
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.940922301
Short name T575
Test name
Test status
Simulation time 54343617 ps
CPU time 2.62 seconds
Started Jul 01 10:34:00 AM PDT 24
Finished Jul 01 10:34:03 AM PDT 24
Peak memory 196944 kb
Host smart-9784afa5-a00b-4538-833a-3086e231e9af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940922301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.940922301
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3196035603
Short name T100
Test name
Test status
Simulation time 290389924 ps
CPU time 0.98 seconds
Started Jul 01 10:33:52 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 194408 kb
Host smart-e9a11884-68a4-43ec-887d-71f127bdd35e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196035603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3196035603
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.72470097
Short name T558
Test name
Test status
Simulation time 81846481 ps
CPU time 0.85 seconds
Started Jul 01 10:34:17 AM PDT 24
Finished Jul 01 10:34:21 AM PDT 24
Peak memory 196352 kb
Host smart-c8389fd0-7304-44ed-a74c-eb0fa432145e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72470097 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.72470097
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.1399081835
Short name T89
Test name
Test status
Simulation time 110815950 ps
CPU time 0.63 seconds
Started Jul 01 10:34:01 AM PDT 24
Finished Jul 01 10:34:03 AM PDT 24
Peak memory 182172 kb
Host smart-a9f63429-525d-4c1e-aed3-cf085f64011b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399081835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.1399081835
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.2049915627
Short name T496
Test name
Test status
Simulation time 13711522 ps
CPU time 0.55 seconds
Started Jul 01 10:33:57 AM PDT 24
Finished Jul 01 10:33:59 AM PDT 24
Peak memory 182028 kb
Host smart-6e2842d2-7c68-423e-9cd7-1f6045a22c48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049915627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.2049915627
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1426788407
Short name T565
Test name
Test status
Simulation time 200900546 ps
CPU time 0.77 seconds
Started Jul 01 10:33:50 AM PDT 24
Finished Jul 01 10:33:54 AM PDT 24
Peak memory 191084 kb
Host smart-da339134-da99-47bd-b049-4047823092de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426788407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1426788407
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1605772188
Short name T456
Test name
Test status
Simulation time 77422248 ps
CPU time 1.11 seconds
Started Jul 01 10:34:09 AM PDT 24
Finished Jul 01 10:34:12 AM PDT 24
Peak memory 196964 kb
Host smart-10be22e9-0de3-4b71-ac0f-34a912e55ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605772188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1605772188
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1617441826
Short name T28
Test name
Test status
Simulation time 536657958 ps
CPU time 0.82 seconds
Started Jul 01 10:33:51 AM PDT 24
Finished Jul 01 10:33:55 AM PDT 24
Peak memory 193152 kb
Host smart-b653b2a7-aac8-4553-8e56-8caecad18fd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617441826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1617441826
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.833371437
Short name T540
Test name
Test status
Simulation time 103945783 ps
CPU time 0.75 seconds
Started Jul 01 10:33:50 AM PDT 24
Finished Jul 01 10:33:55 AM PDT 24
Peak memory 194360 kb
Host smart-2c697eea-541b-4e2c-a32e-17b83e8ce4d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833371437 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.833371437
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1320822702
Short name T555
Test name
Test status
Simulation time 17464487 ps
CPU time 0.62 seconds
Started Jul 01 10:34:00 AM PDT 24
Finished Jul 01 10:34:02 AM PDT 24
Peak memory 182168 kb
Host smart-3d7ff9dc-a9ea-4d38-9038-65ab3566fee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320822702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1320822702
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1929811786
Short name T551
Test name
Test status
Simulation time 13294386 ps
CPU time 0.54 seconds
Started Jul 01 10:33:54 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 182052 kb
Host smart-70aea2c4-6a6b-4474-b80a-0fbf5df7cacc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929811786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1929811786
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3917605031
Short name T527
Test name
Test status
Simulation time 14566036 ps
CPU time 0.6 seconds
Started Jul 01 10:33:50 AM PDT 24
Finished Jul 01 10:33:54 AM PDT 24
Peak memory 190868 kb
Host smart-b82976db-28b9-46a7-8a4b-7a539c7ea409
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917605031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3917605031
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3418446095
Short name T568
Test name
Test status
Simulation time 1633585476 ps
CPU time 2.14 seconds
Started Jul 01 10:34:02 AM PDT 24
Finished Jul 01 10:34:05 AM PDT 24
Peak memory 196872 kb
Host smart-690ba697-6c5f-4319-902a-ee8e2030cd74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418446095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3418446095
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2366447223
Short name T569
Test name
Test status
Simulation time 99903826 ps
CPU time 0.84 seconds
Started Jul 01 10:34:09 AM PDT 24
Finished Jul 01 10:34:12 AM PDT 24
Peak memory 192940 kb
Host smart-1c17b99c-e608-4bb7-8114-0fc873217f90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366447223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2366447223
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.906861693
Short name T88
Test name
Test status
Simulation time 73259184 ps
CPU time 0.69 seconds
Started Jul 01 10:33:42 AM PDT 24
Finished Jul 01 10:33:43 AM PDT 24
Peak memory 182172 kb
Host smart-03b0160c-60f2-4557-8e02-b900e7d03be5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906861693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.906861693
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1483094498
Short name T485
Test name
Test status
Simulation time 929727398 ps
CPU time 2.61 seconds
Started Jul 01 10:33:49 AM PDT 24
Finished Jul 01 10:33:54 AM PDT 24
Peak memory 190500 kb
Host smart-f215691b-f2e7-4ff6-bbf6-e483ae0d772c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483094498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1483094498
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2365975417
Short name T472
Test name
Test status
Simulation time 54251613 ps
CPU time 0.57 seconds
Started Jul 01 10:33:40 AM PDT 24
Finished Jul 01 10:33:41 AM PDT 24
Peak memory 182012 kb
Host smart-9b3d7b1e-6684-42bf-9a7e-ae18a81b75cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365975417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2365975417
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1567386578
Short name T583
Test name
Test status
Simulation time 108143903 ps
CPU time 1.25 seconds
Started Jul 01 10:33:47 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 196980 kb
Host smart-416046de-ade9-4498-84a6-4adf00e0bff3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567386578 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1567386578
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3055096953
Short name T499
Test name
Test status
Simulation time 16618145 ps
CPU time 0.57 seconds
Started Jul 01 10:33:39 AM PDT 24
Finished Jul 01 10:33:40 AM PDT 24
Peak memory 182172 kb
Host smart-9f9e164b-efb1-4512-9f23-fe5ffbb9d7ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055096953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3055096953
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1753150360
Short name T541
Test name
Test status
Simulation time 23146806 ps
CPU time 0.53 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 182044 kb
Host smart-ed5bb8f7-f522-4c68-8bbc-97c25f9b8af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753150360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1753150360
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3568015958
Short name T515
Test name
Test status
Simulation time 15762620 ps
CPU time 0.67 seconds
Started Jul 01 10:33:36 AM PDT 24
Finished Jul 01 10:33:37 AM PDT 24
Peak memory 191108 kb
Host smart-3006d43e-a20e-4a31-839e-e06abdff4075
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568015958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3568015958
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1997940621
Short name T464
Test name
Test status
Simulation time 44440288 ps
CPU time 2.25 seconds
Started Jul 01 10:33:48 AM PDT 24
Finished Jul 01 10:33:52 AM PDT 24
Peak memory 196780 kb
Host smart-56288a9e-45e2-4fe0-ac71-673bf8c6331f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997940621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1997940621
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2056693418
Short name T99
Test name
Test status
Simulation time 75767992 ps
CPU time 0.88 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 192980 kb
Host smart-2ff90cd3-4852-43f6-b1c0-88a3766c8e16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056693418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2056693418
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4079109347
Short name T563
Test name
Test status
Simulation time 15109798 ps
CPU time 0.56 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:05 AM PDT 24
Peak memory 182092 kb
Host smart-dd1dea6d-b831-46c2-b1bd-3ef1ecac8091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079109347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4079109347
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1940836871
Short name T564
Test name
Test status
Simulation time 180451232 ps
CPU time 0.55 seconds
Started Jul 01 10:33:58 AM PDT 24
Finished Jul 01 10:34:00 AM PDT 24
Peak memory 182012 kb
Host smart-95644631-5321-41bc-8528-9cd8876c3798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940836871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1940836871
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2204023643
Short name T476
Test name
Test status
Simulation time 31898547 ps
CPU time 0.57 seconds
Started Jul 01 10:33:57 AM PDT 24
Finished Jul 01 10:33:59 AM PDT 24
Peak memory 182104 kb
Host smart-af2fc867-3970-4602-8e57-2b9b590b7a20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204023643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2204023643
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.640521782
Short name T483
Test name
Test status
Simulation time 34314571 ps
CPU time 0.55 seconds
Started Jul 01 10:33:58 AM PDT 24
Finished Jul 01 10:34:00 AM PDT 24
Peak memory 181724 kb
Host smart-d8b9338a-d1d8-4152-a75e-f964d867bab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640521782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.640521782
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.3901518528
Short name T462
Test name
Test status
Simulation time 81270031 ps
CPU time 0.57 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 182020 kb
Host smart-d02a03ea-a60a-43dc-a46d-4a01f9c9584a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901518528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.3901518528
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2063166546
Short name T468
Test name
Test status
Simulation time 14895891 ps
CPU time 0.57 seconds
Started Jul 01 10:33:53 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 181968 kb
Host smart-8ec9f340-fd68-467e-b851-e5317a10ebe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063166546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2063166546
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.450011298
Short name T581
Test name
Test status
Simulation time 24476233 ps
CPU time 0.55 seconds
Started Jul 01 10:34:00 AM PDT 24
Finished Jul 01 10:34:01 AM PDT 24
Peak memory 181540 kb
Host smart-459560a5-d380-40d5-82bb-e25c9161108b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450011298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.450011298
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.926377949
Short name T505
Test name
Test status
Simulation time 35139542 ps
CPU time 0.54 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:12 AM PDT 24
Peak memory 181688 kb
Host smart-4005e359-4fb5-47ee-81aa-a49cd6eb9075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926377949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.926377949
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2380323364
Short name T512
Test name
Test status
Simulation time 48827775 ps
CPU time 0.56 seconds
Started Jul 01 10:34:03 AM PDT 24
Finished Jul 01 10:34:05 AM PDT 24
Peak memory 182068 kb
Host smart-9adae67d-90ba-4838-8849-0f87db873183
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380323364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2380323364
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3425396
Short name T497
Test name
Test status
Simulation time 16526444 ps
CPU time 0.53 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 181544 kb
Host smart-a4fa0513-274a-4b33-9064-2151350b7c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3425396
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3433924926
Short name T500
Test name
Test status
Simulation time 46697095 ps
CPU time 0.87 seconds
Started Jul 01 10:33:50 AM PDT 24
Finished Jul 01 10:33:53 AM PDT 24
Peak memory 190340 kb
Host smart-4e8b7179-2656-4a6b-a896-b09c9aab4edb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433924926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3433924926
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.167116703
Short name T557
Test name
Test status
Simulation time 350847184 ps
CPU time 3.27 seconds
Started Jul 01 10:33:51 AM PDT 24
Finished Jul 01 10:33:59 AM PDT 24
Peak memory 182244 kb
Host smart-aff7d2f8-b390-4d93-927b-d5135113b1e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167116703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.167116703
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1321412921
Short name T577
Test name
Test status
Simulation time 44192715 ps
CPU time 0.54 seconds
Started Jul 01 10:33:44 AM PDT 24
Finished Jul 01 10:33:46 AM PDT 24
Peak memory 182012 kb
Host smart-3a4c0b2b-a4bb-49a1-b4de-14d9c00208cc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321412921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1321412921
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3692012165
Short name T481
Test name
Test status
Simulation time 130458947 ps
CPU time 1.02 seconds
Started Jul 01 10:33:45 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 196792 kb
Host smart-a25251be-def1-40d3-a80b-46f6b890d5ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692012165 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3692012165
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3068386074
Short name T98
Test name
Test status
Simulation time 13892871 ps
CPU time 0.54 seconds
Started Jul 01 10:33:38 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 182140 kb
Host smart-864b713d-7593-4647-92e8-9dbbb77c7756
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068386074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3068386074
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.753027573
Short name T498
Test name
Test status
Simulation time 12930163 ps
CPU time 0.54 seconds
Started Jul 01 10:33:40 AM PDT 24
Finished Jul 01 10:33:41 AM PDT 24
Peak memory 181524 kb
Host smart-53d36b95-9ce9-4238-a7a5-2e07dc6f2f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753027573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.753027573
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.235497819
Short name T91
Test name
Test status
Simulation time 98091624 ps
CPU time 0.74 seconds
Started Jul 01 10:33:38 AM PDT 24
Finished Jul 01 10:33:39 AM PDT 24
Peak memory 191080 kb
Host smart-5d53482e-32b5-4756-9739-8a358a5d3d51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235497819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_tim
er_same_csr_outstanding.235497819
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2183124642
Short name T532
Test name
Test status
Simulation time 249272598 ps
CPU time 2 seconds
Started Jul 01 10:33:44 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 196952 kb
Host smart-01fc57c5-e77b-4f13-8db7-b6c62910f058
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183124642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2183124642
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.4125887660
Short name T47
Test name
Test status
Simulation time 83542851 ps
CPU time 0.87 seconds
Started Jul 01 10:33:51 AM PDT 24
Finished Jul 01 10:33:56 AM PDT 24
Peak memory 193184 kb
Host smart-56f476f1-dd26-4ea3-b963-b7446f821973
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125887660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.4125887660
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3658490811
Short name T480
Test name
Test status
Simulation time 14157499 ps
CPU time 0.54 seconds
Started Jul 01 10:34:07 AM PDT 24
Finished Jul 01 10:34:10 AM PDT 24
Peak memory 181652 kb
Host smart-cbedbe43-ee3d-4ba3-bd93-32ab90f77288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658490811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3658490811
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3550974996
Short name T534
Test name
Test status
Simulation time 13800428 ps
CPU time 0.56 seconds
Started Jul 01 10:33:59 AM PDT 24
Finished Jul 01 10:34:00 AM PDT 24
Peak memory 182060 kb
Host smart-98064dc0-19fc-4aa5-b240-8575b32d624f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550974996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3550974996
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3504011498
Short name T491
Test name
Test status
Simulation time 22178587 ps
CPU time 0.58 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:09 AM PDT 24
Peak memory 182100 kb
Host smart-e8082012-a1ad-482f-9b4a-7ab867af570f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504011498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3504011498
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.630268577
Short name T528
Test name
Test status
Simulation time 41924286 ps
CPU time 0.55 seconds
Started Jul 01 10:34:10 AM PDT 24
Finished Jul 01 10:34:13 AM PDT 24
Peak memory 182040 kb
Host smart-fca8ffd4-1674-44cb-86d2-810623c08adb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630268577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.630268577
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.401925541
Short name T473
Test name
Test status
Simulation time 17004213 ps
CPU time 0.56 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:19 AM PDT 24
Peak memory 182236 kb
Host smart-af8312ba-9895-45f3-90f0-4613e1dff1cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401925541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.401925541
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3115897672
Short name T487
Test name
Test status
Simulation time 31622388 ps
CPU time 0.57 seconds
Started Jul 01 10:34:00 AM PDT 24
Finished Jul 01 10:34:02 AM PDT 24
Peak memory 182024 kb
Host smart-754730be-3119-45cd-aa6f-38376bdb1148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115897672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3115897672
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.136522571
Short name T454
Test name
Test status
Simulation time 83936981 ps
CPU time 0.54 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:06 AM PDT 24
Peak memory 182024 kb
Host smart-e47a085a-d7c3-4d40-baba-c6f60b1503b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136522571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.136522571
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.789076893
Short name T526
Test name
Test status
Simulation time 25202214 ps
CPU time 0.52 seconds
Started Jul 01 10:33:58 AM PDT 24
Finished Jul 01 10:34:00 AM PDT 24
Peak memory 181544 kb
Host smart-6e621b9b-2134-4b82-b129-ce5e62c5c8fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789076893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.789076893
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3240265731
Short name T574
Test name
Test status
Simulation time 15632048 ps
CPU time 0.54 seconds
Started Jul 01 10:33:53 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 182012 kb
Host smart-c4cfe55b-6fd0-4db6-bd7d-fa99862a8610
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240265731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3240265731
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1139613106
Short name T572
Test name
Test status
Simulation time 74363039 ps
CPU time 0.55 seconds
Started Jul 01 10:33:57 AM PDT 24
Finished Jul 01 10:34:00 AM PDT 24
Peak memory 182088 kb
Host smart-b43f7f09-7cff-446f-8915-54de00b444ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139613106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1139613106
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1756064977
Short name T86
Test name
Test status
Simulation time 18843194 ps
CPU time 0.65 seconds
Started Jul 01 10:33:50 AM PDT 24
Finished Jul 01 10:33:53 AM PDT 24
Peak memory 182172 kb
Host smart-b4d3c067-178b-48b3-9c3e-33c0ec525657
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756064977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1756064977
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3366908840
Short name T470
Test name
Test status
Simulation time 189879404 ps
CPU time 2.55 seconds
Started Jul 01 10:33:42 AM PDT 24
Finished Jul 01 10:33:46 AM PDT 24
Peak memory 193252 kb
Host smart-076c8f01-62d2-46d0-8a1f-9f739efd1152
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366908840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3366908840
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.29246229
Short name T514
Test name
Test status
Simulation time 91611296 ps
CPU time 0.51 seconds
Started Jul 01 10:33:45 AM PDT 24
Finished Jul 01 10:33:47 AM PDT 24
Peak memory 181552 kb
Host smart-b020176b-320d-4be4-95f9-6c7fd19b2608
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29246229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_res
et.29246229
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1316007347
Short name T457
Test name
Test status
Simulation time 15948378 ps
CPU time 0.59 seconds
Started Jul 01 10:33:53 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 192588 kb
Host smart-c380da73-faf9-4f06-b1cb-3e182dc903f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316007347 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1316007347
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1188382779
Short name T520
Test name
Test status
Simulation time 21578360 ps
CPU time 0.56 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 182108 kb
Host smart-82fe9add-9b45-46e0-adab-bf42ff084702
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188382779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1188382779
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2262912726
Short name T489
Test name
Test status
Simulation time 44417334 ps
CPU time 0.59 seconds
Started Jul 01 10:33:48 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 182032 kb
Host smart-d705f481-a184-465f-94d4-5e6ded569bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262912726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2262912726
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2729844225
Short name T93
Test name
Test status
Simulation time 21889806 ps
CPU time 0.57 seconds
Started Jul 01 10:33:44 AM PDT 24
Finished Jul 01 10:33:46 AM PDT 24
Peak memory 191464 kb
Host smart-88439c0f-a0bd-43b8-b526-cc65ba74081f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729844225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2729844225
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1993218030
Short name T46
Test name
Test status
Simulation time 132551016 ps
CPU time 2.18 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 196912 kb
Host smart-9ecd70ee-9a80-4986-8d68-77ef6254fd8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993218030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1993218030
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2372968080
Short name T508
Test name
Test status
Simulation time 381967276 ps
CPU time 1.26 seconds
Started Jul 01 10:33:55 AM PDT 24
Finished Jul 01 10:33:58 AM PDT 24
Peak memory 194900 kb
Host smart-76187827-17d0-4a68-8ca2-534c7c5afabf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372968080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2372968080
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2655121980
Short name T478
Test name
Test status
Simulation time 28597829 ps
CPU time 0.55 seconds
Started Jul 01 10:33:58 AM PDT 24
Finished Jul 01 10:34:00 AM PDT 24
Peak memory 181976 kb
Host smart-d0f141c7-3220-4dab-94cd-5a749b38aec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655121980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2655121980
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1159992842
Short name T461
Test name
Test status
Simulation time 35282623 ps
CPU time 0.56 seconds
Started Jul 01 10:34:01 AM PDT 24
Finished Jul 01 10:34:03 AM PDT 24
Peak memory 182032 kb
Host smart-b9bb81a9-c826-4dd0-9d76-9283d6475b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159992842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1159992842
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.478651276
Short name T479
Test name
Test status
Simulation time 27853553 ps
CPU time 0.54 seconds
Started Jul 01 10:34:04 AM PDT 24
Finished Jul 01 10:34:07 AM PDT 24
Peak memory 182044 kb
Host smart-5f35bf0c-1611-47ee-ab58-09a9b2d018ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478651276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.478651276
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3281252320
Short name T474
Test name
Test status
Simulation time 80996619 ps
CPU time 0.55 seconds
Started Jul 01 10:34:08 AM PDT 24
Finished Jul 01 10:34:11 AM PDT 24
Peak memory 182084 kb
Host smart-8bb34ff5-0a64-467e-aa61-403507a6e602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281252320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3281252320
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4056124042
Short name T556
Test name
Test status
Simulation time 28006848 ps
CPU time 0.56 seconds
Started Jul 01 10:34:26 AM PDT 24
Finished Jul 01 10:34:27 AM PDT 24
Peak memory 182032 kb
Host smart-10e26c83-799f-43af-afe0-7a93a858cfad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056124042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4056124042
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3695005251
Short name T522
Test name
Test status
Simulation time 42181180 ps
CPU time 0.54 seconds
Started Jul 01 10:34:06 AM PDT 24
Finished Jul 01 10:34:09 AM PDT 24
Peak memory 182104 kb
Host smart-a95b0152-8ea2-4a6a-8319-5bbe8b02fd6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695005251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3695005251
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4176332325
Short name T531
Test name
Test status
Simulation time 17770347 ps
CPU time 0.54 seconds
Started Jul 01 10:34:02 AM PDT 24
Finished Jul 01 10:34:04 AM PDT 24
Peak memory 182092 kb
Host smart-158e7f64-6785-4d77-a51e-0f5bf558babf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176332325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.4176332325
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2146515246
Short name T580
Test name
Test status
Simulation time 24108879 ps
CPU time 0.53 seconds
Started Jul 01 10:34:01 AM PDT 24
Finished Jul 01 10:34:02 AM PDT 24
Peak memory 181508 kb
Host smart-6a084bf8-6679-4470-aba9-e3070b8503c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146515246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2146515246
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2391137490
Short name T490
Test name
Test status
Simulation time 34167587 ps
CPU time 0.54 seconds
Started Jul 01 10:34:05 AM PDT 24
Finished Jul 01 10:34:08 AM PDT 24
Peak memory 182060 kb
Host smart-f89a2351-e86a-4e3b-8301-82a34f2665d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391137490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2391137490
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.747208627
Short name T542
Test name
Test status
Simulation time 45985524 ps
CPU time 0.53 seconds
Started Jul 01 10:34:02 AM PDT 24
Finished Jul 01 10:34:04 AM PDT 24
Peak memory 182040 kb
Host smart-3250331a-1c21-4544-b373-eb83283766af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747208627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.747208627
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.632833119
Short name T49
Test name
Test status
Simulation time 27187050 ps
CPU time 0.61 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 193036 kb
Host smart-9d178738-34d9-4d9a-beac-575495393c36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632833119 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.632833119
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.115716088
Short name T469
Test name
Test status
Simulation time 12437049 ps
CPU time 0.58 seconds
Started Jul 01 10:33:44 AM PDT 24
Finished Jul 01 10:33:46 AM PDT 24
Peak memory 182152 kb
Host smart-bc3d96c9-c143-432f-9a4a-702956356e3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115716088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.115716088
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1826293714
Short name T518
Test name
Test status
Simulation time 13300253 ps
CPU time 0.59 seconds
Started Jul 01 10:33:47 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 182036 kb
Host smart-5b7f9ebd-6c9a-4961-9ac7-89db9b8a6590
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826293714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1826293714
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1415369888
Short name T538
Test name
Test status
Simulation time 33851119 ps
CPU time 0.74 seconds
Started Jul 01 10:33:48 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 191076 kb
Host smart-d2424280-f9ce-4f63-a61d-d900c1b833e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415369888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1415369888
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3646672682
Short name T482
Test name
Test status
Simulation time 110799568 ps
CPU time 1.89 seconds
Started Jul 01 10:33:47 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 196868 kb
Host smart-23cfbcaf-3adc-443f-9eb3-eed95c1b4bac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646672682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3646672682
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.987398396
Short name T504
Test name
Test status
Simulation time 473885258 ps
CPU time 1.22 seconds
Started Jul 01 10:33:41 AM PDT 24
Finished Jul 01 10:33:43 AM PDT 24
Peak memory 194732 kb
Host smart-edfd60f9-da30-443a-82f8-b5a46ffc8991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987398396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_int
g_err.987398396
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3688553945
Short name T458
Test name
Test status
Simulation time 107691215 ps
CPU time 0.89 seconds
Started Jul 01 10:33:43 AM PDT 24
Finished Jul 01 10:33:45 AM PDT 24
Peak memory 196528 kb
Host smart-5ddbc31c-e003-4d28-a760-5bdce27d13fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688553945 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3688553945
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3735583008
Short name T85
Test name
Test status
Simulation time 13120097 ps
CPU time 0.56 seconds
Started Jul 01 10:33:52 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 182172 kb
Host smart-f6eab6d6-ae11-48e9-b715-dcbf5e2125ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735583008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3735583008
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2724005139
Short name T533
Test name
Test status
Simulation time 18314597 ps
CPU time 0.55 seconds
Started Jul 01 10:33:50 AM PDT 24
Finished Jul 01 10:33:54 AM PDT 24
Peak memory 181968 kb
Host smart-07728447-9b3c-4ab9-a959-f2a5441de3d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724005139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2724005139
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2002150245
Short name T78
Test name
Test status
Simulation time 21394746 ps
CPU time 0.74 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 191132 kb
Host smart-a4600682-3a47-4dea-8595-494f7a845ccd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002150245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2002150245
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.176216246
Short name T60
Test name
Test status
Simulation time 2875092452 ps
CPU time 3.13 seconds
Started Jul 01 10:33:39 AM PDT 24
Finished Jul 01 10:33:43 AM PDT 24
Peak memory 197008 kb
Host smart-11470b3c-a85b-4127-b2c4-7d0f2e0970da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176216246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.176216246
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1622512712
Short name T529
Test name
Test status
Simulation time 42419254 ps
CPU time 0.84 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 193028 kb
Host smart-01a8e3c0-c308-439a-8269-488411f7ab02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622512712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1622512712
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2180418180
Short name T507
Test name
Test status
Simulation time 127994084 ps
CPU time 0.86 seconds
Started Jul 01 10:33:50 AM PDT 24
Finished Jul 01 10:33:55 AM PDT 24
Peak memory 196732 kb
Host smart-767a1f8a-4ee2-4469-8886-417dd9411832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180418180 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2180418180
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2423960634
Short name T84
Test name
Test status
Simulation time 138739351 ps
CPU time 0.58 seconds
Started Jul 01 10:33:48 AM PDT 24
Finished Jul 01 10:33:51 AM PDT 24
Peak memory 182140 kb
Host smart-809a2518-d568-4edb-b899-4675583ed4d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423960634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2423960634
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3827050485
Short name T552
Test name
Test status
Simulation time 127986382 ps
CPU time 0.56 seconds
Started Jul 01 10:33:41 AM PDT 24
Finished Jul 01 10:33:42 AM PDT 24
Peak memory 182000 kb
Host smart-714ce0aa-894c-4975-9c15-37b9b222914e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827050485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3827050485
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2934757099
Short name T536
Test name
Test status
Simulation time 22172566 ps
CPU time 0.72 seconds
Started Jul 01 10:34:02 AM PDT 24
Finished Jul 01 10:34:04 AM PDT 24
Peak memory 191096 kb
Host smart-5a0a1c85-1923-4c4e-9a24-a4b2e402b64f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934757099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2934757099
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.533680090
Short name T550
Test name
Test status
Simulation time 241970862 ps
CPU time 2.2 seconds
Started Jul 01 10:33:45 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 196952 kb
Host smart-e05e2512-e700-4a82-8692-aa50a8899352
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533680090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.533680090
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.780757565
Short name T50
Test name
Test status
Simulation time 109408291 ps
CPU time 1.1 seconds
Started Jul 01 10:33:40 AM PDT 24
Finished Jul 01 10:33:43 AM PDT 24
Peak memory 193672 kb
Host smart-27f2d444-66b6-4c9b-9785-eee988d6d174
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780757565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.780757565
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3020130787
Short name T524
Test name
Test status
Simulation time 17675761 ps
CPU time 0.62 seconds
Started Jul 01 10:33:46 AM PDT 24
Finished Jul 01 10:33:49 AM PDT 24
Peak memory 193008 kb
Host smart-6c147f50-2afb-49a8-8ade-569b5c33a060
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020130787 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3020130787
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3240521586
Short name T560
Test name
Test status
Simulation time 15811112 ps
CPU time 0.56 seconds
Started Jul 01 10:33:39 AM PDT 24
Finished Jul 01 10:33:41 AM PDT 24
Peak memory 182136 kb
Host smart-358785c9-bf9c-4b8c-8f4b-c16c2d249151
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240521586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3240521586
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3355957331
Short name T543
Test name
Test status
Simulation time 39903491 ps
CPU time 0.52 seconds
Started Jul 01 10:33:44 AM PDT 24
Finished Jul 01 10:33:46 AM PDT 24
Peak memory 181976 kb
Host smart-89414de4-947a-4e74-9346-703282b19583
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355957331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3355957331
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.194734378
Short name T525
Test name
Test status
Simulation time 81621802 ps
CPU time 0.71 seconds
Started Jul 01 10:33:49 AM PDT 24
Finished Jul 01 10:33:52 AM PDT 24
Peak memory 191112 kb
Host smart-95e5d16a-5b3e-40a2-8f0e-ccf02d2c75e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194734378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_tim
er_same_csr_outstanding.194734378
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2252232257
Short name T517
Test name
Test status
Simulation time 73692583 ps
CPU time 1.75 seconds
Started Jul 01 10:33:42 AM PDT 24
Finished Jul 01 10:33:44 AM PDT 24
Peak memory 196896 kb
Host smart-d90da0df-2d69-446d-8a03-1a000ec76c50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252232257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2252232257
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2614497052
Short name T539
Test name
Test status
Simulation time 50009664 ps
CPU time 0.8 seconds
Started Jul 01 10:33:45 AM PDT 24
Finished Jul 01 10:33:48 AM PDT 24
Peak memory 193248 kb
Host smart-a4c669e6-5a92-47fc-a726-0a938523b4ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614497052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2614497052
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3676346467
Short name T519
Test name
Test status
Simulation time 117950823 ps
CPU time 1.41 seconds
Started Jul 01 10:33:44 AM PDT 24
Finished Jul 01 10:33:46 AM PDT 24
Peak memory 197000 kb
Host smart-121ea6c0-d71b-42a1-9e12-f81476ac9d20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676346467 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3676346467
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.951908557
Short name T494
Test name
Test status
Simulation time 14146160 ps
CPU time 0.56 seconds
Started Jul 01 10:33:51 AM PDT 24
Finished Jul 01 10:33:56 AM PDT 24
Peak memory 182084 kb
Host smart-a886d910-5b6f-4e53-85ab-5e87f9b5a072
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951908557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.951908557
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.124674774
Short name T493
Test name
Test status
Simulation time 22681189 ps
CPU time 0.6 seconds
Started Jul 01 10:33:47 AM PDT 24
Finished Jul 01 10:33:50 AM PDT 24
Peak memory 182080 kb
Host smart-87724899-20a7-4fb7-b47e-0a80946c4b30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124674774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.124674774
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1610716593
Short name T95
Test name
Test status
Simulation time 18443965 ps
CPU time 0.72 seconds
Started Jul 01 10:33:54 AM PDT 24
Finished Jul 01 10:33:57 AM PDT 24
Peak memory 191112 kb
Host smart-fece5cac-49f2-41a5-b7a1-18dbd29b258c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610716593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1610716593
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2262683184
Short name T570
Test name
Test status
Simulation time 84472757 ps
CPU time 1.5 seconds
Started Jul 01 10:33:39 AM PDT 24
Finished Jul 01 10:33:41 AM PDT 24
Peak memory 196888 kb
Host smart-88369819-837b-4406-9f99-af562de7a627
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262683184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2262683184
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3366895709
Short name T562
Test name
Test status
Simulation time 80146056 ps
CPU time 1.05 seconds
Started Jul 01 10:33:32 AM PDT 24
Finished Jul 01 10:33:34 AM PDT 24
Peak memory 194664 kb
Host smart-00eca86a-74e9-4cf3-8bea-5a6c21f6144c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366895709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3366895709
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.1819525752
Short name T426
Test name
Test status
Simulation time 32141531434 ps
CPU time 47.57 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:53:30 AM PDT 24
Peak memory 183004 kb
Host smart-34be45fc-9085-40e7-8460-702025a3166e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819525752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.1819525752
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1732119609
Short name T359
Test name
Test status
Simulation time 127266903746 ps
CPU time 158.15 seconds
Started Jul 01 10:52:49 AM PDT 24
Finished Jul 01 10:55:31 AM PDT 24
Peak memory 191180 kb
Host smart-e28b0364-bfaf-4e3e-9ace-e18af59d58c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732119609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1732119609
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1974483079
Short name T453
Test name
Test status
Simulation time 808235339448 ps
CPU time 404.26 seconds
Started Jul 01 10:52:43 AM PDT 24
Finished Jul 01 10:59:31 AM PDT 24
Peak memory 183080 kb
Host smart-9c3b8766-9c74-43fe-9c49-4bcc92734847
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974483079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1974483079
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.4002217740
Short name T447
Test name
Test status
Simulation time 11495754214 ps
CPU time 2.61 seconds
Started Jul 01 10:52:44 AM PDT 24
Finished Jul 01 10:52:50 AM PDT 24
Peak memory 183076 kb
Host smart-173e4501-26c9-4440-af34-9a9d43a16b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002217740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.4002217740
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3523800729
Short name T329
Test name
Test status
Simulation time 509275216651 ps
CPU time 190.93 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:55:54 AM PDT 24
Peak memory 191276 kb
Host smart-83448884-d159-4ace-b580-36df8e422cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523800729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3523800729
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2455924132
Short name T160
Test name
Test status
Simulation time 113296868261 ps
CPU time 264.54 seconds
Started Jul 01 10:52:44 AM PDT 24
Finished Jul 01 10:57:12 AM PDT 24
Peak memory 183068 kb
Host smart-89c182e8-1de3-4580-b7f4-0a1036c71695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455924132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2455924132
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.4261939332
Short name T15
Test name
Test status
Simulation time 120957411 ps
CPU time 0.74 seconds
Started Jul 01 10:52:39 AM PDT 24
Finished Jul 01 10:52:43 AM PDT 24
Peak memory 213288 kb
Host smart-bcb98de4-c6d5-45a5-82d6-79545e9ddd83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261939332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.4261939332
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.331216777
Short name T433
Test name
Test status
Simulation time 6142489698 ps
CPU time 10.48 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:53:06 AM PDT 24
Peak memory 183096 kb
Host smart-7da614a6-e6db-480b-969f-3e13edbf12bb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331216777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.331216777
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3176969677
Short name T411
Test name
Test status
Simulation time 101503029368 ps
CPU time 151.4 seconds
Started Jul 01 10:52:51 AM PDT 24
Finished Jul 01 10:55:27 AM PDT 24
Peak memory 183132 kb
Host smart-f8108bfe-a2a2-421a-8d1d-839fb3ad2630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176969677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3176969677
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1053004712
Short name T126
Test name
Test status
Simulation time 68169196365 ps
CPU time 111.4 seconds
Started Jul 01 10:52:49 AM PDT 24
Finished Jul 01 10:54:45 AM PDT 24
Peak memory 191284 kb
Host smart-f10a4185-7e21-4e12-b055-c8033e6b0ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053004712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1053004712
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3044989989
Short name T257
Test name
Test status
Simulation time 40253371035 ps
CPU time 55.64 seconds
Started Jul 01 10:52:54 AM PDT 24
Finished Jul 01 10:53:54 AM PDT 24
Peak memory 191208 kb
Host smart-d4df33ef-0f97-47d8-93f7-bef208cd65d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044989989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3044989989
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.2780775509
Short name T366
Test name
Test status
Simulation time 177678357262 ps
CPU time 113.53 seconds
Started Jul 01 10:54:03 AM PDT 24
Finished Jul 01 10:55:57 AM PDT 24
Peak memory 183108 kb
Host smart-a721ed08-2d2b-445f-aaf4-9e03c1c07f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780775509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.2780775509
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3232509513
Short name T9
Test name
Test status
Simulation time 37451924548 ps
CPU time 35.14 seconds
Started Jul 01 10:54:09 AM PDT 24
Finished Jul 01 10:54:47 AM PDT 24
Peak memory 183112 kb
Host smart-6e26336f-8f10-49cb-8b9b-452b993a00f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232509513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3232509513
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2291206346
Short name T425
Test name
Test status
Simulation time 13791567073 ps
CPU time 18.4 seconds
Started Jul 01 10:54:08 AM PDT 24
Finished Jul 01 10:54:27 AM PDT 24
Peak memory 183076 kb
Host smart-92972e63-b5db-4db1-a16a-4ff9f6e9993e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291206346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2291206346
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.217701629
Short name T375
Test name
Test status
Simulation time 300720394469 ps
CPU time 393.45 seconds
Started Jul 01 10:54:09 AM PDT 24
Finished Jul 01 11:00:44 AM PDT 24
Peak memory 191164 kb
Host smart-004a2c3f-db8c-4d39-bcd5-07dc335fd341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217701629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.217701629
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.335177414
Short name T214
Test name
Test status
Simulation time 80627593823 ps
CPU time 117.68 seconds
Started Jul 01 10:54:10 AM PDT 24
Finished Jul 01 10:56:09 AM PDT 24
Peak memory 195000 kb
Host smart-8daa173f-3644-4db5-b2b7-29e4d2e17823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335177414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.335177414
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2067088877
Short name T361
Test name
Test status
Simulation time 18866708323 ps
CPU time 28.04 seconds
Started Jul 01 10:54:09 AM PDT 24
Finished Jul 01 10:54:39 AM PDT 24
Peak memory 193876 kb
Host smart-effbed39-b095-41c2-824d-6218493dd78c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067088877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2067088877
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2226444148
Short name T24
Test name
Test status
Simulation time 178154593016 ps
CPU time 233.02 seconds
Started Jul 01 10:52:48 AM PDT 24
Finished Jul 01 10:56:45 AM PDT 24
Peak memory 183076 kb
Host smart-9d8721f9-e68e-49a3-9792-b6fad0ac2e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226444148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2226444148
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1433316765
Short name T419
Test name
Test status
Simulation time 12137024308 ps
CPU time 22.17 seconds
Started Jul 01 10:52:49 AM PDT 24
Finished Jul 01 10:53:16 AM PDT 24
Peak memory 191300 kb
Host smart-86fb154b-b4d0-4723-bb4a-9ea2802b7b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433316765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1433316765
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.857615975
Short name T259
Test name
Test status
Simulation time 2079250955735 ps
CPU time 1119.94 seconds
Started Jul 01 10:52:52 AM PDT 24
Finished Jul 01 11:11:36 AM PDT 24
Peak memory 191280 kb
Host smart-b6cbb8e8-33ee-4fb2-851b-7bcdd7408826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857615975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
857615975
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.2902684364
Short name T333
Test name
Test status
Simulation time 378509009491 ps
CPU time 169.76 seconds
Started Jul 01 10:54:08 AM PDT 24
Finished Jul 01 10:57:00 AM PDT 24
Peak memory 191252 kb
Host smart-18e687d5-9b78-4dee-afe6-f1bd1dae19d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902684364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2902684364
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2208865165
Short name T182
Test name
Test status
Simulation time 1886004445 ps
CPU time 2.48 seconds
Started Jul 01 10:54:12 AM PDT 24
Finished Jul 01 10:54:15 AM PDT 24
Peak memory 183048 kb
Host smart-ea480e48-c12a-45a6-ace2-dc712ad8532d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208865165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2208865165
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1745844972
Short name T276
Test name
Test status
Simulation time 100991934653 ps
CPU time 84.47 seconds
Started Jul 01 10:54:12 AM PDT 24
Finished Jul 01 10:55:38 AM PDT 24
Peak memory 183092 kb
Host smart-b4a44090-781c-4931-a45e-6c89f750e397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745844972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1745844972
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2843035531
Short name T56
Test name
Test status
Simulation time 29047810813 ps
CPU time 64.5 seconds
Started Jul 01 10:54:16 AM PDT 24
Finished Jul 01 10:55:21 AM PDT 24
Peak memory 183060 kb
Host smart-48dc04c4-7a8b-452f-8dc8-624618d8a3f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843035531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2843035531
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2701400628
Short name T125
Test name
Test status
Simulation time 68403107185 ps
CPU time 135.04 seconds
Started Jul 01 10:54:18 AM PDT 24
Finished Jul 01 10:56:33 AM PDT 24
Peak memory 191308 kb
Host smart-9f9dd720-ae1b-43fa-970b-902a7de70232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701400628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2701400628
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.4210405779
Short name T143
Test name
Test status
Simulation time 68122837765 ps
CPU time 92.04 seconds
Started Jul 01 10:54:15 AM PDT 24
Finished Jul 01 10:55:48 AM PDT 24
Peak memory 191312 kb
Host smart-2d44e1ac-4f8d-4d45-8a2e-5eec07ebbf91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210405779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.4210405779
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1988611094
Short name T314
Test name
Test status
Simulation time 240230622766 ps
CPU time 208.95 seconds
Started Jul 01 10:54:17 AM PDT 24
Finished Jul 01 10:57:47 AM PDT 24
Peak memory 191264 kb
Host smart-2d63e9a5-39da-4401-bd07-28402904a9fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988611094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1988611094
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.642367894
Short name T417
Test name
Test status
Simulation time 252120665736 ps
CPU time 300.37 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:57:56 AM PDT 24
Peak memory 183076 kb
Host smart-65653076-f526-49a3-a3eb-47e47a21ff79
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642367894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.642367894
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.350181697
Short name T398
Test name
Test status
Simulation time 91082864966 ps
CPU time 116.48 seconds
Started Jul 01 10:53:00 AM PDT 24
Finished Jul 01 10:54:59 AM PDT 24
Peak memory 183060 kb
Host smart-4b8379ab-5eaf-4033-ace8-0238f11f888d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350181697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.350181697
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2023008942
Short name T340
Test name
Test status
Simulation time 127184757311 ps
CPU time 67.6 seconds
Started Jul 01 10:52:52 AM PDT 24
Finished Jul 01 10:54:05 AM PDT 24
Peak memory 183084 kb
Host smart-fb79112c-b143-45cd-8432-338687b24c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023008942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2023008942
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2311581938
Short name T334
Test name
Test status
Simulation time 82703331670 ps
CPU time 379.64 seconds
Started Jul 01 10:52:51 AM PDT 24
Finished Jul 01 10:59:16 AM PDT 24
Peak memory 191284 kb
Host smart-944064bd-4882-49e5-81a1-bdf02789b495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311581938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2311581938
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.1280018287
Short name T40
Test name
Test status
Simulation time 16901961954 ps
CPU time 123.05 seconds
Started Jul 01 10:52:54 AM PDT 24
Finished Jul 01 10:55:01 AM PDT 24
Peak memory 196936 kb
Host smart-f86925db-4943-4db0-b92b-e25c1506c92b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280018287 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.1280018287
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1564993459
Short name T190
Test name
Test status
Simulation time 286854977539 ps
CPU time 385.6 seconds
Started Jul 01 10:54:17 AM PDT 24
Finished Jul 01 11:00:43 AM PDT 24
Peak memory 191244 kb
Host smart-c27f3adf-2a22-452e-b5f1-6ead0f8b75fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564993459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1564993459
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3104784975
Short name T171
Test name
Test status
Simulation time 175393557808 ps
CPU time 147.04 seconds
Started Jul 01 10:54:17 AM PDT 24
Finished Jul 01 10:56:44 AM PDT 24
Peak memory 191304 kb
Host smart-2c5bb90f-db3e-4612-a9c9-855d624b6aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104784975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3104784975
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1192672730
Short name T103
Test name
Test status
Simulation time 601206436966 ps
CPU time 190.21 seconds
Started Jul 01 10:54:20 AM PDT 24
Finished Jul 01 10:57:31 AM PDT 24
Peak memory 191244 kb
Host smart-50c175e0-b29f-4198-b6d3-dc1d302e2e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192672730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1192672730
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1887750327
Short name T218
Test name
Test status
Simulation time 806519911497 ps
CPU time 534.44 seconds
Started Jul 01 10:52:52 AM PDT 24
Finished Jul 01 11:01:51 AM PDT 24
Peak memory 183080 kb
Host smart-5c66ffcc-1331-43eb-805d-71d23617961c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887750327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1887750327
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1259395429
Short name T436
Test name
Test status
Simulation time 51141911517 ps
CPU time 76.37 seconds
Started Jul 01 10:53:09 AM PDT 24
Finished Jul 01 10:54:28 AM PDT 24
Peak memory 183116 kb
Host smart-58ff4746-2a27-47b9-829f-80d0b11d1f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259395429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1259395429
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.274069283
Short name T111
Test name
Test status
Simulation time 156191220967 ps
CPU time 256.83 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:57:12 AM PDT 24
Peak memory 191240 kb
Host smart-b171252f-7629-46f0-985b-2a555e8311bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274069283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.274069283
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2049287623
Short name T161
Test name
Test status
Simulation time 58151238529 ps
CPU time 354.9 seconds
Started Jul 01 10:52:49 AM PDT 24
Finished Jul 01 10:58:49 AM PDT 24
Peak memory 183116 kb
Host smart-853bebe6-a69c-4c2a-8d2d-224c874fab89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049287623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2049287623
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2341816145
Short name T55
Test name
Test status
Simulation time 1653269432962 ps
CPU time 776.84 seconds
Started Jul 01 10:52:51 AM PDT 24
Finished Jul 01 11:05:53 AM PDT 24
Peak memory 191308 kb
Host smart-fa83282c-2aa3-4018-978b-b791c2033a08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341816145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2341816145
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.2633975530
Short name T140
Test name
Test status
Simulation time 297901487976 ps
CPU time 203.34 seconds
Started Jul 01 10:54:26 AM PDT 24
Finished Jul 01 10:57:50 AM PDT 24
Peak memory 192620 kb
Host smart-59ef7c4c-6d4e-4046-8314-e5036b1d5ebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633975530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2633975530
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3454317867
Short name T102
Test name
Test status
Simulation time 615687588818 ps
CPU time 491.91 seconds
Started Jul 01 10:54:25 AM PDT 24
Finished Jul 01 11:02:38 AM PDT 24
Peak memory 191284 kb
Host smart-fec754c8-ee0e-4b79-a6eb-7962ae5f4ad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454317867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3454317867
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2854406765
Short name T313
Test name
Test status
Simulation time 228227020844 ps
CPU time 200.8 seconds
Started Jul 01 10:54:27 AM PDT 24
Finished Jul 01 10:57:48 AM PDT 24
Peak memory 191308 kb
Host smart-677f7f34-23b9-4f4d-8aa9-d7ee6781499e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854406765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2854406765
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2070445470
Short name T219
Test name
Test status
Simulation time 77390046632 ps
CPU time 121.69 seconds
Started Jul 01 10:54:25 AM PDT 24
Finished Jul 01 10:56:27 AM PDT 24
Peak memory 191292 kb
Host smart-ad33e368-dc1a-4b4b-b109-806af05fee3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070445470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2070445470
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1526634553
Short name T374
Test name
Test status
Simulation time 65074056824 ps
CPU time 182.59 seconds
Started Jul 01 10:54:26 AM PDT 24
Finished Jul 01 10:57:29 AM PDT 24
Peak memory 191308 kb
Host smart-785f0ca0-cb34-4fd9-a10f-751deca8f352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526634553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1526634553
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3529510749
Short name T175
Test name
Test status
Simulation time 285031467409 ps
CPU time 522.83 seconds
Started Jul 01 10:54:30 AM PDT 24
Finished Jul 01 11:03:14 AM PDT 24
Peak memory 191248 kb
Host smart-7ad6ee2f-9d42-4a5c-a011-32adea2123d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529510749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3529510749
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2264131396
Short name T262
Test name
Test status
Simulation time 33954767487 ps
CPU time 157.86 seconds
Started Jul 01 10:54:31 AM PDT 24
Finished Jul 01 10:57:10 AM PDT 24
Peak memory 182980 kb
Host smart-60814b3d-b90f-4c51-8327-8ee013a63f9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264131396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2264131396
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3311406620
Short name T337
Test name
Test status
Simulation time 49928518532 ps
CPU time 81.55 seconds
Started Jul 01 10:54:28 AM PDT 24
Finished Jul 01 10:55:50 AM PDT 24
Peak memory 194484 kb
Host smart-4fb44093-7d12-436c-a98b-92ca4f9be10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311406620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3311406620
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.493805989
Short name T279
Test name
Test status
Simulation time 67796128360 ps
CPU time 112.65 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:54:47 AM PDT 24
Peak memory 183056 kb
Host smart-73990aa8-3ab2-4b54-9b56-5a922c692759
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493805989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.493805989
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2652000961
Short name T379
Test name
Test status
Simulation time 388972574282 ps
CPU time 143.69 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:55:19 AM PDT 24
Peak memory 183080 kb
Host smart-c34bb917-dd5e-4bc3-a636-cfd6ab5fb9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652000961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2652000961
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.2291967000
Short name T51
Test name
Test status
Simulation time 59075539377 ps
CPU time 85.59 seconds
Started Jul 01 10:52:52 AM PDT 24
Finished Jul 01 10:54:23 AM PDT 24
Peak memory 191284 kb
Host smart-17ad6ac8-d18d-491b-9a9e-cbda235cb08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291967000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2291967000
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2557779973
Short name T343
Test name
Test status
Simulation time 225741581312 ps
CPU time 332.63 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:58:28 AM PDT 24
Peak memory 191276 kb
Host smart-16f83486-6fc7-4b83-9954-58ddf34bed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557779973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2557779973
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.112817950
Short name T444
Test name
Test status
Simulation time 262852410698 ps
CPU time 179.86 seconds
Started Jul 01 10:52:56 AM PDT 24
Finished Jul 01 10:56:00 AM PDT 24
Peak memory 183100 kb
Host smart-424641b8-ad77-4586-b2b4-c2096e4078a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112817950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
112817950
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.1508052746
Short name T2
Test name
Test status
Simulation time 57413773767 ps
CPU time 144.99 seconds
Started Jul 01 10:54:31 AM PDT 24
Finished Jul 01 10:56:56 AM PDT 24
Peak memory 191312 kb
Host smart-bf924574-8cdb-4c52-a439-06d28d633d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508052746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1508052746
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2758161240
Short name T105
Test name
Test status
Simulation time 183323365719 ps
CPU time 928.2 seconds
Started Jul 01 10:54:29 AM PDT 24
Finished Jul 01 11:09:58 AM PDT 24
Peak memory 191324 kb
Host smart-7a9a6b99-2ddb-461d-9578-a2158616a478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758161240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2758161240
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3408451494
Short name T241
Test name
Test status
Simulation time 62151156849 ps
CPU time 239.42 seconds
Started Jul 01 10:54:35 AM PDT 24
Finished Jul 01 10:58:35 AM PDT 24
Peak memory 191192 kb
Host smart-99f370a9-3c95-4ef2-8698-9d47a49d2c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408451494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3408451494
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3189906439
Short name T231
Test name
Test status
Simulation time 237059518528 ps
CPU time 442.7 seconds
Started Jul 01 10:54:37 AM PDT 24
Finished Jul 01 11:02:00 AM PDT 24
Peak memory 191204 kb
Host smart-16cc897c-732c-43bc-bc5d-c03b7864a472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189906439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3189906439
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.875457070
Short name T239
Test name
Test status
Simulation time 313409786007 ps
CPU time 692.22 seconds
Started Jul 01 10:54:33 AM PDT 24
Finished Jul 01 11:06:06 AM PDT 24
Peak memory 194984 kb
Host smart-35cbf859-bc86-456d-8e8f-600904f63d2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875457070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.875457070
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2460958471
Short name T112
Test name
Test status
Simulation time 285205832607 ps
CPU time 170.51 seconds
Started Jul 01 10:54:34 AM PDT 24
Finished Jul 01 10:57:26 AM PDT 24
Peak memory 191172 kb
Host smart-c7cd4371-d6fb-4fff-8023-8c90c0e1af8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460958471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2460958471
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2140018222
Short name T427
Test name
Test status
Simulation time 216782580977 ps
CPU time 322.2 seconds
Started Jul 01 10:52:51 AM PDT 24
Finished Jul 01 10:58:18 AM PDT 24
Peak memory 183112 kb
Host smart-898790a0-5fe5-415c-8d69-7d4f94c296d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140018222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2140018222
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3037767098
Short name T53
Test name
Test status
Simulation time 152052925713 ps
CPU time 220.67 seconds
Started Jul 01 10:52:54 AM PDT 24
Finished Jul 01 10:56:39 AM PDT 24
Peak memory 182360 kb
Host smart-69ccf0b1-3eb9-4aee-9d47-6a5db9d9caed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037767098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3037767098
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3160432826
Short name T395
Test name
Test status
Simulation time 444946196 ps
CPU time 2.04 seconds
Started Jul 01 10:52:51 AM PDT 24
Finished Jul 01 10:52:58 AM PDT 24
Peak memory 183068 kb
Host smart-2c2fe6ad-3623-4020-a1d3-5d44e8b7768d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160432826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3160432826
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.461611392
Short name T327
Test name
Test status
Simulation time 30922452274 ps
CPU time 1067.12 seconds
Started Jul 01 10:54:33 AM PDT 24
Finished Jul 01 11:12:21 AM PDT 24
Peak memory 183084 kb
Host smart-e855d500-71d1-4dab-ab29-df5ddee4e224
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461611392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.461611392
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.843182872
Short name T278
Test name
Test status
Simulation time 333350496604 ps
CPU time 627.4 seconds
Started Jul 01 10:54:39 AM PDT 24
Finished Jul 01 11:05:07 AM PDT 24
Peak memory 191376 kb
Host smart-769241dd-d160-4409-b6f7-c8fcff8f6ca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843182872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.843182872
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.305104231
Short name T159
Test name
Test status
Simulation time 45357048197 ps
CPU time 55.05 seconds
Started Jul 01 10:54:37 AM PDT 24
Finished Jul 01 10:55:33 AM PDT 24
Peak memory 191276 kb
Host smart-238b9d6c-a468-4251-8a9e-c05d9aff8876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305104231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.305104231
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1223378559
Short name T68
Test name
Test status
Simulation time 276962720046 ps
CPU time 107.34 seconds
Started Jul 01 10:54:39 AM PDT 24
Finished Jul 01 10:56:26 AM PDT 24
Peak memory 193256 kb
Host smart-01dfe892-a119-45f7-8947-17128c73cc8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223378559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1223378559
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.2081800134
Short name T238
Test name
Test status
Simulation time 1724706989090 ps
CPU time 3269.8 seconds
Started Jul 01 10:54:43 AM PDT 24
Finished Jul 01 11:49:14 AM PDT 24
Peak memory 191304 kb
Host smart-dbc4c00f-7dc9-4e74-b7d8-0091a3918589
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081800134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.2081800134
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3641946013
Short name T406
Test name
Test status
Simulation time 10498197582 ps
CPU time 14.58 seconds
Started Jul 01 10:54:42 AM PDT 24
Finished Jul 01 10:54:57 AM PDT 24
Peak memory 183124 kb
Host smart-f6818935-db3c-47b0-886a-62e44a7f2a2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641946013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3641946013
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.239642820
Short name T385
Test name
Test status
Simulation time 19087258028 ps
CPU time 29.43 seconds
Started Jul 01 10:52:55 AM PDT 24
Finished Jul 01 10:53:29 AM PDT 24
Peak memory 183128 kb
Host smart-946b353e-258b-4de6-85be-e5210ff10b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239642820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.239642820
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2952552913
Short name T394
Test name
Test status
Simulation time 383250581513 ps
CPU time 331.86 seconds
Started Jul 01 10:52:54 AM PDT 24
Finished Jul 01 10:58:30 AM PDT 24
Peak memory 191292 kb
Host smart-1b46454d-a506-418d-b3ff-e9fe19ccc038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952552913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2952552913
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.1474792610
Short name T96
Test name
Test status
Simulation time 51280741955 ps
CPU time 368.73 seconds
Started Jul 01 10:53:21 AM PDT 24
Finished Jul 01 10:59:33 AM PDT 24
Peak memory 205944 kb
Host smart-47c5bf17-9b97-4126-9b2c-65c3a1f57358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474792610 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.1474792610
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.3976724542
Short name T158
Test name
Test status
Simulation time 626849154381 ps
CPU time 140.76 seconds
Started Jul 01 10:54:43 AM PDT 24
Finished Jul 01 10:57:04 AM PDT 24
Peak memory 191332 kb
Host smart-4302a1da-bd82-4d70-b9e5-f0cce662f4be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976724542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3976724542
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3728195383
Short name T74
Test name
Test status
Simulation time 224194765203 ps
CPU time 198.8 seconds
Started Jul 01 10:54:47 AM PDT 24
Finished Jul 01 10:58:06 AM PDT 24
Peak memory 191304 kb
Host smart-939edc0b-4c35-4c3a-b90a-3b261141dbd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728195383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3728195383
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.716456897
Short name T252
Test name
Test status
Simulation time 40589912780 ps
CPU time 45.82 seconds
Started Jul 01 10:54:48 AM PDT 24
Finished Jul 01 10:55:34 AM PDT 24
Peak memory 182896 kb
Host smart-01377ad6-b1f6-47c8-97cf-70f3f8299601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716456897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.716456897
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2055623800
Short name T19
Test name
Test status
Simulation time 101607577482 ps
CPU time 164.78 seconds
Started Jul 01 10:54:48 AM PDT 24
Finished Jul 01 10:57:33 AM PDT 24
Peak memory 191208 kb
Host smart-0b850b19-df2a-452f-bcdf-c82ede0dc94c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055623800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2055623800
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1861097143
Short name T130
Test name
Test status
Simulation time 70402453446 ps
CPU time 99.57 seconds
Started Jul 01 10:54:54 AM PDT 24
Finished Jul 01 10:56:34 AM PDT 24
Peak memory 191420 kb
Host smart-975ecd44-6426-4611-99c9-8bb7e97041ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861097143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1861097143
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2906003969
Short name T142
Test name
Test status
Simulation time 167000389260 ps
CPU time 137.33 seconds
Started Jul 01 10:54:46 AM PDT 24
Finished Jul 01 10:57:04 AM PDT 24
Peak memory 191284 kb
Host smart-2857d60e-f0af-49c3-a9b4-0ac939c0d4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906003969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2906003969
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1664416644
Short name T206
Test name
Test status
Simulation time 175917268499 ps
CPU time 367.53 seconds
Started Jul 01 10:54:47 AM PDT 24
Finished Jul 01 11:00:55 AM PDT 24
Peak memory 194040 kb
Host smart-d9f9f487-8ffd-47d6-b1ff-f62292435b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664416644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1664416644
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1378395800
Short name T203
Test name
Test status
Simulation time 1143180574424 ps
CPU time 633.55 seconds
Started Jul 01 10:52:56 AM PDT 24
Finished Jul 01 11:03:34 AM PDT 24
Peak memory 183080 kb
Host smart-2dd80269-67f2-4727-b8f2-f1f7d8cfb6bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378395800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1378395800
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.497718683
Short name T73
Test name
Test status
Simulation time 34927933517 ps
CPU time 51.72 seconds
Started Jul 01 10:53:23 AM PDT 24
Finished Jul 01 10:54:17 AM PDT 24
Peak memory 183224 kb
Host smart-549968fc-362c-4255-97c2-21b9b8c6c47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497718683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.497718683
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.2272479416
Short name T43
Test name
Test status
Simulation time 62770003012 ps
CPU time 105.62 seconds
Started Jul 01 10:52:55 AM PDT 24
Finished Jul 01 10:54:45 AM PDT 24
Peak memory 191532 kb
Host smart-38d899f7-77a3-456a-940d-073261b67903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272479416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2272479416
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.2804029074
Short name T195
Test name
Test status
Simulation time 113841471494 ps
CPU time 180.6 seconds
Started Jul 01 10:54:53 AM PDT 24
Finished Jul 01 10:57:54 AM PDT 24
Peak memory 191312 kb
Host smart-dc4ae45f-3e8e-4f43-a788-70e3671d2ff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804029074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2804029074
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.883215925
Short name T309
Test name
Test status
Simulation time 300906433013 ps
CPU time 85.56 seconds
Started Jul 01 10:54:53 AM PDT 24
Finished Jul 01 10:56:19 AM PDT 24
Peak memory 183092 kb
Host smart-c939ca4b-55c9-4608-9299-0701f57d6d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883215925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.883215925
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2655525665
Short name T264
Test name
Test status
Simulation time 232243954639 ps
CPU time 268.56 seconds
Started Jul 01 10:54:56 AM PDT 24
Finished Jul 01 10:59:25 AM PDT 24
Peak memory 191232 kb
Host smart-1eb93aeb-d627-4062-b924-4ba9bb27be1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655525665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2655525665
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.4122155876
Short name T172
Test name
Test status
Simulation time 207760793174 ps
CPU time 86.27 seconds
Started Jul 01 10:54:55 AM PDT 24
Finished Jul 01 10:56:22 AM PDT 24
Peak memory 193568 kb
Host smart-0d5d00ec-b90e-419b-8979-e444f89a2431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122155876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4122155876
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2763117192
Short name T331
Test name
Test status
Simulation time 116082250941 ps
CPU time 430.19 seconds
Started Jul 01 10:54:56 AM PDT 24
Finished Jul 01 11:02:06 AM PDT 24
Peak memory 191240 kb
Host smart-712e17f8-74dd-4dbd-b962-8214335e6c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763117192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2763117192
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.244805351
Short name T119
Test name
Test status
Simulation time 290196843768 ps
CPU time 171.84 seconds
Started Jul 01 10:54:55 AM PDT 24
Finished Jul 01 10:57:47 AM PDT 24
Peak memory 191292 kb
Host smart-25bda46b-b5de-4c15-96da-c0471af58a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244805351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.244805351
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.687239607
Short name T367
Test name
Test status
Simulation time 381500881698 ps
CPU time 110.77 seconds
Started Jul 01 10:53:02 AM PDT 24
Finished Jul 01 10:54:56 AM PDT 24
Peak memory 183084 kb
Host smart-1e082973-e993-4b4b-a56d-aa678ba663df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687239607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.687239607
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1996062902
Short name T387
Test name
Test status
Simulation time 848355893728 ps
CPU time 140.52 seconds
Started Jul 01 10:52:53 AM PDT 24
Finished Jul 01 10:55:18 AM PDT 24
Peak memory 183144 kb
Host smart-c7a56eb9-8b34-4c2b-85dd-1f2811961312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996062902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1996062902
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.4197374674
Short name T39
Test name
Test status
Simulation time 92738935910 ps
CPU time 1071.18 seconds
Started Jul 01 10:53:07 AM PDT 24
Finished Jul 01 11:11:00 AM PDT 24
Peak memory 210716 kb
Host smart-7a80266c-b148-4924-a39a-3068fc201ebd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197374674 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.4197374674
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3503379580
Short name T251
Test name
Test status
Simulation time 424010717811 ps
CPU time 356.45 seconds
Started Jul 01 10:54:58 AM PDT 24
Finished Jul 01 11:00:55 AM PDT 24
Peak memory 191268 kb
Host smart-416abb7e-02bd-4d64-b0e7-01ca45e90c5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503379580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3503379580
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.686018774
Short name T150
Test name
Test status
Simulation time 9181477137 ps
CPU time 34.67 seconds
Started Jul 01 10:55:01 AM PDT 24
Finished Jul 01 10:55:37 AM PDT 24
Peak memory 191284 kb
Host smart-ce502712-9b48-4a81-aaac-f6288e9317e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686018774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.686018774
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.750188828
Short name T135
Test name
Test status
Simulation time 74183156345 ps
CPU time 1800.41 seconds
Started Jul 01 10:55:03 AM PDT 24
Finished Jul 01 11:25:04 AM PDT 24
Peak memory 191272 kb
Host smart-6d39b379-a16e-4416-9769-96bd3302d5d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750188828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.750188828
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3997483992
Short name T291
Test name
Test status
Simulation time 710760930701 ps
CPU time 645.2 seconds
Started Jul 01 10:55:08 AM PDT 24
Finished Jul 01 11:05:53 AM PDT 24
Peak memory 191420 kb
Host smart-b8e6bbe6-6fcb-47f2-bce2-a92c71f85548
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997483992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3997483992
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2382419868
Short name T180
Test name
Test status
Simulation time 2251102144667 ps
CPU time 797.29 seconds
Started Jul 01 10:55:01 AM PDT 24
Finished Jul 01 11:08:20 AM PDT 24
Peak memory 191288 kb
Host smart-0f1ce7f8-1603-462b-a69d-0b0b7d4ace1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382419868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2382419868
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3602185802
Short name T352
Test name
Test status
Simulation time 111758983614 ps
CPU time 158.34 seconds
Started Jul 01 10:52:57 AM PDT 24
Finished Jul 01 10:55:39 AM PDT 24
Peak memory 183072 kb
Host smart-63d9ab03-2fab-4b03-969e-e8f6a96c4d7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602185802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3602185802
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1669568273
Short name T386
Test name
Test status
Simulation time 97848614607 ps
CPU time 94.89 seconds
Started Jul 01 10:53:13 AM PDT 24
Finished Jul 01 10:54:50 AM PDT 24
Peak memory 183112 kb
Host smart-89d7888c-b7fc-45d6-9081-bfd382b6769d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669568273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1669568273
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1172507956
Short name T205
Test name
Test status
Simulation time 274430426062 ps
CPU time 539.3 seconds
Started Jul 01 10:52:55 AM PDT 24
Finished Jul 01 11:01:59 AM PDT 24
Peak memory 191296 kb
Host smart-89679e7a-3052-451c-9fd9-0360c930d015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172507956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1172507956
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1397883633
Short name T363
Test name
Test status
Simulation time 15476010686 ps
CPU time 48.47 seconds
Started Jul 01 10:52:56 AM PDT 24
Finished Jul 01 10:53:48 AM PDT 24
Peak memory 191304 kb
Host smart-9cd37d4a-f4ee-43f3-9ae6-dc3ff1ce60d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397883633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1397883633
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3833720298
Short name T409
Test name
Test status
Simulation time 560140689923 ps
CPU time 414.57 seconds
Started Jul 01 10:52:59 AM PDT 24
Finished Jul 01 10:59:57 AM PDT 24
Peak memory 191296 kb
Host smart-0e74ff15-4a80-4ef5-ad1d-eeb47fde8d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833720298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3833720298
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.3099032237
Short name T227
Test name
Test status
Simulation time 273858308551 ps
CPU time 154.59 seconds
Started Jul 01 10:55:06 AM PDT 24
Finished Jul 01 10:57:41 AM PDT 24
Peak memory 191284 kb
Host smart-f8a18061-71c7-4f5e-9a2d-7a4083294a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099032237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3099032237
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.432120025
Short name T117
Test name
Test status
Simulation time 104532554321 ps
CPU time 362.4 seconds
Started Jul 01 10:55:06 AM PDT 24
Finished Jul 01 11:01:09 AM PDT 24
Peak memory 191292 kb
Host smart-4e3c7ff7-44bb-4cd6-88e4-fb1e6804cc91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432120025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.432120025
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3333446952
Short name T104
Test name
Test status
Simulation time 288625561632 ps
CPU time 354.74 seconds
Started Jul 01 10:55:07 AM PDT 24
Finished Jul 01 11:01:03 AM PDT 24
Peak memory 191268 kb
Host smart-119257ce-70ee-41fa-8902-f4f9a21ff46e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333446952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3333446952
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1039911937
Short name T138
Test name
Test status
Simulation time 444269547592 ps
CPU time 408.62 seconds
Started Jul 01 10:55:06 AM PDT 24
Finished Jul 01 11:01:55 AM PDT 24
Peak memory 191296 kb
Host smart-56e7eabd-2ae1-4861-b65e-19da75086d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039911937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1039911937
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.343342419
Short name T193
Test name
Test status
Simulation time 625159783117 ps
CPU time 402.31 seconds
Started Jul 01 10:55:07 AM PDT 24
Finished Jul 01 11:01:50 AM PDT 24
Peak memory 193668 kb
Host smart-c466e61d-1340-4855-8339-8d3a3b22d28b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343342419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.343342419
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1326538393
Short name T141
Test name
Test status
Simulation time 80494251831 ps
CPU time 124.15 seconds
Started Jul 01 10:55:10 AM PDT 24
Finished Jul 01 10:57:14 AM PDT 24
Peak memory 191292 kb
Host smart-e18fde98-1755-4f1f-9e5e-151ab4aa8ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326538393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1326538393
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.931665187
Short name T202
Test name
Test status
Simulation time 519957483480 ps
CPU time 717.46 seconds
Started Jul 01 10:55:11 AM PDT 24
Finished Jul 01 11:07:09 AM PDT 24
Peak memory 191244 kb
Host smart-34402fd8-d50e-4e80-8293-7ad710efaefd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931665187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.931665187
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.529459086
Short name T287
Test name
Test status
Simulation time 1639790093978 ps
CPU time 643.09 seconds
Started Jul 01 10:55:15 AM PDT 24
Finished Jul 01 11:05:59 AM PDT 24
Peak memory 191304 kb
Host smart-52031805-1d79-4bd0-aa38-d469d0e3bbd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529459086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.529459086
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.480153362
Short name T267
Test name
Test status
Simulation time 61724017407 ps
CPU time 116.66 seconds
Started Jul 01 10:55:16 AM PDT 24
Finished Jul 01 10:57:13 AM PDT 24
Peak memory 191304 kb
Host smart-ee65a1ed-b8c1-49b4-8850-77ce633f2730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480153362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.480153362
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3522244816
Short name T445
Test name
Test status
Simulation time 16672492586 ps
CPU time 16.64 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:53:12 AM PDT 24
Peak memory 183112 kb
Host smart-e42e5111-1ec7-48d2-bc44-6edb1b69fc72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522244816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3522244816
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3807720477
Short name T404
Test name
Test status
Simulation time 536394614584 ps
CPU time 185.85 seconds
Started Jul 01 10:52:47 AM PDT 24
Finished Jul 01 10:55:56 AM PDT 24
Peak memory 183108 kb
Host smart-8e0d9f76-6683-4a3e-b3b9-3b8c55e7cc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807720477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3807720477
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.4121479711
Short name T440
Test name
Test status
Simulation time 25389468773 ps
CPU time 23.08 seconds
Started Jul 01 10:52:42 AM PDT 24
Finished Jul 01 10:53:08 AM PDT 24
Peak memory 182960 kb
Host smart-992c61b3-99db-4134-81f9-b41de5214d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121479711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.4121479711
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2641662163
Short name T354
Test name
Test status
Simulation time 24637183173 ps
CPU time 35.4 seconds
Started Jul 01 10:52:42 AM PDT 24
Finished Jul 01 10:53:21 AM PDT 24
Peak memory 191276 kb
Host smart-611a225a-40ec-42a7-9ec6-6a39413e2467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641662163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2641662163
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3615383333
Short name T13
Test name
Test status
Simulation time 80694904 ps
CPU time 0.9 seconds
Started Jul 01 10:52:41 AM PDT 24
Finished Jul 01 10:52:45 AM PDT 24
Peak memory 214540 kb
Host smart-482ba18b-5f80-4025-b805-c7c553dd0152
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615383333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3615383333
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2717388525
Short name T380
Test name
Test status
Simulation time 494269159156 ps
CPU time 208.89 seconds
Started Jul 01 10:53:00 AM PDT 24
Finished Jul 01 10:56:33 AM PDT 24
Peak memory 183080 kb
Host smart-861d26a1-9d5b-469a-86f6-0a1a2064d458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717388525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2717388525
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3107806848
Short name T294
Test name
Test status
Simulation time 86236684512 ps
CPU time 152.88 seconds
Started Jul 01 10:53:14 AM PDT 24
Finished Jul 01 10:55:50 AM PDT 24
Peak memory 193604 kb
Host smart-11621472-f5ff-4d2f-8002-1875f2a81c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107806848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3107806848
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.471004786
Short name T330
Test name
Test status
Simulation time 177941083396 ps
CPU time 963.93 seconds
Started Jul 01 10:53:10 AM PDT 24
Finished Jul 01 11:09:17 AM PDT 24
Peak memory 195828 kb
Host smart-60b0b006-3873-4a9d-9f53-01775c5497e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471004786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
471004786
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2704814230
Short name T269
Test name
Test status
Simulation time 12663254713 ps
CPU time 6.94 seconds
Started Jul 01 10:52:59 AM PDT 24
Finished Jul 01 10:53:09 AM PDT 24
Peak memory 183152 kb
Host smart-863cdc3c-1d16-4a62-8463-a50ff9593082
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704814230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2704814230
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2147654679
Short name T377
Test name
Test status
Simulation time 146952709389 ps
CPU time 57.2 seconds
Started Jul 01 10:53:14 AM PDT 24
Finished Jul 01 10:54:14 AM PDT 24
Peak memory 183244 kb
Host smart-59c1839f-c885-436b-87e2-4d4a6d02289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147654679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2147654679
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.721307059
Short name T222
Test name
Test status
Simulation time 154302779120 ps
CPU time 140.78 seconds
Started Jul 01 10:53:08 AM PDT 24
Finished Jul 01 10:55:30 AM PDT 24
Peak memory 191236 kb
Host smart-a40cfe0c-2dcb-4c9d-8657-847648812a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721307059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.721307059
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3241026241
Short name T420
Test name
Test status
Simulation time 74052477 ps
CPU time 0.86 seconds
Started Jul 01 10:53:21 AM PDT 24
Finished Jul 01 10:53:25 AM PDT 24
Peak memory 191840 kb
Host smart-975b96f4-1f8f-41f8-89e4-a07f90bb30d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241026241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3241026241
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.1435801257
Short name T97
Test name
Test status
Simulation time 54708697920 ps
CPU time 487.95 seconds
Started Jul 01 10:53:12 AM PDT 24
Finished Jul 01 11:01:23 AM PDT 24
Peak memory 197740 kb
Host smart-9b9295f8-d681-4954-a24c-833a685a452e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435801257 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.1435801257
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2397299514
Short name T302
Test name
Test status
Simulation time 16117729049 ps
CPU time 8.39 seconds
Started Jul 01 10:53:01 AM PDT 24
Finished Jul 01 10:53:12 AM PDT 24
Peak memory 183052 kb
Host smart-fac75318-de56-4189-8803-7a1523923ba2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397299514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2397299514
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.4051137026
Short name T392
Test name
Test status
Simulation time 225519735725 ps
CPU time 145.81 seconds
Started Jul 01 10:53:02 AM PDT 24
Finished Jul 01 10:55:31 AM PDT 24
Peak memory 183100 kb
Host smart-f842f02e-65f1-4fcf-9b30-896cb320f2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051137026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.4051137026
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.982009322
Short name T410
Test name
Test status
Simulation time 30775423140 ps
CPU time 21.51 seconds
Started Jul 01 10:52:59 AM PDT 24
Finished Jul 01 10:53:24 AM PDT 24
Peak memory 182972 kb
Host smart-ed56e4e2-e2f4-4c30-8d7b-f732bd95b448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982009322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.982009322
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.816835456
Short name T371
Test name
Test status
Simulation time 10491518305 ps
CPU time 9.82 seconds
Started Jul 01 10:53:04 AM PDT 24
Finished Jul 01 10:53:17 AM PDT 24
Peak memory 183080 kb
Host smart-243ea64d-84b8-4fce-a728-f73aa9be3fce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816835456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.816835456
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.4101675723
Short name T4
Test name
Test status
Simulation time 13253547649 ps
CPU time 21.01 seconds
Started Jul 01 10:53:20 AM PDT 24
Finished Jul 01 10:53:45 AM PDT 24
Peak memory 183016 kb
Host smart-eea8b7cf-d864-4a12-9362-20e6f24ddedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101675723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.4101675723
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2544463011
Short name T396
Test name
Test status
Simulation time 507131012 ps
CPU time 0.91 seconds
Started Jul 01 10:53:05 AM PDT 24
Finished Jul 01 10:53:09 AM PDT 24
Peak memory 182916 kb
Host smart-d9375944-6d89-49a3-ad76-b9e1ae1e6228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544463011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2544463011
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1508965891
Short name T318
Test name
Test status
Simulation time 1050680195375 ps
CPU time 628.45 seconds
Started Jul 01 10:53:04 AM PDT 24
Finished Jul 01 11:03:36 AM PDT 24
Peak memory 191276 kb
Host smart-3169a778-b31d-4ed7-b2db-fe24b1322831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508965891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1508965891
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.4062936243
Short name T35
Test name
Test status
Simulation time 116599460461 ps
CPU time 436.87 seconds
Started Jul 01 10:53:15 AM PDT 24
Finished Jul 01 11:00:35 AM PDT 24
Peak memory 205960 kb
Host smart-ba055775-7a75-4f03-9c73-140365cf36d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062936243 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.4062936243
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2201303582
Short name T237
Test name
Test status
Simulation time 313593455766 ps
CPU time 522.17 seconds
Started Jul 01 10:53:04 AM PDT 24
Finished Jul 01 11:01:49 AM PDT 24
Peak memory 183108 kb
Host smart-bf49512c-a870-4d69-ae80-ca37c6ad5e2c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201303582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2201303582
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3704250270
Short name T381
Test name
Test status
Simulation time 406774746781 ps
CPU time 147.01 seconds
Started Jul 01 10:53:21 AM PDT 24
Finished Jul 01 10:55:51 AM PDT 24
Peak memory 183128 kb
Host smart-e061c60a-d5b5-4a98-a57c-325397e9eaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704250270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3704250270
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3723536585
Short name T155
Test name
Test status
Simulation time 53419299009 ps
CPU time 72.27 seconds
Started Jul 01 10:53:16 AM PDT 24
Finished Jul 01 10:54:36 AM PDT 24
Peak memory 191212 kb
Host smart-eac3bd9b-cc63-42a0-8e26-b5a58cf8fee5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723536585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3723536585
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3264774290
Short name T364
Test name
Test status
Simulation time 211302866369 ps
CPU time 426.02 seconds
Started Jul 01 10:53:04 AM PDT 24
Finished Jul 01 11:00:13 AM PDT 24
Peak memory 195168 kb
Host smart-525fb2b1-e552-4408-a7c3-d863b29b83b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264774290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3264774290
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.301306336
Short name T416
Test name
Test status
Simulation time 97933331054 ps
CPU time 786.72 seconds
Started Jul 01 10:53:03 AM PDT 24
Finished Jul 01 11:06:13 AM PDT 24
Peak memory 209044 kb
Host smart-58ea6c10-12ca-4400-ba7c-6547242c7a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301306336 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.301306336
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.821146441
Short name T10
Test name
Test status
Simulation time 98360181004 ps
CPU time 172.37 seconds
Started Jul 01 10:53:16 AM PDT 24
Finished Jul 01 10:56:13 AM PDT 24
Peak memory 183084 kb
Host smart-df494bca-6cec-4461-b447-a7e1deeeb788
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821146441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.821146441
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1386656185
Short name T412
Test name
Test status
Simulation time 181673991270 ps
CPU time 208.83 seconds
Started Jul 01 10:53:23 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 183132 kb
Host smart-f7c664e1-b6c4-4ce6-8620-df7789ac8630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386656185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1386656185
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2232126430
Short name T268
Test name
Test status
Simulation time 125857026467 ps
CPU time 227.69 seconds
Started Jul 01 10:53:10 AM PDT 24
Finished Jul 01 10:57:00 AM PDT 24
Peak memory 191296 kb
Host smart-4f2e1480-b0d7-4f71-bb01-e8c76d821af0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232126430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2232126430
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3895360914
Short name T113
Test name
Test status
Simulation time 265279715733 ps
CPU time 146.41 seconds
Started Jul 01 10:53:05 AM PDT 24
Finished Jul 01 10:55:34 AM PDT 24
Peak memory 191296 kb
Host smart-b93f1a06-80ef-466c-a9f5-df2e35ad1dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895360914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3895360914
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2868625899
Short name T310
Test name
Test status
Simulation time 613514342988 ps
CPU time 571.58 seconds
Started Jul 01 10:53:04 AM PDT 24
Finished Jul 01 11:02:39 AM PDT 24
Peak memory 191276 kb
Host smart-8210aad5-a86e-4b9e-a2bf-a613af21fbf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868625899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2868625899
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1733794316
Short name T437
Test name
Test status
Simulation time 1154171714550 ps
CPU time 633.89 seconds
Started Jul 01 10:53:09 AM PDT 24
Finished Jul 01 11:03:45 AM PDT 24
Peak memory 183080 kb
Host smart-7a809055-96cc-4d51-a955-ed75217b72d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733794316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1733794316
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_random.882808410
Short name T450
Test name
Test status
Simulation time 81855103341 ps
CPU time 264.79 seconds
Started Jul 01 10:53:04 AM PDT 24
Finished Jul 01 10:57:33 AM PDT 24
Peak memory 191276 kb
Host smart-78538243-b538-4e4c-b40e-fd7dfbe3ecc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882808410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.882808410
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.416342229
Short name T273
Test name
Test status
Simulation time 112901868189 ps
CPU time 47.97 seconds
Started Jul 01 10:53:23 AM PDT 24
Finished Jul 01 10:54:14 AM PDT 24
Peak memory 191324 kb
Host smart-9c5986be-1221-4f53-9c03-d8a85622f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416342229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.416342229
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2431153361
Short name T350
Test name
Test status
Simulation time 789915853103 ps
CPU time 1110.79 seconds
Started Jul 01 10:53:29 AM PDT 24
Finished Jul 01 11:12:01 AM PDT 24
Peak memory 191528 kb
Host smart-a4b8fb41-7001-4cd9-b493-eab77f4c41e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431153361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2431153361
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.564793157
Short name T383
Test name
Test status
Simulation time 465238605981 ps
CPU time 145.15 seconds
Started Jul 01 10:53:12 AM PDT 24
Finished Jul 01 10:55:39 AM PDT 24
Peak memory 183100 kb
Host smart-86fd132f-4474-484a-af63-1cb7913871a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564793157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.564793157
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1820638418
Short name T132
Test name
Test status
Simulation time 110455334936 ps
CPU time 368.47 seconds
Started Jul 01 10:53:33 AM PDT 24
Finished Jul 01 10:59:43 AM PDT 24
Peak memory 191244 kb
Host smart-8f538a01-46a9-474d-97dc-729579e1cfb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820638418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1820638418
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2323916114
Short name T201
Test name
Test status
Simulation time 37917994978 ps
CPU time 36.24 seconds
Started Jul 01 10:53:12 AM PDT 24
Finished Jul 01 10:53:51 AM PDT 24
Peak memory 191328 kb
Host smart-a5cf0f00-4c1d-46d3-a1cd-0cf7759f986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323916114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2323916114
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.935296840
Short name T345
Test name
Test status
Simulation time 32742182925 ps
CPU time 48.62 seconds
Started Jul 01 10:53:18 AM PDT 24
Finished Jul 01 10:54:11 AM PDT 24
Peak memory 183088 kb
Host smart-473e32fd-911d-453e-b52a-f74ee070150a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935296840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.935296840
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1525718970
Short name T382
Test name
Test status
Simulation time 168250749453 ps
CPU time 141.53 seconds
Started Jul 01 10:53:10 AM PDT 24
Finished Jul 01 10:55:34 AM PDT 24
Peak memory 183120 kb
Host smart-5c3dd5ae-d125-4cfe-9064-5d4c18612adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525718970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1525718970
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.316135595
Short name T407
Test name
Test status
Simulation time 992625438 ps
CPU time 2.35 seconds
Started Jul 01 10:53:12 AM PDT 24
Finished Jul 01 10:53:17 AM PDT 24
Peak memory 183068 kb
Host smart-4e15ffb4-940c-416c-9263-8358bafdf1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316135595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.316135595
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4015443498
Short name T107
Test name
Test status
Simulation time 203006379369 ps
CPU time 155.47 seconds
Started Jul 01 10:53:10 AM PDT 24
Finished Jul 01 10:55:47 AM PDT 24
Peak memory 191280 kb
Host smart-17f3e588-3f14-4cd2-b606-5ed092afd9b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015443498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4015443498
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.456814661
Short name T127
Test name
Test status
Simulation time 229677076377 ps
CPU time 352.04 seconds
Started Jul 01 10:53:10 AM PDT 24
Finished Jul 01 10:59:04 AM PDT 24
Peak memory 183056 kb
Host smart-c91dafab-925b-4c52-a099-18680da9738b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456814661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.456814661
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1461781363
Short name T403
Test name
Test status
Simulation time 120389108231 ps
CPU time 49.89 seconds
Started Jul 01 10:53:12 AM PDT 24
Finished Jul 01 10:54:05 AM PDT 24
Peak memory 183120 kb
Host smart-dcf590c0-e3a0-4b0a-b698-76eeb1846512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461781363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1461781363
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.484467639
Short name T439
Test name
Test status
Simulation time 120820463 ps
CPU time 0.8 seconds
Started Jul 01 10:53:11 AM PDT 24
Finished Jul 01 10:53:14 AM PDT 24
Peak memory 183180 kb
Host smart-c4cf4849-50c4-48aa-9699-d10e296466a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484467639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.484467639
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2675839980
Short name T431
Test name
Test status
Simulation time 549896483982 ps
CPU time 232.29 seconds
Started Jul 01 10:53:12 AM PDT 24
Finished Jul 01 10:57:06 AM PDT 24
Peak memory 183084 kb
Host smart-cf88bdb2-2778-4841-acb2-2e52b33109e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675839980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2675839980
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3236428148
Short name T38
Test name
Test status
Simulation time 76717613185 ps
CPU time 144.39 seconds
Started Jul 01 10:53:12 AM PDT 24
Finished Jul 01 10:55:39 AM PDT 24
Peak memory 197788 kb
Host smart-9a12a4e5-0821-4060-a153-23d970c86195
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236428148 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3236428148
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1874221103
Short name T369
Test name
Test status
Simulation time 13806407281 ps
CPU time 8.65 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:52:51 AM PDT 24
Peak memory 183072 kb
Host smart-55f1a6e4-8fd5-4470-9650-3dad60ec173f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874221103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1874221103
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2420984287
Short name T391
Test name
Test status
Simulation time 81509145434 ps
CPU time 34.2 seconds
Started Jul 01 10:52:58 AM PDT 24
Finished Jul 01 10:53:35 AM PDT 24
Peak memory 183100 kb
Host smart-c1568ba4-801f-4105-8582-e232439b3a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420984287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2420984287
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.4035250083
Short name T349
Test name
Test status
Simulation time 93084428619 ps
CPU time 55.42 seconds
Started Jul 01 10:52:55 AM PDT 24
Finished Jul 01 10:53:54 AM PDT 24
Peak memory 194460 kb
Host smart-b093c2ff-173b-426a-ae62-975568724b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035250083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.4035250083
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1958190595
Short name T17
Test name
Test status
Simulation time 158756349 ps
CPU time 0.75 seconds
Started Jul 01 10:52:48 AM PDT 24
Finished Jul 01 10:52:51 AM PDT 24
Peak memory 213320 kb
Host smart-8af2c5c9-cf0d-4e65-b090-63d4f2f06209
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958190595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1958190595
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.801021452
Short name T207
Test name
Test status
Simulation time 1410704417062 ps
CPU time 1068.34 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 11:10:43 AM PDT 24
Peak memory 197028 kb
Host smart-c57557ed-cbda-4bc6-9f59-574fa6cfcfec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801021452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.801021452
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.870357655
Short name T186
Test name
Test status
Simulation time 142636494418 ps
CPU time 221.75 seconds
Started Jul 01 10:53:31 AM PDT 24
Finished Jul 01 10:57:14 AM PDT 24
Peak memory 183056 kb
Host smart-c0a8227a-0871-4186-9448-5005727d4c4e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870357655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.870357655
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2229573098
Short name T21
Test name
Test status
Simulation time 127065422740 ps
CPU time 160.57 seconds
Started Jul 01 10:53:30 AM PDT 24
Finished Jul 01 10:56:11 AM PDT 24
Peak memory 183140 kb
Host smart-6d8ed289-5d2c-46d9-b29e-f19a80473884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229573098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2229573098
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3266908284
Short name T139
Test name
Test status
Simulation time 48875267375 ps
CPU time 107.87 seconds
Started Jul 01 10:53:11 AM PDT 24
Finished Jul 01 10:55:02 AM PDT 24
Peak memory 191292 kb
Host smart-02384dcb-6c16-4ba0-b88e-9259324137b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266908284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3266908284
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3193280432
Short name T362
Test name
Test status
Simulation time 304357899836 ps
CPU time 205.53 seconds
Started Jul 01 10:53:17 AM PDT 24
Finished Jul 01 10:56:47 AM PDT 24
Peak memory 194804 kb
Host smart-b9ad78ea-a9d7-49ec-95eb-addfb1514987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193280432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3193280432
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1782280651
Short name T271
Test name
Test status
Simulation time 1749515929871 ps
CPU time 839.12 seconds
Started Jul 01 10:53:17 AM PDT 24
Finished Jul 01 11:07:21 AM PDT 24
Peak memory 191276 kb
Host smart-2523d287-3e41-46ea-b6b1-d3f07cee59b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782280651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1782280651
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_random.1815642039
Short name T144
Test name
Test status
Simulation time 268790864268 ps
CPU time 265.6 seconds
Started Jul 01 10:53:12 AM PDT 24
Finished Jul 01 10:57:40 AM PDT 24
Peak memory 191296 kb
Host smart-b366a621-ee40-4082-8dae-a9374ae01af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815642039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1815642039
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3321106324
Short name T6
Test name
Test status
Simulation time 508524586 ps
CPU time 0.93 seconds
Started Jul 01 10:53:27 AM PDT 24
Finished Jul 01 10:53:30 AM PDT 24
Peak memory 182976 kb
Host smart-f9ed0290-3921-41e4-a2ba-48859b019b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321106324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3321106324
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2440595190
Short name T389
Test name
Test status
Simulation time 54830525039 ps
CPU time 86.52 seconds
Started Jul 01 10:53:17 AM PDT 24
Finished Jul 01 10:54:48 AM PDT 24
Peak memory 183080 kb
Host smart-eace7c2b-d108-4d15-ae60-09d2ff91c3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440595190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2440595190
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2990523125
Short name T136
Test name
Test status
Simulation time 137101396194 ps
CPU time 591.6 seconds
Started Jul 01 10:53:14 AM PDT 24
Finished Jul 01 11:03:08 AM PDT 24
Peak memory 194040 kb
Host smart-d0e56d57-ae50-4a0b-88fa-3bdc3be20b20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990523125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2990523125
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1937450970
Short name T307
Test name
Test status
Simulation time 71814367980 ps
CPU time 94.15 seconds
Started Jul 01 10:53:13 AM PDT 24
Finished Jul 01 10:54:50 AM PDT 24
Peak memory 191324 kb
Host smart-4caf9453-33fe-4495-8c39-d8c1316fec02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937450970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1937450970
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.1016778116
Short name T41
Test name
Test status
Simulation time 106823636495 ps
CPU time 241.85 seconds
Started Jul 01 10:53:13 AM PDT 24
Finished Jul 01 10:57:18 AM PDT 24
Peak memory 205968 kb
Host smart-d10947dd-43e3-449a-87e1-b693de270b98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016778116 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.1016778116
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3127111535
Short name T435
Test name
Test status
Simulation time 1417077797615 ps
CPU time 687.03 seconds
Started Jul 01 10:53:31 AM PDT 24
Finished Jul 01 11:04:59 AM PDT 24
Peak memory 183032 kb
Host smart-3d6c1d79-bd74-462a-897f-f99cecadf5a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127111535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3127111535
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.871040991
Short name T402
Test name
Test status
Simulation time 6330279267 ps
CPU time 4.41 seconds
Started Jul 01 10:53:30 AM PDT 24
Finished Jul 01 10:53:35 AM PDT 24
Peak memory 183124 kb
Host smart-b7badbc0-6213-4ca8-91bb-c53afa93a0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871040991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.871040991
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3368360764
Short name T236
Test name
Test status
Simulation time 581225757325 ps
CPU time 484.92 seconds
Started Jul 01 10:53:17 AM PDT 24
Finished Jul 01 11:01:26 AM PDT 24
Peak memory 191252 kb
Host smart-7d07d91c-fa89-480f-8763-d8493578b5e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368360764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3368360764
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3560734154
Short name T217
Test name
Test status
Simulation time 183574201747 ps
CPU time 188.87 seconds
Started Jul 01 10:53:29 AM PDT 24
Finished Jul 01 10:56:38 AM PDT 24
Peak memory 183068 kb
Host smart-b3b83387-5dc4-4ae9-b354-0eeb7aed318c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560734154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3560734154
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.4104073861
Short name T326
Test name
Test status
Simulation time 205730454234 ps
CPU time 346.25 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 191296 kb
Host smart-53813101-fb9d-4504-b9c9-5894e08170d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104073861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.4104073861
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3013159206
Short name T179
Test name
Test status
Simulation time 109233606887 ps
CPU time 97.53 seconds
Started Jul 01 10:53:35 AM PDT 24
Finished Jul 01 10:55:14 AM PDT 24
Peak memory 183032 kb
Host smart-9935e427-70e0-4493-a0a6-d5c5fd1b217b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013159206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3013159206
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1249028602
Short name T448
Test name
Test status
Simulation time 144402009279 ps
CPU time 203.09 seconds
Started Jul 01 10:53:20 AM PDT 24
Finished Jul 01 10:56:46 AM PDT 24
Peak memory 183108 kb
Host smart-15901694-2a95-45fa-b3e2-bc11c33e280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249028602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1249028602
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.4277458417
Short name T149
Test name
Test status
Simulation time 251161196465 ps
CPU time 229.28 seconds
Started Jul 01 10:53:20 AM PDT 24
Finished Jul 01 10:57:13 AM PDT 24
Peak memory 191172 kb
Host smart-82085dd4-74e6-4aea-be7f-118f6f868d70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277458417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.4277458417
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.955885970
Short name T393
Test name
Test status
Simulation time 113929004 ps
CPU time 0.67 seconds
Started Jul 01 10:53:22 AM PDT 24
Finished Jul 01 10:53:26 AM PDT 24
Peak memory 182920 kb
Host smart-acbf1dbb-d6af-47df-a62a-a703eba811e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955885970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.955885970
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3640822638
Short name T415
Test name
Test status
Simulation time 332425552053 ps
CPU time 129.17 seconds
Started Jul 01 10:53:19 AM PDT 24
Finished Jul 01 10:55:32 AM PDT 24
Peak memory 195688 kb
Host smart-9fbb0fcc-6f75-46ae-a73d-e955567612f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640822638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3640822638
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1496058574
Short name T209
Test name
Test status
Simulation time 555809992362 ps
CPU time 274.98 seconds
Started Jul 01 10:53:31 AM PDT 24
Finished Jul 01 10:58:07 AM PDT 24
Peak memory 183080 kb
Host smart-e0797655-c2ab-4f94-b3ef-954a541988cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496058574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1496058574
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.790741335
Short name T422
Test name
Test status
Simulation time 1459882794 ps
CPU time 1.52 seconds
Started Jul 01 10:53:30 AM PDT 24
Finished Jul 01 10:53:33 AM PDT 24
Peak memory 182948 kb
Host smart-81aaeb17-7508-4e08-8019-9894bf52ae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790741335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.790741335
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.100465103
Short name T57
Test name
Test status
Simulation time 131501534692 ps
CPU time 246.19 seconds
Started Jul 01 10:53:34 AM PDT 24
Finished Jul 01 10:57:41 AM PDT 24
Peak memory 191524 kb
Host smart-84db312c-cc29-41a8-a89c-ca5fa5f8f6fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100465103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.100465103
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2223164933
Short name T452
Test name
Test status
Simulation time 20197682242 ps
CPU time 31.52 seconds
Started Jul 01 10:53:30 AM PDT 24
Finished Jul 01 10:54:02 AM PDT 24
Peak memory 183112 kb
Host smart-3646883e-e792-4276-964f-f4c176536315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223164933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2223164933
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3850294879
Short name T63
Test name
Test status
Simulation time 1307753181396 ps
CPU time 1520.11 seconds
Started Jul 01 10:53:26 AM PDT 24
Finished Jul 01 11:18:48 AM PDT 24
Peak memory 195780 kb
Host smart-cb250133-dde0-440b-b9dd-431a0cf29af7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850294879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3850294879
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3708952451
Short name T284
Test name
Test status
Simulation time 127940650513 ps
CPU time 214.41 seconds
Started Jul 01 10:53:22 AM PDT 24
Finished Jul 01 10:56:59 AM PDT 24
Peak memory 183104 kb
Host smart-a0560408-817c-4144-b97d-c7184eefa81f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708952451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3708952451
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2465800451
Short name T414
Test name
Test status
Simulation time 280347508001 ps
CPU time 189.17 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 10:56:42 AM PDT 24
Peak memory 183120 kb
Host smart-2310b34d-1971-4ee3-b4eb-7cf2cc37779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465800451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2465800451
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3696499376
Short name T192
Test name
Test status
Simulation time 4190935534 ps
CPU time 2.78 seconds
Started Jul 01 10:53:17 AM PDT 24
Finished Jul 01 10:53:24 AM PDT 24
Peak memory 194820 kb
Host smart-f52ec892-0694-4a8e-bb93-4ffbcd2e1c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696499376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3696499376
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.693121971
Short name T405
Test name
Test status
Simulation time 161102581 ps
CPU time 0.64 seconds
Started Jul 01 10:53:22 AM PDT 24
Finished Jul 01 10:53:25 AM PDT 24
Peak memory 182964 kb
Host smart-f7baf551-2094-4b31-82e8-2675731b06b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693121971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
693121971
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2215869686
Short name T293
Test name
Test status
Simulation time 345019684621 ps
CPU time 285.28 seconds
Started Jul 01 10:53:33 AM PDT 24
Finished Jul 01 10:58:19 AM PDT 24
Peak memory 183100 kb
Host smart-98c66f5e-1c57-4e75-abee-fba9d9ceb4ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215869686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2215869686
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1667279901
Short name T397
Test name
Test status
Simulation time 98728339674 ps
CPU time 148.85 seconds
Started Jul 01 10:53:17 AM PDT 24
Finished Jul 01 10:55:50 AM PDT 24
Peak memory 183100 kb
Host smart-5991146b-96d7-48a0-ae23-ab952c247b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667279901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1667279901
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.860966408
Short name T166
Test name
Test status
Simulation time 105056022829 ps
CPU time 790.94 seconds
Started Jul 01 10:53:17 AM PDT 24
Finished Jul 01 11:06:33 AM PDT 24
Peak memory 191288 kb
Host smart-1c97f33b-c5e7-4b23-90da-e7442c836036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860966408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.860966408
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.850961845
Short name T378
Test name
Test status
Simulation time 9741490421 ps
CPU time 4.46 seconds
Started Jul 01 10:53:29 AM PDT 24
Finished Jul 01 10:53:35 AM PDT 24
Peak memory 183148 kb
Host smart-2ee56feb-851d-435a-88df-4286ca651339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850961845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.850961845
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3993664164
Short name T451
Test name
Test status
Simulation time 376131750918 ps
CPU time 205.55 seconds
Started Jul 01 10:53:33 AM PDT 24
Finished Jul 01 10:57:00 AM PDT 24
Peak memory 183100 kb
Host smart-4d7ef83f-13be-4180-936d-c5388d239635
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993664164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3993664164
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1341640469
Short name T449
Test name
Test status
Simulation time 9150548968 ps
CPU time 6.38 seconds
Started Jul 01 10:53:21 AM PDT 24
Finished Jul 01 10:53:31 AM PDT 24
Peak memory 182988 kb
Host smart-64f0cbb1-5f5b-4b1b-b91d-e06d5512914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341640469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1341640469
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2724916958
Short name T128
Test name
Test status
Simulation time 173685646008 ps
CPU time 337.27 seconds
Started Jul 01 10:53:38 AM PDT 24
Finished Jul 01 10:59:16 AM PDT 24
Peak memory 191428 kb
Host smart-60c54e47-a145-43da-9114-ca5ac0e6b2ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724916958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2724916958
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1066908931
Short name T274
Test name
Test status
Simulation time 49448184055 ps
CPU time 198.54 seconds
Started Jul 01 10:53:17 AM PDT 24
Finished Jul 01 10:56:40 AM PDT 24
Peak memory 195188 kb
Host smart-eeb5ae24-289e-4c41-addc-975e5e23b282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066908931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1066908931
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3720676458
Short name T42
Test name
Test status
Simulation time 49449738371 ps
CPU time 82.99 seconds
Started Jul 01 10:53:20 AM PDT 24
Finished Jul 01 10:54:47 AM PDT 24
Peak memory 183080 kb
Host smart-7d8e61cc-a75c-4bd4-95b5-3fd26c80b98c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720676458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3720676458
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3305868793
Short name T76
Test name
Test status
Simulation time 163574156033 ps
CPU time 120.32 seconds
Started Jul 01 10:53:27 AM PDT 24
Finished Jul 01 10:55:28 AM PDT 24
Peak memory 183056 kb
Host smart-87a9a22e-3d95-414e-9590-d076c63b9fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305868793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3305868793
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.737226919
Short name T8
Test name
Test status
Simulation time 27777876019 ps
CPU time 44.09 seconds
Started Jul 01 10:53:34 AM PDT 24
Finished Jul 01 10:54:20 AM PDT 24
Peak memory 183036 kb
Host smart-421fbca4-0c03-4068-9be4-3c167db9d102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737226919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.737226919
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1720794241
Short name T1
Test name
Test status
Simulation time 212536051843 ps
CPU time 357.95 seconds
Started Jul 01 10:53:18 AM PDT 24
Finished Jul 01 10:59:20 AM PDT 24
Peak memory 191332 kb
Host smart-2597474e-7233-4b40-8670-396253e9a224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720794241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1720794241
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1114582929
Short name T418
Test name
Test status
Simulation time 180106735097 ps
CPU time 272.77 seconds
Started Jul 01 10:53:18 AM PDT 24
Finished Jul 01 10:57:55 AM PDT 24
Peak memory 191300 kb
Host smart-04be2e8d-d6cd-49e3-b5cd-4cf19ea6e960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114582929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1114582929
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.524724466
Short name T44
Test name
Test status
Simulation time 28942784503 ps
CPU time 193.43 seconds
Started Jul 01 10:53:18 AM PDT 24
Finished Jul 01 10:56:35 AM PDT 24
Peak memory 205944 kb
Host smart-9687398d-5267-47be-b7cd-1296f591b099
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524724466 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.524724466
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1054414530
Short name T145
Test name
Test status
Simulation time 357217682374 ps
CPU time 82.5 seconds
Started Jul 01 10:52:52 AM PDT 24
Finished Jul 01 10:54:19 AM PDT 24
Peak memory 183028 kb
Host smart-37c91ce5-709f-453c-ba12-fb0af2c5d2fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054414530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1054414530
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.294792786
Short name T401
Test name
Test status
Simulation time 221073378208 ps
CPU time 261.39 seconds
Started Jul 01 10:52:47 AM PDT 24
Finished Jul 01 10:57:12 AM PDT 24
Peak memory 182964 kb
Host smart-1c75af33-24c0-48a1-9aa1-4b6b98da75fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294792786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.294792786
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2741102248
Short name T373
Test name
Test status
Simulation time 178819531671 ps
CPU time 3305 seconds
Started Jul 01 10:52:45 AM PDT 24
Finished Jul 01 11:47:54 AM PDT 24
Peak memory 191280 kb
Host smart-347e104f-98a5-4787-b444-6edf26e0e9c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741102248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2741102248
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2405288793
Short name T277
Test name
Test status
Simulation time 148997891522 ps
CPU time 364.35 seconds
Started Jul 01 10:52:50 AM PDT 24
Finished Jul 01 10:58:59 AM PDT 24
Peak memory 183132 kb
Host smart-5cd875f0-fd8f-4d64-9641-8adadcdb2161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405288793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2405288793
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1288301858
Short name T16
Test name
Test status
Simulation time 866114032 ps
CPU time 1 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 10:52:50 AM PDT 24
Peak memory 214516 kb
Host smart-d2cabf67-6ea0-4313-9c91-50e9ed3869e4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288301858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1288301858
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1101132105
Short name T355
Test name
Test status
Simulation time 91548021890 ps
CPU time 162.27 seconds
Started Jul 01 10:53:23 AM PDT 24
Finished Jul 01 10:56:08 AM PDT 24
Peak memory 183080 kb
Host smart-19bd164a-a7b0-4c27-888c-a9c11bb0eed4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101132105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1101132105
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.410236334
Short name T388
Test name
Test status
Simulation time 15637823629 ps
CPU time 23.26 seconds
Started Jul 01 10:53:31 AM PDT 24
Finished Jul 01 10:53:55 AM PDT 24
Peak memory 183128 kb
Host smart-4f191ca5-3b3c-4e5f-b3ce-d076082ae5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410236334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.410236334
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.842575566
Short name T434
Test name
Test status
Simulation time 23874304079 ps
CPU time 54.83 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 10:54:28 AM PDT 24
Peak memory 183112 kb
Host smart-e908d2b8-e980-48a4-873d-9ce3c89ea44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842575566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.842575566
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.15114924
Short name T34
Test name
Test status
Simulation time 492533583304 ps
CPU time 978.73 seconds
Started Jul 01 10:53:37 AM PDT 24
Finished Jul 01 11:09:56 AM PDT 24
Peak memory 191316 kb
Host smart-15bbe0ea-a141-47e0-b3c6-d70125a0df15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15114924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.15114924
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.2389001011
Short name T428
Test name
Test status
Simulation time 22241154079 ps
CPU time 185.94 seconds
Started Jul 01 10:53:22 AM PDT 24
Finished Jul 01 10:56:31 AM PDT 24
Peak memory 197768 kb
Host smart-3638691b-50da-4b0e-977e-c4da9dbf3467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389001011 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.2389001011
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.4065868609
Short name T321
Test name
Test status
Simulation time 131827400218 ps
CPU time 67.06 seconds
Started Jul 01 10:53:23 AM PDT 24
Finished Jul 01 10:54:33 AM PDT 24
Peak memory 183072 kb
Host smart-0328b7bf-eae8-4b20-b42a-44e42d5bba0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065868609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.4065868609
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1376341615
Short name T384
Test name
Test status
Simulation time 98601165575 ps
CPU time 147.27 seconds
Started Jul 01 10:53:26 AM PDT 24
Finished Jul 01 10:55:55 AM PDT 24
Peak memory 182992 kb
Host smart-42c45f2e-15e9-42c4-9866-541ec3cc47ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376341615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1376341615
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3283452823
Short name T23
Test name
Test status
Simulation time 31751655077 ps
CPU time 53.97 seconds
Started Jul 01 10:53:25 AM PDT 24
Finished Jul 01 10:54:21 AM PDT 24
Peak memory 183092 kb
Host smart-2fb7571f-1765-4ddf-9b27-5c56aa40fa5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283452823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3283452823
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2569430357
Short name T308
Test name
Test status
Simulation time 440361256620 ps
CPU time 448.35 seconds
Started Jul 01 10:53:35 AM PDT 24
Finished Jul 01 11:01:05 AM PDT 24
Peak memory 191256 kb
Host smart-b4bc2574-a780-4910-8f84-f6cf89542212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569430357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2569430357
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2776883619
Short name T429
Test name
Test status
Simulation time 965372639136 ps
CPU time 254.82 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 10:57:48 AM PDT 24
Peak memory 183132 kb
Host smart-77f4b525-bb46-4d28-80e6-d52fffc502c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776883619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2776883619
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3754790065
Short name T226
Test name
Test status
Simulation time 509140048482 ps
CPU time 1656.95 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 11:21:10 AM PDT 24
Peak memory 191268 kb
Host smart-706fdc82-80f8-4a51-b386-ea3fcd4bcdb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754790065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3754790065
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.444510534
Short name T242
Test name
Test status
Simulation time 85396381928 ps
CPU time 93.09 seconds
Started Jul 01 10:53:30 AM PDT 24
Finished Jul 01 10:55:04 AM PDT 24
Peak memory 183140 kb
Host smart-86134ee2-a43b-4280-9fa4-5f8a6f8ffb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444510534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.444510534
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1824814432
Short name T65
Test name
Test status
Simulation time 349685788391 ps
CPU time 808.42 seconds
Started Jul 01 10:53:34 AM PDT 24
Finished Jul 01 11:07:04 AM PDT 24
Peak memory 191316 kb
Host smart-04c516bf-2cc2-4432-82c8-cc24b82306c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824814432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1824814432
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1053301456
Short name T336
Test name
Test status
Simulation time 971076075826 ps
CPU time 467.46 seconds
Started Jul 01 10:53:23 AM PDT 24
Finished Jul 01 11:01:13 AM PDT 24
Peak memory 182988 kb
Host smart-0db0da4b-9ea8-4bfb-b3a2-63c04609ad38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053301456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1053301456
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1328094403
Short name T20
Test name
Test status
Simulation time 10614326631 ps
CPU time 16.56 seconds
Started Jul 01 10:53:34 AM PDT 24
Finished Jul 01 10:53:53 AM PDT 24
Peak memory 183016 kb
Host smart-5ea6bef3-7c02-4f08-86dc-ed07f57f4860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328094403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1328094403
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2522530499
Short name T221
Test name
Test status
Simulation time 120829666826 ps
CPU time 184.16 seconds
Started Jul 01 10:53:34 AM PDT 24
Finished Jul 01 10:56:39 AM PDT 24
Peak memory 191324 kb
Host smart-a51c58ec-f197-4368-b522-9564c21d21b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522530499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2522530499
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.1379949969
Short name T75
Test name
Test status
Simulation time 44884771589 ps
CPU time 40.84 seconds
Started Jul 01 10:53:33 AM PDT 24
Finished Jul 01 10:54:15 AM PDT 24
Peak memory 191316 kb
Host smart-958862ef-13e4-4fd9-9523-b24bf1492881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379949969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.1379949969
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2790202028
Short name T11
Test name
Test status
Simulation time 29741287575 ps
CPU time 85.96 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 10:54:59 AM PDT 24
Peak memory 197828 kb
Host smart-13fda67d-78c5-4c46-8b83-1fe6af437a28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790202028 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2790202028
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1207146729
Short name T413
Test name
Test status
Simulation time 146593779295 ps
CPU time 107.75 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 10:55:21 AM PDT 24
Peak memory 183132 kb
Host smart-0eb4b5f8-4405-4176-8ae1-1ab6af60ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207146729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1207146729
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3355158269
Short name T261
Test name
Test status
Simulation time 125191281554 ps
CPU time 51.04 seconds
Started Jul 01 10:53:33 AM PDT 24
Finished Jul 01 10:54:25 AM PDT 24
Peak memory 183124 kb
Host smart-11be7454-a38c-4026-a684-3f5392117a97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355158269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3355158269
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.679968547
Short name T176
Test name
Test status
Simulation time 23627694654 ps
CPU time 32.55 seconds
Started Jul 01 10:53:42 AM PDT 24
Finished Jul 01 10:54:16 AM PDT 24
Peak memory 194840 kb
Host smart-46e3122d-b2a8-4f3c-bac5-7799b7992e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679968547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.679968547
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.2488514328
Short name T37
Test name
Test status
Simulation time 60855693898 ps
CPU time 179.8 seconds
Started Jul 01 10:53:36 AM PDT 24
Finished Jul 01 10:56:37 AM PDT 24
Peak memory 206028 kb
Host smart-9ce6fc1f-9c62-41f0-a294-17eb07da3849
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488514328 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.2488514328
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.803295943
Short name T152
Test name
Test status
Simulation time 40062963637 ps
CPU time 21.86 seconds
Started Jul 01 10:53:38 AM PDT 24
Finished Jul 01 10:54:01 AM PDT 24
Peak memory 183124 kb
Host smart-ada3c2f8-8005-4d28-b2e5-8cd66873b66d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803295943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.803295943
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1355595305
Short name T390
Test name
Test status
Simulation time 153970250862 ps
CPU time 101.92 seconds
Started Jul 01 10:53:27 AM PDT 24
Finished Jul 01 10:55:10 AM PDT 24
Peak memory 183088 kb
Host smart-3c26e4d5-e870-4913-8044-cbc94e839c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355595305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1355595305
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2633679323
Short name T441
Test name
Test status
Simulation time 57305502 ps
CPU time 0.54 seconds
Started Jul 01 10:53:33 AM PDT 24
Finished Jul 01 10:53:35 AM PDT 24
Peak memory 182908 kb
Host smart-993fc8a7-2392-4cbb-8175-2486d9a109c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633679323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2633679323
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.337231891
Short name T58
Test name
Test status
Simulation time 67180109281 ps
CPU time 110.19 seconds
Started Jul 01 10:53:33 AM PDT 24
Finished Jul 01 10:55:25 AM PDT 24
Peak memory 183120 kb
Host smart-de59f0e1-f93f-4cdd-af49-967274e48b74
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337231891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.337231891
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.509773683
Short name T442
Test name
Test status
Simulation time 103026011989 ps
CPU time 15.69 seconds
Started Jul 01 10:53:26 AM PDT 24
Finished Jul 01 10:53:43 AM PDT 24
Peak memory 183132 kb
Host smart-3a609674-00e8-4fd9-911b-e61839d77b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509773683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.509773683
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.375817360
Short name T301
Test name
Test status
Simulation time 301947485777 ps
CPU time 443.66 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 11:00:57 AM PDT 24
Peak memory 191280 kb
Host smart-1ddfe242-5e85-4843-b7a6-0c98be2200d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375817360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.375817360
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2498719415
Short name T7
Test name
Test status
Simulation time 94915536477 ps
CPU time 66.17 seconds
Started Jul 01 10:53:33 AM PDT 24
Finished Jul 01 10:54:40 AM PDT 24
Peak memory 191256 kb
Host smart-974502af-ab9c-40db-8889-d00c428384b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498719415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2498719415
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.160556941
Short name T225
Test name
Test status
Simulation time 320327961032 ps
CPU time 496.78 seconds
Started Jul 01 10:53:28 AM PDT 24
Finished Jul 01 11:01:46 AM PDT 24
Peak memory 191276 kb
Host smart-58fd8b86-2eb2-427f-b95e-cf317b7fbf5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160556941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
160556941
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3904471642
Short name T305
Test name
Test status
Simulation time 432222577678 ps
CPU time 699.1 seconds
Started Jul 01 10:53:26 AM PDT 24
Finished Jul 01 11:05:06 AM PDT 24
Peak memory 183092 kb
Host smart-3e49b987-eedc-4fef-a430-a7f26326edb8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904471642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3904471642
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1910471543
Short name T432
Test name
Test status
Simulation time 618818303019 ps
CPU time 145.65 seconds
Started Jul 01 10:53:34 AM PDT 24
Finished Jul 01 10:56:01 AM PDT 24
Peak memory 182976 kb
Host smart-a5ee0e70-0b03-4efd-bb98-bc2700ee084e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910471543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1910471543
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.801099192
Short name T167
Test name
Test status
Simulation time 192185574582 ps
CPU time 278.89 seconds
Started Jul 01 10:53:28 AM PDT 24
Finished Jul 01 10:58:08 AM PDT 24
Peak memory 191268 kb
Host smart-658aa136-ed4f-48c3-834e-13caac4d522d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801099192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.801099192
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3823235370
Short name T421
Test name
Test status
Simulation time 14494973001 ps
CPU time 13.62 seconds
Started Jul 01 10:53:31 AM PDT 24
Finished Jul 01 10:53:45 AM PDT 24
Peak memory 191256 kb
Host smart-dca39a09-04de-49c8-add9-14e1e68651d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823235370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3823235370
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1210698829
Short name T320
Test name
Test status
Simulation time 344415452660 ps
CPU time 503.19 seconds
Started Jul 01 10:53:38 AM PDT 24
Finished Jul 01 11:02:03 AM PDT 24
Peak memory 195724 kb
Host smart-5c33e13b-7e57-46c1-846a-f2e21bdc5a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210698829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1210698829
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3987749008
Short name T338
Test name
Test status
Simulation time 1976907123931 ps
CPU time 926.49 seconds
Started Jul 01 10:53:31 AM PDT 24
Finished Jul 01 11:08:59 AM PDT 24
Peak memory 182960 kb
Host smart-3fdbdb31-b59b-4830-9d24-07e6689fba22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987749008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3987749008
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.4095552882
Short name T443
Test name
Test status
Simulation time 163613643219 ps
CPU time 126.64 seconds
Started Jul 01 10:53:29 AM PDT 24
Finished Jul 01 10:55:37 AM PDT 24
Peak memory 183096 kb
Host smart-27c0cb41-b9d1-4d15-8c93-93826244d3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095552882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.4095552882
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.866877751
Short name T70
Test name
Test status
Simulation time 491188901892 ps
CPU time 224.16 seconds
Started Jul 01 10:53:34 AM PDT 24
Finished Jul 01 10:57:20 AM PDT 24
Peak memory 191284 kb
Host smart-12d13ec1-23e4-42a0-a799-2dc2b7863f6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866877751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.866877751
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2148730776
Short name T244
Test name
Test status
Simulation time 2550021656 ps
CPU time 3.66 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 10:53:36 AM PDT 24
Peak memory 183024 kb
Host smart-7b301006-9fbf-4e0c-a587-e5cab7ffd2a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148730776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2148730776
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1465810555
Short name T25
Test name
Test status
Simulation time 38426043114 ps
CPU time 23.67 seconds
Started Jul 01 10:53:32 AM PDT 24
Finished Jul 01 10:53:56 AM PDT 24
Peak memory 183100 kb
Host smart-d2d19aad-7e8b-4502-bda4-35c9a67a8338
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465810555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1465810555
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1397463625
Short name T408
Test name
Test status
Simulation time 88662101199 ps
CPU time 126.42 seconds
Started Jul 01 10:53:36 AM PDT 24
Finished Jul 01 10:55:44 AM PDT 24
Peak memory 183068 kb
Host smart-87958729-1128-4028-8454-d0cd464f569a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397463625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1397463625
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.423051488
Short name T424
Test name
Test status
Simulation time 78812768454 ps
CPU time 263.77 seconds
Started Jul 01 10:53:31 AM PDT 24
Finished Jul 01 10:57:56 AM PDT 24
Peak memory 191300 kb
Host smart-64e69091-6eb2-438b-a813-3c532e7656d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423051488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.423051488
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.605967930
Short name T282
Test name
Test status
Simulation time 238050052776 ps
CPU time 340.7 seconds
Started Jul 01 10:53:31 AM PDT 24
Finished Jul 01 10:59:12 AM PDT 24
Peak memory 191288 kb
Host smart-ccca4822-968b-4fc5-9aab-22c4a6cd4ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605967930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
605967930
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3014358272
Short name T376
Test name
Test status
Simulation time 368628605582 ps
CPU time 190.33 seconds
Started Jul 01 10:52:47 AM PDT 24
Finished Jul 01 10:56:00 AM PDT 24
Peak memory 183084 kb
Host smart-4023d04f-c201-4568-8e1c-26328c6501b9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014358272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3014358272
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.708423343
Short name T71
Test name
Test status
Simulation time 215597914859 ps
CPU time 351.36 seconds
Started Jul 01 10:52:45 AM PDT 24
Finished Jul 01 10:58:39 AM PDT 24
Peak memory 183092 kb
Host smart-fb7afd38-e774-4875-837f-95850d24ca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708423343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.708423343
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2817109322
Short name T323
Test name
Test status
Simulation time 93811559885 ps
CPU time 114.83 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 10:54:44 AM PDT 24
Peak memory 191288 kb
Host smart-ff5c0910-e546-4dca-afcc-61127fcf73cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817109322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2817109322
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3720976494
Short name T124
Test name
Test status
Simulation time 349743405583 ps
CPU time 228.8 seconds
Started Jul 01 10:52:44 AM PDT 24
Finished Jul 01 10:56:37 AM PDT 24
Peak memory 194536 kb
Host smart-c282070c-57e3-4e7f-869e-67df4bd1af0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720976494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3720976494
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3309285402
Short name T341
Test name
Test status
Simulation time 237633737877 ps
CPU time 823.04 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 11:06:32 AM PDT 24
Peak memory 191288 kb
Host smart-f1083290-d773-41e4-81fb-2cae17dc85bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309285402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3309285402
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.1919113385
Short name T59
Test name
Test status
Simulation time 285191110129 ps
CPU time 469.28 seconds
Started Jul 01 10:53:34 AM PDT 24
Finished Jul 01 11:01:25 AM PDT 24
Peak memory 191252 kb
Host smart-5232967f-bedf-4907-a833-af8e0a46accd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919113385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1919113385
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.316343204
Short name T353
Test name
Test status
Simulation time 73214580272 ps
CPU time 256.91 seconds
Started Jul 01 10:53:36 AM PDT 24
Finished Jul 01 10:57:54 AM PDT 24
Peak memory 191296 kb
Host smart-0375a950-d8ad-492b-886a-8d59283d9934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316343204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.316343204
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.968037764
Short name T368
Test name
Test status
Simulation time 13229535156 ps
CPU time 21.64 seconds
Started Jul 01 10:53:37 AM PDT 24
Finished Jul 01 10:54:00 AM PDT 24
Peak memory 182964 kb
Host smart-41331839-059e-46f3-ba01-549b8dcbe654
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968037764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.968037764
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2763801803
Short name T146
Test name
Test status
Simulation time 186492843274 ps
CPU time 186.85 seconds
Started Jul 01 10:53:42 AM PDT 24
Finished Jul 01 10:56:50 AM PDT 24
Peak memory 191288 kb
Host smart-48e57b3b-9466-40d7-9d2d-bd126e775959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763801803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2763801803
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2891454334
Short name T164
Test name
Test status
Simulation time 101161672487 ps
CPU time 148.89 seconds
Started Jul 01 10:53:45 AM PDT 24
Finished Jul 01 10:56:14 AM PDT 24
Peak memory 194676 kb
Host smart-91711989-fc9f-48e6-9bcf-ba3d5f3bd215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891454334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2891454334
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.839302068
Short name T280
Test name
Test status
Simulation time 18452158367 ps
CPU time 91.54 seconds
Started Jul 01 10:53:41 AM PDT 24
Finished Jul 01 10:55:14 AM PDT 24
Peak memory 183116 kb
Host smart-ffbf0c7b-5665-4c81-8826-3bffaa1683b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839302068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.839302068
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.418965472
Short name T234
Test name
Test status
Simulation time 161647574404 ps
CPU time 525.05 seconds
Started Jul 01 10:53:41 AM PDT 24
Finished Jul 01 11:02:28 AM PDT 24
Peak memory 191284 kb
Host smart-67c36496-3639-4fbb-9bd3-a20a2798d6c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418965472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.418965472
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2434173803
Short name T430
Test name
Test status
Simulation time 75221531766 ps
CPU time 134.15 seconds
Started Jul 01 10:53:43 AM PDT 24
Finished Jul 01 10:55:58 AM PDT 24
Peak memory 183084 kb
Host smart-318d1e34-912b-466a-b711-0f21a601cf93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434173803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2434173803
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.3977509216
Short name T358
Test name
Test status
Simulation time 93673134610 ps
CPU time 479.5 seconds
Started Jul 01 10:53:41 AM PDT 24
Finished Jul 01 11:01:42 AM PDT 24
Peak memory 191312 kb
Host smart-cdf40eec-8319-4d70-b90b-711a2dbbcf58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977509216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.3977509216
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2191887638
Short name T370
Test name
Test status
Simulation time 201762342132 ps
CPU time 74.78 seconds
Started Jul 01 10:53:39 AM PDT 24
Finished Jul 01 10:54:55 AM PDT 24
Peak memory 191292 kb
Host smart-e0e4d297-6334-4fa5-9257-4c93a8c0f217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191887638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2191887638
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1341138539
Short name T356
Test name
Test status
Simulation time 44549698694 ps
CPU time 68.35 seconds
Started Jul 01 10:52:45 AM PDT 24
Finished Jul 01 10:53:57 AM PDT 24
Peak memory 183088 kb
Host smart-14eaa98e-f2ff-4b17-a660-c082ccb07247
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341138539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1341138539
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2440030243
Short name T5
Test name
Test status
Simulation time 164352054190 ps
CPU time 223.87 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 10:56:33 AM PDT 24
Peak memory 183108 kb
Host smart-cc86733c-43fe-4209-b398-edbc96c8bd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440030243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2440030243
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3249161139
Short name T131
Test name
Test status
Simulation time 37801040743 ps
CPU time 1358.2 seconds
Started Jul 01 10:52:45 AM PDT 24
Finished Jul 01 11:15:27 AM PDT 24
Peak memory 183020 kb
Host smart-4cd4b110-31b4-4381-b035-ea6fb1dea26c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249161139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3249161139
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2017552209
Short name T423
Test name
Test status
Simulation time 724768013 ps
CPU time 0.88 seconds
Started Jul 01 10:52:48 AM PDT 24
Finished Jul 01 10:52:51 AM PDT 24
Peak memory 192892 kb
Host smart-a56f4663-bdf2-4ba2-8d76-1112111c245b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017552209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2017552209
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3557351718
Short name T134
Test name
Test status
Simulation time 934923556855 ps
CPU time 3369.87 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 11:49:06 AM PDT 24
Peak memory 191304 kb
Host smart-91c3c533-19de-49b1-854f-4764b2852f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557351718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3557351718
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.420126663
Short name T109
Test name
Test status
Simulation time 658813892868 ps
CPU time 403.05 seconds
Started Jul 01 10:53:39 AM PDT 24
Finished Jul 01 11:00:23 AM PDT 24
Peak memory 191156 kb
Host smart-e52b707f-fbac-4753-9661-f4546e9a649a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420126663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.420126663
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.82069314
Short name T151
Test name
Test status
Simulation time 206493881142 ps
CPU time 504.29 seconds
Started Jul 01 10:53:42 AM PDT 24
Finished Jul 01 11:02:08 AM PDT 24
Peak memory 191276 kb
Host smart-28159e74-0f72-40cb-a88a-db14c43b427a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82069314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.82069314
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.4291307179
Short name T110
Test name
Test status
Simulation time 113469780157 ps
CPU time 251.84 seconds
Started Jul 01 10:53:42 AM PDT 24
Finished Jul 01 10:57:55 AM PDT 24
Peak memory 183084 kb
Host smart-ba467905-f765-4f85-88e9-508ad8d423e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291307179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4291307179
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3973725183
Short name T191
Test name
Test status
Simulation time 5564486634 ps
CPU time 6.37 seconds
Started Jul 01 10:53:45 AM PDT 24
Finished Jul 01 10:53:52 AM PDT 24
Peak memory 183116 kb
Host smart-dc98aa0c-459f-4ef0-a523-bff3c77375e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973725183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3973725183
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3117874320
Short name T372
Test name
Test status
Simulation time 400167987841 ps
CPU time 96.64 seconds
Started Jul 01 10:53:41 AM PDT 24
Finished Jul 01 10:55:19 AM PDT 24
Peak memory 183104 kb
Host smart-139cc818-f640-4f83-be36-05a47723b0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117874320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3117874320
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4159650375
Short name T250
Test name
Test status
Simulation time 237462216310 ps
CPU time 188.71 seconds
Started Jul 01 10:53:40 AM PDT 24
Finished Jul 01 10:56:49 AM PDT 24
Peak memory 194568 kb
Host smart-eee446a3-5672-412a-8734-acfff288df5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159650375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4159650375
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2176265822
Short name T275
Test name
Test status
Simulation time 84288895052 ps
CPU time 243.44 seconds
Started Jul 01 10:53:44 AM PDT 24
Finished Jul 01 10:57:48 AM PDT 24
Peak memory 191288 kb
Host smart-122ee8b5-694a-405e-9305-cadc5936164a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176265822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2176265822
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.877326728
Short name T346
Test name
Test status
Simulation time 88237261478 ps
CPU time 83.21 seconds
Started Jul 01 10:52:47 AM PDT 24
Finished Jul 01 10:54:13 AM PDT 24
Peak memory 183100 kb
Host smart-49abf9f7-3848-4bff-b417-cd65000a4eaf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877326728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.877326728
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4140858873
Short name T438
Test name
Test status
Simulation time 367830017673 ps
CPU time 284.99 seconds
Started Jul 01 10:52:43 AM PDT 24
Finished Jul 01 10:57:31 AM PDT 24
Peak memory 183096 kb
Host smart-5357dca8-15d1-427c-a84e-3aef05a75d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140858873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4140858873
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2211029561
Short name T300
Test name
Test status
Simulation time 82282490443 ps
CPU time 146.96 seconds
Started Jul 01 10:52:52 AM PDT 24
Finished Jul 01 10:55:24 AM PDT 24
Peak memory 191328 kb
Host smart-cbade5f4-b08b-4387-9055-24db2e0c8397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211029561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2211029561
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3039027013
Short name T297
Test name
Test status
Simulation time 5024078865 ps
CPU time 6.73 seconds
Started Jul 01 10:52:40 AM PDT 24
Finished Jul 01 10:52:50 AM PDT 24
Peak memory 191300 kb
Host smart-f6050944-2e15-4a76-b349-ddb938f7b23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039027013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3039027013
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.273332815
Short name T36
Test name
Test status
Simulation time 60623885122 ps
CPU time 159.96 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 10:55:29 AM PDT 24
Peak memory 205992 kb
Host smart-17abaf95-a00e-40b0-baa2-686eec97f3a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273332815 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.273332815
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.917286155
Short name T317
Test name
Test status
Simulation time 447973046691 ps
CPU time 255.32 seconds
Started Jul 01 10:53:44 AM PDT 24
Finished Jul 01 10:58:00 AM PDT 24
Peak memory 191192 kb
Host smart-e2ef8fc6-f0f1-440e-9382-cc1cc39446b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917286155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.917286155
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1786150436
Short name T316
Test name
Test status
Simulation time 383655540402 ps
CPU time 123.49 seconds
Started Jul 01 10:53:45 AM PDT 24
Finished Jul 01 10:55:49 AM PDT 24
Peak memory 183104 kb
Host smart-7e067e99-3d3e-4d9a-9d56-2346addd487f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786150436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1786150436
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.138166598
Short name T198
Test name
Test status
Simulation time 16684439759 ps
CPU time 10 seconds
Started Jul 01 10:53:45 AM PDT 24
Finished Jul 01 10:53:55 AM PDT 24
Peak memory 183004 kb
Host smart-b56b0c31-ca03-4120-a0b0-981b522ba51f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138166598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.138166598
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3877863521
Short name T348
Test name
Test status
Simulation time 11275987795 ps
CPU time 15.44 seconds
Started Jul 01 10:53:44 AM PDT 24
Finished Jul 01 10:54:00 AM PDT 24
Peak memory 183160 kb
Host smart-3648faf5-ca07-4b81-a008-0b17ee0ec71e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877863521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3877863521
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1112014989
Short name T174
Test name
Test status
Simulation time 376838206780 ps
CPU time 175.04 seconds
Started Jul 01 10:53:46 AM PDT 24
Finished Jul 01 10:56:41 AM PDT 24
Peak memory 191312 kb
Host smart-b7cfa94f-ee97-4b0e-bcf8-273f3c056977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112014989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1112014989
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1218770698
Short name T235
Test name
Test status
Simulation time 144426725920 ps
CPU time 109.81 seconds
Started Jul 01 10:53:45 AM PDT 24
Finished Jul 01 10:55:35 AM PDT 24
Peak memory 191272 kb
Host smart-16a68acf-4f8c-4d76-a080-fdacae4ff4b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218770698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1218770698
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2983007519
Short name T163
Test name
Test status
Simulation time 381597344531 ps
CPU time 171.26 seconds
Started Jul 01 10:53:51 AM PDT 24
Finished Jul 01 10:56:42 AM PDT 24
Peak memory 191208 kb
Host smart-63f20f6e-3f98-4f38-942b-d20824ceb4f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983007519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2983007519
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.363246937
Short name T154
Test name
Test status
Simulation time 216481068767 ps
CPU time 346.71 seconds
Started Jul 01 10:53:48 AM PDT 24
Finished Jul 01 10:59:35 AM PDT 24
Peak memory 191256 kb
Host smart-f79fbc03-8b46-43f2-946c-d2a506386935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363246937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.363246937
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.4041265312
Short name T118
Test name
Test status
Simulation time 328469522052 ps
CPU time 1619.29 seconds
Started Jul 01 10:53:51 AM PDT 24
Finished Jul 01 11:20:51 AM PDT 24
Peak memory 191268 kb
Host smart-67401c21-75c1-4b1a-97df-b9e1a957c261
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041265312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4041265312
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2464219558
Short name T243
Test name
Test status
Simulation time 140464587792 ps
CPU time 236.28 seconds
Started Jul 01 10:52:53 AM PDT 24
Finished Jul 01 10:56:54 AM PDT 24
Peak memory 183076 kb
Host smart-24af1df6-a240-4d8f-acd0-82ce07e4825b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464219558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2464219558
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2694578495
Short name T399
Test name
Test status
Simulation time 466998005359 ps
CPU time 234.94 seconds
Started Jul 01 10:52:41 AM PDT 24
Finished Jul 01 10:56:39 AM PDT 24
Peak memory 183076 kb
Host smart-da72f089-d22c-44c6-8334-9b564e711163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694578495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2694578495
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1255411231
Short name T266
Test name
Test status
Simulation time 115966781624 ps
CPU time 95.96 seconds
Started Jul 01 10:52:42 AM PDT 24
Finished Jul 01 10:54:22 AM PDT 24
Peak memory 191188 kb
Host smart-0a58aa9c-08b9-4395-b25d-cecb9fc47367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255411231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1255411231
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1469283924
Short name T253
Test name
Test status
Simulation time 51245735163 ps
CPU time 195.3 seconds
Started Jul 01 10:52:52 AM PDT 24
Finished Jul 01 10:56:12 AM PDT 24
Peak memory 191304 kb
Host smart-38c1d20d-84af-4b1a-827f-805015e93c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469283924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1469283924
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3908392433
Short name T137
Test name
Test status
Simulation time 22280255220 ps
CPU time 159.58 seconds
Started Jul 01 10:53:50 AM PDT 24
Finished Jul 01 10:56:30 AM PDT 24
Peak memory 191192 kb
Host smart-854fd469-8243-4481-91c4-a7581d98c0db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908392433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3908392433
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1376308921
Short name T296
Test name
Test status
Simulation time 76669489303 ps
CPU time 151.63 seconds
Started Jul 01 10:53:58 AM PDT 24
Finished Jul 01 10:56:30 AM PDT 24
Peak memory 192736 kb
Host smart-13310621-c2b1-4dc3-a232-307b35638720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376308921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1376308921
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1945985498
Short name T147
Test name
Test status
Simulation time 144672736518 ps
CPU time 248.16 seconds
Started Jul 01 10:53:50 AM PDT 24
Finished Jul 01 10:57:58 AM PDT 24
Peak memory 194556 kb
Host smart-47b190de-e255-4cb8-b798-f49bf890027a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945985498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1945985498
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.655917030
Short name T22
Test name
Test status
Simulation time 236594580583 ps
CPU time 387.35 seconds
Started Jul 01 10:53:50 AM PDT 24
Finished Jul 01 11:00:17 AM PDT 24
Peak memory 191324 kb
Host smart-62f2ca90-e948-4170-9d80-f840b82f0904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655917030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.655917030
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2973549173
Short name T311
Test name
Test status
Simulation time 712479150725 ps
CPU time 306.99 seconds
Started Jul 01 10:53:50 AM PDT 24
Finished Jul 01 10:58:58 AM PDT 24
Peak memory 191324 kb
Host smart-8e1bed5f-9cb9-4d01-b9e0-b63996661305
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973549173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2973549173
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3095620226
Short name T122
Test name
Test status
Simulation time 252182888007 ps
CPU time 351.83 seconds
Started Jul 01 10:53:55 AM PDT 24
Finished Jul 01 10:59:47 AM PDT 24
Peak memory 191268 kb
Host smart-d44f761a-ccb8-41ae-9e25-f688272d1ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095620226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3095620226
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.768910697
Short name T170
Test name
Test status
Simulation time 618006342670 ps
CPU time 532.05 seconds
Started Jul 01 10:53:55 AM PDT 24
Finished Jul 01 11:02:48 AM PDT 24
Peak memory 191324 kb
Host smart-f25f49bc-076d-4a4c-90ce-8f4eea4163ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768910697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.768910697
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.395367625
Short name T342
Test name
Test status
Simulation time 81501112736 ps
CPU time 135.82 seconds
Started Jul 01 10:54:00 AM PDT 24
Finished Jul 01 10:56:17 AM PDT 24
Peak memory 191308 kb
Host smart-dea04f94-75a0-4ca5-8708-9f9cccdce382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395367625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.395367625
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.4048463512
Short name T254
Test name
Test status
Simulation time 375323976809 ps
CPU time 661.5 seconds
Started Jul 01 10:53:00 AM PDT 24
Finished Jul 01 11:04:05 AM PDT 24
Peak memory 182988 kb
Host smart-31718bcf-a4c7-4d59-8554-a94c62966303
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048463512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.4048463512
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2276111897
Short name T400
Test name
Test status
Simulation time 115398797050 ps
CPU time 45.92 seconds
Started Jul 01 10:52:51 AM PDT 24
Finished Jul 01 10:53:41 AM PDT 24
Peak memory 183116 kb
Host smart-cef51cdd-0172-4038-bc84-6ed027ea134f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276111897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2276111897
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3448847271
Short name T106
Test name
Test status
Simulation time 71412565414 ps
CPU time 116.95 seconds
Started Jul 01 10:52:45 AM PDT 24
Finished Jul 01 10:54:46 AM PDT 24
Peak memory 191308 kb
Host smart-b95c456f-c147-4832-8b86-08ccf4e6b9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448847271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3448847271
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1914571347
Short name T165
Test name
Test status
Simulation time 73325283872 ps
CPU time 118.32 seconds
Started Jul 01 10:52:55 AM PDT 24
Finished Jul 01 10:54:58 AM PDT 24
Peak memory 183108 kb
Host smart-9ecd97d3-ab57-4805-9089-8c17df6ea023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914571347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1914571347
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.821888505
Short name T288
Test name
Test status
Simulation time 473601236112 ps
CPU time 215.9 seconds
Started Jul 01 10:52:51 AM PDT 24
Finished Jul 01 10:56:32 AM PDT 24
Peak memory 195364 kb
Host smart-8dba52bf-e489-4cd3-894d-0a0f8b9f17ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821888505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.821888505
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.434324946
Short name T12
Test name
Test status
Simulation time 28810774127 ps
CPU time 310.8 seconds
Started Jul 01 10:52:46 AM PDT 24
Finished Jul 01 10:58:00 AM PDT 24
Peak memory 197764 kb
Host smart-1e3392e6-934f-4c96-9df1-b913f4aa7cf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434324946 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.434324946
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.3528203348
Short name T351
Test name
Test status
Simulation time 119361730757 ps
CPU time 191.56 seconds
Started Jul 01 10:54:01 AM PDT 24
Finished Jul 01 10:57:13 AM PDT 24
Peak memory 191244 kb
Host smart-89c0b439-e936-4f59-97f0-44b19aac6ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528203348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3528203348
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1714187193
Short name T156
Test name
Test status
Simulation time 65731443258 ps
CPU time 1131.54 seconds
Started Jul 01 10:54:02 AM PDT 24
Finished Jul 01 11:12:54 AM PDT 24
Peak memory 191284 kb
Host smart-387706c9-09bc-41df-85e1-e57083222a43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714187193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1714187193
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3641314671
Short name T18
Test name
Test status
Simulation time 27220283161 ps
CPU time 44.07 seconds
Started Jul 01 10:54:00 AM PDT 24
Finished Jul 01 10:54:45 AM PDT 24
Peak memory 183128 kb
Host smart-ec00dd32-6c8a-47dc-9156-87bfab28b0e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641314671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3641314671
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2146791772
Short name T319
Test name
Test status
Simulation time 644539260136 ps
CPU time 862.88 seconds
Started Jul 01 10:54:01 AM PDT 24
Finished Jul 01 11:08:24 AM PDT 24
Peak memory 191276 kb
Host smart-8ce3b195-b413-4dc8-b89e-e32bdcb0c4b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146791772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2146791772
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3417684845
Short name T240
Test name
Test status
Simulation time 60786737355 ps
CPU time 50.86 seconds
Started Jul 01 10:54:05 AM PDT 24
Finished Jul 01 10:54:56 AM PDT 24
Peak memory 183116 kb
Host smart-eb20187e-7bb5-480e-9b98-f1deda3a1696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417684845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3417684845
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.715152819
Short name T197
Test name
Test status
Simulation time 5185433662 ps
CPU time 2.42 seconds
Started Jul 01 10:54:02 AM PDT 24
Finished Jul 01 10:54:05 AM PDT 24
Peak memory 182980 kb
Host smart-9bf04b46-cd5c-4974-9319-854a7b9495f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715152819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.715152819
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2845401174
Short name T188
Test name
Test status
Simulation time 192105733510 ps
CPU time 160.21 seconds
Started Jul 01 10:54:03 AM PDT 24
Finished Jul 01 10:56:44 AM PDT 24
Peak memory 191304 kb
Host smart-3816119d-d015-45d3-bc85-7a9999de2289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845401174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2845401174
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.4113302087
Short name T216
Test name
Test status
Simulation time 163520244495 ps
CPU time 236.91 seconds
Started Jul 01 10:54:03 AM PDT 24
Finished Jul 01 10:58:00 AM PDT 24
Peak memory 192332 kb
Host smart-ea630ff7-5498-4e66-8536-8f6e6f13d160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113302087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.4113302087
Directory /workspace/99.rv_timer_random/latest
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