Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 586
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T506 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1251279535 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:04 PM PDT 24 25655980 ps
T507 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.757707956 Jul 01 04:28:41 PM PDT 24 Jul 01 04:28:50 PM PDT 24 57805219 ps
T508 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3242191310 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:04 PM PDT 24 75545393 ps
T509 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1604557103 Jul 01 04:28:44 PM PDT 24 Jul 01 04:28:56 PM PDT 24 22798068 ps
T510 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1492154573 Jul 01 04:29:03 PM PDT 24 Jul 01 04:29:15 PM PDT 24 41832230 ps
T511 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1610792997 Jul 01 04:28:36 PM PDT 24 Jul 01 04:28:45 PM PDT 24 185437396 ps
T512 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3079816043 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:04 PM PDT 24 188003827 ps
T513 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3257433044 Jul 01 04:29:00 PM PDT 24 Jul 01 04:29:13 PM PDT 24 13231634 ps
T514 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.726382139 Jul 01 04:28:40 PM PDT 24 Jul 01 04:28:49 PM PDT 24 43269452 ps
T515 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.163471538 Jul 01 04:28:57 PM PDT 24 Jul 01 04:29:12 PM PDT 24 12914888 ps
T516 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3362568632 Jul 01 04:28:51 PM PDT 24 Jul 01 04:29:07 PM PDT 24 130623049 ps
T91 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2586136362 Jul 01 04:28:46 PM PDT 24 Jul 01 04:28:59 PM PDT 24 28542427 ps
T517 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2580258568 Jul 01 04:28:50 PM PDT 24 Jul 01 04:29:05 PM PDT 24 46766327 ps
T518 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2931889519 Jul 01 04:28:45 PM PDT 24 Jul 01 04:28:57 PM PDT 24 21442766 ps
T519 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2189100713 Jul 01 04:28:33 PM PDT 24 Jul 01 04:28:39 PM PDT 24 44451948 ps
T520 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.638545130 Jul 01 04:28:55 PM PDT 24 Jul 01 04:29:10 PM PDT 24 46976545 ps
T92 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1229356662 Jul 01 04:28:44 PM PDT 24 Jul 01 04:28:55 PM PDT 24 18482990 ps
T521 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3936369587 Jul 01 04:28:53 PM PDT 24 Jul 01 04:29:08 PM PDT 24 37722601 ps
T522 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2907706749 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:04 PM PDT 24 56780673 ps
T523 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3434145800 Jul 01 04:28:46 PM PDT 24 Jul 01 04:29:00 PM PDT 24 41570802 ps
T524 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1569155270 Jul 01 04:28:52 PM PDT 24 Jul 01 04:29:07 PM PDT 24 23340774 ps
T525 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2545026550 Jul 01 04:28:50 PM PDT 24 Jul 01 04:29:04 PM PDT 24 49486715 ps
T93 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.692462753 Jul 01 04:28:44 PM PDT 24 Jul 01 04:28:56 PM PDT 24 140722493 ps
T94 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.714783596 Jul 01 04:28:42 PM PDT 24 Jul 01 04:28:51 PM PDT 24 15714594 ps
T526 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1211559890 Jul 01 04:28:51 PM PDT 24 Jul 01 04:29:07 PM PDT 24 331126754 ps
T527 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1725876359 Jul 01 04:28:53 PM PDT 24 Jul 01 04:29:08 PM PDT 24 228868367 ps
T528 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3551821168 Jul 01 04:28:50 PM PDT 24 Jul 01 04:29:06 PM PDT 24 185589154 ps
T529 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2774295979 Jul 01 04:28:52 PM PDT 24 Jul 01 04:29:07 PM PDT 24 34701053 ps
T530 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1183734776 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:03 PM PDT 24 17516452 ps
T531 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2911399020 Jul 01 04:28:50 PM PDT 24 Jul 01 04:29:07 PM PDT 24 279526335 ps
T532 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2467172465 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:00 PM PDT 24 30535966 ps
T533 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3832759084 Jul 01 04:28:38 PM PDT 24 Jul 01 04:28:45 PM PDT 24 90950083 ps
T534 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1736637856 Jul 01 04:28:52 PM PDT 24 Jul 01 04:29:07 PM PDT 24 14652337 ps
T535 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1985707597 Jul 01 04:29:01 PM PDT 24 Jul 01 04:29:15 PM PDT 24 34603954 ps
T536 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2489219818 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:01 PM PDT 24 224199118 ps
T537 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.308025803 Jul 01 04:28:59 PM PDT 24 Jul 01 04:29:13 PM PDT 24 12517105 ps
T538 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.546432271 Jul 01 04:28:54 PM PDT 24 Jul 01 04:29:09 PM PDT 24 22995529 ps
T539 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4191689198 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:03 PM PDT 24 40250960 ps
T540 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1484085215 Jul 01 04:28:55 PM PDT 24 Jul 01 04:29:11 PM PDT 24 31420601 ps
T541 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.964576524 Jul 01 04:28:41 PM PDT 24 Jul 01 04:28:49 PM PDT 24 214329850 ps
T542 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.759737548 Jul 01 04:28:42 PM PDT 24 Jul 01 04:28:51 PM PDT 24 37367105 ps
T95 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2745047082 Jul 01 04:28:50 PM PDT 24 Jul 01 04:29:05 PM PDT 24 46920173 ps
T543 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1127223477 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:03 PM PDT 24 31665033 ps
T544 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3422383742 Jul 01 04:28:46 PM PDT 24 Jul 01 04:28:59 PM PDT 24 43920053 ps
T545 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2178155690 Jul 01 04:28:44 PM PDT 24 Jul 01 04:28:55 PM PDT 24 93339990 ps
T546 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.670530587 Jul 01 04:28:43 PM PDT 24 Jul 01 04:28:55 PM PDT 24 2795659519 ps
T547 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1619022824 Jul 01 04:29:01 PM PDT 24 Jul 01 04:29:15 PM PDT 24 53917827 ps
T548 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1247499324 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:00 PM PDT 24 56892347 ps
T549 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3788267038 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:00 PM PDT 24 12917468 ps
T550 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1838780890 Jul 01 04:28:44 PM PDT 24 Jul 01 04:28:55 PM PDT 24 14402135 ps
T551 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.775080795 Jul 01 04:28:53 PM PDT 24 Jul 01 04:29:08 PM PDT 24 103701079 ps
T552 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4080887892 Jul 01 04:28:44 PM PDT 24 Jul 01 04:28:55 PM PDT 24 515678974 ps
T553 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2440261990 Jul 01 04:28:52 PM PDT 24 Jul 01 04:29:06 PM PDT 24 26827565 ps
T554 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1569744367 Jul 01 04:28:42 PM PDT 24 Jul 01 04:28:52 PM PDT 24 152813553 ps
T555 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.55496274 Jul 01 04:28:45 PM PDT 24 Jul 01 04:28:57 PM PDT 24 32059002 ps
T556 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4126550632 Jul 01 04:29:00 PM PDT 24 Jul 01 04:29:13 PM PDT 24 42948034 ps
T557 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1721547442 Jul 01 04:28:36 PM PDT 24 Jul 01 04:28:42 PM PDT 24 34515044 ps
T558 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3709514177 Jul 01 04:28:41 PM PDT 24 Jul 01 04:28:50 PM PDT 24 25711465 ps
T559 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3807096171 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:00 PM PDT 24 79013646 ps
T560 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2528457064 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:01 PM PDT 24 53782042 ps
T561 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3923604604 Jul 01 04:29:00 PM PDT 24 Jul 01 04:29:14 PM PDT 24 168417744 ps
T562 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2359364332 Jul 01 04:28:50 PM PDT 24 Jul 01 04:29:04 PM PDT 24 29995931 ps
T563 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4126905507 Jul 01 04:28:45 PM PDT 24 Jul 01 04:28:58 PM PDT 24 329633888 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3834915017 Jul 01 04:28:55 PM PDT 24 Jul 01 04:29:11 PM PDT 24 44153773 ps
T565 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2790542121 Jul 01 04:29:00 PM PDT 24 Jul 01 04:29:14 PM PDT 24 84661735 ps
T566 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.433688872 Jul 01 04:29:00 PM PDT 24 Jul 01 04:29:13 PM PDT 24 24027553 ps
T567 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3350466530 Jul 01 04:28:52 PM PDT 24 Jul 01 04:29:07 PM PDT 24 36811365 ps
T568 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3832921449 Jul 01 04:28:42 PM PDT 24 Jul 01 04:28:50 PM PDT 24 36262437 ps
T569 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1659842163 Jul 01 04:28:48 PM PDT 24 Jul 01 04:29:01 PM PDT 24 33611588 ps
T570 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2104849531 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:03 PM PDT 24 78178003 ps
T571 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3924030257 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:00 PM PDT 24 30569584 ps
T572 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3987403453 Jul 01 04:28:47 PM PDT 24 Jul 01 04:29:00 PM PDT 24 177142678 ps
T573 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1152837355 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:03 PM PDT 24 50996225 ps
T574 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3044154181 Jul 01 04:28:43 PM PDT 24 Jul 01 04:28:55 PM PDT 24 50338982 ps
T575 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.40963143 Jul 01 04:28:52 PM PDT 24 Jul 01 04:29:07 PM PDT 24 44270417 ps
T576 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2085316813 Jul 01 04:28:55 PM PDT 24 Jul 01 04:29:09 PM PDT 24 48054104 ps
T577 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3462426793 Jul 01 04:28:31 PM PDT 24 Jul 01 04:28:37 PM PDT 24 113708641 ps
T578 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.397739501 Jul 01 04:28:46 PM PDT 24 Jul 01 04:29:00 PM PDT 24 111297153 ps
T579 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1488765327 Jul 01 04:29:07 PM PDT 24 Jul 01 04:29:18 PM PDT 24 57737013 ps
T580 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2026922988 Jul 01 04:28:39 PM PDT 24 Jul 01 04:28:47 PM PDT 24 14412419 ps
T581 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2907066146 Jul 01 04:28:54 PM PDT 24 Jul 01 04:29:08 PM PDT 24 14579515 ps
T582 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2903494953 Jul 01 04:28:37 PM PDT 24 Jul 01 04:28:45 PM PDT 24 36474463 ps
T583 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3099644552 Jul 01 04:28:56 PM PDT 24 Jul 01 04:29:11 PM PDT 24 11772011 ps
T584 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1618045372 Jul 01 04:28:56 PM PDT 24 Jul 01 04:29:11 PM PDT 24 12695363 ps
T585 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.764061092 Jul 01 04:28:49 PM PDT 24 Jul 01 04:29:04 PM PDT 24 16334583 ps
T586 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1379166713 Jul 01 04:28:41 PM PDT 24 Jul 01 04:28:49 PM PDT 24 101441014 ps

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.1550201551
Short name T4
Test name
Test status
Simulation time 226795780012 ps
CPU time 714.17 seconds
Started Jul 01 04:36:33 PM PDT 24
Finished Jul 01 04:48:33 PM PDT 24
Peak memory 209536 kb
Host smart-35cf2872-e6ec-4070-93cc-9a730f474cd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550201551 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.1550201551
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2754922365
Short name T3
Test name
Test status
Simulation time 218452388414 ps
CPU time 545.49 seconds
Started Jul 01 04:36:15 PM PDT 24
Finished Jul 01 04:45:35 PM PDT 24
Peak memory 191396 kb
Host smart-9720a097-6a34-4c29-9f62-d9bdb2adedc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754922365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2754922365
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1226702339
Short name T33
Test name
Test status
Simulation time 876209602310 ps
CPU time 1713.07 seconds
Started Jul 01 04:36:48 PM PDT 24
Finished Jul 01 05:05:26 PM PDT 24
Peak memory 191284 kb
Host smart-75f9a428-a2ac-4031-8f12-1d1649ab7080
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226702339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1226702339
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.826027440
Short name T174
Test name
Test status
Simulation time 5543521928674 ps
CPU time 2254.45 seconds
Started Jul 01 04:36:32 PM PDT 24
Finished Jul 01 05:14:13 PM PDT 24
Peak memory 191296 kb
Host smart-d650a83a-5936-4873-ab26-389872ed0dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826027440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
826027440
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3828885731
Short name T28
Test name
Test status
Simulation time 89248976 ps
CPU time 0.88 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 193308 kb
Host smart-6eeeb113-6901-411b-b222-e8eba5dd676c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828885731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3828885731
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.878917367
Short name T73
Test name
Test status
Simulation time 21632782 ps
CPU time 0.55 seconds
Started Jul 01 04:28:45 PM PDT 24
Finished Jul 01 04:28:57 PM PDT 24
Peak memory 182168 kb
Host smart-3f0f88f7-9d12-49c8-90ee-9954fd61dd63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878917367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.878917367
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3272577688
Short name T129
Test name
Test status
Simulation time 992849419309 ps
CPU time 1734.49 seconds
Started Jul 01 04:36:53 PM PDT 24
Finished Jul 01 05:05:52 PM PDT 24
Peak memory 196136 kb
Host smart-0cfd2462-c74a-4a3e-b66a-6b391c52c484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272577688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3272577688
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.274278289
Short name T67
Test name
Test status
Simulation time 756171161333 ps
CPU time 1467.5 seconds
Started Jul 01 04:36:58 PM PDT 24
Finished Jul 01 05:01:29 PM PDT 24
Peak memory 191196 kb
Host smart-e31c86c0-aa1d-45fe-8859-b1a8c6d3e5d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274278289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
274278289
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.650698790
Short name T150
Test name
Test status
Simulation time 2873914952121 ps
CPU time 2202.59 seconds
Started Jul 01 04:36:30 PM PDT 24
Finished Jul 01 05:13:20 PM PDT 24
Peak memory 191188 kb
Host smart-1b3e6a02-5ea7-4ea1-9853-042b4ffc68c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650698790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
650698790
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.4150337439
Short name T118
Test name
Test status
Simulation time 1798184744265 ps
CPU time 2463.55 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 05:17:35 PM PDT 24
Peak memory 191288 kb
Host smart-442f4e4d-d8fe-4670-8b0e-ea6f41ed7925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150337439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.4150337439
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2887483070
Short name T54
Test name
Test status
Simulation time 267562694400 ps
CPU time 1133.52 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:55:25 PM PDT 24
Peak memory 191288 kb
Host smart-0bdc6185-0ee9-4f60-949e-7d297ebfe73f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887483070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2887483070
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2603124140
Short name T164
Test name
Test status
Simulation time 691501492996 ps
CPU time 2736.64 seconds
Started Jul 01 04:36:24 PM PDT 24
Finished Jul 01 05:22:12 PM PDT 24
Peak memory 191352 kb
Host smart-fd2f06f9-887b-431f-8d57-6c87c14bb411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603124140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2603124140
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2184674654
Short name T173
Test name
Test status
Simulation time 1749369854531 ps
CPU time 1450.27 seconds
Started Jul 01 04:36:43 PM PDT 24
Finished Jul 01 05:00:57 PM PDT 24
Peak memory 195820 kb
Host smart-bc018aa5-5f9e-4f5b-b0b3-ca9165e81c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184674654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2184674654
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.715799559
Short name T14
Test name
Test status
Simulation time 225086558 ps
CPU time 0.83 seconds
Started Jul 01 04:36:11 PM PDT 24
Finished Jul 01 04:36:27 PM PDT 24
Peak memory 213340 kb
Host smart-a2e84175-e55e-4fbd-b66b-17073a4cf93e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715799559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.715799559
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/48.rv_timer_random.1659687355
Short name T9
Test name
Test status
Simulation time 86392769088 ps
CPU time 132.05 seconds
Started Jul 01 04:36:53 PM PDT 24
Finished Jul 01 04:39:10 PM PDT 24
Peak memory 183092 kb
Host smart-8ca459f4-1794-4945-b785-b181cd49156d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659687355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1659687355
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1131934578
Short name T160
Test name
Test status
Simulation time 290758855511 ps
CPU time 1503.65 seconds
Started Jul 01 04:37:19 PM PDT 24
Finished Jul 01 05:02:25 PM PDT 24
Peak memory 191288 kb
Host smart-86b265d6-791b-47f7-8bfc-29ae02b5999f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131934578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1131934578
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.775006241
Short name T185
Test name
Test status
Simulation time 1103443514391 ps
CPU time 1465.01 seconds
Started Jul 01 04:36:40 PM PDT 24
Finished Jul 01 05:01:09 PM PDT 24
Peak memory 196580 kb
Host smart-0bec10f6-72cf-4c9d-884d-65beac851a58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775006241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
775006241
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3654353608
Short name T148
Test name
Test status
Simulation time 3140236728106 ps
CPU time 2394.1 seconds
Started Jul 01 04:36:58 PM PDT 24
Finished Jul 01 05:16:56 PM PDT 24
Peak memory 191408 kb
Host smart-40688f33-b253-44c9-9930-3412ba2007b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654353608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3654353608
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random.2969707419
Short name T24
Test name
Test status
Simulation time 168308956296 ps
CPU time 268.05 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:41:18 PM PDT 24
Peak memory 191276 kb
Host smart-d234bb52-9dd8-42a6-841f-ccd595cbb306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969707419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2969707419
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3504777360
Short name T222
Test name
Test status
Simulation time 472310298032 ps
CPU time 1549.38 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 05:02:31 PM PDT 24
Peak memory 191272 kb
Host smart-e6f04a4e-1d15-4414-b27d-d5197a2e3a91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504777360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3504777360
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1753144667
Short name T62
Test name
Test status
Simulation time 580531259623 ps
CPU time 1126.18 seconds
Started Jul 01 04:36:43 PM PDT 24
Finished Jul 01 04:55:33 PM PDT 24
Peak memory 191152 kb
Host smart-e2ae7239-b284-4b00-a5dc-3bc7eed822dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753144667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1753144667
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_random.2135093248
Short name T166
Test name
Test status
Simulation time 187840991668 ps
CPU time 1100.84 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:55:12 PM PDT 24
Peak memory 191412 kb
Host smart-e0644047-0784-4bc9-a576-b3d633b1c419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135093248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2135093248
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2009180912
Short name T269
Test name
Test status
Simulation time 1969465285917 ps
CPU time 1010.69 seconds
Started Jul 01 04:36:10 PM PDT 24
Finished Jul 01 04:53:16 PM PDT 24
Peak memory 196180 kb
Host smart-cc9ebf75-a9db-4b92-9055-6c1a8dfe8909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009180912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2009180912
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1016721985
Short name T259
Test name
Test status
Simulation time 2038304775030 ps
CPU time 3900.79 seconds
Started Jul 01 04:36:47 PM PDT 24
Finished Jul 01 05:41:53 PM PDT 24
Peak memory 194800 kb
Host smart-528c95ae-8c49-4698-b4e1-26949b232ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016721985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1016721985
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/118.rv_timer_random.3554000842
Short name T153
Test name
Test status
Simulation time 171232012941 ps
CPU time 1025.71 seconds
Started Jul 01 04:37:10 PM PDT 24
Finished Jul 01 04:54:19 PM PDT 24
Peak memory 194168 kb
Host smart-f562d3f2-6a9e-45e9-b8d0-8fdbf195328e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554000842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3554000842
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3011843291
Short name T215
Test name
Test status
Simulation time 341948194234 ps
CPU time 471.18 seconds
Started Jul 01 04:36:33 PM PDT 24
Finished Jul 01 04:44:30 PM PDT 24
Peak memory 194868 kb
Host smart-2ed776a7-fe8f-412d-8856-ec9d2bfec14e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011843291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3011843291
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.1645825829
Short name T219
Test name
Test status
Simulation time 1925190193957 ps
CPU time 555.84 seconds
Started Jul 01 04:37:14 PM PDT 24
Finished Jul 01 04:46:32 PM PDT 24
Peak memory 191280 kb
Host smart-9ea7426a-293b-4692-8093-4cecec3d7c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645825829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1645825829
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random.1478573696
Short name T152
Test name
Test status
Simulation time 870847242513 ps
CPU time 396.51 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:43:39 PM PDT 24
Peak memory 191292 kb
Host smart-334e0d6e-86a3-411d-913c-3d6126b9faab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478573696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1478573696
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3062657875
Short name T57
Test name
Test status
Simulation time 1736845561946 ps
CPU time 508.58 seconds
Started Jul 01 04:37:19 PM PDT 24
Finished Jul 01 04:45:49 PM PDT 24
Peak memory 191280 kb
Host smart-5406cb2d-0694-435d-82c7-2c90ba00a27d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062657875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3062657875
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4240526495
Short name T184
Test name
Test status
Simulation time 200604436124 ps
CPU time 794.27 seconds
Started Jul 01 04:37:30 PM PDT 24
Finished Jul 01 04:50:46 PM PDT 24
Peak memory 191288 kb
Host smart-f6bb214a-c5fb-4054-8c7b-6c75be4f0666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240526495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4240526495
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3550034544
Short name T220
Test name
Test status
Simulation time 188693326411 ps
CPU time 515.78 seconds
Started Jul 01 04:37:30 PM PDT 24
Finished Jul 01 04:46:07 PM PDT 24
Peak memory 191288 kb
Host smart-113f49df-d0f7-41fb-9fdb-2d14a2a4d9a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550034544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3550034544
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.426760314
Short name T265
Test name
Test status
Simulation time 294873503161 ps
CPU time 162.34 seconds
Started Jul 01 04:37:40 PM PDT 24
Finished Jul 01 04:40:23 PM PDT 24
Peak memory 191284 kb
Host smart-458543df-0955-45e3-abba-ece3fcc4b17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426760314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.426760314
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2002590246
Short name T124
Test name
Test status
Simulation time 1429425722584 ps
CPU time 897.82 seconds
Started Jul 01 04:36:52 PM PDT 24
Finished Jul 01 04:51:55 PM PDT 24
Peak memory 182976 kb
Host smart-fbe3ec9e-eb4c-4a04-9820-a58ab408921f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002590246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2002590246
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/58.rv_timer_random.1288027670
Short name T328
Test name
Test status
Simulation time 312002438988 ps
CPU time 272.46 seconds
Started Jul 01 04:36:52 PM PDT 24
Finished Jul 01 04:41:30 PM PDT 24
Peak memory 194816 kb
Host smart-ebf6dab4-c517-45a6-8dff-f228be07dac3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288027670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1288027670
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1131490741
Short name T191
Test name
Test status
Simulation time 3288615791719 ps
CPU time 2103.6 seconds
Started Jul 01 04:36:15 PM PDT 24
Finished Jul 01 05:11:33 PM PDT 24
Peak memory 191188 kb
Host smart-0fb47e68-7dab-4f0f-b0cf-08bfa3a07087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131490741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1131490741
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/113.rv_timer_random.2285224249
Short name T203
Test name
Test status
Simulation time 206716962355 ps
CPU time 534.53 seconds
Started Jul 01 04:37:09 PM PDT 24
Finished Jul 01 04:46:06 PM PDT 24
Peak memory 193412 kb
Host smart-04777675-ab03-480c-b968-de121cec8f26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285224249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2285224249
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2154589602
Short name T300
Test name
Test status
Simulation time 351813645816 ps
CPU time 1079.44 seconds
Started Jul 01 04:36:22 PM PDT 24
Finished Jul 01 04:54:34 PM PDT 24
Peak memory 191420 kb
Host smart-c6405544-4564-458e-b7fe-9418fc079bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154589602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2154589602
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.963759854
Short name T51
Test name
Test status
Simulation time 129187536987 ps
CPU time 290.87 seconds
Started Jul 01 04:37:06 PM PDT 24
Finished Jul 01 04:41:58 PM PDT 24
Peak memory 191196 kb
Host smart-66d8f413-fe94-4444-abb7-a1fbc332d4de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963759854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.963759854
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2364962753
Short name T316
Test name
Test status
Simulation time 452331704469 ps
CPU time 705.21 seconds
Started Jul 01 04:37:17 PM PDT 24
Finished Jul 01 04:49:04 PM PDT 24
Peak memory 191284 kb
Host smart-a77c9920-52a6-4b80-b129-dec5c1ecbf41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364962753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2364962753
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.4178990842
Short name T41
Test name
Test status
Simulation time 236746312613 ps
CPU time 435.68 seconds
Started Jul 01 04:36:27 PM PDT 24
Finished Jul 01 04:43:52 PM PDT 24
Peak memory 183228 kb
Host smart-ff1220a9-2e9e-4ee1-aa69-c6eaebf51d44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178990842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.4178990842
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3647357608
Short name T135
Test name
Test status
Simulation time 646848483324 ps
CPU time 976.41 seconds
Started Jul 01 04:36:47 PM PDT 24
Finished Jul 01 04:53:08 PM PDT 24
Peak memory 191288 kb
Host smart-1a1f0b71-df82-4a06-9597-a5b7d447def9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647357608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3647357608
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2173549117
Short name T21
Test name
Test status
Simulation time 1300802958657 ps
CPU time 1032.43 seconds
Started Jul 01 04:36:58 PM PDT 24
Finished Jul 01 04:54:14 PM PDT 24
Peak memory 191188 kb
Host smart-5940f335-65b3-402d-8a9c-1d49a98b6758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173549117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2173549117
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/85.rv_timer_random.425316710
Short name T284
Test name
Test status
Simulation time 343781630900 ps
CPU time 1073.76 seconds
Started Jul 01 04:37:01 PM PDT 24
Finished Jul 01 04:54:58 PM PDT 24
Peak memory 191276 kb
Host smart-dce9b342-52ee-43f0-ac48-bfd559ee3b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425316710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.425316710
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/90.rv_timer_random.2443737942
Short name T178
Test name
Test status
Simulation time 170855961740 ps
CPU time 385.08 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:43:27 PM PDT 24
Peak memory 191264 kb
Host smart-1233780d-1f77-4ff3-8db4-06a4c103f735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443737942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2443737942
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1276216920
Short name T109
Test name
Test status
Simulation time 161967794565 ps
CPU time 364.8 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 04:43:09 PM PDT 24
Peak memory 191284 kb
Host smart-55712b8d-bfa5-43ce-a43e-8b62158cb182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276216920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1276216920
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4075450422
Short name T192
Test name
Test status
Simulation time 348675420569 ps
CPU time 301.58 seconds
Started Jul 01 04:37:08 PM PDT 24
Finished Jul 01 04:42:12 PM PDT 24
Peak memory 191292 kb
Host smart-e28201f9-8ba2-466b-95ee-f3198fa03ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075450422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4075450422
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.740989531
Short name T228
Test name
Test status
Simulation time 97860124877 ps
CPU time 150.1 seconds
Started Jul 01 04:37:06 PM PDT 24
Finished Jul 01 04:39:38 PM PDT 24
Peak memory 191196 kb
Host smart-2a6efbba-037e-4b0b-a1e6-b3eaa51104e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740989531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.740989531
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.245068936
Short name T260
Test name
Test status
Simulation time 130504435253 ps
CPU time 375.69 seconds
Started Jul 01 04:36:28 PM PDT 24
Finished Jul 01 04:42:52 PM PDT 24
Peak memory 193468 kb
Host smart-ee8c30d0-a2e0-48e8-bd36-370d9cd7b184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245068936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.245068936
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1117775420
Short name T275
Test name
Test status
Simulation time 91403921879 ps
CPU time 1873.74 seconds
Started Jul 01 04:37:40 PM PDT 24
Finished Jul 01 05:08:55 PM PDT 24
Peak memory 191288 kb
Host smart-b64aa98b-d866-4980-9d60-a1f65398ee26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117775420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1117775420
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random.1177407574
Short name T324
Test name
Test status
Simulation time 148259284021 ps
CPU time 247.88 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:40:50 PM PDT 24
Peak memory 191372 kb
Host smart-ebb39e98-3ad7-44b2-a557-760cacf8cc1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177407574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1177407574
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2652243638
Short name T138
Test name
Test status
Simulation time 504607433344 ps
CPU time 1614.5 seconds
Started Jul 01 04:36:51 PM PDT 24
Finished Jul 01 05:03:51 PM PDT 24
Peak memory 191132 kb
Host smart-75a9697f-6106-4625-967a-dfca9f826afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652243638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2652243638
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2020530949
Short name T137
Test name
Test status
Simulation time 489898998996 ps
CPU time 1216.95 seconds
Started Jul 01 04:36:49 PM PDT 24
Finished Jul 01 04:57:11 PM PDT 24
Peak memory 190940 kb
Host smart-82156f61-5fc3-4f90-960c-c1a35444b95c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020530949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2020530949
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/52.rv_timer_random.2323861714
Short name T121
Test name
Test status
Simulation time 603914819323 ps
CPU time 332.67 seconds
Started Jul 01 04:36:57 PM PDT 24
Finished Jul 01 04:42:34 PM PDT 24
Peak memory 191336 kb
Host smart-2a3266ab-ae50-4b62-8934-d30d08303723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323861714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2323861714
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.2826367908
Short name T262
Test name
Test status
Simulation time 304849597656 ps
CPU time 845.74 seconds
Started Jul 01 04:36:56 PM PDT 24
Finished Jul 01 04:51:06 PM PDT 24
Peak memory 191284 kb
Host smart-1e731639-4995-4fe5-9f2d-e8d1690f4cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826367908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2826367908
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1990132880
Short name T101
Test name
Test status
Simulation time 17545954 ps
CPU time 0.55 seconds
Started Jul 01 04:28:39 PM PDT 24
Finished Jul 01 04:28:46 PM PDT 24
Peak memory 182168 kb
Host smart-96ca33e7-8c4c-407e-8f4b-be6435153842
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990132880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1990132880
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/106.rv_timer_random.2576346285
Short name T143
Test name
Test status
Simulation time 127830322443 ps
CPU time 63.84 seconds
Started Jul 01 04:37:01 PM PDT 24
Finished Jul 01 04:38:08 PM PDT 24
Peak memory 194800 kb
Host smart-53459c6c-2eb2-4fe8-a184-6881710e1368
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576346285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2576346285
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.3127124091
Short name T233
Test name
Test status
Simulation time 436461540030 ps
CPU time 465.48 seconds
Started Jul 01 04:36:20 PM PDT 24
Finished Jul 01 04:44:18 PM PDT 24
Peak memory 191284 kb
Host smart-faadda83-8941-463f-adc0-6e18d5b00ae4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127124091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3127124091
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1497189447
Short name T50
Test name
Test status
Simulation time 756814242291 ps
CPU time 1580.43 seconds
Started Jul 01 04:36:29 PM PDT 24
Finished Jul 01 05:02:57 PM PDT 24
Peak memory 191248 kb
Host smart-4fa370cc-946e-4d2b-91e6-2778d3ac3bbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497189447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1497189447
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/143.rv_timer_random.2720096258
Short name T341
Test name
Test status
Simulation time 172662229517 ps
CPU time 243.36 seconds
Started Jul 01 04:37:10 PM PDT 24
Finished Jul 01 04:41:16 PM PDT 24
Peak memory 191280 kb
Host smart-df96abd5-d3e5-454a-8a2e-39dc7f7bfbf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720096258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2720096258
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1637173540
Short name T297
Test name
Test status
Simulation time 82284426871 ps
CPU time 228.68 seconds
Started Jul 01 04:37:14 PM PDT 24
Finished Jul 01 04:41:05 PM PDT 24
Peak memory 191184 kb
Host smart-d5aac6c9-f247-4ad6-b147-1f34b9c17b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637173540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1637173540
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1593469149
Short name T337
Test name
Test status
Simulation time 306609344034 ps
CPU time 252.17 seconds
Started Jul 01 04:36:20 PM PDT 24
Finished Jul 01 04:40:45 PM PDT 24
Peak memory 191312 kb
Host smart-4064126e-6e64-4e43-bf30-c00c00848845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593469149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1593469149
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3329539662
Short name T119
Test name
Test status
Simulation time 237996721778 ps
CPU time 480.04 seconds
Started Jul 01 04:37:20 PM PDT 24
Finished Jul 01 04:45:21 PM PDT 24
Peak memory 191192 kb
Host smart-200fb171-b84b-4421-ae4a-6233469abe5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329539662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3329539662
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2023078735
Short name T249
Test name
Test status
Simulation time 106497754974 ps
CPU time 155.22 seconds
Started Jul 01 04:37:32 PM PDT 24
Finished Jul 01 04:40:08 PM PDT 24
Peak memory 191184 kb
Host smart-4b735ca9-654e-4da7-a00d-310b7c4486a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023078735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2023078735
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3817183648
Short name T321
Test name
Test status
Simulation time 126130857764 ps
CPU time 210.58 seconds
Started Jul 01 04:36:51 PM PDT 24
Finished Jul 01 04:40:27 PM PDT 24
Peak memory 183060 kb
Host smart-17a5095e-7be3-44a6-9e17-d1c3ac1dacd7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817183648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3817183648
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1448936648
Short name T205
Test name
Test status
Simulation time 725069370025 ps
CPU time 1127.26 seconds
Started Jul 01 04:36:35 PM PDT 24
Finished Jul 01 04:55:28 PM PDT 24
Peak memory 191256 kb
Host smart-3f206ceb-681b-4d05-83ac-3f6f5b06bca3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448936648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1448936648
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.982847842
Short name T332
Test name
Test status
Simulation time 1927124280747 ps
CPU time 851.21 seconds
Started Jul 01 04:36:48 PM PDT 24
Finished Jul 01 04:51:04 PM PDT 24
Peak memory 182992 kb
Host smart-c4271670-3c61-49e1-9a82-1896d67c85b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982847842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.982847842
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1028581655
Short name T169
Test name
Test status
Simulation time 4934520279722 ps
CPU time 1150.66 seconds
Started Jul 01 04:36:54 PM PDT 24
Finished Jul 01 04:56:09 PM PDT 24
Peak memory 183196 kb
Host smart-e382ea25-5b5c-4145-b6dd-90e02baf5cc4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028581655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1028581655
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.68308321
Short name T63
Test name
Test status
Simulation time 789100908572 ps
CPU time 493.26 seconds
Started Jul 01 04:36:54 PM PDT 24
Finished Jul 01 04:45:12 PM PDT 24
Peak memory 191288 kb
Host smart-8cfaccc9-4c09-43c4-a4b6-b705773a71e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68308321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all.68308321
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2169831519
Short name T114
Test name
Test status
Simulation time 221509383 ps
CPU time 1.42 seconds
Started Jul 01 04:28:38 PM PDT 24
Finished Jul 01 04:28:46 PM PDT 24
Peak memory 195144 kb
Host smart-68ba970e-7f11-4d45-bd36-33af091b8934
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169831519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2169831519
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.338061654
Short name T291
Test name
Test status
Simulation time 79699661538 ps
CPU time 119.88 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:38:30 PM PDT 24
Peak memory 191248 kb
Host smart-89202bdf-65e2-45c6-8cf3-bb4cdb257d49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338061654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.338061654
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3792570743
Short name T250
Test name
Test status
Simulation time 174432979778 ps
CPU time 435.54 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:44:21 PM PDT 24
Peak memory 191272 kb
Host smart-20630dba-8df5-4145-9b73-49ebe219f9bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792570743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3792570743
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3071416138
Short name T235
Test name
Test status
Simulation time 84259550406 ps
CPU time 122.39 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 04:39:06 PM PDT 24
Peak memory 191288 kb
Host smart-c6d9d3d8-e8cf-4a79-b4e2-f84d98a4c67a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071416138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3071416138
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2822042100
Short name T241
Test name
Test status
Simulation time 179234905433 ps
CPU time 249.59 seconds
Started Jul 01 04:37:09 PM PDT 24
Finished Jul 01 04:41:22 PM PDT 24
Peak memory 191188 kb
Host smart-e0c92611-73b0-4522-85a1-eef6d79ac100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822042100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2822042100
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2260570759
Short name T158
Test name
Test status
Simulation time 1702075061023 ps
CPU time 2222.28 seconds
Started Jul 01 04:37:07 PM PDT 24
Finished Jul 01 05:14:12 PM PDT 24
Peak memory 191360 kb
Host smart-2ea195cb-afb3-4c1d-8d51-922218019916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260570759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2260570759
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.4039918324
Short name T146
Test name
Test status
Simulation time 431479176989 ps
CPU time 541.28 seconds
Started Jul 01 04:37:04 PM PDT 24
Finished Jul 01 04:46:08 PM PDT 24
Peak memory 193756 kb
Host smart-99054ed2-3d1d-444f-9740-c0716f678845
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039918324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.4039918324
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3736588553
Short name T441
Test name
Test status
Simulation time 49899262601 ps
CPU time 61.06 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:37:29 PM PDT 24
Peak memory 191944 kb
Host smart-2b5ea99b-f15f-47ab-a01a-1b07fe38b674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736588553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3736588553
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.3427780628
Short name T252
Test name
Test status
Simulation time 292070803437 ps
CPU time 227.64 seconds
Started Jul 01 04:37:16 PM PDT 24
Finished Jul 01 04:41:05 PM PDT 24
Peak memory 191288 kb
Host smart-3ac4f372-fa6e-4ef3-b753-16a47c62e806
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427780628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3427780628
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1808394144
Short name T303
Test name
Test status
Simulation time 230047787291 ps
CPU time 255.03 seconds
Started Jul 01 04:37:17 PM PDT 24
Finished Jul 01 04:41:33 PM PDT 24
Peak memory 191288 kb
Host smart-32a080bc-0a36-4361-a905-b292a94277e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808394144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1808394144
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.916888198
Short name T154
Test name
Test status
Simulation time 359620304378 ps
CPU time 175.8 seconds
Started Jul 01 04:37:18 PM PDT 24
Finished Jul 01 04:40:15 PM PDT 24
Peak memory 191284 kb
Host smart-56eb1dbd-b660-4f71-97fe-9e2d5c019b50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916888198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.916888198
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.995335578
Short name T179
Test name
Test status
Simulation time 153829648923 ps
CPU time 262.52 seconds
Started Jul 01 04:37:24 PM PDT 24
Finished Jul 01 04:41:48 PM PDT 24
Peak memory 191272 kb
Host smart-c49b0538-24ae-4123-84b3-1994df7f8a29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995335578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.995335578
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.2492612119
Short name T243
Test name
Test status
Simulation time 1975001136291 ps
CPU time 1020.91 seconds
Started Jul 01 04:36:21 PM PDT 24
Finished Jul 01 04:53:35 PM PDT 24
Peak memory 183084 kb
Host smart-54765751-26e9-4fd8-9e65-225c1397c433
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492612119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.2492612119
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_random.510407628
Short name T172
Test name
Test status
Simulation time 107433118637 ps
CPU time 190.21 seconds
Started Jul 01 04:36:22 PM PDT 24
Finished Jul 01 04:39:44 PM PDT 24
Peak memory 191408 kb
Host smart-205d5ffc-198a-4490-902b-8fcdcd8259dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510407628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.510407628
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.4174052603
Short name T286
Test name
Test status
Simulation time 119594179631 ps
CPU time 459.95 seconds
Started Jul 01 04:37:25 PM PDT 24
Finished Jul 01 04:45:06 PM PDT 24
Peak memory 182992 kb
Host smart-6917d1bf-b52e-4f8b-8128-d3e638c46009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174052603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.4174052603
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1523586992
Short name T74
Test name
Test status
Simulation time 542843000712 ps
CPU time 469.11 seconds
Started Jul 01 04:37:39 PM PDT 24
Finished Jul 01 04:45:29 PM PDT 24
Peak memory 194612 kb
Host smart-7d86b152-7db9-448a-90dc-dfa3a8712027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523586992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1523586992
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.3960763004
Short name T350
Test name
Test status
Simulation time 41131328350 ps
CPU time 90.21 seconds
Started Jul 01 04:37:38 PM PDT 24
Finished Jul 01 04:39:10 PM PDT 24
Peak memory 183152 kb
Host smart-9ae6eb7d-5943-4186-b4b5-8137328bfeda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960763004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.3960763004
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.269370816
Short name T312
Test name
Test status
Simulation time 203173426725 ps
CPU time 164.29 seconds
Started Jul 01 04:36:22 PM PDT 24
Finished Jul 01 04:39:18 PM PDT 24
Peak memory 191272 kb
Host smart-af131572-b636-4f3d-9f6b-b16b8946782a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269370816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.269370816
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.393009768
Short name T161
Test name
Test status
Simulation time 981205032736 ps
CPU time 516.39 seconds
Started Jul 01 04:36:44 PM PDT 24
Finished Jul 01 04:45:25 PM PDT 24
Peak memory 182892 kb
Host smart-aa4be061-a13f-4b64-b543-3fbe940afa3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393009768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.393009768
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2927523954
Short name T198
Test name
Test status
Simulation time 211242583698 ps
CPU time 188.69 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:39:59 PM PDT 24
Peak memory 183084 kb
Host smart-a27cf681-d5f0-48bc-9a7c-516f6cd262d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927523954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2927523954
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.324969769
Short name T274
Test name
Test status
Simulation time 42395008790 ps
CPU time 69.97 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:38:00 PM PDT 24
Peak memory 191212 kb
Host smart-744c93e0-d3d6-40c9-84f7-d6ff3bb07395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324969769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.324969769
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.4021989466
Short name T83
Test name
Test status
Simulation time 419897069698 ps
CPU time 395.9 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:43:17 PM PDT 24
Peak memory 183036 kb
Host smart-5fed4456-4823-421f-b949-809c111f06c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021989466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.4021989466
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.107232296
Short name T283
Test name
Test status
Simulation time 1200730867205 ps
CPU time 417.88 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:43:39 PM PDT 24
Peak memory 183080 kb
Host smart-98ff23cf-b0f3-4a9d-8c25-a0b983f6780a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107232296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.107232296
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2795467042
Short name T309
Test name
Test status
Simulation time 28188504618 ps
CPU time 223.41 seconds
Started Jul 01 04:36:52 PM PDT 24
Finished Jul 01 04:40:40 PM PDT 24
Peak memory 183200 kb
Host smart-bf4c9447-6b97-44d0-86de-fe98f4e3610a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795467042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2795467042
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3866718050
Short name T299
Test name
Test status
Simulation time 166612400847 ps
CPU time 145.29 seconds
Started Jul 01 04:36:51 PM PDT 24
Finished Jul 01 04:39:21 PM PDT 24
Peak memory 191216 kb
Host smart-ef7522fb-e8de-42a5-ad87-e4976e0150d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866718050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3866718050
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2809939298
Short name T123
Test name
Test status
Simulation time 146461075826 ps
CPU time 236.81 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:40:25 PM PDT 24
Peak memory 183024 kb
Host smart-17ca90a4-f2dd-4738-88d7-628cbd1f52d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809939298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2809939298
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/61.rv_timer_random.1267474657
Short name T317
Test name
Test status
Simulation time 980551917099 ps
CPU time 494.64 seconds
Started Jul 01 04:36:52 PM PDT 24
Finished Jul 01 04:45:11 PM PDT 24
Peak memory 191260 kb
Host smart-80b5c19f-c66e-4c31-bbe6-3a8983b699c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267474657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1267474657
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.692462753
Short name T93
Test name
Test status
Simulation time 140722493 ps
CPU time 0.8 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:56 PM PDT 24
Peak memory 191996 kb
Host smart-403d0a84-53d4-46cc-a6a9-083955eeece6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692462753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alias
ing.692462753
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2393726077
Short name T47
Test name
Test status
Simulation time 853793330 ps
CPU time 3.66 seconds
Started Jul 01 04:28:46 PM PDT 24
Finished Jul 01 04:29:02 PM PDT 24
Peak memory 192104 kb
Host smart-a92488e9-ba9d-4c0e-8a7b-13ba0b260a58
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393726077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2393726077
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.650785436
Short name T44
Test name
Test status
Simulation time 37487290 ps
CPU time 0.61 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:41 PM PDT 24
Peak memory 182172 kb
Host smart-39f8b937-e817-4b62-8166-dd1b2f585da4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650785436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.650785436
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2896666822
Short name T470
Test name
Test status
Simulation time 57724301 ps
CPU time 0.81 seconds
Started Jul 01 04:28:30 PM PDT 24
Finished Jul 01 04:28:36 PM PDT 24
Peak memory 195848 kb
Host smart-d1360556-7d9c-462d-af84-d5f82207b452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896666822 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2896666822
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1925843064
Short name T489
Test name
Test status
Simulation time 68809099 ps
CPU time 0.55 seconds
Started Jul 01 04:28:38 PM PDT 24
Finished Jul 01 04:28:46 PM PDT 24
Peak memory 181752 kb
Host smart-37ec88ba-1cbd-4ea7-864a-6167c5838a5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925843064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1925843064
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2907706749
Short name T522
Test name
Test status
Simulation time 56780673 ps
CPU time 0.83 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 193152 kb
Host smart-62e7fba5-8f15-4ee6-b736-de8aec6ea59b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907706749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2907706749
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2857745732
Short name T463
Test name
Test status
Simulation time 161979989 ps
CPU time 0.98 seconds
Started Jul 01 04:28:41 PM PDT 24
Finished Jul 01 04:28:51 PM PDT 24
Peak memory 196064 kb
Host smart-7d8630f0-cfa8-403c-978c-9c3935433c5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857745732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2857745732
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.2903494953
Short name T582
Test name
Test status
Simulation time 36474463 ps
CPU time 0.65 seconds
Started Jul 01 04:28:37 PM PDT 24
Finished Jul 01 04:28:45 PM PDT 24
Peak memory 182172 kb
Host smart-77238ad2-c4a0-4bb1-89af-724a41d3133e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903494953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.2903494953
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.758161243
Short name T32
Test name
Test status
Simulation time 396188018 ps
CPU time 1.47 seconds
Started Jul 01 04:28:45 PM PDT 24
Finished Jul 01 04:28:57 PM PDT 24
Peak memory 190744 kb
Host smart-c9a54763-cacc-457d-9d82-5fdcc9bb06e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758161243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.758161243
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1247499324
Short name T548
Test name
Test status
Simulation time 56892347 ps
CPU time 0.61 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 182364 kb
Host smart-3fac5e75-c82f-41d6-9715-3f879c7ed13d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247499324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1247499324
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.759737548
Short name T542
Test name
Test status
Simulation time 37367105 ps
CPU time 0.95 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:51 PM PDT 24
Peak memory 196828 kb
Host smart-d21ac726-e275-4010-befe-91450f512d72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759737548 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.759737548
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1653809165
Short name T477
Test name
Test status
Simulation time 48635409 ps
CPU time 0.56 seconds
Started Jul 01 04:28:48 PM PDT 24
Finished Jul 01 04:29:01 PM PDT 24
Peak memory 182264 kb
Host smart-10059d1d-b974-442b-8700-a039c5313087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653809165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1653809165
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3987403453
Short name T572
Test name
Test status
Simulation time 177142678 ps
CPU time 0.65 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 191664 kb
Host smart-402e7564-d20f-4df6-8bdd-899aba6bdec5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987403453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3987403453
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1604557103
Short name T509
Test name
Test status
Simulation time 22798068 ps
CPU time 1.13 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:56 PM PDT 24
Peak memory 196968 kb
Host smart-0de8f7e1-09e7-48f1-87fd-04553681f768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604557103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1604557103
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3462426793
Short name T577
Test name
Test status
Simulation time 113708641 ps
CPU time 1.07 seconds
Started Jul 01 04:28:31 PM PDT 24
Finished Jul 01 04:28:37 PM PDT 24
Peak memory 193644 kb
Host smart-c3619bf3-8c03-43e5-b2b9-4f592c5e5af6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462426793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3462426793
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4126905507
Short name T563
Test name
Test status
Simulation time 329633888 ps
CPU time 1.01 seconds
Started Jul 01 04:28:45 PM PDT 24
Finished Jul 01 04:28:58 PM PDT 24
Peak memory 196768 kb
Host smart-7cf1eb37-52eb-4460-a7fa-d80b294320e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126905507 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.4126905507
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.546432271
Short name T538
Test name
Test status
Simulation time 22995529 ps
CPU time 0.57 seconds
Started Jul 01 04:28:54 PM PDT 24
Finished Jul 01 04:29:09 PM PDT 24
Peak memory 182184 kb
Host smart-2c526abd-b648-41ea-831f-fe766989df37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546432271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.546432271
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2816980509
Short name T473
Test name
Test status
Simulation time 54842173 ps
CPU time 0.59 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:56 PM PDT 24
Peak memory 182020 kb
Host smart-a4b2db51-d27c-4944-bfe3-d7763ced6ab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816980509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2816980509
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1871506040
Short name T45
Test name
Test status
Simulation time 22516703 ps
CPU time 0.68 seconds
Started Jul 01 04:28:46 PM PDT 24
Finished Jul 01 04:28:58 PM PDT 24
Peak memory 191480 kb
Host smart-0be9dd68-9dfc-42a4-baf3-44ddaad2955a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871506040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1871506040
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1127223477
Short name T543
Test name
Test status
Simulation time 31665033 ps
CPU time 1.33 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 196948 kb
Host smart-97739589-feb0-4487-8972-fdda0f87dd14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127223477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1127223477
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.156757178
Short name T112
Test name
Test status
Simulation time 126254249 ps
CPU time 1.35 seconds
Started Jul 01 04:28:54 PM PDT 24
Finished Jul 01 04:29:09 PM PDT 24
Peak memory 195116 kb
Host smart-2539f2ad-5617-472a-9979-1545284bb436
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156757178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.156757178
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3363171075
Short name T478
Test name
Test status
Simulation time 75269483 ps
CPU time 0.86 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 196060 kb
Host smart-47885cdc-6c12-494e-94fb-057213778cf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363171075 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3363171075
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.170179876
Short name T31
Test name
Test status
Simulation time 54967961 ps
CPU time 0.58 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 182140 kb
Host smart-ce4a2902-9442-4eb5-9d89-0fffa1a75c65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170179876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.170179876
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1736637856
Short name T534
Test name
Test status
Simulation time 14652337 ps
CPU time 0.54 seconds
Started Jul 01 04:28:52 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 181504 kb
Host smart-c5db0976-c046-4df1-95a1-0ce577a197b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736637856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1736637856
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.875457704
Short name T97
Test name
Test status
Simulation time 62364042 ps
CPU time 0.63 seconds
Started Jul 01 04:28:55 PM PDT 24
Finished Jul 01 04:29:09 PM PDT 24
Peak memory 192488 kb
Host smart-addb06b5-036b-48f4-af31-b8431c05ce02
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875457704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.875457704
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2911399020
Short name T531
Test name
Test status
Simulation time 279526335 ps
CPU time 2.76 seconds
Started Jul 01 04:28:50 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 197144 kb
Host smart-a3f43e61-243b-4508-ba80-e10e036e8ec3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911399020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2911399020
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4080887892
Short name T552
Test name
Test status
Simulation time 515678974 ps
CPU time 0.77 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:55 PM PDT 24
Peak memory 193080 kb
Host smart-6ffbb91d-a495-455b-a2e7-706f5e9b8ffa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080887892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.4080887892
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.272193264
Short name T496
Test name
Test status
Simulation time 27889757 ps
CPU time 1.22 seconds
Started Jul 01 04:28:50 PM PDT 24
Finished Jul 01 04:29:05 PM PDT 24
Peak memory 196956 kb
Host smart-4cd18be1-b148-43c2-a97f-403a4924b244
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272193264 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.272193264
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3938232629
Short name T492
Test name
Test status
Simulation time 30127824 ps
CPU time 0.61 seconds
Started Jul 01 04:28:53 PM PDT 24
Finished Jul 01 04:29:08 PM PDT 24
Peak memory 182484 kb
Host smart-1a3c5d6f-a5f2-4517-a468-a0edca13342d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938232629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3938232629
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2042096198
Short name T500
Test name
Test status
Simulation time 18603112 ps
CPU time 0.57 seconds
Started Jul 01 04:28:34 PM PDT 24
Finished Jul 01 04:28:41 PM PDT 24
Peak memory 182060 kb
Host smart-d06d771e-2e69-4410-9275-fe44629213f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042096198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2042096198
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3555108059
Short name T102
Test name
Test status
Simulation time 31554611 ps
CPU time 0.65 seconds
Started Jul 01 04:28:50 PM PDT 24
Finished Jul 01 04:29:05 PM PDT 24
Peak memory 191120 kb
Host smart-d78df06e-88d9-4d1b-b1ec-8d702d6ebd98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555108059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3555108059
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2728350190
Short name T487
Test name
Test status
Simulation time 366877452 ps
CPU time 2.73 seconds
Started Jul 01 04:28:48 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 196968 kb
Host smart-5c8372b4-7950-4eeb-b687-9725729176cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728350190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2728350190
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.964576524
Short name T541
Test name
Test status
Simulation time 214329850 ps
CPU time 1.04 seconds
Started Jul 01 04:28:41 PM PDT 24
Finished Jul 01 04:28:49 PM PDT 24
Peak memory 193700 kb
Host smart-3a8a0093-5329-4d86-9e5f-c7955382785c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964576524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_in
tg_err.964576524
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4191689198
Short name T539
Test name
Test status
Simulation time 40250960 ps
CPU time 0.93 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 196828 kb
Host smart-817d1b0e-c55e-4463-b26d-dcc8d2cc5600
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191689198 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.4191689198
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1659842163
Short name T569
Test name
Test status
Simulation time 33611588 ps
CPU time 0.58 seconds
Started Jul 01 04:28:48 PM PDT 24
Finished Jul 01 04:29:01 PM PDT 24
Peak memory 182492 kb
Host smart-f8b1e710-338f-40c0-98bf-096f651a926d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659842163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1659842163
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3788267038
Short name T549
Test name
Test status
Simulation time 12917468 ps
CPU time 0.54 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 182100 kb
Host smart-0a194b13-64a0-415c-9040-4a080d1ef95e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788267038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3788267038
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.688819677
Short name T99
Test name
Test status
Simulation time 38184595 ps
CPU time 0.78 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 192984 kb
Host smart-54bdad34-7c94-474f-875d-db043b51b2d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688819677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.688819677
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3271358691
Short name T59
Test name
Test status
Simulation time 147427500 ps
CPU time 2.66 seconds
Started Jul 01 04:29:01 PM PDT 24
Finished Jul 01 04:29:16 PM PDT 24
Peak memory 196944 kb
Host smart-75b11c70-34aa-4db3-b51a-195cf065968d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271358691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3271358691
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2734618650
Short name T29
Test name
Test status
Simulation time 100539515 ps
CPU time 1.11 seconds
Started Jul 01 04:28:50 PM PDT 24
Finished Jul 01 04:29:06 PM PDT 24
Peak memory 183208 kb
Host smart-eff9df84-71db-4373-bec9-be6efdad5774
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734618650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2734618650
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.397739501
Short name T578
Test name
Test status
Simulation time 111297153 ps
CPU time 1.49 seconds
Started Jul 01 04:28:46 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 196972 kb
Host smart-3738e2a2-11b4-4fff-8ce6-9fc079fcbe7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397739501 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.397739501
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3832921449
Short name T568
Test name
Test status
Simulation time 36262437 ps
CPU time 0.61 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:50 PM PDT 24
Peak memory 191404 kb
Host smart-f54521fd-bcdf-41a1-aa43-4b181326a9b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832921449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3832921449
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1047525687
Short name T465
Test name
Test status
Simulation time 108522260 ps
CPU time 0.53 seconds
Started Jul 01 04:28:46 PM PDT 24
Finished Jul 01 04:28:58 PM PDT 24
Peak memory 182096 kb
Host smart-40ae01f7-01dd-440c-9668-a7f63bd3a1f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047525687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1047525687
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2774295979
Short name T529
Test name
Test status
Simulation time 34701053 ps
CPU time 0.74 seconds
Started Jul 01 04:28:52 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 192768 kb
Host smart-ee517cbb-4a77-4dad-b375-c1901a0b48e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774295979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2774295979
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1325824763
Short name T480
Test name
Test status
Simulation time 146263978 ps
CPU time 1.61 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 196976 kb
Host smart-087fe575-bd06-46ae-a3a9-50b76f5ee1f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325824763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1325824763
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2790542121
Short name T565
Test name
Test status
Simulation time 84661735 ps
CPU time 1 seconds
Started Jul 01 04:29:00 PM PDT 24
Finished Jul 01 04:29:14 PM PDT 24
Peak memory 196812 kb
Host smart-f61b3de8-a892-47cc-85e9-9e3b8b1afb3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790542121 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2790542121
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1985707597
Short name T535
Test name
Test status
Simulation time 34603954 ps
CPU time 0.51 seconds
Started Jul 01 04:29:01 PM PDT 24
Finished Jul 01 04:29:15 PM PDT 24
Peak memory 182036 kb
Host smart-68f9b635-6d3d-4c5d-9d8d-2997d05f8c4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985707597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1985707597
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3099644552
Short name T583
Test name
Test status
Simulation time 11772011 ps
CPU time 0.6 seconds
Started Jul 01 04:28:56 PM PDT 24
Finished Jul 01 04:29:11 PM PDT 24
Peak memory 182376 kb
Host smart-3b754674-318d-4c9c-ad23-09f858ec3bea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099644552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3099644552
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1693729210
Short name T86
Test name
Test status
Simulation time 273785775 ps
CPU time 0.66 seconds
Started Jul 01 04:28:54 PM PDT 24
Finished Jul 01 04:29:09 PM PDT 24
Peak memory 191200 kb
Host smart-6fe643be-7d2a-444b-a6d2-ceb1a7873ca7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693729210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1693729210
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3551821168
Short name T528
Test name
Test status
Simulation time 185589154 ps
CPU time 2.85 seconds
Started Jul 01 04:28:50 PM PDT 24
Finished Jul 01 04:29:06 PM PDT 24
Peak memory 196876 kb
Host smart-49b9c469-544d-48b2-91bc-35ecc11d871a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551821168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3551821168
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3923604604
Short name T561
Test name
Test status
Simulation time 168417744 ps
CPU time 0.84 seconds
Started Jul 01 04:29:00 PM PDT 24
Finished Jul 01 04:29:14 PM PDT 24
Peak memory 192352 kb
Host smart-2f662f25-dcbf-45d3-a450-5c414cf1fa33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923604604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3923604604
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2235233179
Short name T464
Test name
Test status
Simulation time 103164831 ps
CPU time 1.41 seconds
Started Jul 01 04:28:48 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 196976 kb
Host smart-8b256e52-bd08-4dff-8f6c-1ecff21724c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235233179 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2235233179
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3924030257
Short name T571
Test name
Test status
Simulation time 30569584 ps
CPU time 0.6 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 182144 kb
Host smart-6d0fa23f-cf3e-4c99-b213-80db1863944a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924030257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3924030257
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.721457052
Short name T503
Test name
Test status
Simulation time 84387914 ps
CPU time 0.54 seconds
Started Jul 01 04:28:53 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 181992 kb
Host smart-78b70559-34fb-445f-9a3c-5ad2c800ae27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721457052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.721457052
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2907066146
Short name T581
Test name
Test status
Simulation time 14579515 ps
CPU time 0.64 seconds
Started Jul 01 04:28:54 PM PDT 24
Finished Jul 01 04:29:08 PM PDT 24
Peak memory 191652 kb
Host smart-24b665f5-0283-4dee-807e-e319ecadecfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907066146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2907066146
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1484085215
Short name T540
Test name
Test status
Simulation time 31420601 ps
CPU time 1.55 seconds
Started Jul 01 04:28:55 PM PDT 24
Finished Jul 01 04:29:11 PM PDT 24
Peak memory 196972 kb
Host smart-5c6bdb69-f233-4e4a-8599-db29bcaf830f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484085215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1484085215
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3342318914
Short name T115
Test name
Test status
Simulation time 299126091 ps
CPU time 1.03 seconds
Started Jul 01 04:28:45 PM PDT 24
Finished Jul 01 04:28:57 PM PDT 24
Peak memory 194364 kb
Host smart-b9c6d68e-3ff3-4655-aca2-a134e814fd0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342318914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3342318914
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2467172465
Short name T532
Test name
Test status
Simulation time 30535966 ps
CPU time 0.74 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 194436 kb
Host smart-d7a9c547-ce02-4ecb-93be-0d3c727aaff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467172465 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2467172465
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.4159813438
Short name T474
Test name
Test status
Simulation time 81578828 ps
CPU time 0.55 seconds
Started Jul 01 04:28:54 PM PDT 24
Finished Jul 01 04:29:09 PM PDT 24
Peak memory 182144 kb
Host smart-1a1ceea3-9ecb-4e5c-9e6c-7d0d92d8b0b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159813438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.4159813438
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3350466530
Short name T567
Test name
Test status
Simulation time 36811365 ps
CPU time 0.57 seconds
Started Jul 01 04:28:52 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 181984 kb
Host smart-fe6d2b17-6d8f-4fa9-aec1-108239fc13a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350466530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3350466530
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1183734776
Short name T530
Test name
Test status
Simulation time 17516452 ps
CPU time 0.6 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 191380 kb
Host smart-28a03ed9-6d6f-4c29-9b21-8713389c0958
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183734776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1183734776
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.775080795
Short name T551
Test name
Test status
Simulation time 103701079 ps
CPU time 1.14 seconds
Started Jul 01 04:28:53 PM PDT 24
Finished Jul 01 04:29:08 PM PDT 24
Peak memory 196708 kb
Host smart-8f243db2-7567-4373-997d-612cf8b65190
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775080795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.775080795
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2104849531
Short name T570
Test name
Test status
Simulation time 78178003 ps
CPU time 1.1 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 194384 kb
Host smart-1bb66669-354a-4d4d-8a9c-7357f2aa7ba3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104849531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2104849531
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2670803802
Short name T504
Test name
Test status
Simulation time 51471026 ps
CPU time 1.08 seconds
Started Jul 01 04:29:00 PM PDT 24
Finished Jul 01 04:29:14 PM PDT 24
Peak memory 196832 kb
Host smart-47ed60e8-8aa6-4704-b6fe-a2fc80980216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670803802 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2670803802
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3587221798
Short name T49
Test name
Test status
Simulation time 15752229 ps
CPU time 0.58 seconds
Started Jul 01 04:29:10 PM PDT 24
Finished Jul 01 04:29:21 PM PDT 24
Peak memory 182212 kb
Host smart-8858db06-a6e7-4381-acea-b03fbf05de47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587221798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3587221798
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1671268011
Short name T467
Test name
Test status
Simulation time 20152481 ps
CPU time 0.56 seconds
Started Jul 01 04:28:54 PM PDT 24
Finished Jul 01 04:29:09 PM PDT 24
Peak memory 181756 kb
Host smart-aa6baf56-684a-48a2-8adb-8907cb51b559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671268011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1671268011
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1710245483
Short name T100
Test name
Test status
Simulation time 174654754 ps
CPU time 0.66 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:55 PM PDT 24
Peak memory 191040 kb
Host smart-ed82bc79-b7f5-4b65-aa0c-3a88bf1c1481
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710245483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1710245483
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1152837355
Short name T573
Test name
Test status
Simulation time 50996225 ps
CPU time 1.2 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 197276 kb
Host smart-73c748fd-f67b-43fc-a04d-57a31ea0b05d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152837355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1152837355
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2266161708
Short name T481
Test name
Test status
Simulation time 120021300 ps
CPU time 1.3 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:29:13 PM PDT 24
Peak memory 193928 kb
Host smart-0cb3b89a-0e84-45ec-9afc-1d62881190ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266161708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2266161708
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1258879479
Short name T461
Test name
Test status
Simulation time 123797281 ps
CPU time 0.85 seconds
Started Jul 01 04:28:54 PM PDT 24
Finished Jul 01 04:29:08 PM PDT 24
Peak memory 195812 kb
Host smart-a6be561a-4059-45bb-99bf-94ceb97e3266
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258879479 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1258879479
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1251279535
Short name T506
Test name
Test status
Simulation time 25655980 ps
CPU time 0.58 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 181876 kb
Host smart-fb643296-6f94-4a71-bae7-182cd1bc27eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251279535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1251279535
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1569155270
Short name T524
Test name
Test status
Simulation time 23340774 ps
CPU time 0.53 seconds
Started Jul 01 04:28:52 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 182012 kb
Host smart-7c3200d3-fe45-4976-9fdb-21ae5b93952b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569155270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1569155270
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2545026550
Short name T525
Test name
Test status
Simulation time 49486715 ps
CPU time 0.68 seconds
Started Jul 01 04:28:50 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 191712 kb
Host smart-54c9d872-719c-435e-9fcb-dbf0623326fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545026550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2545026550
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1725876359
Short name T527
Test name
Test status
Simulation time 228868367 ps
CPU time 1.23 seconds
Started Jul 01 04:28:53 PM PDT 24
Finished Jul 01 04:29:08 PM PDT 24
Peak memory 196908 kb
Host smart-1eac1c00-9aac-461b-93a6-1b48249327a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725876359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1725876359
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1211559890
Short name T526
Test name
Test status
Simulation time 331126754 ps
CPU time 1.27 seconds
Started Jul 01 04:28:51 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 195048 kb
Host smart-c368fc69-f6f7-4ff6-a299-d90391766c7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211559890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1211559890
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2155331206
Short name T89
Test name
Test status
Simulation time 29469250 ps
CPU time 0.7 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 191384 kb
Host smart-73f1e5b0-93c5-4313-8059-25fd497af2da
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155331206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2155331206
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.390786403
Short name T471
Test name
Test status
Simulation time 262444586 ps
CPU time 2.32 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:56 PM PDT 24
Peak memory 193284 kb
Host smart-69d93ea2-1272-45f6-a1fd-28360ba969d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390786403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_b
ash.390786403
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2586136362
Short name T91
Test name
Test status
Simulation time 28542427 ps
CPU time 0.57 seconds
Started Jul 01 04:28:46 PM PDT 24
Finished Jul 01 04:28:59 PM PDT 24
Peak memory 182260 kb
Host smart-fcb3f0a3-53f0-4f52-9460-64373530a16f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586136362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2586136362
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2189100713
Short name T519
Test name
Test status
Simulation time 44451948 ps
CPU time 1.02 seconds
Started Jul 01 04:28:33 PM PDT 24
Finished Jul 01 04:28:39 PM PDT 24
Peak memory 196656 kb
Host smart-f311bf74-5725-4199-a58f-26ea1955136c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189100713 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2189100713
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2745047082
Short name T95
Test name
Test status
Simulation time 46920173 ps
CPU time 0.55 seconds
Started Jul 01 04:28:50 PM PDT 24
Finished Jul 01 04:29:05 PM PDT 24
Peak memory 182180 kb
Host smart-326c338f-5d1b-4081-8fac-1fc5148c8060
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745047082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2745047082
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2536539941
Short name T469
Test name
Test status
Simulation time 15761317 ps
CPU time 0.53 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:29:01 PM PDT 24
Peak memory 181972 kb
Host smart-c3619123-961e-4df5-b791-eb64cba7b6d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536539941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2536539941
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1249494596
Short name T501
Test name
Test status
Simulation time 85325919 ps
CPU time 0.68 seconds
Started Jul 01 04:28:48 PM PDT 24
Finished Jul 01 04:29:02 PM PDT 24
Peak memory 191664 kb
Host smart-209bf57f-f1ae-4f9b-9d4a-038934f541ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249494596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1249494596
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3434145800
Short name T523
Test name
Test status
Simulation time 41570802 ps
CPU time 1.84 seconds
Started Jul 01 04:28:46 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 196972 kb
Host smart-400e5e7c-d7b6-4f35-b61b-13802e65436a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434145800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3434145800
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1525542458
Short name T113
Test name
Test status
Simulation time 204000907 ps
CPU time 1.1 seconds
Started Jul 01 04:28:37 PM PDT 24
Finished Jul 01 04:28:44 PM PDT 24
Peak memory 194104 kb
Host smart-5d330b13-a8e6-4515-b4bc-aa8cd4d9c58c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525542458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1525542458
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3242191310
Short name T508
Test name
Test status
Simulation time 75545393 ps
CPU time 0.55 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 182228 kb
Host smart-850fcc40-04d0-4f0d-aa17-48b43562c145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242191310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3242191310
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1488765327
Short name T579
Test name
Test status
Simulation time 57737013 ps
CPU time 0.59 seconds
Started Jul 01 04:29:07 PM PDT 24
Finished Jul 01 04:29:18 PM PDT 24
Peak memory 182164 kb
Host smart-7a73522a-03eb-4e99-98da-492dc8f06f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488765327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1488765327
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2135088167
Short name T494
Test name
Test status
Simulation time 181345830 ps
CPU time 0.55 seconds
Started Jul 01 04:28:51 PM PDT 24
Finished Jul 01 04:29:05 PM PDT 24
Peak memory 182092 kb
Host smart-33897ed2-ea08-4d4c-8e1d-fa874bd1d50d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135088167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2135088167
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3352175536
Short name T459
Test name
Test status
Simulation time 12666310 ps
CPU time 0.55 seconds
Started Jul 01 04:28:51 PM PDT 24
Finished Jul 01 04:29:06 PM PDT 24
Peak memory 182056 kb
Host smart-978c1c83-0213-464a-aca7-283ba554e18b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352175536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3352175536
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.4039968479
Short name T475
Test name
Test status
Simulation time 16003050 ps
CPU time 0.65 seconds
Started Jul 01 04:29:09 PM PDT 24
Finished Jul 01 04:29:20 PM PDT 24
Peak memory 182236 kb
Host smart-79528b08-577c-41ce-a36c-633736bc6c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039968479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.4039968479
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4134439638
Short name T499
Test name
Test status
Simulation time 16921421 ps
CPU time 0.54 seconds
Started Jul 01 04:28:52 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 182016 kb
Host smart-6007d949-a1ce-4d75-8573-7ca3fbe46019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134439638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4134439638
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1618045372
Short name T584
Test name
Test status
Simulation time 12695363 ps
CPU time 0.54 seconds
Started Jul 01 04:28:56 PM PDT 24
Finished Jul 01 04:29:11 PM PDT 24
Peak memory 182064 kb
Host smart-6a48812d-fb04-4a3d-9832-eec089f176aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618045372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1618045372
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2127468030
Short name T498
Test name
Test status
Simulation time 20826611 ps
CPU time 0.56 seconds
Started Jul 01 04:28:53 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 182092 kb
Host smart-388ab52e-0f08-4b10-97d0-7d1a9987a92e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127468030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2127468030
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1492154573
Short name T510
Test name
Test status
Simulation time 41832230 ps
CPU time 0.52 seconds
Started Jul 01 04:29:03 PM PDT 24
Finished Jul 01 04:29:15 PM PDT 24
Peak memory 181564 kb
Host smart-e8cd6979-d51b-401f-b2b1-0258581e18de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492154573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1492154573
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.433688872
Short name T566
Test name
Test status
Simulation time 24027553 ps
CPU time 0.51 seconds
Started Jul 01 04:29:00 PM PDT 24
Finished Jul 01 04:29:13 PM PDT 24
Peak memory 181548 kb
Host smart-20c1e413-c157-4d50-aac7-5c871dd9e5ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433688872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.433688872
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1471470912
Short name T90
Test name
Test status
Simulation time 81419593 ps
CPU time 0.81 seconds
Started Jul 01 04:28:52 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 192024 kb
Host smart-e5785a42-d3df-4e20-948a-adaa21421a63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471470912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1471470912
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3063797104
Short name T48
Test name
Test status
Simulation time 360296151 ps
CPU time 3.8 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:57 PM PDT 24
Peak memory 193732 kb
Host smart-bca5ccb2-0c97-434b-be3c-e2d0c027dca7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063797104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3063797104
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.55496274
Short name T555
Test name
Test status
Simulation time 32059002 ps
CPU time 0.6 seconds
Started Jul 01 04:28:45 PM PDT 24
Finished Jul 01 04:28:57 PM PDT 24
Peak memory 182396 kb
Host smart-a8a33503-6d12-4339-8878-8fc2d9d00235
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55496274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_res
et.55496274
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3422383742
Short name T544
Test name
Test status
Simulation time 43920053 ps
CPU time 0.9 seconds
Started Jul 01 04:28:46 PM PDT 24
Finished Jul 01 04:28:59 PM PDT 24
Peak memory 196536 kb
Host smart-35fa1333-8bdb-4b43-916e-fa4166fdf347
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422383742 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3422383742
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2535004710
Short name T483
Test name
Test status
Simulation time 18633349 ps
CPU time 0.6 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:52 PM PDT 24
Peak memory 182180 kb
Host smart-7e8bddf9-7f1c-476d-8552-98043cba991e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535004710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2535004710
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3409618420
Short name T495
Test name
Test status
Simulation time 29763556 ps
CPU time 0.55 seconds
Started Jul 01 04:28:39 PM PDT 24
Finished Jul 01 04:28:46 PM PDT 24
Peak memory 181540 kb
Host smart-1fb7f557-acf7-4c0a-990a-28087de02e88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409618420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3409618420
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2359364332
Short name T562
Test name
Test status
Simulation time 29995931 ps
CPU time 0.61 seconds
Started Jul 01 04:28:50 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 191408 kb
Host smart-06405bea-5ccd-4353-becf-4509ca337f40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359364332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2359364332
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1610792997
Short name T511
Test name
Test status
Simulation time 185437396 ps
CPU time 3.71 seconds
Started Jul 01 04:28:36 PM PDT 24
Finished Jul 01 04:28:45 PM PDT 24
Peak memory 196940 kb
Host smart-f82cc3d3-64c4-4be9-8be8-f78ee73cec3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610792997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1610792997
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3512859933
Short name T497
Test name
Test status
Simulation time 73279246 ps
CPU time 1.05 seconds
Started Jul 01 04:28:41 PM PDT 24
Finished Jul 01 04:28:50 PM PDT 24
Peak memory 182624 kb
Host smart-3e76861a-2fc8-42d6-b858-db51eed6c7e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512859933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3512859933
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2085316813
Short name T576
Test name
Test status
Simulation time 48054104 ps
CPU time 0.55 seconds
Started Jul 01 04:28:55 PM PDT 24
Finished Jul 01 04:29:09 PM PDT 24
Peak memory 182012 kb
Host smart-f8bfe634-c374-46cd-8276-798bf13d95b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085316813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2085316813
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4126550632
Short name T556
Test name
Test status
Simulation time 42948034 ps
CPU time 0.57 seconds
Started Jul 01 04:29:00 PM PDT 24
Finished Jul 01 04:29:13 PM PDT 24
Peak memory 182096 kb
Host smart-4248442e-c945-4307-b690-b82d0d8a2550
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126550632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4126550632
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3257433044
Short name T513
Test name
Test status
Simulation time 13231634 ps
CPU time 0.55 seconds
Started Jul 01 04:29:00 PM PDT 24
Finished Jul 01 04:29:13 PM PDT 24
Peak memory 181540 kb
Host smart-5bbb0909-c819-427e-98dc-f9fb3eb87c90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257433044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3257433044
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.655277630
Short name T479
Test name
Test status
Simulation time 41398878 ps
CPU time 0.57 seconds
Started Jul 01 04:28:54 PM PDT 24
Finished Jul 01 04:29:09 PM PDT 24
Peak memory 182108 kb
Host smart-31cba879-866c-47bd-af96-dac70eaa6f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655277630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.655277630
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.163471538
Short name T515
Test name
Test status
Simulation time 12914888 ps
CPU time 0.56 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:29:12 PM PDT 24
Peak memory 181756 kb
Host smart-80c802f9-1e79-4bd2-ad8e-13d9602c46ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163471538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.163471538
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1009843897
Short name T458
Test name
Test status
Simulation time 32561681 ps
CPU time 0.54 seconds
Started Jul 01 04:29:17 PM PDT 24
Finished Jul 01 04:29:27 PM PDT 24
Peak memory 182104 kb
Host smart-a877a09d-0a0a-44dc-9504-4a17eeeabbc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009843897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1009843897
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.40963143
Short name T575
Test name
Test status
Simulation time 44270417 ps
CPU time 0.54 seconds
Started Jul 01 04:28:52 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 181528 kb
Host smart-bf3677ec-910f-4597-a1b3-8542285ac791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40963143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.40963143
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3176413305
Short name T482
Test name
Test status
Simulation time 18551674 ps
CPU time 0.58 seconds
Started Jul 01 04:28:57 PM PDT 24
Finished Jul 01 04:29:12 PM PDT 24
Peak memory 182020 kb
Host smart-1ea06795-3a33-4a84-96a9-50bc7d7f8c7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176413305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3176413305
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.764061092
Short name T585
Test name
Test status
Simulation time 16334583 ps
CPU time 0.55 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 182084 kb
Host smart-cac8173b-07a9-4ec9-8433-a974bce93264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764061092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.764061092
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1841898580
Short name T493
Test name
Test status
Simulation time 31562949 ps
CPU time 0.58 seconds
Started Jul 01 04:28:53 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 182256 kb
Host smart-bc2e4557-c084-4269-8c0f-6cf254aa5cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841898580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1841898580
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1967624366
Short name T87
Test name
Test status
Simulation time 22585035 ps
CPU time 0.63 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:55 PM PDT 24
Peak memory 182180 kb
Host smart-86cf2cd9-2661-45bb-9f72-71d0dd841660
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967624366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1967624366
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.232013936
Short name T88
Test name
Test status
Simulation time 855394950 ps
CPU time 3.83 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 193416 kb
Host smart-f1a969f4-da32-4c5a-ba2a-875ca63bf76b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232013936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.232013936
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1721547442
Short name T557
Test name
Test status
Simulation time 34515044 ps
CPU time 0.54 seconds
Started Jul 01 04:28:36 PM PDT 24
Finished Jul 01 04:28:42 PM PDT 24
Peak memory 181832 kb
Host smart-a6f0df52-6580-493a-9934-75f6c3cd043f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721547442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1721547442
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3515217340
Short name T472
Test name
Test status
Simulation time 15433164 ps
CPU time 0.63 seconds
Started Jul 01 04:28:40 PM PDT 24
Finished Jul 01 04:28:47 PM PDT 24
Peak memory 193156 kb
Host smart-4021156c-08d4-4dd3-af60-5931ba7e740e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515217340 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3515217340
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1229356662
Short name T92
Test name
Test status
Simulation time 18482990 ps
CPU time 0.61 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:55 PM PDT 24
Peak memory 182156 kb
Host smart-21032b1d-fb61-4087-8e09-89fb7d914355
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229356662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1229356662
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2528457064
Short name T560
Test name
Test status
Simulation time 53782042 ps
CPU time 0.57 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:01 PM PDT 24
Peak memory 182280 kb
Host smart-34ff72a9-76c3-4dac-9ee0-32779112bb5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528457064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2528457064
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.89836662
Short name T96
Test name
Test status
Simulation time 65460085 ps
CPU time 0.65 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:52 PM PDT 24
Peak memory 191536 kb
Host smart-0a020ba3-89f0-4342-839b-a03a4d24b6b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89836662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_time
r_same_csr_outstanding.89836662
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3044154181
Short name T574
Test name
Test status
Simulation time 50338982 ps
CPU time 2.34 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:55 PM PDT 24
Peak memory 196972 kb
Host smart-1691334e-3ac7-427f-b17e-1bbc8eff6153
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044154181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3044154181
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3834915017
Short name T564
Test name
Test status
Simulation time 44153773 ps
CPU time 0.85 seconds
Started Jul 01 04:28:55 PM PDT 24
Finished Jul 01 04:29:11 PM PDT 24
Peak memory 182752 kb
Host smart-c9ccc028-1e6c-4ba7-aa49-eb8e7468c3b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834915017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3834915017
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1619022824
Short name T547
Test name
Test status
Simulation time 53917827 ps
CPU time 0.56 seconds
Started Jul 01 04:29:01 PM PDT 24
Finished Jul 01 04:29:15 PM PDT 24
Peak memory 182044 kb
Host smart-c481c492-0a32-4479-b5f7-f26680c21afd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619022824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1619022824
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3936369587
Short name T521
Test name
Test status
Simulation time 37722601 ps
CPU time 0.53 seconds
Started Jul 01 04:28:53 PM PDT 24
Finished Jul 01 04:29:08 PM PDT 24
Peak memory 181552 kb
Host smart-706b4046-5116-46b2-a9a9-d1252296f181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936369587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3936369587
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.881228346
Short name T485
Test name
Test status
Simulation time 15768881 ps
CPU time 0.53 seconds
Started Jul 01 04:28:53 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 181980 kb
Host smart-6481501e-3bde-4735-8e22-a0b7da7c85e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881228346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.881228346
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2368964928
Short name T466
Test name
Test status
Simulation time 32256359 ps
CPU time 0.55 seconds
Started Jul 01 04:29:01 PM PDT 24
Finished Jul 01 04:29:14 PM PDT 24
Peak memory 182028 kb
Host smart-949bf901-4a12-4c14-ba56-3525a7265195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368964928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2368964928
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2440261990
Short name T553
Test name
Test status
Simulation time 26827565 ps
CPU time 0.54 seconds
Started Jul 01 04:28:52 PM PDT 24
Finished Jul 01 04:29:06 PM PDT 24
Peak memory 182188 kb
Host smart-bc01f89f-f6d3-4954-8207-2cb120c6cf95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440261990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2440261990
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3777756536
Short name T468
Test name
Test status
Simulation time 45874450 ps
CPU time 0.55 seconds
Started Jul 01 04:28:56 PM PDT 24
Finished Jul 01 04:29:11 PM PDT 24
Peak memory 182060 kb
Host smart-38364401-7920-4968-959e-c58bd404a4aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777756536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3777756536
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1570799461
Short name T460
Test name
Test status
Simulation time 22234321 ps
CPU time 0.54 seconds
Started Jul 01 04:29:04 PM PDT 24
Finished Jul 01 04:29:16 PM PDT 24
Peak memory 181776 kb
Host smart-29710aa4-841d-454c-afed-f30beac386b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570799461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1570799461
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.638545130
Short name T520
Test name
Test status
Simulation time 46976545 ps
CPU time 0.55 seconds
Started Jul 01 04:28:55 PM PDT 24
Finished Jul 01 04:29:10 PM PDT 24
Peak memory 182044 kb
Host smart-b3cf449a-8459-436d-a553-96b3f8cea322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638545130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.638545130
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1838780890
Short name T550
Test name
Test status
Simulation time 14402135 ps
CPU time 0.52 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:55 PM PDT 24
Peak memory 182096 kb
Host smart-643c1036-b61f-4b18-8797-0e66c0302730
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838780890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1838780890
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.308025803
Short name T537
Test name
Test status
Simulation time 12517105 ps
CPU time 0.58 seconds
Started Jul 01 04:28:59 PM PDT 24
Finished Jul 01 04:29:13 PM PDT 24
Peak memory 181548 kb
Host smart-4050bfb5-eeb6-4a68-8031-182a7f441def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308025803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.308025803
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2178155690
Short name T545
Test name
Test status
Simulation time 93339990 ps
CPU time 0.8 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:55 PM PDT 24
Peak memory 194264 kb
Host smart-0ed5e1ab-f359-44c5-904c-88140247b3ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178155690 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2178155690
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.881937783
Short name T502
Test name
Test status
Simulation time 53076552 ps
CPU time 0.66 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:54 PM PDT 24
Peak memory 182336 kb
Host smart-37d94449-0cdd-4b41-9e1c-5155ef5ab8f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881937783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.881937783
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1379166713
Short name T586
Test name
Test status
Simulation time 101441014 ps
CPU time 0.56 seconds
Started Jul 01 04:28:41 PM PDT 24
Finished Jul 01 04:28:49 PM PDT 24
Peak memory 182164 kb
Host smart-b219d6b2-fc62-4849-8947-23b862b9258b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379166713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1379166713
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2931889519
Short name T518
Test name
Test status
Simulation time 21442766 ps
CPU time 0.79 seconds
Started Jul 01 04:28:45 PM PDT 24
Finished Jul 01 04:28:57 PM PDT 24
Peak memory 192956 kb
Host smart-5a6a86c3-1114-4263-96c8-b1ff285ef8cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931889519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2931889519
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3455084390
Short name T476
Test name
Test status
Simulation time 86451686 ps
CPU time 0.99 seconds
Started Jul 01 04:28:35 PM PDT 24
Finished Jul 01 04:28:42 PM PDT 24
Peak memory 195468 kb
Host smart-56386cc3-e582-47be-9abc-9cbdc42ca61b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455084390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3455084390
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3362568632
Short name T516
Test name
Test status
Simulation time 130623049 ps
CPU time 1.42 seconds
Started Jul 01 04:28:51 PM PDT 24
Finished Jul 01 04:29:07 PM PDT 24
Peak memory 194708 kb
Host smart-fb5ef1bb-1f95-45a1-9364-d72568dcccc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362568632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3362568632
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2364624327
Short name T30
Test name
Test status
Simulation time 16539871 ps
CPU time 0.64 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:53 PM PDT 24
Peak memory 193452 kb
Host smart-64984302-424f-4957-a8ff-eb7085366c3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364624327 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2364624327
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2580258568
Short name T517
Test name
Test status
Simulation time 46766327 ps
CPU time 0.58 seconds
Started Jul 01 04:28:50 PM PDT 24
Finished Jul 01 04:29:05 PM PDT 24
Peak memory 182184 kb
Host smart-e306b63b-e5b7-42ec-91c1-d344ecdd0e2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580258568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2580258568
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2026922988
Short name T580
Test name
Test status
Simulation time 14412419 ps
CPU time 0.57 seconds
Started Jul 01 04:28:39 PM PDT 24
Finished Jul 01 04:28:47 PM PDT 24
Peak memory 182100 kb
Host smart-2c646802-b6e3-4bbb-883d-b56c77985a93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026922988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2026922988
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3807096171
Short name T559
Test name
Test status
Simulation time 79013646 ps
CPU time 0.6 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 191132 kb
Host smart-47d753d9-a607-48aa-880b-6ed0301cd1dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807096171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3807096171
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.726382139
Short name T514
Test name
Test status
Simulation time 43269452 ps
CPU time 2.02 seconds
Started Jul 01 04:28:40 PM PDT 24
Finished Jul 01 04:28:49 PM PDT 24
Peak memory 196952 kb
Host smart-b91ddf71-1e2f-485f-9fe5-c0ec1de9a6c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726382139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.726382139
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2113121131
Short name T27
Test name
Test status
Simulation time 301339204 ps
CPU time 1.03 seconds
Started Jul 01 04:28:45 PM PDT 24
Finished Jul 01 04:28:57 PM PDT 24
Peak memory 194364 kb
Host smart-40b8536e-cf8d-41d3-8c13-bbf09665b967
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113121131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2113121131
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3329102712
Short name T490
Test name
Test status
Simulation time 305208451 ps
CPU time 0.97 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:52 PM PDT 24
Peak memory 196604 kb
Host smart-b53dce59-477b-4a5d-bb6f-46c59ccdf73e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329102712 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3329102712
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3709514177
Short name T558
Test name
Test status
Simulation time 25711465 ps
CPU time 0.59 seconds
Started Jul 01 04:28:41 PM PDT 24
Finished Jul 01 04:28:50 PM PDT 24
Peak memory 182172 kb
Host smart-6272bd07-f475-4c3c-b168-6c4e091661d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709514177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3709514177
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3832759084
Short name T533
Test name
Test status
Simulation time 90950083 ps
CPU time 0.58 seconds
Started Jul 01 04:28:38 PM PDT 24
Finished Jul 01 04:28:45 PM PDT 24
Peak memory 181456 kb
Host smart-6b160ef9-84df-4fc3-9f8d-45216aeebe04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832759084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3832759084
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3019636327
Short name T103
Test name
Test status
Simulation time 78867094 ps
CPU time 0.73 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 191132 kb
Host smart-efb04acc-15cb-4267-9de3-3edc0ef42d53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019636327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3019636327
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3914281997
Short name T486
Test name
Test status
Simulation time 144370519 ps
CPU time 0.94 seconds
Started Jul 01 04:28:38 PM PDT 24
Finished Jul 01 04:28:45 PM PDT 24
Peak memory 194292 kb
Host smart-de924045-492a-44ff-b7d8-e91075672fae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914281997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3914281997
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.670530587
Short name T546
Test name
Test status
Simulation time 2795659519 ps
CPU time 1.99 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:55 PM PDT 24
Peak memory 182708 kb
Host smart-adefe0b8-e241-4a6f-a876-fcfd49e8832e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670530587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.670530587
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2775405478
Short name T488
Test name
Test status
Simulation time 49093848 ps
CPU time 1.11 seconds
Started Jul 01 04:28:44 PM PDT 24
Finished Jul 01 04:28:56 PM PDT 24
Peak memory 196976 kb
Host smart-0afb1841-2110-47c1-8b54-e0e9e5c7f6c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775405478 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2775405478
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.757707956
Short name T507
Test name
Test status
Simulation time 57805219 ps
CPU time 0.56 seconds
Started Jul 01 04:28:41 PM PDT 24
Finished Jul 01 04:28:50 PM PDT 24
Peak memory 182176 kb
Host smart-4a3f1305-9374-4415-ab63-f0053ac5316d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757707956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.757707956
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3635243124
Short name T462
Test name
Test status
Simulation time 11912419 ps
CPU time 0.55 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:03 PM PDT 24
Peak memory 182080 kb
Host smart-e9d312d8-7e23-41c8-9955-444a246b27aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635243124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3635243124
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2034399768
Short name T505
Test name
Test status
Simulation time 76326051 ps
CPU time 0.87 seconds
Started Jul 01 04:28:45 PM PDT 24
Finished Jul 01 04:28:58 PM PDT 24
Peak memory 191268 kb
Host smart-be0cd483-344c-4ef5-99ea-895349365fb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034399768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2034399768
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2489219818
Short name T536
Test name
Test status
Simulation time 224199118 ps
CPU time 1.05 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:01 PM PDT 24
Peak memory 195484 kb
Host smart-5bddb529-3aba-4c04-b249-3caa3703edeb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489219818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2489219818
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.70880046
Short name T491
Test name
Test status
Simulation time 542615660 ps
CPU time 1.4 seconds
Started Jul 01 04:28:48 PM PDT 24
Finished Jul 01 04:29:02 PM PDT 24
Peak memory 193956 kb
Host smart-bfb5a95b-5874-49cb-85d4-030429930e94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70880046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_intg
_err.70880046
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2794193034
Short name T46
Test name
Test status
Simulation time 129191529 ps
CPU time 0.85 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:51 PM PDT 24
Peak memory 196292 kb
Host smart-56062d24-5a33-4d6f-9418-e49285b53982
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794193034 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2794193034
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.714783596
Short name T94
Test name
Test status
Simulation time 15714594 ps
CPU time 0.59 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:51 PM PDT 24
Peak memory 182168 kb
Host smart-11cd3e29-35cc-407b-853e-e9fa2cfcd3d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714783596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.714783596
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2745291222
Short name T484
Test name
Test status
Simulation time 19449764 ps
CPU time 0.58 seconds
Started Jul 01 04:28:47 PM PDT 24
Finished Jul 01 04:29:00 PM PDT 24
Peak memory 182112 kb
Host smart-954226f4-bfe2-4ac1-a7fd-d7e98e78a387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745291222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2745291222
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3290187461
Short name T98
Test name
Test status
Simulation time 160194001 ps
CPU time 0.75 seconds
Started Jul 01 04:28:43 PM PDT 24
Finished Jul 01 04:28:54 PM PDT 24
Peak memory 192744 kb
Host smart-6bf489f6-d667-4159-94ba-7ee6d30b7573
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290187461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3290187461
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1569744367
Short name T554
Test name
Test status
Simulation time 152813553 ps
CPU time 1.64 seconds
Started Jul 01 04:28:42 PM PDT 24
Finished Jul 01 04:28:52 PM PDT 24
Peak memory 196936 kb
Host smart-71910e7a-3965-49a2-9b97-f36b426e9bd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569744367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1569744367
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3079816043
Short name T512
Test name
Test status
Simulation time 188003827 ps
CPU time 1.26 seconds
Started Jul 01 04:28:49 PM PDT 24
Finished Jul 01 04:29:04 PM PDT 24
Peak memory 182640 kb
Host smart-712e67e4-cd17-406a-aa89-d1a4a91cb22f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079816043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3079816043
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1705804366
Short name T181
Test name
Test status
Simulation time 26656241489 ps
CPU time 37.94 seconds
Started Jul 01 04:36:23 PM PDT 24
Finished Jul 01 04:37:12 PM PDT 24
Peak memory 183052 kb
Host smart-c49faec9-75fc-4ec7-a890-aa7b67be0ea0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705804366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1705804366
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.4191708732
Short name T414
Test name
Test status
Simulation time 781011532040 ps
CPU time 288.36 seconds
Started Jul 01 04:36:07 PM PDT 24
Finished Jul 01 04:41:08 PM PDT 24
Peak memory 183104 kb
Host smart-ca65e09a-16cd-4683-89cc-cf9d2e9254c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191708732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.4191708732
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.676753447
Short name T381
Test name
Test status
Simulation time 43851436 ps
CPU time 0.62 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 04:36:32 PM PDT 24
Peak memory 182920 kb
Host smart-1b94630e-564c-41e5-97a8-ce54f43f9c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676753447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.676753447
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.431271350
Short name T36
Test name
Test status
Simulation time 180165619152 ps
CPU time 498.67 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 04:44:50 PM PDT 24
Peak memory 206032 kb
Host smart-19a1ea0d-9d9c-435e-8a25-4de1c28bebbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431271350 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.431271350
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1843495765
Short name T42
Test name
Test status
Simulation time 233423688310 ps
CPU time 284.64 seconds
Started Jul 01 04:36:11 PM PDT 24
Finished Jul 01 04:41:11 PM PDT 24
Peak memory 182932 kb
Host smart-b1c31ea1-f16b-4451-b3b5-184ecb1ddb53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843495765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1843495765
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3771589775
Short name T449
Test name
Test status
Simulation time 35673183864 ps
CPU time 14.16 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:36:42 PM PDT 24
Peak memory 183108 kb
Host smart-3d9522c9-73df-47e3-9696-6c706a5c7e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771589775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3771589775
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3438214058
Short name T302
Test name
Test status
Simulation time 238290120036 ps
CPU time 216.8 seconds
Started Jul 01 04:36:15 PM PDT 24
Finished Jul 01 04:40:06 PM PDT 24
Peak memory 191296 kb
Host smart-4777697f-c915-45e8-ac6b-e74acf91706b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438214058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3438214058
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2224524785
Short name T320
Test name
Test status
Simulation time 96469024006 ps
CPU time 308 seconds
Started Jul 01 04:36:12 PM PDT 24
Finished Jul 01 04:41:35 PM PDT 24
Peak memory 191312 kb
Host smart-a48267c8-ee4a-4c90-8ab7-3c554be69497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224524785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2224524785
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1525138234
Short name T16
Test name
Test status
Simulation time 435347042 ps
CPU time 1.31 seconds
Started Jul 01 04:36:10 PM PDT 24
Finished Jul 01 04:36:25 PM PDT 24
Peak memory 214528 kb
Host smart-c8f6115b-97de-455d-974f-be98af32fa2b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525138234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1525138234
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.821586318
Short name T277
Test name
Test status
Simulation time 1035383123874 ps
CPU time 538.74 seconds
Started Jul 01 04:36:16 PM PDT 24
Finished Jul 01 04:45:29 PM PDT 24
Peak memory 191288 kb
Host smart-7820f7e0-6aee-4808-8d90-2053a1592436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821586318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.821586318
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.4013766930
Short name T206
Test name
Test status
Simulation time 4301645313 ps
CPU time 8.38 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 04:36:40 PM PDT 24
Peak memory 182984 kb
Host smart-62556f9e-84b9-4248-80c9-24aa45310be7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013766930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.4013766930
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3048108975
Short name T378
Test name
Test status
Simulation time 191853469040 ps
CPU time 152.31 seconds
Started Jul 01 04:36:20 PM PDT 24
Finished Jul 01 04:39:06 PM PDT 24
Peak memory 183216 kb
Host smart-853e2db0-a002-4899-ae42-de4d8e2c032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048108975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3048108975
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1241635475
Short name T165
Test name
Test status
Simulation time 1023881714888 ps
CPU time 1191.45 seconds
Started Jul 01 04:36:23 PM PDT 24
Finished Jul 01 04:56:26 PM PDT 24
Peak memory 191284 kb
Host smart-275307a9-0a72-443e-a354-3fcb8de2148e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241635475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1241635475
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3531263450
Short name T78
Test name
Test status
Simulation time 62305716308 ps
CPU time 27.9 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:37:09 PM PDT 24
Peak memory 191400 kb
Host smart-850d23b9-5a97-4cf9-a311-ade30527c142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531263450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3531263450
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.3036435492
Short name T79
Test name
Test status
Simulation time 397642448329 ps
CPU time 1141.2 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 04:55:33 PM PDT 24
Peak memory 213880 kb
Host smart-d560abaa-12c1-4ab3-a2fb-c0f854d637c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036435492 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.3036435492
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.4162092664
Short name T396
Test name
Test status
Simulation time 287824386406 ps
CPU time 1793.87 seconds
Started Jul 01 04:36:57 PM PDT 24
Finished Jul 01 05:06:55 PM PDT 24
Peak memory 183092 kb
Host smart-4b952421-d655-477d-9ba5-e3d0aeaeeb48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162092664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4162092664
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2950238366
Short name T142
Test name
Test status
Simulation time 79925497567 ps
CPU time 66.4 seconds
Started Jul 01 04:37:01 PM PDT 24
Finished Jul 01 04:38:11 PM PDT 24
Peak memory 183092 kb
Host smart-53fccdee-ed30-49d4-961d-490238ef8632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950238366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2950238366
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1781721799
Short name T415
Test name
Test status
Simulation time 5612334232 ps
CPU time 8.25 seconds
Started Jul 01 04:36:58 PM PDT 24
Finished Jul 01 04:37:10 PM PDT 24
Peak memory 183088 kb
Host smart-23d95763-230c-4e15-bb06-874320d9127b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781721799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1781721799
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3384938606
Short name T196
Test name
Test status
Simulation time 77439599135 ps
CPU time 84.22 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:38:29 PM PDT 24
Peak memory 191172 kb
Host smart-100dba0e-cc68-422e-b3e3-201c4b0fa4d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384938606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3384938606
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.76625347
Short name T348
Test name
Test status
Simulation time 269405944523 ps
CPU time 1250.95 seconds
Started Jul 01 04:36:57 PM PDT 24
Finished Jul 01 04:57:52 PM PDT 24
Peak memory 191264 kb
Host smart-083587a6-7360-4482-a819-88760ea67d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76625347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.76625347
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1921024886
Short name T106
Test name
Test status
Simulation time 1487228750271 ps
CPU time 319.82 seconds
Started Jul 01 04:37:09 PM PDT 24
Finished Jul 01 04:42:32 PM PDT 24
Peak memory 191272 kb
Host smart-e4ab6601-394a-48f5-98f3-d2cfc0100648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921024886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1921024886
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.4241245050
Short name T313
Test name
Test status
Simulation time 298450445785 ps
CPU time 157.59 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:39:19 PM PDT 24
Peak memory 182984 kb
Host smart-460fda01-7559-41e4-af4b-8c95072a3cd2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241245050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.4241245050
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3404262218
Short name T397
Test name
Test status
Simulation time 81517056410 ps
CPU time 108.78 seconds
Started Jul 01 04:36:30 PM PDT 24
Finished Jul 01 04:38:26 PM PDT 24
Peak memory 182996 kb
Host smart-af12f914-bc22-49ba-9aeb-537a2ab051ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404262218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3404262218
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1304285018
Short name T210
Test name
Test status
Simulation time 418999032014 ps
CPU time 276.65 seconds
Started Jul 01 04:36:22 PM PDT 24
Finished Jul 01 04:41:11 PM PDT 24
Peak memory 191372 kb
Host smart-991b45d6-ca65-45e2-89af-c6c64e966b70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304285018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1304285018
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3999779803
Short name T176
Test name
Test status
Simulation time 65679401843 ps
CPU time 48.26 seconds
Started Jul 01 04:36:24 PM PDT 24
Finished Jul 01 04:37:23 PM PDT 24
Peak memory 191276 kb
Host smart-431eb236-d7ff-44fa-bdc9-46b4a8fb493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999779803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3999779803
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.2518931921
Short name T427
Test name
Test status
Simulation time 79972188914 ps
CPU time 113.32 seconds
Started Jul 01 04:37:07 PM PDT 24
Finished Jul 01 04:39:02 PM PDT 24
Peak memory 191192 kb
Host smart-17ee783b-a442-4c51-b84c-c187c4c7069b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518931921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2518931921
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1182073469
Short name T244
Test name
Test status
Simulation time 260370078333 ps
CPU time 168.64 seconds
Started Jul 01 04:37:09 PM PDT 24
Finished Jul 01 04:40:01 PM PDT 24
Peak memory 191400 kb
Host smart-97fbc50a-7bd7-4a9b-a7e0-8429d7bc1e86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182073469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1182073469
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3629529340
Short name T224
Test name
Test status
Simulation time 405532345206 ps
CPU time 576.56 seconds
Started Jul 01 04:37:07 PM PDT 24
Finished Jul 01 04:46:46 PM PDT 24
Peak memory 191308 kb
Host smart-7f28421b-99d5-470d-8292-5b98ce734d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629529340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3629529340
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.42468884
Short name T325
Test name
Test status
Simulation time 224355298196 ps
CPU time 516.13 seconds
Started Jul 01 04:37:06 PM PDT 24
Finished Jul 01 04:45:44 PM PDT 24
Peak memory 191348 kb
Host smart-861e9ec8-a1f0-45f9-8ae9-cea2039b3695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42468884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.42468884
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1729994536
Short name T149
Test name
Test status
Simulation time 556535669440 ps
CPU time 1323.67 seconds
Started Jul 01 04:37:09 PM PDT 24
Finished Jul 01 04:59:16 PM PDT 24
Peak memory 191276 kb
Host smart-ca79d957-16f0-4568-9f3b-a8506578cd1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729994536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1729994536
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.4223789818
Short name T2
Test name
Test status
Simulation time 136363421032 ps
CPU time 401.24 seconds
Started Jul 01 04:37:07 PM PDT 24
Finished Jul 01 04:43:50 PM PDT 24
Peak memory 191316 kb
Host smart-d14d6540-d990-4c95-97ef-3fd9b6369d20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223789818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.4223789818
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.4067102735
Short name T331
Test name
Test status
Simulation time 538652035727 ps
CPU time 289.93 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 04:41:23 PM PDT 24
Peak memory 182980 kb
Host smart-3efa08d1-9001-4a00-84c4-b9add40d8020
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067102735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.4067102735
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2084553274
Short name T355
Test name
Test status
Simulation time 92610025305 ps
CPU time 42.79 seconds
Started Jul 01 04:36:20 PM PDT 24
Finished Jul 01 04:37:16 PM PDT 24
Peak memory 183208 kb
Host smart-19394848-3e6a-4070-b532-540c14899fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084553274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2084553274
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2338496756
Short name T295
Test name
Test status
Simulation time 324271485564 ps
CPU time 417.02 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:43:28 PM PDT 24
Peak memory 183104 kb
Host smart-9153d80f-842b-471a-89c8-2ebc6eca732c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338496756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2338496756
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.2037021152
Short name T388
Test name
Test status
Simulation time 43380591828 ps
CPU time 59.73 seconds
Started Jul 01 04:36:39 PM PDT 24
Finished Jul 01 04:37:42 PM PDT 24
Peak memory 183196 kb
Host smart-12cfde25-0708-490b-8106-3fd3a2379f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037021152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.2037021152
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.3211590487
Short name T110
Test name
Test status
Simulation time 437225641166 ps
CPU time 508.53 seconds
Started Jul 01 04:37:09 PM PDT 24
Finished Jul 01 04:45:40 PM PDT 24
Peak memory 191284 kb
Host smart-46adc5e2-3450-4904-924b-f50645fa40c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211590487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3211590487
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2585690311
Short name T426
Test name
Test status
Simulation time 297044281075 ps
CPU time 1519.81 seconds
Started Jul 01 04:37:08 PM PDT 24
Finished Jul 01 05:02:31 PM PDT 24
Peak memory 183092 kb
Host smart-d8d0e8a5-7ff8-4409-8a7d-4aeda497067a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585690311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2585690311
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3796412957
Short name T225
Test name
Test status
Simulation time 284764582179 ps
CPU time 215.57 seconds
Started Jul 01 04:37:09 PM PDT 24
Finished Jul 01 04:40:48 PM PDT 24
Peak memory 192612 kb
Host smart-4f31df87-3698-4e65-ba49-2d42a152b4fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796412957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3796412957
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1478522523
Short name T344
Test name
Test status
Simulation time 386183117913 ps
CPU time 850.07 seconds
Started Jul 01 04:37:05 PM PDT 24
Finished Jul 01 04:51:17 PM PDT 24
Peak memory 191292 kb
Host smart-ed1f9860-78d6-4df2-ab6c-7d369a06a1f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478522523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1478522523
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1130701290
Short name T136
Test name
Test status
Simulation time 585711206480 ps
CPU time 564.88 seconds
Started Jul 01 04:37:06 PM PDT 24
Finished Jul 01 04:46:33 PM PDT 24
Peak memory 191292 kb
Host smart-28fadb6b-6f6d-4d04-888c-b9e99599dfbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130701290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1130701290
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1233594262
Short name T200
Test name
Test status
Simulation time 40887108796 ps
CPU time 143.86 seconds
Started Jul 01 04:37:07 PM PDT 24
Finished Jul 01 04:39:33 PM PDT 24
Peak memory 191524 kb
Host smart-4e1862af-61fe-473c-8f39-b9e974f21d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233594262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1233594262
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1807469046
Short name T163
Test name
Test status
Simulation time 112776475398 ps
CPU time 179 seconds
Started Jul 01 04:37:07 PM PDT 24
Finished Jul 01 04:40:08 PM PDT 24
Peak memory 191284 kb
Host smart-11c16f03-8b02-45e0-8d7c-d9a0687bd5a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807469046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1807469046
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3522812343
Short name T133
Test name
Test status
Simulation time 212377554038 ps
CPU time 202.16 seconds
Started Jul 01 04:37:08 PM PDT 24
Finished Jul 01 04:40:33 PM PDT 24
Peak memory 191192 kb
Host smart-95ce1764-f359-4d42-96b9-37172cb287e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522812343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3522812343
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1053806017
Short name T10
Test name
Test status
Simulation time 134705459921 ps
CPU time 218.36 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:40:09 PM PDT 24
Peak memory 183184 kb
Host smart-430f78bb-58ce-41a6-a1c9-c1d12cfa8989
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053806017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1053806017
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.647393556
Short name T457
Test name
Test status
Simulation time 150031338408 ps
CPU time 205.65 seconds
Started Jul 01 04:36:29 PM PDT 24
Finished Jul 01 04:40:02 PM PDT 24
Peak memory 183132 kb
Host smart-c6cec115-5163-4462-aacb-c92de7375d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647393556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.647393556
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.1762281749
Short name T245
Test name
Test status
Simulation time 472088988466 ps
CPU time 494.1 seconds
Started Jul 01 04:36:29 PM PDT 24
Finished Jul 01 04:44:51 PM PDT 24
Peak memory 191256 kb
Host smart-e292e177-bd5e-4b1b-a7c8-d5e15bd861d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762281749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.1762281749
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.3783383793
Short name T40
Test name
Test status
Simulation time 23091395549 ps
CPU time 195.3 seconds
Started Jul 01 04:36:16 PM PDT 24
Finished Jul 01 04:39:46 PM PDT 24
Peak memory 197272 kb
Host smart-de7969d9-83b1-4835-b0d2-5b3b88b0724b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783383793 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.3783383793
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2498943454
Short name T253
Test name
Test status
Simulation time 44109735087 ps
CPU time 77.2 seconds
Started Jul 01 04:37:05 PM PDT 24
Finished Jul 01 04:38:24 PM PDT 24
Peak memory 183196 kb
Host smart-4242824f-321f-43d0-8bb5-0cd06bc03cb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498943454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2498943454
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.4155414519
Short name T171
Test name
Test status
Simulation time 120621991657 ps
CPU time 255.54 seconds
Started Jul 01 04:37:07 PM PDT 24
Finished Jul 01 04:41:25 PM PDT 24
Peak memory 191180 kb
Host smart-af16437d-ebb0-4d52-a5e0-288ac68d43be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155414519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.4155414519
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2176152796
Short name T270
Test name
Test status
Simulation time 11439626289 ps
CPU time 30.17 seconds
Started Jul 01 04:37:06 PM PDT 24
Finished Jul 01 04:37:38 PM PDT 24
Peak memory 191288 kb
Host smart-3f337637-3a37-4ff0-9df0-fca75f4ead5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176152796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2176152796
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3835919388
Short name T327
Test name
Test status
Simulation time 87331231382 ps
CPU time 138.13 seconds
Started Jul 01 04:37:10 PM PDT 24
Finished Jul 01 04:39:31 PM PDT 24
Peak memory 191264 kb
Host smart-10c332ed-0577-4acb-8fcc-133efdff0a2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835919388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3835919388
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2316483463
Short name T281
Test name
Test status
Simulation time 184058251599 ps
CPU time 164.6 seconds
Started Jul 01 04:37:12 PM PDT 24
Finished Jul 01 04:39:59 PM PDT 24
Peak memory 191184 kb
Host smart-483ac660-666d-4ec5-86a7-df5c8332ee8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316483463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2316483463
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1840081953
Short name T453
Test name
Test status
Simulation time 107455080965 ps
CPU time 202.93 seconds
Started Jul 01 04:37:12 PM PDT 24
Finished Jul 01 04:40:37 PM PDT 24
Peak memory 191284 kb
Host smart-9669630a-0597-4a6a-9690-95b8362eb59c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840081953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1840081953
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3128375623
Short name T416
Test name
Test status
Simulation time 92410311764 ps
CPU time 133.04 seconds
Started Jul 01 04:37:14 PM PDT 24
Finished Jul 01 04:39:29 PM PDT 24
Peak memory 191232 kb
Host smart-30799926-20b8-4c8b-b9ce-98dc3f67119c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128375623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3128375623
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2028427690
Short name T65
Test name
Test status
Simulation time 442459061859 ps
CPU time 446.95 seconds
Started Jul 01 04:37:12 PM PDT 24
Finished Jul 01 04:44:41 PM PDT 24
Peak memory 191332 kb
Host smart-39b5c8f5-dcab-412a-af1f-cddc9c6645be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028427690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2028427690
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1266306028
Short name T8
Test name
Test status
Simulation time 66315936976 ps
CPU time 22.71 seconds
Started Jul 01 04:37:14 PM PDT 24
Finished Jul 01 04:37:39 PM PDT 24
Peak memory 183088 kb
Host smart-42425da5-a71d-45a4-a011-c16a2939c012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266306028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1266306028
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2533148601
Short name T404
Test name
Test status
Simulation time 122163579033 ps
CPU time 183 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 04:39:36 PM PDT 24
Peak memory 183052 kb
Host smart-eca79b7a-e6b9-4e19-aa21-f6f1f4f046e9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533148601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2533148601
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.523912725
Short name T373
Test name
Test status
Simulation time 11761101487 ps
CPU time 5.01 seconds
Started Jul 01 04:36:19 PM PDT 24
Finished Jul 01 04:36:37 PM PDT 24
Peak memory 183008 kb
Host smart-daf81ba5-43d0-455e-bda9-2e46af76ffa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523912725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.523912725
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3916548587
Short name T107
Test name
Test status
Simulation time 6513461503 ps
CPU time 10.05 seconds
Started Jul 01 04:36:20 PM PDT 24
Finished Jul 01 04:36:43 PM PDT 24
Peak memory 183084 kb
Host smart-f1a96795-d4b6-4d94-ac36-d8b616260db6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916548587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3916548587
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1846679144
Short name T431
Test name
Test status
Simulation time 660945274 ps
CPU time 1.19 seconds
Started Jul 01 04:36:38 PM PDT 24
Finished Jul 01 04:36:44 PM PDT 24
Peak memory 192260 kb
Host smart-a8c3a559-d695-41bb-a8b4-9c902b1a927d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846679144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1846679144
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.2799579760
Short name T125
Test name
Test status
Simulation time 138739667193 ps
CPU time 621.75 seconds
Started Jul 01 04:37:14 PM PDT 24
Finished Jul 01 04:47:38 PM PDT 24
Peak memory 191192 kb
Host smart-c5725885-10dd-4455-b53b-b61d94dc8a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799579760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2799579760
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1855733187
Short name T43
Test name
Test status
Simulation time 77547055783 ps
CPU time 29.61 seconds
Started Jul 01 04:37:14 PM PDT 24
Finished Jul 01 04:37:46 PM PDT 24
Peak memory 182992 kb
Host smart-24e5e5b2-8d7a-4a37-a50e-8943d10e79c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855733187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1855733187
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1624711183
Short name T296
Test name
Test status
Simulation time 100227232870 ps
CPU time 135.1 seconds
Started Jul 01 04:37:14 PM PDT 24
Finished Jul 01 04:39:31 PM PDT 24
Peak memory 191224 kb
Host smart-85ccdbdb-5a22-403b-a441-e6b89ff1d95b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624711183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1624711183
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3120057844
Short name T52
Test name
Test status
Simulation time 108492201143 ps
CPU time 279.01 seconds
Started Jul 01 04:37:12 PM PDT 24
Finished Jul 01 04:41:53 PM PDT 24
Peak memory 191184 kb
Host smart-ee3e0c7b-3bd5-463f-a9ee-ca1bf06a9d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120057844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3120057844
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2737901602
Short name T435
Test name
Test status
Simulation time 105522978733 ps
CPU time 47.04 seconds
Started Jul 01 04:37:12 PM PDT 24
Finished Jul 01 04:38:01 PM PDT 24
Peak memory 183084 kb
Host smart-2e82ec75-f100-4143-b2c4-fe7c7824cbd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737901602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2737901602
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3197136036
Short name T193
Test name
Test status
Simulation time 1781323516 ps
CPU time 3.5 seconds
Started Jul 01 04:37:14 PM PDT 24
Finished Jul 01 04:37:20 PM PDT 24
Peak memory 182804 kb
Host smart-1253dba5-eab8-4113-80a1-cf9121f6744a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197136036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3197136036
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.4284606721
Short name T263
Test name
Test status
Simulation time 349681120803 ps
CPU time 1111.56 seconds
Started Jul 01 04:37:11 PM PDT 24
Finished Jul 01 04:55:45 PM PDT 24
Peak memory 191172 kb
Host smart-3fba976f-e0e9-48f0-abd5-f85b311e9b70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284606721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.4284606721
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1817347903
Short name T432
Test name
Test status
Simulation time 530843052266 ps
CPU time 296.83 seconds
Started Jul 01 04:36:16 PM PDT 24
Finished Jul 01 04:41:27 PM PDT 24
Peak memory 183252 kb
Host smart-a72f1263-0ebd-4f89-8789-39995b5c3c67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817347903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1817347903
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1892132492
Short name T1
Test name
Test status
Simulation time 137435488728 ps
CPU time 177.09 seconds
Started Jul 01 04:36:15 PM PDT 24
Finished Jul 01 04:39:26 PM PDT 24
Peak memory 183096 kb
Host smart-1df78c5f-09f4-4638-987e-b4f7fafd7627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892132492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1892132492
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3378156383
Short name T201
Test name
Test status
Simulation time 38592383111 ps
CPU time 67.23 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:37:38 PM PDT 24
Peak memory 191292 kb
Host smart-7960d3eb-46d4-4309-9058-78a094dca125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378156383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3378156383
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3698396394
Short name T409
Test name
Test status
Simulation time 938385082056 ps
CPU time 350.66 seconds
Started Jul 01 04:36:24 PM PDT 24
Finished Jul 01 04:42:25 PM PDT 24
Peak memory 191192 kb
Host smart-e9d0e046-2c23-4530-892a-37ee8a90504b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698396394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3698396394
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.432455120
Short name T5
Test name
Test status
Simulation time 500384148079 ps
CPU time 959.03 seconds
Started Jul 01 04:37:15 PM PDT 24
Finished Jul 01 04:53:16 PM PDT 24
Peak memory 191164 kb
Host smart-d984c775-a701-4795-87a6-60590aec62eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432455120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.432455120
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3376675832
Short name T134
Test name
Test status
Simulation time 67525628224 ps
CPU time 238.18 seconds
Started Jul 01 04:37:18 PM PDT 24
Finished Jul 01 04:41:18 PM PDT 24
Peak memory 191280 kb
Host smart-d9a0b84c-d63d-49ff-99af-c0bdaf9f9fc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376675832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3376675832
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2361094728
Short name T229
Test name
Test status
Simulation time 286808125379 ps
CPU time 320.36 seconds
Started Jul 01 04:37:19 PM PDT 24
Finished Jul 01 04:42:41 PM PDT 24
Peak memory 191192 kb
Host smart-c100be28-2324-4248-b091-1426b771bc2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361094728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2361094728
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2336009268
Short name T330
Test name
Test status
Simulation time 627075463879 ps
CPU time 582.93 seconds
Started Jul 01 04:37:17 PM PDT 24
Finished Jul 01 04:47:02 PM PDT 24
Peak memory 191292 kb
Host smart-a64e7806-bf2c-4ddf-bfbe-6af3aca74c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336009268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2336009268
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3112094789
Short name T248
Test name
Test status
Simulation time 58066703730 ps
CPU time 912.5 seconds
Started Jul 01 04:37:20 PM PDT 24
Finished Jul 01 04:52:34 PM PDT 24
Peak memory 191192 kb
Host smart-2e08f055-15ae-40fe-a218-ec1e1aa86120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112094789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3112094789
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3567959530
Short name T212
Test name
Test status
Simulation time 149462060212 ps
CPU time 244.21 seconds
Started Jul 01 04:37:18 PM PDT 24
Finished Jul 01 04:41:24 PM PDT 24
Peak memory 191280 kb
Host smart-2b58b1be-7e52-436b-8bb2-76a2f55a41c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567959530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3567959530
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.58178797
Short name T175
Test name
Test status
Simulation time 11444147164 ps
CPU time 6.33 seconds
Started Jul 01 04:36:20 PM PDT 24
Finished Jul 01 04:36:39 PM PDT 24
Peak memory 183088 kb
Host smart-4ec13df8-ccb0-48b9-89b1-8f07b9f0c226
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58178797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.rv_timer_cfg_update_on_fly.58178797
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.4016498620
Short name T401
Test name
Test status
Simulation time 156100074003 ps
CPU time 208.92 seconds
Started Jul 01 04:36:34 PM PDT 24
Finished Jul 01 04:40:08 PM PDT 24
Peak memory 183108 kb
Host smart-80b17bad-98fd-489f-84b4-8aba30c2621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016498620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.4016498620
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1406328661
Short name T64
Test name
Test status
Simulation time 355899230640 ps
CPU time 509.97 seconds
Started Jul 01 04:36:43 PM PDT 24
Finished Jul 01 04:45:17 PM PDT 24
Peak memory 194796 kb
Host smart-2cb1aabe-3bef-4596-bebc-22e98fda0904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406328661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1406328661
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/161.rv_timer_random.3354236408
Short name T144
Test name
Test status
Simulation time 208831295310 ps
CPU time 109.81 seconds
Started Jul 01 04:37:16 PM PDT 24
Finished Jul 01 04:39:08 PM PDT 24
Peak memory 193896 kb
Host smart-9a9e30a7-b4ff-45c4-ac1e-d4bfbc433bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354236408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3354236408
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.76221833
Short name T304
Test name
Test status
Simulation time 2617985466324 ps
CPU time 1654.9 seconds
Started Jul 01 04:37:16 PM PDT 24
Finished Jul 01 05:04:53 PM PDT 24
Peak memory 191288 kb
Host smart-9b51a373-2ff4-420c-9892-4e8d0eb1ca86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76221833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.76221833
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.906444553
Short name T162
Test name
Test status
Simulation time 104575155357 ps
CPU time 224.36 seconds
Started Jul 01 04:37:17 PM PDT 24
Finished Jul 01 04:41:03 PM PDT 24
Peak memory 191372 kb
Host smart-28e2b2bc-7afa-42e4-a5b7-f9a4c8533b2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906444553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.906444553
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3704388617
Short name T390
Test name
Test status
Simulation time 89040854782 ps
CPU time 68.53 seconds
Started Jul 01 04:37:25 PM PDT 24
Finished Jul 01 04:38:35 PM PDT 24
Peak memory 183168 kb
Host smart-ce2933ad-dc9b-42e3-b738-077cd8aa8c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704388617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3704388617
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1983518805
Short name T391
Test name
Test status
Simulation time 21386508500 ps
CPU time 30.46 seconds
Started Jul 01 04:36:22 PM PDT 24
Finished Jul 01 04:37:05 PM PDT 24
Peak memory 183096 kb
Host smart-9be5764f-df6c-4540-b08d-cf5af8068870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983518805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1983518805
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.400998513
Short name T26
Test name
Test status
Simulation time 177380999238 ps
CPU time 745.5 seconds
Started Jul 01 04:36:40 PM PDT 24
Finished Jul 01 04:49:09 PM PDT 24
Peak memory 191300 kb
Host smart-ace87688-ce09-4dcf-934b-dd30144e4405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400998513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.400998513
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1097948037
Short name T408
Test name
Test status
Simulation time 153587980697 ps
CPU time 228.29 seconds
Started Jul 01 04:36:32 PM PDT 24
Finished Jul 01 04:40:27 PM PDT 24
Peak memory 194808 kb
Host smart-ef8479c1-9340-4c6b-bc44-7167c3e5ab6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097948037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1097948037
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.1911318749
Short name T232
Test name
Test status
Simulation time 132660085755 ps
CPU time 191.32 seconds
Started Jul 01 04:37:28 PM PDT 24
Finished Jul 01 04:40:41 PM PDT 24
Peak memory 195108 kb
Host smart-98f6dd1c-27c6-411e-bfbe-91ca3ffacff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911318749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1911318749
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2804566321
Short name T256
Test name
Test status
Simulation time 100676338314 ps
CPU time 116.19 seconds
Started Jul 01 04:37:24 PM PDT 24
Finished Jul 01 04:39:22 PM PDT 24
Peak memory 183080 kb
Host smart-91311d55-bc97-4a67-be43-5fe7e10528dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804566321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2804566321
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3107371854
Short name T290
Test name
Test status
Simulation time 234575769148 ps
CPU time 131.2 seconds
Started Jul 01 04:37:23 PM PDT 24
Finished Jul 01 04:39:35 PM PDT 24
Peak memory 191292 kb
Host smart-76475702-ec5b-4fcd-b152-50e4bcc813c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107371854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3107371854
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1040492026
Short name T66
Test name
Test status
Simulation time 84674455740 ps
CPU time 84.05 seconds
Started Jul 01 04:37:31 PM PDT 24
Finished Jul 01 04:38:56 PM PDT 24
Peak memory 183088 kb
Host smart-e3f7e489-a3c3-4c0e-8e33-7f7383e696ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040492026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1040492026
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.672064587
Short name T333
Test name
Test status
Simulation time 131190430074 ps
CPU time 637.54 seconds
Started Jul 01 04:37:35 PM PDT 24
Finished Jul 01 04:48:13 PM PDT 24
Peak memory 191292 kb
Host smart-d3599711-d155-412c-8953-c412f8ce859b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672064587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.672064587
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3871559910
Short name T82
Test name
Test status
Simulation time 87496480397 ps
CPU time 973.8 seconds
Started Jul 01 04:37:38 PM PDT 24
Finished Jul 01 04:53:53 PM PDT 24
Peak memory 191188 kb
Host smart-23e6bfe7-d082-496a-806d-30ff4fae7586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871559910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3871559910
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.74238333
Short name T211
Test name
Test status
Simulation time 173314403049 ps
CPU time 1422.55 seconds
Started Jul 01 04:37:33 PM PDT 24
Finished Jul 01 05:01:17 PM PDT 24
Peak memory 191184 kb
Host smart-c359777e-41d0-4e35-a547-cab626165f91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74238333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.74238333
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2598194650
Short name T287
Test name
Test status
Simulation time 159777841112 ps
CPU time 125.13 seconds
Started Jul 01 04:37:45 PM PDT 24
Finished Jul 01 04:39:51 PM PDT 24
Peak memory 195108 kb
Host smart-7ca412e7-ba1f-4141-9365-b5798f3e4dd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598194650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2598194650
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3206976536
Short name T439
Test name
Test status
Simulation time 1619306797159 ps
CPU time 905.84 seconds
Started Jul 01 04:36:35 PM PDT 24
Finished Jul 01 04:51:46 PM PDT 24
Peak memory 183160 kb
Host smart-24b43c2c-dde8-46c9-a7f5-70a72a90c3e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206976536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3206976536
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.439418276
Short name T451
Test name
Test status
Simulation time 9000768434 ps
CPU time 13.82 seconds
Started Jul 01 04:36:34 PM PDT 24
Finished Jul 01 04:36:54 PM PDT 24
Peak memory 183320 kb
Host smart-342873cd-7df8-4eae-a3e3-3dab94015906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439418276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.439418276
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2507856263
Short name T305
Test name
Test status
Simulation time 85161252050 ps
CPU time 273.93 seconds
Started Jul 01 04:36:29 PM PDT 24
Finished Jul 01 04:41:11 PM PDT 24
Peak memory 191392 kb
Host smart-1f5ef93f-3b84-4eee-ac48-4f45cf7025f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507856263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2507856263
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.256996034
Short name T354
Test name
Test status
Simulation time 27310550 ps
CPU time 0.56 seconds
Started Jul 01 04:36:42 PM PDT 24
Finished Jul 01 04:36:46 PM PDT 24
Peak memory 183012 kb
Host smart-85d5b47e-6909-4c2b-a91e-08f8e2ada57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256996034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.256996034
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3249278417
Short name T182
Test name
Test status
Simulation time 213788614399 ps
CPU time 804.61 seconds
Started Jul 01 04:36:28 PM PDT 24
Finished Jul 01 04:50:01 PM PDT 24
Peak memory 194868 kb
Host smart-7e8d3049-5dfa-4b17-857f-ad4821be2d3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249278417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3249278417
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.2998032063
Short name T140
Test name
Test status
Simulation time 167813630635 ps
CPU time 241.84 seconds
Started Jul 01 04:37:39 PM PDT 24
Finished Jul 01 04:41:42 PM PDT 24
Peak memory 191256 kb
Host smart-a928b941-ed82-4c43-b30f-7ed2d5c1b17b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998032063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2998032063
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1968079944
Short name T436
Test name
Test status
Simulation time 42839181375 ps
CPU time 339.14 seconds
Started Jul 01 04:37:40 PM PDT 24
Finished Jul 01 04:43:20 PM PDT 24
Peak memory 183080 kb
Host smart-80989acf-3ae6-4f6c-8811-e48822240948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968079944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1968079944
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.859141833
Short name T310
Test name
Test status
Simulation time 184961981022 ps
CPU time 77.18 seconds
Started Jul 01 04:37:41 PM PDT 24
Finished Jul 01 04:38:59 PM PDT 24
Peak memory 183088 kb
Host smart-8951aa1b-2087-41fc-8502-20720e0c2d54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859141833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.859141833
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1062254439
Short name T423
Test name
Test status
Simulation time 83207264239 ps
CPU time 137.2 seconds
Started Jul 01 04:37:40 PM PDT 24
Finished Jul 01 04:39:58 PM PDT 24
Peak memory 191288 kb
Host smart-cbe39efc-1cda-4a0e-b987-76225c9355f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062254439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1062254439
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.322261790
Short name T69
Test name
Test status
Simulation time 385451177737 ps
CPU time 115.23 seconds
Started Jul 01 04:37:45 PM PDT 24
Finished Jul 01 04:39:41 PM PDT 24
Peak memory 191192 kb
Host smart-24f68413-8a82-4619-8e92-73897dd96d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322261790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.322261790
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.508971634
Short name T307
Test name
Test status
Simulation time 67921512644 ps
CPU time 76.41 seconds
Started Jul 01 04:37:40 PM PDT 24
Finished Jul 01 04:38:58 PM PDT 24
Peak memory 182976 kb
Host smart-6f6251f6-3970-4ab8-8261-8bc131ac7818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508971634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.508971634
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3826364254
Short name T405
Test name
Test status
Simulation time 316535899539 ps
CPU time 287.62 seconds
Started Jul 01 04:36:31 PM PDT 24
Finished Jul 01 04:41:26 PM PDT 24
Peak memory 183084 kb
Host smart-6e8a1014-405c-4e66-a329-720fac720518
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826364254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3826364254
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3688017497
Short name T429
Test name
Test status
Simulation time 32467007831 ps
CPU time 44.2 seconds
Started Jul 01 04:36:25 PM PDT 24
Finished Jul 01 04:37:19 PM PDT 24
Peak memory 183108 kb
Host smart-8db56150-f381-496b-83ad-0cc9061f7a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688017497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3688017497
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.181528219
Short name T272
Test name
Test status
Simulation time 219033465084 ps
CPU time 129.94 seconds
Started Jul 01 04:36:27 PM PDT 24
Finished Jul 01 04:38:46 PM PDT 24
Peak memory 183100 kb
Host smart-2dee37db-0b3c-4120-930c-40eedd63b055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181528219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.181528219
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.4057583597
Short name T410
Test name
Test status
Simulation time 12979913002 ps
CPU time 15.36 seconds
Started Jul 01 04:37:48 PM PDT 24
Finished Jul 01 04:38:05 PM PDT 24
Peak memory 183088 kb
Host smart-fe78cb7a-7fde-430f-a1ad-a764bd1f1d84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057583597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4057583597
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3005355048
Short name T58
Test name
Test status
Simulation time 260361778835 ps
CPU time 111.28 seconds
Started Jul 01 04:37:47 PM PDT 24
Finished Jul 01 04:39:39 PM PDT 24
Peak memory 191396 kb
Host smart-ee61e70c-6e50-4596-9f33-97e5c4540dc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005355048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3005355048
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3763186269
Short name T246
Test name
Test status
Simulation time 281887895017 ps
CPU time 941.9 seconds
Started Jul 01 04:37:48 PM PDT 24
Finished Jul 01 04:53:32 PM PDT 24
Peak memory 191212 kb
Host smart-04d95f6b-0493-4c12-91df-2f95cbf3cb10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763186269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3763186269
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3600832441
Short name T271
Test name
Test status
Simulation time 30152897904 ps
CPU time 47.16 seconds
Started Jul 01 04:37:49 PM PDT 24
Finished Jul 01 04:38:39 PM PDT 24
Peak memory 183088 kb
Host smart-f0f1dcb1-7d07-4608-ac93-995eb5ac7872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600832441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3600832441
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3896297771
Short name T226
Test name
Test status
Simulation time 59879289657 ps
CPU time 95.6 seconds
Started Jul 01 04:37:48 PM PDT 24
Finished Jul 01 04:39:25 PM PDT 24
Peak memory 191288 kb
Host smart-3bd42101-c922-4c09-b57c-de99adf15aa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896297771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3896297771
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1766054462
Short name T120
Test name
Test status
Simulation time 117296598395 ps
CPU time 547.17 seconds
Started Jul 01 04:37:47 PM PDT 24
Finished Jul 01 04:46:56 PM PDT 24
Peak memory 191288 kb
Host smart-4882635a-01a4-4936-a8bf-b94c9d5d218e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766054462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1766054462
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1966536561
Short name T105
Test name
Test status
Simulation time 151105432463 ps
CPU time 326.06 seconds
Started Jul 01 04:37:48 PM PDT 24
Finished Jul 01 04:43:16 PM PDT 24
Peak memory 191524 kb
Host smart-856be424-54ad-43ee-a11d-80432fc49b2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966536561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1966536561
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.318355347
Short name T199
Test name
Test status
Simulation time 156423874697 ps
CPU time 398.32 seconds
Started Jul 01 04:37:48 PM PDT 24
Finished Jul 01 04:44:29 PM PDT 24
Peak memory 191244 kb
Host smart-48f48634-0b82-4a30-879f-b64f5d2f09d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318355347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.318355347
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3489228863
Short name T234
Test name
Test status
Simulation time 340163006722 ps
CPU time 264.54 seconds
Started Jul 01 04:37:49 PM PDT 24
Finished Jul 01 04:42:15 PM PDT 24
Peak memory 191332 kb
Host smart-c9c6356b-ca3f-48f4-b61d-1cd042af987b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489228863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3489228863
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3570131810
Short name T261
Test name
Test status
Simulation time 385208413847 ps
CPU time 785.74 seconds
Started Jul 01 04:37:50 PM PDT 24
Finished Jul 01 04:50:59 PM PDT 24
Peak memory 191288 kb
Host smart-e0ba4974-3704-4a2e-abe7-67c5c5a2065a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570131810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3570131810
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2209403514
Short name T207
Test name
Test status
Simulation time 510477785992 ps
CPU time 421.93 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:43:30 PM PDT 24
Peak memory 183132 kb
Host smart-dabb952f-7cc0-4630-ac8a-8365987a5994
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209403514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2209403514
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2597946061
Short name T447
Test name
Test status
Simulation time 285717250080 ps
CPU time 216.65 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:40:18 PM PDT 24
Peak memory 183000 kb
Host smart-99d062c3-18c0-4f95-8400-3eac9661cd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597946061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2597946061
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1267548669
Short name T108
Test name
Test status
Simulation time 33672755808 ps
CPU time 47.49 seconds
Started Jul 01 04:36:12 PM PDT 24
Finished Jul 01 04:37:14 PM PDT 24
Peak memory 191320 kb
Host smart-faf77ae1-bcc9-4428-8c32-1c5df321b101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267548669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1267548669
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3405147600
Short name T359
Test name
Test status
Simulation time 497425091 ps
CPU time 0.84 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:36:43 PM PDT 24
Peak memory 191716 kb
Host smart-30300307-168e-4adb-8783-1ea7fbd20df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405147600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3405147600
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2380224441
Short name T18
Test name
Test status
Simulation time 1022571063 ps
CPU time 0.8 seconds
Started Jul 01 04:36:10 PM PDT 24
Finished Jul 01 04:36:25 PM PDT 24
Peak memory 214032 kb
Host smart-43cd8d0b-a7f3-48e0-a761-bfb1d0941789
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380224441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2380224441
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2785107377
Short name T413
Test name
Test status
Simulation time 903805726525 ps
CPU time 352.81 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 191288 kb
Host smart-61acf105-2a92-4f17-bc65-b0c4acb52446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785107377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2785107377
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1697572926
Short name T56
Test name
Test status
Simulation time 72288253113 ps
CPU time 116.15 seconds
Started Jul 01 04:36:21 PM PDT 24
Finished Jul 01 04:38:30 PM PDT 24
Peak memory 183228 kb
Host smart-c439b143-f916-4428-9ed9-04685c7c7fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697572926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1697572926
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4203360008
Short name T342
Test name
Test status
Simulation time 84509846878 ps
CPU time 32.46 seconds
Started Jul 01 04:36:30 PM PDT 24
Finished Jul 01 04:37:10 PM PDT 24
Peak memory 183024 kb
Host smart-489b1d19-3966-485f-9029-a603a15079e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203360008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4203360008
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2172623110
Short name T183
Test name
Test status
Simulation time 215953560738 ps
CPU time 112.36 seconds
Started Jul 01 04:36:32 PM PDT 24
Finished Jul 01 04:38:31 PM PDT 24
Peak memory 183080 kb
Host smart-2fae7a22-479b-46a6-b45c-9c845a14db8f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172623110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2172623110
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.352624304
Short name T365
Test name
Test status
Simulation time 510003572370 ps
CPU time 204.1 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:40:05 PM PDT 24
Peak memory 183228 kb
Host smart-06d4c67d-65f8-4951-8fab-d7f3def89411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352624304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.352624304
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3512767720
Short name T197
Test name
Test status
Simulation time 259661101207 ps
CPU time 198.62 seconds
Started Jul 01 04:36:42 PM PDT 24
Finished Jul 01 04:40:04 PM PDT 24
Peak memory 191364 kb
Host smart-4cdf6575-2237-4438-b5d6-61e8fd774b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512767720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3512767720
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.222709492
Short name T285
Test name
Test status
Simulation time 24794771451 ps
CPU time 43.76 seconds
Started Jul 01 04:36:33 PM PDT 24
Finished Jul 01 04:37:22 PM PDT 24
Peak memory 183100 kb
Host smart-ccbe9988-1ce7-4d09-810b-92106073f2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222709492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.222709492
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4130533214
Short name T180
Test name
Test status
Simulation time 414057935351 ps
CPU time 710.85 seconds
Started Jul 01 04:36:22 PM PDT 24
Finished Jul 01 04:48:25 PM PDT 24
Peak memory 183004 kb
Host smart-58c1dcc3-5038-4b30-8196-148291e66f52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130533214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4130533214
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.833260601
Short name T360
Test name
Test status
Simulation time 154671939285 ps
CPU time 119.29 seconds
Started Jul 01 04:36:22 PM PDT 24
Finished Jul 01 04:38:33 PM PDT 24
Peak memory 183104 kb
Host smart-74d9b468-99ce-4d8b-adcb-79892b642a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833260601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.833260601
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.4050573228
Short name T334
Test name
Test status
Simulation time 82407880512 ps
CPU time 54.61 seconds
Started Jul 01 04:36:23 PM PDT 24
Finished Jul 01 04:37:29 PM PDT 24
Peak memory 183176 kb
Host smart-7201e0ef-8ea8-4e1e-9e03-7d17c9504341
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050573228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.4050573228
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.4093097450
Short name T437
Test name
Test status
Simulation time 176831311585 ps
CPU time 1133.68 seconds
Started Jul 01 04:36:23 PM PDT 24
Finished Jul 01 04:55:28 PM PDT 24
Peak memory 183116 kb
Host smart-d85d479a-9138-48c7-b9af-9cd1fc14d5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093097450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.4093097450
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3060763809
Short name T266
Test name
Test status
Simulation time 533590089306 ps
CPU time 829.38 seconds
Started Jul 01 04:36:39 PM PDT 24
Finished Jul 01 04:50:33 PM PDT 24
Peak memory 191396 kb
Host smart-56a86aef-39fc-4419-8ba6-fe599a699660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060763809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3060763809
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3503014220
Short name T443
Test name
Test status
Simulation time 141121960440 ps
CPU time 349.53 seconds
Started Jul 01 04:36:23 PM PDT 24
Finished Jul 01 04:42:24 PM PDT 24
Peak memory 197780 kb
Host smart-567dc25c-c2c0-4aac-b218-9097735b2684
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503014220 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3503014220
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.4205563975
Short name T231
Test name
Test status
Simulation time 145371404257 ps
CPU time 121.82 seconds
Started Jul 01 04:36:44 PM PDT 24
Finished Jul 01 04:38:50 PM PDT 24
Peak memory 182952 kb
Host smart-b2058d40-47d4-4f9d-ace0-1ea4ec407f4c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205563975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.4205563975
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1896721057
Short name T363
Test name
Test status
Simulation time 69160971181 ps
CPU time 99.05 seconds
Started Jul 01 04:36:26 PM PDT 24
Finished Jul 01 04:38:15 PM PDT 24
Peak memory 183108 kb
Host smart-43be457e-e59a-4cc1-a8f3-f13abda64678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896721057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1896721057
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.357326026
Short name T343
Test name
Test status
Simulation time 442973623458 ps
CPU time 250.59 seconds
Started Jul 01 04:36:21 PM PDT 24
Finished Jul 01 04:40:45 PM PDT 24
Peak memory 191288 kb
Host smart-820e0d6e-73b5-4328-95b9-e00cc2d588c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357326026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.357326026
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.986715049
Short name T419
Test name
Test status
Simulation time 233572466 ps
CPU time 0.79 seconds
Started Jul 01 04:36:44 PM PDT 24
Finished Jul 01 04:36:49 PM PDT 24
Peak memory 182880 kb
Host smart-823de00a-a512-4c8a-a9f1-0557f3651f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986715049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.986715049
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3571510822
Short name T216
Test name
Test status
Simulation time 408085664025 ps
CPU time 663.88 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:47:46 PM PDT 24
Peak memory 191256 kb
Host smart-859f61cd-6458-48d2-8dfe-741602c920c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571510822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3571510822
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.920553510
Short name T377
Test name
Test status
Simulation time 215448605662 ps
CPU time 76.54 seconds
Started Jul 01 04:36:49 PM PDT 24
Finished Jul 01 04:38:11 PM PDT 24
Peak memory 183108 kb
Host smart-cde9c1fc-c07f-4984-98ee-5f6ed88065e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920553510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.920553510
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3847558331
Short name T167
Test name
Test status
Simulation time 58749852379 ps
CPU time 202.56 seconds
Started Jul 01 04:36:32 PM PDT 24
Finished Jul 01 04:40:01 PM PDT 24
Peak memory 191292 kb
Host smart-742087bc-0a66-40ce-b76f-4c45a9ed7e56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847558331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3847558331
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3359191740
Short name T53
Test name
Test status
Simulation time 45581369037 ps
CPU time 83.15 seconds
Started Jul 01 04:36:43 PM PDT 24
Finished Jul 01 04:38:10 PM PDT 24
Peak memory 191284 kb
Host smart-a214e096-cc5b-423b-b5c2-f76e99ce652b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359191740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3359191740
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.4005593926
Short name T23
Test name
Test status
Simulation time 527043981796 ps
CPU time 924.56 seconds
Started Jul 01 04:36:52 PM PDT 24
Finished Jul 01 04:52:21 PM PDT 24
Peak memory 183016 kb
Host smart-1d6548ef-6e92-45ea-bf87-a96e1b2b8597
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005593926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.4005593926
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.177580216
Short name T379
Test name
Test status
Simulation time 226438852875 ps
CPU time 178.92 seconds
Started Jul 01 04:36:42 PM PDT 24
Finished Jul 01 04:39:44 PM PDT 24
Peak memory 183028 kb
Host smart-d52db483-0f26-40e0-90dc-b17d83da7334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177580216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.177580216
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1996682768
Short name T151
Test name
Test status
Simulation time 49323901021 ps
CPU time 382.43 seconds
Started Jul 01 04:36:42 PM PDT 24
Finished Jul 01 04:43:08 PM PDT 24
Peak memory 193884 kb
Host smart-60cb93d8-6d23-40ad-be66-a0d5d72bf70e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996682768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1996682768
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3626495297
Short name T361
Test name
Test status
Simulation time 698751578 ps
CPU time 2.13 seconds
Started Jul 01 04:36:34 PM PDT 24
Finished Jul 01 04:36:42 PM PDT 24
Peak memory 183040 kb
Host smart-8a89286e-eb68-4422-973b-2170eb546ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626495297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3626495297
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2610208620
Short name T375
Test name
Test status
Simulation time 203367501306 ps
CPU time 284.16 seconds
Started Jul 01 04:36:30 PM PDT 24
Finished Jul 01 04:41:21 PM PDT 24
Peak memory 195672 kb
Host smart-f0bb79eb-834a-4126-a389-4916c02e7a1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610208620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2610208620
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1948943437
Short name T77
Test name
Test status
Simulation time 36852925661 ps
CPU time 45.84 seconds
Started Jul 01 04:36:39 PM PDT 24
Finished Jul 01 04:37:29 PM PDT 24
Peak memory 183036 kb
Host smart-e92a4cf8-4af2-4365-a334-d77370a57c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948943437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1948943437
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1383957752
Short name T116
Test name
Test status
Simulation time 442294089165 ps
CPU time 495.02 seconds
Started Jul 01 04:36:34 PM PDT 24
Finished Jul 01 04:44:55 PM PDT 24
Peak memory 190888 kb
Host smart-04a7b9b2-fa35-47a1-a095-33d608d81a41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383957752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1383957752
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3207490245
Short name T264
Test name
Test status
Simulation time 8116255045 ps
CPU time 4.99 seconds
Started Jul 01 04:36:35 PM PDT 24
Finished Jul 01 04:36:46 PM PDT 24
Peak memory 191376 kb
Host smart-78afacf7-9a62-4f55-84bc-6c5b35c6d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207490245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3207490245
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1676596969
Short name T20
Test name
Test status
Simulation time 124915299235 ps
CPU time 144.9 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:39:15 PM PDT 24
Peak memory 183104 kb
Host smart-532ac6ff-e253-4d56-b3f3-68ecc6c53d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676596969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1676596969
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2279680059
Short name T156
Test name
Test status
Simulation time 529090323475 ps
CPU time 511.69 seconds
Started Jul 01 04:36:27 PM PDT 24
Finished Jul 01 04:45:08 PM PDT 24
Peak memory 191464 kb
Host smart-2964246e-0804-4638-87f3-0c6262251e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279680059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2279680059
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1470345342
Short name T247
Test name
Test status
Simulation time 53388483161 ps
CPU time 45.82 seconds
Started Jul 01 04:36:34 PM PDT 24
Finished Jul 01 04:37:25 PM PDT 24
Peak memory 190892 kb
Host smart-1dfcc8c6-cb4e-4484-bf35-2996b2f991ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470345342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1470345342
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2514866861
Short name T230
Test name
Test status
Simulation time 316697967556 ps
CPU time 415.01 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:43:45 PM PDT 24
Peak memory 183084 kb
Host smart-b459599c-092d-4ba3-b588-70bf4ebce237
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514866861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2514866861
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1834816065
Short name T382
Test name
Test status
Simulation time 314234840565 ps
CPU time 122.07 seconds
Started Jul 01 04:36:41 PM PDT 24
Finished Jul 01 04:38:47 PM PDT 24
Peak memory 183096 kb
Host smart-fb6f874d-f99e-488a-8c36-544f22d318b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834816065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1834816065
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.4013335987
Short name T278
Test name
Test status
Simulation time 614998733432 ps
CPU time 648.81 seconds
Started Jul 01 04:36:32 PM PDT 24
Finished Jul 01 04:47:27 PM PDT 24
Peak memory 191296 kb
Host smart-2bd86d9c-3aca-4cb0-b63d-47f163eec5c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013335987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4013335987
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.1840775628
Short name T428
Test name
Test status
Simulation time 19083005129 ps
CPU time 198.37 seconds
Started Jul 01 04:36:47 PM PDT 24
Finished Jul 01 04:40:10 PM PDT 24
Peak memory 197632 kb
Host smart-34eb0777-e698-4079-b3d4-92c42b86ed87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840775628 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.1840775628
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2989231958
Short name T420
Test name
Test status
Simulation time 615829018079 ps
CPU time 173.47 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:39:34 PM PDT 24
Peak memory 183048 kb
Host smart-aa19b60e-0b76-4a74-97a1-9c0477b4f00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989231958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2989231958
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2169139641
Short name T358
Test name
Test status
Simulation time 103437910 ps
CPU time 0.63 seconds
Started Jul 01 04:36:36 PM PDT 24
Finished Jul 01 04:36:42 PM PDT 24
Peak memory 182948 kb
Host smart-33c52ce0-c5c0-4c5a-8ea5-c4247717139c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169139641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2169139641
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1216452339
Short name T383
Test name
Test status
Simulation time 1011236555943 ps
CPU time 413.2 seconds
Started Jul 01 04:36:48 PM PDT 24
Finished Jul 01 04:43:46 PM PDT 24
Peak memory 194616 kb
Host smart-fb3c7736-e638-4d10-80b5-2e75c0ea000b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216452339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1216452339
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2785406344
Short name T37
Test name
Test status
Simulation time 205166715813 ps
CPU time 403.99 seconds
Started Jul 01 04:36:42 PM PDT 24
Finished Jul 01 04:43:30 PM PDT 24
Peak memory 206000 kb
Host smart-56f33be8-6bad-4f9c-80fb-6887ae8db0b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785406344 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2785406344
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.831021441
Short name T279
Test name
Test status
Simulation time 15895812585 ps
CPU time 28.32 seconds
Started Jul 01 04:36:14 PM PDT 24
Finished Jul 01 04:36:57 PM PDT 24
Peak memory 183080 kb
Host smart-b21d1d5d-f5e1-4444-8b94-3e0896529592
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831021441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.831021441
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1433892051
Short name T424
Test name
Test status
Simulation time 267888539347 ps
CPU time 174.27 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 04:39:26 PM PDT 24
Peak memory 182736 kb
Host smart-44c7b680-1be5-4365-bf65-b690c339d7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433892051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1433892051
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3589707396
Short name T80
Test name
Test status
Simulation time 120895882107 ps
CPU time 72.45 seconds
Started Jul 01 04:36:10 PM PDT 24
Finished Jul 01 04:37:36 PM PDT 24
Peak memory 182980 kb
Host smart-b5b02f57-429f-466d-b63e-65279a0e260b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589707396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3589707396
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2994681857
Short name T347
Test name
Test status
Simulation time 45195185123 ps
CPU time 73.26 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:37:41 PM PDT 24
Peak memory 183104 kb
Host smart-529a5dee-80bf-47eb-b1b5-c6cb95d2c159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994681857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2994681857
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1436659402
Short name T15
Test name
Test status
Simulation time 308469618 ps
CPU time 0.91 seconds
Started Jul 01 04:36:09 PM PDT 24
Finished Jul 01 04:36:24 PM PDT 24
Peak memory 214528 kb
Host smart-085bbe44-3fbe-4507-8d9f-f12a69e56d78
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436659402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1436659402
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2028159817
Short name T434
Test name
Test status
Simulation time 746106676003 ps
CPU time 232.6 seconds
Started Jul 01 04:36:07 PM PDT 24
Finished Jul 01 04:40:14 PM PDT 24
Peak memory 183060 kb
Host smart-d25b2b69-d6ab-47dc-814a-632525df861b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028159817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2028159817
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.1836375487
Short name T345
Test name
Test status
Simulation time 87066041613 ps
CPU time 42.07 seconds
Started Jul 01 04:36:50 PM PDT 24
Finished Jul 01 04:37:37 PM PDT 24
Peak memory 183080 kb
Host smart-4a759398-28a1-43c2-be89-3db47f7b4647
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836375487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.1836375487
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2898329137
Short name T357
Test name
Test status
Simulation time 347229882903 ps
CPU time 132.57 seconds
Started Jul 01 04:36:52 PM PDT 24
Finished Jul 01 04:39:09 PM PDT 24
Peak memory 183196 kb
Host smart-b1719334-a064-4483-b2f0-b0244b475f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898329137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2898329137
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.890040124
Short name T280
Test name
Test status
Simulation time 351162403842 ps
CPU time 370.99 seconds
Started Jul 01 04:36:43 PM PDT 24
Finished Jul 01 04:42:58 PM PDT 24
Peak memory 191256 kb
Host smart-bac7c95c-b133-4463-a9d5-5a64caad4b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890040124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.890040124
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1706502272
Short name T389
Test name
Test status
Simulation time 556573979 ps
CPU time 1.07 seconds
Started Jul 01 04:36:35 PM PDT 24
Finished Jul 01 04:36:41 PM PDT 24
Peak memory 182956 kb
Host smart-e317895e-a673-4561-a6e5-5f6a57698150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706502272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1706502272
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1756673952
Short name T445
Test name
Test status
Simulation time 1521974580124 ps
CPU time 500.43 seconds
Started Jul 01 04:36:44 PM PDT 24
Finished Jul 01 04:45:08 PM PDT 24
Peak memory 194552 kb
Host smart-a180c6d8-a483-4307-8668-b15360866c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756673952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1756673952
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2194612376
Short name T75
Test name
Test status
Simulation time 76973082842 ps
CPU time 540.23 seconds
Started Jul 01 04:36:47 PM PDT 24
Finished Jul 01 04:45:52 PM PDT 24
Peak memory 205996 kb
Host smart-0c9d89f0-c8e9-412d-8e0f-91836998b3a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194612376 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2194612376
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3885954633
Short name T398
Test name
Test status
Simulation time 259073787246 ps
CPU time 86.5 seconds
Started Jul 01 04:36:38 PM PDT 24
Finished Jul 01 04:38:09 PM PDT 24
Peak memory 183008 kb
Host smart-cc2f7cc7-fadc-481a-9d2d-f90e8adc7b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885954633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3885954633
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2017808064
Short name T311
Test name
Test status
Simulation time 115695638678 ps
CPU time 57.7 seconds
Started Jul 01 04:36:47 PM PDT 24
Finished Jul 01 04:37:49 PM PDT 24
Peak memory 183156 kb
Host smart-b95e1d2d-b93d-4055-a7fc-7779d6640b69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017808064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2017808064
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2317856528
Short name T126
Test name
Test status
Simulation time 43982794756 ps
CPU time 72.53 seconds
Started Jul 01 04:36:34 PM PDT 24
Finished Jul 01 04:37:52 PM PDT 24
Peak memory 183112 kb
Host smart-fa4e57ba-5cf2-46d5-a13b-d4e7b2fd33b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317856528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2317856528
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.144843470
Short name T218
Test name
Test status
Simulation time 595882032666 ps
CPU time 858.29 seconds
Started Jul 01 04:36:47 PM PDT 24
Finished Jul 01 04:51:09 PM PDT 24
Peak memory 194828 kb
Host smart-2d2012fb-44a6-4c78-8338-64ccc0157666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144843470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
144843470
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.593116800
Short name T39
Test name
Test status
Simulation time 31237221359 ps
CPU time 339.33 seconds
Started Jul 01 04:36:37 PM PDT 24
Finished Jul 01 04:42:21 PM PDT 24
Peak memory 205940 kb
Host smart-4efb96d3-9b70-49c4-b11a-90031f5f360b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593116800 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.593116800
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.918799537
Short name T238
Test name
Test status
Simulation time 116694856882 ps
CPU time 179.88 seconds
Started Jul 01 04:36:47 PM PDT 24
Finished Jul 01 04:39:52 PM PDT 24
Peak memory 183140 kb
Host smart-f30bd8fe-4567-4d7f-8a8a-d3b35e981106
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918799537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.918799537
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3006648650
Short name T438
Test name
Test status
Simulation time 347501913045 ps
CPU time 145.21 seconds
Started Jul 01 04:36:38 PM PDT 24
Finished Jul 01 04:39:08 PM PDT 24
Peak memory 183192 kb
Host smart-06b84971-81dd-4dfe-97ff-036fd13a1992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006648650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3006648650
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3480332174
Short name T221
Test name
Test status
Simulation time 193300745562 ps
CPU time 103.93 seconds
Started Jul 01 04:36:40 PM PDT 24
Finished Jul 01 04:38:28 PM PDT 24
Peak memory 191284 kb
Host smart-ea2f305d-d2d4-480e-aaa9-13a30a702420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480332174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3480332174
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2554929119
Short name T442
Test name
Test status
Simulation time 67473995 ps
CPU time 0.69 seconds
Started Jul 01 04:36:51 PM PDT 24
Finished Jul 01 04:36:57 PM PDT 24
Peak memory 191632 kb
Host smart-4b688d15-77ab-4e81-8fe0-8807e561923e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554929119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2554929119
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2543446246
Short name T217
Test name
Test status
Simulation time 747171965326 ps
CPU time 486.43 seconds
Started Jul 01 04:36:43 PM PDT 24
Finished Jul 01 04:44:53 PM PDT 24
Peak memory 191264 kb
Host smart-11b3417e-f9d1-4517-b5b3-42223a30f23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543446246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2543446246
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.43170305
Short name T406
Test name
Test status
Simulation time 93176104230 ps
CPU time 484.64 seconds
Started Jul 01 04:36:44 PM PDT 24
Finished Jul 01 04:44:52 PM PDT 24
Peak memory 197700 kb
Host smart-231ddcfc-f4e1-4fe1-9d9f-9a93028d31b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43170305 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.43170305
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3478791564
Short name T338
Test name
Test status
Simulation time 226748336503 ps
CPU time 110.79 seconds
Started Jul 01 04:36:35 PM PDT 24
Finished Jul 01 04:38:31 PM PDT 24
Peak memory 183036 kb
Host smart-df0ce10d-25dd-4d41-ad2d-6a772c687bbc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478791564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3478791564
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1870017357
Short name T364
Test name
Test status
Simulation time 331363935704 ps
CPU time 221.65 seconds
Started Jul 01 04:36:39 PM PDT 24
Finished Jul 01 04:40:25 PM PDT 24
Peak memory 183184 kb
Host smart-f64c349c-535b-4547-9048-4d769fea4065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870017357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1870017357
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1571480870
Short name T407
Test name
Test status
Simulation time 89977742900 ps
CPU time 63.68 seconds
Started Jul 01 04:36:43 PM PDT 24
Finished Jul 01 04:37:50 PM PDT 24
Peak memory 183148 kb
Host smart-2bb0be9d-7bee-427a-805e-2cf8f3f25fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571480870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1571480870
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3392402399
Short name T353
Test name
Test status
Simulation time 366288653 ps
CPU time 1.26 seconds
Started Jul 01 04:36:33 PM PDT 24
Finished Jul 01 04:36:40 PM PDT 24
Peak memory 183040 kb
Host smart-b3556318-8079-40b9-a23c-0b4ae30e310b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392402399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3392402399
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3077571902
Short name T61
Test name
Test status
Simulation time 344877239321 ps
CPU time 519.96 seconds
Started Jul 01 04:36:35 PM PDT 24
Finished Jul 01 04:45:20 PM PDT 24
Peak memory 195972 kb
Host smart-aeaf5559-8c6d-4f98-bb43-10e9a98790be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077571902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3077571902
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1591694571
Short name T38
Test name
Test status
Simulation time 41687743390 ps
CPU time 332.75 seconds
Started Jul 01 04:36:52 PM PDT 24
Finished Jul 01 04:42:30 PM PDT 24
Peak memory 206060 kb
Host smart-d52d2aa4-905e-4869-85ec-cba24adf380d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591694571 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1591694571
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2514504283
Short name T308
Test name
Test status
Simulation time 2709213269997 ps
CPU time 694.35 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:48:24 PM PDT 24
Peak memory 182984 kb
Host smart-12cf1342-688c-4b90-931c-8d75234e60d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514504283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2514504283
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1621913237
Short name T374
Test name
Test status
Simulation time 148443657324 ps
CPU time 192.73 seconds
Started Jul 01 04:36:44 PM PDT 24
Finished Jul 01 04:40:01 PM PDT 24
Peak memory 183076 kb
Host smart-ebd39227-b105-44ea-bee1-3e2bf2a33c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621913237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1621913237
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.1066528106
Short name T70
Test name
Test status
Simulation time 25856373598 ps
CPU time 17.79 seconds
Started Jul 01 04:36:49 PM PDT 24
Finished Jul 01 04:37:12 PM PDT 24
Peak memory 183048 kb
Host smart-3b93b624-f0c5-4c1b-a503-1796209afcdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066528106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1066528106
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3087605524
Short name T433
Test name
Test status
Simulation time 13719293633 ps
CPU time 73.77 seconds
Started Jul 01 04:36:45 PM PDT 24
Finished Jul 01 04:38:03 PM PDT 24
Peak memory 182976 kb
Host smart-c92db088-1496-4195-9ab3-d1734aa2db3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087605524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3087605524
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3762904577
Short name T189
Test name
Test status
Simulation time 119991998253 ps
CPU time 25.77 seconds
Started Jul 01 04:36:38 PM PDT 24
Finished Jul 01 04:37:08 PM PDT 24
Peak memory 183036 kb
Host smart-f6b65a5a-e2f6-4104-abe0-b19afc0a0646
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762904577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3762904577
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1491443018
Short name T421
Test name
Test status
Simulation time 236433913828 ps
CPU time 212.83 seconds
Started Jul 01 04:36:44 PM PDT 24
Finished Jul 01 04:40:21 PM PDT 24
Peak memory 183060 kb
Host smart-1e5d18db-f239-457a-be64-870f384b898e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491443018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1491443018
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3154623651
Short name T159
Test name
Test status
Simulation time 478470342835 ps
CPU time 1046.47 seconds
Started Jul 01 04:36:48 PM PDT 24
Finished Jul 01 04:54:20 PM PDT 24
Peak memory 191184 kb
Host smart-9a600b65-8e54-4870-bba9-a5e953801a33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154623651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3154623651
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3941540887
Short name T236
Test name
Test status
Simulation time 427772530310 ps
CPU time 682.83 seconds
Started Jul 01 04:36:37 PM PDT 24
Finished Jul 01 04:48:05 PM PDT 24
Peak memory 182984 kb
Host smart-94f39377-94f4-4e4f-948b-12a15b05395f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941540887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3941540887
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3508352145
Short name T368
Test name
Test status
Simulation time 27624634619 ps
CPU time 18.56 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:37:08 PM PDT 24
Peak memory 183104 kb
Host smart-d0c42eee-798a-44fd-be4c-a350f447e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508352145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3508352145
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3700674186
Short name T188
Test name
Test status
Simulation time 456536559487 ps
CPU time 464.51 seconds
Started Jul 01 04:36:54 PM PDT 24
Finished Jul 01 04:44:43 PM PDT 24
Peak memory 193608 kb
Host smart-f4468cd9-e223-44dd-985e-30bdfb4d469b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700674186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3700674186
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3958299879
Short name T376
Test name
Test status
Simulation time 205276179087 ps
CPU time 92.14 seconds
Started Jul 01 04:36:38 PM PDT 24
Finished Jul 01 04:38:14 PM PDT 24
Peak memory 191284 kb
Host smart-5126d1f5-5493-4a34-9e57-2ad84c2c9907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958299879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3958299879
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3052208885
Short name T76
Test name
Test status
Simulation time 30581419 ps
CPU time 0.58 seconds
Started Jul 01 04:36:43 PM PDT 24
Finished Jul 01 04:36:47 PM PDT 24
Peak memory 182936 kb
Host smart-e79772d3-d683-47cd-a5a5-2d7e11e24c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052208885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3052208885
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3830931294
Short name T117
Test name
Test status
Simulation time 163241328026 ps
CPU time 292.83 seconds
Started Jul 01 04:36:49 PM PDT 24
Finished Jul 01 04:41:47 PM PDT 24
Peak memory 183028 kb
Host smart-6eefba3e-b8e8-4447-b755-1b531aedf734
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830931294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3830931294
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.516583510
Short name T372
Test name
Test status
Simulation time 34825063036 ps
CPU time 27.15 seconds
Started Jul 01 04:36:43 PM PDT 24
Finished Jul 01 04:37:14 PM PDT 24
Peak memory 183104 kb
Host smart-06b66405-3c0a-4265-9965-e63f99a019c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516583510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.516583510
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3051144519
Short name T132
Test name
Test status
Simulation time 233406198194 ps
CPU time 309.56 seconds
Started Jul 01 04:36:43 PM PDT 24
Finished Jul 01 04:41:56 PM PDT 24
Peak memory 193452 kb
Host smart-a0907569-21ad-4772-95ff-22d3ab1c5240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051144519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3051144519
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1651913352
Short name T168
Test name
Test status
Simulation time 10376680648 ps
CPU time 9.03 seconds
Started Jul 01 04:36:54 PM PDT 24
Finished Jul 01 04:37:07 PM PDT 24
Peak memory 191192 kb
Host smart-13d2f3d6-00ae-413f-a100-cada24ca5fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651913352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1651913352
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.2142666557
Short name T12
Test name
Test status
Simulation time 36787826375 ps
CPU time 432.04 seconds
Started Jul 01 04:36:50 PM PDT 24
Finished Jul 01 04:44:07 PM PDT 24
Peak memory 206060 kb
Host smart-7704a0f0-d068-466f-8ff8-79ef34061ad5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142666557 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.2142666557
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3744417300
Short name T84
Test name
Test status
Simulation time 169688269587 ps
CPU time 229.34 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:40:39 PM PDT 24
Peak memory 183004 kb
Host smart-aa9a0bab-7ccd-4f1e-84d8-9c3fde761cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744417300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3744417300
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.411379027
Short name T25
Test name
Test status
Simulation time 73546772176 ps
CPU time 74.87 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:38:05 PM PDT 24
Peak memory 182864 kb
Host smart-eeabe039-b010-4146-a653-76ccaacd1920
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411379027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.411379027
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1466706641
Short name T323
Test name
Test status
Simulation time 38468843484 ps
CPU time 126.85 seconds
Started Jul 01 04:36:47 PM PDT 24
Finished Jul 01 04:38:58 PM PDT 24
Peak memory 193060 kb
Host smart-c1dde0bc-3273-4a7f-acbb-9c045769aef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466706641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1466706641
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4233585675
Short name T394
Test name
Test status
Simulation time 453879096528 ps
CPU time 619.3 seconds
Started Jul 01 04:36:45 PM PDT 24
Finished Jul 01 04:47:08 PM PDT 24
Peak memory 195352 kb
Host smart-4288cf01-5d6d-4629-8bdf-2c25569ee15e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233585675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4233585675
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1077972842
Short name T194
Test name
Test status
Simulation time 392913705670 ps
CPU time 615.29 seconds
Started Jul 01 04:36:48 PM PDT 24
Finished Jul 01 04:47:08 PM PDT 24
Peak memory 183060 kb
Host smart-4cb0924e-c34e-4458-b6c8-c225b52b66e1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077972842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1077972842
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.4020771472
Short name T366
Test name
Test status
Simulation time 981923093806 ps
CPU time 337.39 seconds
Started Jul 01 04:36:39 PM PDT 24
Finished Jul 01 04:42:21 PM PDT 24
Peak memory 183192 kb
Host smart-f6f38003-732e-49ab-bed5-7f1c3647ffc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020771472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.4020771472
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3935690872
Short name T204
Test name
Test status
Simulation time 73115771440 ps
CPU time 97.26 seconds
Started Jul 01 04:36:48 PM PDT 24
Finished Jul 01 04:38:30 PM PDT 24
Peak memory 194792 kb
Host smart-6dc6481e-cebb-44f6-8faf-8e7fe8ba147c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935690872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3935690872
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.327398613
Short name T292
Test name
Test status
Simulation time 49298190160 ps
CPU time 57.24 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:37:48 PM PDT 24
Peak memory 191284 kb
Host smart-c431acd2-8b42-41f8-9c6e-675383d0692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327398613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.327398613
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3114091624
Short name T213
Test name
Test status
Simulation time 6010157012 ps
CPU time 10.32 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 04:36:42 PM PDT 24
Peak memory 182992 kb
Host smart-be9fcc43-0edb-4789-a048-c9f43ffc810f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114091624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3114091624
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1598915766
Short name T6
Test name
Test status
Simulation time 339638871631 ps
CPU time 275.45 seconds
Started Jul 01 04:36:08 PM PDT 24
Finished Jul 01 04:40:58 PM PDT 24
Peak memory 183008 kb
Host smart-5a3e52b4-c3d1-4b93-8cd3-a97fc614d86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598915766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1598915766
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3177531666
Short name T392
Test name
Test status
Simulation time 59451637110 ps
CPU time 85.25 seconds
Started Jul 01 04:36:09 PM PDT 24
Finished Jul 01 04:37:49 PM PDT 24
Peak memory 194864 kb
Host smart-532a24eb-018c-4554-be5a-03c4f7a8357d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177531666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3177531666
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3093097034
Short name T371
Test name
Test status
Simulation time 62850283 ps
CPU time 0.59 seconds
Started Jul 01 04:36:12 PM PDT 24
Finished Jul 01 04:36:28 PM PDT 24
Peak memory 182920 kb
Host smart-8dc4d416-a46b-4a76-ae15-d804d160292d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093097034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3093097034
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3811012167
Short name T17
Test name
Test status
Simulation time 1097733449 ps
CPU time 0.83 seconds
Started Jul 01 04:36:18 PM PDT 24
Finished Jul 01 04:36:32 PM PDT 24
Peak memory 214088 kb
Host smart-6fc5d133-38f3-4642-849c-fe36d8d3ee3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811012167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3811012167
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.353628515
Short name T60
Test name
Test status
Simulation time 322359276590 ps
CPU time 305.74 seconds
Started Jul 01 04:36:12 PM PDT 24
Finished Jul 01 04:41:33 PM PDT 24
Peak memory 194052 kb
Host smart-55d96e37-6af9-41d4-80c9-82ffacc8aa13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353628515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.353628515
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.133140138
Short name T380
Test name
Test status
Simulation time 118235628974 ps
CPU time 184.46 seconds
Started Jul 01 04:36:55 PM PDT 24
Finished Jul 01 04:40:04 PM PDT 24
Peak memory 183104 kb
Host smart-ffc6104a-fa72-416f-8bc5-aaf103fb3275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133140138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.133140138
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1046819350
Short name T315
Test name
Test status
Simulation time 289686550894 ps
CPU time 234.45 seconds
Started Jul 01 04:36:48 PM PDT 24
Finished Jul 01 04:40:47 PM PDT 24
Peak memory 191524 kb
Host smart-123d3754-d45c-4155-a907-d93ed8504269
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046819350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1046819350
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.3933204070
Short name T340
Test name
Test status
Simulation time 24137475878 ps
CPU time 173.12 seconds
Started Jul 01 04:36:45 PM PDT 24
Finished Jul 01 04:39:42 PM PDT 24
Peak memory 197792 kb
Host smart-b7837abb-7e0f-4767-8609-16b02c1ded01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933204070 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.3933204070
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2178353925
Short name T455
Test name
Test status
Simulation time 890011312822 ps
CPU time 431.17 seconds
Started Jul 01 04:36:45 PM PDT 24
Finished Jul 01 04:44:01 PM PDT 24
Peak memory 183208 kb
Host smart-0d4b6477-397e-4f57-ae3c-1280c02f2c27
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178353925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2178353925
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.730036830
Short name T412
Test name
Test status
Simulation time 139562012473 ps
CPU time 108.96 seconds
Started Jul 01 04:36:56 PM PDT 24
Finished Jul 01 04:38:49 PM PDT 24
Peak memory 183148 kb
Host smart-cbc743f9-18f8-468d-8201-6806ab0c6842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730036830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.730036830
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1862726947
Short name T55
Test name
Test status
Simulation time 833060238545 ps
CPU time 1234.35 seconds
Started Jul 01 04:36:50 PM PDT 24
Finished Jul 01 04:57:29 PM PDT 24
Peak memory 191292 kb
Host smart-c1f1b6e1-6d47-4795-bc0c-4f9c8d89486d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862726947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1862726947
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.644950395
Short name T352
Test name
Test status
Simulation time 2085647901 ps
CPU time 6.03 seconds
Started Jul 01 04:36:55 PM PDT 24
Finished Jul 01 04:37:05 PM PDT 24
Peak memory 191148 kb
Host smart-451f9310-ae05-4471-be67-4e1ce774e004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644950395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.644950395
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2075908523
Short name T186
Test name
Test status
Simulation time 492609724186 ps
CPU time 444.89 seconds
Started Jul 01 04:36:51 PM PDT 24
Finished Jul 01 04:44:20 PM PDT 24
Peak memory 183220 kb
Host smart-ba2df179-4fee-4d1a-be51-a9e06b4cddfe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075908523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2075908523
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1503714316
Short name T418
Test name
Test status
Simulation time 432347508640 ps
CPU time 177.84 seconds
Started Jul 01 04:36:55 PM PDT 24
Finished Jul 01 04:39:57 PM PDT 24
Peak memory 182976 kb
Host smart-d0f807c8-c1b2-4e31-996a-e8d24912c95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503714316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1503714316
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.4093702784
Short name T214
Test name
Test status
Simulation time 12134122405 ps
CPU time 16.87 seconds
Started Jul 01 04:36:54 PM PDT 24
Finished Jul 01 04:37:15 PM PDT 24
Peak memory 182996 kb
Host smart-97fad035-98c0-4486-a40e-6fdcbb19ad2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093702784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4093702784
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.764978868
Short name T11
Test name
Test status
Simulation time 485784687877 ps
CPU time 768.33 seconds
Started Jul 01 04:36:49 PM PDT 24
Finished Jul 01 04:49:42 PM PDT 24
Peak memory 191188 kb
Host smart-3784c3d1-988e-40c1-bf37-9adde3b381eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764978868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
764978868
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3747795397
Short name T314
Test name
Test status
Simulation time 855695277465 ps
CPU time 696.79 seconds
Started Jul 01 04:36:47 PM PDT 24
Finished Jul 01 04:48:29 PM PDT 24
Peak memory 183080 kb
Host smart-9e693f11-d157-4d7a-927c-15fc426a9079
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747795397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3747795397
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2703810581
Short name T384
Test name
Test status
Simulation time 236891542180 ps
CPU time 295.07 seconds
Started Jul 01 04:36:47 PM PDT 24
Finished Jul 01 04:41:46 PM PDT 24
Peak memory 183108 kb
Host smart-a4d7bc31-231c-4105-942d-57e12ec6103a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703810581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2703810581
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2111579865
Short name T294
Test name
Test status
Simulation time 90903449987 ps
CPU time 324.52 seconds
Started Jul 01 04:36:50 PM PDT 24
Finished Jul 01 04:42:20 PM PDT 24
Peak memory 191284 kb
Host smart-d26edb70-0976-49bb-b95f-2f609aa54cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111579865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2111579865
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.4074691908
Short name T452
Test name
Test status
Simulation time 8875111496 ps
CPU time 5.28 seconds
Started Jul 01 04:36:55 PM PDT 24
Finished Jul 01 04:37:05 PM PDT 24
Peak memory 191288 kb
Host smart-65518352-2a45-49f4-aea1-d0bd96f69165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074691908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4074691908
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.611542159
Short name T35
Test name
Test status
Simulation time 67118469863 ps
CPU time 518.37 seconds
Started Jul 01 04:36:54 PM PDT 24
Finished Jul 01 04:45:37 PM PDT 24
Peak memory 205900 kb
Host smart-01d39514-3a00-49e7-a509-e1501ec33555
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611542159 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.611542159
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3251610208
Short name T293
Test name
Test status
Simulation time 212820780983 ps
CPU time 115.04 seconds
Started Jul 01 04:36:51 PM PDT 24
Finished Jul 01 04:38:51 PM PDT 24
Peak memory 183124 kb
Host smart-e245a01e-d275-4295-b1c7-b93bdb24e251
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251610208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3251610208
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.4203877445
Short name T448
Test name
Test status
Simulation time 121709115228 ps
CPU time 166.05 seconds
Started Jul 01 04:36:50 PM PDT 24
Finished Jul 01 04:39:41 PM PDT 24
Peak memory 183008 kb
Host smart-2c177b07-ee15-4b68-aeba-73c784e9234c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203877445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4203877445
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3125231731
Short name T336
Test name
Test status
Simulation time 156358950589 ps
CPU time 1656.99 seconds
Started Jul 01 04:36:44 PM PDT 24
Finished Jul 01 05:04:25 PM PDT 24
Peak memory 183088 kb
Host smart-90d834f0-d1b3-43f6-b7ce-675773405a55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125231731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3125231731
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.504333115
Short name T454
Test name
Test status
Simulation time 99353203319 ps
CPU time 215.25 seconds
Started Jul 01 04:36:49 PM PDT 24
Finished Jul 01 04:40:30 PM PDT 24
Peak memory 191160 kb
Host smart-319c1011-bcf0-4800-9d99-99e19fa48f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504333115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.504333115
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3986205335
Short name T387
Test name
Test status
Simulation time 86616586 ps
CPU time 0.66 seconds
Started Jul 01 04:36:46 PM PDT 24
Finished Jul 01 04:36:51 PM PDT 24
Peak memory 182832 kb
Host smart-77bf8caf-fba2-45ff-b766-f71b48321a10
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986205335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3986205335
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2632233335
Short name T386
Test name
Test status
Simulation time 512250388914 ps
CPU time 185.17 seconds
Started Jul 01 04:36:48 PM PDT 24
Finished Jul 01 04:39:58 PM PDT 24
Peak memory 183100 kb
Host smart-bd2faa1b-44f9-4163-86cf-4cdef72cf769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632233335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2632233335
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.4145590318
Short name T122
Test name
Test status
Simulation time 96833993834 ps
CPU time 715.64 seconds
Started Jul 01 04:36:49 PM PDT 24
Finished Jul 01 04:48:50 PM PDT 24
Peak memory 191236 kb
Host smart-43ef9b60-2b55-4444-95f9-41e0f0e3380d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145590318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.4145590318
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1372590882
Short name T362
Test name
Test status
Simulation time 20032937 ps
CPU time 0.54 seconds
Started Jul 01 04:36:54 PM PDT 24
Finished Jul 01 04:36:59 PM PDT 24
Peak memory 182932 kb
Host smart-0cb12ba9-a6da-448b-b2d6-c8341c83e531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372590882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1372590882
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.765197407
Short name T399
Test name
Test status
Simulation time 142251899075 ps
CPU time 230.72 seconds
Started Jul 01 04:36:50 PM PDT 24
Finished Jul 01 04:40:46 PM PDT 24
Peak memory 183104 kb
Host smart-0344876b-55b6-4a94-abfa-dcecd3caf5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765197407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.765197407
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.1342136175
Short name T422
Test name
Test status
Simulation time 293510453241 ps
CPU time 528.82 seconds
Started Jul 01 04:36:51 PM PDT 24
Finished Jul 01 04:45:45 PM PDT 24
Peak memory 206132 kb
Host smart-53fc5137-dc68-4bbc-8185-fa334680599e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342136175 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.1342136175
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2363631482
Short name T456
Test name
Test status
Simulation time 18814636961 ps
CPU time 31.08 seconds
Started Jul 01 04:36:50 PM PDT 24
Finished Jul 01 04:37:26 PM PDT 24
Peak memory 183076 kb
Host smart-83bdee01-cf01-40e7-9d15-1e4168b0ab18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363631482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2363631482
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.4005195518
Short name T369
Test name
Test status
Simulation time 338170237417 ps
CPU time 125.05 seconds
Started Jul 01 04:36:55 PM PDT 24
Finished Jul 01 04:39:04 PM PDT 24
Peak memory 183104 kb
Host smart-cf2d6993-ff64-4207-a517-33a897c76506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005195518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.4005195518
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.262307371
Short name T7
Test name
Test status
Simulation time 511625085193 ps
CPU time 249.49 seconds
Started Jul 01 04:36:57 PM PDT 24
Finished Jul 01 04:41:11 PM PDT 24
Peak memory 191264 kb
Host smart-89b2178a-e3bd-43a6-8ae5-71bd274e2bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262307371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.262307371
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.902330492
Short name T351
Test name
Test status
Simulation time 90042017348 ps
CPU time 340.97 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 04:42:45 PM PDT 24
Peak memory 183108 kb
Host smart-0dd1020e-9e8a-42b7-991b-f762c84ec6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902330492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.902330492
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.900655318
Short name T104
Test name
Test status
Simulation time 351619030309 ps
CPU time 299.56 seconds
Started Jul 01 04:36:57 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 183092 kb
Host smart-13aeb9ae-833a-434c-a474-e948bcee31be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900655318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.900655318
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3425564453
Short name T393
Test name
Test status
Simulation time 40342191838 ps
CPU time 57.04 seconds
Started Jul 01 04:36:56 PM PDT 24
Finished Jul 01 04:37:57 PM PDT 24
Peak memory 183104 kb
Host smart-cf77801f-3585-4dbe-828c-e873e15c511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425564453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3425564453
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.508289344
Short name T450
Test name
Test status
Simulation time 37604707299 ps
CPU time 66.59 seconds
Started Jul 01 04:36:58 PM PDT 24
Finished Jul 01 04:38:08 PM PDT 24
Peak memory 194448 kb
Host smart-3e50b674-72b7-4181-94b6-e5d3e55bc36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508289344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.508289344
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1042644462
Short name T349
Test name
Test status
Simulation time 2390735899 ps
CPU time 2.62 seconds
Started Jul 01 04:36:55 PM PDT 24
Finished Jul 01 04:37:01 PM PDT 24
Peak memory 182984 kb
Host smart-7322a28d-05b3-4ddb-ac75-808cf8f0ec11
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042644462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1042644462
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3281171407
Short name T19
Test name
Test status
Simulation time 270796635081 ps
CPU time 84.89 seconds
Started Jul 01 04:36:53 PM PDT 24
Finished Jul 01 04:38:22 PM PDT 24
Peak memory 183312 kb
Host smart-841907c5-f4fb-4b18-8bc5-4cda91ca7a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281171407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3281171407
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.1876439296
Short name T170
Test name
Test status
Simulation time 6798009988 ps
CPU time 16.39 seconds
Started Jul 01 04:36:49 PM PDT 24
Finished Jul 01 04:37:11 PM PDT 24
Peak memory 183076 kb
Host smart-ad7392f1-8eea-4fa9-aae5-27e2d02c35e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876439296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.1876439296
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2916173020
Short name T237
Test name
Test status
Simulation time 40449574297 ps
CPU time 64.17 seconds
Started Jul 01 04:36:51 PM PDT 24
Finished Jul 01 04:38:01 PM PDT 24
Peak memory 191176 kb
Host smart-a8588c33-2823-4830-827a-1db70a79ec61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916173020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2916173020
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4138986388
Short name T68
Test name
Test status
Simulation time 192494890043 ps
CPU time 342.79 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:42:11 PM PDT 24
Peak memory 183044 kb
Host smart-167afbeb-c1b9-4a95-86dd-3bf467996ce6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138986388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.4138986388
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2546959078
Short name T403
Test name
Test status
Simulation time 315466176666 ps
CPU time 128.95 seconds
Started Jul 01 04:36:14 PM PDT 24
Finished Jul 01 04:38:38 PM PDT 24
Peak memory 183104 kb
Host smart-6562d758-7623-4455-a31e-1228a070e155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546959078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2546959078
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.501974653
Short name T257
Test name
Test status
Simulation time 173982549679 ps
CPU time 307.03 seconds
Started Jul 01 04:36:10 PM PDT 24
Finished Jul 01 04:41:32 PM PDT 24
Peak memory 191360 kb
Host smart-c2344ece-02a7-48d0-bc11-5401418fdfa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501974653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.501974653
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3772257441
Short name T395
Test name
Test status
Simulation time 798956238 ps
CPU time 0.8 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:36:29 PM PDT 24
Peak memory 182956 kb
Host smart-1dced241-0767-4e84-ae61-f5e28632f3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772257441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3772257441
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1561034347
Short name T223
Test name
Test status
Simulation time 357603826513 ps
CPU time 247.8 seconds
Started Jul 01 04:36:12 PM PDT 24
Finished Jul 01 04:40:35 PM PDT 24
Peak memory 193200 kb
Host smart-5614afd0-0ad5-4dcd-aeab-6378c817cc14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561034347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1561034347
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.3760991910
Short name T85
Test name
Test status
Simulation time 93978279557 ps
CPU time 1038.76 seconds
Started Jul 01 04:36:11 PM PDT 24
Finished Jul 01 04:53:44 PM PDT 24
Peak memory 212688 kb
Host smart-71f3c8be-a7b6-4ec0-b144-832079e1c914
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760991910 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.3760991910
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.90016418
Short name T240
Test name
Test status
Simulation time 334796149315 ps
CPU time 140.19 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 04:39:24 PM PDT 24
Peak memory 191288 kb
Host smart-bee8f5e2-bfc0-470a-a6fe-69eee7baf8f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90016418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.90016418
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.2201883627
Short name T131
Test name
Test status
Simulation time 15916126385 ps
CPU time 23.64 seconds
Started Jul 01 04:36:53 PM PDT 24
Finished Jul 01 04:37:21 PM PDT 24
Peak memory 182996 kb
Host smart-1b809e81-4c04-4a4d-b8ce-9322ef85fece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201883627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.2201883627
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2162620380
Short name T339
Test name
Test status
Simulation time 35128014387 ps
CPU time 25.92 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 04:37:29 PM PDT 24
Peak memory 191292 kb
Host smart-6cdd0e3c-33b8-4cd2-8b2e-cdfce32d70f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162620380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2162620380
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2158433602
Short name T306
Test name
Test status
Simulation time 23113107030 ps
CPU time 35.6 seconds
Started Jul 01 04:36:51 PM PDT 24
Finished Jul 01 04:37:31 PM PDT 24
Peak memory 183004 kb
Host smart-0acd3cfe-6a34-42f5-a3f7-866b1e4dc7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158433602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2158433602
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.362524846
Short name T202
Test name
Test status
Simulation time 174305031456 ps
CPU time 301.81 seconds
Started Jul 01 04:36:55 PM PDT 24
Finished Jul 01 04:42:01 PM PDT 24
Peak memory 191368 kb
Host smart-08cadadb-8d02-4a7e-bd10-3d3fb081884c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362524846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.362524846
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.652671027
Short name T127
Test name
Test status
Simulation time 34739268278 ps
CPU time 65.02 seconds
Started Jul 01 04:36:55 PM PDT 24
Finished Jul 01 04:38:04 PM PDT 24
Peak memory 191192 kb
Host smart-2ac600f6-147d-436d-bc9f-363e3800ee46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652671027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.652671027
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2858300039
Short name T440
Test name
Test status
Simulation time 123596901923 ps
CPU time 864.79 seconds
Started Jul 01 04:36:49 PM PDT 24
Finished Jul 01 04:51:19 PM PDT 24
Peak memory 191292 kb
Host smart-2e28906b-f6da-4c26-98fc-901f2ec332aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858300039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2858300039
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3417267126
Short name T208
Test name
Test status
Simulation time 89709564911 ps
CPU time 42.16 seconds
Started Jul 01 04:36:51 PM PDT 24
Finished Jul 01 04:37:38 PM PDT 24
Peak memory 183092 kb
Host smart-dc60b598-3f88-40e6-92a5-3b14ff54ae37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417267126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3417267126
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.4014928672
Short name T385
Test name
Test status
Simulation time 58072941981 ps
CPU time 70.33 seconds
Started Jul 01 04:36:21 PM PDT 24
Finished Jul 01 04:37:44 PM PDT 24
Peak memory 183000 kb
Host smart-48f6209e-f983-4aed-8f0b-809f4950def2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014928672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.4014928672
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.407426169
Short name T71
Test name
Test status
Simulation time 253731451918 ps
CPU time 218.38 seconds
Started Jul 01 04:36:14 PM PDT 24
Finished Jul 01 04:40:07 PM PDT 24
Peak memory 194880 kb
Host smart-ddbd8a6e-eb69-404b-86a1-304fbeca5876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407426169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.407426169
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2876466033
Short name T319
Test name
Test status
Simulation time 20530709738 ps
CPU time 5.47 seconds
Started Jul 01 04:36:29 PM PDT 24
Finished Jul 01 04:36:42 PM PDT 24
Peak memory 183000 kb
Host smart-547744dd-93d0-477d-b0ff-c2fcfa1102d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876466033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2876466033
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1154910037
Short name T276
Test name
Test status
Simulation time 303727482003 ps
CPU time 516.51 seconds
Started Jul 01 04:36:14 PM PDT 24
Finished Jul 01 04:45:05 PM PDT 24
Peak memory 191288 kb
Host smart-5984d986-a8be-479b-9d57-6797921e4c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154910037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1154910037
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.3359755457
Short name T13
Test name
Test status
Simulation time 37579387232 ps
CPU time 366.3 seconds
Started Jul 01 04:36:45 PM PDT 24
Finished Jul 01 04:42:55 PM PDT 24
Peak memory 205888 kb
Host smart-2db6c34a-5e20-44e9-a300-f7cc6bd9eda7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359755457 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.3359755457
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.rv_timer_random.2869135776
Short name T329
Test name
Test status
Simulation time 560948989423 ps
CPU time 395.42 seconds
Started Jul 01 04:37:04 PM PDT 24
Finished Jul 01 04:43:41 PM PDT 24
Peak memory 191196 kb
Host smart-08fb3db9-ec06-4b08-a577-429ca7d3c08d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869135776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2869135776
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.349752318
Short name T411
Test name
Test status
Simulation time 66199394225 ps
CPU time 49.87 seconds
Started Jul 01 04:36:55 PM PDT 24
Finished Jul 01 04:37:49 PM PDT 24
Peak memory 183088 kb
Host smart-89dada99-97da-4d6b-8f78-3b6794cff092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349752318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.349752318
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.754687898
Short name T251
Test name
Test status
Simulation time 128641026274 ps
CPU time 103.31 seconds
Started Jul 01 04:36:52 PM PDT 24
Finished Jul 01 04:38:41 PM PDT 24
Peak memory 183056 kb
Host smart-ea3b6b9b-7ef4-40ce-8d98-faaf77943143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754687898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.754687898
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1158419187
Short name T267
Test name
Test status
Simulation time 407385930916 ps
CPU time 983.58 seconds
Started Jul 01 04:36:52 PM PDT 24
Finished Jul 01 04:53:21 PM PDT 24
Peak memory 194224 kb
Host smart-6849a583-7a12-40f1-8758-61bc95a15d52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158419187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1158419187
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.326793131
Short name T444
Test name
Test status
Simulation time 27932236706 ps
CPU time 240.55 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:41:03 PM PDT 24
Peak memory 183304 kb
Host smart-7f0f8b7c-a34b-4c3c-9366-ab78a88b714f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326793131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.326793131
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2157502926
Short name T239
Test name
Test status
Simulation time 128785852916 ps
CPU time 493 seconds
Started Jul 01 04:36:57 PM PDT 24
Finished Jul 01 04:45:14 PM PDT 24
Peak memory 191292 kb
Host smart-aa37fe83-6a9b-4f6f-95ce-6bc7a2d0266c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157502926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2157502926
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.22292205
Short name T288
Test name
Test status
Simulation time 43164242259 ps
CPU time 108.69 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:38:54 PM PDT 24
Peak memory 183024 kb
Host smart-49f5265a-d158-4062-a9b5-b44590fe1cb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22292205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.22292205
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3502936759
Short name T322
Test name
Test status
Simulation time 1004406984535 ps
CPU time 156.9 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:39:42 PM PDT 24
Peak memory 191184 kb
Host smart-4c3262ce-dddd-403b-a261-25b983e1d715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502936759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3502936759
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.502414845
Short name T430
Test name
Test status
Simulation time 10961289264 ps
CPU time 18.99 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:36:50 PM PDT 24
Peak memory 182708 kb
Host smart-9b81ea27-75aa-4afd-8c54-3e21ddf0b89b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502414845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.502414845
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1618344349
Short name T400
Test name
Test status
Simulation time 513277482946 ps
CPU time 200.53 seconds
Started Jul 01 04:36:25 PM PDT 24
Finished Jul 01 04:39:55 PM PDT 24
Peak memory 182996 kb
Host smart-3b120f2a-c95f-4324-8533-fb9bd1dd9f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618344349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1618344349
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.325770223
Short name T130
Test name
Test status
Simulation time 486106100628 ps
CPU time 324.19 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:41:52 PM PDT 24
Peak memory 193744 kb
Host smart-42657d3b-3699-499d-b8c6-fe2081226490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325770223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.325770223
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3411586802
Short name T326
Test name
Test status
Simulation time 95793971037 ps
CPU time 60.57 seconds
Started Jul 01 04:36:10 PM PDT 24
Finished Jul 01 04:37:26 PM PDT 24
Peak memory 191144 kb
Host smart-c4edb687-411f-4a7a-8f1d-5752704c7299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411586802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3411586802
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.4044749680
Short name T147
Test name
Test status
Simulation time 666407372122 ps
CPU time 3958.99 seconds
Started Jul 01 04:36:14 PM PDT 24
Finished Jul 01 05:42:28 PM PDT 24
Peak memory 191292 kb
Host smart-168d7ecd-18aa-4ea3-b642-93f9240a6a65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044749680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
4044749680
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.1243018291
Short name T72
Test name
Test status
Simulation time 51591547668 ps
CPU time 218.56 seconds
Started Jul 01 04:37:01 PM PDT 24
Finished Jul 01 04:40:43 PM PDT 24
Peak memory 182984 kb
Host smart-d4fa66b7-e831-4268-b98e-83f8110d27cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243018291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1243018291
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2964083251
Short name T298
Test name
Test status
Simulation time 265264963431 ps
CPU time 648.69 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:47:52 PM PDT 24
Peak memory 191252 kb
Host smart-e52b1090-dac3-44ba-80bd-eb35e0bb07bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964083251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2964083251
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.74655077
Short name T145
Test name
Test status
Simulation time 228724718668 ps
CPU time 2023.2 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 05:10:47 PM PDT 24
Peak memory 191324 kb
Host smart-2fcb919b-60c5-494e-9e47-6bf930d9e745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74655077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.74655077
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1265559010
Short name T190
Test name
Test status
Simulation time 377263785871 ps
CPU time 164.99 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:39:48 PM PDT 24
Peak memory 191288 kb
Host smart-7d965c2d-3998-4665-9d40-3cbb5fbdd289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265559010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1265559010
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.1382033838
Short name T242
Test name
Test status
Simulation time 101183055834 ps
CPU time 536.56 seconds
Started Jul 01 04:37:01 PM PDT 24
Finished Jul 01 04:46:01 PM PDT 24
Peak memory 191236 kb
Host smart-7bdc05d7-b3c1-4a8b-918a-6e1f7f00cc57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382033838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.1382033838
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2336241903
Short name T187
Test name
Test status
Simulation time 74384540153 ps
CPU time 42.5 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 04:37:46 PM PDT 24
Peak memory 191424 kb
Host smart-afb1f682-9d6e-44fa-b49e-7a2b4d1fec27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336241903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2336241903
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2673803757
Short name T227
Test name
Test status
Simulation time 129656259409 ps
CPU time 536.01 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:45:59 PM PDT 24
Peak memory 191284 kb
Host smart-4336a2e6-0c2d-4457-a875-c61cbfc2718e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673803757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2673803757
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.301804158
Short name T268
Test name
Test status
Simulation time 127971787724 ps
CPU time 323.53 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:42:28 PM PDT 24
Peak memory 191172 kb
Host smart-6bfdb085-c2a6-46c3-9979-7354953f65fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301804158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.301804158
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3786437790
Short name T255
Test name
Test status
Simulation time 131032145633 ps
CPU time 483.02 seconds
Started Jul 01 04:37:01 PM PDT 24
Finished Jul 01 04:45:07 PM PDT 24
Peak memory 191196 kb
Host smart-ee540f64-ae4f-42c6-ab7a-07b693b9d7ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786437790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3786437790
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.57925620
Short name T128
Test name
Test status
Simulation time 802418354680 ps
CPU time 210.55 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:40:33 PM PDT 24
Peak memory 191408 kb
Host smart-241797b6-13f1-4f0f-8b25-3ef3788d017b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57925620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.57925620
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1398623370
Short name T417
Test name
Test status
Simulation time 362290235275 ps
CPU time 629.95 seconds
Started Jul 01 04:36:11 PM PDT 24
Finished Jul 01 04:46:56 PM PDT 24
Peak memory 183076 kb
Host smart-3912ac64-a02f-487e-83e8-d50e8188b50c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398623370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1398623370
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2758253332
Short name T367
Test name
Test status
Simulation time 365590597848 ps
CPU time 279.25 seconds
Started Jul 01 04:36:13 PM PDT 24
Finished Jul 01 04:41:07 PM PDT 24
Peak memory 183100 kb
Host smart-b3989737-3a98-4dce-9ca5-d9d38b6ea14b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758253332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2758253332
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3287572880
Short name T22
Test name
Test status
Simulation time 125126797308 ps
CPU time 249.92 seconds
Started Jul 01 04:36:12 PM PDT 24
Finished Jul 01 04:40:38 PM PDT 24
Peak memory 191284 kb
Host smart-3c602ccd-a8a7-48e5-81e7-1a921efcc226
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287572880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3287572880
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3952789532
Short name T346
Test name
Test status
Simulation time 59486967048 ps
CPU time 65.92 seconds
Started Jul 01 04:36:10 PM PDT 24
Finished Jul 01 04:37:31 PM PDT 24
Peak memory 191368 kb
Host smart-9e535256-74c4-4d30-ace3-1efebca0c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952789532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3952789532
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.2106448691
Short name T34
Test name
Test status
Simulation time 58415909890 ps
CPU time 640.71 seconds
Started Jul 01 04:36:11 PM PDT 24
Finished Jul 01 04:47:08 PM PDT 24
Peak memory 206140 kb
Host smart-e569b51f-26df-4d3c-868b-289634480ef2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106448691 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.2106448691
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.4224254441
Short name T273
Test name
Test status
Simulation time 135439025190 ps
CPU time 125.25 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:39:08 PM PDT 24
Peak memory 183092 kb
Host smart-9838458e-481b-44f1-9587-52db22aef500
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224254441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4224254441
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3309443707
Short name T301
Test name
Test status
Simulation time 143516707092 ps
CPU time 117.45 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:39:00 PM PDT 24
Peak memory 191292 kb
Host smart-e54bb2ec-c7da-4946-8058-0a4f3213da62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309443707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3309443707
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1827382149
Short name T111
Test name
Test status
Simulation time 400222466261 ps
CPU time 168.94 seconds
Started Jul 01 04:36:57 PM PDT 24
Finished Jul 01 04:39:50 PM PDT 24
Peak memory 191284 kb
Host smart-0f6b824d-a57d-4191-8132-573d7a0984f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827382149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1827382149
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.4212587509
Short name T446
Test name
Test status
Simulation time 154201884538 ps
CPU time 329.84 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 04:42:34 PM PDT 24
Peak memory 183232 kb
Host smart-98ef442d-0e47-4630-b15b-1f9b5a797c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212587509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.4212587509
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2688391732
Short name T209
Test name
Test status
Simulation time 97991554420 ps
CPU time 1033.16 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 04:54:17 PM PDT 24
Peak memory 191304 kb
Host smart-d6735886-4fc9-40dd-a537-97653bcbb3fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688391732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2688391732
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.884060406
Short name T141
Test name
Test status
Simulation time 188133469478 ps
CPU time 361.58 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:43:04 PM PDT 24
Peak memory 191408 kb
Host smart-aff715de-ec7d-4299-bff3-2d5af8f97180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884060406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.884060406
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.4190273494
Short name T139
Test name
Test status
Simulation time 90925127294 ps
CPU time 133.63 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:39:19 PM PDT 24
Peak memory 191292 kb
Host smart-5e83ae20-5450-4b12-b45e-b42925fc3aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190273494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.4190273494
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.193964235
Short name T155
Test name
Test status
Simulation time 88565799595 ps
CPU time 157.86 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:39:43 PM PDT 24
Peak memory 191352 kb
Host smart-53f70bc4-5b1d-4be5-9d36-6e20afa33fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193964235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.193964235
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.2310021990
Short name T402
Test name
Test status
Simulation time 362307556252 ps
CPU time 450.1 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:44:36 PM PDT 24
Peak memory 191348 kb
Host smart-d0461bb7-a9d5-447c-9fdb-a29a233079ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310021990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2310021990
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2157536840
Short name T157
Test name
Test status
Simulation time 135402432968 ps
CPU time 65.26 seconds
Started Jul 01 04:36:20 PM PDT 24
Finished Jul 01 04:37:38 PM PDT 24
Peak memory 183068 kb
Host smart-52b67748-d436-4c70-90a1-88b32df62bc0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157536840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2157536840
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.328854144
Short name T370
Test name
Test status
Simulation time 261590792844 ps
CPU time 94.86 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:38:05 PM PDT 24
Peak memory 183096 kb
Host smart-9213717b-4176-4d98-a3ee-611aca6da81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328854144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.328854144
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3623646026
Short name T318
Test name
Test status
Simulation time 41394127540 ps
CPU time 31.44 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:37:02 PM PDT 24
Peak memory 192464 kb
Host smart-0ef82af0-9685-4a61-8ed8-3a4dc9ad7ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623646026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3623646026
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.4019719473
Short name T425
Test name
Test status
Simulation time 1862004650 ps
CPU time 13.73 seconds
Started Jul 01 04:36:17 PM PDT 24
Finished Jul 01 04:36:44 PM PDT 24
Peak memory 183024 kb
Host smart-13e95d2f-5a3d-49eb-99e1-5b2070c2c8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019719473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.4019719473
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.4199796533
Short name T356
Test name
Test status
Simulation time 595409601028 ps
CPU time 408.36 seconds
Started Jul 01 04:36:12 PM PDT 24
Finished Jul 01 04:43:16 PM PDT 24
Peak memory 195080 kb
Host smart-d4a461ee-bf38-406d-b05d-4e0617136ca7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199796533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
4199796533
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.3447534305
Short name T282
Test name
Test status
Simulation time 33102379641 ps
CPU time 46.84 seconds
Started Jul 01 04:37:01 PM PDT 24
Finished Jul 01 04:37:51 PM PDT 24
Peak memory 182996 kb
Host smart-a3c469a0-65ac-4b08-866f-427b7f9a6530
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447534305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3447534305
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.839161418
Short name T254
Test name
Test status
Simulation time 42970882807 ps
CPU time 57.56 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:38:00 PM PDT 24
Peak memory 191192 kb
Host smart-e1c353d6-75f5-4a36-82f8-a878ab2ed6e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839161418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.839161418
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.23042012
Short name T335
Test name
Test status
Simulation time 171727508158 ps
CPU time 201.87 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:40:27 PM PDT 24
Peak memory 191192 kb
Host smart-0998ed6d-2cc1-476d-bd0e-c74f2efda342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23042012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.23042012
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3716952748
Short name T177
Test name
Test status
Simulation time 69292714055 ps
CPU time 95.76 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:38:41 PM PDT 24
Peak memory 191276 kb
Host smart-1b6138cd-0dec-4ce3-bf48-2ccc911f5d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716952748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3716952748
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1129836725
Short name T81
Test name
Test status
Simulation time 340637209185 ps
CPU time 475.53 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 04:44:59 PM PDT 24
Peak memory 191288 kb
Host smart-401a5efc-6eee-40ae-95bb-f022f7987398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129836725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1129836725
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1457543309
Short name T258
Test name
Test status
Simulation time 352737752000 ps
CPU time 411.49 seconds
Started Jul 01 04:36:59 PM PDT 24
Finished Jul 01 04:43:54 PM PDT 24
Peak memory 191304 kb
Host smart-5b3e9059-c4be-48ca-a972-b5feb6f92772
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457543309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1457543309
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2958516041
Short name T289
Test name
Test status
Simulation time 156373451209 ps
CPU time 466.15 seconds
Started Jul 01 04:37:00 PM PDT 24
Finished Jul 01 04:44:50 PM PDT 24
Peak memory 191156 kb
Host smart-d20bfbcf-7e0a-4540-9f80-f9d1e8cf6e19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958516041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2958516041
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2158895217
Short name T195
Test name
Test status
Simulation time 57234187542 ps
CPU time 31.62 seconds
Started Jul 01 04:37:02 PM PDT 24
Finished Jul 01 04:37:36 PM PDT 24
Peak memory 191236 kb
Host smart-3e54b340-ac14-43d8-955c-5b5d256ba1a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158895217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2158895217
Directory /workspace/99.rv_timer_random/latest
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