Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
129178083 |
1 |
|
T1 |
148776 |
|
T2 |
72783 |
|
T3 |
47584 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
59563072 |
1 |
|
T1 |
1330 |
|
T2 |
72685 |
|
T3 |
28695 |
auto[1] |
69615011 |
1 |
|
T1 |
147446 |
|
T2 |
98 |
|
T3 |
18889 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
129172291 |
1 |
|
T1 |
148766 |
|
T2 |
72777 |
|
T3 |
47579 |
auto[1] |
5792 |
1 |
|
T1 |
10 |
|
T2 |
6 |
|
T3 |
5 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
59559988 |
1 |
|
T1 |
1328 |
|
T2 |
72679 |
|
T3 |
28692 |
all_values[0] |
auto[0] |
auto[1] |
3084 |
1 |
|
T1 |
2 |
|
T2 |
6 |
|
T3 |
3 |
all_values[0] |
auto[1] |
auto[0] |
69612303 |
1 |
|
T1 |
147438 |
|
T2 |
98 |
|
T3 |
18887 |
all_values[0] |
auto[1] |
auto[1] |
2708 |
1 |
|
T1 |
8 |
|
T3 |
2 |
|
T5 |
2 |