Summary for Variable cp_intr_pin
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr_pin
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
129178083 |
1 |
|
T1 |
148776 |
|
T2 |
72783 |
|
T3 |
47584 |
Summary for Variable cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for cp_intr_pin_value
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
values[0x0] |
129175375 |
1 |
|
T1 |
148768 |
|
T2 |
72783 |
|
T3 |
47582 |
values[0x1] |
2708 |
1 |
|
T1 |
8 |
|
T3 |
2 |
|
T5 |
2 |
transitions[0x0=>0x1] |
866 |
1 |
|
T1 |
3 |
|
T3 |
1 |
|
T5 |
1 |
transitions[0x1=>0x0] |
866 |
1 |
|
T1 |
3 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Cross cp_intr_pins_all_values
Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_intr_pins_all_values
Bins
cp_intr_pin | cp_intr_pin_value | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_pins[0] |
values[0x0] |
129175375 |
1 |
|
T1 |
148768 |
|
T2 |
72783 |
|
T3 |
47582 |
all_pins[0] |
values[0x1] |
2708 |
1 |
|
T1 |
8 |
|
T3 |
2 |
|
T5 |
2 |
all_pins[0] |
transitions[0x0=>0x1] |
866 |
1 |
|
T1 |
3 |
|
T3 |
1 |
|
T5 |
1 |
all_pins[0] |
transitions[0x1=>0x0] |
866 |
1 |
|
T1 |
3 |
|
T3 |
1 |
|
T5 |
1 |