Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.51 99.36 98.73 100.00 100.00 100.00 98.98


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1000767173 Jul 03 04:48:34 PM PDT 24 Jul 03 04:48:35 PM PDT 24 30569474 ps
T509 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.594701145 Jul 03 04:48:34 PM PDT 24 Jul 03 04:48:34 PM PDT 24 15530950 ps
T510 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.923070580 Jul 03 04:48:31 PM PDT 24 Jul 03 04:48:32 PM PDT 24 19824143 ps
T511 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2900882321 Jul 03 04:48:38 PM PDT 24 Jul 03 04:48:39 PM PDT 24 104039756 ps
T512 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2734166220 Jul 03 04:48:28 PM PDT 24 Jul 03 04:48:29 PM PDT 24 14290211 ps
T513 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.811918123 Jul 03 04:48:24 PM PDT 24 Jul 03 04:48:25 PM PDT 24 38779931 ps
T514 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3408573265 Jul 03 04:48:31 PM PDT 24 Jul 03 04:48:38 PM PDT 24 16845383 ps
T515 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.321901187 Jul 03 04:48:20 PM PDT 24 Jul 03 04:48:21 PM PDT 24 15374258 ps
T516 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.344007616 Jul 03 04:48:46 PM PDT 24 Jul 03 04:48:47 PM PDT 24 31441368 ps
T517 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.858443938 Jul 03 04:48:42 PM PDT 24 Jul 03 04:48:43 PM PDT 24 21330630 ps
T518 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3948856375 Jul 03 04:48:28 PM PDT 24 Jul 03 04:48:29 PM PDT 24 153772952 ps
T519 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3394186000 Jul 03 04:48:22 PM PDT 24 Jul 03 04:48:23 PM PDT 24 111139669 ps
T520 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1321196323 Jul 03 04:48:21 PM PDT 24 Jul 03 04:48:23 PM PDT 24 191112507 ps
T521 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1699318249 Jul 03 04:48:35 PM PDT 24 Jul 03 04:48:37 PM PDT 24 37639881 ps
T522 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1847421940 Jul 03 04:48:37 PM PDT 24 Jul 03 04:48:39 PM PDT 24 325622107 ps
T523 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3255792613 Jul 03 04:48:26 PM PDT 24 Jul 03 04:48:27 PM PDT 24 32594332 ps
T524 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1930942550 Jul 03 04:48:18 PM PDT 24 Jul 03 04:48:20 PM PDT 24 17999917 ps
T525 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2462437756 Jul 03 04:48:30 PM PDT 24 Jul 03 04:48:31 PM PDT 24 29665919 ps
T526 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.595642151 Jul 03 04:48:30 PM PDT 24 Jul 03 04:48:31 PM PDT 24 56257494 ps
T527 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1057056097 Jul 03 04:48:47 PM PDT 24 Jul 03 04:48:48 PM PDT 24 33522480 ps
T528 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1102737731 Jul 03 04:48:33 PM PDT 24 Jul 03 04:48:35 PM PDT 24 26790519 ps
T529 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1945146593 Jul 03 04:48:21 PM PDT 24 Jul 03 04:48:23 PM PDT 24 24352320 ps
T530 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2683262541 Jul 03 04:48:20 PM PDT 24 Jul 03 04:48:22 PM PDT 24 35783936 ps
T531 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3901195708 Jul 03 04:48:30 PM PDT 24 Jul 03 04:48:31 PM PDT 24 58981513 ps
T81 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2269687333 Jul 03 04:48:29 PM PDT 24 Jul 03 04:48:30 PM PDT 24 23355656 ps
T532 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1334139746 Jul 03 04:48:35 PM PDT 24 Jul 03 04:48:36 PM PDT 24 35343094 ps
T533 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1984607534 Jul 03 04:48:13 PM PDT 24 Jul 03 04:48:17 PM PDT 24 135388519 ps
T534 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3165359212 Jul 03 04:48:32 PM PDT 24 Jul 03 04:48:34 PM PDT 24 536375230 ps
T86 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3080227330 Jul 03 04:48:15 PM PDT 24 Jul 03 04:48:20 PM PDT 24 431234901 ps
T535 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1337026654 Jul 03 04:48:19 PM PDT 24 Jul 03 04:48:21 PM PDT 24 259111013 ps
T536 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2513469503 Jul 03 04:48:19 PM PDT 24 Jul 03 04:48:21 PM PDT 24 106400188 ps
T82 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.689975010 Jul 03 04:48:15 PM PDT 24 Jul 03 04:48:17 PM PDT 24 35704105 ps
T537 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3023895065 Jul 03 04:48:21 PM PDT 24 Jul 03 04:48:22 PM PDT 24 82777003 ps
T538 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.481846944 Jul 03 04:48:19 PM PDT 24 Jul 03 04:48:21 PM PDT 24 13336687 ps
T539 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1935637135 Jul 03 04:48:39 PM PDT 24 Jul 03 04:48:40 PM PDT 24 138673275 ps
T540 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.909255440 Jul 03 04:48:35 PM PDT 24 Jul 03 04:48:36 PM PDT 24 16831010 ps
T541 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1763348634 Jul 03 04:48:51 PM PDT 24 Jul 03 04:48:52 PM PDT 24 18092599 ps
T542 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.667663453 Jul 03 04:48:16 PM PDT 24 Jul 03 04:48:19 PM PDT 24 41516348 ps
T543 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2765118650 Jul 03 04:48:36 PM PDT 24 Jul 03 04:48:37 PM PDT 24 13970255 ps
T544 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1805853608 Jul 03 04:48:36 PM PDT 24 Jul 03 04:48:37 PM PDT 24 64995688 ps
T545 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2435399030 Jul 03 04:48:33 PM PDT 24 Jul 03 04:48:35 PM PDT 24 94154995 ps
T546 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2758882218 Jul 03 04:48:57 PM PDT 24 Jul 03 04:48:58 PM PDT 24 219075617 ps
T547 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.4074203537 Jul 03 04:48:42 PM PDT 24 Jul 03 04:48:43 PM PDT 24 12094891 ps
T548 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3570414339 Jul 03 04:48:29 PM PDT 24 Jul 03 04:48:29 PM PDT 24 14814567 ps
T549 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2495459795 Jul 03 04:48:42 PM PDT 24 Jul 03 04:48:43 PM PDT 24 15229708 ps
T550 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2255613228 Jul 03 04:48:35 PM PDT 24 Jul 03 04:48:36 PM PDT 24 13974808 ps
T551 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.4108263950 Jul 03 04:48:32 PM PDT 24 Jul 03 04:48:33 PM PDT 24 39354432 ps
T552 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.817033032 Jul 03 04:48:18 PM PDT 24 Jul 03 04:48:20 PM PDT 24 54206580 ps
T553 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.81343847 Jul 03 04:48:39 PM PDT 24 Jul 03 04:48:40 PM PDT 24 48632698 ps
T83 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3227330900 Jul 03 04:48:33 PM PDT 24 Jul 03 04:48:34 PM PDT 24 43357444 ps
T554 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1521080501 Jul 03 04:48:34 PM PDT 24 Jul 03 04:48:35 PM PDT 24 24727614 ps
T555 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3304756428 Jul 03 04:48:37 PM PDT 24 Jul 03 04:48:38 PM PDT 24 39302748 ps
T556 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2091393550 Jul 03 04:48:24 PM PDT 24 Jul 03 04:48:25 PM PDT 24 145598719 ps
T557 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2560525642 Jul 03 04:48:17 PM PDT 24 Jul 03 04:48:20 PM PDT 24 24222779 ps
T558 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4221630171 Jul 03 04:48:51 PM PDT 24 Jul 03 04:48:53 PM PDT 24 18337216 ps
T559 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.416605987 Jul 03 04:48:30 PM PDT 24 Jul 03 04:48:31 PM PDT 24 46644271 ps
T560 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.8463309 Jul 03 04:48:29 PM PDT 24 Jul 03 04:48:32 PM PDT 24 38404326 ps
T561 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.617421495 Jul 03 04:48:18 PM PDT 24 Jul 03 04:48:20 PM PDT 24 90617675 ps
T562 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4015923583 Jul 03 04:48:30 PM PDT 24 Jul 03 04:48:31 PM PDT 24 18638397 ps
T563 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2111562020 Jul 03 04:48:15 PM PDT 24 Jul 03 04:48:18 PM PDT 24 112328174 ps
T564 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2138403229 Jul 03 04:48:42 PM PDT 24 Jul 03 04:48:43 PM PDT 24 12397323 ps
T565 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4050897986 Jul 03 04:48:15 PM PDT 24 Jul 03 04:48:16 PM PDT 24 142681689 ps
T566 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.410073217 Jul 03 04:48:21 PM PDT 24 Jul 03 04:48:22 PM PDT 24 54293597 ps
T567 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3005006037 Jul 03 04:48:35 PM PDT 24 Jul 03 04:48:36 PM PDT 24 13135185 ps
T84 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4166339060 Jul 03 04:48:16 PM PDT 24 Jul 03 04:48:19 PM PDT 24 145834054 ps
T568 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1098067857 Jul 03 04:48:21 PM PDT 24 Jul 03 04:48:23 PM PDT 24 95730797 ps
T569 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2305037092 Jul 03 04:48:18 PM PDT 24 Jul 03 04:48:20 PM PDT 24 66199553 ps
T570 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2508821658 Jul 03 04:48:21 PM PDT 24 Jul 03 04:48:23 PM PDT 24 172574292 ps
T571 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1402253617 Jul 03 04:48:22 PM PDT 24 Jul 03 04:48:23 PM PDT 24 72580602 ps
T572 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1023380071 Jul 03 04:48:34 PM PDT 24 Jul 03 04:48:35 PM PDT 24 70819729 ps
T573 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1315858639 Jul 03 04:48:35 PM PDT 24 Jul 03 04:48:36 PM PDT 24 18135498 ps
T574 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.422043559 Jul 03 04:48:25 PM PDT 24 Jul 03 04:48:26 PM PDT 24 214111913 ps
T87 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3316200399 Jul 03 04:48:18 PM PDT 24 Jul 03 04:48:23 PM PDT 24 1631683100 ps
T575 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1338489862 Jul 03 04:48:30 PM PDT 24 Jul 03 04:48:33 PM PDT 24 660818516 ps
T576 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2045097727 Jul 03 04:48:17 PM PDT 24 Jul 03 04:48:20 PM PDT 24 1510582921 ps
T577 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2834343639 Jul 03 04:48:35 PM PDT 24 Jul 03 04:48:36 PM PDT 24 77663575 ps
T578 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1897668458 Jul 03 04:48:30 PM PDT 24 Jul 03 04:48:32 PM PDT 24 43623710 ps
T579 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3962190752 Jul 03 04:48:21 PM PDT 24 Jul 03 04:48:23 PM PDT 24 85077127 ps
T85 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.815873837 Jul 03 04:48:21 PM PDT 24 Jul 03 04:48:22 PM PDT 24 12771547 ps
T580 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.35786575 Jul 03 04:48:21 PM PDT 24 Jul 03 04:48:23 PM PDT 24 50407753 ps

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.2718361722
Short name T9
Test name
Test status
Simulation time 84792724933 ps
CPU time 526.81 seconds
Started Jul 03 05:05:31 PM PDT 24
Finished Jul 03 05:14:18 PM PDT 24
Peak memory 206596 kb
Host smart-7fa1b4dc-b46b-4b25-a134-6d64fa3b2e6c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718361722 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.2718361722
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2120946271
Short name T12
Test name
Test status
Simulation time 1333926388148 ps
CPU time 575.52 seconds
Started Jul 03 05:05:57 PM PDT 24
Finished Jul 03 05:15:33 PM PDT 24
Peak memory 183068 kb
Host smart-37875a3f-086c-4adc-ae71-86d20546372b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120946271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2120946271
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3019954964
Short name T62
Test name
Test status
Simulation time 3515315131385 ps
CPU time 2294.18 seconds
Started Jul 03 05:05:43 PM PDT 24
Finished Jul 03 05:43:58 PM PDT 24
Peak memory 191316 kb
Host smart-5e7eff21-799f-453f-934b-29059928f1c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019954964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3019954964
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3201051229
Short name T29
Test name
Test status
Simulation time 128900315 ps
CPU time 1.38 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 194888 kb
Host smart-0d35d788-53bc-4a61-abc7-02e44242ab6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201051229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3201051229
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.931901365
Short name T25
Test name
Test status
Simulation time 2685194253144 ps
CPU time 1040.3 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:22:40 PM PDT 24
Peak memory 191196 kb
Host smart-10fc992e-174b-4175-aa98-28d981e4ab66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931901365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.931901365
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1512654707
Short name T54
Test name
Test status
Simulation time 768011238183 ps
CPU time 1974.89 seconds
Started Jul 03 05:05:43 PM PDT 24
Finished Jul 03 05:38:38 PM PDT 24
Peak memory 191316 kb
Host smart-ff983c27-368b-43df-877a-0fbe22505004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512654707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1512654707
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1971419787
Short name T100
Test name
Test status
Simulation time 2263552789698 ps
CPU time 1422.17 seconds
Started Jul 03 05:05:54 PM PDT 24
Finished Jul 03 05:29:37 PM PDT 24
Peak memory 191284 kb
Host smart-2bbbff78-3388-416f-b846-73487ded6334
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971419787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1971419787
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.60686315
Short name T36
Test name
Test status
Simulation time 60788733912 ps
CPU time 331.02 seconds
Started Jul 03 05:05:30 PM PDT 24
Finished Jul 03 05:11:01 PM PDT 24
Peak memory 205992 kb
Host smart-79163551-1621-4889-838c-13ca1b3634df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60686315 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.60686315
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1759263468
Short name T65
Test name
Test status
Simulation time 469757444806 ps
CPU time 1635.72 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:32:36 PM PDT 24
Peak memory 191280 kb
Host smart-90284d71-36fc-405b-91e8-fe2f05d82dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759263468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1759263468
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1866215512
Short name T208
Test name
Test status
Simulation time 2861088001302 ps
CPU time 2809.52 seconds
Started Jul 03 05:05:46 PM PDT 24
Finished Jul 03 05:52:37 PM PDT 24
Peak memory 191284 kb
Host smart-4ef3bf56-94fe-4417-a95f-1cad65a5267a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866215512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1866215512
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1424209341
Short name T94
Test name
Test status
Simulation time 457388743080 ps
CPU time 897.24 seconds
Started Jul 03 05:05:20 PM PDT 24
Finished Jul 03 05:20:20 PM PDT 24
Peak memory 191260 kb
Host smart-8912b459-3af6-42b6-b1e5-725cf4b7cdbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424209341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1424209341
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2386789943
Short name T339
Test name
Test status
Simulation time 594062354721 ps
CPU time 4265.96 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 06:17:14 PM PDT 24
Peak memory 191252 kb
Host smart-690b14b0-8c07-4484-a82c-3439cd27001a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386789943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2386789943
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.756519323
Short name T15
Test name
Test status
Simulation time 186452872 ps
CPU time 0.92 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:05:20 PM PDT 24
Peak memory 214368 kb
Host smart-3f0b32b9-d265-40c9-b663-bb9ee8796559
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756519323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.756519323
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3054584315
Short name T199
Test name
Test status
Simulation time 1239001166899 ps
CPU time 1304.09 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:27:56 PM PDT 24
Peak memory 191300 kb
Host smart-14e35b1d-1393-4050-9672-ae7cef31e2d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054584315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3054584315
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2339705074
Short name T263
Test name
Test status
Simulation time 2553216228505 ps
CPU time 1631.64 seconds
Started Jul 03 05:05:46 PM PDT 24
Finished Jul 03 05:32:59 PM PDT 24
Peak memory 191312 kb
Host smart-0d6ae1bb-69d0-4693-874c-812380437820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339705074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2339705074
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2208337329
Short name T158
Test name
Test status
Simulation time 343633725552 ps
CPU time 1376.82 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:28:41 PM PDT 24
Peak memory 191296 kb
Host smart-8d43ae41-1ff4-4417-bf2b-6292b4183006
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208337329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2208337329
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2168589241
Short name T64
Test name
Test status
Simulation time 1112155556702 ps
CPU time 1200.31 seconds
Started Jul 03 05:05:21 PM PDT 24
Finished Jul 03 05:25:24 PM PDT 24
Peak memory 191304 kb
Host smart-c29a9c85-9190-4bf5-8d80-98a1f84c1596
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168589241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2168589241
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1451913611
Short name T63
Test name
Test status
Simulation time 1808661424177 ps
CPU time 916.92 seconds
Started Jul 03 05:05:57 PM PDT 24
Finished Jul 03 05:21:14 PM PDT 24
Peak memory 191280 kb
Host smart-df531317-98e9-482f-bd53-8d35c35555a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451913611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1451913611
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.4102415226
Short name T141
Test name
Test status
Simulation time 748699318191 ps
CPU time 4977.45 seconds
Started Jul 03 05:05:42 PM PDT 24
Finished Jul 03 06:28:40 PM PDT 24
Peak memory 191168 kb
Host smart-b7ad5b62-0907-4819-bc79-157d1e51cb3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102415226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.4102415226
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/119.rv_timer_random.3353429206
Short name T46
Test name
Test status
Simulation time 493369854393 ps
CPU time 2139.08 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:41:51 PM PDT 24
Peak memory 191316 kb
Host smart-859d2645-ee8a-4820-9c15-d640308b9131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353429206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3353429206
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2661450469
Short name T190
Test name
Test status
Simulation time 672381468666 ps
CPU time 1155.49 seconds
Started Jul 03 05:06:15 PM PDT 24
Finished Jul 03 05:25:31 PM PDT 24
Peak memory 191172 kb
Host smart-e94c45ed-37ba-4194-8b4c-8fe64ab46e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661450469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2661450469
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3504907806
Short name T134
Test name
Test status
Simulation time 352199661361 ps
CPU time 1011.31 seconds
Started Jul 03 05:05:42 PM PDT 24
Finished Jul 03 05:22:34 PM PDT 24
Peak memory 190636 kb
Host smart-b2380b2e-185a-4053-a946-ecfb9a1a8e75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504907806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3504907806
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/105.rv_timer_random.1629364271
Short name T245
Test name
Test status
Simulation time 128040942136 ps
CPU time 415.81 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:13:04 PM PDT 24
Peak memory 190748 kb
Host smart-c18d633f-46ec-4b85-88e5-0a02e01c826e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629364271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1629364271
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1736031747
Short name T127
Test name
Test status
Simulation time 1387961810870 ps
CPU time 1039.01 seconds
Started Jul 03 05:06:15 PM PDT 24
Finished Jul 03 05:23:35 PM PDT 24
Peak memory 191332 kb
Host smart-955cbb06-7bbc-4c5a-88d3-630f8b68ccc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736031747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1736031747
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3968130244
Short name T213
Test name
Test status
Simulation time 175147959121 ps
CPU time 658.41 seconds
Started Jul 03 05:06:21 PM PDT 24
Finished Jul 03 05:17:20 PM PDT 24
Peak memory 191328 kb
Host smart-5d812f5c-f8e0-4346-af40-b5aaaddbefc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968130244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3968130244
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.110016262
Short name T262
Test name
Test status
Simulation time 5422175759130 ps
CPU time 1356.47 seconds
Started Jul 03 05:05:43 PM PDT 24
Finished Jul 03 05:28:20 PM PDT 24
Peak memory 195936 kb
Host smart-6f9adc7e-d222-4bb9-b1f5-af3543715fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110016262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
110016262
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3561980361
Short name T105
Test name
Test status
Simulation time 1343787863859 ps
CPU time 1524.01 seconds
Started Jul 03 05:05:56 PM PDT 24
Finished Jul 03 05:31:21 PM PDT 24
Peak memory 195428 kb
Host smart-008f5e8d-ace1-47f2-b1ca-b1979fce3579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561980361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3561980361
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1144542927
Short name T230
Test name
Test status
Simulation time 444399027543 ps
CPU time 1945.4 seconds
Started Jul 03 05:05:42 PM PDT 24
Finished Jul 03 05:38:08 PM PDT 24
Peak memory 191328 kb
Host smart-b2c75153-e73c-428e-b0f8-cdf0ce389884
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144542927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1144542927
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.4190785672
Short name T66
Test name
Test status
Simulation time 1977604210505 ps
CPU time 1224.98 seconds
Started Jul 03 05:05:46 PM PDT 24
Finished Jul 03 05:26:12 PM PDT 24
Peak memory 197012 kb
Host smart-6741921a-6178-45fa-a07e-171cbd63ab5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190785672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.4190785672
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_random.3323223118
Short name T288
Test name
Test status
Simulation time 133978701010 ps
CPU time 571.56 seconds
Started Jul 03 05:05:58 PM PDT 24
Finished Jul 03 05:15:30 PM PDT 24
Peak memory 191316 kb
Host smart-4050ad1b-dc90-4f1a-b88c-1652a3eddcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323223118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3323223118
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.1301158272
Short name T118
Test name
Test status
Simulation time 99331372277 ps
CPU time 282.62 seconds
Started Jul 03 05:05:45 PM PDT 24
Finished Jul 03 05:10:28 PM PDT 24
Peak memory 191280 kb
Host smart-bceb853c-d43d-4a4d-805c-71b1f7b1db6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301158272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1301158272
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1569995891
Short name T197
Test name
Test status
Simulation time 547729728799 ps
CPU time 648.42 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:16:07 PM PDT 24
Peak memory 183088 kb
Host smart-24b1cbf6-6253-4795-842e-21b997211cd2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569995891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1569995891
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3316200399
Short name T87
Test name
Test status
Simulation time 1631683100 ps
CPU time 3.66 seconds
Started Jul 03 04:48:18 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 190528 kb
Host smart-dec5026a-2d15-4cd8-b0d9-1a846033cf5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316200399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3316200399
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/104.rv_timer_random.2930276284
Short name T166
Test name
Test status
Simulation time 135060691306 ps
CPU time 308.62 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:11:19 PM PDT 24
Peak memory 191268 kb
Host smart-c8a5b4a2-8621-416c-b7a7-49c660aeafa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930276284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2930276284
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2510675161
Short name T70
Test name
Test status
Simulation time 529324280637 ps
CPU time 282.86 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:11:00 PM PDT 24
Peak memory 191316 kb
Host smart-bea1be63-7aad-4d7c-bf9e-f5a55514b5b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510675161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2510675161
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.3557227025
Short name T115
Test name
Test status
Simulation time 144717984368 ps
CPU time 588.36 seconds
Started Jul 03 05:05:34 PM PDT 24
Finished Jul 03 05:15:23 PM PDT 24
Peak memory 191316 kb
Host smart-b2b1848e-e877-4546-8fdd-538cf4eb8569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557227025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3557227025
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.89004497
Short name T101
Test name
Test status
Simulation time 611318689641 ps
CPU time 1483.25 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:30:27 PM PDT 24
Peak memory 191252 kb
Host smart-6edb9686-e7c9-49c8-aca2-36420978aa78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89004497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.89004497
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1078117199
Short name T114
Test name
Test status
Simulation time 450209053691 ps
CPU time 392.5 seconds
Started Jul 03 05:05:59 PM PDT 24
Finished Jul 03 05:12:32 PM PDT 24
Peak memory 183068 kb
Host smart-968b34be-536e-4c46-a232-e6d7fd9d4e8d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078117199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1078117199
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.724871458
Short name T26
Test name
Test status
Simulation time 1607338104164 ps
CPU time 935.53 seconds
Started Jul 03 05:06:04 PM PDT 24
Finished Jul 03 05:21:40 PM PDT 24
Peak memory 191272 kb
Host smart-19f6c7eb-28ec-405d-b5f8-5a968c941b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724871458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.
724871458
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.964738030
Short name T287
Test name
Test status
Simulation time 949146977405 ps
CPU time 673.41 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:17:24 PM PDT 24
Peak memory 191308 kb
Host smart-ae5d9e5e-6cee-481d-9e58-05147201f0cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964738030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.964738030
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.1585284434
Short name T108
Test name
Test status
Simulation time 692957322709 ps
CPU time 344.81 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:11:52 PM PDT 24
Peak memory 191284 kb
Host smart-a424922b-7af4-4f07-8f59-706f1d80eeba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585284434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1585284434
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.988745856
Short name T110
Test name
Test status
Simulation time 526392850352 ps
CPU time 1484.98 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:30:58 PM PDT 24
Peak memory 191316 kb
Host smart-24d033b3-fa7f-4d55-ae67-a8753a99460f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988745856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.988745856
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.4045940323
Short name T139
Test name
Test status
Simulation time 548072304129 ps
CPU time 933.75 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:21:27 PM PDT 24
Peak memory 191284 kb
Host smart-6016d28a-6968-4c68-a9d4-987885b55ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045940323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.4045940323
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.619921370
Short name T103
Test name
Test status
Simulation time 198944215979 ps
CPU time 156.31 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:08:30 PM PDT 24
Peak memory 191252 kb
Host smart-95261d4b-ac05-4fb3-910c-a61194959088
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619921370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.619921370
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random.122921996
Short name T140
Test name
Test status
Simulation time 234001523031 ps
CPU time 526.65 seconds
Started Jul 03 05:05:20 PM PDT 24
Finished Jul 03 05:14:10 PM PDT 24
Peak memory 191320 kb
Host smart-19535d87-0308-4832-abcb-611f5b8f7788
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122921996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.122921996
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.2709993127
Short name T321
Test name
Test status
Simulation time 147850304867 ps
CPU time 578.97 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:15:01 PM PDT 24
Peak memory 191300 kb
Host smart-68da51d7-1a3a-476f-92ff-6b3caa319382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709993127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2709993127
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.912630696
Short name T209
Test name
Test status
Simulation time 133576061532 ps
CPU time 229.86 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:09:57 PM PDT 24
Peak memory 191208 kb
Host smart-29a664bc-23c1-43b0-857f-3d502fa73789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912630696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.912630696
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2644134164
Short name T168
Test name
Test status
Simulation time 112923694180 ps
CPU time 202.5 seconds
Started Jul 03 05:06:08 PM PDT 24
Finished Jul 03 05:09:31 PM PDT 24
Peak memory 191336 kb
Host smart-b9cb3bd3-b416-4130-b865-f5d65f5d912a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644134164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2644134164
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2381982505
Short name T135
Test name
Test status
Simulation time 226778076002 ps
CPU time 515.4 seconds
Started Jul 03 05:06:14 PM PDT 24
Finished Jul 03 05:14:50 PM PDT 24
Peak memory 194576 kb
Host smart-12c032f8-57f8-40be-892c-de1547c07f28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381982505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2381982505
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.98472957
Short name T150
Test name
Test status
Simulation time 790155173900 ps
CPU time 237.27 seconds
Started Jul 03 05:05:32 PM PDT 24
Finished Jul 03 05:09:30 PM PDT 24
Peak memory 191280 kb
Host smart-25d42b79-65bb-43ce-ac1a-d6ad8b800377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98472957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.98472957
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.593678691
Short name T172
Test name
Test status
Simulation time 322648720535 ps
CPU time 143.69 seconds
Started Jul 03 05:05:36 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 191284 kb
Host smart-9326f984-620d-4200-87d9-ee98c09aab49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593678691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.593678691
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/193.rv_timer_random.1511982055
Short name T129
Test name
Test status
Simulation time 157721808431 ps
CPU time 258.91 seconds
Started Jul 03 05:06:27 PM PDT 24
Finished Jul 03 05:10:46 PM PDT 24
Peak memory 191308 kb
Host smart-94437e86-f535-4fba-a707-e20d4d3265b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511982055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1511982055
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1229326368
Short name T298
Test name
Test status
Simulation time 69089938360 ps
CPU time 58.27 seconds
Started Jul 03 05:06:23 PM PDT 24
Finished Jul 03 05:07:21 PM PDT 24
Peak memory 191316 kb
Host smart-340b93bb-985d-47df-b43e-5403095a55f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229326368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1229326368
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random.642286587
Short name T203
Test name
Test status
Simulation time 474802208386 ps
CPU time 765.85 seconds
Started Jul 03 05:05:58 PM PDT 24
Finished Jul 03 05:18:45 PM PDT 24
Peak memory 191268 kb
Host smart-0920bd0d-7148-4c44-b1f7-0b403f304e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642286587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.642286587
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1707670478
Short name T35
Test name
Test status
Simulation time 1522959721897 ps
CPU time 1778.37 seconds
Started Jul 03 05:05:57 PM PDT 24
Finished Jul 03 05:35:36 PM PDT 24
Peak memory 195644 kb
Host smart-c6a7308d-2008-49f0-a595-d97e94940c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707670478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1707670478
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2337914067
Short name T90
Test name
Test status
Simulation time 68913963 ps
CPU time 0.8 seconds
Started Jul 03 04:48:15 PM PDT 24
Finished Jul 03 04:48:17 PM PDT 24
Peak memory 192880 kb
Host smart-30066490-e520-4f91-9e0e-77484bc85356
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337914067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2337914067
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.350840406
Short name T96
Test name
Test status
Simulation time 625723051 ps
CPU time 1.36 seconds
Started Jul 03 04:48:12 PM PDT 24
Finished Jul 03 04:48:13 PM PDT 24
Peak memory 195388 kb
Host smart-2ce2f998-c933-4bff-93f3-b1904b9683e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350840406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.350840406
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2201802288
Short name T254
Test name
Test status
Simulation time 167819734989 ps
CPU time 291.56 seconds
Started Jul 03 05:05:39 PM PDT 24
Finished Jul 03 05:10:31 PM PDT 24
Peak memory 183068 kb
Host smart-8ca35155-6d8a-4660-ad5d-0d182d4b9d5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201802288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2201802288
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/110.rv_timer_random.3476624800
Short name T191
Test name
Test status
Simulation time 400769175157 ps
CPU time 412.06 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:13:05 PM PDT 24
Peak memory 191292 kb
Host smart-b5658178-5773-4d4c-ae1d-4a6b00bf17d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476624800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3476624800
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1214320421
Short name T160
Test name
Test status
Simulation time 155710690190 ps
CPU time 259.31 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:10:30 PM PDT 24
Peak memory 191244 kb
Host smart-6e91970d-3aea-4c10-8997-d8072172a447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214320421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1214320421
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.361278385
Short name T261
Test name
Test status
Simulation time 521184384184 ps
CPU time 295.6 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:11:07 PM PDT 24
Peak memory 194640 kb
Host smart-9073765a-1fcb-498d-80c4-bb8d4d6d3b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361278385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.361278385
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3028822748
Short name T210
Test name
Test status
Simulation time 3048106880278 ps
CPU time 802.07 seconds
Started Jul 03 05:05:37 PM PDT 24
Finished Jul 03 05:18:59 PM PDT 24
Peak memory 191168 kb
Host smart-60089794-cc1d-4523-97d5-4c0f129310af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028822748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3028822748
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.73269372
Short name T155
Test name
Test status
Simulation time 767680620689 ps
CPU time 384.62 seconds
Started Jul 03 05:05:24 PM PDT 24
Finished Jul 03 05:11:49 PM PDT 24
Peak memory 191308 kb
Host smart-3ab90545-2e76-4f04-83ea-b48647488ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73269372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.73269372
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/136.rv_timer_random.1825279950
Short name T238
Test name
Test status
Simulation time 511159387157 ps
CPU time 1620.73 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:33:18 PM PDT 24
Peak memory 191316 kb
Host smart-d6cb5d46-60d5-43ec-a8d5-cd8d95adca5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825279950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1825279950
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3748758517
Short name T284
Test name
Test status
Simulation time 549423797115 ps
CPU time 689.39 seconds
Started Jul 03 05:06:22 PM PDT 24
Finished Jul 03 05:17:52 PM PDT 24
Peak memory 191308 kb
Host smart-e5b45d01-66a8-45db-8545-fd07a7c06fa0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748758517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3748758517
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.4180848674
Short name T187
Test name
Test status
Simulation time 210033979822 ps
CPU time 185.13 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:09:18 PM PDT 24
Peak memory 191308 kb
Host smart-a9d809f6-7c3f-4548-89f7-88fd8ec7c53f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180848674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.4180848674
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2148979501
Short name T268
Test name
Test status
Simulation time 44148912854 ps
CPU time 68.16 seconds
Started Jul 03 05:06:20 PM PDT 24
Finished Jul 03 05:07:29 PM PDT 24
Peak memory 191308 kb
Host smart-b6bd3c5e-d896-4080-94a1-3ee0da486206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148979501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2148979501
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.4000264457
Short name T194
Test name
Test status
Simulation time 511275774974 ps
CPU time 967.02 seconds
Started Jul 03 05:06:14 PM PDT 24
Finished Jul 03 05:22:22 PM PDT 24
Peak memory 191284 kb
Host smart-246185e8-619e-441e-9cb2-3c1078d8e433
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000264457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.4000264457
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1656011505
Short name T204
Test name
Test status
Simulation time 3654747493284 ps
CPU time 742.48 seconds
Started Jul 03 05:05:48 PM PDT 24
Finished Jul 03 05:18:11 PM PDT 24
Peak memory 183096 kb
Host smart-e5cf8567-502f-4309-af90-167e364bec73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656011505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1656011505
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/161.rv_timer_random.792399744
Short name T299
Test name
Test status
Simulation time 787718705074 ps
CPU time 286.76 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:10:55 PM PDT 24
Peak memory 191324 kb
Host smart-5567972a-e282-481a-b485-48ec277ced42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792399744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.792399744
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.702998104
Short name T120
Test name
Test status
Simulation time 25499999551 ps
CPU time 55.97 seconds
Started Jul 03 05:06:14 PM PDT 24
Finished Jul 03 05:07:11 PM PDT 24
Peak memory 191284 kb
Host smart-4b2a85fc-1a58-409f-8374-c04335b94bc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702998104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.702998104
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1585081887
Short name T205
Test name
Test status
Simulation time 119310180110 ps
CPU time 815.24 seconds
Started Jul 03 05:06:18 PM PDT 24
Finished Jul 03 05:19:54 PM PDT 24
Peak memory 191324 kb
Host smart-9a609483-7002-4a8e-a200-a2bb3e917d05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585081887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1585081887
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.910600456
Short name T207
Test name
Test status
Simulation time 603654131020 ps
CPU time 311.21 seconds
Started Jul 03 05:06:22 PM PDT 24
Finished Jul 03 05:11:34 PM PDT 24
Peak memory 191300 kb
Host smart-3c08c671-2e2b-495c-ab3b-5ec5339a2564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910600456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.910600456
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1445742085
Short name T248
Test name
Test status
Simulation time 90379545463 ps
CPU time 476.62 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:14:14 PM PDT 24
Peak memory 191164 kb
Host smart-ba60216c-4da2-4b2b-96c7-cd37161b1b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445742085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1445742085
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2374988882
Short name T295
Test name
Test status
Simulation time 143708073886 ps
CPU time 296.57 seconds
Started Jul 03 05:06:19 PM PDT 24
Finished Jul 03 05:11:16 PM PDT 24
Peak memory 191256 kb
Host smart-a733556b-92ea-45cd-b122-fd3d555ce7bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374988882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2374988882
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1365304799
Short name T104
Test name
Test status
Simulation time 494114137017 ps
CPU time 832.59 seconds
Started Jul 03 05:06:21 PM PDT 24
Finished Jul 03 05:20:14 PM PDT 24
Peak memory 192584 kb
Host smart-b3050a44-bce6-4296-a76f-45f0ba02230f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365304799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1365304799
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2050098797
Short name T161
Test name
Test status
Simulation time 222052404010 ps
CPU time 67.55 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:07:16 PM PDT 24
Peak memory 182552 kb
Host smart-06772345-4c1e-415c-8c70-0a51d894160a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050098797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2050098797
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2386534909
Short name T276
Test name
Test status
Simulation time 1473719084563 ps
CPU time 761.94 seconds
Started Jul 03 05:05:39 PM PDT 24
Finished Jul 03 05:18:21 PM PDT 24
Peak memory 183072 kb
Host smart-4f657ff6-240e-4b34-988e-b4e63e25b5e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386534909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2386534909
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/76.rv_timer_random.574899338
Short name T258
Test name
Test status
Simulation time 413714827702 ps
CPU time 548.4 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:15:19 PM PDT 24
Peak memory 191168 kb
Host smart-310b022a-c384-4cb0-a82a-ac48e8349b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574899338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.574899338
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1952844742
Short name T147
Test name
Test status
Simulation time 358845442976 ps
CPU time 155.69 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:08:47 PM PDT 24
Peak memory 191276 kb
Host smart-80f36b98-07ca-4271-9355-a3c096922209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952844742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1952844742
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2277314372
Short name T181
Test name
Test status
Simulation time 114725833133 ps
CPU time 174.03 seconds
Started Jul 03 05:06:18 PM PDT 24
Finished Jul 03 05:09:12 PM PDT 24
Peak memory 191328 kb
Host smart-eb045659-6b05-41fa-96db-7d4b7017ff33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277314372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2277314372
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.622410145
Short name T278
Test name
Test status
Simulation time 84473476673 ps
CPU time 653.71 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:17:06 PM PDT 24
Peak memory 191316 kb
Host smart-42cdfa37-4ad2-48c6-a797-63775e78f442
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622410145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.622410145
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1998322810
Short name T250
Test name
Test status
Simulation time 498378384733 ps
CPU time 1916.95 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:38:14 PM PDT 24
Peak memory 191172 kb
Host smart-50f4b0ed-e8a0-4ca2-8dc0-fca7a45de989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998322810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1998322810
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2484424908
Short name T137
Test name
Test status
Simulation time 139663947369 ps
CPU time 374.92 seconds
Started Jul 03 05:06:09 PM PDT 24
Finished Jul 03 05:12:25 PM PDT 24
Peak memory 191316 kb
Host smart-4d6cb836-5dc6-418f-95b8-b2dbd588867f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484424908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2484424908
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3081171252
Short name T335
Test name
Test status
Simulation time 705505603359 ps
CPU time 340.91 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:11:58 PM PDT 24
Peak memory 191300 kb
Host smart-aa4fea76-472b-472c-beba-314c3f6a323a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081171252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3081171252
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.557077703
Short name T146
Test name
Test status
Simulation time 161625801593 ps
CPU time 298.36 seconds
Started Jul 03 05:06:17 PM PDT 24
Finished Jul 03 05:11:16 PM PDT 24
Peak memory 191280 kb
Host smart-d687dadf-4772-4d07-af91-0cef6ca65b07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557077703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.557077703
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2926979247
Short name T124
Test name
Test status
Simulation time 187960599058 ps
CPU time 449.02 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:13:40 PM PDT 24
Peak memory 191316 kb
Host smart-9ab20749-2719-4ebe-94f6-c8285a150650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926979247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2926979247
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2537407213
Short name T178
Test name
Test status
Simulation time 1395822276596 ps
CPU time 1490.22 seconds
Started Jul 03 05:05:42 PM PDT 24
Finished Jul 03 05:30:32 PM PDT 24
Peak memory 196288 kb
Host smart-d3638d64-c672-4d4c-b499-779c288d36e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537407213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2537407213
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/164.rv_timer_random.3943726460
Short name T291
Test name
Test status
Simulation time 187275822694 ps
CPU time 458.49 seconds
Started Jul 03 05:06:14 PM PDT 24
Finished Jul 03 05:13:54 PM PDT 24
Peak memory 191320 kb
Host smart-e7ea3784-7d7a-4155-8e38-40ae43b3c435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943726460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3943726460
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.4284676465
Short name T384
Test name
Test status
Simulation time 683306946564 ps
CPU time 331.36 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:11:16 PM PDT 24
Peak memory 183068 kb
Host smart-8509170d-5977-44a2-8eb7-89dad01fe6ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284676465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.4284676465
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/180.rv_timer_random.2673169701
Short name T264
Test name
Test status
Simulation time 428577458083 ps
CPU time 292.72 seconds
Started Jul 03 05:06:18 PM PDT 24
Finished Jul 03 05:11:11 PM PDT 24
Peak memory 191324 kb
Host smart-d0f06a27-d537-4a7c-a2ec-da12a2944ef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673169701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2673169701
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2814023019
Short name T319
Test name
Test status
Simulation time 27030134667 ps
CPU time 48.29 seconds
Started Jul 03 05:06:18 PM PDT 24
Finished Jul 03 05:07:07 PM PDT 24
Peak memory 191276 kb
Host smart-b1b55136-d473-4d04-8782-773d0fd1d46b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814023019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2814023019
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3446933593
Short name T221
Test name
Test status
Simulation time 1965314117143 ps
CPU time 500.41 seconds
Started Jul 03 05:05:42 PM PDT 24
Finished Jul 03 05:14:03 PM PDT 24
Peak memory 183096 kb
Host smart-f46080d4-afe6-4085-9c12-226aed861b58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446933593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3446933593
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.1711358347
Short name T169
Test name
Test status
Simulation time 225377378604 ps
CPU time 220.28 seconds
Started Jul 03 05:05:47 PM PDT 24
Finished Jul 03 05:09:28 PM PDT 24
Peak memory 191172 kb
Host smart-893842a6-fc6b-4ab1-8124-35a6d5620798
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711358347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1711358347
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.55956812
Short name T239
Test name
Test status
Simulation time 262922098634 ps
CPU time 388.74 seconds
Started Jul 03 05:05:40 PM PDT 24
Finished Jul 03 05:12:09 PM PDT 24
Peak memory 183136 kb
Host smart-59b615b0-ea45-420a-9b32-008e69c5ad08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55956812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.rv_timer_cfg_update_on_fly.55956812
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1530449101
Short name T165
Test name
Test status
Simulation time 45918050106 ps
CPU time 64.16 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:06:58 PM PDT 24
Peak memory 194936 kb
Host smart-646d8d58-e513-498b-a0ff-262a88e63578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530449101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1530449101
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_random.3499917692
Short name T215
Test name
Test status
Simulation time 228824150443 ps
CPU time 398.87 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:12:32 PM PDT 24
Peak memory 191252 kb
Host smart-07995798-5af2-4db4-a170-560257049c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499917692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3499917692
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.646219949
Short name T325
Test name
Test status
Simulation time 148205705333 ps
CPU time 136.24 seconds
Started Jul 03 05:05:43 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 191300 kb
Host smart-8c686eac-2e1b-42f9-8c83-8b0bff5d3c1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646219949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.646219949
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1024288807
Short name T179
Test name
Test status
Simulation time 883813732274 ps
CPU time 1812.48 seconds
Started Jul 03 05:05:48 PM PDT 24
Finished Jul 03 05:36:01 PM PDT 24
Peak memory 191320 kb
Host smart-b5856a47-a8f7-4192-9631-c99094d3f319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024288807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1024288807
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.1972231561
Short name T107
Test name
Test status
Simulation time 2295247166840 ps
CPU time 534.63 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:15:05 PM PDT 24
Peak memory 191308 kb
Host smart-c7cc311a-6140-42af-9ea5-226e9ac696b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972231561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1972231561
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1562518269
Short name T251
Test name
Test status
Simulation time 2732067936 ps
CPU time 23.3 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:06:31 PM PDT 24
Peak memory 183100 kb
Host smart-6a5cccb6-a696-485a-b2cf-b286d569fa65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562518269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1562518269
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.87273408
Short name T460
Test name
Test status
Simulation time 20188896 ps
CPU time 0.65 seconds
Started Jul 03 04:48:12 PM PDT 24
Finished Jul 03 04:48:13 PM PDT 24
Peak memory 191448 kb
Host smart-f892107c-bf37-4cf6-8861-bdc5df233d99
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87273408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_aliasi
ng.87273408
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3080227330
Short name T86
Test name
Test status
Simulation time 431234901 ps
CPU time 3.64 seconds
Started Jul 03 04:48:15 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 191908 kb
Host smart-e68de581-6b48-4def-a60f-cb58a5bd2e24
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080227330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3080227330
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1446068600
Short name T92
Test name
Test status
Simulation time 38633108 ps
CPU time 0.62 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:22 PM PDT 24
Peak memory 191452 kb
Host smart-62e56cf7-23c3-4b6e-84c3-af6f159135c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446068600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1446068600
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3859087229
Short name T467
Test name
Test status
Simulation time 130272380 ps
CPU time 0.79 seconds
Started Jul 03 04:48:16 PM PDT 24
Finished Jul 03 04:48:18 PM PDT 24
Peak memory 194908 kb
Host smart-5a4553eb-fad6-440b-8fd0-4bf0308bfc8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859087229 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3859087229
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.815873837
Short name T85
Test name
Test status
Simulation time 12771547 ps
CPU time 0.58 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:22 PM PDT 24
Peak memory 182228 kb
Host smart-42708029-9a17-4f66-a9cd-43b20a473a0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815873837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.815873837
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2070376818
Short name T474
Test name
Test status
Simulation time 28910781 ps
CPU time 0.56 seconds
Started Jul 03 04:48:14 PM PDT 24
Finished Jul 03 04:48:16 PM PDT 24
Peak memory 182124 kb
Host smart-b584cafd-e2b6-4083-bb23-4096250901fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070376818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2070376818
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2111562020
Short name T563
Test name
Test status
Simulation time 112328174 ps
CPU time 2.32 seconds
Started Jul 03 04:48:15 PM PDT 24
Finished Jul 03 04:48:18 PM PDT 24
Peak memory 197036 kb
Host smart-b35669ef-70d0-4be6-b503-531233450ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111562020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2111562020
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2508821658
Short name T570
Test name
Test status
Simulation time 172574292 ps
CPU time 0.9 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 193188 kb
Host smart-c0f89f47-2c24-49d4-b301-c28b486d1645
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508821658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2508821658
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.410073217
Short name T566
Test name
Test status
Simulation time 54293597 ps
CPU time 0.74 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:22 PM PDT 24
Peak memory 182240 kb
Host smart-9a9e45f1-8d81-4762-9026-9df5874c8e74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410073217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.410073217
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1459110070
Short name T469
Test name
Test status
Simulation time 356469129 ps
CPU time 1.47 seconds
Started Jul 03 04:48:29 PM PDT 24
Finished Jul 03 04:48:31 PM PDT 24
Peak memory 190560 kb
Host smart-92e4a5da-9ecc-44f5-8493-953b707ed8b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459110070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1459110070
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.4050897986
Short name T565
Test name
Test status
Simulation time 142681689 ps
CPU time 0.58 seconds
Started Jul 03 04:48:15 PM PDT 24
Finished Jul 03 04:48:16 PM PDT 24
Peak memory 182172 kb
Host smart-a3cd3b5e-1d44-4683-a168-8f3650746776
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050897986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.4050897986
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3962190752
Short name T579
Test name
Test status
Simulation time 85077127 ps
CPU time 0.79 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 194632 kb
Host smart-1f24ef86-3acc-454a-a1b3-9891b7335c4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962190752 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3962190752
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2560525642
Short name T557
Test name
Test status
Simulation time 24222779 ps
CPU time 0.56 seconds
Started Jul 03 04:48:17 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 182212 kb
Host smart-eeee090b-3499-4187-a34a-a954428b6b1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560525642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2560525642
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1944886004
Short name T503
Test name
Test status
Simulation time 12358499 ps
CPU time 0.52 seconds
Started Jul 03 04:48:13 PM PDT 24
Finished Jul 03 04:48:14 PM PDT 24
Peak memory 181596 kb
Host smart-510e356f-f3c2-44e7-8195-3ca80a822e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944886004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1944886004
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3408573265
Short name T514
Test name
Test status
Simulation time 16845383 ps
CPU time 0.68 seconds
Started Jul 03 04:48:31 PM PDT 24
Finished Jul 03 04:48:38 PM PDT 24
Peak memory 191232 kb
Host smart-a5e56958-6299-4d2b-b669-134d71f0b0bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408573265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3408573265
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1984607534
Short name T533
Test name
Test status
Simulation time 135388519 ps
CPU time 2.45 seconds
Started Jul 03 04:48:13 PM PDT 24
Finished Jul 03 04:48:17 PM PDT 24
Peak memory 196392 kb
Host smart-05d6e4f2-ab32-498d-b6e5-5036bf5e5518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984607534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1984607534
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.141158237
Short name T458
Test name
Test status
Simulation time 57791084 ps
CPU time 0.87 seconds
Started Jul 03 04:48:23 PM PDT 24
Finished Jul 03 04:48:24 PM PDT 24
Peak memory 196636 kb
Host smart-416cf7d1-72dc-42e8-bf7f-29d7ca3c802b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141158237 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.141158237
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.220345272
Short name T475
Test name
Test status
Simulation time 74240417 ps
CPU time 0.54 seconds
Started Jul 03 04:48:29 PM PDT 24
Finished Jul 03 04:48:30 PM PDT 24
Peak memory 182068 kb
Host smart-6a7dfb38-3ba2-49ad-a6a4-d6de738701ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220345272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.220345272
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2091393550
Short name T556
Test name
Test status
Simulation time 145598719 ps
CPU time 0.5 seconds
Started Jul 03 04:48:24 PM PDT 24
Finished Jul 03 04:48:25 PM PDT 24
Peak memory 181612 kb
Host smart-2bf80216-8503-4ca6-9512-0cb134fcaf1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091393550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2091393550
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3644962026
Short name T76
Test name
Test status
Simulation time 137915023 ps
CPU time 0.63 seconds
Started Jul 03 04:48:27 PM PDT 24
Finished Jul 03 04:48:28 PM PDT 24
Peak memory 191152 kb
Host smart-61414519-5b37-4b9b-b74d-e63d0dd81c9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644962026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3644962026
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.379348626
Short name T466
Test name
Test status
Simulation time 185037712 ps
CPU time 1.02 seconds
Started Jul 03 04:48:27 PM PDT 24
Finished Jul 03 04:48:28 PM PDT 24
Peak memory 196632 kb
Host smart-304c2ada-3f0b-4312-a263-aa6df90acbfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379348626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.379348626
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1000767173
Short name T508
Test name
Test status
Simulation time 30569474 ps
CPU time 0.74 seconds
Started Jul 03 04:48:34 PM PDT 24
Finished Jul 03 04:48:35 PM PDT 24
Peak memory 194008 kb
Host smart-3ea42483-48b2-4625-9326-e26997293407
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000767173 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1000767173
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3570414339
Short name T548
Test name
Test status
Simulation time 14814567 ps
CPU time 0.55 seconds
Started Jul 03 04:48:29 PM PDT 24
Finished Jul 03 04:48:29 PM PDT 24
Peak memory 182096 kb
Host smart-97d0ac3c-bb23-4c7e-a16f-9b5bc83cfbf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570414339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3570414339
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4015923583
Short name T562
Test name
Test status
Simulation time 18638397 ps
CPU time 0.57 seconds
Started Jul 03 04:48:30 PM PDT 24
Finished Jul 03 04:48:31 PM PDT 24
Peak memory 182108 kb
Host smart-f1b9f108-2ea6-4e09-b309-fd53b01f2043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015923583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4015923583
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2748359444
Short name T506
Test name
Test status
Simulation time 70958767 ps
CPU time 0.87 seconds
Started Jul 03 04:48:30 PM PDT 24
Finished Jul 03 04:48:32 PM PDT 24
Peak memory 193076 kb
Host smart-61355396-b897-4bf6-b9d7-e1ceae497b0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748359444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2748359444
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.4214814493
Short name T478
Test name
Test status
Simulation time 187327220 ps
CPU time 2.29 seconds
Started Jul 03 04:48:26 PM PDT 24
Finished Jul 03 04:48:29 PM PDT 24
Peak memory 197008 kb
Host smart-e33e86e2-8b4e-400e-973b-7ace15355091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214814493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.4214814493
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3104498482
Short name T50
Test name
Test status
Simulation time 87959123 ps
CPU time 1.14 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:22 PM PDT 24
Peak memory 194636 kb
Host smart-fd9ba42b-9de4-4f2b-a22c-332fc2290317
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104498482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3104498482
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2140742712
Short name T507
Test name
Test status
Simulation time 39493265 ps
CPU time 0.87 seconds
Started Jul 03 04:48:34 PM PDT 24
Finished Jul 03 04:48:35 PM PDT 24
Peak memory 196184 kb
Host smart-d8a5f695-eced-4256-8968-f0b4071d1818
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140742712 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2140742712
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2255613228
Short name T550
Test name
Test status
Simulation time 13974808 ps
CPU time 0.58 seconds
Started Jul 03 04:48:35 PM PDT 24
Finished Jul 03 04:48:36 PM PDT 24
Peak memory 182248 kb
Host smart-7facbda8-609e-43cf-acfc-9d0fab86a2c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255613228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2255613228
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2998254923
Short name T499
Test name
Test status
Simulation time 80980136 ps
CPU time 0.59 seconds
Started Jul 03 04:48:38 PM PDT 24
Finished Jul 03 04:48:40 PM PDT 24
Peak memory 182192 kb
Host smart-67ba3901-f8ef-4b7c-9db2-23f178797b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998254923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2998254923
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.72581800
Short name T32
Test name
Test status
Simulation time 77996104 ps
CPU time 0.81 seconds
Started Jul 03 04:48:41 PM PDT 24
Finished Jul 03 04:48:43 PM PDT 24
Peak memory 193568 kb
Host smart-dc757afa-c503-4d08-a753-56011c5a6780
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72581800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_tim
er_same_csr_outstanding.72581800
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1699318249
Short name T521
Test name
Test status
Simulation time 37639881 ps
CPU time 1.93 seconds
Started Jul 03 04:48:35 PM PDT 24
Finished Jul 03 04:48:37 PM PDT 24
Peak memory 197020 kb
Host smart-82ec8fe0-d38d-483a-8eac-927201b55a08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699318249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1699318249
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3588201624
Short name T30
Test name
Test status
Simulation time 259798273 ps
CPU time 0.84 seconds
Started Jul 03 04:48:39 PM PDT 24
Finished Jul 03 04:48:41 PM PDT 24
Peak memory 193340 kb
Host smart-d8a4b2b1-8756-4dda-8c78-f799608f3ded
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588201624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3588201624
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3087967974
Short name T498
Test name
Test status
Simulation time 88702493 ps
CPU time 0.75 seconds
Started Jul 03 04:48:32 PM PDT 24
Finished Jul 03 04:48:33 PM PDT 24
Peak memory 195148 kb
Host smart-37af83e6-9eb5-4343-a323-4966dad20a8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087967974 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3087967974
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2485053877
Short name T472
Test name
Test status
Simulation time 29676503 ps
CPU time 0.62 seconds
Started Jul 03 04:48:29 PM PDT 24
Finished Jul 03 04:48:30 PM PDT 24
Peak memory 191456 kb
Host smart-df93d64d-111f-47d2-bbde-2a9910dac415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485053877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2485053877
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.594701145
Short name T509
Test name
Test status
Simulation time 15530950 ps
CPU time 0.57 seconds
Started Jul 03 04:48:34 PM PDT 24
Finished Jul 03 04:48:34 PM PDT 24
Peak memory 181820 kb
Host smart-2f022c7a-d75a-41ab-b46f-adcdadac96bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594701145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.594701145
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3560192287
Short name T48
Test name
Test status
Simulation time 26518525 ps
CPU time 0.71 seconds
Started Jul 03 04:48:26 PM PDT 24
Finished Jul 03 04:48:27 PM PDT 24
Peak memory 191508 kb
Host smart-824411a7-2ec7-4a0e-959c-cb26b36615eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560192287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3560192287
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1338489862
Short name T575
Test name
Test status
Simulation time 660818516 ps
CPU time 2.98 seconds
Started Jul 03 04:48:30 PM PDT 24
Finished Jul 03 04:48:33 PM PDT 24
Peak memory 196988 kb
Host smart-9bc3a191-ece7-4525-a20f-5d04b38973a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338489862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1338489862
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1847421940
Short name T522
Test name
Test status
Simulation time 325622107 ps
CPU time 1.34 seconds
Started Jul 03 04:48:37 PM PDT 24
Finished Jul 03 04:48:39 PM PDT 24
Peak memory 182644 kb
Host smart-e9be64ec-b996-4d37-a0fe-5b8fc1cff525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847421940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1847421940
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.238945293
Short name T483
Test name
Test status
Simulation time 48723271 ps
CPU time 0.75 seconds
Started Jul 03 04:48:41 PM PDT 24
Finished Jul 03 04:48:42 PM PDT 24
Peak memory 194584 kb
Host smart-8eb6c92d-5c20-4eca-8a4d-da79ee77ec1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238945293 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.238945293
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.416605987
Short name T559
Test name
Test status
Simulation time 46644271 ps
CPU time 0.6 seconds
Started Jul 03 04:48:30 PM PDT 24
Finished Jul 03 04:48:31 PM PDT 24
Peak memory 182220 kb
Host smart-1d7ecb02-92e2-455d-acc4-272579eec25e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416605987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.416605987
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1339511270
Short name T462
Test name
Test status
Simulation time 63253856 ps
CPU time 0.55 seconds
Started Jul 03 04:48:31 PM PDT 24
Finished Jul 03 04:48:32 PM PDT 24
Peak memory 182120 kb
Host smart-3fe28b77-de7d-4d9d-ae95-4e11e3946c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339511270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1339511270
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2081646313
Short name T89
Test name
Test status
Simulation time 44534618 ps
CPU time 0.69 seconds
Started Jul 03 04:48:27 PM PDT 24
Finished Jul 03 04:48:33 PM PDT 24
Peak memory 191204 kb
Host smart-319de8b6-d286-4ad2-9915-46e41fc40e61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081646313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2081646313
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.8463309
Short name T560
Test name
Test status
Simulation time 38404326 ps
CPU time 1.98 seconds
Started Jul 03 04:48:29 PM PDT 24
Finished Jul 03 04:48:32 PM PDT 24
Peak memory 197036 kb
Host smart-b90eb673-088a-46c0-bb9e-e95d87a3c0fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8463309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.8463309
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3165359212
Short name T534
Test name
Test status
Simulation time 536375230 ps
CPU time 1.33 seconds
Started Jul 03 04:48:32 PM PDT 24
Finished Jul 03 04:48:34 PM PDT 24
Peak memory 182932 kb
Host smart-abd572d1-e960-4708-9a84-07c6071728db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165359212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3165359212
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2462437756
Short name T525
Test name
Test status
Simulation time 29665919 ps
CPU time 0.82 seconds
Started Jul 03 04:48:30 PM PDT 24
Finished Jul 03 04:48:31 PM PDT 24
Peak memory 194980 kb
Host smart-1fb23336-1e37-493a-9075-c2c091881585
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462437756 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2462437756
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2734166220
Short name T512
Test name
Test status
Simulation time 14290211 ps
CPU time 0.59 seconds
Started Jul 03 04:48:28 PM PDT 24
Finished Jul 03 04:48:29 PM PDT 24
Peak memory 182208 kb
Host smart-429d79b0-2b52-4a97-95c6-760632ad6e61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734166220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2734166220
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2669866849
Short name T502
Test name
Test status
Simulation time 14369494 ps
CPU time 0.57 seconds
Started Jul 03 04:48:32 PM PDT 24
Finished Jul 03 04:48:33 PM PDT 24
Peak memory 182136 kb
Host smart-017a2cdd-cfb0-430e-bfe8-1373a00b21d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669866849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2669866849
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1229589716
Short name T74
Test name
Test status
Simulation time 38769443 ps
CPU time 0.65 seconds
Started Jul 03 04:48:32 PM PDT 24
Finished Jul 03 04:48:33 PM PDT 24
Peak memory 191148 kb
Host smart-0aaff15f-f6ab-431b-bedf-667a17672794
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229589716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1229589716
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2834343639
Short name T577
Test name
Test status
Simulation time 77663575 ps
CPU time 1.04 seconds
Started Jul 03 04:48:35 PM PDT 24
Finished Jul 03 04:48:36 PM PDT 24
Peak memory 196724 kb
Host smart-8b2581b6-a359-4e7f-8018-fdaec1abb394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834343639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2834343639
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2961105052
Short name T501
Test name
Test status
Simulation time 67116266 ps
CPU time 1.11 seconds
Started Jul 03 04:48:31 PM PDT 24
Finished Jul 03 04:48:32 PM PDT 24
Peak memory 182732 kb
Host smart-9adac93b-950a-44f8-9472-736daf721bab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961105052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2961105052
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1102737731
Short name T528
Test name
Test status
Simulation time 26790519 ps
CPU time 1.31 seconds
Started Jul 03 04:48:33 PM PDT 24
Finished Jul 03 04:48:35 PM PDT 24
Peak memory 196996 kb
Host smart-2b5c09ca-94ba-40ce-b685-e394047e10ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102737731 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1102737731
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.10716283
Short name T473
Test name
Test status
Simulation time 14859766 ps
CPU time 0.54 seconds
Started Jul 03 04:48:44 PM PDT 24
Finished Jul 03 04:48:44 PM PDT 24
Peak memory 182088 kb
Host smart-4c52a829-e929-4216-8b9f-109856cb1a73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10716283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.10716283
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.923070580
Short name T510
Test name
Test status
Simulation time 19824143 ps
CPU time 0.55 seconds
Started Jul 03 04:48:31 PM PDT 24
Finished Jul 03 04:48:32 PM PDT 24
Peak memory 181776 kb
Host smart-bbcb2de1-87aa-42cb-a9ce-4a994fe6ffec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923070580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.923070580
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1023380071
Short name T572
Test name
Test status
Simulation time 70819729 ps
CPU time 0.79 seconds
Started Jul 03 04:48:34 PM PDT 24
Finished Jul 03 04:48:35 PM PDT 24
Peak memory 193148 kb
Host smart-b4d2f536-edbc-445a-9493-4b7de85bcab1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023380071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1023380071
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3771850522
Short name T471
Test name
Test status
Simulation time 121949089 ps
CPU time 2.27 seconds
Started Jul 03 04:48:38 PM PDT 24
Finished Jul 03 04:48:41 PM PDT 24
Peak memory 196996 kb
Host smart-073bd3f7-02fb-48f7-bce1-a902b819e10b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771850522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3771850522
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1560015066
Short name T497
Test name
Test status
Simulation time 157388393 ps
CPU time 0.82 seconds
Started Jul 03 04:48:41 PM PDT 24
Finished Jul 03 04:48:42 PM PDT 24
Peak memory 193400 kb
Host smart-24fed45d-b002-45ac-8e01-95eada8443e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560015066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1560015066
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3304756428
Short name T555
Test name
Test status
Simulation time 39302748 ps
CPU time 1 seconds
Started Jul 03 04:48:37 PM PDT 24
Finished Jul 03 04:48:38 PM PDT 24
Peak memory 196868 kb
Host smart-29cc5e0b-8486-4bc2-8e8c-75e1ee287a02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304756428 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3304756428
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1521080501
Short name T554
Test name
Test status
Simulation time 24727614 ps
CPU time 0.58 seconds
Started Jul 03 04:48:34 PM PDT 24
Finished Jul 03 04:48:35 PM PDT 24
Peak memory 182224 kb
Host smart-f33c2494-4fc2-41ed-9644-30405fae92d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521080501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1521080501
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3005006037
Short name T567
Test name
Test status
Simulation time 13135185 ps
CPU time 0.53 seconds
Started Jul 03 04:48:35 PM PDT 24
Finished Jul 03 04:48:36 PM PDT 24
Peak memory 181616 kb
Host smart-629c8e21-73c2-4111-baa4-b1a8a9ac9f6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005006037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3005006037
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3901195708
Short name T531
Test name
Test status
Simulation time 58981513 ps
CPU time 0.74 seconds
Started Jul 03 04:48:30 PM PDT 24
Finished Jul 03 04:48:31 PM PDT 24
Peak memory 191672 kb
Host smart-666dba37-1f3c-4933-a3a3-fe627f0cba85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901195708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3901195708
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1508821013
Short name T504
Test name
Test status
Simulation time 19513868 ps
CPU time 0.9 seconds
Started Jul 03 04:48:40 PM PDT 24
Finished Jul 03 04:48:42 PM PDT 24
Peak memory 195316 kb
Host smart-9bfcd2f0-a3b4-4c6f-b961-4d2efacae954
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508821013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1508821013
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2559127097
Short name T480
Test name
Test status
Simulation time 135029646 ps
CPU time 0.82 seconds
Started Jul 03 04:48:39 PM PDT 24
Finished Jul 03 04:48:41 PM PDT 24
Peak memory 193336 kb
Host smart-3ef7646b-15f3-4cf8-85af-6aaca41607ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559127097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2559127097
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1805853608
Short name T544
Test name
Test status
Simulation time 64995688 ps
CPU time 0.98 seconds
Started Jul 03 04:48:36 PM PDT 24
Finished Jul 03 04:48:37 PM PDT 24
Peak memory 196880 kb
Host smart-74be6855-dcc7-4403-b82c-cc6b44926544
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805853608 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1805853608
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2020894815
Short name T75
Test name
Test status
Simulation time 41246804 ps
CPU time 0.57 seconds
Started Jul 03 04:48:40 PM PDT 24
Finished Jul 03 04:48:41 PM PDT 24
Peak memory 182276 kb
Host smart-cd8de29c-b20d-4082-aaab-79e1f4d0d74c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020894815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2020894815
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1863571426
Short name T454
Test name
Test status
Simulation time 30143808 ps
CPU time 0.56 seconds
Started Jul 03 04:48:32 PM PDT 24
Finished Jul 03 04:48:33 PM PDT 24
Peak memory 182048 kb
Host smart-0676cb6d-76e9-491e-863e-25763c78660d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863571426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1863571426
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3948856375
Short name T518
Test name
Test status
Simulation time 153772952 ps
CPU time 0.83 seconds
Started Jul 03 04:48:28 PM PDT 24
Finished Jul 03 04:48:29 PM PDT 24
Peak memory 192756 kb
Host smart-5fedbc60-2a9b-4f7b-b228-945452b6275e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948856375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3948856375
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.4234895420
Short name T451
Test name
Test status
Simulation time 116904456 ps
CPU time 2.37 seconds
Started Jul 03 04:48:29 PM PDT 24
Finished Jul 03 04:48:32 PM PDT 24
Peak memory 197016 kb
Host smart-9d0f18d1-21ce-4817-99ad-5d0cbf835dca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234895420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.4234895420
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2435399030
Short name T545
Test name
Test status
Simulation time 94154995 ps
CPU time 1.16 seconds
Started Jul 03 04:48:33 PM PDT 24
Finished Jul 03 04:48:35 PM PDT 24
Peak memory 194660 kb
Host smart-ac17bf33-1687-401f-a990-2a98be2fe953
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435399030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2435399030
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3358951042
Short name T484
Test name
Test status
Simulation time 28918272 ps
CPU time 1.21 seconds
Started Jul 03 04:48:39 PM PDT 24
Finished Jul 03 04:48:41 PM PDT 24
Peak memory 197064 kb
Host smart-a6a57937-ccb5-4c51-bd72-ed852a86623c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358951042 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3358951042
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.4108263950
Short name T551
Test name
Test status
Simulation time 39354432 ps
CPU time 0.57 seconds
Started Jul 03 04:48:32 PM PDT 24
Finished Jul 03 04:48:33 PM PDT 24
Peak memory 182184 kb
Host smart-ed2a5a6e-1964-43d0-9981-132751246525
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108263950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.4108263950
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1414135729
Short name T450
Test name
Test status
Simulation time 16938558 ps
CPU time 0.55 seconds
Started Jul 03 04:48:50 PM PDT 24
Finished Jul 03 04:48:52 PM PDT 24
Peak memory 182168 kb
Host smart-7fa4d228-ee10-4c76-a029-546f0cb42792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414135729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1414135729
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1656640443
Short name T49
Test name
Test status
Simulation time 40193716 ps
CPU time 0.85 seconds
Started Jul 03 04:48:42 PM PDT 24
Finished Jul 03 04:48:43 PM PDT 24
Peak memory 191236 kb
Host smart-3199fdd5-100a-449b-bb3e-d01cfbca28ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656640443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1656640443
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2609016783
Short name T61
Test name
Test status
Simulation time 128713669 ps
CPU time 2.27 seconds
Started Jul 03 04:48:36 PM PDT 24
Finished Jul 03 04:48:39 PM PDT 24
Peak memory 197016 kb
Host smart-9afa9df5-f1e3-4bc6-bc6e-37a632bccc0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609016783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2609016783
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2900882321
Short name T511
Test name
Test status
Simulation time 104039756 ps
CPU time 0.87 seconds
Started Jul 03 04:48:38 PM PDT 24
Finished Jul 03 04:48:39 PM PDT 24
Peak memory 193444 kb
Host smart-d9bc5e74-c9f9-4286-8b2b-f55b71f14898
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900882321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2900882321
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.811918123
Short name T513
Test name
Test status
Simulation time 38779931 ps
CPU time 0.65 seconds
Started Jul 03 04:48:24 PM PDT 24
Finished Jul 03 04:48:25 PM PDT 24
Peak memory 191476 kb
Host smart-60c9783b-c92a-4e39-b971-48054853f55b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811918123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.811918123
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.689975010
Short name T82
Test name
Test status
Simulation time 35704105 ps
CPU time 0.57 seconds
Started Jul 03 04:48:15 PM PDT 24
Finished Jul 03 04:48:17 PM PDT 24
Peak memory 182248 kb
Host smart-8b23dffa-efd4-4939-b7ab-a53fd3b2de64
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689975010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.689975010
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2683262541
Short name T530
Test name
Test status
Simulation time 35783936 ps
CPU time 0.95 seconds
Started Jul 03 04:48:20 PM PDT 24
Finished Jul 03 04:48:22 PM PDT 24
Peak memory 196476 kb
Host smart-034187f1-0512-421b-a442-6756d260bc3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683262541 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2683262541
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2242813326
Short name T47
Test name
Test status
Simulation time 19833394 ps
CPU time 0.57 seconds
Started Jul 03 04:48:19 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 181948 kb
Host smart-216c05de-b12a-4155-94bb-57ff4a1953a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242813326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2242813326
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.382586350
Short name T461
Test name
Test status
Simulation time 52924700 ps
CPU time 0.53 seconds
Started Jul 03 04:48:15 PM PDT 24
Finished Jul 03 04:48:17 PM PDT 24
Peak memory 182096 kb
Host smart-014117e1-49bd-48b5-81cd-4ad84cbc4ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382586350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.382586350
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3341957980
Short name T77
Test name
Test status
Simulation time 22076734 ps
CPU time 0.65 seconds
Started Jul 03 04:48:32 PM PDT 24
Finished Jul 03 04:48:33 PM PDT 24
Peak memory 190748 kb
Host smart-88f768b7-b4f0-445d-bea6-3791bdb16cbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341957980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3341957980
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.667663453
Short name T542
Test name
Test status
Simulation time 41516348 ps
CPU time 1.2 seconds
Started Jul 03 04:48:16 PM PDT 24
Finished Jul 03 04:48:19 PM PDT 24
Peak memory 197040 kb
Host smart-9781b018-0834-4890-82eb-29f74ad8220c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667663453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.667663453
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2513469503
Short name T536
Test name
Test status
Simulation time 106400188 ps
CPU time 1.34 seconds
Started Jul 03 04:48:19 PM PDT 24
Finished Jul 03 04:48:21 PM PDT 24
Peak memory 194844 kb
Host smart-4024a9f2-4cb9-4a92-bd32-29474a10ae8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513469503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2513469503
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2758882218
Short name T546
Test name
Test status
Simulation time 219075617 ps
CPU time 0.57 seconds
Started Jul 03 04:48:57 PM PDT 24
Finished Jul 03 04:48:58 PM PDT 24
Peak memory 182140 kb
Host smart-af518253-a336-45ee-aeb8-23fe27498bcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758882218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2758882218
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.909255440
Short name T540
Test name
Test status
Simulation time 16831010 ps
CPU time 0.57 seconds
Started Jul 03 04:48:35 PM PDT 24
Finished Jul 03 04:48:36 PM PDT 24
Peak memory 182128 kb
Host smart-0279a906-8f67-46eb-b73f-915d3ea0cea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909255440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.909255440
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.739571853
Short name T487
Test name
Test status
Simulation time 20799735 ps
CPU time 0.61 seconds
Started Jul 03 04:48:38 PM PDT 24
Finished Jul 03 04:48:39 PM PDT 24
Peak memory 182172 kb
Host smart-9444aefc-ead5-4ce9-be23-689bed5bfc89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739571853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.739571853
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.4013024290
Short name T452
Test name
Test status
Simulation time 92892896 ps
CPU time 0.55 seconds
Started Jul 03 04:48:50 PM PDT 24
Finished Jul 03 04:48:51 PM PDT 24
Peak memory 182140 kb
Host smart-a1ad81aa-1c91-470c-a2e4-005f2b9e35f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013024290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.4013024290
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2138403229
Short name T564
Test name
Test status
Simulation time 12397323 ps
CPU time 0.55 seconds
Started Jul 03 04:48:42 PM PDT 24
Finished Jul 03 04:48:43 PM PDT 24
Peak memory 181592 kb
Host smart-e150e1a0-9fad-41ec-87bc-914fd8121238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138403229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2138403229
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.511621839
Short name T470
Test name
Test status
Simulation time 15539819 ps
CPU time 0.57 seconds
Started Jul 03 04:48:40 PM PDT 24
Finished Jul 03 04:48:41 PM PDT 24
Peak memory 182104 kb
Host smart-d5b9a13a-c3f2-443b-a182-1c5f5e0c8230
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511621839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.511621839
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2654201127
Short name T488
Test name
Test status
Simulation time 42463975 ps
CPU time 0.61 seconds
Started Jul 03 04:48:44 PM PDT 24
Finished Jul 03 04:48:44 PM PDT 24
Peak memory 181592 kb
Host smart-588ef6f3-68c9-426b-b1c5-cb9458b951ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654201127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2654201127
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.4074203537
Short name T547
Test name
Test status
Simulation time 12094891 ps
CPU time 0.6 seconds
Started Jul 03 04:48:42 PM PDT 24
Finished Jul 03 04:48:43 PM PDT 24
Peak memory 182136 kb
Host smart-ca60b71c-6267-4a0c-90a9-b03dd5c2f1ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074203537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.4074203537
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3890372756
Short name T459
Test name
Test status
Simulation time 66281959 ps
CPU time 0.52 seconds
Started Jul 03 04:48:40 PM PDT 24
Finished Jul 03 04:48:42 PM PDT 24
Peak memory 181812 kb
Host smart-da318222-0112-4cab-a959-75bcfe9bee27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890372756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3890372756
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1165296060
Short name T463
Test name
Test status
Simulation time 12931169 ps
CPU time 0.54 seconds
Started Jul 03 04:48:35 PM PDT 24
Finished Jul 03 04:48:36 PM PDT 24
Peak memory 181588 kb
Host smart-ed7aeeb5-644b-4365-aff7-b288b638737a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165296060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1165296060
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3227330900
Short name T83
Test name
Test status
Simulation time 43357444 ps
CPU time 0.64 seconds
Started Jul 03 04:48:33 PM PDT 24
Finished Jul 03 04:48:34 PM PDT 24
Peak memory 182220 kb
Host smart-bf5a7532-8f72-4177-8d83-ccae78331ebe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227330900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3227330900
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.315399745
Short name T79
Test name
Test status
Simulation time 164511226 ps
CPU time 3.2 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:25 PM PDT 24
Peak memory 192052 kb
Host smart-9194cac1-3bf0-43d0-a898-295582410dfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315399745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.315399745
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4166339060
Short name T84
Test name
Test status
Simulation time 145834054 ps
CPU time 0.59 seconds
Started Jul 03 04:48:16 PM PDT 24
Finished Jul 03 04:48:19 PM PDT 24
Peak memory 182208 kb
Host smart-4dbce647-2d36-4dde-a1d0-c93618f413f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166339060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4166339060
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.419804078
Short name T479
Test name
Test status
Simulation time 147316709 ps
CPU time 0.81 seconds
Started Jul 03 04:48:20 PM PDT 24
Finished Jul 03 04:48:21 PM PDT 24
Peak memory 195256 kb
Host smart-bb06e7cf-7122-40fa-a664-f4e147a9b1ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419804078 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.419804078
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2269687333
Short name T81
Test name
Test status
Simulation time 23355656 ps
CPU time 0.57 seconds
Started Jul 03 04:48:29 PM PDT 24
Finished Jul 03 04:48:30 PM PDT 24
Peak memory 181996 kb
Host smart-e250f391-5881-4a6d-bf66-c144f66c674a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269687333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2269687333
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.617421495
Short name T561
Test name
Test status
Simulation time 90617675 ps
CPU time 0.54 seconds
Started Jul 03 04:48:18 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 182136 kb
Host smart-06ad6c85-649d-411a-9ee8-f32ee28e2616
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617421495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.617421495
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.35786575
Short name T580
Test name
Test status
Simulation time 50407753 ps
CPU time 0.77 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 191192 kb
Host smart-18cced3c-dbd5-40a1-a961-f88dc67a5ee2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35786575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_time
r_same_csr_outstanding.35786575
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1336075874
Short name T489
Test name
Test status
Simulation time 153743908 ps
CPU time 2.86 seconds
Started Jul 03 04:48:19 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 197036 kb
Host smart-301c11d7-b6cb-4cac-8458-2282fd01518e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336075874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1336075874
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.1337026654
Short name T535
Test name
Test status
Simulation time 259111013 ps
CPU time 1.14 seconds
Started Jul 03 04:48:19 PM PDT 24
Finished Jul 03 04:48:21 PM PDT 24
Peak memory 194884 kb
Host smart-47a8c54a-92cb-4778-8824-5087b271994b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337026654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.1337026654
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.344007616
Short name T516
Test name
Test status
Simulation time 31441368 ps
CPU time 0.53 seconds
Started Jul 03 04:48:46 PM PDT 24
Finished Jul 03 04:48:47 PM PDT 24
Peak memory 182136 kb
Host smart-a1357df8-633d-4793-ad79-bf7d37b7356d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344007616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.344007616
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4221630171
Short name T558
Test name
Test status
Simulation time 18337216 ps
CPU time 0.55 seconds
Started Jul 03 04:48:51 PM PDT 24
Finished Jul 03 04:48:53 PM PDT 24
Peak memory 182140 kb
Host smart-a85a2b80-9c3e-4510-a106-be580e5af868
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221630171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4221630171
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1763348634
Short name T541
Test name
Test status
Simulation time 18092599 ps
CPU time 0.56 seconds
Started Jul 03 04:48:51 PM PDT 24
Finished Jul 03 04:48:52 PM PDT 24
Peak memory 182124 kb
Host smart-65beafd2-0998-4dc8-9853-616e0dc4b394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763348634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1763348634
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1334139746
Short name T532
Test name
Test status
Simulation time 35343094 ps
CPU time 0.55 seconds
Started Jul 03 04:48:35 PM PDT 24
Finished Jul 03 04:48:36 PM PDT 24
Peak memory 182192 kb
Host smart-16b27392-3012-4d62-afc7-4cee895b06ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334139746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1334139746
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1057056097
Short name T527
Test name
Test status
Simulation time 33522480 ps
CPU time 0.55 seconds
Started Jul 03 04:48:47 PM PDT 24
Finished Jul 03 04:48:48 PM PDT 24
Peak memory 182096 kb
Host smart-3e2a84c0-8d67-420e-bf6b-6f4dcad32436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057056097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1057056097
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2765118650
Short name T543
Test name
Test status
Simulation time 13970255 ps
CPU time 0.57 seconds
Started Jul 03 04:48:36 PM PDT 24
Finished Jul 03 04:48:37 PM PDT 24
Peak memory 182168 kb
Host smart-10fd7635-0f2d-4fbe-8442-75875a8be790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765118650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2765118650
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2495459795
Short name T549
Test name
Test status
Simulation time 15229708 ps
CPU time 0.56 seconds
Started Jul 03 04:48:42 PM PDT 24
Finished Jul 03 04:48:43 PM PDT 24
Peak memory 181604 kb
Host smart-2e750671-9774-49f6-98a6-806e5197472a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495459795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2495459795
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.4088188185
Short name T493
Test name
Test status
Simulation time 20804412 ps
CPU time 0.54 seconds
Started Jul 03 04:48:41 PM PDT 24
Finished Jul 03 04:48:42 PM PDT 24
Peak memory 181816 kb
Host smart-bc0c0936-84b2-44c8-a6f4-5dfd510b3d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088188185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4088188185
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1935637135
Short name T539
Test name
Test status
Simulation time 138673275 ps
CPU time 0.54 seconds
Started Jul 03 04:48:39 PM PDT 24
Finished Jul 03 04:48:40 PM PDT 24
Peak memory 181564 kb
Host smart-9139cb10-1559-46d1-b9d5-b0b87156c493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935637135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1935637135
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1315858639
Short name T573
Test name
Test status
Simulation time 18135498 ps
CPU time 0.52 seconds
Started Jul 03 04:48:35 PM PDT 24
Finished Jul 03 04:48:36 PM PDT 24
Peak memory 181636 kb
Host smart-61f87832-09ab-446b-afce-b2660632e018
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315858639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1315858639
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2594113968
Short name T80
Test name
Test status
Simulation time 46224626 ps
CPU time 0.63 seconds
Started Jul 03 04:48:17 PM PDT 24
Finished Jul 03 04:48:19 PM PDT 24
Peak memory 182220 kb
Host smart-912689cc-1d9f-4fdf-a552-08180b53075f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594113968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2594113968
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.2017159638
Short name T33
Test name
Test status
Simulation time 373310346 ps
CPU time 2.43 seconds
Started Jul 03 04:48:18 PM PDT 24
Finished Jul 03 04:48:22 PM PDT 24
Peak memory 193292 kb
Host smart-5af0c87b-c8e9-48b9-9fd5-07263d4e588e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017159638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.2017159638
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.481846944
Short name T538
Test name
Test status
Simulation time 13336687 ps
CPU time 0.55 seconds
Started Jul 03 04:48:19 PM PDT 24
Finished Jul 03 04:48:21 PM PDT 24
Peak memory 182248 kb
Host smart-326d9c9a-da45-45ce-b067-a0a29cb081bc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481846944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.481846944
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1515011390
Short name T476
Test name
Test status
Simulation time 78252960 ps
CPU time 1.07 seconds
Started Jul 03 04:48:18 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 197072 kb
Host smart-c6ff8ed4-9683-4789-8615-7557b61e7442
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515011390 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1515011390
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1930942550
Short name T524
Test name
Test status
Simulation time 17999917 ps
CPU time 0.6 seconds
Started Jul 03 04:48:18 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 182252 kb
Host smart-7140e9a9-3b8a-4eab-b49f-68510c2acb86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930942550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1930942550
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3769679733
Short name T505
Test name
Test status
Simulation time 38994632 ps
CPU time 0.56 seconds
Started Jul 03 04:48:24 PM PDT 24
Finished Jul 03 04:48:25 PM PDT 24
Peak memory 182144 kb
Host smart-346d2e75-4a28-4ad3-a4a9-ed3bd11656ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769679733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3769679733
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.470873805
Short name T492
Test name
Test status
Simulation time 155045082 ps
CPU time 0.97 seconds
Started Jul 03 04:48:18 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 193904 kb
Host smart-95813c16-c00a-4641-b939-23bdbc7c550b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470873805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.470873805
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2045097727
Short name T576
Test name
Test status
Simulation time 1510582921 ps
CPU time 1.67 seconds
Started Jul 03 04:48:17 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 197000 kb
Host smart-b01e4bf3-a1c1-44db-8c68-74b5b23e8bc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045097727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2045097727
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3267594009
Short name T95
Test name
Test status
Simulation time 216495171 ps
CPU time 1.15 seconds
Started Jul 03 04:48:19 PM PDT 24
Finished Jul 03 04:48:21 PM PDT 24
Peak memory 182692 kb
Host smart-5350f69a-48fe-41f2-bca0-ccfacf966926
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267594009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3267594009
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.769248573
Short name T453
Test name
Test status
Simulation time 14905697 ps
CPU time 0.57 seconds
Started Jul 03 04:48:38 PM PDT 24
Finished Jul 03 04:48:39 PM PDT 24
Peak memory 181756 kb
Host smart-3fc2b562-3e9e-4a21-af17-2902e7926784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769248573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.769248573
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3244322519
Short name T449
Test name
Test status
Simulation time 12058858 ps
CPU time 0.53 seconds
Started Jul 03 04:48:48 PM PDT 24
Finished Jul 03 04:48:49 PM PDT 24
Peak memory 182160 kb
Host smart-98629897-0af8-4e99-b4d4-85e46ca5f53c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244322519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3244322519
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3588396235
Short name T455
Test name
Test status
Simulation time 35791532 ps
CPU time 0.52 seconds
Started Jul 03 04:48:53 PM PDT 24
Finished Jul 03 04:48:55 PM PDT 24
Peak memory 181628 kb
Host smart-5c95a508-60cc-4e79-98c0-3bfd73d22b32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588396235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3588396235
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1893122146
Short name T490
Test name
Test status
Simulation time 13195655 ps
CPU time 0.56 seconds
Started Jul 03 04:48:35 PM PDT 24
Finished Jul 03 04:48:36 PM PDT 24
Peak memory 182128 kb
Host smart-ce7d005f-6d05-45ca-a143-ab710e055617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893122146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1893122146
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.858443938
Short name T517
Test name
Test status
Simulation time 21330630 ps
CPU time 0.55 seconds
Started Jul 03 04:48:42 PM PDT 24
Finished Jul 03 04:48:43 PM PDT 24
Peak memory 181584 kb
Host smart-cfc48d14-069b-4c7a-9c36-02b89c5098d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858443938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.858443938
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3400922132
Short name T495
Test name
Test status
Simulation time 43683127 ps
CPU time 0.56 seconds
Started Jul 03 04:48:40 PM PDT 24
Finished Jul 03 04:48:41 PM PDT 24
Peak memory 182080 kb
Host smart-164f1471-6aa2-4a8a-8cdc-10ed3595b766
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400922132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3400922132
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3519159445
Short name T464
Test name
Test status
Simulation time 52926456 ps
CPU time 0.56 seconds
Started Jul 03 04:48:40 PM PDT 24
Finished Jul 03 04:48:41 PM PDT 24
Peak memory 182088 kb
Host smart-d6708cb9-0ec5-4584-9c6a-307076196a73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519159445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3519159445
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.108979048
Short name T457
Test name
Test status
Simulation time 28329649 ps
CPU time 0.57 seconds
Started Jul 03 04:48:40 PM PDT 24
Finished Jul 03 04:48:41 PM PDT 24
Peak memory 182136 kb
Host smart-738863f1-d43e-41b6-9c18-e10adc522266
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108979048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.108979048
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3855129024
Short name T477
Test name
Test status
Simulation time 178396120 ps
CPU time 0.54 seconds
Started Jul 03 04:48:37 PM PDT 24
Finished Jul 03 04:48:38 PM PDT 24
Peak memory 182148 kb
Host smart-da6fca3c-8ef0-443a-a56b-e5fcad8542b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855129024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3855129024
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.81343847
Short name T553
Test name
Test status
Simulation time 48632698 ps
CPU time 0.6 seconds
Started Jul 03 04:48:39 PM PDT 24
Finished Jul 03 04:48:40 PM PDT 24
Peak memory 182156 kb
Host smart-0fbbc6f9-6214-4131-a525-484077085762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81343847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.81343847
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1982741065
Short name T481
Test name
Test status
Simulation time 25688818 ps
CPU time 0.8 seconds
Started Jul 03 04:48:18 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 195064 kb
Host smart-12ed08c2-bc0e-4257-8678-ee767fed42f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982741065 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1982741065
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3787187244
Short name T491
Test name
Test status
Simulation time 44061593 ps
CPU time 0.54 seconds
Started Jul 03 04:48:24 PM PDT 24
Finished Jul 03 04:48:25 PM PDT 24
Peak memory 182244 kb
Host smart-b30bb778-6a7b-4447-bb69-2674762f6b61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787187244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3787187244
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4216781085
Short name T482
Test name
Test status
Simulation time 46634507 ps
CPU time 0.54 seconds
Started Jul 03 04:48:15 PM PDT 24
Finished Jul 03 04:48:17 PM PDT 24
Peak memory 182132 kb
Host smart-86aa261e-d191-45c2-a603-2a5035251c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216781085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4216781085
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1741910851
Short name T73
Test name
Test status
Simulation time 59045512 ps
CPU time 0.71 seconds
Started Jul 03 04:48:19 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 191172 kb
Host smart-a6b13a8a-dff5-4a9a-9ded-f764fbd1809c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741910851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1741910851
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.924043319
Short name T486
Test name
Test status
Simulation time 30421464 ps
CPU time 1.51 seconds
Started Jul 03 04:48:20 PM PDT 24
Finished Jul 03 04:48:22 PM PDT 24
Peak memory 197024 kb
Host smart-f014678b-6cce-402c-905a-edfe888b1d43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924043319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.924043319
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3840923348
Short name T31
Test name
Test status
Simulation time 73678484 ps
CPU time 1.11 seconds
Started Jul 03 04:48:33 PM PDT 24
Finished Jul 03 04:48:34 PM PDT 24
Peak memory 194728 kb
Host smart-a3bf0fc2-6867-4d60-afa0-109655f593b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840923348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3840923348
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1098067857
Short name T568
Test name
Test status
Simulation time 95730797 ps
CPU time 1.16 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 196984 kb
Host smart-1d651866-5b7e-415e-b4e0-27e198be5121
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098067857 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1098067857
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2305037092
Short name T569
Test name
Test status
Simulation time 66199553 ps
CPU time 0.57 seconds
Started Jul 03 04:48:18 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 182228 kb
Host smart-0809d699-88a2-4025-9490-3e339dd9d6d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305037092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2305037092
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.595642151
Short name T526
Test name
Test status
Simulation time 56257494 ps
CPU time 0.58 seconds
Started Jul 03 04:48:30 PM PDT 24
Finished Jul 03 04:48:31 PM PDT 24
Peak memory 182140 kb
Host smart-80468ab3-c5d9-4b6c-8bda-70e58a15a348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595642151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.595642151
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1986561604
Short name T88
Test name
Test status
Simulation time 38367829 ps
CPU time 0.8 seconds
Started Jul 03 04:48:35 PM PDT 24
Finished Jul 03 04:48:37 PM PDT 24
Peak memory 191156 kb
Host smart-ae878082-0898-4ba8-a327-d79ec98d5d9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986561604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1986561604
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3702298551
Short name T51
Test name
Test status
Simulation time 539693133 ps
CPU time 2.41 seconds
Started Jul 03 04:48:37 PM PDT 24
Finished Jul 03 04:48:39 PM PDT 24
Peak memory 197000 kb
Host smart-a1ff9f0b-a4a4-4ffd-b64d-8f0ca367feec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702298551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3702298551
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.817033032
Short name T552
Test name
Test status
Simulation time 54206580 ps
CPU time 0.83 seconds
Started Jul 03 04:48:18 PM PDT 24
Finished Jul 03 04:48:20 PM PDT 24
Peak memory 193076 kb
Host smart-fd585b62-c71b-4b67-aae5-27ea9a63cf24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817033032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.817033032
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1750567881
Short name T456
Test name
Test status
Simulation time 59808807 ps
CPU time 1.4 seconds
Started Jul 03 04:48:27 PM PDT 24
Finished Jul 03 04:48:29 PM PDT 24
Peak memory 196972 kb
Host smart-cbcff5d9-9a4c-4940-bea0-0a8406e383d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750567881 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1750567881
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.321901187
Short name T515
Test name
Test status
Simulation time 15374258 ps
CPU time 0.55 seconds
Started Jul 03 04:48:20 PM PDT 24
Finished Jul 03 04:48:21 PM PDT 24
Peak memory 182064 kb
Host smart-6d9c2e7b-f885-46a1-889c-f3bcbfd0a65e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321901187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.321901187
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.256139286
Short name T494
Test name
Test status
Simulation time 15549823 ps
CPU time 0.55 seconds
Started Jul 03 04:48:29 PM PDT 24
Finished Jul 03 04:48:30 PM PDT 24
Peak memory 181596 kb
Host smart-00b195b3-9713-4e35-9e9a-79817c6d74b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256139286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.256139286
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1482525755
Short name T485
Test name
Test status
Simulation time 21228922 ps
CPU time 0.63 seconds
Started Jul 03 04:48:25 PM PDT 24
Finished Jul 03 04:48:26 PM PDT 24
Peak memory 191448 kb
Host smart-1e4c2c49-c348-4697-9750-271d711d97a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482525755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1482525755
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1897668458
Short name T578
Test name
Test status
Simulation time 43623710 ps
CPU time 1.05 seconds
Started Jul 03 04:48:30 PM PDT 24
Finished Jul 03 04:48:32 PM PDT 24
Peak memory 196856 kb
Host smart-ad08dd5f-cb98-42a1-a29e-69c643cff330
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897668458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1897668458
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2866910644
Short name T500
Test name
Test status
Simulation time 234413117 ps
CPU time 1.16 seconds
Started Jul 03 04:48:29 PM PDT 24
Finished Jul 03 04:48:31 PM PDT 24
Peak memory 193728 kb
Host smart-e5c2dbe5-2677-43ec-a411-8461af9c576f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866910644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2866910644
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3255792613
Short name T523
Test name
Test status
Simulation time 32594332 ps
CPU time 0.97 seconds
Started Jul 03 04:48:26 PM PDT 24
Finished Jul 03 04:48:27 PM PDT 24
Peak memory 196360 kb
Host smart-180e72e2-5604-4533-93d3-cc4c2fa75e1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255792613 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3255792613
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3394186000
Short name T519
Test name
Test status
Simulation time 111139669 ps
CPU time 0.57 seconds
Started Jul 03 04:48:22 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 182228 kb
Host smart-b50b992c-8fa6-48c9-b84e-f792bc28ab62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394186000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3394186000
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3042036484
Short name T468
Test name
Test status
Simulation time 13600592 ps
CPU time 0.56 seconds
Started Jul 03 04:48:23 PM PDT 24
Finished Jul 03 04:48:24 PM PDT 24
Peak memory 181556 kb
Host smart-6a5494c1-72b8-49e3-8200-c85ba7f0fc20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042036484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3042036484
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2366643591
Short name T78
Test name
Test status
Simulation time 70957565 ps
CPU time 0.88 seconds
Started Jul 03 04:48:26 PM PDT 24
Finished Jul 03 04:48:27 PM PDT 24
Peak memory 192236 kb
Host smart-8e56682f-7c35-45dc-9932-d759ec3811f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366643591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2366643591
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.166346972
Short name T496
Test name
Test status
Simulation time 57738531 ps
CPU time 1.71 seconds
Started Jul 03 04:48:25 PM PDT 24
Finished Jul 03 04:48:27 PM PDT 24
Peak memory 197016 kb
Host smart-30dc8432-8a8e-4863-8d23-d01da330aabe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166346972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.166346972
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.422043559
Short name T574
Test name
Test status
Simulation time 214111913 ps
CPU time 1.17 seconds
Started Jul 03 04:48:25 PM PDT 24
Finished Jul 03 04:48:26 PM PDT 24
Peak memory 194712 kb
Host smart-6a545c17-1004-4664-a763-90d92eaf0b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422043559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.422043559
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1945146593
Short name T529
Test name
Test status
Simulation time 24352320 ps
CPU time 1.17 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 197016 kb
Host smart-a68ab55d-91f6-4895-8700-7f24b5897da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945146593 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1945146593
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3432437973
Short name T93
Test name
Test status
Simulation time 71690320 ps
CPU time 0.6 seconds
Started Jul 03 04:48:20 PM PDT 24
Finished Jul 03 04:48:22 PM PDT 24
Peak memory 182236 kb
Host smart-a6622c66-beb9-4276-8319-0165f964ac74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432437973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3432437973
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3023895065
Short name T537
Test name
Test status
Simulation time 82777003 ps
CPU time 0.59 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:22 PM PDT 24
Peak memory 182116 kb
Host smart-479d817b-3fc1-4c07-88c9-13cd94ae0795
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023895065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3023895065
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1321196323
Short name T520
Test name
Test status
Simulation time 191112507 ps
CPU time 0.79 seconds
Started Jul 03 04:48:21 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 191184 kb
Host smart-8fc67b45-7449-40e0-9ffc-57bdf47cbc1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321196323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1321196323
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.4241908897
Short name T465
Test name
Test status
Simulation time 103713365 ps
CPU time 2.26 seconds
Started Jul 03 04:48:24 PM PDT 24
Finished Jul 03 04:48:27 PM PDT 24
Peak memory 197000 kb
Host smart-51a48b2e-4ebc-4794-9a13-d3a75b2a67fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241908897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.4241908897
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1402253617
Short name T571
Test name
Test status
Simulation time 72580602 ps
CPU time 0.81 seconds
Started Jul 03 04:48:22 PM PDT 24
Finished Jul 03 04:48:23 PM PDT 24
Peak memory 193300 kb
Host smart-c799484e-b905-49d2-8546-27c3bea15273
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402253617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1402253617
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2750107992
Short name T411
Test name
Test status
Simulation time 232312083191 ps
CPU time 292.73 seconds
Started Jul 03 05:05:34 PM PDT 24
Finished Jul 03 05:10:27 PM PDT 24
Peak memory 183092 kb
Host smart-2aec5371-d89a-44f8-81af-dc4881946952
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750107992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2750107992
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3896023490
Short name T52
Test name
Test status
Simulation time 34459418486 ps
CPU time 33.95 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:56 PM PDT 24
Peak memory 183100 kb
Host smart-0e3a1cb6-4169-482f-bc37-db26a5e193a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896023490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3896023490
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.2152783271
Short name T177
Test name
Test status
Simulation time 61564815797 ps
CPU time 97.38 seconds
Started Jul 03 05:05:28 PM PDT 24
Finished Jul 03 05:07:05 PM PDT 24
Peak memory 191308 kb
Host smart-93bd1aef-d13b-4945-8b8a-22fd8153aa60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152783271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2152783271
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1305750716
Short name T363
Test name
Test status
Simulation time 149182036 ps
CPU time 1.05 seconds
Started Jul 03 05:05:16 PM PDT 24
Finished Jul 03 05:05:21 PM PDT 24
Peak memory 192144 kb
Host smart-a7fa8f11-ebed-49b0-b671-46fd7bc40252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305750716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1305750716
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.4142221963
Short name T396
Test name
Test status
Simulation time 75065553 ps
CPU time 0.58 seconds
Started Jul 03 05:05:22 PM PDT 24
Finished Jul 03 05:05:24 PM PDT 24
Peak memory 182952 kb
Host smart-17a000f9-3f31-4f64-8335-4fd57a4fd35e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142221963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
4142221963
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1100223786
Short name T119
Test name
Test status
Simulation time 548793126834 ps
CPU time 282.35 seconds
Started Jul 03 05:05:46 PM PDT 24
Finished Jul 03 05:10:29 PM PDT 24
Peak memory 183004 kb
Host smart-4fa1f8e6-266d-443d-9654-28b284ae0b5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100223786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1100223786
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1542152849
Short name T364
Test name
Test status
Simulation time 39304553498 ps
CPU time 52.84 seconds
Started Jul 03 05:05:30 PM PDT 24
Finished Jul 03 05:06:23 PM PDT 24
Peak memory 183068 kb
Host smart-3848eb27-768c-4c3b-a824-350aebbf001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542152849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1542152849
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2944579924
Short name T233
Test name
Test status
Simulation time 61041490289 ps
CPU time 36.13 seconds
Started Jul 03 05:05:26 PM PDT 24
Finished Jul 03 05:06:03 PM PDT 24
Peak memory 194496 kb
Host smart-ec7fecf2-7a30-49f3-9234-caa669733796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944579924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2944579924
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.4154353514
Short name T19
Test name
Test status
Simulation time 399779296 ps
CPU time 0.82 seconds
Started Jul 03 05:05:32 PM PDT 24
Finished Jul 03 05:05:33 PM PDT 24
Peak memory 213372 kb
Host smart-5adcc880-1e34-41d4-8480-f855ba2af0bc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154353514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.4154353514
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2897015456
Short name T427
Test name
Test status
Simulation time 43490614906 ps
CPU time 35.04 seconds
Started Jul 03 05:05:22 PM PDT 24
Finished Jul 03 05:05:59 PM PDT 24
Peak memory 183124 kb
Host smart-de52f4d9-f691-4513-b0ca-d2af6fa227e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897015456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2897015456
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1204344670
Short name T232
Test name
Test status
Simulation time 286241572480 ps
CPU time 164.25 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:08:38 PM PDT 24
Peak memory 191260 kb
Host smart-a3875c24-eec6-4567-a035-5a7f51751a52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204344670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1204344670
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3474894276
Short name T188
Test name
Test status
Simulation time 102209035239 ps
CPU time 419.5 seconds
Started Jul 03 05:05:25 PM PDT 24
Finished Jul 03 05:12:25 PM PDT 24
Peak memory 191260 kb
Host smart-6771a585-743e-4842-9faa-7e215c998470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474894276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3474894276
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.376320777
Short name T34
Test name
Test status
Simulation time 472535102437 ps
CPU time 448.72 seconds
Started Jul 03 05:05:47 PM PDT 24
Finished Jul 03 05:13:17 PM PDT 24
Peak memory 191292 kb
Host smart-04033cb9-0004-496b-9784-d1a94368c461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376320777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
376320777
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.747711994
Short name T39
Test name
Test status
Simulation time 63535615996 ps
CPU time 491.48 seconds
Started Jul 03 05:05:21 PM PDT 24
Finished Jul 03 05:13:35 PM PDT 24
Peak memory 197820 kb
Host smart-81e3f7af-74b2-45eb-b04f-bae9b71f8615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747711994 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.747711994
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/102.rv_timer_random.1174674762
Short name T211
Test name
Test status
Simulation time 28584417011 ps
CPU time 51.07 seconds
Started Jul 03 05:06:15 PM PDT 24
Finished Jul 03 05:07:07 PM PDT 24
Peak memory 183092 kb
Host smart-c44865ce-7118-4b00-95f2-936c0c482b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174674762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1174674762
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3277271609
Short name T243
Test name
Test status
Simulation time 248327910362 ps
CPU time 296.51 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:11:05 PM PDT 24
Peak memory 191284 kb
Host smart-bafdab65-6d5a-49fd-aa0c-17d119167de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277271609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3277271609
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.525369574
Short name T71
Test name
Test status
Simulation time 66224314601 ps
CPU time 70.49 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:07:24 PM PDT 24
Peak memory 183028 kb
Host smart-c3f6205d-a429-4a83-a24c-2f15edf1744c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525369574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.525369574
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3201318174
Short name T265
Test name
Test status
Simulation time 176703742772 ps
CPU time 512.98 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:14:43 PM PDT 24
Peak memory 191308 kb
Host smart-e912df1f-f2c1-4afd-b2f5-fb27425b807e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201318174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3201318174
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2292416938
Short name T435
Test name
Test status
Simulation time 130164641500 ps
CPU time 202.85 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:09:02 PM PDT 24
Peak memory 183068 kb
Host smart-e292951d-8831-4d2f-af31-4e5675739a1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292416938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2292416938
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.981104029
Short name T380
Test name
Test status
Simulation time 233643670228 ps
CPU time 86.68 seconds
Started Jul 03 05:05:37 PM PDT 24
Finished Jul 03 05:07:05 PM PDT 24
Peak memory 183080 kb
Host smart-a68bcfc6-0f5f-4a2f-a090-416ea30e124d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981104029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.981104029
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1574249791
Short name T293
Test name
Test status
Simulation time 544316289775 ps
CPU time 324.18 seconds
Started Jul 03 05:05:35 PM PDT 24
Finished Jul 03 05:10:59 PM PDT 24
Peak memory 191276 kb
Host smart-e4e16663-84fe-4797-9fef-b2c3fab6f740
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574249791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1574249791
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3924875925
Short name T241
Test name
Test status
Simulation time 113016048117 ps
CPU time 61.93 seconds
Started Jul 03 05:05:41 PM PDT 24
Finished Jul 03 05:06:43 PM PDT 24
Peak memory 191292 kb
Host smart-45dde1c2-7dea-48f7-aba2-3eb767c187d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924875925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3924875925
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.3072710376
Short name T388
Test name
Test status
Simulation time 1726882065930 ps
CPU time 338.21 seconds
Started Jul 03 05:05:50 PM PDT 24
Finished Jul 03 05:11:28 PM PDT 24
Peak memory 191332 kb
Host smart-0a7a93c8-0da6-412f-aec7-c5dfce3ef75b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072710376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.3072710376
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/112.rv_timer_random.1910355975
Short name T434
Test name
Test status
Simulation time 11346473192 ps
CPU time 17.47 seconds
Started Jul 03 05:06:08 PM PDT 24
Finished Jul 03 05:06:26 PM PDT 24
Peak memory 183108 kb
Host smart-191865fe-7d0d-44b7-bc37-7aa9347f9c11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910355975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1910355975
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3740545602
Short name T21
Test name
Test status
Simulation time 381911568488 ps
CPU time 276.82 seconds
Started Jul 03 05:06:08 PM PDT 24
Finished Jul 03 05:10:46 PM PDT 24
Peak memory 191324 kb
Host smart-23eca668-9038-4d36-bf34-cd54663abf89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740545602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3740545602
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.60068683
Short name T122
Test name
Test status
Simulation time 31022854931 ps
CPU time 60.14 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:07:09 PM PDT 24
Peak memory 183136 kb
Host smart-aa6f0b25-e9f6-4192-a31b-38ba9c008a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60068683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.60068683
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1314301383
Short name T423
Test name
Test status
Simulation time 1878786550190 ps
CPU time 993.58 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:22:12 PM PDT 24
Peak memory 182968 kb
Host smart-078e1318-f832-483e-922e-5f6ca073cb90
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314301383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1314301383
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.452150569
Short name T370
Test name
Test status
Simulation time 307689026494 ps
CPU time 245.61 seconds
Started Jul 03 05:05:43 PM PDT 24
Finished Jul 03 05:09:49 PM PDT 24
Peak memory 183072 kb
Host smart-7186ccdf-af65-4528-815a-6d1bf92c8b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452150569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.452150569
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3612431164
Short name T393
Test name
Test status
Simulation time 94593821979 ps
CPU time 44.22 seconds
Started Jul 03 05:05:42 PM PDT 24
Finished Jul 03 05:06:27 PM PDT 24
Peak memory 183072 kb
Host smart-49503830-7013-4d22-a3c9-b8909b9b082d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612431164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3612431164
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3086477472
Short name T448
Test name
Test status
Simulation time 298162251576 ps
CPU time 167.7 seconds
Started Jul 03 05:05:32 PM PDT 24
Finished Jul 03 05:08:20 PM PDT 24
Peak memory 191288 kb
Host smart-6309b775-59d7-42b4-8344-e659b84227de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086477472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3086477472
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.403284095
Short name T422
Test name
Test status
Simulation time 82708258927 ps
CPU time 539.96 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:15:08 PM PDT 24
Peak memory 183092 kb
Host smart-3acbeb0e-672f-4cca-8cf0-e42a435841ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403284095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.403284095
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2345364254
Short name T420
Test name
Test status
Simulation time 671960809081 ps
CPU time 170.8 seconds
Started Jul 03 05:06:14 PM PDT 24
Finished Jul 03 05:09:06 PM PDT 24
Peak memory 191280 kb
Host smart-5214376e-5293-4cad-bf19-9cb9187a3905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345364254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2345364254
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3097591192
Short name T60
Test name
Test status
Simulation time 285324641908 ps
CPU time 410.36 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:13:04 PM PDT 24
Peak memory 191244 kb
Host smart-ddf3d85a-be31-4948-9aa7-b0a1307518a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097591192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3097591192
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1424365369
Short name T236
Test name
Test status
Simulation time 7604569845 ps
CPU time 14.57 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:06:26 PM PDT 24
Peak memory 183136 kb
Host smart-40cfa6a0-f1cc-4cdb-9f7e-501b9316299a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424365369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1424365369
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1193967223
Short name T313
Test name
Test status
Simulation time 220186483993 ps
CPU time 161.62 seconds
Started Jul 03 05:06:17 PM PDT 24
Finished Jul 03 05:08:59 PM PDT 24
Peak memory 183080 kb
Host smart-df26fffd-9637-4a55-989a-d6240128671a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193967223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1193967223
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3887798171
Short name T280
Test name
Test status
Simulation time 45605479006 ps
CPU time 21.57 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:06:36 PM PDT 24
Peak memory 183032 kb
Host smart-d6280c7b-446b-4d4c-9353-915aff5cf00e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887798171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3887798171
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1810349068
Short name T111
Test name
Test status
Simulation time 168299895666 ps
CPU time 587.78 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:16:00 PM PDT 24
Peak memory 191308 kb
Host smart-d2f9f398-08c6-4525-ac3b-7fab7569301a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810349068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1810349068
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2802105180
Short name T157
Test name
Test status
Simulation time 33055462449 ps
CPU time 28.83 seconds
Started Jul 03 05:05:42 PM PDT 24
Finished Jul 03 05:06:12 PM PDT 24
Peak memory 182480 kb
Host smart-ed1d2b37-2ccd-47b7-814f-06e9e8575162
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802105180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2802105180
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3143971440
Short name T360
Test name
Test status
Simulation time 18874864888 ps
CPU time 14.46 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:05:53 PM PDT 24
Peak memory 183120 kb
Host smart-418c1b4d-c283-456a-8e2c-a31cba3933fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143971440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3143971440
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.21806747
Short name T405
Test name
Test status
Simulation time 337134043 ps
CPU time 0.8 seconds
Started Jul 03 05:05:24 PM PDT 24
Finished Jul 03 05:05:25 PM PDT 24
Peak memory 182932 kb
Host smart-4d889ab4-ee33-411f-bc59-09b39d8431cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21806747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.21806747
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.3368507788
Short name T327
Test name
Test status
Simulation time 74647068397 ps
CPU time 110.21 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:08:04 PM PDT 24
Peak memory 193592 kb
Host smart-cb08476f-eef3-4b56-9454-294cc905aa52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368507788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3368507788
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.1001830414
Short name T237
Test name
Test status
Simulation time 15177823077 ps
CPU time 24.4 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:06:38 PM PDT 24
Peak memory 183124 kb
Host smart-85e653bf-98b5-481e-a132-5a18f1551ee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001830414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.1001830414
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.178970897
Short name T314
Test name
Test status
Simulation time 18261822520 ps
CPU time 170.01 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:08:57 PM PDT 24
Peak memory 183008 kb
Host smart-7c320fbb-60f3-4ba5-a2d2-a03d565cd3f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178970897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.178970897
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1467626398
Short name T180
Test name
Test status
Simulation time 31037592625 ps
CPU time 37.02 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:06:43 PM PDT 24
Peak memory 193752 kb
Host smart-04198a5a-3c52-47a1-90a8-58716930a4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467626398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1467626398
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.4124285679
Short name T344
Test name
Test status
Simulation time 93054043219 ps
CPU time 501.48 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:14:36 PM PDT 24
Peak memory 191316 kb
Host smart-10da89d0-478b-4f7b-aa0c-ef0d18cdb360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124285679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.4124285679
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2209296689
Short name T123
Test name
Test status
Simulation time 17769928993 ps
CPU time 41.61 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:06:54 PM PDT 24
Peak memory 183088 kb
Host smart-fd735903-921b-40f7-8dcd-e25430527a9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209296689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2209296689
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.1001656300
Short name T5
Test name
Test status
Simulation time 562713802924 ps
CPU time 201.37 seconds
Started Jul 03 05:06:14 PM PDT 24
Finished Jul 03 05:09:36 PM PDT 24
Peak memory 191284 kb
Host smart-16056b5e-4442-4282-bc66-e190c4908603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001656300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.1001656300
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.550590747
Short name T156
Test name
Test status
Simulation time 345927706890 ps
CPU time 592.04 seconds
Started Jul 03 05:05:39 PM PDT 24
Finished Jul 03 05:15:32 PM PDT 24
Peak memory 182960 kb
Host smart-6df07d41-f487-4c0e-a01d-57fe6c4958a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550590747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.rv_timer_cfg_update_on_fly.550590747
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3858630584
Short name T398
Test name
Test status
Simulation time 406787795951 ps
CPU time 131.54 seconds
Started Jul 03 05:05:35 PM PDT 24
Finished Jul 03 05:07:47 PM PDT 24
Peak memory 183116 kb
Host smart-d11d8097-8892-4247-9a2c-f650f6d9c8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858630584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3858630584
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1252042022
Short name T400
Test name
Test status
Simulation time 145856446 ps
CPU time 0.72 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:05:40 PM PDT 24
Peak memory 182956 kb
Host smart-496eaa7e-d1c4-40a3-82e7-4614f0a82879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252042022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1252042022
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.2306035487
Short name T317
Test name
Test status
Simulation time 116552916232 ps
CPU time 70.53 seconds
Started Jul 03 05:06:15 PM PDT 24
Finished Jul 03 05:07:26 PM PDT 24
Peak memory 183116 kb
Host smart-66eabd83-0c3c-4a05-9d57-725c0390ddd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306035487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.2306035487
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.207456433
Short name T151
Test name
Test status
Simulation time 105119855843 ps
CPU time 192.44 seconds
Started Jul 03 05:06:19 PM PDT 24
Finished Jul 03 05:09:32 PM PDT 24
Peak memory 191252 kb
Host smart-42b006ad-33f8-4d52-97d5-b99b3731acc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207456433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.207456433
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2124343758
Short name T279
Test name
Test status
Simulation time 72158955796 ps
CPU time 35.95 seconds
Started Jul 03 05:06:14 PM PDT 24
Finished Jul 03 05:06:51 PM PDT 24
Peak memory 191308 kb
Host smart-9ac81249-3127-4c51-a72b-b27baaa43522
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124343758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2124343758
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.18767405
Short name T98
Test name
Test status
Simulation time 60459228137 ps
CPU time 86.73 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:07:37 PM PDT 24
Peak memory 191312 kb
Host smart-84fc43cc-1c51-4f71-9a5d-56c3bbef2431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18767405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.18767405
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1597933220
Short name T173
Test name
Test status
Simulation time 71907360195 ps
CPU time 63.81 seconds
Started Jul 03 05:06:20 PM PDT 24
Finished Jul 03 05:07:24 PM PDT 24
Peak memory 183108 kb
Host smart-039640f3-07f8-4ae6-8999-51fc9d0a92c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597933220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1597933220
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2850647049
Short name T311
Test name
Test status
Simulation time 285259100153 ps
CPU time 440.74 seconds
Started Jul 03 05:05:37 PM PDT 24
Finished Jul 03 05:12:58 PM PDT 24
Peak memory 183072 kb
Host smart-26d77b58-ab55-492d-8718-597d1b3b2e53
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850647049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2850647049
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2210964386
Short name T357
Test name
Test status
Simulation time 78890516031 ps
CPU time 122.51 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:07:47 PM PDT 24
Peak memory 183052 kb
Host smart-17799f8f-ffae-448f-aa15-74354d8805c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210964386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2210964386
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2480917991
Short name T154
Test name
Test status
Simulation time 176110488873 ps
CPU time 1795.58 seconds
Started Jul 03 05:05:36 PM PDT 24
Finished Jul 03 05:35:32 PM PDT 24
Peak memory 194080 kb
Host smart-227715b6-2e14-449d-bd7e-9e29d1889208
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480917991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2480917991
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3077555519
Short name T253
Test name
Test status
Simulation time 85844801379 ps
CPU time 69.47 seconds
Started Jul 03 05:05:45 PM PDT 24
Finished Jul 03 05:06:55 PM PDT 24
Peak memory 191312 kb
Host smart-3891bb39-8d11-4a8b-a451-829a8b6d9c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077555519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3077555519
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.2068363206
Short name T277
Test name
Test status
Simulation time 49245745081 ps
CPU time 109.59 seconds
Started Jul 03 05:06:20 PM PDT 24
Finished Jul 03 05:08:10 PM PDT 24
Peak memory 194816 kb
Host smart-b3a85144-278c-47af-9c19-5e36cbb14e55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068363206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.2068363206
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2464221938
Short name T269
Test name
Test status
Simulation time 2180431274746 ps
CPU time 395.6 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:12:48 PM PDT 24
Peak memory 194588 kb
Host smart-71a64f25-30a8-496c-9b40-642b2179ac30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464221938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2464221938
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2807110
Short name T342
Test name
Test status
Simulation time 299924083105 ps
CPU time 205.93 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:09:40 PM PDT 24
Peak memory 191256 kb
Host smart-99fdafe4-2fa7-4b9c-803a-6cdc9ab02579
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2807110
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2756006236
Short name T185
Test name
Test status
Simulation time 229720201337 ps
CPU time 1783.61 seconds
Started Jul 03 05:06:18 PM PDT 24
Finished Jul 03 05:36:02 PM PDT 24
Peak memory 191292 kb
Host smart-066b173f-5376-46b6-8bcb-486ce40830ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756006236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2756006236
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2958161238
Short name T143
Test name
Test status
Simulation time 293230473895 ps
CPU time 432.72 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:13:30 PM PDT 24
Peak memory 191300 kb
Host smart-ad90fe4f-af30-4268-a114-6b19a136c2e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958161238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2958161238
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1249008505
Short name T447
Test name
Test status
Simulation time 197058841401 ps
CPU time 83.34 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:07:37 PM PDT 24
Peak memory 191340 kb
Host smart-a3433d2e-c6f9-4500-9042-f3bb4acdb2f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249008505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1249008505
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.7737887
Short name T312
Test name
Test status
Simulation time 91503015796 ps
CPU time 178.87 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:09:11 PM PDT 24
Peak memory 191304 kb
Host smart-b13d741e-e266-4276-9f12-8d5b0f0db17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7737887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.7737887
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2952634906
Short name T189
Test name
Test status
Simulation time 164131689783 ps
CPU time 76.19 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:07:30 PM PDT 24
Peak memory 194784 kb
Host smart-0352c417-42bb-4579-8b29-7c6c19fc0a3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952634906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2952634906
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2265229771
Short name T7
Test name
Test status
Simulation time 58010273356 ps
CPU time 87.38 seconds
Started Jul 03 05:05:45 PM PDT 24
Finished Jul 03 05:07:13 PM PDT 24
Peak memory 183116 kb
Host smart-541e6db9-a6ac-4757-807e-92bbd9b62389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265229771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2265229771
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3548888090
Short name T346
Test name
Test status
Simulation time 465996233278 ps
CPU time 760.12 seconds
Started Jul 03 05:05:41 PM PDT 24
Finished Jul 03 05:18:22 PM PDT 24
Peak memory 191300 kb
Host smart-0b1157cd-35a5-40e6-868c-137459a17fba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548888090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3548888090
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3211885981
Short name T308
Test name
Test status
Simulation time 6829517806 ps
CPU time 38.74 seconds
Started Jul 03 05:05:31 PM PDT 24
Finished Jul 03 05:06:10 PM PDT 24
Peak memory 191280 kb
Host smart-27b426c5-a067-4fbf-a34f-7e4c6897c5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211885981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3211885981
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.346668261
Short name T38
Test name
Test status
Simulation time 65405751104 ps
CPU time 128.89 seconds
Started Jul 03 05:05:36 PM PDT 24
Finished Jul 03 05:07:45 PM PDT 24
Peak memory 205928 kb
Host smart-908319fa-0e2a-42e2-b90b-8a5d1ee7c067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346668261 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.346668261
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1505532511
Short name T290
Test name
Test status
Simulation time 273300894504 ps
CPU time 598.74 seconds
Started Jul 03 05:06:19 PM PDT 24
Finished Jul 03 05:16:18 PM PDT 24
Peak memory 191172 kb
Host smart-6ff62be2-a0ef-44fa-81fe-8a9999618f16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505532511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1505532511
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1391775036
Short name T45
Test name
Test status
Simulation time 88548046208 ps
CPU time 71.05 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:07:27 PM PDT 24
Peak memory 183132 kb
Host smart-176da596-645c-48bf-9188-c1277d2d6045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391775036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1391775036
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.4231757186
Short name T184
Test name
Test status
Simulation time 108072582912 ps
CPU time 339.44 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:11:56 PM PDT 24
Peak memory 191288 kb
Host smart-6feaeb0d-3b7b-4370-84a0-7303683419f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231757186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4231757186
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.558447981
Short name T193
Test name
Test status
Simulation time 1094390671439 ps
CPU time 204.43 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:09:39 PM PDT 24
Peak memory 191324 kb
Host smart-0ffee7bb-c175-47a2-ba45-6d91bbae6327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558447981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.558447981
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4135363500
Short name T334
Test name
Test status
Simulation time 427248434192 ps
CPU time 769.31 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:19:04 PM PDT 24
Peak memory 191300 kb
Host smart-caf773f4-ecd5-4876-97b3-5f40d34e8938
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135363500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4135363500
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3215697457
Short name T222
Test name
Test status
Simulation time 369935789285 ps
CPU time 328.22 seconds
Started Jul 03 05:05:42 PM PDT 24
Finished Jul 03 05:11:11 PM PDT 24
Peak memory 182956 kb
Host smart-8508bc86-b09a-4c83-9766-5fcc37e77a6d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215697457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3215697457
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.151619879
Short name T358
Test name
Test status
Simulation time 398322817684 ps
CPU time 123.16 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:07:42 PM PDT 24
Peak memory 183088 kb
Host smart-b40a3eb9-f792-45ef-bfb0-fbca0eb7d93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151619879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.151619879
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2486132692
Short name T37
Test name
Test status
Simulation time 54446514236 ps
CPU time 104.82 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:07:24 PM PDT 24
Peak memory 197796 kb
Host smart-8c7f22fd-3cf2-499a-a788-c5a7b263a548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486132692 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2486132692
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2788446497
Short name T186
Test name
Test status
Simulation time 53406533172 ps
CPU time 90.44 seconds
Started Jul 03 05:06:18 PM PDT 24
Finished Jul 03 05:07:49 PM PDT 24
Peak memory 191332 kb
Host smart-9e0e445a-5049-4b80-a358-3096cfbe9dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788446497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2788446497
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.4028193268
Short name T273
Test name
Test status
Simulation time 477263718436 ps
CPU time 638.58 seconds
Started Jul 03 05:06:15 PM PDT 24
Finished Jul 03 05:16:55 PM PDT 24
Peak memory 191296 kb
Host smart-3cc7259b-bbb5-4216-baa9-ae819bff9bea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028193268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4028193268
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2483194594
Short name T424
Test name
Test status
Simulation time 95826431735 ps
CPU time 159.38 seconds
Started Jul 03 05:06:15 PM PDT 24
Finished Jul 03 05:08:56 PM PDT 24
Peak memory 191312 kb
Host smart-c7580846-049b-445b-b111-dd1691b28a4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483194594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2483194594
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1042034833
Short name T289
Test name
Test status
Simulation time 144893750049 ps
CPU time 250.86 seconds
Started Jul 03 05:06:14 PM PDT 24
Finished Jul 03 05:10:26 PM PDT 24
Peak memory 191340 kb
Host smart-7ef9cb89-d78b-460b-ab60-bbb29d35e3da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042034833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1042034833
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1145145332
Short name T55
Test name
Test status
Simulation time 215465029627 ps
CPU time 416.81 seconds
Started Jul 03 05:06:17 PM PDT 24
Finished Jul 03 05:13:14 PM PDT 24
Peak memory 191236 kb
Host smart-b33dd60e-33dc-46ca-b742-73bfb6d9a438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145145332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1145145332
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1965136081
Short name T133
Test name
Test status
Simulation time 19950372250 ps
CPU time 288.38 seconds
Started Jul 03 05:06:17 PM PDT 24
Finished Jul 03 05:11:06 PM PDT 24
Peak memory 183116 kb
Host smart-450c646a-461b-405f-9a29-7c3f0c2891f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965136081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1965136081
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2547571
Short name T271
Test name
Test status
Simulation time 51731548209 ps
CPU time 82.36 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:07:40 PM PDT 24
Peak memory 191288 kb
Host smart-e7ff079d-c237-47eb-9b04-311d5b51783c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2547571
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3139414377
Short name T438
Test name
Test status
Simulation time 116052756357 ps
CPU time 162.75 seconds
Started Jul 03 05:06:17 PM PDT 24
Finished Jul 03 05:09:01 PM PDT 24
Peak memory 193908 kb
Host smart-50207124-cb14-47b9-9e9a-50cf7b8fd320
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139414377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3139414377
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.1141491687
Short name T174
Test name
Test status
Simulation time 118666564945 ps
CPU time 283.61 seconds
Started Jul 03 05:05:39 PM PDT 24
Finished Jul 03 05:10:23 PM PDT 24
Peak memory 191292 kb
Host smart-3fd38f66-0ce2-4924-9afe-8c967206b782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141491687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1141491687
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2355550597
Short name T266
Test name
Test status
Simulation time 32461737392 ps
CPU time 6.33 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:05:51 PM PDT 24
Peak memory 191316 kb
Host smart-8417e7c5-0271-4432-b9df-d99167374f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355550597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2355550597
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1731634218
Short name T352
Test name
Test status
Simulation time 45648804266 ps
CPU time 61.13 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:06:40 PM PDT 24
Peak memory 183124 kb
Host smart-1cccafad-478a-4dab-b338-fb99253eadef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731634218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1731634218
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.3658737141
Short name T330
Test name
Test status
Simulation time 21634360632 ps
CPU time 31.51 seconds
Started Jul 03 05:06:15 PM PDT 24
Finished Jul 03 05:06:47 PM PDT 24
Peak memory 182992 kb
Host smart-5587de56-2b20-4720-9502-b370c4128d35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658737141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3658737141
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3851105075
Short name T131
Test name
Test status
Simulation time 206108544627 ps
CPU time 75.62 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:07:33 PM PDT 24
Peak memory 191268 kb
Host smart-1f619629-1cff-4122-92e9-de4efee42346
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851105075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3851105075
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.698274210
Short name T267
Test name
Test status
Simulation time 301563414674 ps
CPU time 562.06 seconds
Started Jul 03 05:06:19 PM PDT 24
Finished Jul 03 05:15:42 PM PDT 24
Peak memory 194060 kb
Host smart-481836d9-7d2c-4a6e-9da0-5c20bcc26397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698274210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.698274210
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3759922628
Short name T320
Test name
Test status
Simulation time 148519343005 ps
CPU time 89.01 seconds
Started Jul 03 05:06:21 PM PDT 24
Finished Jul 03 05:07:50 PM PDT 24
Peak memory 183088 kb
Host smart-bc4561a3-f0a0-400f-85e5-643649ab1c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759922628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3759922628
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1785321684
Short name T212
Test name
Test status
Simulation time 55744360570 ps
CPU time 93.26 seconds
Started Jul 03 05:06:15 PM PDT 24
Finished Jul 03 05:07:49 PM PDT 24
Peak memory 191300 kb
Host smart-f29a9eef-f587-449a-bec7-c3d5c6d38108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785321684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1785321684
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2025207043
Short name T304
Test name
Test status
Simulation time 383291267 ps
CPU time 1.1 seconds
Started Jul 03 05:05:40 PM PDT 24
Finished Jul 03 05:05:41 PM PDT 24
Peak memory 182880 kb
Host smart-40e741d4-f198-4fb3-b9de-b2bfd040b67c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025207043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2025207043
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.743597214
Short name T406
Test name
Test status
Simulation time 93141396420 ps
CPU time 135.6 seconds
Started Jul 03 05:05:37 PM PDT 24
Finished Jul 03 05:07:53 PM PDT 24
Peak memory 183092 kb
Host smart-4db0d7ee-ca17-48ac-9e77-e8b9dcbf1a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743597214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.743597214
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3711791662
Short name T318
Test name
Test status
Simulation time 84273794609 ps
CPU time 81.83 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:07:01 PM PDT 24
Peak memory 191260 kb
Host smart-69f5d053-67d4-4545-970c-e02c7cc372a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711791662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3711791662
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.4206862611
Short name T242
Test name
Test status
Simulation time 319262899508 ps
CPU time 1334.36 seconds
Started Jul 03 05:05:45 PM PDT 24
Finished Jul 03 05:28:00 PM PDT 24
Peak memory 191320 kb
Host smart-c75d3560-b529-439a-849e-438f4dcb34c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206862611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.4206862611
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1428917766
Short name T97
Test name
Test status
Simulation time 97135267708 ps
CPU time 526.82 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:15:04 PM PDT 24
Peak memory 191300 kb
Host smart-2db08ef4-fae3-4eba-a7a9-d274fd2838b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428917766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1428917766
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.103717116
Short name T171
Test name
Test status
Simulation time 107031117610 ps
CPU time 164.4 seconds
Started Jul 03 05:06:22 PM PDT 24
Finished Jul 03 05:09:06 PM PDT 24
Peak memory 191308 kb
Host smart-da908e70-c7ec-431d-a0a5-25ab23e776e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103717116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.103717116
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3348379971
Short name T316
Test name
Test status
Simulation time 103613085060 ps
CPU time 102.24 seconds
Started Jul 03 05:06:21 PM PDT 24
Finished Jul 03 05:08:04 PM PDT 24
Peak memory 191316 kb
Host smart-20ef3055-4a11-4bb8-baf4-d6fe688c8eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348379971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3348379971
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.857038428
Short name T138
Test name
Test status
Simulation time 256780326993 ps
CPU time 274.94 seconds
Started Jul 03 05:06:25 PM PDT 24
Finished Jul 03 05:11:00 PM PDT 24
Peak memory 191276 kb
Host smart-19317226-a001-4454-bb9b-fb899db87f1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857038428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.857038428
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2455034048
Short name T27
Test name
Test status
Simulation time 46284392408 ps
CPU time 66.59 seconds
Started Jul 03 05:06:21 PM PDT 24
Finished Jul 03 05:07:28 PM PDT 24
Peak memory 191244 kb
Host smart-528d79e3-0271-4a80-8ce9-f3f9af3f90c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455034048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2455034048
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.161038835
Short name T148
Test name
Test status
Simulation time 92350903563 ps
CPU time 1224.28 seconds
Started Jul 03 05:06:22 PM PDT 24
Finished Jul 03 05:26:47 PM PDT 24
Peak memory 191308 kb
Host smart-498093a0-2e3c-4ff7-836f-8ddd14ee7eb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161038835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.161038835
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.278841520
Short name T106
Test name
Test status
Simulation time 1690984955891 ps
CPU time 770.59 seconds
Started Jul 03 05:06:18 PM PDT 24
Finished Jul 03 05:19:10 PM PDT 24
Peak memory 191308 kb
Host smart-a81a0ea7-7844-4ef2-9d3f-764f655a3125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278841520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.278841520
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3498130288
Short name T283
Test name
Test status
Simulation time 1324530551567 ps
CPU time 632.23 seconds
Started Jul 03 05:05:41 PM PDT 24
Finished Jul 03 05:16:13 PM PDT 24
Peak memory 183040 kb
Host smart-bf32f4fa-4ff9-484d-94c6-d15dc2cfb4a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498130288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3498130288
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.73241084
Short name T442
Test name
Test status
Simulation time 42883542436 ps
CPU time 69.46 seconds
Started Jul 03 05:05:35 PM PDT 24
Finished Jul 03 05:06:45 PM PDT 24
Peak memory 183104 kb
Host smart-d3c1926c-ab84-4eb8-a2b6-7675f358018f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73241084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.73241084
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1167346223
Short name T322
Test name
Test status
Simulation time 332624006447 ps
CPU time 282.26 seconds
Started Jul 03 05:05:22 PM PDT 24
Finished Jul 03 05:10:06 PM PDT 24
Peak memory 191308 kb
Host smart-11b2e4f1-9fc4-42b3-8898-b55ab3d09196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167346223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1167346223
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3393139856
Short name T152
Test name
Test status
Simulation time 136618294563 ps
CPU time 328.63 seconds
Started Jul 03 05:05:20 PM PDT 24
Finished Jul 03 05:10:52 PM PDT 24
Peak memory 191288 kb
Host smart-d3ccbc4a-2e2f-488d-a9e2-b69e25b8d675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393139856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3393139856
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1820685351
Short name T17
Test name
Test status
Simulation time 89727045 ps
CPU time 0.84 seconds
Started Jul 03 05:05:20 PM PDT 24
Finished Jul 03 05:05:23 PM PDT 24
Peak memory 213372 kb
Host smart-3c30220d-41dc-4d85-8e78-9df2b21734dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820685351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1820685351
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1450314349
Short name T369
Test name
Test status
Simulation time 566858282581 ps
CPU time 214.91 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:08:56 PM PDT 24
Peak memory 183108 kb
Host smart-17967544-5791-44c0-b3ca-635bb614923e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450314349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1450314349
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2801964291
Short name T332
Test name
Test status
Simulation time 117074245605 ps
CPU time 148.9 seconds
Started Jul 03 05:05:47 PM PDT 24
Finished Jul 03 05:08:17 PM PDT 24
Peak memory 183068 kb
Host smart-ce251c5b-7d45-4520-942b-eacc25eb8621
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801964291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2801964291
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4009314085
Short name T443
Test name
Test status
Simulation time 71394190754 ps
CPU time 110.15 seconds
Started Jul 03 05:05:43 PM PDT 24
Finished Jul 03 05:07:34 PM PDT 24
Peak memory 183084 kb
Host smart-85946a76-2d1c-4a6c-8031-9ce24770e1a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009314085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4009314085
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.1608173671
Short name T128
Test name
Test status
Simulation time 155887956721 ps
CPU time 142.52 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:08:01 PM PDT 24
Peak memory 183068 kb
Host smart-512eaa9c-fd4a-4a3d-9862-6dc92511089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608173671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.1608173671
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1589409403
Short name T67
Test name
Test status
Simulation time 643707077889 ps
CPU time 770.82 seconds
Started Jul 03 05:05:36 PM PDT 24
Finished Jul 03 05:18:27 PM PDT 24
Peak memory 191328 kb
Host smart-9175ba12-8dc2-4c3b-a1ab-ad30695b2385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589409403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1589409403
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1290189002
Short name T359
Test name
Test status
Simulation time 144674490893 ps
CPU time 192.87 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:08:57 PM PDT 24
Peak memory 183124 kb
Host smart-3a14614c-3278-4382-b9d3-dc64377c709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290189002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1290189002
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.577737285
Short name T419
Test name
Test status
Simulation time 455564804 ps
CPU time 1.76 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:05:41 PM PDT 24
Peak memory 191264 kb
Host smart-6a6937da-5327-42d5-a424-c878cf676602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577737285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.577737285
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.2325646866
Short name T375
Test name
Test status
Simulation time 285424526307 ps
CPU time 416.97 seconds
Started Jul 03 05:05:42 PM PDT 24
Finished Jul 03 05:12:40 PM PDT 24
Peak memory 191284 kb
Host smart-78b72d49-3ac4-4414-b364-cdc6edcae0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325646866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.2325646866
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4061337731
Short name T341
Test name
Test status
Simulation time 1544128455366 ps
CPU time 490.15 seconds
Started Jul 03 05:05:32 PM PDT 24
Finished Jul 03 05:13:43 PM PDT 24
Peak memory 182952 kb
Host smart-98c86d25-9ed4-46d6-bed8-597701e379d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061337731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4061337731
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3546187919
Short name T409
Test name
Test status
Simulation time 115901396864 ps
CPU time 141.65 seconds
Started Jul 03 05:05:40 PM PDT 24
Finished Jul 03 05:08:02 PM PDT 24
Peak memory 183036 kb
Host smart-ad859ce5-3807-436a-a24b-1414d9546151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546187919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3546187919
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1195168244
Short name T22
Test name
Test status
Simulation time 35887132623 ps
CPU time 28.65 seconds
Started Jul 03 05:05:39 PM PDT 24
Finished Jul 03 05:06:08 PM PDT 24
Peak memory 183100 kb
Host smart-29800e39-ca2c-4244-a132-203057379b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195168244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1195168244
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.4211107661
Short name T367
Test name
Test status
Simulation time 402030851747 ps
CPU time 155.58 seconds
Started Jul 03 05:05:51 PM PDT 24
Finished Jul 03 05:08:27 PM PDT 24
Peak memory 183060 kb
Host smart-3ccf6516-350b-43ad-99ad-9a51e9193603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211107661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.4211107661
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3257942839
Short name T331
Test name
Test status
Simulation time 1067898527017 ps
CPU time 707.62 seconds
Started Jul 03 05:05:48 PM PDT 24
Finished Jul 03 05:17:36 PM PDT 24
Peak memory 191292 kb
Host smart-fc884307-2850-4362-9f81-62bf31befa40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257942839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3257942839
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3729777567
Short name T226
Test name
Test status
Simulation time 45539229875 ps
CPU time 23.61 seconds
Started Jul 03 05:05:52 PM PDT 24
Finished Jul 03 05:06:16 PM PDT 24
Peak memory 183096 kb
Host smart-dc0edcc0-e5b6-44c5-a4a3-69c2286ce0e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729777567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3729777567
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2412930846
Short name T407
Test name
Test status
Simulation time 382897775998 ps
CPU time 135.59 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 183060 kb
Host smart-b9032c66-815b-49f2-9af7-62d068f8ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412930846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2412930846
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1922153853
Short name T439
Test name
Test status
Simulation time 58496484354 ps
CPU time 83.85 seconds
Started Jul 03 05:05:50 PM PDT 24
Finished Jul 03 05:07:15 PM PDT 24
Peak memory 191216 kb
Host smart-fbf09548-0d1e-42a1-b8fb-fc5ed7572c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922153853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1922153853
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3351386440
Short name T371
Test name
Test status
Simulation time 1027006170 ps
CPU time 1.25 seconds
Started Jul 03 05:05:50 PM PDT 24
Finished Jul 03 05:05:52 PM PDT 24
Peak memory 183048 kb
Host smart-99ffe65e-5490-466b-b548-3a1e32804f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351386440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3351386440
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1958923298
Short name T412
Test name
Test status
Simulation time 98277328621 ps
CPU time 132.52 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:07:51 PM PDT 24
Peak memory 191304 kb
Host smart-cd5434c3-32ac-4196-b984-9028d46e823f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958923298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1958923298
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3989815641
Short name T428
Test name
Test status
Simulation time 102437580442 ps
CPU time 88.8 seconds
Started Jul 03 05:05:36 PM PDT 24
Finished Jul 03 05:07:05 PM PDT 24
Peak memory 183044 kb
Host smart-63ae6120-47c7-42e8-af34-165302427434
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989815641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3989815641
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3559221008
Short name T394
Test name
Test status
Simulation time 471272559714 ps
CPU time 223.49 seconds
Started Jul 03 05:05:35 PM PDT 24
Finished Jul 03 05:09:24 PM PDT 24
Peak memory 183084 kb
Host smart-508f6974-8cf6-4e61-89f4-f4a3620f1fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559221008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3559221008
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3516076709
Short name T44
Test name
Test status
Simulation time 62787146706 ps
CPU time 78.67 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:06:57 PM PDT 24
Peak memory 193600 kb
Host smart-ca2f0728-924b-4bdc-98da-301c9dab5650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516076709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3516076709
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1154971133
Short name T72
Test name
Test status
Simulation time 297147817 ps
CPU time 0.81 seconds
Started Jul 03 05:05:45 PM PDT 24
Finished Jul 03 05:05:47 PM PDT 24
Peak memory 182964 kb
Host smart-199e5d14-1d23-4716-bb37-e7561c6048b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154971133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1154971133
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3940768204
Short name T68
Test name
Test status
Simulation time 821547598179 ps
CPU time 360.93 seconds
Started Jul 03 05:05:50 PM PDT 24
Finished Jul 03 05:11:52 PM PDT 24
Peak memory 183056 kb
Host smart-fdd5e2a2-ceae-4abb-86f0-da33bd0162cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940768204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3940768204
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3588264098
Short name T348
Test name
Test status
Simulation time 505080990232 ps
CPU time 178.42 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:08:43 PM PDT 24
Peak memory 183108 kb
Host smart-25f3daf1-66e6-43f1-a51d-c719116a4d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588264098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3588264098
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.729811496
Short name T170
Test name
Test status
Simulation time 302443428145 ps
CPU time 318.41 seconds
Started Jul 03 05:05:49 PM PDT 24
Finished Jul 03 05:11:08 PM PDT 24
Peak memory 191312 kb
Host smart-0b7bd685-5a0b-4f8a-b93f-11d490131d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729811496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.729811496
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2355831680
Short name T432
Test name
Test status
Simulation time 5688040599 ps
CPU time 9.39 seconds
Started Jul 03 05:05:52 PM PDT 24
Finished Jul 03 05:06:02 PM PDT 24
Peak memory 183084 kb
Host smart-74b80dca-0e02-4c31-8de5-a0207a809cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355831680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2355831680
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2510979179
Short name T270
Test name
Test status
Simulation time 244695681403 ps
CPU time 361.14 seconds
Started Jul 03 05:05:49 PM PDT 24
Finished Jul 03 05:11:50 PM PDT 24
Peak memory 183104 kb
Host smart-9aff09d1-f39c-4581-afe9-c93cc845dac7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510979179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2510979179
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2508164878
Short name T430
Test name
Test status
Simulation time 144726479009 ps
CPU time 57.02 seconds
Started Jul 03 05:05:50 PM PDT 24
Finished Jul 03 05:06:48 PM PDT 24
Peak memory 183076 kb
Host smart-7c3993bd-45c0-4ba9-ac78-380cda9570e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508164878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2508164878
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3617123369
Short name T340
Test name
Test status
Simulation time 681231381983 ps
CPU time 1611.85 seconds
Started Jul 03 05:05:46 PM PDT 24
Finished Jul 03 05:32:44 PM PDT 24
Peak memory 193740 kb
Host smart-9c96fd9f-a400-436d-aa16-436069d88995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617123369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3617123369
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3415731430
Short name T149
Test name
Test status
Simulation time 196612258503 ps
CPU time 100.62 seconds
Started Jul 03 05:05:39 PM PDT 24
Finished Jul 03 05:07:20 PM PDT 24
Peak memory 191264 kb
Host smart-b59e8a55-220d-4c8c-9f4b-e2df0172a202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415731430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3415731430
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3388888208
Short name T416
Test name
Test status
Simulation time 323969895470 ps
CPU time 1014.76 seconds
Started Jul 03 05:05:42 PM PDT 24
Finished Jul 03 05:22:37 PM PDT 24
Peak memory 191308 kb
Host smart-57e2db07-fe0c-4cca-8220-094c0c04e763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388888208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3388888208
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1839203336
Short name T113
Test name
Test status
Simulation time 442851277954 ps
CPU time 275.7 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:10:20 PM PDT 24
Peak memory 183100 kb
Host smart-e835c639-c912-4ea6-9d3d-078a595f250b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839203336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1839203336
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.89675352
Short name T392
Test name
Test status
Simulation time 118756512368 ps
CPU time 159.17 seconds
Started Jul 03 05:05:47 PM PDT 24
Finished Jul 03 05:08:27 PM PDT 24
Peak memory 183076 kb
Host smart-accd76f6-5108-459f-8b5a-952bfa02233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89675352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.89675352
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.3917489550
Short name T227
Test name
Test status
Simulation time 126333877818 ps
CPU time 417.54 seconds
Started Jul 03 05:05:48 PM PDT 24
Finished Jul 03 05:12:46 PM PDT 24
Peak memory 191308 kb
Host smart-cbbd02c6-22ab-4708-83cc-e711af76357a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917489550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.3917489550
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.413775962
Short name T437
Test name
Test status
Simulation time 60029914 ps
CPU time 0.61 seconds
Started Jul 03 05:05:49 PM PDT 24
Finished Jul 03 05:05:50 PM PDT 24
Peak memory 182904 kb
Host smart-b587f038-e774-46f7-99bb-8c0312ffce28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413775962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.413775962
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2471223320
Short name T28
Test name
Test status
Simulation time 1810886668 ps
CPU time 1.35 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:05:40 PM PDT 24
Peak memory 192984 kb
Host smart-c31fec80-97c0-44d7-99c3-0b1224735564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471223320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2471223320
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.1680344442
Short name T42
Test name
Test status
Simulation time 55663679149 ps
CPU time 83.16 seconds
Started Jul 03 05:05:52 PM PDT 24
Finished Jul 03 05:07:16 PM PDT 24
Peak memory 197824 kb
Host smart-6e5c361f-3116-4c4b-b3a3-4bad74ea10de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680344442 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.1680344442
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.974434569
Short name T195
Test name
Test status
Simulation time 1614276034294 ps
CPU time 840.17 seconds
Started Jul 03 05:05:46 PM PDT 24
Finished Jul 03 05:19:48 PM PDT 24
Peak memory 183056 kb
Host smart-0df58bab-5703-40e1-b3f0-7327b17275f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974434569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.974434569
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1633527179
Short name T372
Test name
Test status
Simulation time 115996309139 ps
CPU time 126.35 seconds
Started Jul 03 05:05:47 PM PDT 24
Finished Jul 03 05:07:54 PM PDT 24
Peak memory 183076 kb
Host smart-f137f4dc-f8c0-40e4-adb0-09ba21160074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633527179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1633527179
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.454555681
Short name T285
Test name
Test status
Simulation time 333711003891 ps
CPU time 649.13 seconds
Started Jul 03 05:05:51 PM PDT 24
Finished Jul 03 05:16:40 PM PDT 24
Peak memory 191216 kb
Host smart-35f37d08-0f3f-4e42-a853-d1742d8c6e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454555681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.454555681
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2515380478
Short name T436
Test name
Test status
Simulation time 79701416202 ps
CPU time 100.98 seconds
Started Jul 03 05:05:29 PM PDT 24
Finished Jul 03 05:07:10 PM PDT 24
Peak memory 183124 kb
Host smart-3b789122-7a53-458a-af11-479024db447f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515380478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2515380478
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.4143475568
Short name T272
Test name
Test status
Simulation time 196158853480 ps
CPU time 613.07 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:15:33 PM PDT 24
Peak memory 191192 kb
Host smart-b44af521-1f8e-4521-bd0e-3f45a8ba07e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143475568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.4143475568
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.282152320
Short name T382
Test name
Test status
Simulation time 81538159 ps
CPU time 0.61 seconds
Started Jul 03 05:05:33 PM PDT 24
Finished Jul 03 05:05:34 PM PDT 24
Peak memory 182936 kb
Host smart-95371711-9294-48da-bdb4-226d1343790a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282152320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.282152320
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.883353490
Short name T18
Test name
Test status
Simulation time 127212097 ps
CPU time 0.75 seconds
Started Jul 03 05:05:39 PM PDT 24
Finished Jul 03 05:05:40 PM PDT 24
Peak memory 213292 kb
Host smart-44f6e861-8711-48b0-97b9-c6c97f3aab3f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883353490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.883353490
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.691205952
Short name T142
Test name
Test status
Simulation time 3355345663635 ps
CPU time 1768.76 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:35:23 PM PDT 24
Peak memory 182956 kb
Host smart-2ad08ae4-4751-4733-b424-f578525189f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691205952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.691205952
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2904824042
Short name T353
Test name
Test status
Simulation time 47235236247 ps
CPU time 33.32 seconds
Started Jul 03 05:05:55 PM PDT 24
Finished Jul 03 05:06:29 PM PDT 24
Peak memory 183060 kb
Host smart-aab68cd3-4b37-4772-b365-0d072043e491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904824042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2904824042
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1958135999
Short name T247
Test name
Test status
Simulation time 140034745774 ps
CPU time 77.71 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:07:12 PM PDT 24
Peak memory 183108 kb
Host smart-789c056c-c22f-43dd-9ada-e894ad85b2e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958135999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1958135999
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.106992998
Short name T274
Test name
Test status
Simulation time 332073609464 ps
CPU time 136.7 seconds
Started Jul 03 05:05:58 PM PDT 24
Finished Jul 03 05:08:15 PM PDT 24
Peak memory 191272 kb
Host smart-ca9b6bc1-d658-488f-9837-884f480f3ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106992998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.106992998
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3601083720
Short name T69
Test name
Test status
Simulation time 1888921133068 ps
CPU time 815.2 seconds
Started Jul 03 05:05:55 PM PDT 24
Finished Jul 03 05:19:31 PM PDT 24
Peak memory 191284 kb
Host smart-bdb12990-d57f-4269-a6d9-466de9361f93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601083720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3601083720
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1122100357
Short name T3
Test name
Test status
Simulation time 247796053616 ps
CPU time 84.26 seconds
Started Jul 03 05:06:01 PM PDT 24
Finished Jul 03 05:07:26 PM PDT 24
Peak memory 183100 kb
Host smart-e57f73db-4d79-4aa3-8ada-8b51507ba8e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122100357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1122100357
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.34827065
Short name T378
Test name
Test status
Simulation time 99450295825 ps
CPU time 135.36 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:08:00 PM PDT 24
Peak memory 183080 kb
Host smart-bb7dd5be-8458-4011-a433-4e59e5153fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34827065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.34827065
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.753792961
Short name T402
Test name
Test status
Simulation time 676595953 ps
CPU time 1.64 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:05:55 PM PDT 24
Peak memory 191860 kb
Host smart-e0b00888-a286-4760-9996-2489c89541cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753792961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.753792961
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.253046619
Short name T338
Test name
Test status
Simulation time 532729762171 ps
CPU time 638.15 seconds
Started Jul 03 05:05:52 PM PDT 24
Finished Jul 03 05:16:30 PM PDT 24
Peak memory 183064 kb
Host smart-7012fec3-9b1c-4f01-b1f1-49c9d0e692f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253046619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.253046619
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.4255187218
Short name T444
Test name
Test status
Simulation time 527279177782 ps
CPU time 211.53 seconds
Started Jul 03 05:06:01 PM PDT 24
Finished Jul 03 05:09:33 PM PDT 24
Peak memory 183092 kb
Host smart-d5056f59-094d-4393-ac24-8d2eb86e87a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255187218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.4255187218
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3052646136
Short name T421
Test name
Test status
Simulation time 36761613818 ps
CPU time 57.23 seconds
Started Jul 03 05:05:46 PM PDT 24
Finished Jul 03 05:06:43 PM PDT 24
Peak memory 193392 kb
Host smart-bd73b7ed-a9c0-482b-9469-15a81ff43176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052646136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3052646136
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.390005515
Short name T408
Test name
Test status
Simulation time 1009231826 ps
CPU time 1.23 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:05:55 PM PDT 24
Peak memory 182936 kb
Host smart-5febdc7f-39cc-416c-b9e6-bafa12a129e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390005515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.390005515
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3179950423
Short name T153
Test name
Test status
Simulation time 1326046238378 ps
CPU time 945.22 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:21:39 PM PDT 24
Peak memory 183068 kb
Host smart-9837cc50-6412-44b8-9ee4-d253aeff476e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179950423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3179950423
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.481744929
Short name T368
Test name
Test status
Simulation time 728046223897 ps
CPU time 304.44 seconds
Started Jul 03 05:05:46 PM PDT 24
Finished Jul 03 05:10:51 PM PDT 24
Peak memory 183108 kb
Host smart-44de9a28-0afa-4b10-b0f8-d9faac932f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481744929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.481744929
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3362728834
Short name T381
Test name
Test status
Simulation time 1229790528 ps
CPU time 2.94 seconds
Started Jul 03 05:05:51 PM PDT 24
Finished Jul 03 05:05:54 PM PDT 24
Peak memory 183060 kb
Host smart-74d013f5-366f-430d-a10e-01e43623c33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362728834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3362728834
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.1292567695
Short name T324
Test name
Test status
Simulation time 219108460384 ps
CPU time 188.97 seconds
Started Jul 03 05:05:58 PM PDT 24
Finished Jul 03 05:09:07 PM PDT 24
Peak memory 195932 kb
Host smart-6ae41662-7c87-42df-8ce2-fd26315dc150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292567695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.1292567695
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3656908868
Short name T403
Test name
Test status
Simulation time 512920052052 ps
CPU time 211.39 seconds
Started Jul 03 05:05:52 PM PDT 24
Finished Jul 03 05:09:24 PM PDT 24
Peak memory 183008 kb
Host smart-e0d40c08-0657-4744-9654-f39d9124f423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656908868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3656908868
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.4098191780
Short name T286
Test name
Test status
Simulation time 689753093007 ps
CPU time 188.28 seconds
Started Jul 03 05:06:00 PM PDT 24
Finished Jul 03 05:09:09 PM PDT 24
Peak memory 194524 kb
Host smart-786831e4-a5cf-4608-bd9c-6e2cb1af3876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098191780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.4098191780
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.822694281
Short name T425
Test name
Test status
Simulation time 117101929203 ps
CPU time 176.24 seconds
Started Jul 03 05:05:59 PM PDT 24
Finished Jul 03 05:08:56 PM PDT 24
Peak memory 183060 kb
Host smart-7493cad5-cc73-41cb-810f-7e54a6797f91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822694281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.822694281
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3275337612
Short name T397
Test name
Test status
Simulation time 111865089947 ps
CPU time 158.22 seconds
Started Jul 03 05:05:38 PM PDT 24
Finished Jul 03 05:08:17 PM PDT 24
Peak memory 183068 kb
Host smart-8502f8f7-6c5b-4278-84a9-377416720312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275337612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3275337612
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1172827099
Short name T126
Test name
Test status
Simulation time 126246718675 ps
CPU time 815.94 seconds
Started Jul 03 05:06:00 PM PDT 24
Finished Jul 03 05:19:36 PM PDT 24
Peak memory 191316 kb
Host smart-0ce157ea-155c-479e-8db3-5c02eaf14bde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172827099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1172827099
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2095110056
Short name T379
Test name
Test status
Simulation time 34537349197 ps
CPU time 231.67 seconds
Started Jul 03 05:05:56 PM PDT 24
Finished Jul 03 05:09:48 PM PDT 24
Peak memory 183108 kb
Host smart-eb34e3ec-0f1d-470f-a666-bbcb6cd1e16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095110056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2095110056
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3745874027
Short name T249
Test name
Test status
Simulation time 194164104997 ps
CPU time 249.43 seconds
Started Jul 03 05:05:58 PM PDT 24
Finished Jul 03 05:10:08 PM PDT 24
Peak memory 191328 kb
Host smart-45325aa1-93ac-433b-b7c7-d5edaaeed25a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745874027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3745874027
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.4170076712
Short name T14
Test name
Test status
Simulation time 43912070786 ps
CPU time 350.89 seconds
Started Jul 03 05:05:50 PM PDT 24
Finished Jul 03 05:11:42 PM PDT 24
Peak memory 197860 kb
Host smart-7a72a9b9-7ac9-4300-957e-da1e866d9680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170076712 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.4170076712
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2073602515
Short name T8
Test name
Test status
Simulation time 592446329894 ps
CPU time 326.99 seconds
Started Jul 03 05:05:55 PM PDT 24
Finished Jul 03 05:11:22 PM PDT 24
Peak memory 183088 kb
Host smart-e0b711a1-3bb1-4dcf-a2ce-e70505407beb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073602515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2073602515
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2094117722
Short name T395
Test name
Test status
Simulation time 28640459935 ps
CPU time 23.7 seconds
Started Jul 03 05:05:55 PM PDT 24
Finished Jul 03 05:06:19 PM PDT 24
Peak memory 183108 kb
Host smart-a72523fc-5f2c-48f3-88ac-ba330c3a1e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094117722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2094117722
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3106456497
Short name T410
Test name
Test status
Simulation time 14079024214 ps
CPU time 17.79 seconds
Started Jul 03 05:06:03 PM PDT 24
Finished Jul 03 05:06:21 PM PDT 24
Peak memory 191300 kb
Host smart-0f54314f-2e6c-4412-b69f-be880c85e8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106456497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3106456497
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3608745864
Short name T303
Test name
Test status
Simulation time 27140710695 ps
CPU time 52.51 seconds
Started Jul 03 05:05:57 PM PDT 24
Finished Jul 03 05:06:49 PM PDT 24
Peak memory 194200 kb
Host smart-7f9471b7-53bc-4b4d-89c9-5cea528c9b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608745864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3608745864
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2235958533
Short name T336
Test name
Test status
Simulation time 332572560699 ps
CPU time 484.05 seconds
Started Jul 03 05:06:02 PM PDT 24
Finished Jul 03 05:14:06 PM PDT 24
Peak memory 191308 kb
Host smart-aff93e36-025b-4bbf-a369-39ae59c9f994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235958533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2235958533
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3860230746
Short name T196
Test name
Test status
Simulation time 589130766823 ps
CPU time 958.09 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:22:04 PM PDT 24
Peak memory 183024 kb
Host smart-d53b4514-86cb-4a21-9994-8151bdc98007
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860230746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3860230746
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1725231529
Short name T362
Test name
Test status
Simulation time 524882323579 ps
CPU time 310.36 seconds
Started Jul 03 05:05:55 PM PDT 24
Finished Jul 03 05:11:06 PM PDT 24
Peak memory 183068 kb
Host smart-36a4f7e4-b7cf-41d8-b746-46130902ff09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725231529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1725231529
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2998299801
Short name T361
Test name
Test status
Simulation time 13842644 ps
CPU time 0.54 seconds
Started Jul 03 05:05:59 PM PDT 24
Finished Jul 03 05:06:00 PM PDT 24
Peak memory 182916 kb
Host smart-7fff6e0c-2a87-42cb-8cff-4c176ad20467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998299801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2998299801
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.2399496648
Short name T40
Test name
Test status
Simulation time 34497688756 ps
CPU time 249.23 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:10:03 PM PDT 24
Peak memory 205936 kb
Host smart-2f15af9a-cf9c-4c9f-b0ec-aedf621d254a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399496648 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.2399496648
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3083432025
Short name T246
Test name
Test status
Simulation time 302728112567 ps
CPU time 280.95 seconds
Started Jul 03 05:05:56 PM PDT 24
Finished Jul 03 05:10:37 PM PDT 24
Peak memory 183104 kb
Host smart-7c14e670-8141-43ee-84af-4db26bae824a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083432025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3083432025
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2130932523
Short name T386
Test name
Test status
Simulation time 3166711146 ps
CPU time 5.44 seconds
Started Jul 03 05:06:08 PM PDT 24
Finished Jul 03 05:06:14 PM PDT 24
Peak memory 182988 kb
Host smart-6067e8ec-5b5c-4e9b-bdc2-1ed5913ecf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130932523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2130932523
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3310216298
Short name T164
Test name
Test status
Simulation time 143989067446 ps
CPU time 459.03 seconds
Started Jul 03 05:06:01 PM PDT 24
Finished Jul 03 05:13:41 PM PDT 24
Peak memory 191292 kb
Host smart-10b78a39-b59a-477f-b3b2-0d860eeabeef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310216298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3310216298
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2577908567
Short name T256
Test name
Test status
Simulation time 543745041 ps
CPU time 1.26 seconds
Started Jul 03 05:05:58 PM PDT 24
Finished Jul 03 05:06:00 PM PDT 24
Peak memory 182932 kb
Host smart-7b574aa9-1ebc-42f3-bff1-c4b56f70bc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577908567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2577908567
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.918306968
Short name T240
Test name
Test status
Simulation time 122683131447 ps
CPU time 224.39 seconds
Started Jul 03 05:05:49 PM PDT 24
Finished Jul 03 05:09:34 PM PDT 24
Peak memory 191280 kb
Host smart-e61ba3f5-a1e4-467f-bbcd-2203c41a9298
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918306968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
918306968
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3931133824
Short name T192
Test name
Test status
Simulation time 379817527537 ps
CPU time 324.12 seconds
Started Jul 03 05:05:52 PM PDT 24
Finished Jul 03 05:11:17 PM PDT 24
Peak memory 183088 kb
Host smart-0232c5d3-efda-48f3-93ff-7bfb4d5e8ec4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931133824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3931133824
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2005030648
Short name T351
Test name
Test status
Simulation time 891328506488 ps
CPU time 110.57 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:07:58 PM PDT 24
Peak memory 183120 kb
Host smart-dd56ef05-c5a6-4c50-b11f-c65288b27b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005030648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2005030648
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.1720503668
Short name T145
Test name
Test status
Simulation time 42005323914 ps
CPU time 66.68 seconds
Started Jul 03 05:05:57 PM PDT 24
Finished Jul 03 05:07:04 PM PDT 24
Peak memory 183136 kb
Host smart-297af9dc-cf62-4419-8220-e0ec0228e99e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720503668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1720503668
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.476251249
Short name T112
Test name
Test status
Simulation time 17552541207 ps
CPU time 27.41 seconds
Started Jul 03 05:05:54 PM PDT 24
Finished Jul 03 05:06:22 PM PDT 24
Peak memory 183000 kb
Host smart-3e23ada8-c01e-4941-a2c9-210f06d50036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476251249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.476251249
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.833068974
Short name T13
Test name
Test status
Simulation time 12898874819 ps
CPU time 132.14 seconds
Started Jul 03 05:05:53 PM PDT 24
Finished Jul 03 05:08:06 PM PDT 24
Peak memory 197860 kb
Host smart-a97049c7-e96e-4475-812c-9f69583ec16f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833068974 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.833068974
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2250273469
Short name T281
Test name
Test status
Simulation time 436420434936 ps
CPU time 384.44 seconds
Started Jul 03 05:05:43 PM PDT 24
Finished Jul 03 05:12:08 PM PDT 24
Peak memory 183072 kb
Host smart-76716191-4083-4dc3-a819-a27f6c7690bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250273469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2250273469
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.3921834632
Short name T24
Test name
Test status
Simulation time 410482611463 ps
CPU time 147.6 seconds
Started Jul 03 05:05:31 PM PDT 24
Finished Jul 03 05:07:59 PM PDT 24
Peak memory 183124 kb
Host smart-48aa15bf-3fb2-4809-b630-1b91bf593937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921834632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.3921834632
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.1752002916
Short name T121
Test name
Test status
Simulation time 79310912948 ps
CPU time 158.36 seconds
Started Jul 03 05:05:27 PM PDT 24
Finished Jul 03 05:08:06 PM PDT 24
Peak memory 191276 kb
Host smart-dd6c869c-25f7-47dc-a8b6-d793264c0286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752002916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.1752002916
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2565710898
Short name T11
Test name
Test status
Simulation time 16218256596 ps
CPU time 85.57 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:06:47 PM PDT 24
Peak memory 183136 kb
Host smart-e7f4551e-644a-4198-9546-00f50321198e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565710898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2565710898
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2219008759
Short name T16
Test name
Test status
Simulation time 397495623 ps
CPU time 1 seconds
Started Jul 03 05:05:19 PM PDT 24
Finished Jul 03 05:05:22 PM PDT 24
Peak memory 214508 kb
Host smart-0f8af56c-b3d5-4e3a-ba97-7eb361fb78b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219008759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2219008759
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1994645860
Short name T440
Test name
Test status
Simulation time 273395039144 ps
CPU time 418.68 seconds
Started Jul 03 05:05:37 PM PDT 24
Finished Jul 03 05:12:37 PM PDT 24
Peak memory 191244 kb
Host smart-67522f5d-2bbd-4f9f-b3c2-5c44f807c9e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994645860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1994645860
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.4026329783
Short name T343
Test name
Test status
Simulation time 1947842246884 ps
CPU time 1043.02 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:23:31 PM PDT 24
Peak memory 183096 kb
Host smart-d36397d3-8f32-4d75-ac54-46151d9d537e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026329783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.4026329783
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.4046849394
Short name T391
Test name
Test status
Simulation time 187803385903 ps
CPU time 251.42 seconds
Started Jul 03 05:05:54 PM PDT 24
Finished Jul 03 05:10:06 PM PDT 24
Peak memory 183092 kb
Host smart-c20209b0-8d31-4df4-9924-782a2f152ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046849394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.4046849394
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3962712738
Short name T175
Test name
Test status
Simulation time 289784788844 ps
CPU time 313.74 seconds
Started Jul 03 05:05:55 PM PDT 24
Finished Jul 03 05:11:09 PM PDT 24
Peak memory 191260 kb
Host smart-5a4d8f18-b633-46a4-aa51-0a25efaa5e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962712738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3962712738
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3824200877
Short name T2
Test name
Test status
Simulation time 200489467876 ps
CPU time 143.44 seconds
Started Jul 03 05:06:03 PM PDT 24
Finished Jul 03 05:08:27 PM PDT 24
Peak memory 191256 kb
Host smart-faf361cd-1515-4e7a-8b04-698624a1b626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824200877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3824200877
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1669368279
Short name T20
Test name
Test status
Simulation time 214213024747 ps
CPU time 362.13 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:12:16 PM PDT 24
Peak memory 195932 kb
Host smart-0884db74-6418-4d34-98ef-e9332f6daa75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669368279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1669368279
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2927533597
Short name T217
Test name
Test status
Simulation time 17560476758 ps
CPU time 28.51 seconds
Started Jul 03 05:05:52 PM PDT 24
Finished Jul 03 05:06:20 PM PDT 24
Peak memory 183068 kb
Host smart-2ea85c8f-e0e2-40b1-a75c-3e14b802d52c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927533597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2927533597
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2797472450
Short name T349
Test name
Test status
Simulation time 33605493114 ps
CPU time 24.2 seconds
Started Jul 03 05:06:00 PM PDT 24
Finished Jul 03 05:06:24 PM PDT 24
Peak memory 183084 kb
Host smart-16ec2a82-5468-4eb5-a295-45b4e69d36c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797472450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2797472450
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2999840362
Short name T144
Test name
Test status
Simulation time 158344442110 ps
CPU time 342.08 seconds
Started Jul 03 05:06:01 PM PDT 24
Finished Jul 03 05:11:43 PM PDT 24
Peak memory 191320 kb
Host smart-25bc75c0-fd54-4a6a-8058-19646bc977ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999840362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2999840362
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2824150835
Short name T373
Test name
Test status
Simulation time 1821623662332 ps
CPU time 866.18 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:20:33 PM PDT 24
Peak memory 191284 kb
Host smart-46cd26d4-1667-4f00-8bde-951f0975bc11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824150835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2824150835
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3865548849
Short name T223
Test name
Test status
Simulation time 21329941119 ps
CPU time 35.08 seconds
Started Jul 03 05:06:04 PM PDT 24
Finished Jul 03 05:06:39 PM PDT 24
Peak memory 183072 kb
Host smart-0381593f-64ba-4444-bbcd-45833efcb341
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865548849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3865548849
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1179515826
Short name T389
Test name
Test status
Simulation time 70504434620 ps
CPU time 92.65 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:07:41 PM PDT 24
Peak memory 183120 kb
Host smart-cf084c58-59c3-4449-b64e-bf7d01e60a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179515826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1179515826
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1815573697
Short name T328
Test name
Test status
Simulation time 59944392761 ps
CPU time 60.21 seconds
Started Jul 03 05:05:57 PM PDT 24
Finished Jul 03 05:06:58 PM PDT 24
Peak memory 191280 kb
Host smart-30a060f6-5f17-4d32-bd27-355ae007be71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815573697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1815573697
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.549893447
Short name T418
Test name
Test status
Simulation time 55632094648 ps
CPU time 31.57 seconds
Started Jul 03 05:06:02 PM PDT 24
Finished Jul 03 05:06:34 PM PDT 24
Peak memory 191280 kb
Host smart-5a5bb379-6283-4f69-be2c-15fb60ed12da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549893447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.549893447
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.906910594
Short name T431
Test name
Test status
Simulation time 5850528139 ps
CPU time 9.64 seconds
Started Jul 03 05:05:57 PM PDT 24
Finished Jul 03 05:06:07 PM PDT 24
Peak memory 193976 kb
Host smart-c05e2417-5a84-4ffa-b5be-a3629a946e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906910594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
906910594
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.4278161262
Short name T91
Test name
Test status
Simulation time 35771924675 ps
CPU time 278.8 seconds
Started Jul 03 05:05:57 PM PDT 24
Finished Jul 03 05:10:36 PM PDT 24
Peak memory 206024 kb
Host smart-2731cc05-9837-4a06-a216-21ea2b5d8e0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278161262 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.4278161262
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.779415095
Short name T43
Test name
Test status
Simulation time 165144601444 ps
CPU time 276.42 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:10:44 PM PDT 24
Peak memory 183092 kb
Host smart-bfcd1cb1-254d-4780-baba-61ec9127c99a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779415095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.779415095
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3683819706
Short name T433
Test name
Test status
Simulation time 569802068860 ps
CPU time 200.96 seconds
Started Jul 03 05:05:54 PM PDT 24
Finished Jul 03 05:09:16 PM PDT 24
Peak memory 183092 kb
Host smart-8a7244f2-d5e8-4243-9e73-71201dbfd871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683819706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3683819706
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.92966428
Short name T167
Test name
Test status
Simulation time 127263769259 ps
CPU time 197.38 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:09:28 PM PDT 24
Peak memory 191312 kb
Host smart-ac43725c-2c4b-4b12-84ba-cebd022fc4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92966428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.92966428
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2581844944
Short name T329
Test name
Test status
Simulation time 68991917878 ps
CPU time 79.63 seconds
Started Jul 03 05:05:59 PM PDT 24
Finished Jul 03 05:07:19 PM PDT 24
Peak memory 183068 kb
Host smart-6d3f7d82-45b3-4949-b0bc-3ff54a50ed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581844944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2581844944
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2368818958
Short name T255
Test name
Test status
Simulation time 1000171618944 ps
CPU time 749.62 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:18:38 PM PDT 24
Peak memory 191272 kb
Host smart-47aa3a9a-8873-4c15-a996-23a2504bd624
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368818958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2368818958
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2103296774
Short name T377
Test name
Test status
Simulation time 543553005997 ps
CPU time 215.33 seconds
Started Jul 03 05:06:04 PM PDT 24
Finished Jul 03 05:09:40 PM PDT 24
Peak memory 182984 kb
Host smart-5ab7d0c7-d3a4-492a-a3c2-ef33a9bf0bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103296774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2103296774
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1702139904
Short name T116
Test name
Test status
Simulation time 446166175834 ps
CPU time 381.05 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:12:32 PM PDT 24
Peak memory 191324 kb
Host smart-1ff81908-8bb5-4692-8938-6898f91aa983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702139904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1702139904
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2219646839
Short name T376
Test name
Test status
Simulation time 20254488178 ps
CPU time 18.14 seconds
Started Jul 03 05:06:00 PM PDT 24
Finished Jul 03 05:06:19 PM PDT 24
Peak memory 194916 kb
Host smart-d787134c-8213-4950-a6ae-97eec5562344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219646839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2219646839
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2510721574
Short name T252
Test name
Test status
Simulation time 469141186321 ps
CPU time 461.82 seconds
Started Jul 03 05:06:01 PM PDT 24
Finished Jul 03 05:13:43 PM PDT 24
Peak memory 183100 kb
Host smart-2506ff39-7d02-4aba-bc4c-6b7d840d40e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510721574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2510721574
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2713429668
Short name T374
Test name
Test status
Simulation time 43934158298 ps
CPU time 68.24 seconds
Started Jul 03 05:06:00 PM PDT 24
Finished Jul 03 05:07:08 PM PDT 24
Peak memory 183108 kb
Host smart-67bd8a8c-7802-4743-aaf6-a033ab1b0db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713429668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2713429668
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3428552865
Short name T56
Test name
Test status
Simulation time 1128209719131 ps
CPU time 493.29 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:14:20 PM PDT 24
Peak memory 191308 kb
Host smart-7ce232ef-dafc-41b7-97a5-ae18246dc409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428552865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3428552865
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.4284907131
Short name T413
Test name
Test status
Simulation time 361455364 ps
CPU time 0.66 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:06:09 PM PDT 24
Peak memory 182896 kb
Host smart-b5939d81-a29c-44af-8c6e-0fcba21f7bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284907131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.4284907131
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1495406596
Short name T300
Test name
Test status
Simulation time 270183764222 ps
CPU time 415.83 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:13:06 PM PDT 24
Peak memory 183064 kb
Host smart-8c871425-2202-47fc-8a2d-b8f621ceae16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495406596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1495406596
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.963077226
Short name T59
Test name
Test status
Simulation time 373377215861 ps
CPU time 151.18 seconds
Started Jul 03 05:06:08 PM PDT 24
Finished Jul 03 05:08:40 PM PDT 24
Peak memory 183100 kb
Host smart-6b6d5520-6275-49f7-bfb8-7290025d2be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963077226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.963077226
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3608063787
Short name T198
Test name
Test status
Simulation time 105645654294 ps
CPU time 1183.5 seconds
Started Jul 03 05:06:02 PM PDT 24
Finished Jul 03 05:25:46 PM PDT 24
Peak memory 191308 kb
Host smart-aac7898d-6703-445d-b1a1-d49c1c95b087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608063787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3608063787
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3536474365
Short name T404
Test name
Test status
Simulation time 26388298485 ps
CPU time 39.21 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:06:47 PM PDT 24
Peak memory 182988 kb
Host smart-1c127a00-247d-4c50-8b3d-4a9ecf7e5b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536474365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3536474365
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.232865895
Short name T41
Test name
Test status
Simulation time 149897142952 ps
CPU time 1225.69 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:26:33 PM PDT 24
Peak memory 214008 kb
Host smart-2a1c02fd-032e-44a7-bda2-97ac01146eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232865895 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.232865895
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1283842506
Short name T201
Test name
Test status
Simulation time 2897188979105 ps
CPU time 1230.69 seconds
Started Jul 03 05:06:05 PM PDT 24
Finished Jul 03 05:26:36 PM PDT 24
Peak memory 182684 kb
Host smart-aab3096c-20e3-483e-8200-6218ee62012a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283842506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1283842506
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3534160688
Short name T414
Test name
Test status
Simulation time 77659368316 ps
CPU time 62.12 seconds
Started Jul 03 05:06:09 PM PDT 24
Finished Jul 03 05:07:12 PM PDT 24
Peak memory 183108 kb
Host smart-778a932d-f959-4ba8-b3c9-fdf8e2542fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534160688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3534160688
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2939962645
Short name T315
Test name
Test status
Simulation time 69526712512 ps
CPU time 370.06 seconds
Started Jul 03 05:05:59 PM PDT 24
Finished Jul 03 05:12:09 PM PDT 24
Peak memory 183080 kb
Host smart-01a2701f-8e28-45c7-9f1c-2c7aa784f753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939962645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2939962645
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.4269302963
Short name T99
Test name
Test status
Simulation time 486616967306 ps
CPU time 395.44 seconds
Started Jul 03 05:06:01 PM PDT 24
Finished Jul 03 05:12:37 PM PDT 24
Peak memory 183116 kb
Host smart-19747930-7726-48e7-95b0-a838898a2380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269302963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.4269302963
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3213579126
Short name T159
Test name
Test status
Simulation time 1459484801062 ps
CPU time 439.34 seconds
Started Jul 03 05:06:05 PM PDT 24
Finished Jul 03 05:13:25 PM PDT 24
Peak memory 182680 kb
Host smart-dc1ae8e4-33e4-4efa-bdc6-3b5861838627
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213579126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3213579126
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.631705034
Short name T354
Test name
Test status
Simulation time 80901153428 ps
CPU time 19.43 seconds
Started Jul 03 05:06:01 PM PDT 24
Finished Jul 03 05:06:21 PM PDT 24
Peak memory 183084 kb
Host smart-243760e6-3503-48e7-8f65-fb0e9eb01f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631705034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.631705034
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2222117876
Short name T220
Test name
Test status
Simulation time 53260731193 ps
CPU time 94.67 seconds
Started Jul 03 05:06:04 PM PDT 24
Finished Jul 03 05:07:39 PM PDT 24
Peak memory 191272 kb
Host smart-dbd0e3c9-ff08-4337-a65c-567fc39c4484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222117876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2222117876
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1582697304
Short name T387
Test name
Test status
Simulation time 607481683 ps
CPU time 0.89 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:06:08 PM PDT 24
Peak memory 182972 kb
Host smart-8c2cbc95-a966-492e-8c28-31d16cc14f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582697304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1582697304
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2573889473
Short name T132
Test name
Test status
Simulation time 281460674274 ps
CPU time 338.37 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:11:51 PM PDT 24
Peak memory 191324 kb
Host smart-b0587d33-7314-4146-9161-481aaa92a821
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573889473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2573889473
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3921022351
Short name T234
Test name
Test status
Simulation time 318641626066 ps
CPU time 543.22 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:15:11 PM PDT 24
Peak memory 182992 kb
Host smart-0d8cfe9b-5a29-4c70-a9dc-d6a367ac78f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921022351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3921022351
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.525965534
Short name T355
Test name
Test status
Simulation time 58147498561 ps
CPU time 40.51 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:06:53 PM PDT 24
Peak memory 182976 kb
Host smart-c517a05e-c0e1-4dd2-84d1-921d330abf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525965534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.525965534
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2166327911
Short name T109
Test name
Test status
Simulation time 419377029240 ps
CPU time 659.2 seconds
Started Jul 03 05:06:04 PM PDT 24
Finished Jul 03 05:17:04 PM PDT 24
Peak memory 191284 kb
Host smart-17cca2f1-61e6-4383-8e65-58f649d1d7e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166327911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2166327911
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1672359777
Short name T296
Test name
Test status
Simulation time 53213767675 ps
CPU time 245 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:10:19 PM PDT 24
Peak memory 191268 kb
Host smart-448865b3-43f6-40e3-ba0d-c9a7e5538342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672359777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1672359777
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.2178440600
Short name T356
Test name
Test status
Simulation time 477525035624 ps
CPU time 206.5 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:09:39 PM PDT 24
Peak memory 191300 kb
Host smart-3f404def-5e4c-4755-97dd-c418609cdb6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178440600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.2178440600
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.622993632
Short name T10
Test name
Test status
Simulation time 18660699840 ps
CPU time 16.01 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:05:35 PM PDT 24
Peak memory 183092 kb
Host smart-c7e647a0-3360-4e70-97a7-beae494c7617
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622993632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.622993632
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.859952768
Short name T390
Test name
Test status
Simulation time 998777829153 ps
CPU time 295.65 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:10:40 PM PDT 24
Peak memory 183080 kb
Host smart-696d0c41-c8ed-489b-baf7-40feb70bdb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859952768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.859952768
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.596677029
Short name T282
Test name
Test status
Simulation time 1244338778443 ps
CPU time 310.99 seconds
Started Jul 03 05:05:40 PM PDT 24
Finished Jul 03 05:10:51 PM PDT 24
Peak memory 191312 kb
Host smart-8cd90078-4acc-4997-9624-cc6b6a1c9ca4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596677029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.596677029
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2798807358
Short name T445
Test name
Test status
Simulation time 44506870230 ps
CPU time 47.75 seconds
Started Jul 03 05:05:21 PM PDT 24
Finished Jul 03 05:06:11 PM PDT 24
Peak memory 182964 kb
Host smart-1ee72063-5eeb-4ea4-8b06-41b762cf0c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798807358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2798807358
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1887094883
Short name T216
Test name
Test status
Simulation time 584323994672 ps
CPU time 1123.11 seconds
Started Jul 03 05:05:21 PM PDT 24
Finished Jul 03 05:24:07 PM PDT 24
Peak memory 191292 kb
Host smart-4652bfb5-6d7b-49bb-a4b3-f4282c3e7566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887094883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1887094883
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.663437538
Short name T102
Test name
Test status
Simulation time 530842120768 ps
CPU time 1182.01 seconds
Started Jul 03 05:06:15 PM PDT 24
Finished Jul 03 05:25:58 PM PDT 24
Peak memory 191276 kb
Host smart-7dbee071-3058-4a08-b690-df5afbdca369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663437538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.663437538
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.220757901
Short name T4
Test name
Test status
Simulation time 95322597619 ps
CPU time 54.32 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:07:00 PM PDT 24
Peak memory 183064 kb
Host smart-3811e9cc-53fa-4d69-ac91-1b1aa324371d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220757901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.220757901
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.27745849
Short name T244
Test name
Test status
Simulation time 18780645366 ps
CPU time 33.08 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:06:47 PM PDT 24
Peak memory 183104 kb
Host smart-4b55f5be-87a5-4444-9b63-0ae49ed7570a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27745849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.27745849
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.4285993160
Short name T125
Test name
Test status
Simulation time 92874108402 ps
CPU time 182.92 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:09:17 PM PDT 24
Peak memory 191172 kb
Host smart-5eb97c76-06e1-48dc-a2b6-3275a5f7bb31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285993160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.4285993160
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2962096593
Short name T301
Test name
Test status
Simulation time 259574606301 ps
CPU time 140.56 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:08:34 PM PDT 24
Peak memory 191284 kb
Host smart-e2f5b411-4960-46cb-8766-4c5764240b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962096593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2962096593
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.574522267
Short name T136
Test name
Test status
Simulation time 111029556162 ps
CPU time 672.23 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:17:24 PM PDT 24
Peak memory 194796 kb
Host smart-e2a9bec5-0978-433a-b6a4-b59e1b4abee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574522267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.574522267
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2885364555
Short name T229
Test name
Test status
Simulation time 1674211378593 ps
CPU time 963.45 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:22:16 PM PDT 24
Peak memory 191336 kb
Host smart-401d3712-c743-4a94-8c6a-dbf1427c74f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885364555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2885364555
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1287828493
Short name T310
Test name
Test status
Simulation time 12460716470 ps
CPU time 57.96 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:07:11 PM PDT 24
Peak memory 183092 kb
Host smart-4f02c65d-94f6-474c-82f3-295b33c7a83a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287828493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1287828493
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2693956640
Short name T259
Test name
Test status
Simulation time 734216571513 ps
CPU time 853.83 seconds
Started Jul 03 05:06:08 PM PDT 24
Finished Jul 03 05:20:23 PM PDT 24
Peak memory 191260 kb
Host smart-46993f95-fbc8-46f1-b65c-bdffd3d5bf68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693956640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2693956640
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1434378124
Short name T224
Test name
Test status
Simulation time 81656012136 ps
CPU time 297.44 seconds
Started Jul 03 05:06:08 PM PDT 24
Finished Jul 03 05:11:06 PM PDT 24
Peak memory 191280 kb
Host smart-33e83483-aa87-42cb-9404-f295ebb5b76c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434378124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1434378124
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2744801378
Short name T302
Test name
Test status
Simulation time 1217247697932 ps
CPU time 457.87 seconds
Started Jul 03 05:05:30 PM PDT 24
Finished Jul 03 05:13:08 PM PDT 24
Peak memory 183068 kb
Host smart-593464a1-5dd2-45ee-8338-d3f4f828a760
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744801378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2744801378
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2305497610
Short name T350
Test name
Test status
Simulation time 338766418125 ps
CPU time 244.16 seconds
Started Jul 03 05:05:44 PM PDT 24
Finished Jul 03 05:09:49 PM PDT 24
Peak memory 183100 kb
Host smart-9886f609-3b4e-4924-918c-a341a5883309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305497610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2305497610
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2995979798
Short name T176
Test name
Test status
Simulation time 75511285413 ps
CPU time 101.51 seconds
Started Jul 03 05:05:37 PM PDT 24
Finished Jul 03 05:07:19 PM PDT 24
Peak memory 191280 kb
Host smart-1a3c1c12-b81b-432e-9559-273ebea5edb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995979798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2995979798
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.472357783
Short name T365
Test name
Test status
Simulation time 58890705275 ps
CPU time 51.34 seconds
Started Jul 03 05:05:17 PM PDT 24
Finished Jul 03 05:06:10 PM PDT 24
Peak memory 191280 kb
Host smart-24c25e0c-c01e-4a96-ae16-4000703cb05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472357783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.472357783
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.155892449
Short name T345
Test name
Test status
Simulation time 146829412871 ps
CPU time 110.01 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:08:03 PM PDT 24
Peak memory 194228 kb
Host smart-8f2267fc-0509-40ca-8f44-394212b34e90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155892449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.155892449
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1631644018
Short name T162
Test name
Test status
Simulation time 718887592156 ps
CPU time 165.53 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:08:58 PM PDT 24
Peak memory 191316 kb
Host smart-7d181a5f-b52d-4e67-9db3-7d5e77e23f18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631644018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1631644018
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2468472571
Short name T231
Test name
Test status
Simulation time 506323119082 ps
CPU time 405.38 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:12:59 PM PDT 24
Peak memory 192632 kb
Host smart-d29097f6-5867-4164-bd3b-f1b47ecb8b9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468472571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2468472571
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.4135132377
Short name T333
Test name
Test status
Simulation time 435726265936 ps
CPU time 253.03 seconds
Started Jul 03 05:06:05 PM PDT 24
Finished Jul 03 05:10:19 PM PDT 24
Peak memory 191260 kb
Host smart-3c2ac287-0737-4e45-8fd9-b6aefc919434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135132377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.4135132377
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3092776036
Short name T307
Test name
Test status
Simulation time 259112576111 ps
CPU time 407.1 seconds
Started Jul 03 05:06:17 PM PDT 24
Finished Jul 03 05:13:05 PM PDT 24
Peak memory 191316 kb
Host smart-0a023b73-a2e2-4d26-a0bc-d1bb4008480a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092776036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3092776036
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3476486491
Short name T347
Test name
Test status
Simulation time 556888079544 ps
CPU time 1358.03 seconds
Started Jul 03 05:06:08 PM PDT 24
Finished Jul 03 05:28:47 PM PDT 24
Peak memory 191280 kb
Host smart-0bafaf33-21ce-4581-87d3-b50e9d1d132f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476486491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3476486491
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.2418738199
Short name T257
Test name
Test status
Simulation time 99864977272 ps
CPU time 2720.21 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:51:34 PM PDT 24
Peak memory 191308 kb
Host smart-3ee48381-115f-4ceb-8d9e-922dd25dfed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418738199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2418738199
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.3478246224
Short name T415
Test name
Test status
Simulation time 39760275850 ps
CPU time 58.86 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:07:12 PM PDT 24
Peak memory 191300 kb
Host smart-2dbf2b69-78c1-4756-8c52-db5cc82174e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478246224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.3478246224
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2273621504
Short name T57
Test name
Test status
Simulation time 93169103524 ps
CPU time 90.34 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:07:42 PM PDT 24
Peak memory 191204 kb
Host smart-d56bb6e3-efec-4337-850c-47dd9adde390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273621504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2273621504
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.568549073
Short name T383
Test name
Test status
Simulation time 107650689781 ps
CPU time 40.13 seconds
Started Jul 03 05:05:28 PM PDT 24
Finished Jul 03 05:06:08 PM PDT 24
Peak memory 183112 kb
Host smart-26958a7f-00c1-4f68-a271-c43e6b828c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568549073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.568549073
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3541643802
Short name T182
Test name
Test status
Simulation time 151928820569 ps
CPU time 114.8 seconds
Started Jul 03 05:05:21 PM PDT 24
Finished Jul 03 05:07:18 PM PDT 24
Peak memory 191316 kb
Host smart-41723f21-eafe-4d3c-9390-58eced8f82c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541643802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3541643802
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2918186719
Short name T206
Test name
Test status
Simulation time 53437063222 ps
CPU time 104.35 seconds
Started Jul 03 05:05:30 PM PDT 24
Finished Jul 03 05:07:14 PM PDT 24
Peak memory 191288 kb
Host smart-4b92d922-1dc3-40e1-8ec9-9ccb0f9d2a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918186719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2918186719
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.1429423972
Short name T426
Test name
Test status
Simulation time 36724833839 ps
CPU time 74.18 seconds
Started Jul 03 05:06:09 PM PDT 24
Finished Jul 03 05:07:24 PM PDT 24
Peak memory 183068 kb
Host smart-4af779c8-7aa5-49b7-9f81-33fda081c8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429423972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1429423972
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1155587850
Short name T323
Test name
Test status
Simulation time 395398186341 ps
CPU time 195.27 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:09:22 PM PDT 24
Peak memory 191276 kb
Host smart-129bf8ca-23cc-400f-b30e-93f5edf8ab87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155587850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1155587850
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2415083963
Short name T275
Test name
Test status
Simulation time 98502715681 ps
CPU time 161.57 seconds
Started Jul 03 05:06:02 PM PDT 24
Finished Jul 03 05:08:44 PM PDT 24
Peak memory 191284 kb
Host smart-8f93a388-95d2-4651-b005-da651f4e2835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415083963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2415083963
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.4028772883
Short name T53
Test name
Test status
Simulation time 97864195842 ps
CPU time 272.47 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:10:43 PM PDT 24
Peak memory 194284 kb
Host smart-d24dd643-5746-4d0a-bdda-ae407783d496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028772883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.4028772883
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.441121619
Short name T429
Test name
Test status
Simulation time 33810182474 ps
CPU time 56.59 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:07:07 PM PDT 24
Peak memory 183108 kb
Host smart-9f1051cb-56fb-4ecc-b9da-6468c5847b80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441121619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.441121619
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3380947577
Short name T294
Test name
Test status
Simulation time 610713050031 ps
CPU time 2382.52 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:45:50 PM PDT 24
Peak memory 191316 kb
Host smart-ff003b0f-a675-456f-9f1c-1a636c0bdd2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380947577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3380947577
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1651988571
Short name T214
Test name
Test status
Simulation time 496079278661 ps
CPU time 786.68 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:19:13 PM PDT 24
Peak memory 191292 kb
Host smart-8755c2f8-95a5-498b-8d2b-f52a6ab2ed3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651988571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1651988571
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.4145398515
Short name T23
Test name
Test status
Simulation time 2353286871 ps
CPU time 4.89 seconds
Started Jul 03 05:06:09 PM PDT 24
Finished Jul 03 05:06:14 PM PDT 24
Peak memory 183108 kb
Host smart-51ef9a17-dfd2-4736-8031-ecc23a9cc76d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145398515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.4145398515
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.797293298
Short name T385
Test name
Test status
Simulation time 15997588807 ps
CPU time 18.74 seconds
Started Jul 03 05:05:34 PM PDT 24
Finished Jul 03 05:05:53 PM PDT 24
Peak memory 183128 kb
Host smart-f1de5826-4405-4bab-b662-c4f31dd542f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797293298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.797293298
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2808899550
Short name T399
Test name
Test status
Simulation time 27699000168 ps
CPU time 36.82 seconds
Started Jul 03 05:05:25 PM PDT 24
Finished Jul 03 05:06:02 PM PDT 24
Peak memory 183068 kb
Host smart-f6358399-1826-4331-988a-030e7d455a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808899550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2808899550
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.658152981
Short name T446
Test name
Test status
Simulation time 44102749352 ps
CPU time 89.61 seconds
Started Jul 03 05:05:55 PM PDT 24
Finished Jul 03 05:07:25 PM PDT 24
Peak memory 183100 kb
Host smart-02bbd874-aed0-42c9-b39b-3d6b151880ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658152981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.658152981
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1680303556
Short name T225
Test name
Test status
Simulation time 132657680945 ps
CPU time 55.93 seconds
Started Jul 03 05:05:18 PM PDT 24
Finished Jul 03 05:06:16 PM PDT 24
Peak memory 183088 kb
Host smart-eadc480c-fa69-4116-99b2-a0e82248f6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680303556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1680303556
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4168436397
Short name T401
Test name
Test status
Simulation time 328610881000 ps
CPU time 261.65 seconds
Started Jul 03 05:05:32 PM PDT 24
Finished Jul 03 05:09:54 PM PDT 24
Peak memory 191304 kb
Host smart-3890065f-f14a-4a0f-acd7-8beae628324d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168436397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4168436397
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3694667018
Short name T235
Test name
Test status
Simulation time 381467688692 ps
CPU time 210.16 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:09:43 PM PDT 24
Peak memory 191316 kb
Host smart-a8a2ec1a-2386-4b48-b739-47c57182f21b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694667018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3694667018
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.542827196
Short name T306
Test name
Test status
Simulation time 282258533086 ps
CPU time 146.84 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:08:40 PM PDT 24
Peak memory 191300 kb
Host smart-c8ea6511-b963-4d8c-a325-e922739d6236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542827196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.542827196
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1554735575
Short name T228
Test name
Test status
Simulation time 21470585476 ps
CPU time 362.65 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:12:10 PM PDT 24
Peak memory 191316 kb
Host smart-c1648bd0-f611-4953-97ca-e007beaf5074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554735575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1554735575
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.4148047645
Short name T305
Test name
Test status
Simulation time 195176310306 ps
CPU time 100.54 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:07:53 PM PDT 24
Peak memory 183092 kb
Host smart-1b79327b-48e4-47b6-8fca-3032499bbfb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148047645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.4148047645
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.2414078551
Short name T163
Test name
Test status
Simulation time 33982144062 ps
CPU time 60.51 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:07:13 PM PDT 24
Peak memory 191256 kb
Host smart-a8563c00-db19-443e-b08c-86783562055b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414078551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.2414078551
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1868015571
Short name T202
Test name
Test status
Simulation time 418868326205 ps
CPU time 183.73 seconds
Started Jul 03 05:06:15 PM PDT 24
Finished Jul 03 05:09:20 PM PDT 24
Peak memory 191316 kb
Host smart-15f95b1c-8625-4fc0-9544-8173bd93b83c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868015571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1868015571
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.756199789
Short name T130
Test name
Test status
Simulation time 967779650558 ps
CPU time 768.76 seconds
Started Jul 03 05:06:07 PM PDT 24
Finished Jul 03 05:18:57 PM PDT 24
Peak memory 191300 kb
Host smart-1f28cbd0-ce10-4f16-a089-3fe235cd4060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756199789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.756199789
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3910360404
Short name T200
Test name
Test status
Simulation time 681631938816 ps
CPU time 637.28 seconds
Started Jul 03 05:06:06 PM PDT 24
Finished Jul 03 05:16:44 PM PDT 24
Peak memory 191260 kb
Host smart-192d4bc2-ddb3-42c5-b58c-d67554916ea7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910360404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3910360404
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3286759941
Short name T337
Test name
Test status
Simulation time 568743780826 ps
CPU time 1423.48 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:29:57 PM PDT 24
Peak memory 191316 kb
Host smart-1f7e8405-959a-4ded-a803-8488c7fdcedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286759941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3286759941
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.66679396
Short name T326
Test name
Test status
Simulation time 255890759893 ps
CPU time 97.12 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:07:50 PM PDT 24
Peak memory 191212 kb
Host smart-24a23ff8-8b97-465e-bf10-823fe07f09c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66679396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.66679396
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3237909391
Short name T219
Test name
Test status
Simulation time 337737060664 ps
CPU time 317.07 seconds
Started Jul 03 05:05:20 PM PDT 24
Finished Jul 03 05:10:40 PM PDT 24
Peak memory 183084 kb
Host smart-278b30e4-00f3-436a-9165-c0366cbd9af9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237909391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3237909391
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1835013109
Short name T366
Test name
Test status
Simulation time 10402000607 ps
CPU time 14.79 seconds
Started Jul 03 05:05:27 PM PDT 24
Finished Jul 03 05:05:42 PM PDT 24
Peak memory 183088 kb
Host smart-360463dd-fae8-4699-ad76-416c6fe16cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835013109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1835013109
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.624112346
Short name T441
Test name
Test status
Simulation time 12654528923 ps
CPU time 24.51 seconds
Started Jul 03 05:05:36 PM PDT 24
Finished Jul 03 05:06:01 PM PDT 24
Peak memory 191268 kb
Host smart-3dc7705e-1f62-4755-88ec-a453f397e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624112346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.624112346
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3476232459
Short name T117
Test name
Test status
Simulation time 583518747426 ps
CPU time 2513.05 seconds
Started Jul 03 05:05:24 PM PDT 24
Finished Jul 03 05:47:18 PM PDT 24
Peak memory 191264 kb
Host smart-eb6a4863-d94d-40af-9674-8bea388d4048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476232459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3476232459
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.1013560101
Short name T58
Test name
Test status
Simulation time 431206271973 ps
CPU time 246.84 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:10:18 PM PDT 24
Peak memory 191312 kb
Host smart-358f1ead-5485-411e-b744-1b3188a4bfc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013560101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1013560101
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2378518035
Short name T297
Test name
Test status
Simulation time 106365679228 ps
CPU time 151.93 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:08:43 PM PDT 24
Peak memory 194980 kb
Host smart-9d21911a-c860-4673-a07b-2c29e64b9068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378518035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2378518035
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1725215497
Short name T260
Test name
Test status
Simulation time 194140174193 ps
CPU time 163.08 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:08:56 PM PDT 24
Peak memory 191292 kb
Host smart-39b79732-3567-4d57-8c34-3147f888cade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725215497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1725215497
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.270014374
Short name T309
Test name
Test status
Simulation time 1021618240339 ps
CPU time 451.45 seconds
Started Jul 03 05:06:12 PM PDT 24
Finished Jul 03 05:13:45 PM PDT 24
Peak memory 191304 kb
Host smart-8fb1661f-273c-4b03-b533-869754be0472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270014374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.270014374
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3186411557
Short name T183
Test name
Test status
Simulation time 176914047133 ps
CPU time 26.78 seconds
Started Jul 03 05:06:09 PM PDT 24
Finished Jul 03 05:06:37 PM PDT 24
Peak memory 183116 kb
Host smart-2570e5bf-0b32-4b06-8fa2-7f3fe7d4a2cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186411557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3186411557
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2095498763
Short name T6
Test name
Test status
Simulation time 271816581776 ps
CPU time 341.01 seconds
Started Jul 03 05:06:11 PM PDT 24
Finished Jul 03 05:11:53 PM PDT 24
Peak memory 194732 kb
Host smart-544dbb51-f31a-4de1-8270-185e84f0a09e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095498763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2095498763
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3062919260
Short name T218
Test name
Test status
Simulation time 262407208347 ps
CPU time 688.25 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:17:40 PM PDT 24
Peak memory 191308 kb
Host smart-dc13cdd1-12f6-415c-bda7-77ad74cbabdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062919260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3062919260
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1309229041
Short name T417
Test name
Test status
Simulation time 51054882187 ps
CPU time 86.74 seconds
Started Jul 03 05:06:10 PM PDT 24
Finished Jul 03 05:07:37 PM PDT 24
Peak memory 191300 kb
Host smart-1e4371f2-3799-4b38-aad3-47ba4ef27a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309229041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1309229041
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1890180336
Short name T1
Test name
Test status
Simulation time 249942654556 ps
CPU time 196.24 seconds
Started Jul 03 05:06:16 PM PDT 24
Finished Jul 03 05:09:33 PM PDT 24
Peak memory 191204 kb
Host smart-c38ac96e-2e66-40bc-a45f-400124065e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890180336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1890180336
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2586547445
Short name T292
Test name
Test status
Simulation time 112481336633 ps
CPU time 411.12 seconds
Started Jul 03 05:06:13 PM PDT 24
Finished Jul 03 05:13:05 PM PDT 24
Peak memory 193456 kb
Host smart-ff63313e-7a8c-4382-bffb-4030bb1dd8b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586547445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2586547445
Directory /workspace/99.rv_timer_random/latest
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