Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
129092602 |
1 |
|
T1 |
5994 |
|
T2 |
375574 |
|
T3 |
49211 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
63161357 |
1 |
|
T1 |
5994 |
|
T2 |
6 |
|
T3 |
16200 |
auto[1] |
65931245 |
1 |
|
T2 |
375568 |
|
T3 |
33011 |
|
T4 |
2997 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
129086834 |
1 |
|
T1 |
5990 |
|
T2 |
375564 |
|
T3 |
49205 |
auto[1] |
5768 |
1 |
|
T1 |
4 |
|
T2 |
10 |
|
T3 |
6 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
63158518 |
1 |
|
T1 |
5990 |
|
T2 |
6 |
|
T3 |
16198 |
all_values[0] |
auto[0] |
auto[1] |
2839 |
1 |
|
T1 |
4 |
|
T3 |
2 |
|
T4 |
2 |
all_values[0] |
auto[1] |
auto[0] |
65928316 |
1 |
|
T2 |
375558 |
|
T3 |
33007 |
|
T4 |
2995 |
all_values[0] |
auto[1] |
auto[1] |
2929 |
1 |
|
T2 |
10 |
|
T3 |
4 |
|
T4 |
2 |