Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 573
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T505 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.996565574 Jul 04 05:16:49 PM PDT 24 Jul 04 05:16:50 PM PDT 24 24677287 ps
T506 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1856662636 Jul 04 05:17:03 PM PDT 24 Jul 04 05:17:04 PM PDT 24 33463785 ps
T507 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2092826958 Jul 04 05:16:30 PM PDT 24 Jul 04 05:16:32 PM PDT 24 235888744 ps
T508 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.184336248 Jul 04 05:16:59 PM PDT 24 Jul 04 05:17:00 PM PDT 24 13914524 ps
T509 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.64538892 Jul 04 05:16:40 PM PDT 24 Jul 04 05:16:41 PM PDT 24 36969247 ps
T510 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.335420745 Jul 04 05:16:30 PM PDT 24 Jul 04 05:16:31 PM PDT 24 226279563 ps
T511 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2788868630 Jul 04 05:16:42 PM PDT 24 Jul 04 05:16:45 PM PDT 24 425246339 ps
T512 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.743304507 Jul 04 05:16:29 PM PDT 24 Jul 04 05:16:30 PM PDT 24 29299777 ps
T513 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3843153677 Jul 04 05:16:31 PM PDT 24 Jul 04 05:16:32 PM PDT 24 42013730 ps
T514 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3362141528 Jul 04 05:16:31 PM PDT 24 Jul 04 05:16:32 PM PDT 24 168021733 ps
T515 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1713745603 Jul 04 05:16:30 PM PDT 24 Jul 04 05:16:31 PM PDT 24 22249078 ps
T516 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1626777586 Jul 04 05:16:24 PM PDT 24 Jul 04 05:16:24 PM PDT 24 13672277 ps
T517 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.46672552 Jul 04 05:16:45 PM PDT 24 Jul 04 05:16:46 PM PDT 24 37787354 ps
T518 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1104169932 Jul 04 05:16:30 PM PDT 24 Jul 04 05:16:32 PM PDT 24 34829502 ps
T519 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.804285166 Jul 04 05:16:38 PM PDT 24 Jul 04 05:16:39 PM PDT 24 25727383 ps
T520 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3473057035 Jul 04 05:16:41 PM PDT 24 Jul 04 05:16:43 PM PDT 24 118786263 ps
T521 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.4020357839 Jul 04 05:16:31 PM PDT 24 Jul 04 05:16:32 PM PDT 24 75766184 ps
T522 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3630476437 Jul 04 05:16:52 PM PDT 24 Jul 04 05:16:52 PM PDT 24 44999620 ps
T523 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.445405269 Jul 04 05:16:41 PM PDT 24 Jul 04 05:16:43 PM PDT 24 26171371 ps
T524 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3335639855 Jul 04 05:16:30 PM PDT 24 Jul 04 05:16:31 PM PDT 24 15226227 ps
T525 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1726357513 Jul 04 05:16:40 PM PDT 24 Jul 04 05:16:42 PM PDT 24 218541728 ps
T526 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.125241511 Jul 04 05:16:38 PM PDT 24 Jul 04 05:16:40 PM PDT 24 140331456 ps
T527 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3154548955 Jul 04 05:16:29 PM PDT 24 Jul 04 05:16:30 PM PDT 24 17341212 ps
T528 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3468242409 Jul 04 05:16:39 PM PDT 24 Jul 04 05:16:40 PM PDT 24 89768485 ps
T529 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1777789122 Jul 04 05:16:48 PM PDT 24 Jul 04 05:16:51 PM PDT 24 1195131082 ps
T530 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1320626944 Jul 04 05:16:23 PM PDT 24 Jul 04 05:16:24 PM PDT 24 19799373 ps
T531 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.359714382 Jul 04 05:16:28 PM PDT 24 Jul 04 05:16:30 PM PDT 24 24408103 ps
T532 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3728020861 Jul 04 05:16:29 PM PDT 24 Jul 04 05:16:29 PM PDT 24 73754738 ps
T97 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1443517293 Jul 04 05:16:29 PM PDT 24 Jul 04 05:16:29 PM PDT 24 100864593 ps
T98 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3949677259 Jul 04 05:16:20 PM PDT 24 Jul 04 05:16:22 PM PDT 24 129720190 ps
T533 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1650673731 Jul 04 05:16:48 PM PDT 24 Jul 04 05:16:50 PM PDT 24 236427815 ps
T534 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.62423114 Jul 04 05:17:02 PM PDT 24 Jul 04 05:17:02 PM PDT 24 14491173 ps
T535 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.126379804 Jul 04 05:16:38 PM PDT 24 Jul 04 05:16:40 PM PDT 24 280944503 ps
T536 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.167063173 Jul 04 05:16:40 PM PDT 24 Jul 04 05:16:41 PM PDT 24 54842802 ps
T537 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1178150826 Jul 04 05:16:31 PM PDT 24 Jul 04 05:16:34 PM PDT 24 158588633 ps
T538 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2086921081 Jul 04 05:16:39 PM PDT 24 Jul 04 05:16:41 PM PDT 24 19770891 ps
T539 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1311645710 Jul 04 05:16:47 PM PDT 24 Jul 04 05:16:49 PM PDT 24 31751408 ps
T99 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2217177401 Jul 04 05:16:30 PM PDT 24 Jul 04 05:16:32 PM PDT 24 106530400 ps
T540 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.630795085 Jul 04 05:16:40 PM PDT 24 Jul 04 05:16:41 PM PDT 24 19180325 ps
T541 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1242504947 Jul 04 05:16:48 PM PDT 24 Jul 04 05:16:50 PM PDT 24 61815655 ps
T542 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.331796910 Jul 04 05:16:31 PM PDT 24 Jul 04 05:16:32 PM PDT 24 17410817 ps
T543 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3806292143 Jul 04 05:16:20 PM PDT 24 Jul 04 05:16:21 PM PDT 24 165738530 ps
T544 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2238246912 Jul 04 05:16:22 PM PDT 24 Jul 04 05:16:24 PM PDT 24 39442004 ps
T545 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3408083205 Jul 04 05:16:41 PM PDT 24 Jul 04 05:16:43 PM PDT 24 37502446 ps
T546 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.477627401 Jul 04 05:16:29 PM PDT 24 Jul 04 05:16:30 PM PDT 24 150631111 ps
T547 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4156536384 Jul 04 05:16:48 PM PDT 24 Jul 04 05:16:50 PM PDT 24 34997598 ps
T548 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.571389407 Jul 04 05:16:50 PM PDT 24 Jul 04 05:16:52 PM PDT 24 159427694 ps
T549 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2884781731 Jul 04 05:16:39 PM PDT 24 Jul 04 05:16:40 PM PDT 24 39913943 ps
T550 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1137462475 Jul 04 05:16:39 PM PDT 24 Jul 04 05:16:41 PM PDT 24 28129634 ps
T100 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3267235231 Jul 04 05:16:29 PM PDT 24 Jul 04 05:16:30 PM PDT 24 24792578 ps
T551 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.116071933 Jul 04 05:16:53 PM PDT 24 Jul 04 05:16:53 PM PDT 24 30808040 ps
T552 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2901992591 Jul 04 05:16:23 PM PDT 24 Jul 04 05:16:27 PM PDT 24 319074104 ps
T553 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2442316910 Jul 04 05:16:47 PM PDT 24 Jul 04 05:16:50 PM PDT 24 79560011 ps
T554 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4183599697 Jul 04 05:16:22 PM PDT 24 Jul 04 05:16:25 PM PDT 24 58371328 ps
T555 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3482560559 Jul 04 05:16:37 PM PDT 24 Jul 04 05:16:38 PM PDT 24 25643800 ps
T556 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2625783201 Jul 04 05:16:50 PM PDT 24 Jul 04 05:16:50 PM PDT 24 59286881 ps
T557 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.4049365416 Jul 04 05:16:48 PM PDT 24 Jul 04 05:16:50 PM PDT 24 36367761 ps
T558 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2771886486 Jul 04 05:16:38 PM PDT 24 Jul 04 05:16:40 PM PDT 24 123834251 ps
T559 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2573885902 Jul 04 05:16:50 PM PDT 24 Jul 04 05:16:51 PM PDT 24 59986165 ps
T560 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1215703806 Jul 04 05:16:38 PM PDT 24 Jul 04 05:16:40 PM PDT 24 14262530 ps
T561 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2846117002 Jul 04 05:16:47 PM PDT 24 Jul 04 05:16:49 PM PDT 24 18025902 ps
T562 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2467666987 Jul 04 05:17:01 PM PDT 24 Jul 04 05:17:02 PM PDT 24 15114664 ps
T563 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.282430002 Jul 04 05:16:39 PM PDT 24 Jul 04 05:16:40 PM PDT 24 66665821 ps
T564 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.928606395 Jul 04 05:16:59 PM PDT 24 Jul 04 05:17:00 PM PDT 24 23083420 ps
T565 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.976938603 Jul 04 05:16:43 PM PDT 24 Jul 04 05:16:44 PM PDT 24 67971995 ps
T566 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3725220353 Jul 04 05:16:37 PM PDT 24 Jul 04 05:16:39 PM PDT 24 783519822 ps
T567 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2524114133 Jul 04 05:16:58 PM PDT 24 Jul 04 05:16:59 PM PDT 24 16414745 ps
T568 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2513384969 Jul 04 05:16:48 PM PDT 24 Jul 04 05:16:50 PM PDT 24 29404112 ps
T569 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2673422881 Jul 04 05:16:30 PM PDT 24 Jul 04 05:16:31 PM PDT 24 88498289 ps
T570 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2029576670 Jul 04 05:16:28 PM PDT 24 Jul 04 05:16:29 PM PDT 24 170906239 ps
T571 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.859907990 Jul 04 05:16:58 PM PDT 24 Jul 04 05:16:59 PM PDT 24 33171045 ps
T572 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.945224711 Jul 04 05:16:31 PM PDT 24 Jul 04 05:16:32 PM PDT 24 27352938 ps
T573 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3170346379 Jul 04 05:16:47 PM PDT 24 Jul 04 05:16:48 PM PDT 24 36795481 ps

Test location /workspace/coverage/default/63.rv_timer_random.2239728866
Short name T3
Test name
Test status
Simulation time 356338263033 ps
CPU time 172.92 seconds
Started Jul 04 05:17:54 PM PDT 24
Finished Jul 04 05:20:47 PM PDT 24
Peak memory 191272 kb
Host smart-2219fd29-196c-45c4-aa49-e330438aa24f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239728866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2239728866
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.336357345
Short name T13
Test name
Test status
Simulation time 22137561584 ps
CPU time 233.56 seconds
Started Jul 04 05:17:25 PM PDT 24
Finished Jul 04 05:21:19 PM PDT 24
Peak memory 197740 kb
Host smart-9a8c511b-fca4-4e83-9d70-a297c5fd7b45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336357345 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.336357345
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3161236049
Short name T70
Test name
Test status
Simulation time 1059001185936 ps
CPU time 1824.95 seconds
Started Jul 04 05:17:13 PM PDT 24
Finished Jul 04 05:47:39 PM PDT 24
Peak memory 191308 kb
Host smart-1125df65-f5eb-4155-a076-e35d65f34130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161236049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3161236049
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3028167347
Short name T30
Test name
Test status
Simulation time 409339772 ps
CPU time 1.31 seconds
Started Jul 04 05:16:43 PM PDT 24
Finished Jul 04 05:16:44 PM PDT 24
Peak memory 194904 kb
Host smart-f8e8ec65-a7c4-447d-81cb-5563ba04c4fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028167347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3028167347
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.314394173
Short name T198
Test name
Test status
Simulation time 926653350546 ps
CPU time 2389.25 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:57:05 PM PDT 24
Peak memory 191264 kb
Host smart-73f00379-d9c6-45a7-b4cd-e92054d8ed59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314394173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
314394173
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1950762310
Short name T36
Test name
Test status
Simulation time 1524509661178 ps
CPU time 597.46 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:27:08 PM PDT 24
Peak memory 194032 kb
Host smart-bd12f7d6-2822-4b04-9f09-85c25f8191c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950762310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1950762310
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3437520675
Short name T181
Test name
Test status
Simulation time 2843142579773 ps
CPU time 2988.63 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 06:07:01 PM PDT 24
Peak memory 191260 kb
Host smart-f658da85-d52f-46f5-928d-e61fc175e391
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437520675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3437520675
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_random.2546031244
Short name T120
Test name
Test status
Simulation time 384133358991 ps
CPU time 193.71 seconds
Started Jul 04 05:17:06 PM PDT 24
Finished Jul 04 05:20:20 PM PDT 24
Peak memory 183088 kb
Host smart-b5b16c8b-df34-47c1-b346-290ac437e552
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546031244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2546031244
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2546374707
Short name T186
Test name
Test status
Simulation time 1853054915409 ps
CPU time 2584.07 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 06:00:16 PM PDT 24
Peak memory 191248 kb
Host smart-295f032a-7a3c-4d35-8400-d6dc3f039c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546374707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2546374707
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2419279782
Short name T16
Test name
Test status
Simulation time 170049260 ps
CPU time 0.9 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:17:01 PM PDT 24
Peak memory 214452 kb
Host smart-e307273f-8188-4d73-b579-417df2dbf438
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419279782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2419279782
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.755531099
Short name T194
Test name
Test status
Simulation time 2057696805030 ps
CPU time 5340.06 seconds
Started Jul 04 05:17:26 PM PDT 24
Finished Jul 04 06:46:27 PM PDT 24
Peak memory 196392 kb
Host smart-adf8eb0d-8e36-47ee-95c6-c0e9c411a1d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755531099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
755531099
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1614172960
Short name T73
Test name
Test status
Simulation time 709119584359 ps
CPU time 1373.98 seconds
Started Jul 04 05:17:16 PM PDT 24
Finished Jul 04 05:40:10 PM PDT 24
Peak memory 191288 kb
Host smart-aed13fe6-647d-45ae-bb75-bc68b9aa2529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614172960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1614172960
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1181737030
Short name T152
Test name
Test status
Simulation time 1387533151866 ps
CPU time 1404.71 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:40:59 PM PDT 24
Peak memory 191268 kb
Host smart-445b347a-e50e-49e8-82b5-c2c42247b403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181737030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1181737030
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1348030071
Short name T215
Test name
Test status
Simulation time 485215105603 ps
CPU time 954.87 seconds
Started Jul 04 05:17:14 PM PDT 24
Finished Jul 04 05:33:09 PM PDT 24
Peak memory 191308 kb
Host smart-3b26bca4-4980-4329-a414-d3a276cec3cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348030071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1348030071
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.2258033880
Short name T15
Test name
Test status
Simulation time 74420172889 ps
CPU time 801.88 seconds
Started Jul 04 05:17:29 PM PDT 24
Finished Jul 04 05:30:52 PM PDT 24
Peak memory 209148 kb
Host smart-55cf25f5-9936-4d15-964f-21df0da00638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258033880 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.2258033880
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_random.2088496445
Short name T266
Test name
Test status
Simulation time 207884148890 ps
CPU time 354.83 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:23:28 PM PDT 24
Peak memory 191196 kb
Host smart-791c0d7c-26d3-48d2-bac8-fbd9d90ea7ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088496445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2088496445
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1265965205
Short name T220
Test name
Test status
Simulation time 384147078548 ps
CPU time 1236.09 seconds
Started Jul 04 05:17:32 PM PDT 24
Finished Jul 04 05:38:09 PM PDT 24
Peak memory 191236 kb
Host smart-25a121b7-6687-4110-9170-bc5ddeb93f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265965205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1265965205
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2103024005
Short name T68
Test name
Test status
Simulation time 2031042035257 ps
CPU time 842.89 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:31:04 PM PDT 24
Peak memory 191236 kb
Host smart-3ccec4cd-3072-4af9-b9f7-4cea1782ddec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103024005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2103024005
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_random.2072711747
Short name T252
Test name
Test status
Simulation time 202820881654 ps
CPU time 654.68 seconds
Started Jul 04 05:17:37 PM PDT 24
Finished Jul 04 05:28:32 PM PDT 24
Peak memory 183064 kb
Host smart-30c1ffb2-2b5e-464c-839e-96a055a0d108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072711747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2072711747
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1309463852
Short name T111
Test name
Test status
Simulation time 503951672877 ps
CPU time 637.85 seconds
Started Jul 04 05:18:33 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 191288 kb
Host smart-d8fb5df3-ed88-4003-877d-212e69434819
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309463852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1309463852
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.4118008984
Short name T190
Test name
Test status
Simulation time 1751455048515 ps
CPU time 2882.3 seconds
Started Jul 04 05:17:22 PM PDT 24
Finished Jul 04 06:05:25 PM PDT 24
Peak memory 191264 kb
Host smart-26be50cf-aa9c-4fd7-be39-d3ffb448d385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118008984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.4118008984
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3846285599
Short name T159
Test name
Test status
Simulation time 243582727356 ps
CPU time 279.97 seconds
Started Jul 04 05:17:35 PM PDT 24
Finished Jul 04 05:22:15 PM PDT 24
Peak memory 194728 kb
Host smart-17d266d0-4e98-4c33-9a35-65ea5a9cb5c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846285599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3846285599
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.605140870
Short name T115
Test name
Test status
Simulation time 1096992453239 ps
CPU time 1955.57 seconds
Started Jul 04 05:17:46 PM PDT 24
Finished Jul 04 05:50:22 PM PDT 24
Peak memory 191268 kb
Host smart-535a055b-bf21-4df5-ae96-89c73050577a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605140870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
605140870
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.2316004266
Short name T119
Test name
Test status
Simulation time 599068147470 ps
CPU time 1394.77 seconds
Started Jul 04 05:18:18 PM PDT 24
Finished Jul 04 05:41:33 PM PDT 24
Peak memory 191300 kb
Host smart-130ea155-c423-4188-8747-7d0e54104f3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316004266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2316004266
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.929240149
Short name T299
Test name
Test status
Simulation time 586066040308 ps
CPU time 577.34 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:26:47 PM PDT 24
Peak memory 191020 kb
Host smart-9aa34947-16f4-4402-a3f2-d7dc10cbceee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929240149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.929240149
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3984217836
Short name T226
Test name
Test status
Simulation time 481780972630 ps
CPU time 891.83 seconds
Started Jul 04 05:17:06 PM PDT 24
Finished Jul 04 05:31:58 PM PDT 24
Peak memory 191284 kb
Host smart-c21705b0-55cd-4bad-96c3-2ca8bdaa7cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984217836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3984217836
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.1803332340
Short name T246
Test name
Test status
Simulation time 109662426337 ps
CPU time 345.87 seconds
Started Jul 04 05:18:05 PM PDT 24
Finished Jul 04 05:23:51 PM PDT 24
Peak memory 191276 kb
Host smart-549f264f-2ff5-41f9-b2fd-6fced0184d39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803332340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1803332340
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3978662878
Short name T228
Test name
Test status
Simulation time 145010748533 ps
CPU time 609.83 seconds
Started Jul 04 05:18:13 PM PDT 24
Finished Jul 04 05:28:23 PM PDT 24
Peak memory 191280 kb
Host smart-82812997-d22d-4f79-a7e9-0d5ee8e18039
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978662878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3978662878
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.1027098561
Short name T259
Test name
Test status
Simulation time 286088796311 ps
CPU time 147.23 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:19:28 PM PDT 24
Peak memory 191288 kb
Host smart-aede5388-eb90-4966-ac12-842f5a8d5ac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027098561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1027098561
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random.1254513623
Short name T201
Test name
Test status
Simulation time 1056646225184 ps
CPU time 534.73 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:26:29 PM PDT 24
Peak memory 191240 kb
Host smart-ded11027-16ba-422e-84c3-5c3beb8dce0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254513623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1254513623
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.581741553
Short name T193
Test name
Test status
Simulation time 164127961467 ps
CPU time 269.85 seconds
Started Jul 04 05:17:47 PM PDT 24
Finished Jul 04 05:22:17 PM PDT 24
Peak memory 191276 kb
Host smart-36b80d60-4fb5-4946-982a-b5f5bc156612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581741553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.581741553
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3283925264
Short name T224
Test name
Test status
Simulation time 98330920216 ps
CPU time 415.57 seconds
Started Jul 04 05:17:56 PM PDT 24
Finished Jul 04 05:24:52 PM PDT 24
Peak memory 194832 kb
Host smart-e32122e5-c976-4cba-9c2f-86bca46c12a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283925264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3283925264
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1602842354
Short name T101
Test name
Test status
Simulation time 291392975 ps
CPU time 2.67 seconds
Started Jul 04 05:16:32 PM PDT 24
Finished Jul 04 05:16:35 PM PDT 24
Peak memory 182356 kb
Host smart-1852adef-e47f-402d-805c-38844c875491
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602842354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1602842354
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1224905739
Short name T191
Test name
Test status
Simulation time 240996787584 ps
CPU time 2440.71 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:57:52 PM PDT 24
Peak memory 194896 kb
Host smart-b02aab8d-44c8-40db-9184-69535bef3dc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224905739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1224905739
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/195.rv_timer_random.2369234312
Short name T58
Test name
Test status
Simulation time 199279776228 ps
CPU time 865.96 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:33:26 PM PDT 24
Peak memory 191280 kb
Host smart-a4eeeea9-8397-416f-bb30-50af871c3bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369234312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2369234312
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.3729713410
Short name T276
Test name
Test status
Simulation time 311210568191 ps
CPU time 457.63 seconds
Started Jul 04 05:17:16 PM PDT 24
Finished Jul 04 05:24:54 PM PDT 24
Peak memory 194628 kb
Host smart-0bf8cb69-b869-4259-bea6-7db7dec953d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729713410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3729713410
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2628426079
Short name T197
Test name
Test status
Simulation time 844266509050 ps
CPU time 4032.02 seconds
Started Jul 04 05:17:35 PM PDT 24
Finished Jul 04 06:24:48 PM PDT 24
Peak memory 191252 kb
Host smart-5be8ddae-e271-452d-8220-69c0a0a316ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628426079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2628426079
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2652506618
Short name T129
Test name
Test status
Simulation time 1213991617305 ps
CPU time 377.59 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:23:52 PM PDT 24
Peak memory 183020 kb
Host smart-a14d87e8-422b-49b0-8a5a-757492347b16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652506618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2652506618
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/84.rv_timer_random.3254240296
Short name T166
Test name
Test status
Simulation time 278298046696 ps
CPU time 1002.13 seconds
Started Jul 04 05:18:03 PM PDT 24
Finished Jul 04 05:34:45 PM PDT 24
Peak memory 191264 kb
Host smart-29f680d9-ef78-4cac-9863-74e2567a68e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254240296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3254240296
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.4232087638
Short name T142
Test name
Test status
Simulation time 873447268219 ps
CPU time 578.68 seconds
Started Jul 04 05:18:12 PM PDT 24
Finished Jul 04 05:27:51 PM PDT 24
Peak memory 191264 kb
Host smart-9024d7b9-4808-470d-b8fc-1c79975977b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232087638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.4232087638
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1854077737
Short name T188
Test name
Test status
Simulation time 644350870845 ps
CPU time 279.17 seconds
Started Jul 04 05:18:13 PM PDT 24
Finished Jul 04 05:22:52 PM PDT 24
Peak memory 194928 kb
Host smart-b839e493-4bbb-411c-8409-4f0a5dc56538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854077737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1854077737
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.779214253
Short name T229
Test name
Test status
Simulation time 701500025803 ps
CPU time 671.06 seconds
Started Jul 04 05:18:40 PM PDT 24
Finished Jul 04 05:29:52 PM PDT 24
Peak memory 191172 kb
Host smart-3808c48e-f439-4cbe-8992-e52564917b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779214253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.779214253
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.1303131571
Short name T335
Test name
Test status
Simulation time 452457403043 ps
CPU time 773.66 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:30:28 PM PDT 24
Peak memory 191272 kb
Host smart-4cb16442-1eb6-4fda-9ff9-aea3d249183d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303131571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.1303131571
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2029242428
Short name T22
Test name
Test status
Simulation time 621877338626 ps
CPU time 294.48 seconds
Started Jul 04 05:17:57 PM PDT 24
Finished Jul 04 05:22:52 PM PDT 24
Peak memory 191256 kb
Host smart-70a029a5-479a-46d0-b011-3740a93ff1af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029242428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2029242428
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.186656070
Short name T239
Test name
Test status
Simulation time 147819471744 ps
CPU time 666.39 seconds
Started Jul 04 05:18:14 PM PDT 24
Finished Jul 04 05:29:21 PM PDT 24
Peak memory 191240 kb
Host smart-08b77d57-a415-41e4-907a-e5dfe894d64e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186656070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.186656070
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.4107329413
Short name T324
Test name
Test status
Simulation time 338910394403 ps
CPU time 499.07 seconds
Started Jul 04 05:18:17 PM PDT 24
Finished Jul 04 05:26:37 PM PDT 24
Peak memory 191300 kb
Host smart-fbde9f13-ec2e-4dbe-9c1e-38d9b5542cb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107329413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.4107329413
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3772000076
Short name T237
Test name
Test status
Simulation time 593445925615 ps
CPU time 438.51 seconds
Started Jul 04 05:18:22 PM PDT 24
Finished Jul 04 05:25:41 PM PDT 24
Peak memory 191284 kb
Host smart-37ce9a61-59be-4c54-a4a8-49ebb61c5a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772000076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3772000076
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3133154404
Short name T437
Test name
Test status
Simulation time 316925877605 ps
CPU time 553.73 seconds
Started Jul 04 05:18:31 PM PDT 24
Finished Jul 04 05:27:45 PM PDT 24
Peak memory 191200 kb
Host smart-6b74a073-e78e-4426-91fc-484a783a79d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133154404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3133154404
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1495364907
Short name T306
Test name
Test status
Simulation time 122683007958 ps
CPU time 115.55 seconds
Started Jul 04 05:18:31 PM PDT 24
Finished Jul 04 05:20:27 PM PDT 24
Peak memory 191288 kb
Host smart-d7229787-5e68-4f64-88be-528ad1f205a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495364907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1495364907
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.751215420
Short name T25
Test name
Test status
Simulation time 78141069216 ps
CPU time 243 seconds
Started Jul 04 05:18:39 PM PDT 24
Finished Jul 04 05:22:43 PM PDT 24
Peak memory 191276 kb
Host smart-25322d02-af76-4859-a9eb-0a41695dd2d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751215420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.751215420
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.856981233
Short name T169
Test name
Test status
Simulation time 814261936870 ps
CPU time 1706.08 seconds
Started Jul 04 05:18:39 PM PDT 24
Finished Jul 04 05:47:05 PM PDT 24
Peak memory 191204 kb
Host smart-29041d8c-08d2-43df-97f7-edee67fb537f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856981233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.856981233
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.207624562
Short name T251
Test name
Test status
Simulation time 113196346196 ps
CPU time 762.86 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:31:42 PM PDT 24
Peak memory 195684 kb
Host smart-8e5a6a44-c276-40e8-9550-9a4194beacc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207624562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.207624562
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2547273994
Short name T295
Test name
Test status
Simulation time 1066887889384 ps
CPU time 585.08 seconds
Started Jul 04 05:17:24 PM PDT 24
Finished Jul 04 05:27:09 PM PDT 24
Peak memory 183056 kb
Host smart-cba4427a-4781-460b-9a31-4674093d4246
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547273994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2547273994
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1165557418
Short name T202
Test name
Test status
Simulation time 487086289176 ps
CPU time 772.89 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:30:26 PM PDT 24
Peak memory 191268 kb
Host smart-4e5843c4-b555-411b-97dc-edee75feb9f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165557418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1165557418
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.76332463
Short name T51
Test name
Test status
Simulation time 39550444 ps
CPU time 0.82 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 193076 kb
Host smart-af7dfd39-60ab-4f09-b53f-f14b94ce31bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76332463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_time
r_same_csr_outstanding.76332463
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/103.rv_timer_random.3326359297
Short name T250
Test name
Test status
Simulation time 184857387590 ps
CPU time 59.79 seconds
Started Jul 04 05:18:14 PM PDT 24
Finished Jul 04 05:19:14 PM PDT 24
Peak memory 183040 kb
Host smart-e0983f87-27bb-4559-8a12-25b5247c2f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326359297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3326359297
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.713495868
Short name T282
Test name
Test status
Simulation time 246859046222 ps
CPU time 476.6 seconds
Started Jul 04 05:18:18 PM PDT 24
Finished Jul 04 05:26:14 PM PDT 24
Peak memory 191300 kb
Host smart-e124d6bd-be6f-46fd-817b-5e6d1de9ab6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713495868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.713495868
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1138140291
Short name T44
Test name
Test status
Simulation time 87274693277 ps
CPU time 445.57 seconds
Started Jul 04 05:17:13 PM PDT 24
Finished Jul 04 05:24:40 PM PDT 24
Peak memory 191200 kb
Host smart-a0932801-813c-4aa9-be7f-0e3c6eb015b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138140291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1138140291
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1127466709
Short name T320
Test name
Test status
Simulation time 178892775622 ps
CPU time 174.25 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:20:05 PM PDT 24
Peak memory 191260 kb
Host smart-e95fcb00-96b9-472d-8591-09da56a97acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127466709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1127466709
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.1193524949
Short name T344
Test name
Test status
Simulation time 477812178017 ps
CPU time 264.56 seconds
Started Jul 04 05:18:23 PM PDT 24
Finished Jul 04 05:22:48 PM PDT 24
Peak memory 191288 kb
Host smart-f276cd69-0e6d-4ad2-bd39-ff3973b0a11e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193524949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1193524949
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.4217601166
Short name T167
Test name
Test status
Simulation time 162449056982 ps
CPU time 307.76 seconds
Started Jul 04 05:18:23 PM PDT 24
Finished Jul 04 05:23:31 PM PDT 24
Peak memory 191276 kb
Host smart-cf8d8dd9-6138-4e36-a3cb-18331be63d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217601166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4217601166
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.2995720648
Short name T222
Test name
Test status
Simulation time 903612442511 ps
CPU time 352.3 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:23:03 PM PDT 24
Peak memory 191288 kb
Host smart-08d8a5bf-14ae-41d1-8c25-24875908283f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995720648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2995720648
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1358046679
Short name T114
Test name
Test status
Simulation time 1193988337975 ps
CPU time 908.91 seconds
Started Jul 04 05:17:12 PM PDT 24
Finished Jul 04 05:32:21 PM PDT 24
Peak memory 191248 kb
Host smart-c026007a-d8b6-4f79-82b6-97c3cef3d4d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358046679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1358046679
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/137.rv_timer_random.2686233854
Short name T196
Test name
Test status
Simulation time 99518741156 ps
CPU time 1683.89 seconds
Started Jul 04 05:18:31 PM PDT 24
Finished Jul 04 05:46:36 PM PDT 24
Peak memory 191296 kb
Host smart-924c1d3c-1f9a-4d2e-8203-9e29f42e6e84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686233854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2686233854
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2993627245
Short name T268
Test name
Test status
Simulation time 1015379275158 ps
CPU time 398.59 seconds
Started Jul 04 05:18:33 PM PDT 24
Finished Jul 04 05:25:12 PM PDT 24
Peak memory 191192 kb
Host smart-b52d67d4-1b14-435e-812d-5ae17c180469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993627245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2993627245
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3206434825
Short name T264
Test name
Test status
Simulation time 898134473427 ps
CPU time 758.86 seconds
Started Jul 04 05:18:40 PM PDT 24
Finished Jul 04 05:31:19 PM PDT 24
Peak memory 191272 kb
Host smart-e586caf6-e382-48d3-89e1-fa60e988766e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206434825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3206434825
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.1205315567
Short name T157
Test name
Test status
Simulation time 83191615924 ps
CPU time 1654.45 seconds
Started Jul 04 05:17:14 PM PDT 24
Finished Jul 04 05:44:49 PM PDT 24
Peak memory 191264 kb
Host smart-bf20eddd-5cf8-4bde-915f-1ea3a1b3bdc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205315567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1205315567
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2061163309
Short name T253
Test name
Test status
Simulation time 125891364741 ps
CPU time 218.93 seconds
Started Jul 04 05:18:39 PM PDT 24
Finished Jul 04 05:22:19 PM PDT 24
Peak memory 191276 kb
Host smart-c5ca9c76-5eb0-41f9-9e55-c44e84526449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061163309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2061163309
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.577587302
Short name T270
Test name
Test status
Simulation time 306067624416 ps
CPU time 649.96 seconds
Started Jul 04 05:18:49 PM PDT 24
Finished Jul 04 05:29:39 PM PDT 24
Peak memory 191276 kb
Host smart-629a9d27-7157-4095-acc1-6c95761465b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577587302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.577587302
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3566862977
Short name T262
Test name
Test status
Simulation time 151351754924 ps
CPU time 320.12 seconds
Started Jul 04 05:17:47 PM PDT 24
Finished Jul 04 05:23:07 PM PDT 24
Peak memory 192260 kb
Host smart-9a17ec6a-dc9e-4bfc-94bb-2ada48caa8f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566862977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3566862977
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2344172885
Short name T283
Test name
Test status
Simulation time 120631677005 ps
CPU time 122.33 seconds
Started Jul 04 05:17:55 PM PDT 24
Finished Jul 04 05:19:58 PM PDT 24
Peak memory 193388 kb
Host smart-5e1acb39-3f8b-4995-9d56-144a055016eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344172885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2344172885
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3895722928
Short name T236
Test name
Test status
Simulation time 265354029099 ps
CPU time 122.52 seconds
Started Jul 04 05:18:04 PM PDT 24
Finished Jul 04 05:20:07 PM PDT 24
Peak memory 191296 kb
Host smart-0f07af20-d4b4-4344-930d-5627a5da7e46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895722928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3895722928
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.155543656
Short name T318
Test name
Test status
Simulation time 800629859749 ps
CPU time 508.02 seconds
Started Jul 04 05:18:02 PM PDT 24
Finished Jul 04 05:26:30 PM PDT 24
Peak memory 191296 kb
Host smart-48ba8659-faf8-4453-9643-0f62386c048d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155543656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.155543656
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3291971002
Short name T503
Test name
Test status
Simulation time 402279393 ps
CPU time 1.37 seconds
Started Jul 04 05:16:20 PM PDT 24
Finished Jul 04 05:16:22 PM PDT 24
Peak memory 182652 kb
Host smart-e794f8af-5fbc-47c1-84af-0e5348fbdc25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291971002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3291971002
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.768785937
Short name T82
Test name
Test status
Simulation time 32936152713 ps
CPU time 58.26 seconds
Started Jul 04 05:16:58 PM PDT 24
Finished Jul 04 05:17:56 PM PDT 24
Peak memory 191284 kb
Host smart-b33454bc-0b6d-466f-96d4-0c4c47ac8461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768785937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.768785937
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3185468134
Short name T287
Test name
Test status
Simulation time 575985829207 ps
CPU time 96.11 seconds
Started Jul 04 05:18:19 PM PDT 24
Finished Jul 04 05:19:55 PM PDT 24
Peak memory 191296 kb
Host smart-1a5ab3b3-63ef-4d8f-beb4-04d3f4d660ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185468134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3185468134
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2275054031
Short name T146
Test name
Test status
Simulation time 123318514906 ps
CPU time 70.28 seconds
Started Jul 04 05:18:22 PM PDT 24
Finished Jul 04 05:19:33 PM PDT 24
Peak memory 191300 kb
Host smart-2b3d90a0-fffb-4fc3-953e-85b1d3eff00e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275054031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2275054031
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2160124493
Short name T148
Test name
Test status
Simulation time 109900822245 ps
CPU time 131.02 seconds
Started Jul 04 05:18:35 PM PDT 24
Finished Jul 04 05:20:46 PM PDT 24
Peak memory 191280 kb
Host smart-3daa5faa-613d-4010-9928-74e67c0ea6a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160124493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2160124493
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.523051404
Short name T310
Test name
Test status
Simulation time 53116705936 ps
CPU time 474.78 seconds
Started Jul 04 05:18:34 PM PDT 24
Finished Jul 04 05:26:29 PM PDT 24
Peak memory 193564 kb
Host smart-a263f930-c74c-405b-8e7b-7983aa0c9128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523051404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.523051404
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.583479435
Short name T227
Test name
Test status
Simulation time 98059808793 ps
CPU time 126.74 seconds
Started Jul 04 05:18:32 PM PDT 24
Finished Jul 04 05:20:39 PM PDT 24
Peak memory 191172 kb
Host smart-6a409598-6ba0-40ad-aae9-3de7dc61a229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583479435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.583479435
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3347386475
Short name T84
Test name
Test status
Simulation time 2304449512983 ps
CPU time 383.99 seconds
Started Jul 04 05:18:32 PM PDT 24
Finished Jul 04 05:24:56 PM PDT 24
Peak memory 191280 kb
Host smart-920a0003-0b05-4292-b332-735a5c728f6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347386475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3347386475
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.2165939460
Short name T330
Test name
Test status
Simulation time 129908189197 ps
CPU time 200.85 seconds
Started Jul 04 05:18:40 PM PDT 24
Finished Jul 04 05:22:01 PM PDT 24
Peak memory 191288 kb
Host smart-be6383ad-a5c3-45d5-8148-acab90359bb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165939460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.2165939460
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.277917137
Short name T163
Test name
Test status
Simulation time 102012627046 ps
CPU time 87.44 seconds
Started Jul 04 05:18:43 PM PDT 24
Finished Jul 04 05:20:10 PM PDT 24
Peak memory 191296 kb
Host smart-fcc6c275-714f-43e7-8c94-be53d74fad88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277917137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.277917137
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1810793799
Short name T134
Test name
Test status
Simulation time 427919274349 ps
CPU time 693.89 seconds
Started Jul 04 05:18:43 PM PDT 24
Finished Jul 04 05:30:17 PM PDT 24
Peak memory 191296 kb
Host smart-3396a86c-2c8e-422a-9f18-e3e6f0eab0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810793799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1810793799
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.1835585411
Short name T130
Test name
Test status
Simulation time 112341523209 ps
CPU time 1836.76 seconds
Started Jul 04 05:18:39 PM PDT 24
Finished Jul 04 05:49:16 PM PDT 24
Peak memory 193712 kb
Host smart-36d6a61d-2668-4c47-b58a-a4ec367698d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835585411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1835585411
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1520741704
Short name T216
Test name
Test status
Simulation time 129840905204 ps
CPU time 263.89 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:23:23 PM PDT 24
Peak memory 191268 kb
Host smart-c4ce5154-fe25-4751-b8f3-8915b566ff62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520741704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1520741704
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.2711918622
Short name T243
Test name
Test status
Simulation time 499246157615 ps
CPU time 258.49 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:21:28 PM PDT 24
Peak memory 191288 kb
Host smart-1a7ece23-c655-492b-905b-ff05bb7e8256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711918622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2711918622
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random.1160395421
Short name T2
Test name
Test status
Simulation time 480740271035 ps
CPU time 454.71 seconds
Started Jul 04 05:17:13 PM PDT 24
Finished Jul 04 05:24:49 PM PDT 24
Peak memory 191296 kb
Host smart-c656f858-5c49-4ca9-abdd-0af65b32d445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160395421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1160395421
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.4251556262
Short name T204
Test name
Test status
Simulation time 87948849647 ps
CPU time 1284.21 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:38:40 PM PDT 24
Peak memory 191268 kb
Host smart-f22aa632-c5fc-4323-b0d5-5d77c1ffdfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251556262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.4251556262
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_random.602790001
Short name T161
Test name
Test status
Simulation time 6566245270 ps
CPU time 11.57 seconds
Started Jul 04 05:17:24 PM PDT 24
Finished Jul 04 05:17:36 PM PDT 24
Peak memory 183036 kb
Host smart-3709be6f-83f5-4f4b-8d0b-544cf7b3d4d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602790001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.602790001
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3252431302
Short name T173
Test name
Test status
Simulation time 37822591371 ps
CPU time 42.94 seconds
Started Jul 04 05:16:58 PM PDT 24
Finished Jul 04 05:17:41 PM PDT 24
Peak memory 191280 kb
Host smart-4c4accdb-5a2c-4373-afe4-3e59277a9694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252431302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3252431302
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_random.522317173
Short name T192
Test name
Test status
Simulation time 69832991714 ps
CPU time 272.46 seconds
Started Jul 04 05:17:30 PM PDT 24
Finished Jul 04 05:22:03 PM PDT 24
Peak memory 191256 kb
Host smart-2f12d5ba-7ba5-4d55-8ddb-70b3cf6484f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522317173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.522317173
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random.3648411603
Short name T8
Test name
Test status
Simulation time 38642876725 ps
CPU time 37.43 seconds
Started Jul 04 05:17:40 PM PDT 24
Finished Jul 04 05:18:17 PM PDT 24
Peak memory 183048 kb
Host smart-f4c10ef5-68e7-4d10-aa29-d1877ade239b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648411603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3648411603
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.39630996
Short name T131
Test name
Test status
Simulation time 118887249612 ps
CPU time 353.54 seconds
Started Jul 04 05:17:54 PM PDT 24
Finished Jul 04 05:23:48 PM PDT 24
Peak memory 191292 kb
Host smart-1930e920-dbe5-4cf7-9287-c014d26895ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39630996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.39630996
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.883915691
Short name T312
Test name
Test status
Simulation time 197097610600 ps
CPU time 546.44 seconds
Started Jul 04 05:18:04 PM PDT 24
Finished Jul 04 05:27:11 PM PDT 24
Peak memory 191272 kb
Host smart-0c620608-a902-4e00-bb26-7604934144b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883915691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.883915691
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3011753670
Short name T284
Test name
Test status
Simulation time 109183288114 ps
CPU time 666.88 seconds
Started Jul 04 05:18:05 PM PDT 24
Finished Jul 04 05:29:12 PM PDT 24
Peak memory 191272 kb
Host smart-a834cc10-3773-493b-970f-f8600834f8ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011753670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3011753670
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1320626944
Short name T530
Test name
Test status
Simulation time 19799373 ps
CPU time 0.65 seconds
Started Jul 04 05:16:23 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 182232 kb
Host smart-d9bff1ba-5544-4c5a-8e20-f8a52f721d5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320626944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1320626944
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3949677259
Short name T98
Test name
Test status
Simulation time 129720190 ps
CPU time 1.56 seconds
Started Jul 04 05:16:20 PM PDT 24
Finished Jul 04 05:16:22 PM PDT 24
Peak memory 182372 kb
Host smart-d29d1439-bae8-4e84-9541-66f5f70df4b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949677259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3949677259
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3907365409
Short name T95
Test name
Test status
Simulation time 15385945 ps
CPU time 0.6 seconds
Started Jul 04 05:16:21 PM PDT 24
Finished Jul 04 05:16:22 PM PDT 24
Peak memory 182264 kb
Host smart-4bffae09-11ba-47a9-9dad-b6cc8195faa1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907365409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3907365409
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1807689807
Short name T493
Test name
Test status
Simulation time 15456899 ps
CPU time 0.7 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 193848 kb
Host smart-9d5e3488-21f4-44af-8c8e-6256cd0319fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807689807 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1807689807
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3362843579
Short name T55
Test name
Test status
Simulation time 15753764 ps
CPU time 0.57 seconds
Started Jul 04 05:16:21 PM PDT 24
Finished Jul 04 05:16:22 PM PDT 24
Peak memory 182224 kb
Host smart-999afe6a-0241-41c2-b6c6-6d9385bb5db2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362843579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3362843579
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3289824415
Short name T442
Test name
Test status
Simulation time 18571665 ps
CPU time 0.54 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 182172 kb
Host smart-2eff3a89-580c-4dc7-91fd-9c2e4ab6347d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289824415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3289824415
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2923595515
Short name T501
Test name
Test status
Simulation time 74403502 ps
CPU time 1.49 seconds
Started Jul 04 05:16:23 PM PDT 24
Finished Jul 04 05:16:25 PM PDT 24
Peak memory 197044 kb
Host smart-748fc3c0-28b2-45fb-85ae-8fbf263e498d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923595515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2923595515
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3226705431
Short name T454
Test name
Test status
Simulation time 13743031 ps
CPU time 0.62 seconds
Started Jul 04 05:16:20 PM PDT 24
Finished Jul 04 05:16:22 PM PDT 24
Peak memory 182256 kb
Host smart-3f97093b-0939-45c1-8dac-e9fe880fe35a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226705431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3226705431
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2901992591
Short name T552
Test name
Test status
Simulation time 319074104 ps
CPU time 3.34 seconds
Started Jul 04 05:16:23 PM PDT 24
Finished Jul 04 05:16:27 PM PDT 24
Peak memory 182408 kb
Host smart-bd413f46-5753-4b5d-a67f-26b5a4459eac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901992591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2901992591
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.196837049
Short name T53
Test name
Test status
Simulation time 51568416 ps
CPU time 0.54 seconds
Started Jul 04 05:16:24 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 182248 kb
Host smart-9a88be5a-0c3d-42cd-9a83-d0601e039b7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196837049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.196837049
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3968261788
Short name T502
Test name
Test status
Simulation time 349501841 ps
CPU time 1.3 seconds
Started Jul 04 05:16:23 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 197052 kb
Host smart-be67cd1c-69e8-44ec-a8ad-4bc12d1ef3b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968261788 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3968261788
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1626777586
Short name T516
Test name
Test status
Simulation time 13672277 ps
CPU time 0.55 seconds
Started Jul 04 05:16:24 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 182080 kb
Host smart-a60fd1bf-f11d-4db3-badb-33c47cc623d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626777586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1626777586
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2424181620
Short name T496
Test name
Test status
Simulation time 28987666 ps
CPU time 0.54 seconds
Started Jul 04 05:16:23 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 182064 kb
Host smart-8bc45039-4e0c-44b6-97f5-38f090ab7b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424181620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2424181620
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2173689599
Short name T35
Test name
Test status
Simulation time 151307971 ps
CPU time 0.8 seconds
Started Jul 04 05:16:20 PM PDT 24
Finished Jul 04 05:16:21 PM PDT 24
Peak memory 192976 kb
Host smart-c44eb99a-eb19-4b92-a68d-fdb108ea4378
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173689599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2173689599
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.112530156
Short name T468
Test name
Test status
Simulation time 40107620 ps
CPU time 1.06 seconds
Started Jul 04 05:16:20 PM PDT 24
Finished Jul 04 05:16:21 PM PDT 24
Peak memory 196840 kb
Host smart-0069c3d6-cba7-4e92-9665-ebfbc976a230
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112530156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.112530156
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3806292143
Short name T543
Test name
Test status
Simulation time 165738530 ps
CPU time 1.14 seconds
Started Jul 04 05:16:20 PM PDT 24
Finished Jul 04 05:16:21 PM PDT 24
Peak memory 193780 kb
Host smart-3661d45c-28b8-4ca2-9f6d-9dfbce1f291e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806292143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3806292143
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3408083205
Short name T545
Test name
Test status
Simulation time 37502446 ps
CPU time 1.72 seconds
Started Jul 04 05:16:41 PM PDT 24
Finished Jul 04 05:16:43 PM PDT 24
Peak memory 197068 kb
Host smart-da791ea6-db78-4c31-8c49-70139ff8a2ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408083205 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3408083205
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3662658365
Short name T453
Test name
Test status
Simulation time 25804359 ps
CPU time 0.56 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 182216 kb
Host smart-234cf021-4517-44aa-811d-0b81836479af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662658365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3662658365
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.282430002
Short name T563
Test name
Test status
Simulation time 66665821 ps
CPU time 0.55 seconds
Started Jul 04 05:16:39 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 182192 kb
Host smart-2572c31d-4637-4069-851d-24c34eb26c05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282430002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.282430002
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.1634625554
Short name T499
Test name
Test status
Simulation time 30891995 ps
CPU time 0.66 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 191120 kb
Host smart-d3ef58a2-75e7-4da1-a1f5-d022daca2833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634625554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.1634625554
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.125241511
Short name T526
Test name
Test status
Simulation time 140331456 ps
CPU time 2.01 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 197048 kb
Host smart-634d7b39-05b6-4999-a2a9-155ba5fc789e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125241511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.125241511
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.525529235
Short name T108
Test name
Test status
Simulation time 184873189 ps
CPU time 1.36 seconds
Started Jul 04 05:16:39 PM PDT 24
Finished Jul 04 05:16:41 PM PDT 24
Peak memory 182932 kb
Host smart-51f2dca6-082e-44f3-b0cc-78905f0bbe0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525529235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_in
tg_err.525529235
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3981999892
Short name T478
Test name
Test status
Simulation time 72788625 ps
CPU time 0.98 seconds
Started Jul 04 05:16:39 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 196932 kb
Host smart-a19e1a4e-263b-425b-8a43-0f52de20a6fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981999892 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3981999892
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4114251182
Short name T52
Test name
Test status
Simulation time 48986707 ps
CPU time 0.56 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 182188 kb
Host smart-1e0cf677-0e05-4898-9267-9f12b700c364
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114251182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4114251182
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.996382834
Short name T460
Test name
Test status
Simulation time 13235287 ps
CPU time 0.54 seconds
Started Jul 04 05:16:41 PM PDT 24
Finished Jul 04 05:16:42 PM PDT 24
Peak memory 181568 kb
Host smart-ce13dbe9-2bf0-415b-aca2-1e4c961303af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996382834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.996382834
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3803476215
Short name T54
Test name
Test status
Simulation time 20945951 ps
CPU time 0.62 seconds
Started Jul 04 05:16:39 PM PDT 24
Finished Jul 04 05:16:41 PM PDT 24
Peak memory 190992 kb
Host smart-134878a9-9599-41a0-9e8c-a961863230e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803476215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3803476215
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3473057035
Short name T520
Test name
Test status
Simulation time 118786263 ps
CPU time 1.73 seconds
Started Jul 04 05:16:41 PM PDT 24
Finished Jul 04 05:16:43 PM PDT 24
Peak memory 197016 kb
Host smart-1a994dbd-6f74-4b3b-98b0-6ee86c03fc43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473057035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3473057035
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3132729046
Short name T504
Test name
Test status
Simulation time 21420902 ps
CPU time 0.66 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 194044 kb
Host smart-87dcc7b1-82dd-481b-b528-950c4d4541ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132729046 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3132729046
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.779080408
Short name T96
Test name
Test status
Simulation time 89392895 ps
CPU time 0.57 seconds
Started Jul 04 05:16:41 PM PDT 24
Finished Jul 04 05:16:42 PM PDT 24
Peak memory 182216 kb
Host smart-37257bf5-f6a6-4f27-906c-2eac23a08508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779080408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.779080408
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.804285166
Short name T519
Test name
Test status
Simulation time 25727383 ps
CPU time 0.56 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 182072 kb
Host smart-96899e4d-4f85-4237-8cae-a0d251786a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804285166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.804285166
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1137462475
Short name T550
Test name
Test status
Simulation time 28129634 ps
CPU time 0.71 seconds
Started Jul 04 05:16:39 PM PDT 24
Finished Jul 04 05:16:41 PM PDT 24
Peak memory 191216 kb
Host smart-e248d1ac-977a-445d-b07f-a6f18f6ca2c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137462475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1137462475
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1151735951
Short name T469
Test name
Test status
Simulation time 257022610 ps
CPU time 1.55 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 197024 kb
Host smart-c9af992d-d494-4c69-b0c2-07afe801d061
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151735951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1151735951
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3658656561
Short name T66
Test name
Test status
Simulation time 214054637 ps
CPU time 1.09 seconds
Started Jul 04 05:16:37 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 194516 kb
Host smart-6fb9c21e-2919-4665-9692-022ba8692ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658656561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3658656561
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.597296602
Short name T456
Test name
Test status
Simulation time 30752871 ps
CPU time 0.79 seconds
Started Jul 04 05:16:42 PM PDT 24
Finished Jul 04 05:16:43 PM PDT 24
Peak memory 195628 kb
Host smart-997e7215-4755-4e48-91a8-12ccd7b85676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597296602 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.597296602
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3468242409
Short name T528
Test name
Test status
Simulation time 89768485 ps
CPU time 0.57 seconds
Started Jul 04 05:16:39 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 182124 kb
Host smart-29830144-dbba-4df6-899d-995719f488b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468242409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3468242409
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3788599265
Short name T458
Test name
Test status
Simulation time 33146738 ps
CPU time 0.53 seconds
Started Jul 04 05:16:39 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 182144 kb
Host smart-cc874025-452e-4cf1-9adf-e566b4b232d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788599265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3788599265
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.630795085
Short name T540
Test name
Test status
Simulation time 19180325 ps
CPU time 0.63 seconds
Started Jul 04 05:16:40 PM PDT 24
Finished Jul 04 05:16:41 PM PDT 24
Peak memory 191456 kb
Host smart-fdacc61f-6b17-482f-85cc-1f0dc91473a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630795085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.630795085
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3017285770
Short name T473
Test name
Test status
Simulation time 694900806 ps
CPU time 2.95 seconds
Started Jul 04 05:16:40 PM PDT 24
Finished Jul 04 05:16:43 PM PDT 24
Peak memory 197024 kb
Host smart-8a9d5767-55cd-4d76-ba36-33e413599136
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017285770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3017285770
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2022670543
Short name T32
Test name
Test status
Simulation time 339789940 ps
CPU time 1.07 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 194672 kb
Host smart-7ef9e190-a6ed-4ebe-b217-047d20ebc73e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022670543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2022670543
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2536413288
Short name T39
Test name
Test status
Simulation time 78196521 ps
CPU time 1.04 seconds
Started Jul 04 05:16:50 PM PDT 24
Finished Jul 04 05:16:51 PM PDT 24
Peak memory 196848 kb
Host smart-dd912208-99d7-44c1-9885-a7dae4b4a2da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536413288 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2536413288
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2884781731
Short name T549
Test name
Test status
Simulation time 39913943 ps
CPU time 0.55 seconds
Started Jul 04 05:16:39 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 182120 kb
Host smart-5855521d-94ec-48c4-a46c-00b71f1543ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884781731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2884781731
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2902997753
Short name T444
Test name
Test status
Simulation time 47367428 ps
CPU time 0.52 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 181616 kb
Host smart-00c365db-2a58-43a4-bd72-4b481aaac9ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902997753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2902997753
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.220670689
Short name T102
Test name
Test status
Simulation time 32128754 ps
CPU time 0.8 seconds
Started Jul 04 05:16:40 PM PDT 24
Finished Jul 04 05:16:41 PM PDT 24
Peak memory 193024 kb
Host smart-fb09b8aa-e4b2-4edc-a3b8-f62f7cc532a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220670689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.220670689
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.126379804
Short name T535
Test name
Test status
Simulation time 280944503 ps
CPU time 2 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 197080 kb
Host smart-8e251012-a86b-487e-a3c2-fefd3d3bbcdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126379804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.126379804
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2771886486
Short name T558
Test name
Test status
Simulation time 123834251 ps
CPU time 1.34 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 194600 kb
Host smart-c3f324c2-e3d9-4e68-a902-0e24eb0a4765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771886486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2771886486
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1270798658
Short name T56
Test name
Test status
Simulation time 67314257 ps
CPU time 0.63 seconds
Started Jul 04 05:16:45 PM PDT 24
Finished Jul 04 05:16:45 PM PDT 24
Peak memory 192876 kb
Host smart-a94edaad-9947-4e0d-89de-c7cbc4b4eba5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270798658 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1270798658
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.153644952
Short name T486
Test name
Test status
Simulation time 24629237 ps
CPU time 0.58 seconds
Started Jul 04 05:16:50 PM PDT 24
Finished Jul 04 05:16:51 PM PDT 24
Peak memory 182256 kb
Host smart-2f1b0a97-ce4f-496c-b1a5-a35990378f90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153644952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.153644952
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2573885902
Short name T559
Test name
Test status
Simulation time 59986165 ps
CPU time 0.55 seconds
Started Jul 04 05:16:50 PM PDT 24
Finished Jul 04 05:16:51 PM PDT 24
Peak memory 182096 kb
Host smart-73c1a5ad-da71-436b-9e95-0b67638b29a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573885902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2573885902
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1135915179
Short name T495
Test name
Test status
Simulation time 48195091 ps
CPU time 0.66 seconds
Started Jul 04 05:16:51 PM PDT 24
Finished Jul 04 05:16:52 PM PDT 24
Peak memory 191188 kb
Host smart-c59375c3-bbef-480e-824c-1a58056d55f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135915179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1135915179
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1580599980
Short name T40
Test name
Test status
Simulation time 169626149 ps
CPU time 1.11 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 196528 kb
Host smart-ae3669c5-01b1-451a-8af9-6e88765e274f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580599980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1580599980
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1667402529
Short name T487
Test name
Test status
Simulation time 186555169 ps
CPU time 0.84 seconds
Started Jul 04 05:16:49 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 193188 kb
Host smart-11fc52bc-2094-4873-82d6-afaeef590a0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667402529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1667402529
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1201967528
Short name T477
Test name
Test status
Simulation time 25552858 ps
CPU time 0.81 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 195456 kb
Host smart-87c64505-7a45-402b-bd63-8cd728efa1e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201967528 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1201967528
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3298737495
Short name T462
Test name
Test status
Simulation time 24068295 ps
CPU time 0.58 seconds
Started Jul 04 05:16:53 PM PDT 24
Finished Jul 04 05:16:54 PM PDT 24
Peak memory 182232 kb
Host smart-b293dd92-c6ae-4d83-8ec0-96a97c26bd93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298737495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3298737495
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.4049365416
Short name T557
Test name
Test status
Simulation time 36367761 ps
CPU time 0.57 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 182140 kb
Host smart-9c45a723-b94f-4bb0-98c1-56c631776d52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049365416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.4049365416
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.46672552
Short name T517
Test name
Test status
Simulation time 37787354 ps
CPU time 0.83 seconds
Started Jul 04 05:16:45 PM PDT 24
Finished Jul 04 05:16:46 PM PDT 24
Peak memory 193008 kb
Host smart-8f1ab2bf-b0aa-4c3c-8d24-d02e0dd947d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46672552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_tim
er_same_csr_outstanding.46672552
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2442316910
Short name T553
Test name
Test status
Simulation time 79560011 ps
CPU time 1.94 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 197028 kb
Host smart-54dca79a-c82a-4bc6-b894-255100c9c5e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442316910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2442316910
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1650673731
Short name T533
Test name
Test status
Simulation time 236427815 ps
CPU time 1.35 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 194924 kb
Host smart-3cd51ce3-b176-4d10-a49b-85a33f5cf9e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650673731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1650673731
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.625994723
Short name T494
Test name
Test status
Simulation time 27067565 ps
CPU time 0.71 seconds
Started Jul 04 05:16:46 PM PDT 24
Finished Jul 04 05:16:47 PM PDT 24
Peak memory 194584 kb
Host smart-459a2989-73a8-48d0-a948-7ac2a05556a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625994723 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.625994723
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2835408644
Short name T466
Test name
Test status
Simulation time 26090092 ps
CPU time 0.57 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:48 PM PDT 24
Peak memory 182196 kb
Host smart-d0dc4a8e-2e38-444e-835f-21319225cd72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835408644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2835408644
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1760961927
Short name T459
Test name
Test status
Simulation time 31308154 ps
CPU time 0.55 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 182160 kb
Host smart-8513c771-a913-499e-8452-497e35cada88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760961927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1760961927
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1309913141
Short name T105
Test name
Test status
Simulation time 35542048 ps
CPU time 0.74 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 192868 kb
Host smart-9629cd14-b7ee-445e-8edf-1055f6ba61c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309913141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1309913141
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1777789122
Short name T529
Test name
Test status
Simulation time 1195131082 ps
CPU time 2 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:51 PM PDT 24
Peak memory 197008 kb
Host smart-02d28887-44b3-4842-be4a-b7757ead9fee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777789122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1777789122
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2989989672
Short name T109
Test name
Test status
Simulation time 630007413 ps
CPU time 1.32 seconds
Started Jul 04 05:16:45 PM PDT 24
Finished Jul 04 05:16:47 PM PDT 24
Peak memory 194896 kb
Host smart-cf248959-8ec2-435f-ad99-0b1e065b4ed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989989672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2989989672
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1311645710
Short name T539
Test name
Test status
Simulation time 31751408 ps
CPU time 0.76 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 194444 kb
Host smart-6b4288fd-34c6-4b82-b600-e9dc4f689966
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311645710 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1311645710
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2846117002
Short name T561
Test name
Test status
Simulation time 18025902 ps
CPU time 0.58 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 182272 kb
Host smart-ce5ca9c2-ea92-4af6-88ea-b0ff8296837f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846117002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2846117002
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4141107785
Short name T476
Test name
Test status
Simulation time 36264159 ps
CPU time 0.58 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:48 PM PDT 24
Peak memory 181596 kb
Host smart-0816afde-b1fc-42dd-98dd-e9491249010e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141107785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.4141107785
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1692090219
Short name T33
Test name
Test status
Simulation time 14822194 ps
CPU time 0.67 seconds
Started Jul 04 05:16:54 PM PDT 24
Finished Jul 04 05:16:55 PM PDT 24
Peak memory 191556 kb
Host smart-c5603759-7c60-419c-bab6-a477fa1dbeea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692090219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1692090219
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1113020816
Short name T474
Test name
Test status
Simulation time 434782678 ps
CPU time 2.64 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:52 PM PDT 24
Peak memory 196952 kb
Host smart-eaa1f8ab-e9d7-4f68-bc9b-963aa7eb2a34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113020816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1113020816
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.571389407
Short name T548
Test name
Test status
Simulation time 159427694 ps
CPU time 1.04 seconds
Started Jul 04 05:16:50 PM PDT 24
Finished Jul 04 05:16:52 PM PDT 24
Peak memory 182716 kb
Host smart-ac8851ae-ac86-4faf-99d4-1f65980f1461
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571389407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.571389407
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3630476437
Short name T522
Test name
Test status
Simulation time 44999620 ps
CPU time 0.67 seconds
Started Jul 04 05:16:52 PM PDT 24
Finished Jul 04 05:16:52 PM PDT 24
Peak memory 193660 kb
Host smart-7b6faff6-b84d-4890-8ba9-6f941fbe0dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630476437 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3630476437
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1242504947
Short name T541
Test name
Test status
Simulation time 61815655 ps
CPU time 0.59 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 182268 kb
Host smart-28e701c8-947d-4b78-bc56-e8d0bfc4e2be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242504947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1242504947
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3170346379
Short name T573
Test name
Test status
Simulation time 36795481 ps
CPU time 0.53 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:48 PM PDT 24
Peak memory 181644 kb
Host smart-4a0cc7dd-931e-4f36-bf1c-090096e4726f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170346379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3170346379
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1983156068
Short name T103
Test name
Test status
Simulation time 19356115 ps
CPU time 0.62 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:48 PM PDT 24
Peak memory 190976 kb
Host smart-14bd12dc-eb78-4404-a139-6ba508870220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983156068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1983156068
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.348407728
Short name T485
Test name
Test status
Simulation time 580484707 ps
CPU time 2.64 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:52 PM PDT 24
Peak memory 197004 kb
Host smart-da9a2b42-95bd-414c-8299-ebb136ffe73b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348407728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.348407728
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.955765377
Short name T470
Test name
Test status
Simulation time 174101850 ps
CPU time 0.81 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 193264 kb
Host smart-72915b83-4ebd-4fa5-9ad7-8e0f1e025e74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955765377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.955765377
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1203420328
Short name T491
Test name
Test status
Simulation time 21301734 ps
CPU time 0.63 seconds
Started Jul 04 05:16:32 PM PDT 24
Finished Jul 04 05:16:33 PM PDT 24
Peak memory 182248 kb
Host smart-5a39770a-e854-4184-9c7f-e25a3e30f761
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203420328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1203420328
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3154548955
Short name T527
Test name
Test status
Simulation time 17341212 ps
CPU time 0.59 seconds
Started Jul 04 05:16:29 PM PDT 24
Finished Jul 04 05:16:30 PM PDT 24
Peak memory 191412 kb
Host smart-82899e62-eaad-42d8-b469-7c0777bce015
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154548955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3154548955
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3335639855
Short name T524
Test name
Test status
Simulation time 15226227 ps
CPU time 0.65 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 193052 kb
Host smart-6a355c7a-bfd2-4512-8ae0-79ad7d9ac727
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335639855 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3335639855
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3267235231
Short name T100
Test name
Test status
Simulation time 24792578 ps
CPU time 0.59 seconds
Started Jul 04 05:16:29 PM PDT 24
Finished Jul 04 05:16:30 PM PDT 24
Peak memory 182272 kb
Host smart-556b0e0f-7910-49ec-867c-1fc9d4554508
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267235231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3267235231
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.4018501992
Short name T483
Test name
Test status
Simulation time 12940361 ps
CPU time 0.55 seconds
Started Jul 04 05:16:20 PM PDT 24
Finished Jul 04 05:16:21 PM PDT 24
Peak memory 182120 kb
Host smart-dfd1ca0d-16cf-4b16-9f4f-07f6ff0d2e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018501992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.4018501992
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2296628740
Short name T34
Test name
Test status
Simulation time 53245778 ps
CPU time 0.74 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 192752 kb
Host smart-9cea49f5-1145-4efd-b703-0607881a24d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296628740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2296628740
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4183599697
Short name T554
Test name
Test status
Simulation time 58371328 ps
CPU time 2.81 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:16:25 PM PDT 24
Peak memory 197056 kb
Host smart-3147fc57-ea30-4487-aff3-7870e0f09e10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183599697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4183599697
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2238246912
Short name T544
Test name
Test status
Simulation time 39442004 ps
CPU time 0.84 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 193196 kb
Host smart-d2cac203-87b2-4141-85b8-1f199fdf676c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238246912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2238246912
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2513384969
Short name T568
Test name
Test status
Simulation time 29404112 ps
CPU time 0.6 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 182164 kb
Host smart-510da403-e3fb-4769-9521-fb1cdb867982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513384969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2513384969
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.159272456
Short name T481
Test name
Test status
Simulation time 62754932 ps
CPU time 0.57 seconds
Started Jul 04 05:16:54 PM PDT 24
Finished Jul 04 05:16:55 PM PDT 24
Peak memory 182156 kb
Host smart-212dbce6-6f42-4e7a-a7ea-514e66a97d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159272456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.159272456
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1203600206
Short name T475
Test name
Test status
Simulation time 39544528 ps
CPU time 0.54 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:48 PM PDT 24
Peak memory 182172 kb
Host smart-99cceabc-7e2d-4cf9-b613-83573aa50591
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203600206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1203600206
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.996565574
Short name T505
Test name
Test status
Simulation time 24677287 ps
CPU time 0.55 seconds
Started Jul 04 05:16:49 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 182136 kb
Host smart-c7abd4b7-95c0-4538-bf32-786f19b1ab06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996565574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.996565574
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2653223021
Short name T461
Test name
Test status
Simulation time 11617446 ps
CPU time 0.54 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 181620 kb
Host smart-2aba9f07-b696-4ae6-9f23-e9e2c776147c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653223021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2653223021
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2283799227
Short name T443
Test name
Test status
Simulation time 54086072 ps
CPU time 0.55 seconds
Started Jul 04 05:16:50 PM PDT 24
Finished Jul 04 05:16:51 PM PDT 24
Peak memory 182100 kb
Host smart-862ae3e4-70ff-4dba-bbce-dae029956542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283799227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2283799227
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.4156536384
Short name T547
Test name
Test status
Simulation time 34997598 ps
CPU time 0.53 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 181832 kb
Host smart-82146a5f-5239-4b13-bd45-a147d83aba29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156536384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.4156536384
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3610842165
Short name T455
Test name
Test status
Simulation time 73798157 ps
CPU time 0.52 seconds
Started Jul 04 05:16:52 PM PDT 24
Finished Jul 04 05:16:52 PM PDT 24
Peak memory 181660 kb
Host smart-8233f2a3-a4ff-4bce-b969-ea8b13f303fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610842165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3610842165
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1338919298
Short name T449
Test name
Test status
Simulation time 37207809 ps
CPU time 0.55 seconds
Started Jul 04 05:16:47 PM PDT 24
Finished Jul 04 05:16:48 PM PDT 24
Peak memory 182116 kb
Host smart-6d350c28-c144-488a-9b9d-2b86050877a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338919298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1338919298
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4124497772
Short name T482
Test name
Test status
Simulation time 16098598 ps
CPU time 0.63 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 182164 kb
Host smart-570d1ca7-69f3-4f64-91da-16f048aacf3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124497772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4124497772
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2217177401
Short name T99
Test name
Test status
Simulation time 106530400 ps
CPU time 0.7 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 191836 kb
Host smart-623b2c45-2d58-4e88-91e9-ed5e4c0a44bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217177401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2217177401
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1882462227
Short name T451
Test name
Test status
Simulation time 276714340 ps
CPU time 3.42 seconds
Started Jul 04 05:16:33 PM PDT 24
Finished Jul 04 05:16:37 PM PDT 24
Peak memory 190620 kb
Host smart-47f6b3c9-4999-4397-86f4-c616dc4ba67f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882462227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1882462227
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3728020861
Short name T532
Test name
Test status
Simulation time 73754738 ps
CPU time 0.55 seconds
Started Jul 04 05:16:29 PM PDT 24
Finished Jul 04 05:16:29 PM PDT 24
Peak memory 182184 kb
Host smart-dab13ee3-daa9-40e3-9786-4c0c967c0b6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728020861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3728020861
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.743304507
Short name T512
Test name
Test status
Simulation time 29299777 ps
CPU time 0.8 seconds
Started Jul 04 05:16:29 PM PDT 24
Finished Jul 04 05:16:30 PM PDT 24
Peak memory 195744 kb
Host smart-2038c24e-7327-4c34-bdf8-c4d70bad60a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743304507 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.743304507
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.331796910
Short name T542
Test name
Test status
Simulation time 17410817 ps
CPU time 0.56 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 182204 kb
Host smart-978f94d7-5df7-42fb-af71-259b31879f22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331796910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.331796910
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.945224711
Short name T572
Test name
Test status
Simulation time 27352938 ps
CPU time 0.54 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 182176 kb
Host smart-5ab9c31d-5b7b-4590-8bf5-4e94f35c0322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945224711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.945224711
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3362141528
Short name T514
Test name
Test status
Simulation time 168021733 ps
CPU time 0.63 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 191584 kb
Host smart-a4b00adb-d833-4686-9083-02a62f18bdf0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362141528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3362141528
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1713745603
Short name T515
Test name
Test status
Simulation time 22249078 ps
CPU time 1.13 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 197036 kb
Host smart-42b771fd-359f-49c1-b8fd-b48e0d65905c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713745603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1713745603
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.461304499
Short name T110
Test name
Test status
Simulation time 330257000 ps
CPU time 1.02 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 182636 kb
Host smart-c8975c8d-432e-4f14-8622-8dca974bd1ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461304499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.461304499
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3957743706
Short name T472
Test name
Test status
Simulation time 14156911 ps
CPU time 0.56 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 182148 kb
Host smart-f86ebb5a-8d20-4fb3-8d5d-593ed1c3e5c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957743706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3957743706
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.116071933
Short name T551
Test name
Test status
Simulation time 30808040 ps
CPU time 0.55 seconds
Started Jul 04 05:16:53 PM PDT 24
Finished Jul 04 05:16:53 PM PDT 24
Peak memory 182152 kb
Host smart-2b9cb02f-f1c0-4a47-8dd3-707bba84fe4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116071933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.116071933
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2625783201
Short name T556
Test name
Test status
Simulation time 59286881 ps
CPU time 0.56 seconds
Started Jul 04 05:16:50 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 182080 kb
Host smart-b3100610-df56-4406-b8de-4c0e6b66691d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625783201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2625783201
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3634431168
Short name T450
Test name
Test status
Simulation time 16642794 ps
CPU time 0.57 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 181644 kb
Host smart-6359826f-213b-47f0-a88e-48a15294254f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634431168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3634431168
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.819811047
Short name T480
Test name
Test status
Simulation time 28399200 ps
CPU time 0.57 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:49 PM PDT 24
Peak memory 182100 kb
Host smart-2fe88c22-b4a5-412e-a1de-4981706fdeb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819811047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.819811047
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.1411733385
Short name T490
Test name
Test status
Simulation time 16517101 ps
CPU time 0.58 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 182180 kb
Host smart-5721e636-9128-450a-b149-e8faa1864a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411733385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.1411733385
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3810228100
Short name T488
Test name
Test status
Simulation time 37452687 ps
CPU time 0.51 seconds
Started Jul 04 05:16:49 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 181592 kb
Host smart-cff8bc84-6161-4e02-a749-444c170bc445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810228100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3810228100
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3727771971
Short name T500
Test name
Test status
Simulation time 50839628 ps
CPU time 0.57 seconds
Started Jul 04 05:16:48 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 182128 kb
Host smart-48cf74db-f37d-4f6f-9510-739c9d260f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727771971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3727771971
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3565832264
Short name T471
Test name
Test status
Simulation time 32582966 ps
CPU time 0.59 seconds
Started Jul 04 05:17:07 PM PDT 24
Finished Jul 04 05:17:08 PM PDT 24
Peak memory 182124 kb
Host smart-11b89f9f-9a6a-4eb2-85cb-d4d4002c1641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565832264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3565832264
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.859907990
Short name T571
Test name
Test status
Simulation time 33171045 ps
CPU time 0.55 seconds
Started Jul 04 05:16:58 PM PDT 24
Finished Jul 04 05:16:59 PM PDT 24
Peak memory 182200 kb
Host smart-e2badcc0-19e4-4a6b-9221-13396d4cc58c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859907990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.859907990
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.335420745
Short name T510
Test name
Test status
Simulation time 226279563 ps
CPU time 0.71 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 182220 kb
Host smart-86449411-e276-4a1d-941c-87f2f945a63d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335420745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.335420745
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.85395169
Short name T107
Test name
Test status
Simulation time 192711057 ps
CPU time 2.46 seconds
Started Jul 04 05:16:29 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 182348 kb
Host smart-d33cdb29-15e9-40af-9980-6b4d13f9be18
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85395169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_ba
sh.85395169
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3928121518
Short name T94
Test name
Test status
Simulation time 15122048 ps
CPU time 0.54 seconds
Started Jul 04 05:16:29 PM PDT 24
Finished Jul 04 05:16:30 PM PDT 24
Peak memory 182220 kb
Host smart-e7f638fd-6982-468a-8010-1acd8cfdfba4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928121518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3928121518
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1619847678
Short name T479
Test name
Test status
Simulation time 70211625 ps
CPU time 0.62 seconds
Started Jul 04 05:16:33 PM PDT 24
Finished Jul 04 05:16:34 PM PDT 24
Peak memory 193212 kb
Host smart-b8aad3e6-99d5-4f8f-b399-d64bda75e1a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619847678 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1619847678
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.1358840787
Short name T489
Test name
Test status
Simulation time 25385395 ps
CPU time 0.51 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 182048 kb
Host smart-cce2bea1-4f52-40bd-ac27-0698c83d667c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358840787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.1358840787
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2057209893
Short name T448
Test name
Test status
Simulation time 13999611 ps
CPU time 0.56 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 182208 kb
Host smart-101033dd-a4ca-4a74-9211-d9fa87d9922b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057209893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2057209893
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1104169932
Short name T518
Test name
Test status
Simulation time 34829502 ps
CPU time 0.8 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 191216 kb
Host smart-f293f3c7-b526-4e7c-9706-724d2dfbf029
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104169932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1104169932
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2092826958
Short name T507
Test name
Test status
Simulation time 235888744 ps
CPU time 1.24 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 197100 kb
Host smart-a3df228f-fd4a-4745-8cbe-b4052ffe0d49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092826958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2092826958
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2673422881
Short name T569
Test name
Test status
Simulation time 88498289 ps
CPU time 1.09 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 194712 kb
Host smart-194b24b6-5a42-430a-a49d-0cb333e753b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673422881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2673422881
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.227473454
Short name T464
Test name
Test status
Simulation time 36566557 ps
CPU time 0.53 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:17:01 PM PDT 24
Peak memory 182132 kb
Host smart-d5bf440d-cac1-4ab2-b4af-5516e3f86d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227473454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.227473454
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.4096802984
Short name T452
Test name
Test status
Simulation time 18725669 ps
CPU time 0.57 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:17:00 PM PDT 24
Peak memory 181552 kb
Host smart-114f2e6e-280f-41a9-aa4f-aafefe636223
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096802984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.4096802984
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.62423114
Short name T534
Test name
Test status
Simulation time 14491173 ps
CPU time 0.57 seconds
Started Jul 04 05:17:02 PM PDT 24
Finished Jul 04 05:17:02 PM PDT 24
Peak memory 182116 kb
Host smart-7227b0c4-b4b9-4678-825c-76c0b4062623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62423114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.62423114
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.928606395
Short name T564
Test name
Test status
Simulation time 23083420 ps
CPU time 0.57 seconds
Started Jul 04 05:16:59 PM PDT 24
Finished Jul 04 05:17:00 PM PDT 24
Peak memory 182108 kb
Host smart-2b149efc-31f3-4545-9073-c8b4dd1a3391
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928606395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.928606395
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.184336248
Short name T508
Test name
Test status
Simulation time 13914524 ps
CPU time 0.61 seconds
Started Jul 04 05:16:59 PM PDT 24
Finished Jul 04 05:17:00 PM PDT 24
Peak memory 181636 kb
Host smart-8b4deb9a-5d36-4b26-accf-f8a47ccc8355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184336248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.184336248
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3690779599
Short name T445
Test name
Test status
Simulation time 51681407 ps
CPU time 0.57 seconds
Started Jul 04 05:16:59 PM PDT 24
Finished Jul 04 05:17:00 PM PDT 24
Peak memory 182168 kb
Host smart-c8810df0-3e64-448a-9ccf-ba2fee8c639c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690779599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3690779599
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1856662636
Short name T506
Test name
Test status
Simulation time 33463785 ps
CPU time 0.55 seconds
Started Jul 04 05:17:03 PM PDT 24
Finished Jul 04 05:17:04 PM PDT 24
Peak memory 182132 kb
Host smart-e184a071-c5cf-406e-89b2-e140663137a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856662636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1856662636
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.3985210927
Short name T447
Test name
Test status
Simulation time 42180856 ps
CPU time 0.55 seconds
Started Jul 04 05:16:59 PM PDT 24
Finished Jul 04 05:16:59 PM PDT 24
Peak memory 182196 kb
Host smart-b55596bb-a8c3-4e20-96bb-5430abcc6fe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985210927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.3985210927
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2524114133
Short name T567
Test name
Test status
Simulation time 16414745 ps
CPU time 0.53 seconds
Started Jul 04 05:16:58 PM PDT 24
Finished Jul 04 05:16:59 PM PDT 24
Peak memory 182140 kb
Host smart-03c78a31-9356-4c81-937b-48ea748962a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524114133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2524114133
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2467666987
Short name T562
Test name
Test status
Simulation time 15114664 ps
CPU time 0.59 seconds
Started Jul 04 05:17:01 PM PDT 24
Finished Jul 04 05:17:02 PM PDT 24
Peak memory 182096 kb
Host smart-f1ad2398-b074-4b5d-b368-ff923c89978d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467666987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2467666987
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2029576670
Short name T570
Test name
Test status
Simulation time 170906239 ps
CPU time 0.84 seconds
Started Jul 04 05:16:28 PM PDT 24
Finished Jul 04 05:16:29 PM PDT 24
Peak memory 196888 kb
Host smart-c6aa58be-c143-424d-8887-fcd17bc7a5c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029576670 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2029576670
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3141458407
Short name T446
Test name
Test status
Simulation time 14827531 ps
CPU time 0.54 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 182000 kb
Host smart-acd70489-5371-4643-b14b-31952da3d7bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141458407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3141458407
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3089810279
Short name T498
Test name
Test status
Simulation time 17531709 ps
CPU time 0.55 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 181784 kb
Host smart-d2b7d1ad-a137-478c-82d1-27fc50ef67bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089810279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3089810279
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2948826629
Short name T106
Test name
Test status
Simulation time 31419935 ps
CPU time 0.59 seconds
Started Jul 04 05:16:29 PM PDT 24
Finished Jul 04 05:16:30 PM PDT 24
Peak memory 190860 kb
Host smart-641f5a74-d581-4ff5-84ee-7a8b29d4e5e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948826629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2948826629
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.359714382
Short name T531
Test name
Test status
Simulation time 24408103 ps
CPU time 1.17 seconds
Started Jul 04 05:16:28 PM PDT 24
Finished Jul 04 05:16:30 PM PDT 24
Peak memory 197044 kb
Host smart-512826f6-4e09-4624-b711-0f5e7d3c7ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359714382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.359714382
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3119100070
Short name T31
Test name
Test status
Simulation time 321402336 ps
CPU time 1.29 seconds
Started Jul 04 05:16:29 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 194740 kb
Host smart-59d03eb0-ba3f-4786-b088-84636838fbc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119100070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3119100070
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1333081728
Short name T457
Test name
Test status
Simulation time 21813038 ps
CPU time 1.06 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:33 PM PDT 24
Peak memory 196844 kb
Host smart-b1136883-4f1d-402e-b6e0-f94a294c9c34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333081728 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1333081728
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.694975749
Short name T463
Test name
Test status
Simulation time 38250521 ps
CPU time 0.58 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 182024 kb
Host smart-37a4666c-bb75-4a49-aeaf-f4a569af98a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694975749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.694975749
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3843153677
Short name T513
Test name
Test status
Simulation time 42013730 ps
CPU time 0.53 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 182156 kb
Host smart-1cdc938d-b4a5-440b-8445-ede92a293ab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843153677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3843153677
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.477627401
Short name T546
Test name
Test status
Simulation time 150631111 ps
CPU time 0.82 seconds
Started Jul 04 05:16:29 PM PDT 24
Finished Jul 04 05:16:30 PM PDT 24
Peak memory 192896 kb
Host smart-34dbd985-7c4d-4380-a491-53204c261c27
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477627401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.477627401
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.394742720
Short name T465
Test name
Test status
Simulation time 171512379 ps
CPU time 1.17 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:33 PM PDT 24
Peak memory 196872 kb
Host smart-b00c8d46-70c1-483e-a08f-0748097f3447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394742720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.394742720
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2922799173
Short name T497
Test name
Test status
Simulation time 223854807 ps
CPU time 1.36 seconds
Started Jul 04 05:16:30 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 195080 kb
Host smart-eeac301e-d6e2-4107-baa0-95d15eca267b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922799173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2922799173
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3262578188
Short name T467
Test name
Test status
Simulation time 28019748 ps
CPU time 1.19 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:33 PM PDT 24
Peak memory 197028 kb
Host smart-6f4ac5b3-5e82-46c5-a9d6-d767e3364954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262578188 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3262578188
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1443517293
Short name T97
Test name
Test status
Simulation time 100864593 ps
CPU time 0.52 seconds
Started Jul 04 05:16:29 PM PDT 24
Finished Jul 04 05:16:29 PM PDT 24
Peak memory 182008 kb
Host smart-a5ab23a7-d252-469b-87a9-d4fd5afbbdb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443517293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1443517293
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.110293273
Short name T492
Test name
Test status
Simulation time 25836454 ps
CPU time 0.55 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 182128 kb
Host smart-3c84969f-3ccb-4e68-be27-ad9d5566be4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110293273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.110293273
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.4020357839
Short name T521
Test name
Test status
Simulation time 75766184 ps
CPU time 0.78 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:32 PM PDT 24
Peak memory 191200 kb
Host smart-c37613cd-c7c9-40c5-8a5b-01713333abce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020357839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.4020357839
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1178150826
Short name T537
Test name
Test status
Simulation time 158588633 ps
CPU time 2.13 seconds
Started Jul 04 05:16:31 PM PDT 24
Finished Jul 04 05:16:34 PM PDT 24
Peak memory 196976 kb
Host smart-fd5893a5-648d-48f4-b451-89d3c20920b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178150826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1178150826
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3865188309
Short name T484
Test name
Test status
Simulation time 202725170 ps
CPU time 0.86 seconds
Started Jul 04 05:16:28 PM PDT 24
Finished Jul 04 05:16:29 PM PDT 24
Peak memory 182736 kb
Host smart-669ddfcb-5289-4baf-9c21-ddf957665944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865188309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3865188309
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.445405269
Short name T523
Test name
Test status
Simulation time 26171371 ps
CPU time 1.22 seconds
Started Jul 04 05:16:41 PM PDT 24
Finished Jul 04 05:16:43 PM PDT 24
Peak memory 197048 kb
Host smart-e9859b14-e5ca-4a4a-8173-b64fbe65c4ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445405269 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.445405269
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.167063173
Short name T536
Test name
Test status
Simulation time 54842802 ps
CPU time 0.65 seconds
Started Jul 04 05:16:40 PM PDT 24
Finished Jul 04 05:16:41 PM PDT 24
Peak memory 191424 kb
Host smart-c9fb4a82-000a-40be-9141-a55ab0af104d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167063173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.167063173
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2086921081
Short name T538
Test name
Test status
Simulation time 19770891 ps
CPU time 0.56 seconds
Started Jul 04 05:16:39 PM PDT 24
Finished Jul 04 05:16:41 PM PDT 24
Peak memory 182124 kb
Host smart-402ddd60-c5de-431f-b132-d4c45c316c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086921081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2086921081
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1215703806
Short name T560
Test name
Test status
Simulation time 14262530 ps
CPU time 0.65 seconds
Started Jul 04 05:16:38 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 190804 kb
Host smart-38a40dce-9f71-4d2e-b3e7-b50119d0a1da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215703806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1215703806
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1461901275
Short name T41
Test name
Test status
Simulation time 40728491 ps
CPU time 2.11 seconds
Started Jul 04 05:16:40 PM PDT 24
Finished Jul 04 05:16:43 PM PDT 24
Peak memory 197028 kb
Host smart-f6a404a3-57a2-426e-b91e-265e3a33bf77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461901275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1461901275
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.976938603
Short name T565
Test name
Test status
Simulation time 67971995 ps
CPU time 1.07 seconds
Started Jul 04 05:16:43 PM PDT 24
Finished Jul 04 05:16:44 PM PDT 24
Peak memory 182952 kb
Host smart-7cc395bf-b02a-4bcd-a832-3987b436931e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976938603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.976938603
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1726357513
Short name T525
Test name
Test status
Simulation time 218541728 ps
CPU time 1.16 seconds
Started Jul 04 05:16:40 PM PDT 24
Finished Jul 04 05:16:42 PM PDT 24
Peak memory 196792 kb
Host smart-61de4f03-6118-418f-83bd-d4ae803ef674
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726357513 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1726357513
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3482560559
Short name T555
Test name
Test status
Simulation time 25643800 ps
CPU time 0.54 seconds
Started Jul 04 05:16:37 PM PDT 24
Finished Jul 04 05:16:38 PM PDT 24
Peak memory 182188 kb
Host smart-21d69951-1131-45ee-a4ce-a919b90d1915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482560559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3482560559
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.64538892
Short name T509
Test name
Test status
Simulation time 36969247 ps
CPU time 0.54 seconds
Started Jul 04 05:16:40 PM PDT 24
Finished Jul 04 05:16:41 PM PDT 24
Peak memory 182100 kb
Host smart-93555de6-fbe2-4fb0-a916-bda196fb8f3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64538892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.64538892
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2076237769
Short name T104
Test name
Test status
Simulation time 92894718 ps
CPU time 0.72 seconds
Started Jul 04 05:16:41 PM PDT 24
Finished Jul 04 05:16:42 PM PDT 24
Peak memory 192896 kb
Host smart-e94c6efe-92bb-432b-a67a-360f01a9af4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076237769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2076237769
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2788868630
Short name T511
Test name
Test status
Simulation time 425246339 ps
CPU time 2.08 seconds
Started Jul 04 05:16:42 PM PDT 24
Finished Jul 04 05:16:45 PM PDT 24
Peak memory 197052 kb
Host smart-c9882bdf-25aa-47fa-ba18-376dc6a1dce4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788868630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2788868630
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.3725220353
Short name T566
Test name
Test status
Simulation time 783519822 ps
CPU time 1.38 seconds
Started Jul 04 05:16:37 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 194588 kb
Host smart-57176e93-dbac-4730-95e7-ebbdf102d357
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725220353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.3725220353
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.765538040
Short name T156
Test name
Test status
Simulation time 19261549988 ps
CPU time 30.62 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:17:31 PM PDT 24
Peak memory 183092 kb
Host smart-00dd6156-ede4-422a-aa57-6e5d7466467a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765538040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.765538040
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.303030971
Short name T62
Test name
Test status
Simulation time 50664004553 ps
CPU time 78.15 seconds
Started Jul 04 05:16:58 PM PDT 24
Finished Jul 04 05:18:17 PM PDT 24
Peak memory 183040 kb
Host smart-8c9afa61-4242-4235-916a-ee742639557b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303030971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.303030971
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1464477987
Short name T221
Test name
Test status
Simulation time 128935185160 ps
CPU time 110.56 seconds
Started Jul 04 05:17:01 PM PDT 24
Finished Jul 04 05:18:52 PM PDT 24
Peak memory 183036 kb
Host smart-d66f63be-8358-4d8c-a310-849ea80704bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464477987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1464477987
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1688005555
Short name T273
Test name
Test status
Simulation time 253361991669 ps
CPU time 150.22 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:19:31 PM PDT 24
Peak memory 182984 kb
Host smart-68717c89-7330-40af-a405-3ddd0bced4ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688005555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1688005555
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.287735309
Short name T408
Test name
Test status
Simulation time 91502598122 ps
CPU time 117.38 seconds
Started Jul 04 05:16:58 PM PDT 24
Finished Jul 04 05:18:56 PM PDT 24
Peak memory 182996 kb
Host smart-3188bd53-0d6c-4f0f-836a-5d3dd30bdae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287735309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.287735309
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.786548753
Short name T376
Test name
Test status
Simulation time 64868629597 ps
CPU time 29.93 seconds
Started Jul 04 05:16:58 PM PDT 24
Finished Jul 04 05:17:28 PM PDT 24
Peak memory 183080 kb
Host smart-4dce2dfd-37fb-464e-a778-232d5c5a0b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786548753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.786548753
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2915409485
Short name T18
Test name
Test status
Simulation time 250568522 ps
CPU time 0.86 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:17:01 PM PDT 24
Peak memory 213428 kb
Host smart-74b08898-ba95-4f10-85cc-44e134723242
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915409485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2915409485
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3365041402
Short name T168
Test name
Test status
Simulation time 1280723980569 ps
CPU time 1377.57 seconds
Started Jul 04 05:17:01 PM PDT 24
Finished Jul 04 05:39:59 PM PDT 24
Peak memory 195080 kb
Host smart-03a73fe9-e1f9-4346-8950-7f9842301b2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365041402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3365041402
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.4077566744
Short name T177
Test name
Test status
Simulation time 439658568709 ps
CPU time 395.68 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:23:46 PM PDT 24
Peak memory 183104 kb
Host smart-a20682ad-9690-453c-8e2b-3a9e5327a194
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077566744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.4077566744
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3205897189
Short name T91
Test name
Test status
Simulation time 38938437261 ps
CPU time 52.52 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:18:03 PM PDT 24
Peak memory 182992 kb
Host smart-c75d69c4-225c-432e-a75e-2c7f429bd8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205897189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3205897189
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2167521760
Short name T26
Test name
Test status
Simulation time 17664615920 ps
CPU time 30.52 seconds
Started Jul 04 05:17:08 PM PDT 24
Finished Jul 04 05:17:39 PM PDT 24
Peak memory 183084 kb
Host smart-29f853ae-82e8-425e-af76-524685d6eed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167521760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2167521760
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.4163936919
Short name T375
Test name
Test status
Simulation time 1498001896 ps
CPU time 1.09 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:17:13 PM PDT 24
Peak memory 192888 kb
Host smart-63971fe1-1e45-406c-a946-f96a1dd182c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163936919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.4163936919
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1184223520
Short name T69
Test name
Test status
Simulation time 1643517049212 ps
CPU time 958.79 seconds
Started Jul 04 05:17:06 PM PDT 24
Finished Jul 04 05:33:05 PM PDT 24
Peak memory 191236 kb
Host smart-a3deef37-8417-439d-8fae-6faaeeb18fb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184223520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1184223520
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.55357023
Short name T332
Test name
Test status
Simulation time 534698615357 ps
CPU time 649.49 seconds
Started Jul 04 05:18:17 PM PDT 24
Finished Jul 04 05:29:07 PM PDT 24
Peak memory 191296 kb
Host smart-2d62569d-4977-4177-96a8-07b1540520d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55357023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.55357023
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.483774031
Short name T271
Test name
Test status
Simulation time 143966552988 ps
CPU time 267.09 seconds
Started Jul 04 05:18:17 PM PDT 24
Finished Jul 04 05:22:45 PM PDT 24
Peak memory 191300 kb
Host smart-5fbabe54-fa07-4714-8cff-c9a86b91b888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483774031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.483774031
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.566104089
Short name T323
Test name
Test status
Simulation time 211357533587 ps
CPU time 380.59 seconds
Started Jul 04 05:18:16 PM PDT 24
Finished Jul 04 05:24:37 PM PDT 24
Peak memory 191276 kb
Host smart-a97e3b98-7b7a-4c3e-9497-061ca2bf7c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566104089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.566104089
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.3891199606
Short name T178
Test name
Test status
Simulation time 121825604411 ps
CPU time 296.1 seconds
Started Jul 04 05:18:12 PM PDT 24
Finished Jul 04 05:23:09 PM PDT 24
Peak memory 183072 kb
Host smart-0b0d5aa2-37bb-41f3-bcd2-5fd4ebc7651d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891199606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.3891199606
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2408623243
Short name T327
Test name
Test status
Simulation time 959644662010 ps
CPU time 503.14 seconds
Started Jul 04 05:17:08 PM PDT 24
Finished Jul 04 05:25:31 PM PDT 24
Peak memory 183048 kb
Host smart-1d772a64-d0dc-4381-9841-9a58c3bf3ed7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408623243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2408623243
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.4051499782
Short name T308
Test name
Test status
Simulation time 194600301420 ps
CPU time 117.74 seconds
Started Jul 04 05:17:06 PM PDT 24
Finished Jul 04 05:19:04 PM PDT 24
Peak memory 191240 kb
Host smart-f30e9452-6700-426a-bc7b-a1671940df44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051499782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4051499782
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.1764926033
Short name T214
Test name
Test status
Simulation time 198448128222 ps
CPU time 187.08 seconds
Started Jul 04 05:18:16 PM PDT 24
Finished Jul 04 05:21:23 PM PDT 24
Peak memory 191276 kb
Host smart-1723b137-1ddf-4a88-8558-16da61a353c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764926033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1764926033
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.4250584001
Short name T24
Test name
Test status
Simulation time 1295568222094 ps
CPU time 1023.72 seconds
Started Jul 04 05:18:11 PM PDT 24
Finished Jul 04 05:35:15 PM PDT 24
Peak memory 194176 kb
Host smart-0de85b0a-3bd2-407a-becc-9a5e58a9837d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250584001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.4250584001
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3023415371
Short name T245
Test name
Test status
Simulation time 166932565014 ps
CPU time 112.16 seconds
Started Jul 04 05:18:12 PM PDT 24
Finished Jul 04 05:20:04 PM PDT 24
Peak memory 191296 kb
Host smart-ea2e0776-9e2e-49e6-ad93-9dbd54a5fa10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023415371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3023415371
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2067499568
Short name T126
Test name
Test status
Simulation time 153604653618 ps
CPU time 58.91 seconds
Started Jul 04 05:18:12 PM PDT 24
Finished Jul 04 05:19:12 PM PDT 24
Peak memory 183004 kb
Host smart-5797868f-fbef-4cc1-be55-25201847d9a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067499568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2067499568
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2965333572
Short name T200
Test name
Test status
Simulation time 59027860204 ps
CPU time 551.06 seconds
Started Jul 04 05:18:13 PM PDT 24
Finished Jul 04 05:27:25 PM PDT 24
Peak memory 191284 kb
Host smart-1227d74b-a711-49b3-bf5a-471b4bb521fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965333572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2965333572
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.476928399
Short name T238
Test name
Test status
Simulation time 116076766369 ps
CPU time 529.75 seconds
Started Jul 04 05:18:12 PM PDT 24
Finished Jul 04 05:27:03 PM PDT 24
Peak memory 191296 kb
Host smart-5a3c9110-577e-4205-8665-6963a00c99dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476928399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.476928399
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.4035876856
Short name T405
Test name
Test status
Simulation time 296729472101 ps
CPU time 117.03 seconds
Started Jul 04 05:18:23 PM PDT 24
Finished Jul 04 05:20:20 PM PDT 24
Peak memory 191256 kb
Host smart-b93f23f3-6c54-4839-b458-4c2dc9d47a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035876856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.4035876856
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.570816804
Short name T341
Test name
Test status
Simulation time 52078865304 ps
CPU time 167.18 seconds
Started Jul 04 05:18:24 PM PDT 24
Finished Jul 04 05:21:11 PM PDT 24
Peak memory 191264 kb
Host smart-6ed7da88-a335-4dd4-a95f-1f4075491ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570816804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.570816804
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1961985785
Short name T160
Test name
Test status
Simulation time 140268782820 ps
CPU time 241.96 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:21:13 PM PDT 24
Peak memory 183056 kb
Host smart-e8a50a83-4a79-4bc5-ace0-b3239b5e7bca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961985785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1961985785
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1881721388
Short name T65
Test name
Test status
Simulation time 259331352273 ps
CPU time 72.21 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:18:22 PM PDT 24
Peak memory 183088 kb
Host smart-d77bc461-f252-493b-a05f-4b1264ac2bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881721388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1881721388
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1810381038
Short name T182
Test name
Test status
Simulation time 583016463967 ps
CPU time 652.75 seconds
Started Jul 04 05:17:14 PM PDT 24
Finished Jul 04 05:28:07 PM PDT 24
Peak memory 194716 kb
Host smart-d2cd431b-2feb-45d8-89c9-8e4b3f4dc567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810381038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1810381038
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.568859251
Short name T219
Test name
Test status
Simulation time 660482078076 ps
CPU time 443.03 seconds
Started Jul 04 05:18:23 PM PDT 24
Finished Jul 04 05:25:46 PM PDT 24
Peak memory 191296 kb
Host smart-6cbca7e7-40cb-4ee2-92fb-5046cd5d6a0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568859251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.568859251
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2046926822
Short name T171
Test name
Test status
Simulation time 510669610008 ps
CPU time 433.01 seconds
Started Jul 04 05:18:23 PM PDT 24
Finished Jul 04 05:25:37 PM PDT 24
Peak memory 194552 kb
Host smart-1b76036f-f154-420e-a509-fbef4e690d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046926822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2046926822
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.1624904267
Short name T80
Test name
Test status
Simulation time 314674975905 ps
CPU time 721.73 seconds
Started Jul 04 05:18:23 PM PDT 24
Finished Jul 04 05:30:26 PM PDT 24
Peak memory 194548 kb
Host smart-5d92dab0-c83a-4f77-9589-8a352d465782
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624904267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.1624904267
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2202132917
Short name T231
Test name
Test status
Simulation time 160030522541 ps
CPU time 142.38 seconds
Started Jul 04 05:18:22 PM PDT 24
Finished Jul 04 05:20:45 PM PDT 24
Peak memory 191216 kb
Host smart-8795b72f-b9d2-4a69-9e0b-3e504b215f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202132917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2202132917
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3419556905
Short name T278
Test name
Test status
Simulation time 59536244888 ps
CPU time 1076.59 seconds
Started Jul 04 05:18:22 PM PDT 24
Finished Jul 04 05:36:19 PM PDT 24
Peak memory 191192 kb
Host smart-2c8a0215-c701-4590-996d-e254ffb9876c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419556905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3419556905
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1079089842
Short name T348
Test name
Test status
Simulation time 11215903084 ps
CPU time 27.92 seconds
Started Jul 04 05:18:24 PM PDT 24
Finished Jul 04 05:18:52 PM PDT 24
Peak memory 183072 kb
Host smart-b965a65f-1188-4a59-bd29-b26ad1d0bdd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079089842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1079089842
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3428424601
Short name T379
Test name
Test status
Simulation time 68286207493 ps
CPU time 82.54 seconds
Started Jul 04 05:18:21 PM PDT 24
Finished Jul 04 05:19:44 PM PDT 24
Peak memory 191264 kb
Host smart-aac9448c-49fd-4e9d-87a4-a8dd27b42837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428424601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3428424601
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.4202723071
Short name T89
Test name
Test status
Simulation time 1073910213995 ps
CPU time 939.7 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:32:51 PM PDT 24
Peak memory 183040 kb
Host smart-76db4edd-43cd-4c6b-8a6d-fabab27cd806
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202723071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.4202723071
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.434565075
Short name T46
Test name
Test status
Simulation time 53825084947 ps
CPU time 76.66 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:18:27 PM PDT 24
Peak memory 183080 kb
Host smart-3a871e61-51f2-4eb2-aaee-fd74fb0b7a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434565075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.434565075
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3303033812
Short name T76
Test name
Test status
Simulation time 14924482907 ps
CPU time 10.98 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:17:23 PM PDT 24
Peak memory 191276 kb
Host smart-95acceb4-4bac-4401-ad52-3a6133f2ed0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303033812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3303033812
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.1679979662
Short name T255
Test name
Test status
Simulation time 59966419261 ps
CPU time 245.06 seconds
Started Jul 04 05:18:23 PM PDT 24
Finished Jul 04 05:22:29 PM PDT 24
Peak memory 183072 kb
Host smart-546f77c4-44b7-4cf1-a01f-19c4088bfb31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679979662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1679979662
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.964590702
Short name T147
Test name
Test status
Simulation time 111851885218 ps
CPU time 119.87 seconds
Started Jul 04 05:18:23 PM PDT 24
Finished Jul 04 05:20:24 PM PDT 24
Peak memory 191232 kb
Host smart-b7c9362c-04e5-4f09-9393-07adfb05cebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964590702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.964590702
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3252155242
Short name T217
Test name
Test status
Simulation time 149005789134 ps
CPU time 1690.76 seconds
Started Jul 04 05:18:22 PM PDT 24
Finished Jul 04 05:46:33 PM PDT 24
Peak memory 191204 kb
Host smart-e4bbaf46-1437-4a1a-9d53-c26446b01386
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252155242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3252155242
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1283781757
Short name T112
Test name
Test status
Simulation time 180660301483 ps
CPU time 312.12 seconds
Started Jul 04 05:18:22 PM PDT 24
Finished Jul 04 05:23:34 PM PDT 24
Peak memory 191296 kb
Host smart-e7da86b9-3573-4901-8e71-39f8433f2805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283781757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1283781757
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2531509946
Short name T275
Test name
Test status
Simulation time 89219940423 ps
CPU time 315.41 seconds
Started Jul 04 05:18:32 PM PDT 24
Finished Jul 04 05:23:48 PM PDT 24
Peak memory 191296 kb
Host smart-28114bbd-7d39-4602-9bc4-7ef5fb72866e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531509946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2531509946
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2105497494
Short name T234
Test name
Test status
Simulation time 161718303897 ps
CPU time 91.17 seconds
Started Jul 04 05:18:35 PM PDT 24
Finished Jul 04 05:20:06 PM PDT 24
Peak memory 193324 kb
Host smart-88bb96cd-e832-4806-8f73-e8a1a200034c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105497494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2105497494
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3816944827
Short name T49
Test name
Test status
Simulation time 178224107385 ps
CPU time 168.37 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:20:00 PM PDT 24
Peak memory 182944 kb
Host smart-318377ce-4a51-44ec-8a93-12193674105b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816944827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3816944827
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.4111032126
Short name T433
Test name
Test status
Simulation time 60640342218 ps
CPU time 78 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:18:29 PM PDT 24
Peak memory 183068 kb
Host smart-27ae3113-9f99-41e1-a7cc-ab66e78e2f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111032126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4111032126
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.3196829735
Short name T118
Test name
Test status
Simulation time 789757466926 ps
CPU time 294.09 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 191244 kb
Host smart-fa637f06-67e1-4cda-8a11-b67c35cb1e59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196829735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.3196829735
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4055246520
Short name T328
Test name
Test status
Simulation time 48035007754 ps
CPU time 64.14 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:18:15 PM PDT 24
Peak memory 182972 kb
Host smart-3d576189-4cf4-467e-b5c6-9949cdc12ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055246520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4055246520
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1988728175
Short name T185
Test name
Test status
Simulation time 996976318853 ps
CPU time 641.07 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:27:51 PM PDT 24
Peak memory 195068 kb
Host smart-81a3e743-4203-435d-beec-a897ada8f0a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988728175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1988728175
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.3959950250
Short name T90
Test name
Test status
Simulation time 50606970167 ps
CPU time 93.65 seconds
Started Jul 04 05:18:32 PM PDT 24
Finished Jul 04 05:20:06 PM PDT 24
Peak memory 191244 kb
Host smart-bbf4d8e2-1294-4340-bc94-4099cf2b28e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959950250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3959950250
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2128735034
Short name T343
Test name
Test status
Simulation time 28171400485 ps
CPU time 40.32 seconds
Started Jul 04 05:18:32 PM PDT 24
Finished Jul 04 05:19:13 PM PDT 24
Peak memory 191216 kb
Host smart-7b03382e-f53f-416d-b2c4-55fc3fe965c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128735034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2128735034
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3536813075
Short name T394
Test name
Test status
Simulation time 185570590810 ps
CPU time 207.07 seconds
Started Jul 04 05:18:34 PM PDT 24
Finished Jul 04 05:22:01 PM PDT 24
Peak memory 183088 kb
Host smart-de69715d-efb3-4652-b020-86f530d02fa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536813075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3536813075
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1841024691
Short name T292
Test name
Test status
Simulation time 323498872593 ps
CPU time 160.67 seconds
Started Jul 04 05:18:31 PM PDT 24
Finished Jul 04 05:21:12 PM PDT 24
Peak memory 191276 kb
Host smart-1885baf5-a61b-434d-86bf-6b9746b438eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841024691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1841024691
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.769099595
Short name T43
Test name
Test status
Simulation time 31364179597 ps
CPU time 47.67 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:17:59 PM PDT 24
Peak memory 183096 kb
Host smart-d2f00bc8-1a89-443e-8702-d3069ba87dc8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769099595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.769099595
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.3943493239
Short name T373
Test name
Test status
Simulation time 213574796107 ps
CPU time 139.88 seconds
Started Jul 04 05:17:14 PM PDT 24
Finished Jul 04 05:19:35 PM PDT 24
Peak memory 183056 kb
Host smart-682a52e5-e950-4d25-aa10-b3229e23b997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943493239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.3943493239
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3950995220
Short name T218
Test name
Test status
Simulation time 21840344964 ps
CPU time 39.83 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:17:51 PM PDT 24
Peak memory 182984 kb
Host smart-af8ea9e9-9758-4bb7-ac48-0850afcde4bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950995220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3950995220
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3176652493
Short name T257
Test name
Test status
Simulation time 53474791309 ps
CPU time 177.98 seconds
Started Jul 04 05:17:14 PM PDT 24
Finished Jul 04 05:20:13 PM PDT 24
Peak memory 191268 kb
Host smart-07825104-58ae-4501-aae7-0e71be6d79a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176652493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3176652493
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.8498537
Short name T48
Test name
Test status
Simulation time 4087549495385 ps
CPU time 818.52 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:30:48 PM PDT 24
Peak memory 182988 kb
Host smart-acdf95c4-a580-4905-aa95-09dbd2ce0467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8498537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.8498537
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1302388622
Short name T316
Test name
Test status
Simulation time 124775865599 ps
CPU time 543.17 seconds
Started Jul 04 05:18:34 PM PDT 24
Finished Jul 04 05:27:38 PM PDT 24
Peak memory 191288 kb
Host smart-8a180f70-aeba-4bfb-a088-3ae96a46d82a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302388622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1302388622
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.1760224871
Short name T47
Test name
Test status
Simulation time 165410588159 ps
CPU time 171.31 seconds
Started Jul 04 05:18:42 PM PDT 24
Finished Jul 04 05:21:33 PM PDT 24
Peak memory 192316 kb
Host smart-da7f10f5-c58a-4240-aca0-a04e81a6de93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760224871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.1760224871
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3510613960
Short name T212
Test name
Test status
Simulation time 432582558600 ps
CPU time 197.3 seconds
Started Jul 04 05:18:40 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 191300 kb
Host smart-8cbb40f8-1259-48ec-a7eb-9a01a2cdd1fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510613960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3510613960
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.263504579
Short name T285
Test name
Test status
Simulation time 78184978126 ps
CPU time 178.21 seconds
Started Jul 04 05:18:39 PM PDT 24
Finished Jul 04 05:21:38 PM PDT 24
Peak memory 191300 kb
Host smart-296c7361-15f2-4432-905d-10b58d0a5497
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263504579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.263504579
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2750878208
Short name T289
Test name
Test status
Simulation time 955068459533 ps
CPU time 463.44 seconds
Started Jul 04 05:18:39 PM PDT 24
Finished Jul 04 05:26:23 PM PDT 24
Peak memory 191272 kb
Host smart-00bb170b-4a55-47c6-851b-343f99d7dd47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750878208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2750878208
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1699164177
Short name T225
Test name
Test status
Simulation time 78741937849 ps
CPU time 124.31 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:19:16 PM PDT 24
Peak memory 183068 kb
Host smart-49f7fcb0-a420-484c-b156-b19931637487
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699164177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1699164177
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1071631584
Short name T384
Test name
Test status
Simulation time 191641615083 ps
CPU time 149.01 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:19:40 PM PDT 24
Peak memory 183092 kb
Host smart-cf3975ac-90e8-47c7-a13f-c28844564606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071631584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1071631584
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.4107663470
Short name T422
Test name
Test status
Simulation time 126799768408 ps
CPU time 457.82 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:24:48 PM PDT 24
Peak memory 191284 kb
Host smart-ad363950-14d2-47e2-8fb6-d3c7f3faae7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107663470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.4107663470
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1320288879
Short name T57
Test name
Test status
Simulation time 299524102301 ps
CPU time 358.9 seconds
Started Jul 04 05:18:38 PM PDT 24
Finished Jul 04 05:24:38 PM PDT 24
Peak memory 191276 kb
Host smart-94fd5cfd-4fbb-4cbb-abb8-544b645605ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320288879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1320288879
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2808341372
Short name T288
Test name
Test status
Simulation time 26100441728 ps
CPU time 58.95 seconds
Started Jul 04 05:18:38 PM PDT 24
Finished Jul 04 05:19:38 PM PDT 24
Peak memory 191288 kb
Host smart-629bdc35-0eda-4989-92be-aeb87ace96a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808341372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2808341372
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3115186139
Short name T149
Test name
Test status
Simulation time 284320221394 ps
CPU time 76.66 seconds
Started Jul 04 05:18:39 PM PDT 24
Finished Jul 04 05:19:57 PM PDT 24
Peak memory 191272 kb
Host smart-501dcdce-d2d0-4b1e-961f-5bac2d24669c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115186139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3115186139
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2091149578
Short name T431
Test name
Test status
Simulation time 64206209741 ps
CPU time 96.98 seconds
Started Jul 04 05:18:39 PM PDT 24
Finished Jul 04 05:20:17 PM PDT 24
Peak memory 193900 kb
Host smart-2cff8f64-fed7-434f-b2ec-7cf937a7baa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091149578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2091149578
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3493117613
Short name T233
Test name
Test status
Simulation time 864437568929 ps
CPU time 243.33 seconds
Started Jul 04 05:18:39 PM PDT 24
Finished Jul 04 05:22:43 PM PDT 24
Peak memory 191252 kb
Host smart-64f2882f-f135-40b8-b2c0-31c49d7117ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493117613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3493117613
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2487865056
Short name T395
Test name
Test status
Simulation time 5773278270 ps
CPU time 5.17 seconds
Started Jul 04 05:18:40 PM PDT 24
Finished Jul 04 05:18:45 PM PDT 24
Peak memory 183072 kb
Host smart-ce6ba5be-34e9-4ef0-84b2-1b80ff5d427d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487865056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2487865056
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1651905288
Short name T9
Test name
Test status
Simulation time 70343094430 ps
CPU time 65.77 seconds
Started Jul 04 05:18:39 PM PDT 24
Finished Jul 04 05:19:45 PM PDT 24
Peak memory 183040 kb
Host smart-3817ff6d-8d14-475f-a0bc-7d923b9d5e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651905288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1651905288
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3216552583
Short name T418
Test name
Test status
Simulation time 190568725387 ps
CPU time 160.01 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:19:52 PM PDT 24
Peak memory 183044 kb
Host smart-2dd9c51f-ff1d-4aa6-a9d5-53838764aa39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216552583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3216552583
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.42301146
Short name T368
Test name
Test status
Simulation time 3857852643 ps
CPU time 6.74 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:17:18 PM PDT 24
Peak memory 182992 kb
Host smart-2d9cd5a4-ba7e-483f-af57-3dfeb32b3fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42301146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.42301146
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3062240056
Short name T21
Test name
Test status
Simulation time 245773319080 ps
CPU time 114.6 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:19:07 PM PDT 24
Peak memory 191272 kb
Host smart-484bae73-8c69-4a79-99f3-60cd3e0190ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062240056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3062240056
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2226294391
Short name T370
Test name
Test status
Simulation time 57810019 ps
CPU time 0.64 seconds
Started Jul 04 05:17:07 PM PDT 24
Finished Jul 04 05:17:08 PM PDT 24
Peak memory 182948 kb
Host smart-bfd559ef-96c6-4bec-a4e5-d698d9ec760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226294391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2226294391
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.291962509
Short name T354
Test name
Test status
Simulation time 240770253848 ps
CPU time 675.17 seconds
Started Jul 04 05:17:08 PM PDT 24
Finished Jul 04 05:28:23 PM PDT 24
Peak memory 193304 kb
Host smart-5a9b2af6-1d88-4668-bb33-946d53ca66db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291962509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
291962509
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/171.rv_timer_random.2593526680
Short name T230
Test name
Test status
Simulation time 379594635656 ps
CPU time 165.88 seconds
Started Jul 04 05:18:50 PM PDT 24
Finished Jul 04 05:21:37 PM PDT 24
Peak memory 191244 kb
Host smart-eab8f41e-44d0-479c-9443-71b4798d7f74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593526680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2593526680
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2088726114
Short name T302
Test name
Test status
Simulation time 38968823703 ps
CPU time 31.58 seconds
Started Jul 04 05:18:52 PM PDT 24
Finished Jul 04 05:19:24 PM PDT 24
Peak memory 183068 kb
Host smart-f79733e2-5d14-4f13-bf9c-2c195f9f2944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088726114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2088726114
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3639686396
Short name T355
Test name
Test status
Simulation time 214967996705 ps
CPU time 153.33 seconds
Started Jul 04 05:18:51 PM PDT 24
Finished Jul 04 05:21:24 PM PDT 24
Peak memory 191264 kb
Host smart-ec22b23d-de45-41d3-a95c-b2b6571d0554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639686396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3639686396
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.4024412322
Short name T50
Test name
Test status
Simulation time 729638718555 ps
CPU time 204.54 seconds
Started Jul 04 05:18:49 PM PDT 24
Finished Jul 04 05:22:14 PM PDT 24
Peak memory 191260 kb
Host smart-4687889c-4591-48a0-9d6c-7eef361fab12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024412322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.4024412322
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2446505253
Short name T117
Test name
Test status
Simulation time 25463476381 ps
CPU time 41.84 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:19:41 PM PDT 24
Peak memory 191216 kb
Host smart-a0790add-83d8-4927-9d41-82536425754f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446505253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2446505253
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.4142025770
Short name T247
Test name
Test status
Simulation time 240058984959 ps
CPU time 368.45 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:25:08 PM PDT 24
Peak memory 191284 kb
Host smart-da4e52be-4b5f-4797-8acf-e0efa6c95b24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142025770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4142025770
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3153739170
Short name T314
Test name
Test status
Simulation time 21810460016 ps
CPU time 167.13 seconds
Started Jul 04 05:19:00 PM PDT 24
Finished Jul 04 05:21:48 PM PDT 24
Peak memory 183096 kb
Host smart-052275c4-86cb-4ebf-921c-8dc7febf311e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153739170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3153739170
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4096829366
Short name T414
Test name
Test status
Simulation time 88695330415 ps
CPU time 2441.56 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:59:41 PM PDT 24
Peak memory 191276 kb
Host smart-54faedde-ea16-478e-bf52-12780d57b976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096829366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4096829366
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2203267810
Short name T143
Test name
Test status
Simulation time 75084723339 ps
CPU time 130.5 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:19:22 PM PDT 24
Peak memory 183056 kb
Host smart-607f5572-d7ab-4056-bb07-d040febcb6c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203267810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2203267810
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.850072006
Short name T86
Test name
Test status
Simulation time 608352646979 ps
CPU time 236 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:21:05 PM PDT 24
Peak memory 183020 kb
Host smart-721dcce8-64fe-4352-9bc8-fecb04403488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850072006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.850072006
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1300126994
Short name T209
Test name
Test status
Simulation time 113200002073 ps
CPU time 443.14 seconds
Started Jul 04 05:17:12 PM PDT 24
Finished Jul 04 05:24:36 PM PDT 24
Peak memory 191256 kb
Host smart-c0786c79-8abf-4b20-a7d9-fdee50e84921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300126994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1300126994
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3574748611
Short name T83
Test name
Test status
Simulation time 30401853440 ps
CPU time 12.36 seconds
Started Jul 04 05:17:08 PM PDT 24
Finished Jul 04 05:17:20 PM PDT 24
Peak memory 194740 kb
Host smart-430531aa-a6da-4218-830e-f8a9706eac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574748611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3574748611
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2427092983
Short name T12
Test name
Test status
Simulation time 25579413527 ps
CPU time 13.12 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:17:23 PM PDT 24
Peak memory 193884 kb
Host smart-83376de3-c440-4570-84a2-81b697b8de0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427092983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2427092983
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.1701583469
Short name T93
Test name
Test status
Simulation time 379695035799 ps
CPU time 542.12 seconds
Started Jul 04 05:19:00 PM PDT 24
Finished Jul 04 05:28:02 PM PDT 24
Peak memory 191300 kb
Host smart-8c7852cc-c7b2-4c53-aae5-aee596e5251f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701583469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1701583469
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.310892690
Short name T113
Test name
Test status
Simulation time 105791672948 ps
CPU time 177.65 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:21:57 PM PDT 24
Peak memory 194708 kb
Host smart-607c65cf-5a87-401b-bef9-a01f109a10bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310892690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.310892690
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3219619872
Short name T339
Test name
Test status
Simulation time 45918620088 ps
CPU time 43.74 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:19:43 PM PDT 24
Peak memory 183040 kb
Host smart-731223a1-c5dd-4efb-8f78-48c77218c96e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219619872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3219619872
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3358837218
Short name T170
Test name
Test status
Simulation time 75645062563 ps
CPU time 1312.79 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:40:52 PM PDT 24
Peak memory 191312 kb
Host smart-9250f42b-c6fe-45bf-afe6-6bd13d5ed00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358837218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3358837218
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.2890528701
Short name T307
Test name
Test status
Simulation time 151963182304 ps
CPU time 88.94 seconds
Started Jul 04 05:18:58 PM PDT 24
Finished Jul 04 05:20:27 PM PDT 24
Peak memory 183016 kb
Host smart-4a0b3e00-9c5f-4f94-adbd-04e81856d6e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890528701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2890528701
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.416602157
Short name T138
Test name
Test status
Simulation time 48718956736 ps
CPU time 83.86 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:20:23 PM PDT 24
Peak memory 191268 kb
Host smart-9c6bf6e4-eace-4adf-8d8d-ef6c029e6367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416602157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.416602157
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3477616736
Short name T413
Test name
Test status
Simulation time 159636449898 ps
CPU time 258.28 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:23:17 PM PDT 24
Peak memory 191296 kb
Host smart-8f711d1c-d6c5-4a45-aada-b56e812549d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477616736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3477616736
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1526653032
Short name T45
Test name
Test status
Simulation time 43989892417 ps
CPU time 1171.7 seconds
Started Jul 04 05:18:58 PM PDT 24
Finished Jul 04 05:38:30 PM PDT 24
Peak memory 183072 kb
Host smart-2c7c1a87-cd68-47a8-9174-c853b6c7bf60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526653032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1526653032
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.576956264
Short name T263
Test name
Test status
Simulation time 336509494395 ps
CPU time 300.52 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:22:11 PM PDT 24
Peak memory 183040 kb
Host smart-75c12189-2540-4e8b-86c4-aa7ef33ef8aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576956264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.576956264
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2842971431
Short name T389
Test name
Test status
Simulation time 181073030067 ps
CPU time 171.26 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:20:06 PM PDT 24
Peak memory 183068 kb
Host smart-25e05c5a-8c37-4c19-be72-8f6ee69e3256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842971431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2842971431
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3369259173
Short name T396
Test name
Test status
Simulation time 14119945836 ps
CPU time 7.96 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:17:18 PM PDT 24
Peak memory 183048 kb
Host smart-2613b36b-f85b-4e40-a4c8-8532e3894206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369259173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3369259173
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.2744342995
Short name T424
Test name
Test status
Simulation time 318264917812 ps
CPU time 324.49 seconds
Started Jul 04 05:17:12 PM PDT 24
Finished Jul 04 05:22:37 PM PDT 24
Peak memory 191308 kb
Host smart-6b4a219e-2e58-4a69-a998-b504db7091ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744342995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.2744342995
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.306213357
Short name T304
Test name
Test status
Simulation time 618836276634 ps
CPU time 196.1 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:22:16 PM PDT 24
Peak memory 191244 kb
Host smart-881088a6-6ab3-4b6d-96c1-4b8519200107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306213357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.306213357
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1735322038
Short name T10
Test name
Test status
Simulation time 341850519722 ps
CPU time 330.14 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:24:29 PM PDT 24
Peak memory 183044 kb
Host smart-0213629d-1385-4fa6-9847-83acaadd002a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735322038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1735322038
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.626821657
Short name T294
Test name
Test status
Simulation time 111139830575 ps
CPU time 175.17 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:21:54 PM PDT 24
Peak memory 191244 kb
Host smart-23936d2c-3c9e-4bfe-8dca-a2c327752099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626821657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.626821657
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3954687672
Short name T153
Test name
Test status
Simulation time 72075907385 ps
CPU time 134.13 seconds
Started Jul 04 05:19:00 PM PDT 24
Finished Jul 04 05:21:15 PM PDT 24
Peak memory 191276 kb
Host smart-6c8ada0c-60a6-4ac6-bcad-2814c31c5a8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954687672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3954687672
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.268318041
Short name T137
Test name
Test status
Simulation time 169338947202 ps
CPU time 151.64 seconds
Started Jul 04 05:19:00 PM PDT 24
Finished Jul 04 05:21:32 PM PDT 24
Peak memory 191288 kb
Host smart-8c1553ff-4b2f-409c-9921-be7cf144e7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268318041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.268318041
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1301604840
Short name T87
Test name
Test status
Simulation time 759297295189 ps
CPU time 808.63 seconds
Started Jul 04 05:18:58 PM PDT 24
Finished Jul 04 05:32:27 PM PDT 24
Peak memory 191248 kb
Host smart-3b215233-704f-4b59-aea7-396d76a715e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301604840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1301604840
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1092722459
Short name T290
Test name
Test status
Simulation time 128545184600 ps
CPU time 276.18 seconds
Started Jul 04 05:18:59 PM PDT 24
Finished Jul 04 05:23:36 PM PDT 24
Peak memory 191260 kb
Host smart-73b0eacf-d01c-4b88-87eb-d849e2344ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092722459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1092722459
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1097819752
Short name T342
Test name
Test status
Simulation time 1087137920678 ps
CPU time 1019.94 seconds
Started Jul 04 05:19:12 PM PDT 24
Finished Jul 04 05:36:12 PM PDT 24
Peak memory 193532 kb
Host smart-7ce41c91-c278-45cf-af4e-9ba2362a0749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097819752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1097819752
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.4153886394
Short name T175
Test name
Test status
Simulation time 1100747693172 ps
CPU time 509.72 seconds
Started Jul 04 05:19:13 PM PDT 24
Finished Jul 04 05:27:43 PM PDT 24
Peak memory 193536 kb
Host smart-9d1a37af-98de-4660-a7ff-ed7c66382d27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153886394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.4153886394
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1914426266
Short name T133
Test name
Test status
Simulation time 217364407923 ps
CPU time 347.73 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:22:48 PM PDT 24
Peak memory 183048 kb
Host smart-c3149a8c-3df1-40d7-943f-700018087a49
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914426266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1914426266
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1396642142
Short name T61
Test name
Test status
Simulation time 672148487434 ps
CPU time 170.74 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:19:52 PM PDT 24
Peak memory 182996 kb
Host smart-36bed4d5-a9d9-4cf9-9161-be8a70b1d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396642142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1396642142
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2085837430
Short name T412
Test name
Test status
Simulation time 31060280996 ps
CPU time 21.73 seconds
Started Jul 04 05:17:03 PM PDT 24
Finished Jul 04 05:17:25 PM PDT 24
Peak memory 183096 kb
Host smart-2310309d-8829-4384-b8b6-4fb3942df7a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085837430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2085837430
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1747180307
Short name T11
Test name
Test status
Simulation time 1405038626 ps
CPU time 1.57 seconds
Started Jul 04 05:17:03 PM PDT 24
Finished Jul 04 05:17:05 PM PDT 24
Peak memory 182904 kb
Host smart-142096d1-0a2b-4e1f-83cf-8dd54b8bc1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747180307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1747180307
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.498205792
Short name T19
Test name
Test status
Simulation time 77347865 ps
CPU time 0.76 seconds
Started Jul 04 05:16:58 PM PDT 24
Finished Jul 04 05:16:59 PM PDT 24
Peak memory 214152 kb
Host smart-e716ebe4-d02b-4da5-a1fb-cc4f4bda68b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498205792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.498205792
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.958478597
Short name T432
Test name
Test status
Simulation time 328061793428 ps
CPU time 485.1 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:25:05 PM PDT 24
Peak memory 191264 kb
Host smart-029be4a2-58ea-4115-9189-501c2686ed56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958478597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.958478597
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2661894940
Short name T333
Test name
Test status
Simulation time 1004378157654 ps
CPU time 509 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:25:40 PM PDT 24
Peak memory 183040 kb
Host smart-ef63bda5-7f62-474d-8a06-79d2b2dfb033
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661894940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2661894940
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.336037293
Short name T407
Test name
Test status
Simulation time 22093991291 ps
CPU time 16.34 seconds
Started Jul 04 05:17:12 PM PDT 24
Finished Jul 04 05:17:29 PM PDT 24
Peak memory 183088 kb
Host smart-c18ce10a-6271-4af6-abc8-b467d09fa119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336037293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.336037293
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.3272965247
Short name T174
Test name
Test status
Simulation time 393370927871 ps
CPU time 176.32 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:20:08 PM PDT 24
Peak memory 193316 kb
Host smart-a562e654-8801-482c-9754-ae4c5e58c03e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272965247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3272965247
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3581994308
Short name T410
Test name
Test status
Simulation time 425064340 ps
CPU time 0.65 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:17:16 PM PDT 24
Peak memory 182944 kb
Host smart-0bc1980f-4654-47ac-bd5e-6ea3e001eae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581994308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3581994308
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.484758343
Short name T336
Test name
Test status
Simulation time 275753405629 ps
CPU time 201.24 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:20:37 PM PDT 24
Peak memory 191272 kb
Host smart-f18bfbb3-a283-4cd8-8963-5e364a17ecc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484758343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
484758343
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1611954837
Short name T399
Test name
Test status
Simulation time 384838269863 ps
CPU time 559.45 seconds
Started Jul 04 05:17:16 PM PDT 24
Finished Jul 04 05:26:35 PM PDT 24
Peak memory 183036 kb
Host smart-d7868bb6-2e34-48b4-abed-931fa2363611
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611954837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1611954837
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1826490815
Short name T359
Test name
Test status
Simulation time 78434582626 ps
CPU time 29.81 seconds
Started Jul 04 05:17:13 PM PDT 24
Finished Jul 04 05:17:43 PM PDT 24
Peak memory 183072 kb
Host smart-7eb4b458-56c6-4514-a440-3a4ef44d3cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826490815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1826490815
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1121007971
Short name T338
Test name
Test status
Simulation time 59531276525 ps
CPU time 357.9 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:23:14 PM PDT 24
Peak memory 183068 kb
Host smart-05b34593-85b8-40bc-968d-e24ccfa64484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121007971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1121007971
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1898025768
Short name T213
Test name
Test status
Simulation time 394965653064 ps
CPU time 376.56 seconds
Started Jul 04 05:17:17 PM PDT 24
Finished Jul 04 05:23:33 PM PDT 24
Peak memory 183084 kb
Host smart-472d1d05-d627-4d1d-a133-a98822433dd0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898025768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1898025768
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2450906688
Short name T417
Test name
Test status
Simulation time 423503964001 ps
CPU time 192.52 seconds
Started Jul 04 05:17:12 PM PDT 24
Finished Jul 04 05:20:25 PM PDT 24
Peak memory 182956 kb
Host smart-fadf2ee9-087a-4995-9912-8e34676e515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450906688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2450906688
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3271338239
Short name T356
Test name
Test status
Simulation time 269919739895 ps
CPU time 676.03 seconds
Started Jul 04 05:17:17 PM PDT 24
Finished Jul 04 05:28:33 PM PDT 24
Peak memory 191244 kb
Host smart-3d3ea0d4-e949-4185-b699-42158625c031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271338239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3271338239
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3235951330
Short name T313
Test name
Test status
Simulation time 55608333880 ps
CPU time 106.77 seconds
Started Jul 04 05:17:17 PM PDT 24
Finished Jul 04 05:19:04 PM PDT 24
Peak memory 191284 kb
Host smart-45cbfd88-984d-4cfc-8b53-4c18fd72ec9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235951330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3235951330
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.4141089089
Short name T317
Test name
Test status
Simulation time 508605101558 ps
CPU time 1080.18 seconds
Started Jul 04 05:17:14 PM PDT 24
Finished Jul 04 05:35:14 PM PDT 24
Peak memory 195240 kb
Host smart-ae6e95eb-11d2-4e2e-9825-71cdb1819cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141089089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.4141089089
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.2562663905
Short name T37
Test name
Test status
Simulation time 7710928315 ps
CPU time 60.44 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:18:21 PM PDT 24
Peak memory 197748 kb
Host smart-737402b8-7e67-4288-8176-2107c3d0255e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562663905 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.2562663905
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1062913446
Short name T334
Test name
Test status
Simulation time 166470259461 ps
CPU time 150.36 seconds
Started Jul 04 05:17:14 PM PDT 24
Finished Jul 04 05:19:44 PM PDT 24
Peak memory 183020 kb
Host smart-68347202-3bfb-48a9-9921-2e28de63aed7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062913446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1062913446
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.189123707
Short name T378
Test name
Test status
Simulation time 401394629973 ps
CPU time 61.72 seconds
Started Jul 04 05:17:16 PM PDT 24
Finished Jul 04 05:18:18 PM PDT 24
Peak memory 183092 kb
Host smart-261a0ccb-5661-4e5e-9da4-208cdfa19056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189123707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.189123707
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1037224237
Short name T235
Test name
Test status
Simulation time 48852670477 ps
CPU time 74.9 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:18:30 PM PDT 24
Peak memory 191540 kb
Host smart-1910a3ea-e3cb-414e-b031-fd8ccb7730c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037224237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1037224237
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.381973488
Short name T374
Test name
Test status
Simulation time 39384670842 ps
CPU time 62.65 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:18:18 PM PDT 24
Peak memory 183084 kb
Host smart-e274470b-999b-4077-afe9-7102e497bf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381973488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.381973488
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.130760246
Short name T210
Test name
Test status
Simulation time 93493430245 ps
CPU time 147.49 seconds
Started Jul 04 05:17:17 PM PDT 24
Finished Jul 04 05:19:45 PM PDT 24
Peak memory 182968 kb
Host smart-b6362a84-8dc3-4b0e-884f-aeb8c540fb58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130760246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.130760246
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3684749728
Short name T430
Test name
Test status
Simulation time 168497264764 ps
CPU time 239.6 seconds
Started Jul 04 05:17:13 PM PDT 24
Finished Jul 04 05:21:13 PM PDT 24
Peak memory 183080 kb
Host smart-fd91c0ea-d030-47fd-a09e-0ba2701eaa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684749728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3684749728
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.1931250594
Short name T277
Test name
Test status
Simulation time 33728646617 ps
CPU time 53.71 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:18:09 PM PDT 24
Peak memory 183348 kb
Host smart-78f25ebb-6ca7-4ab4-8e19-9c76cdddaa86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931250594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.1931250594
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.775207082
Short name T337
Test name
Test status
Simulation time 53275264490 ps
CPU time 40.86 seconds
Started Jul 04 05:17:17 PM PDT 24
Finished Jul 04 05:17:58 PM PDT 24
Peak memory 183028 kb
Host smart-b1c16d97-b4d3-49bf-aa04-42acf5e4e79c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775207082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.775207082
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.738341864
Short name T63
Test name
Test status
Simulation time 17462141105 ps
CPU time 22.75 seconds
Started Jul 04 05:17:13 PM PDT 24
Finished Jul 04 05:17:37 PM PDT 24
Peak memory 183096 kb
Host smart-f7664b58-3b7e-47b1-9447-15584a213624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738341864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.738341864
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.861420821
Short name T260
Test name
Test status
Simulation time 1006980651201 ps
CPU time 248.14 seconds
Started Jul 04 05:17:17 PM PDT 24
Finished Jul 04 05:21:26 PM PDT 24
Peak memory 194772 kb
Host smart-a156869c-25ac-48d4-a6e1-ad3a492683c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861420821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.861420821
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.794812543
Short name T145
Test name
Test status
Simulation time 66366985723 ps
CPU time 116.45 seconds
Started Jul 04 05:17:14 PM PDT 24
Finished Jul 04 05:19:11 PM PDT 24
Peak memory 183072 kb
Host smart-a0b159c1-f384-4fbb-9fe2-a6663cf411ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794812543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.794812543
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.599927203
Short name T300
Test name
Test status
Simulation time 63749782332 ps
CPU time 101.97 seconds
Started Jul 04 05:17:14 PM PDT 24
Finished Jul 04 05:18:56 PM PDT 24
Peak memory 183068 kb
Host smart-451abc56-b055-4866-b1c1-15151f5ce7ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599927203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.599927203
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3562046915
Short name T419
Test name
Test status
Simulation time 102729768954 ps
CPU time 142.22 seconds
Started Jul 04 05:17:17 PM PDT 24
Finished Jul 04 05:19:39 PM PDT 24
Peak memory 183092 kb
Host smart-f0500e1c-1d5a-4688-940e-d8dfb543eeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562046915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3562046915
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.4093039107
Short name T429
Test name
Test status
Simulation time 10324192310 ps
CPU time 16.88 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:17:29 PM PDT 24
Peak memory 182968 kb
Host smart-cae38a16-b491-4c85-8da6-a7910d13aeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093039107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.4093039107
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.936915268
Short name T439
Test name
Test status
Simulation time 1480198511637 ps
CPU time 230.9 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:21:06 PM PDT 24
Peak memory 194696 kb
Host smart-d60e17d7-af8c-42bb-b2e1-3d3dc6438d78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936915268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
936915268
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3808372990
Short name T124
Test name
Test status
Simulation time 8856368308 ps
CPU time 16.05 seconds
Started Jul 04 05:17:13 PM PDT 24
Finished Jul 04 05:17:29 PM PDT 24
Peak memory 183068 kb
Host smart-86293558-27c2-4070-9b88-a396d7148795
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808372990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3808372990
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2816243758
Short name T415
Test name
Test status
Simulation time 72710987054 ps
CPU time 99.54 seconds
Started Jul 04 05:17:14 PM PDT 24
Finished Jul 04 05:18:53 PM PDT 24
Peak memory 183080 kb
Host smart-404b55a7-090e-4cce-a22e-0d49470d4aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816243758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2816243758
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3907751211
Short name T128
Test name
Test status
Simulation time 42057794711 ps
CPU time 65.66 seconds
Started Jul 04 05:17:17 PM PDT 24
Finished Jul 04 05:18:23 PM PDT 24
Peak memory 183044 kb
Host smart-31f626e5-734e-4202-95c2-8d80479308ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907751211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3907751211
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.371833014
Short name T92
Test name
Test status
Simulation time 722930078934 ps
CPU time 154.09 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:19:50 PM PDT 24
Peak memory 191224 kb
Host smart-40696196-b58f-4b41-952c-ab501fc523f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371833014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.371833014
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2932604524
Short name T206
Test name
Test status
Simulation time 521447582922 ps
CPU time 1226.47 seconds
Started Jul 04 05:17:25 PM PDT 24
Finished Jul 04 05:37:52 PM PDT 24
Peak memory 194644 kb
Host smart-42083865-f2d9-4b96-8a63-737b9403b81b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932604524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2932604524
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1928811818
Short name T425
Test name
Test status
Simulation time 23349297729 ps
CPU time 12.89 seconds
Started Jul 04 05:17:22 PM PDT 24
Finished Jul 04 05:17:35 PM PDT 24
Peak memory 183076 kb
Host smart-d42503c4-5d37-46d3-8b59-9ccd170293f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928811818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1928811818
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2811512917
Short name T387
Test name
Test status
Simulation time 166187726402 ps
CPU time 205.89 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:20:59 PM PDT 24
Peak memory 183060 kb
Host smart-843ef93c-5c0d-46db-a7ad-59c9b2e88279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811512917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2811512917
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.306854934
Short name T223
Test name
Test status
Simulation time 451322037427 ps
CPU time 611.89 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:27:46 PM PDT 24
Peak memory 191204 kb
Host smart-96338633-5ce2-4c1c-b0c8-79ae0be72f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306854934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.306854934
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1078813784
Short name T326
Test name
Test status
Simulation time 4189117119 ps
CPU time 10.49 seconds
Started Jul 04 05:17:30 PM PDT 24
Finished Jul 04 05:17:40 PM PDT 24
Peak memory 183064 kb
Host smart-a23313bf-282f-4b35-a5cd-9b9eb6e75bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078813784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1078813784
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2386424106
Short name T435
Test name
Test status
Simulation time 103611673842 ps
CPU time 123.38 seconds
Started Jul 04 05:17:23 PM PDT 24
Finished Jul 04 05:19:27 PM PDT 24
Peak memory 183028 kb
Host smart-eadd254e-95cf-4219-ab58-aa466ee60df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386424106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2386424106
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.4293773651
Short name T242
Test name
Test status
Simulation time 2134082307342 ps
CPU time 1093.54 seconds
Started Jul 04 05:17:24 PM PDT 24
Finished Jul 04 05:35:38 PM PDT 24
Peak memory 183084 kb
Host smart-fbd9297e-ce39-4a28-a3b7-74c8a5103c05
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293773651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.4293773651
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3483205625
Short name T364
Test name
Test status
Simulation time 494152314028 ps
CPU time 193.34 seconds
Started Jul 04 05:17:26 PM PDT 24
Finished Jul 04 05:20:40 PM PDT 24
Peak memory 183052 kb
Host smart-26d7c216-fc8c-4378-9aeb-dd3631a548ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483205625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3483205625
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3223981643
Short name T298
Test name
Test status
Simulation time 82320762573 ps
CPU time 145.23 seconds
Started Jul 04 05:17:23 PM PDT 24
Finished Jul 04 05:19:49 PM PDT 24
Peak memory 191284 kb
Host smart-682fe0cc-423c-49e9-a845-dce95a233f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223981643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3223981643
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3599560248
Short name T274
Test name
Test status
Simulation time 154836191392 ps
CPU time 111.03 seconds
Started Jul 04 05:17:23 PM PDT 24
Finished Jul 04 05:19:14 PM PDT 24
Peak memory 191292 kb
Host smart-32c0a784-899c-4e26-9af8-19c6b7e460a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599560248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3599560248
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4198524357
Short name T122
Test name
Test status
Simulation time 2047632374027 ps
CPU time 1056.94 seconds
Started Jul 04 05:17:01 PM PDT 24
Finished Jul 04 05:34:38 PM PDT 24
Peak memory 183060 kb
Host smart-94039763-defa-402c-a0ac-fc8661f0c09c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198524357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4198524357
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.127524255
Short name T392
Test name
Test status
Simulation time 82510564197 ps
CPU time 110.82 seconds
Started Jul 04 05:16:59 PM PDT 24
Finished Jul 04 05:18:50 PM PDT 24
Peak memory 183028 kb
Host smart-ed6bd1e9-801c-462e-be20-553910304d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127524255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.127524255
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3893218464
Short name T241
Test name
Test status
Simulation time 67913434765 ps
CPU time 54.53 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:17:55 PM PDT 24
Peak memory 183068 kb
Host smart-392940f5-115f-47fd-b466-9ecc6c892e4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893218464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3893218464
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1891740776
Short name T360
Test name
Test status
Simulation time 124262221 ps
CPU time 1.09 seconds
Started Jul 04 05:17:01 PM PDT 24
Finished Jul 04 05:17:02 PM PDT 24
Peak memory 183012 kb
Host smart-d64b790d-8e32-47d3-b81d-d3f7ffb6a525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891740776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1891740776
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2395645673
Short name T20
Test name
Test status
Simulation time 121123227 ps
CPU time 0.89 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:17:01 PM PDT 24
Peak memory 213392 kb
Host smart-5a9ab60d-051b-4f24-aa29-d47648c2a789
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395645673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2395645673
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2254340152
Short name T72
Test name
Test status
Simulation time 119489933 ps
CPU time 0.57 seconds
Started Jul 04 05:16:59 PM PDT 24
Finished Jul 04 05:17:00 PM PDT 24
Peak memory 182896 kb
Host smart-a5b16d45-9264-481d-8081-3e2ed82616d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254340152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2254340152
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2084580317
Short name T38
Test name
Test status
Simulation time 122191641190 ps
CPU time 414.32 seconds
Started Jul 04 05:16:59 PM PDT 24
Finished Jul 04 05:23:54 PM PDT 24
Peak memory 206004 kb
Host smart-3745e544-375e-405e-ad75-0ba713a000a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084580317 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.2084580317
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3982850359
Short name T254
Test name
Test status
Simulation time 123514661546 ps
CPU time 178.76 seconds
Started Jul 04 05:17:22 PM PDT 24
Finished Jul 04 05:20:21 PM PDT 24
Peak memory 183020 kb
Host smart-50c06ce4-e331-4737-ad6d-04222081f946
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982850359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3982850359
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1914257457
Short name T367
Test name
Test status
Simulation time 160801400109 ps
CPU time 126.08 seconds
Started Jul 04 05:17:23 PM PDT 24
Finished Jul 04 05:19:30 PM PDT 24
Peak memory 183068 kb
Host smart-3b165785-5383-4549-b1e6-c740d252660b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914257457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1914257457
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.2502505660
Short name T180
Test name
Test status
Simulation time 271944948345 ps
CPU time 121.78 seconds
Started Jul 04 05:17:29 PM PDT 24
Finished Jul 04 05:19:31 PM PDT 24
Peak memory 191204 kb
Host smart-2ad2c85d-cd95-4f6d-a6bd-2d085240bd33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502505660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2502505660
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1241184509
Short name T64
Test name
Test status
Simulation time 115548210605 ps
CPU time 396.46 seconds
Started Jul 04 05:17:29 PM PDT 24
Finished Jul 04 05:24:06 PM PDT 24
Peak memory 183088 kb
Host smart-35413437-72bb-4008-b2d3-1558d7fdec54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241184509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1241184509
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.779469127
Short name T75
Test name
Test status
Simulation time 537984684141 ps
CPU time 386.77 seconds
Started Jul 04 05:17:24 PM PDT 24
Finished Jul 04 05:23:51 PM PDT 24
Peak memory 191268 kb
Host smart-72bb043e-8652-4fe1-b090-0ef1fb997b2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779469127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
779469127
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.2490183071
Short name T14
Test name
Test status
Simulation time 191425335629 ps
CPU time 374.23 seconds
Started Jul 04 05:17:24 PM PDT 24
Finished Jul 04 05:23:39 PM PDT 24
Peak memory 206024 kb
Host smart-a8015600-ba09-45fe-b4e8-78d53230297c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490183071 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.2490183071
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_random.4031040732
Short name T281
Test name
Test status
Simulation time 33794721178 ps
CPU time 179.44 seconds
Started Jul 04 05:17:23 PM PDT 24
Finished Jul 04 05:20:23 PM PDT 24
Peak memory 183048 kb
Host smart-6aad4875-ced4-4919-bc6a-22b36a7126c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031040732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4031040732
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3416409605
Short name T357
Test name
Test status
Simulation time 832673341 ps
CPU time 2.21 seconds
Started Jul 04 05:17:28 PM PDT 24
Finished Jul 04 05:17:31 PM PDT 24
Peak memory 183000 kb
Host smart-bb9e232d-1536-47c6-baa4-e5aced59c815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416409605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3416409605
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.12875550
Short name T321
Test name
Test status
Simulation time 2450951356530 ps
CPU time 1113.61 seconds
Started Jul 04 05:17:24 PM PDT 24
Finished Jul 04 05:35:58 PM PDT 24
Peak memory 183068 kb
Host smart-65a9f432-3e13-4151-87c2-ea316b3ce99d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12875550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.rv_timer_cfg_update_on_fly.12875550
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1239092570
Short name T371
Test name
Test status
Simulation time 279721777251 ps
CPU time 100.85 seconds
Started Jul 04 05:17:24 PM PDT 24
Finished Jul 04 05:19:05 PM PDT 24
Peak memory 183080 kb
Host smart-fe0e369a-1dc2-4522-971e-10523427d416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239092570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1239092570
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1740344102
Short name T301
Test name
Test status
Simulation time 524855512251 ps
CPU time 693.17 seconds
Started Jul 04 05:17:23 PM PDT 24
Finished Jul 04 05:28:57 PM PDT 24
Peak memory 191196 kb
Host smart-d11661b3-deea-43a7-859d-aa7d5fd9ad74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740344102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1740344102
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1352487514
Short name T440
Test name
Test status
Simulation time 330058539 ps
CPU time 0.97 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:17:35 PM PDT 24
Peak memory 182952 kb
Host smart-76552738-f043-406e-84db-4672b3dbf64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352487514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1352487514
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1193080437
Short name T362
Test name
Test status
Simulation time 22192715 ps
CPU time 0.55 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:17:35 PM PDT 24
Peak memory 182948 kb
Host smart-3671ec6b-dadd-4686-824b-c457c4267d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193080437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1193080437
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1215509454
Short name T121
Test name
Test status
Simulation time 47814585545 ps
CPU time 83.26 seconds
Started Jul 04 05:17:36 PM PDT 24
Finished Jul 04 05:18:59 PM PDT 24
Peak memory 183000 kb
Host smart-b07ad97b-273f-4fcc-a2c6-7dd336bc0ce3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215509454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1215509454
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.103624017
Short name T81
Test name
Test status
Simulation time 200542636743 ps
CPU time 153.35 seconds
Started Jul 04 05:17:24 PM PDT 24
Finished Jul 04 05:19:58 PM PDT 24
Peak memory 183020 kb
Host smart-ffd29617-ff20-4eea-9392-d2b9d2f1676e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103624017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.103624017
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1057044286
Short name T426
Test name
Test status
Simulation time 76946614425 ps
CPU time 434.46 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:24:48 PM PDT 24
Peak memory 183096 kb
Host smart-6bc948b1-0276-4e86-a808-7ba87d2ca03c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057044286 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1057044286
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.262687291
Short name T6
Test name
Test status
Simulation time 52449888991 ps
CPU time 77.4 seconds
Started Jul 04 05:17:29 PM PDT 24
Finished Jul 04 05:18:46 PM PDT 24
Peak memory 182984 kb
Host smart-35411c45-2eef-46d3-a45a-70e42fac4c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262687291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.262687291
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.940598210
Short name T345
Test name
Test status
Simulation time 566077938214 ps
CPU time 300.35 seconds
Started Jul 04 05:17:23 PM PDT 24
Finished Jul 04 05:22:24 PM PDT 24
Peak memory 183056 kb
Host smart-97e523d2-81d6-47f9-bace-2011debc9b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940598210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
940598210
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2466495812
Short name T325
Test name
Test status
Simulation time 2030818481757 ps
CPU time 1082.53 seconds
Started Jul 04 05:17:24 PM PDT 24
Finished Jul 04 05:35:27 PM PDT 24
Peak memory 183028 kb
Host smart-b8dbea36-8ee2-4c28-8213-c977352ce3de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466495812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2466495812
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.441042123
Short name T79
Test name
Test status
Simulation time 85544111233 ps
CPU time 119.76 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:19:34 PM PDT 24
Peak memory 183092 kb
Host smart-b168eb95-05bf-4b17-9d44-445ef35278e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441042123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.441042123
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3941201059
Short name T144
Test name
Test status
Simulation time 115395550660 ps
CPU time 336.96 seconds
Started Jul 04 05:17:23 PM PDT 24
Finished Jul 04 05:23:00 PM PDT 24
Peak memory 191268 kb
Host smart-db3688ae-d599-456a-b5b0-2f625ccac54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941201059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3941201059
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.462109603
Short name T322
Test name
Test status
Simulation time 394711785577 ps
CPU time 678.38 seconds
Started Jul 04 05:17:28 PM PDT 24
Finished Jul 04 05:28:46 PM PDT 24
Peak memory 183056 kb
Host smart-37300b00-11b9-4cfc-8f32-d948694b1286
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462109603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.462109603
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.4000327718
Short name T409
Test name
Test status
Simulation time 591963540801 ps
CPU time 233.83 seconds
Started Jul 04 05:17:29 PM PDT 24
Finished Jul 04 05:21:23 PM PDT 24
Peak memory 183092 kb
Host smart-f479e34d-43b6-4bac-b574-867bcd670c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000327718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.4000327718
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2492759514
Short name T154
Test name
Test status
Simulation time 390757418331 ps
CPU time 723.37 seconds
Started Jul 04 05:17:27 PM PDT 24
Finished Jul 04 05:29:31 PM PDT 24
Peak memory 191236 kb
Host smart-b31e7a0f-9068-4b5a-aac7-803aa6746cb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492759514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2492759514
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2717206190
Short name T258
Test name
Test status
Simulation time 197341059847 ps
CPU time 680.14 seconds
Started Jul 04 05:17:25 PM PDT 24
Finished Jul 04 05:28:45 PM PDT 24
Peak memory 183052 kb
Host smart-5386ee87-597e-42af-b661-5eafa850a26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717206190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2717206190
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.4038353789
Short name T293
Test name
Test status
Simulation time 214566859638 ps
CPU time 1882.52 seconds
Started Jul 04 05:17:30 PM PDT 24
Finished Jul 04 05:48:53 PM PDT 24
Peak memory 191268 kb
Host smart-124a774a-03a8-45e7-b3d7-6698f377d406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038353789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.4038353789
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.4278835807
Short name T420
Test name
Test status
Simulation time 166121072695 ps
CPU time 130.73 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:19:44 PM PDT 24
Peak memory 183084 kb
Host smart-881ab7e6-0255-4350-9f23-3e245542e457
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278835807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.4278835807
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3184439497
Short name T369
Test name
Test status
Simulation time 23076459489 ps
CPU time 4.46 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:17:39 PM PDT 24
Peak memory 183028 kb
Host smart-333f8f72-f47b-4791-8f6c-227a5c2d9da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184439497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3184439497
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.135887030
Short name T404
Test name
Test status
Simulation time 107880750646 ps
CPU time 137.06 seconds
Started Jul 04 05:17:38 PM PDT 24
Finished Jul 04 05:19:55 PM PDT 24
Peak memory 183088 kb
Host smart-4d262d17-6d3b-4194-ae9b-c31c7396beab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135887030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.135887030
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1801372147
Short name T88
Test name
Test status
Simulation time 160633156816 ps
CPU time 76.24 seconds
Started Jul 04 05:17:36 PM PDT 24
Finished Jul 04 05:18:53 PM PDT 24
Peak memory 183088 kb
Host smart-fc728490-cc88-4755-9fc8-f35e8fc270c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801372147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1801372147
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1416875603
Short name T28
Test name
Test status
Simulation time 757979009651 ps
CPU time 301.73 seconds
Started Jul 04 05:17:35 PM PDT 24
Finished Jul 04 05:22:37 PM PDT 24
Peak memory 191308 kb
Host smart-45d0c0c4-8a96-46e6-87d9-f6bc5b1b94cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416875603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1416875603
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3598121083
Short name T59
Test name
Test status
Simulation time 20371831536 ps
CPU time 17.84 seconds
Started Jul 04 05:17:35 PM PDT 24
Finished Jul 04 05:17:54 PM PDT 24
Peak memory 183088 kb
Host smart-46dfc41d-f70f-4c54-9254-480d24dc59c4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598121083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3598121083
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.126934522
Short name T372
Test name
Test status
Simulation time 519725408894 ps
CPU time 193.5 seconds
Started Jul 04 05:17:38 PM PDT 24
Finished Jul 04 05:20:51 PM PDT 24
Peak memory 183080 kb
Host smart-d5108260-5004-436e-85e7-92e1b4b607ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126934522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.126934522
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.83848548
Short name T179
Test name
Test status
Simulation time 140892711103 ps
CPU time 236.3 seconds
Started Jul 04 05:17:35 PM PDT 24
Finished Jul 04 05:21:31 PM PDT 24
Peak memory 191212 kb
Host smart-cf7d76c9-2c9e-4ada-acae-d7709bbf3cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83848548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.83848548
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3442714729
Short name T352
Test name
Test status
Simulation time 76420992753 ps
CPU time 55.22 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:18:29 PM PDT 24
Peak memory 193580 kb
Host smart-a31fa08d-de10-4f16-bd10-49bc46c79221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442714729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3442714729
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.562567763
Short name T127
Test name
Test status
Simulation time 1037086949635 ps
CPU time 2096.24 seconds
Started Jul 04 05:17:35 PM PDT 24
Finished Jul 04 05:52:32 PM PDT 24
Peak memory 191324 kb
Host smart-805862d8-d92f-43f4-9fdf-9eb78dd81700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562567763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
562567763
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.4124053362
Short name T85
Test name
Test status
Simulation time 73094408475 ps
CPU time 115.82 seconds
Started Jul 04 05:17:31 PM PDT 24
Finished Jul 04 05:19:27 PM PDT 24
Peak memory 183040 kb
Host smart-a105600a-926b-4ff0-b9d0-97854d6e22b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124053362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.4124053362
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1032169923
Short name T428
Test name
Test status
Simulation time 144365184476 ps
CPU time 93.71 seconds
Started Jul 04 05:17:30 PM PDT 24
Finished Jul 04 05:19:04 PM PDT 24
Peak memory 183036 kb
Host smart-d3a45d88-5718-480c-a0cc-9f81dea2645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032169923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1032169923
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1502047227
Short name T164
Test name
Test status
Simulation time 11918010160 ps
CPU time 21.73 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:17:56 PM PDT 24
Peak memory 191212 kb
Host smart-3910dcd3-6139-4670-ab62-e6b92a8fb3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502047227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1502047227
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3160156847
Short name T303
Test name
Test status
Simulation time 30376709269 ps
CPU time 11.64 seconds
Started Jul 04 05:17:35 PM PDT 24
Finished Jul 04 05:17:47 PM PDT 24
Peak memory 182980 kb
Host smart-237d5660-070f-496f-aca1-2e345bd1c37d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160156847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3160156847
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.3098088108
Short name T400
Test name
Test status
Simulation time 17822369770 ps
CPU time 25.51 seconds
Started Jul 04 05:17:37 PM PDT 24
Finished Jul 04 05:18:02 PM PDT 24
Peak memory 183064 kb
Host smart-50eca962-f403-45bd-bd47-eeb77857f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098088108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.3098088108
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3163884693
Short name T132
Test name
Test status
Simulation time 257386989923 ps
CPU time 2251.54 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:55:05 PM PDT 24
Peak memory 191256 kb
Host smart-08d3e777-2d79-4a3a-83ab-3113300aab4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163884693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3163884693
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.768497515
Short name T309
Test name
Test status
Simulation time 113131610769 ps
CPU time 81.97 seconds
Started Jul 04 05:17:34 PM PDT 24
Finished Jul 04 05:18:56 PM PDT 24
Peak memory 191296 kb
Host smart-d7b085c2-b866-4f27-a0e4-10a1d5e75917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768497515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.768497515
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3096656242
Short name T406
Test name
Test status
Simulation time 8899067221 ps
CPU time 8.51 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:17:09 PM PDT 24
Peak memory 183000 kb
Host smart-f12fe55f-2541-47e5-8610-687bce6a8d7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096656242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3096656242
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.545805665
Short name T427
Test name
Test status
Simulation time 446680019000 ps
CPU time 164.31 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:19:45 PM PDT 24
Peak memory 183064 kb
Host smart-d730bb1e-f356-4c93-b469-7543a87d3c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545805665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.545805665
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2249172232
Short name T176
Test name
Test status
Simulation time 38636116031 ps
CPU time 61.49 seconds
Started Jul 04 05:17:01 PM PDT 24
Finished Jul 04 05:18:03 PM PDT 24
Peak memory 183024 kb
Host smart-5481f749-71f1-4221-bcce-81175548950a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249172232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2249172232
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.757918362
Short name T17
Test name
Test status
Simulation time 127381657 ps
CPU time 0.8 seconds
Started Jul 04 05:16:59 PM PDT 24
Finished Jul 04 05:17:00 PM PDT 24
Peak memory 213388 kb
Host smart-f8bda394-516b-4078-ae1e-07b2caf2946a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757918362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.757918362
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1105698644
Short name T441
Test name
Test status
Simulation time 458349150241 ps
CPU time 371.83 seconds
Started Jul 04 05:16:58 PM PDT 24
Finished Jul 04 05:23:10 PM PDT 24
Peak memory 191248 kb
Host smart-dad3ed34-6485-4015-9f00-341a0a5d24df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105698644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1105698644
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1189970456
Short name T350
Test name
Test status
Simulation time 243685517098 ps
CPU time 126.11 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:19:39 PM PDT 24
Peak memory 183076 kb
Host smart-1faac594-0f84-4079-9ce9-fe057a05ed3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189970456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1189970456
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2669314227
Short name T382
Test name
Test status
Simulation time 589233784337 ps
CPU time 96.59 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:19:10 PM PDT 24
Peak memory 183068 kb
Host smart-8d54a4f3-1517-4655-88ac-7d663a376cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669314227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2669314227
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3503511148
Short name T42
Test name
Test status
Simulation time 126838430072 ps
CPU time 287.12 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:22:20 PM PDT 24
Peak memory 191264 kb
Host smart-64b10f48-e826-49ab-974a-143bc7421cf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503511148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3503511148
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.416598373
Short name T436
Test name
Test status
Simulation time 64796025 ps
CPU time 0.63 seconds
Started Jul 04 05:17:41 PM PDT 24
Finished Jul 04 05:17:42 PM PDT 24
Peak memory 182900 kb
Host smart-1a0372d5-d5b8-4fd9-9a86-6e218ae32894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416598373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.416598373
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2127996550
Short name T151
Test name
Test status
Simulation time 18673128650 ps
CPU time 29.99 seconds
Started Jul 04 05:17:31 PM PDT 24
Finished Jul 04 05:18:01 PM PDT 24
Peak memory 183048 kb
Host smart-8270ac17-f018-4553-b8d3-56fa37433377
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127996550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2127996550
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3661433670
Short name T381
Test name
Test status
Simulation time 814622125538 ps
CPU time 276.13 seconds
Started Jul 04 05:17:32 PM PDT 24
Finished Jul 04 05:22:08 PM PDT 24
Peak memory 183080 kb
Host smart-7cc685c6-c4c7-425b-9939-8e52d9bab109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661433670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3661433670
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2067475946
Short name T207
Test name
Test status
Simulation time 249414788970 ps
CPU time 487.98 seconds
Started Jul 04 05:17:36 PM PDT 24
Finished Jul 04 05:25:44 PM PDT 24
Peak memory 194848 kb
Host smart-d2ff07ea-3aae-4cc4-9f07-d2f38f3deb53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067475946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2067475946
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3866024542
Short name T232
Test name
Test status
Simulation time 265051845099 ps
CPU time 281.44 seconds
Started Jul 04 05:17:41 PM PDT 24
Finished Jul 04 05:22:23 PM PDT 24
Peak memory 191268 kb
Host smart-3d3c178c-9d43-4c77-a4dc-3b229e1fcef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866024542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3866024542
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.107172290
Short name T184
Test name
Test status
Simulation time 624389009698 ps
CPU time 531.53 seconds
Started Jul 04 05:17:31 PM PDT 24
Finished Jul 04 05:26:22 PM PDT 24
Peak memory 183032 kb
Host smart-016b131b-ade5-47a4-a893-556915f7e2b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107172290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.107172290
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.758935253
Short name T388
Test name
Test status
Simulation time 70666380323 ps
CPU time 95.7 seconds
Started Jul 04 05:17:35 PM PDT 24
Finished Jul 04 05:19:11 PM PDT 24
Peak memory 183024 kb
Host smart-47489a18-449b-47db-8b7d-c1df7e207d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758935253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.758935253
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1468565645
Short name T199
Test name
Test status
Simulation time 176506815749 ps
CPU time 181.16 seconds
Started Jul 04 05:17:31 PM PDT 24
Finished Jul 04 05:20:32 PM PDT 24
Peak memory 191280 kb
Host smart-179a4eb2-003f-4aa8-82e2-f8874d4faa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468565645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1468565645
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2747773526
Short name T403
Test name
Test status
Simulation time 436832761114 ps
CPU time 158.3 seconds
Started Jul 04 05:17:31 PM PDT 24
Finished Jul 04 05:20:10 PM PDT 24
Peak memory 194016 kb
Host smart-63c7ce95-7b50-406a-892d-f5b3e668af78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747773526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2747773526
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3340141478
Short name T187
Test name
Test status
Simulation time 240523826142 ps
CPU time 326.36 seconds
Started Jul 04 05:17:30 PM PDT 24
Finished Jul 04 05:22:57 PM PDT 24
Peak memory 183060 kb
Host smart-741faa46-caa3-455a-98c0-cc4cfa99b7f5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340141478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3340141478
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.551076738
Short name T365
Test name
Test status
Simulation time 316240455468 ps
CPU time 258.02 seconds
Started Jul 04 05:17:41 PM PDT 24
Finished Jul 04 05:21:59 PM PDT 24
Peak memory 183048 kb
Host smart-5a0685e8-ddbe-4a01-94d1-80437cdf0faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551076738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.551076738
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.4037901844
Short name T393
Test name
Test status
Simulation time 74784183 ps
CPU time 0.55 seconds
Started Jul 04 05:17:30 PM PDT 24
Finished Jul 04 05:17:31 PM PDT 24
Peak memory 182900 kb
Host smart-c4a3a06c-17e3-44b4-8e05-7424286e7464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037901844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.4037901844
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2308651337
Short name T67
Test name
Test status
Simulation time 271985960300 ps
CPU time 757.86 seconds
Started Jul 04 05:17:35 PM PDT 24
Finished Jul 04 05:30:14 PM PDT 24
Peak memory 196228 kb
Host smart-4cc080fb-abcb-4614-906b-ac963356eda6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308651337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2308651337
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.193552381
Short name T256
Test name
Test status
Simulation time 152019349640 ps
CPU time 161.18 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:20:14 PM PDT 24
Peak memory 183032 kb
Host smart-fb4be26d-7d4e-4976-a848-6534008cbaa6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193552381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.193552381
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3683165974
Short name T23
Test name
Test status
Simulation time 34424810374 ps
CPU time 55.37 seconds
Started Jul 04 05:17:31 PM PDT 24
Finished Jul 04 05:18:26 PM PDT 24
Peak memory 183080 kb
Host smart-2c2ea1bd-565a-4dda-b9a3-e9496dc75dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683165974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3683165974
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3311172580
Short name T267
Test name
Test status
Simulation time 210347744362 ps
CPU time 37.3 seconds
Started Jul 04 05:17:39 PM PDT 24
Finished Jul 04 05:18:16 PM PDT 24
Peak memory 194108 kb
Host smart-fb463ebf-17ca-459d-b128-7eddfe1063ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311172580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3311172580
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3957601839
Short name T385
Test name
Test status
Simulation time 39876604177 ps
CPU time 53.25 seconds
Started Jul 04 05:17:33 PM PDT 24
Finished Jul 04 05:18:26 PM PDT 24
Peak memory 194716 kb
Host smart-0fd469c0-137a-4690-bd7c-e783f55c2301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957601839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3957601839
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1567864053
Short name T398
Test name
Test status
Simulation time 218019469000 ps
CPU time 93.14 seconds
Started Jul 04 05:17:30 PM PDT 24
Finished Jul 04 05:19:03 PM PDT 24
Peak memory 183068 kb
Host smart-a7034dac-aba7-4ccf-963a-0015350c7f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567864053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1567864053
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.656554916
Short name T286
Test name
Test status
Simulation time 1378538110407 ps
CPU time 911.23 seconds
Started Jul 04 05:17:40 PM PDT 24
Finished Jul 04 05:32:52 PM PDT 24
Peak memory 191248 kb
Host smart-15607e05-255a-406a-ac0e-08267f17f873
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656554916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.656554916
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3526412954
Short name T280
Test name
Test status
Simulation time 208697801831 ps
CPU time 85.45 seconds
Started Jul 04 05:17:32 PM PDT 24
Finished Jul 04 05:18:58 PM PDT 24
Peak memory 182992 kb
Host smart-1e76a84c-7220-4cdc-9ee1-bd9a44744092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526412954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3526412954
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3182395122
Short name T71
Test name
Test status
Simulation time 1467205866254 ps
CPU time 893.58 seconds
Started Jul 04 05:17:35 PM PDT 24
Finished Jul 04 05:32:29 PM PDT 24
Peak memory 191236 kb
Host smart-f361da94-5612-49f8-8a55-6622c3c0028a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182395122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3182395122
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2224660441
Short name T172
Test name
Test status
Simulation time 367021154182 ps
CPU time 563.89 seconds
Started Jul 04 05:17:38 PM PDT 24
Finished Jul 04 05:27:02 PM PDT 24
Peak memory 183020 kb
Host smart-a0131a7c-ca31-40ef-b75e-3b0172a61a0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224660441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2224660441
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2189662506
Short name T386
Test name
Test status
Simulation time 340983228778 ps
CPU time 99 seconds
Started Jul 04 05:17:38 PM PDT 24
Finished Jul 04 05:19:17 PM PDT 24
Peak memory 183104 kb
Host smart-6a09ddcd-402f-4ae4-a045-b9fd3e326c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189662506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2189662506
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3805757820
Short name T315
Test name
Test status
Simulation time 115755149550 ps
CPU time 87.41 seconds
Started Jul 04 05:17:39 PM PDT 24
Finished Jul 04 05:19:06 PM PDT 24
Peak memory 183084 kb
Host smart-a0a45a28-ab21-47d9-82d9-31dee318c1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805757820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3805757820
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.37776866
Short name T391
Test name
Test status
Simulation time 143852068217 ps
CPU time 211.84 seconds
Started Jul 04 05:17:37 PM PDT 24
Finished Jul 04 05:21:09 PM PDT 24
Peak memory 183088 kb
Host smart-d622040b-d859-4336-9070-69aaa2ae4c11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37776866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all.37776866
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3875297763
Short name T240
Test name
Test status
Simulation time 371436276460 ps
CPU time 318.17 seconds
Started Jul 04 05:17:37 PM PDT 24
Finished Jul 04 05:22:56 PM PDT 24
Peak memory 183052 kb
Host smart-0f9449a5-04c0-4789-85c0-b88de37ddecc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875297763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3875297763
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2671828770
Short name T434
Test name
Test status
Simulation time 431241722615 ps
CPU time 185.14 seconds
Started Jul 04 05:17:39 PM PDT 24
Finished Jul 04 05:20:44 PM PDT 24
Peak memory 183072 kb
Host smart-1b05ee00-3479-43c0-8bb6-9e47d3c06ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671828770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2671828770
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.325006397
Short name T329
Test name
Test status
Simulation time 142999610818 ps
CPU time 221.19 seconds
Started Jul 04 05:17:37 PM PDT 24
Finished Jul 04 05:21:18 PM PDT 24
Peak memory 193488 kb
Host smart-26d3dd28-a49a-4042-aa05-161b6b1f946b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325006397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.325006397
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2356425677
Short name T27
Test name
Test status
Simulation time 57510586993 ps
CPU time 47.23 seconds
Started Jul 04 05:17:38 PM PDT 24
Finished Jul 04 05:18:26 PM PDT 24
Peak memory 194796 kb
Host smart-57401d0a-bf19-4ace-9375-c135ea576c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356425677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2356425677
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2038491346
Short name T416
Test name
Test status
Simulation time 694793639550 ps
CPU time 325.18 seconds
Started Jul 04 05:17:38 PM PDT 24
Finished Jul 04 05:23:03 PM PDT 24
Peak memory 191304 kb
Host smart-0abbf9bf-41f2-487e-a43d-3d2de05f2bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038491346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2038491346
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3318081924
Short name T141
Test name
Test status
Simulation time 293061041138 ps
CPU time 502.74 seconds
Started Jul 04 05:17:40 PM PDT 24
Finished Jul 04 05:26:03 PM PDT 24
Peak memory 183076 kb
Host smart-df160dde-e929-44a3-b654-506e1138f735
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318081924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3318081924
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1730708273
Short name T402
Test name
Test status
Simulation time 589540845707 ps
CPU time 268.49 seconds
Started Jul 04 05:17:37 PM PDT 24
Finished Jul 04 05:22:06 PM PDT 24
Peak memory 183048 kb
Host smart-a5512ded-3f37-4c9f-ae2b-0e1d8c0015cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730708273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1730708273
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3607122956
Short name T205
Test name
Test status
Simulation time 192062372156 ps
CPU time 505.56 seconds
Started Jul 04 05:17:38 PM PDT 24
Finished Jul 04 05:26:04 PM PDT 24
Peak memory 191268 kb
Host smart-90fcb481-d338-4850-aed7-a91d9cfa04b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607122956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3607122956
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2940395211
Short name T195
Test name
Test status
Simulation time 9302725473 ps
CPU time 13.3 seconds
Started Jul 04 05:17:37 PM PDT 24
Finished Jul 04 05:17:51 PM PDT 24
Peak memory 183080 kb
Host smart-be3e7943-ac67-4dc5-bb0c-3ccf2a59d758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940395211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2940395211
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2784971405
Short name T361
Test name
Test status
Simulation time 213474025 ps
CPU time 0.53 seconds
Started Jul 04 05:17:39 PM PDT 24
Finished Jul 04 05:17:40 PM PDT 24
Peak memory 182944 kb
Host smart-23bf8e38-fa73-43f4-9bd8-178e419b49c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784971405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2784971405
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3444791036
Short name T165
Test name
Test status
Simulation time 508405819532 ps
CPU time 761.14 seconds
Started Jul 04 05:17:40 PM PDT 24
Finished Jul 04 05:30:21 PM PDT 24
Peak memory 183084 kb
Host smart-c0178f1a-172e-4852-aa0c-53c496f70944
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444791036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3444791036
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3170428907
Short name T358
Test name
Test status
Simulation time 161904192211 ps
CPU time 42.52 seconds
Started Jul 04 05:17:40 PM PDT 24
Finished Jul 04 05:18:22 PM PDT 24
Peak memory 183068 kb
Host smart-92cb973f-b639-4f7d-8fa9-5edf5a0e747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170428907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3170428907
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.614703088
Short name T383
Test name
Test status
Simulation time 358833535 ps
CPU time 1.08 seconds
Started Jul 04 05:17:47 PM PDT 24
Finished Jul 04 05:17:48 PM PDT 24
Peak memory 183044 kb
Host smart-abbd3130-ec9d-481e-9923-ffa8c0cdbd28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614703088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.614703088
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2190233156
Short name T4
Test name
Test status
Simulation time 66084781460 ps
CPU time 29.09 seconds
Started Jul 04 05:17:15 PM PDT 24
Finished Jul 04 05:17:44 PM PDT 24
Peak memory 183048 kb
Host smart-b5c9ede9-e1b0-4f96-bedd-441083855b3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190233156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2190233156
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1810689181
Short name T366
Test name
Test status
Simulation time 54816765080 ps
CPU time 62.35 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:18:14 PM PDT 24
Peak memory 183036 kb
Host smart-e55aa252-a95e-4856-b28e-65e94cc5cab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810689181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1810689181
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2665077470
Short name T311
Test name
Test status
Simulation time 327630011522 ps
CPU time 226.72 seconds
Started Jul 04 05:17:00 PM PDT 24
Finished Jul 04 05:20:47 PM PDT 24
Peak memory 191288 kb
Host smart-e5986a50-932a-4a6e-a56f-e843178365d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665077470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2665077470
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.654793217
Short name T249
Test name
Test status
Simulation time 181021572558 ps
CPU time 52.2 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:18:02 PM PDT 24
Peak memory 183056 kb
Host smart-80ed3eff-de76-4e54-bad8-d724354a0670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654793217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.654793217
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3101581237
Short name T74
Test name
Test status
Simulation time 24189113 ps
CPU time 0.58 seconds
Started Jul 04 05:17:07 PM PDT 24
Finished Jul 04 05:17:08 PM PDT 24
Peak memory 182908 kb
Host smart-a64ba6af-f6ff-4b56-9507-5097cef104ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101581237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3101581237
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.2077195227
Short name T116
Test name
Test status
Simulation time 375346525225 ps
CPU time 642.89 seconds
Started Jul 04 05:17:46 PM PDT 24
Finished Jul 04 05:28:29 PM PDT 24
Peak memory 191216 kb
Host smart-26b0e018-6a23-45f0-99e9-7ec85b37226e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077195227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2077195227
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3530885260
Short name T1
Test name
Test status
Simulation time 22215628042 ps
CPU time 37.72 seconds
Started Jul 04 05:17:46 PM PDT 24
Finished Jul 04 05:18:24 PM PDT 24
Peak memory 191296 kb
Host smart-1e7a6fa2-c226-49b5-9178-566c5b611f51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530885260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3530885260
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1184508794
Short name T340
Test name
Test status
Simulation time 100813783478 ps
CPU time 29.13 seconds
Started Jul 04 05:17:45 PM PDT 24
Finished Jul 04 05:18:15 PM PDT 24
Peak memory 183088 kb
Host smart-348e7543-0653-41e0-9c35-d1cd94ae5b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184508794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1184508794
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1936524730
Short name T265
Test name
Test status
Simulation time 63373447059 ps
CPU time 103.86 seconds
Started Jul 04 05:17:47 PM PDT 24
Finished Jul 04 05:19:31 PM PDT 24
Peak memory 191216 kb
Host smart-5d45f741-a2f0-466c-8de1-e548dfa6b2e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936524730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1936524730
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3083997455
Short name T125
Test name
Test status
Simulation time 416400550963 ps
CPU time 1059.97 seconds
Started Jul 04 05:17:48 PM PDT 24
Finished Jul 04 05:35:28 PM PDT 24
Peak memory 191296 kb
Host smart-d212e9a8-c2d0-4e31-9814-4cf0c4923da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083997455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3083997455
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.595872144
Short name T331
Test name
Test status
Simulation time 87828147565 ps
CPU time 76.98 seconds
Started Jul 04 05:17:47 PM PDT 24
Finished Jul 04 05:19:04 PM PDT 24
Peak memory 183064 kb
Host smart-ab6924a8-5b52-4ebb-afdd-56d388bf7292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595872144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.595872144
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3393290785
Short name T397
Test name
Test status
Simulation time 113727873622 ps
CPU time 49.48 seconds
Started Jul 04 05:17:47 PM PDT 24
Finished Jul 04 05:18:37 PM PDT 24
Peak memory 183096 kb
Host smart-a4be30b8-d7e2-45ae-bc59-54ac02f375e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393290785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3393290785
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2143034485
Short name T211
Test name
Test status
Simulation time 42878353461 ps
CPU time 311.09 seconds
Started Jul 04 05:17:46 PM PDT 24
Finished Jul 04 05:22:58 PM PDT 24
Peak memory 193812 kb
Host smart-cac20ab1-56a7-43cf-a90d-b9dce12f4310
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143034485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2143034485
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1366643439
Short name T269
Test name
Test status
Simulation time 246959511798 ps
CPU time 390.73 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:23:43 PM PDT 24
Peak memory 183072 kb
Host smart-b521ec6c-a32c-4af3-8d12-8726a332a558
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366643439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1366643439
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.299334564
Short name T390
Test name
Test status
Simulation time 404193913950 ps
CPU time 90.44 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:18:41 PM PDT 24
Peak memory 183068 kb
Host smart-abee393b-dae9-45a1-ab7b-05930fe24695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299334564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.299334564
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.4158678554
Short name T380
Test name
Test status
Simulation time 174909196 ps
CPU time 0.7 seconds
Started Jul 04 05:17:08 PM PDT 24
Finished Jul 04 05:17:09 PM PDT 24
Peak memory 182940 kb
Host smart-8ae783d2-3751-481a-821b-2080bfa412ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158678554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.4158678554
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.320536850
Short name T158
Test name
Test status
Simulation time 411390714588 ps
CPU time 1570.08 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:43:22 PM PDT 24
Peak memory 196288 kb
Host smart-3b5cd6c6-1500-4086-accc-bc7dc5ad5a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320536850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.320536850
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.449075263
Short name T123
Test name
Test status
Simulation time 390020558292 ps
CPU time 216.22 seconds
Started Jul 04 05:17:46 PM PDT 24
Finished Jul 04 05:21:22 PM PDT 24
Peak memory 191280 kb
Host smart-f02619a6-848a-408a-8409-9fdb82a1e610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449075263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.449075263
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2174817227
Short name T183
Test name
Test status
Simulation time 143587090590 ps
CPU time 43.25 seconds
Started Jul 04 05:17:54 PM PDT 24
Finished Jul 04 05:18:37 PM PDT 24
Peak memory 191272 kb
Host smart-4a9894a8-ce1e-45ed-bfce-e16aee9b0fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174817227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2174817227
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.881803845
Short name T135
Test name
Test status
Simulation time 194314119110 ps
CPU time 845.94 seconds
Started Jul 04 05:17:56 PM PDT 24
Finished Jul 04 05:32:02 PM PDT 24
Peak memory 194996 kb
Host smart-c95257af-cd7d-41c5-b2a1-b6b00e1bb327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881803845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.881803845
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.4158945769
Short name T272
Test name
Test status
Simulation time 86311002561 ps
CPU time 85.26 seconds
Started Jul 04 05:17:56 PM PDT 24
Finished Jul 04 05:19:21 PM PDT 24
Peak memory 191296 kb
Host smart-32e3dedf-e453-47b5-aa1e-cf1adcc67910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158945769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4158945769
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3909261988
Short name T60
Test name
Test status
Simulation time 209646419211 ps
CPU time 180.95 seconds
Started Jul 04 05:17:56 PM PDT 24
Finished Jul 04 05:20:57 PM PDT 24
Peak memory 191284 kb
Host smart-08393944-3720-4fed-9526-b69a1e0a9125
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909261988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3909261988
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1366489439
Short name T349
Test name
Test status
Simulation time 181197508030 ps
CPU time 485.99 seconds
Started Jul 04 05:17:55 PM PDT 24
Finished Jul 04 05:26:01 PM PDT 24
Peak memory 191276 kb
Host smart-9cfb4f0a-4254-4217-a3eb-42fc8eca3242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366489439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1366489439
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1687222880
Short name T29
Test name
Test status
Simulation time 48988092201 ps
CPU time 31.26 seconds
Started Jul 04 05:17:56 PM PDT 24
Finished Jul 04 05:18:27 PM PDT 24
Peak memory 183000 kb
Host smart-9af87597-cd1a-442a-bfb6-af00748f00b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687222880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1687222880
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.406956269
Short name T319
Test name
Test status
Simulation time 103496256952 ps
CPU time 146.28 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:19:38 PM PDT 24
Peak memory 183008 kb
Host smart-3d7ea218-0e76-45a5-9d52-fd4974a6a561
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406956269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.406956269
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2295826120
Short name T377
Test name
Test status
Simulation time 101638646619 ps
CPU time 136.82 seconds
Started Jul 04 05:17:06 PM PDT 24
Finished Jul 04 05:19:23 PM PDT 24
Peak memory 183088 kb
Host smart-fb4214ff-57d2-447a-9d17-179cb571f66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295826120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2295826120
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.233488220
Short name T423
Test name
Test status
Simulation time 109506917 ps
CPU time 0.75 seconds
Started Jul 04 05:17:13 PM PDT 24
Finished Jul 04 05:17:15 PM PDT 24
Peak memory 182816 kb
Host smart-2716fa06-674a-4000-ad49-91b1a7279323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233488220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.233488220
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.1440189926
Short name T421
Test name
Test status
Simulation time 48735187647 ps
CPU time 126.97 seconds
Started Jul 04 05:17:53 PM PDT 24
Finished Jul 04 05:20:00 PM PDT 24
Peak memory 191276 kb
Host smart-5ba989fb-56bb-4108-b90d-ba861fc760bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440189926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.1440189926
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3012600284
Short name T279
Test name
Test status
Simulation time 177543940825 ps
CPU time 161.45 seconds
Started Jul 04 05:17:56 PM PDT 24
Finished Jul 04 05:20:38 PM PDT 24
Peak memory 191284 kb
Host smart-a301b010-ae7b-430f-97c3-474014112ce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012600284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3012600284
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2318188128
Short name T297
Test name
Test status
Simulation time 181186865552 ps
CPU time 163.56 seconds
Started Jul 04 05:18:03 PM PDT 24
Finished Jul 04 05:20:46 PM PDT 24
Peak memory 191312 kb
Host smart-7c71525c-ac3c-4f27-ba26-597cbcb754ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318188128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2318188128
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2110543264
Short name T401
Test name
Test status
Simulation time 169939290857 ps
CPU time 71.58 seconds
Started Jul 04 05:18:03 PM PDT 24
Finished Jul 04 05:19:15 PM PDT 24
Peak memory 192464 kb
Host smart-b13b7a72-19b8-436f-bd98-d5d179d963da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110543264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2110543264
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.498083404
Short name T261
Test name
Test status
Simulation time 89847740566 ps
CPU time 348.66 seconds
Started Jul 04 05:18:03 PM PDT 24
Finished Jul 04 05:23:52 PM PDT 24
Peak memory 191288 kb
Host smart-0d859397-f357-4804-8ed9-6a7f9e14ccc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498083404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.498083404
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2908380929
Short name T155
Test name
Test status
Simulation time 88528424403 ps
CPU time 59.67 seconds
Started Jul 04 05:18:03 PM PDT 24
Finished Jul 04 05:19:03 PM PDT 24
Peak memory 183096 kb
Host smart-c5e72d2a-e125-4409-90c9-d25bd21f4957
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908380929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2908380929
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2854585244
Short name T78
Test name
Test status
Simulation time 34502472671 ps
CPU time 56.89 seconds
Started Jul 04 05:17:08 PM PDT 24
Finished Jul 04 05:18:05 PM PDT 24
Peak memory 183088 kb
Host smart-e3638605-a016-440e-b285-cdfde0e857cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854585244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2854585244
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.1006565629
Short name T7
Test name
Test status
Simulation time 75311127903 ps
CPU time 104.58 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:18:54 PM PDT 24
Peak memory 182772 kb
Host smart-b23333fa-5dfc-4c87-8ce3-65528177a1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006565629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.1006565629
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1469869720
Short name T139
Test name
Test status
Simulation time 125036757019 ps
CPU time 578.35 seconds
Started Jul 04 05:17:11 PM PDT 24
Finished Jul 04 05:26:50 PM PDT 24
Peak memory 191192 kb
Host smart-5f36bca8-d696-4688-ad1f-e1320c9857b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469869720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1469869720
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3893356538
Short name T5
Test name
Test status
Simulation time 63054152515 ps
CPU time 194.64 seconds
Started Jul 04 05:17:06 PM PDT 24
Finished Jul 04 05:20:21 PM PDT 24
Peak memory 191304 kb
Host smart-22f44673-ecbb-42ad-8f70-5dca9803e2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893356538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3893356538
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.576997687
Short name T162
Test name
Test status
Simulation time 220833373953 ps
CPU time 834.82 seconds
Started Jul 04 05:18:03 PM PDT 24
Finished Jul 04 05:31:58 PM PDT 24
Peak memory 191276 kb
Host smart-287f5a62-6f18-4178-8c3b-5cb0b0cab405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576997687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.576997687
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.826565751
Short name T411
Test name
Test status
Simulation time 12571764415 ps
CPU time 18.44 seconds
Started Jul 04 05:18:03 PM PDT 24
Finished Jul 04 05:18:22 PM PDT 24
Peak memory 183032 kb
Host smart-a3b3a753-1fa2-49ca-9873-c386a29d7ab2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826565751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.826565751
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.814903821
Short name T305
Test name
Test status
Simulation time 1198372776781 ps
CPU time 1993.86 seconds
Started Jul 04 05:18:04 PM PDT 24
Finished Jul 04 05:51:18 PM PDT 24
Peak memory 191272 kb
Host smart-d366a0d9-b28f-47a0-91ae-a2e1524cc1c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814903821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.814903821
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.709415390
Short name T203
Test name
Test status
Simulation time 156278798026 ps
CPU time 54.52 seconds
Started Jul 04 05:18:04 PM PDT 24
Finished Jul 04 05:18:59 PM PDT 24
Peak memory 191296 kb
Host smart-29c16451-f18e-4cab-8d8d-3b804974c8c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709415390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.709415390
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1337842861
Short name T351
Test name
Test status
Simulation time 49556939857 ps
CPU time 251.91 seconds
Started Jul 04 05:18:03 PM PDT 24
Finished Jul 04 05:22:15 PM PDT 24
Peak memory 191244 kb
Host smart-decdbba3-a6c6-48c1-a4cf-0f191d2e9da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337842861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1337842861
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.4226052931
Short name T346
Test name
Test status
Simulation time 26125791985 ps
CPU time 41.13 seconds
Started Jul 04 05:18:04 PM PDT 24
Finished Jul 04 05:18:45 PM PDT 24
Peak memory 182996 kb
Host smart-a3a0264d-0dec-4227-9664-4cfa867d507f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226052931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4226052931
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.82630156
Short name T291
Test name
Test status
Simulation time 835854622883 ps
CPU time 660.88 seconds
Started Jul 04 05:18:04 PM PDT 24
Finished Jul 04 05:29:05 PM PDT 24
Peak memory 191272 kb
Host smart-9633fb24-16aa-4aac-8ab0-2ae2571e3839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82630156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.82630156
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2323388469
Short name T347
Test name
Test status
Simulation time 24502981552 ps
CPU time 11.4 seconds
Started Jul 04 05:17:09 PM PDT 24
Finished Jul 04 05:17:21 PM PDT 24
Peak memory 183084 kb
Host smart-f4fdc133-e578-4ef2-82c4-21cd6ba5eb02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323388469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2323388469
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2277610533
Short name T77
Test name
Test status
Simulation time 258851700694 ps
CPU time 189.28 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:20:21 PM PDT 24
Peak memory 183016 kb
Host smart-8bb66a77-28d0-40eb-a511-12881744c73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277610533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2277610533
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.4169572808
Short name T150
Test name
Test status
Simulation time 157626791522 ps
CPU time 502.54 seconds
Started Jul 04 05:17:06 PM PDT 24
Finished Jul 04 05:25:28 PM PDT 24
Peak memory 191276 kb
Host smart-df431fc8-80e2-4d00-8367-196813f1b7d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169572808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.4169572808
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1553963134
Short name T140
Test name
Test status
Simulation time 348713276574 ps
CPU time 73.57 seconds
Started Jul 04 05:17:10 PM PDT 24
Finished Jul 04 05:18:24 PM PDT 24
Peak memory 191280 kb
Host smart-65bbc8b3-e4ff-484a-97bc-78e4360682eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553963134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1553963134
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2713850797
Short name T363
Test name
Test status
Simulation time 10844422350 ps
CPU time 16.98 seconds
Started Jul 04 05:17:08 PM PDT 24
Finished Jul 04 05:17:26 PM PDT 24
Peak memory 183032 kb
Host smart-52570429-695a-4b4c-ab3f-45148e121cca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713850797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2713850797
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.3127968168
Short name T244
Test name
Test status
Simulation time 129147518331 ps
CPU time 338.04 seconds
Started Jul 04 05:18:04 PM PDT 24
Finished Jul 04 05:23:42 PM PDT 24
Peak memory 191296 kb
Host smart-5358de73-4b80-4f4d-a58d-e4544245c695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127968168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3127968168
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2210168246
Short name T296
Test name
Test status
Simulation time 94379346058 ps
CPU time 480.05 seconds
Started Jul 04 05:18:03 PM PDT 24
Finished Jul 04 05:26:03 PM PDT 24
Peak memory 191272 kb
Host smart-a331b0ba-b1ce-4b3a-9648-f4f8ced37726
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210168246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2210168246
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.941352343
Short name T248
Test name
Test status
Simulation time 195211173025 ps
CPU time 1617.56 seconds
Started Jul 04 05:18:04 PM PDT 24
Finished Jul 04 05:45:02 PM PDT 24
Peak memory 191276 kb
Host smart-03350828-764f-4335-8f20-47e88a7d39be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941352343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.941352343
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3629683845
Short name T189
Test name
Test status
Simulation time 573030928397 ps
CPU time 401.96 seconds
Started Jul 04 05:18:13 PM PDT 24
Finished Jul 04 05:24:55 PM PDT 24
Peak memory 191204 kb
Host smart-b6b24e43-f279-4623-ac9b-0b36faee8bfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629683845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3629683845
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3988396093
Short name T438
Test name
Test status
Simulation time 407491642733 ps
CPU time 194.41 seconds
Started Jul 04 05:18:12 PM PDT 24
Finished Jul 04 05:21:26 PM PDT 24
Peak memory 193844 kb
Host smart-649ac0a1-e0fb-4ff2-8ffb-bf087295e08c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988396093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3988396093
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.4064514476
Short name T353
Test name
Test status
Simulation time 213173707936 ps
CPU time 218.66 seconds
Started Jul 04 05:18:12 PM PDT 24
Finished Jul 04 05:21:51 PM PDT 24
Peak memory 191216 kb
Host smart-41c9f581-0a94-483c-a58c-c0137524663b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064514476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.4064514476
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1227540946
Short name T136
Test name
Test status
Simulation time 115010916686 ps
CPU time 213.38 seconds
Started Jul 04 05:18:16 PM PDT 24
Finished Jul 04 05:21:50 PM PDT 24
Peak memory 191276 kb
Host smart-dd620249-fcc5-4300-b458-89780a751c3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227540946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1227540946
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2178476292
Short name T208
Test name
Test status
Simulation time 160697483019 ps
CPU time 283.13 seconds
Started Jul 04 05:18:12 PM PDT 24
Finished Jul 04 05:22:56 PM PDT 24
Peak memory 191240 kb
Host smart-b4f873e3-597f-47bf-b2da-9651b8e66dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178476292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2178476292
Directory /workspace/99.rv_timer_random/latest
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