Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.47 99.36 98.73 100.00 100.00 100.00 98.75


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T511 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1853662213 Jul 05 04:34:06 PM PDT 24 Jul 05 04:34:10 PM PDT 24 11792747 ps
T512 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4212701498 Jul 05 04:33:45 PM PDT 24 Jul 05 04:33:49 PM PDT 24 115651113 ps
T513 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4288768935 Jul 05 04:33:52 PM PDT 24 Jul 05 04:33:54 PM PDT 24 82869534 ps
T514 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3877517919 Jul 05 04:34:12 PM PDT 24 Jul 05 04:34:18 PM PDT 24 13726321 ps
T515 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3493743077 Jul 05 04:34:09 PM PDT 24 Jul 05 04:34:15 PM PDT 24 29947504 ps
T516 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1909866092 Jul 05 04:34:12 PM PDT 24 Jul 05 04:34:19 PM PDT 24 66124873 ps
T517 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1383680331 Jul 05 04:33:59 PM PDT 24 Jul 05 04:34:02 PM PDT 24 27198147 ps
T518 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1154744877 Jul 05 04:33:55 PM PDT 24 Jul 05 04:33:57 PM PDT 24 38718845 ps
T519 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1765155222 Jul 05 04:34:09 PM PDT 24 Jul 05 04:34:13 PM PDT 24 18798152 ps
T520 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1409637932 Jul 05 04:34:01 PM PDT 24 Jul 05 04:34:05 PM PDT 24 29993205 ps
T116 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4279657820 Jul 05 04:33:57 PM PDT 24 Jul 05 04:34:01 PM PDT 24 226481454 ps
T521 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1689134466 Jul 05 04:34:01 PM PDT 24 Jul 05 04:34:07 PM PDT 24 250271146 ps
T522 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2318921217 Jul 05 04:33:53 PM PDT 24 Jul 05 04:33:55 PM PDT 24 174417681 ps
T523 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4156297437 Jul 05 04:34:09 PM PDT 24 Jul 05 04:34:14 PM PDT 24 284531545 ps
T524 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.325943132 Jul 05 04:34:14 PM PDT 24 Jul 05 04:34:20 PM PDT 24 14762527 ps
T525 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2445398803 Jul 05 04:34:09 PM PDT 24 Jul 05 04:34:14 PM PDT 24 28268834 ps
T91 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3006235756 Jul 05 04:33:58 PM PDT 24 Jul 05 04:34:02 PM PDT 24 59058719 ps
T526 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2176751494 Jul 05 04:34:11 PM PDT 24 Jul 05 04:34:17 PM PDT 24 20886883 ps
T527 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4026858451 Jul 05 04:34:10 PM PDT 24 Jul 05 04:34:15 PM PDT 24 61037868 ps
T528 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3735123770 Jul 05 04:34:24 PM PDT 24 Jul 05 04:34:25 PM PDT 24 17083555 ps
T529 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2656965657 Jul 05 04:34:08 PM PDT 24 Jul 05 04:34:12 PM PDT 24 14880181 ps
T92 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.713042236 Jul 05 04:34:11 PM PDT 24 Jul 05 04:34:17 PM PDT 24 33713278 ps
T530 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.687328313 Jul 05 04:33:58 PM PDT 24 Jul 05 04:34:01 PM PDT 24 93808688 ps
T531 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3008847762 Jul 05 04:33:54 PM PDT 24 Jul 05 04:33:55 PM PDT 24 135232152 ps
T532 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2083729399 Jul 05 04:34:08 PM PDT 24 Jul 05 04:34:13 PM PDT 24 238938273 ps
T533 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3441113047 Jul 05 04:34:05 PM PDT 24 Jul 05 04:34:08 PM PDT 24 44189346 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.948829128 Jul 05 04:34:05 PM PDT 24 Jul 05 04:34:08 PM PDT 24 15974786 ps
T535 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2204046927 Jul 05 04:33:49 PM PDT 24 Jul 05 04:33:53 PM PDT 24 163435577 ps
T536 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1956680999 Jul 05 04:34:00 PM PDT 24 Jul 05 04:34:03 PM PDT 24 14284295 ps
T537 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1690609291 Jul 05 04:34:13 PM PDT 24 Jul 05 04:34:19 PM PDT 24 11056905 ps
T93 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1807472458 Jul 05 04:34:03 PM PDT 24 Jul 05 04:34:06 PM PDT 24 17989303 ps
T538 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3769331036 Jul 05 04:34:12 PM PDT 24 Jul 05 04:34:18 PM PDT 24 76861362 ps
T539 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.741790695 Jul 05 04:34:11 PM PDT 24 Jul 05 04:34:17 PM PDT 24 47728340 ps
T94 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3232159456 Jul 05 04:33:47 PM PDT 24 Jul 05 04:33:49 PM PDT 24 40531079 ps
T540 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3686120303 Jul 05 04:34:13 PM PDT 24 Jul 05 04:34:20 PM PDT 24 27770597 ps
T541 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2204235054 Jul 05 04:33:56 PM PDT 24 Jul 05 04:33:59 PM PDT 24 39001723 ps
T95 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1082326417 Jul 05 04:33:46 PM PDT 24 Jul 05 04:33:49 PM PDT 24 28434740 ps
T98 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.458159396 Jul 05 04:34:00 PM PDT 24 Jul 05 04:34:04 PM PDT 24 35103247 ps
T542 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.313042854 Jul 05 04:34:04 PM PDT 24 Jul 05 04:34:07 PM PDT 24 99497815 ps
T543 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4193877505 Jul 05 04:34:06 PM PDT 24 Jul 05 04:34:10 PM PDT 24 157584130 ps
T544 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.967754162 Jul 05 04:33:58 PM PDT 24 Jul 05 04:34:02 PM PDT 24 12459109 ps
T545 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1065460396 Jul 05 04:33:58 PM PDT 24 Jul 05 04:34:01 PM PDT 24 49501989 ps
T546 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3296059578 Jul 05 04:34:12 PM PDT 24 Jul 05 04:34:18 PM PDT 24 25782400 ps
T547 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2744746158 Jul 05 04:34:13 PM PDT 24 Jul 05 04:34:20 PM PDT 24 41282557 ps
T548 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3745758451 Jul 05 04:34:11 PM PDT 24 Jul 05 04:34:17 PM PDT 24 17018234 ps
T549 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.34575506 Jul 05 04:34:08 PM PDT 24 Jul 05 04:34:12 PM PDT 24 14353721 ps
T550 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3276923096 Jul 05 04:34:08 PM PDT 24 Jul 05 04:34:12 PM PDT 24 114310459 ps
T96 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3094269232 Jul 05 04:34:10 PM PDT 24 Jul 05 04:34:15 PM PDT 24 28777181 ps
T551 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3384515354 Jul 05 04:34:10 PM PDT 24 Jul 05 04:34:15 PM PDT 24 15380698 ps
T552 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2825089977 Jul 05 04:33:59 PM PDT 24 Jul 05 04:34:02 PM PDT 24 40809851 ps
T553 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1655148681 Jul 05 04:34:13 PM PDT 24 Jul 05 04:34:19 PM PDT 24 67087414 ps
T554 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1872270980 Jul 05 04:34:29 PM PDT 24 Jul 05 04:34:34 PM PDT 24 814888830 ps
T555 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2718820160 Jul 05 04:34:00 PM PDT 24 Jul 05 04:34:04 PM PDT 24 95900325 ps
T556 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2037822199 Jul 05 04:34:29 PM PDT 24 Jul 05 04:34:30 PM PDT 24 45422858 ps
T557 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2245158030 Jul 05 04:33:46 PM PDT 24 Jul 05 04:33:49 PM PDT 24 82251466 ps
T99 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1526453434 Jul 05 04:34:03 PM PDT 24 Jul 05 04:34:07 PM PDT 24 26096480 ps
T558 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1310187893 Jul 05 04:34:11 PM PDT 24 Jul 05 04:34:17 PM PDT 24 32873307 ps
T559 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1723111057 Jul 05 04:34:10 PM PDT 24 Jul 05 04:34:16 PM PDT 24 76004221 ps
T560 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3699569501 Jul 05 04:34:12 PM PDT 24 Jul 05 04:34:19 PM PDT 24 31000706 ps
T561 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2423966088 Jul 05 04:33:53 PM PDT 24 Jul 05 04:33:56 PM PDT 24 499106146 ps
T562 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.944418130 Jul 05 04:34:12 PM PDT 24 Jul 05 04:34:19 PM PDT 24 128801218 ps
T563 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2435532078 Jul 05 04:34:08 PM PDT 24 Jul 05 04:34:12 PM PDT 24 47549679 ps
T564 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3119518412 Jul 05 04:33:52 PM PDT 24 Jul 05 04:33:53 PM PDT 24 90338632 ps
T565 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2918735707 Jul 05 04:34:15 PM PDT 24 Jul 05 04:34:21 PM PDT 24 57107351 ps
T566 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.929580823 Jul 05 04:34:02 PM PDT 24 Jul 05 04:34:08 PM PDT 24 167832708 ps
T567 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3214059425 Jul 05 04:34:14 PM PDT 24 Jul 05 04:34:21 PM PDT 24 34847692 ps
T568 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2131610052 Jul 05 04:34:12 PM PDT 24 Jul 05 04:34:18 PM PDT 24 19146546 ps
T569 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2383394231 Jul 05 04:34:10 PM PDT 24 Jul 05 04:34:17 PM PDT 24 138754499 ps
T570 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1240724760 Jul 05 04:33:58 PM PDT 24 Jul 05 04:34:01 PM PDT 24 80422111 ps
T571 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.4184547574 Jul 05 04:34:03 PM PDT 24 Jul 05 04:34:07 PM PDT 24 149721876 ps
T572 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3146524221 Jul 05 04:34:06 PM PDT 24 Jul 05 04:34:10 PM PDT 24 76151673 ps
T97 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1194711735 Jul 05 04:33:53 PM PDT 24 Jul 05 04:33:58 PM PDT 24 1627968424 ps
T573 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.36185941 Jul 05 04:33:51 PM PDT 24 Jul 05 04:33:54 PM PDT 24 208828562 ps
T574 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3907415258 Jul 05 04:34:08 PM PDT 24 Jul 05 04:34:13 PM PDT 24 20703071 ps
T575 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2095570556 Jul 05 04:34:11 PM PDT 24 Jul 05 04:34:17 PM PDT 24 30696408 ps
T576 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4125426624 Jul 05 04:34:19 PM PDT 24 Jul 05 04:34:24 PM PDT 24 378210510 ps
T577 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2987905372 Jul 05 04:34:07 PM PDT 24 Jul 05 04:34:12 PM PDT 24 98844817 ps
T578 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2071795871 Jul 05 04:33:59 PM PDT 24 Jul 05 04:34:02 PM PDT 24 58803518 ps
T579 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1724855102 Jul 05 04:33:59 PM PDT 24 Jul 05 04:34:04 PM PDT 24 436549876 ps
T580 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1506763588 Jul 05 04:34:08 PM PDT 24 Jul 05 04:34:12 PM PDT 24 34300132 ps
T581 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1987106645 Jul 05 04:34:09 PM PDT 24 Jul 05 04:34:14 PM PDT 24 15445295 ps
T582 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.669693016 Jul 05 04:34:03 PM PDT 24 Jul 05 04:34:07 PM PDT 24 77071648 ps

Test location /workspace/coverage/default/39.rv_timer_random.2709817678
Short name T5
Test name
Test status
Simulation time 228037070627 ps
CPU time 591.78 seconds
Started Jul 05 05:05:22 PM PDT 24
Finished Jul 05 05:15:15 PM PDT 24
Peak memory 191336 kb
Host smart-1d2a0918-af43-4f8d-ac9c-24eea795f091
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709817678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2709817678
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.2343271099
Short name T11
Test name
Test status
Simulation time 392434431099 ps
CPU time 800.03 seconds
Started Jul 05 05:03:15 PM PDT 24
Finished Jul 05 05:16:35 PM PDT 24
Peak memory 212544 kb
Host smart-b5d39877-7e76-404e-92af-420d84df8b30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343271099 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.2343271099
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3368855714
Short name T9
Test name
Test status
Simulation time 1876746891222 ps
CPU time 2287.21 seconds
Started Jul 05 05:04:55 PM PDT 24
Finished Jul 05 05:43:03 PM PDT 24
Peak memory 191356 kb
Host smart-c246ffe0-ec4a-4c4c-aab1-ad96bdd553dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368855714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3368855714
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3856535361
Short name T142
Test name
Test status
Simulation time 1256031735524 ps
CPU time 2075.59 seconds
Started Jul 05 05:02:36 PM PDT 24
Finished Jul 05 05:37:13 PM PDT 24
Peak memory 191308 kb
Host smart-2926e06a-556c-4237-99eb-4440a96b15f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856535361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3856535361
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1811079008
Short name T28
Test name
Test status
Simulation time 470543843 ps
CPU time 1.32 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 04:34:14 PM PDT 24
Peak memory 195056 kb
Host smart-ce47996e-26d6-4e90-a4e8-a7225a7e7395
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811079008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1811079008
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1233670094
Short name T184
Test name
Test status
Simulation time 726311777470 ps
CPU time 2567.38 seconds
Started Jul 05 05:05:16 PM PDT 24
Finished Jul 05 05:48:04 PM PDT 24
Peak memory 191276 kb
Host smart-8f1aa26b-d869-4fcb-8ded-fba351b5bedb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233670094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1233670094
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2492979052
Short name T135
Test name
Test status
Simulation time 367830240002 ps
CPU time 1134.74 seconds
Started Jul 05 05:03:28 PM PDT 24
Finished Jul 05 05:22:23 PM PDT 24
Peak memory 191604 kb
Host smart-531064cd-be5a-47b5-b752-803a291b76cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492979052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2492979052
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.502453517
Short name T16
Test name
Test status
Simulation time 79899000 ps
CPU time 0.76 seconds
Started Jul 05 05:01:34 PM PDT 24
Finished Jul 05 05:01:36 PM PDT 24
Peak memory 213372 kb
Host smart-89d3de04-cbaa-4bb8-ab8c-fc7ca35f6981
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502453517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.502453517
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1696017221
Short name T133
Test name
Test status
Simulation time 925884928097 ps
CPU time 2353.74 seconds
Started Jul 05 05:03:02 PM PDT 24
Finished Jul 05 05:42:17 PM PDT 24
Peak memory 191288 kb
Host smart-2f79db8b-1a67-44e5-929f-46dafb4e691e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696017221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1696017221
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.318294273
Short name T221
Test name
Test status
Simulation time 2425055505501 ps
CPU time 2278.46 seconds
Started Jul 05 05:05:22 PM PDT 24
Finished Jul 05 05:43:21 PM PDT 24
Peak memory 191240 kb
Host smart-3f9a1627-714d-48ef-ad2f-3fd8096cc5c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318294273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
318294273
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3006235756
Short name T91
Test name
Test status
Simulation time 59058719 ps
CPU time 0.79 seconds
Started Jul 05 04:33:58 PM PDT 24
Finished Jul 05 04:34:02 PM PDT 24
Peak memory 191540 kb
Host smart-ba239696-3a0f-4a9e-ab4a-b6306dbbd25d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006235756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3006235756
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2292445320
Short name T8
Test name
Test status
Simulation time 1625771755090 ps
CPU time 450.62 seconds
Started Jul 05 05:04:17 PM PDT 24
Finished Jul 05 05:11:49 PM PDT 24
Peak memory 195788 kb
Host smart-39494772-7095-4278-ba90-61af12f78dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292445320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2292445320
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1934306823
Short name T106
Test name
Test status
Simulation time 623001215231 ps
CPU time 864.38 seconds
Started Jul 05 05:03:14 PM PDT 24
Finished Jul 05 05:17:39 PM PDT 24
Peak memory 191304 kb
Host smart-a109a43f-3ca6-4636-a564-a1c93f562787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934306823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1934306823
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1163991611
Short name T230
Test name
Test status
Simulation time 398424144316 ps
CPU time 1109.83 seconds
Started Jul 05 05:06:03 PM PDT 24
Finished Jul 05 05:24:34 PM PDT 24
Peak memory 195276 kb
Host smart-5a9ebd0f-036d-4d1f-bea2-5455a6d65aa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163991611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1163991611
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3746625788
Short name T262
Test name
Test status
Simulation time 603369222249 ps
CPU time 4702.12 seconds
Started Jul 05 05:01:32 PM PDT 24
Finished Jul 05 06:19:55 PM PDT 24
Peak memory 191220 kb
Host smart-ae5867b4-88f7-40f5-b6b3-d81d44cfa31c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746625788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3746625788
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.3679695298
Short name T123
Test name
Test status
Simulation time 320907316538 ps
CPU time 766.54 seconds
Started Jul 05 05:07:22 PM PDT 24
Finished Jul 05 05:20:10 PM PDT 24
Peak memory 193388 kb
Host smart-14fd7d83-ac1c-4d65-a320-2fadf5097d69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679695298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3679695298
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.380993798
Short name T67
Test name
Test status
Simulation time 155290727907 ps
CPU time 703.79 seconds
Started Jul 05 05:08:32 PM PDT 24
Finished Jul 05 05:20:17 PM PDT 24
Peak memory 191304 kb
Host smart-883cb78e-ed60-41c7-a7d0-f8c4249d0e1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380993798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.380993798
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.3671363148
Short name T155
Test name
Test status
Simulation time 6558283834237 ps
CPU time 2505.02 seconds
Started Jul 05 05:06:16 PM PDT 24
Finished Jul 05 05:48:02 PM PDT 24
Peak memory 191236 kb
Host smart-0e047cca-8c1c-4fd1-91b5-8f1325ec359a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671363148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.3671363148
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.775775687
Short name T32
Test name
Test status
Simulation time 31544746 ps
CPU time 0.75 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 04:34:21 PM PDT 24
Peak memory 193104 kb
Host smart-5c5b167e-c66c-4fd5-a269-7512e859941e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775775687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.775775687
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/84.rv_timer_random.528337788
Short name T237
Test name
Test status
Simulation time 124581447517 ps
CPU time 220.73 seconds
Started Jul 05 05:06:48 PM PDT 24
Finished Jul 05 05:10:30 PM PDT 24
Peak memory 191360 kb
Host smart-79675e96-90bc-4020-b2fa-2c7f922869dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528337788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.528337788
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2855779341
Short name T147
Test name
Test status
Simulation time 1169785130025 ps
CPU time 696.35 seconds
Started Jul 05 05:05:09 PM PDT 24
Finished Jul 05 05:16:46 PM PDT 24
Peak memory 191220 kb
Host smart-63eb994e-e70c-42ed-9b8e-5c3f209fbc3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855779341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2855779341
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2864351464
Short name T22
Test name
Test status
Simulation time 1503478552413 ps
CPU time 1841.26 seconds
Started Jul 05 05:05:29 PM PDT 24
Finished Jul 05 05:36:11 PM PDT 24
Peak memory 191276 kb
Host smart-720c3d83-ec00-4d75-9dca-ac450fb661b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864351464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2864351464
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.792881169
Short name T265
Test name
Test status
Simulation time 1550041911742 ps
CPU time 839.8 seconds
Started Jul 05 05:02:50 PM PDT 24
Finished Jul 05 05:16:50 PM PDT 24
Peak memory 191296 kb
Host smart-eff8c7bc-872d-4b84-88fb-a516ee7fcf45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792881169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
792881169
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_random.461029023
Short name T232
Test name
Test status
Simulation time 247797762353 ps
CPU time 260.02 seconds
Started Jul 05 05:02:54 PM PDT 24
Finished Jul 05 05:07:14 PM PDT 24
Peak memory 191348 kb
Host smart-22b63d9e-be56-41d7-bcfa-a156ffe4697b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461029023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.461029023
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1855462100
Short name T201
Test name
Test status
Simulation time 294399370475 ps
CPU time 1948.4 seconds
Started Jul 05 05:07:41 PM PDT 24
Finished Jul 05 05:40:10 PM PDT 24
Peak memory 191344 kb
Host smart-267a4615-4aac-435b-93f3-5caac46fe0ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855462100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1855462100
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2213167195
Short name T226
Test name
Test status
Simulation time 293277400519 ps
CPU time 918.35 seconds
Started Jul 05 05:04:56 PM PDT 24
Finished Jul 05 05:20:16 PM PDT 24
Peak memory 191336 kb
Host smart-19495ce1-de6a-4380-9d62-9eeb46b33856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213167195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2213167195
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_random.563346208
Short name T296
Test name
Test status
Simulation time 333135939858 ps
CPU time 330.79 seconds
Started Jul 05 05:05:43 PM PDT 24
Finished Jul 05 05:11:14 PM PDT 24
Peak memory 191304 kb
Host smart-5452e02e-65f2-436f-903a-da1e90e864fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563346208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.563346208
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.1960035520
Short name T286
Test name
Test status
Simulation time 112809688851 ps
CPU time 131.12 seconds
Started Jul 05 05:06:38 PM PDT 24
Finished Jul 05 05:08:49 PM PDT 24
Peak memory 191332 kb
Host smart-8bff752c-1134-4dbf-b7e5-0fd278a99aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960035520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.1960035520
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4121678614
Short name T2
Test name
Test status
Simulation time 163930874515 ps
CPU time 389.97 seconds
Started Jul 05 05:06:57 PM PDT 24
Finished Jul 05 05:13:27 PM PDT 24
Peak memory 193424 kb
Host smart-0127b8ad-88b3-4dbd-9903-c43c33ff1cf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121678614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4121678614
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.619279941
Short name T163
Test name
Test status
Simulation time 223503319698 ps
CPU time 133.77 seconds
Started Jul 05 05:06:59 PM PDT 24
Finished Jul 05 05:09:13 PM PDT 24
Peak memory 191336 kb
Host smart-5e78fd77-b269-4ec1-aac5-d7e43fae1377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619279941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.619279941
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2866741890
Short name T145
Test name
Test status
Simulation time 425225547903 ps
CPU time 1098.71 seconds
Started Jul 05 05:07:16 PM PDT 24
Finished Jul 05 05:25:35 PM PDT 24
Peak memory 191220 kb
Host smart-e576ded6-8904-43ec-b4e1-a4170b674927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866741890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2866741890
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2291991200
Short name T178
Test name
Test status
Simulation time 592489872472 ps
CPU time 406.42 seconds
Started Jul 05 05:07:57 PM PDT 24
Finished Jul 05 05:14:45 PM PDT 24
Peak memory 191348 kb
Host smart-58bc8a63-5f7e-4df4-af05-4430eb449348
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291991200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2291991200
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1553967829
Short name T317
Test name
Test status
Simulation time 125063953678 ps
CPU time 267.5 seconds
Started Jul 05 05:08:32 PM PDT 24
Finished Jul 05 05:13:01 PM PDT 24
Peak memory 191348 kb
Host smart-59fd845b-5d50-40ae-babc-3e9262877afb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553967829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1553967829
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random.715693530
Short name T177
Test name
Test status
Simulation time 501312318934 ps
CPU time 1053.06 seconds
Started Jul 05 05:05:30 PM PDT 24
Finished Jul 05 05:23:04 PM PDT 24
Peak memory 194868 kb
Host smart-3c9c5caa-46d8-4727-9a36-4b7f4c5675e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715693530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.715693530
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3423367953
Short name T137
Test name
Test status
Simulation time 565786307787 ps
CPU time 226.84 seconds
Started Jul 05 05:06:43 PM PDT 24
Finished Jul 05 05:10:30 PM PDT 24
Peak memory 191340 kb
Host smart-50f0669b-b352-4247-b804-7a6b6983a665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423367953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3423367953
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.3554277764
Short name T344
Test name
Test status
Simulation time 177688341080 ps
CPU time 433.19 seconds
Started Jul 05 05:01:33 PM PDT 24
Finished Jul 05 05:08:47 PM PDT 24
Peak memory 194836 kb
Host smart-707769bd-20da-4bd7-96ea-65603e559d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554277764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3554277764
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.3201253038
Short name T285
Test name
Test status
Simulation time 295616888577 ps
CPU time 304.96 seconds
Started Jul 05 05:02:04 PM PDT 24
Finished Jul 05 05:07:10 PM PDT 24
Peak memory 191264 kb
Host smart-ff2beb3e-148b-4fe6-8d03-578a8ef5c4e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201253038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3201253038
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.317350342
Short name T129
Test name
Test status
Simulation time 321390334417 ps
CPU time 1661.96 seconds
Started Jul 05 05:02:08 PM PDT 24
Finished Jul 05 05:29:51 PM PDT 24
Peak memory 191336 kb
Host smart-547a1dd5-a8ed-4a36-8f61-ca0bddbaa73a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317350342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.317350342
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2049377579
Short name T175
Test name
Test status
Simulation time 556987754238 ps
CPU time 366.58 seconds
Started Jul 05 05:03:55 PM PDT 24
Finished Jul 05 05:10:02 PM PDT 24
Peak memory 183032 kb
Host smart-303636d2-143d-482b-ac6e-74055523a051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049377579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2049377579
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_random.2570967432
Short name T273
Test name
Test status
Simulation time 1114440178202 ps
CPU time 702.01 seconds
Started Jul 05 05:05:21 PM PDT 24
Finished Jul 05 05:17:04 PM PDT 24
Peak memory 191332 kb
Host smart-7841292d-77fd-4269-9884-6b97033dbde2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570967432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2570967432
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2435645342
Short name T166
Test name
Test status
Simulation time 1115166771160 ps
CPU time 702.09 seconds
Started Jul 05 05:06:37 PM PDT 24
Finished Jul 05 05:18:19 PM PDT 24
Peak memory 191244 kb
Host smart-fb45a596-4eea-4012-a5d7-dd2c6745ddd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435645342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2435645342
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.212397883
Short name T47
Test name
Test status
Simulation time 300385153658 ps
CPU time 268.53 seconds
Started Jul 05 05:06:37 PM PDT 24
Finished Jul 05 05:11:06 PM PDT 24
Peak memory 193708 kb
Host smart-6eaa7800-3173-4cce-a4a9-0fe698a80fbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212397883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.212397883
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1101647385
Short name T146
Test name
Test status
Simulation time 207599191244 ps
CPU time 644.86 seconds
Started Jul 05 05:06:49 PM PDT 24
Finished Jul 05 05:17:35 PM PDT 24
Peak memory 191256 kb
Host smart-e4f7363f-6405-495c-b141-ff97a4c83b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101647385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1101647385
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1284667454
Short name T295
Test name
Test status
Simulation time 162731827274 ps
CPU time 246.07 seconds
Started Jul 05 05:07:09 PM PDT 24
Finished Jul 05 05:11:16 PM PDT 24
Peak memory 191248 kb
Host smart-409433e7-fc46-4c25-878f-25838b852b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284667454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1284667454
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1138832244
Short name T181
Test name
Test status
Simulation time 99694387536 ps
CPU time 1783.95 seconds
Started Jul 05 05:08:03 PM PDT 24
Finished Jul 05 05:37:48 PM PDT 24
Peak memory 191348 kb
Host smart-70e60489-bb27-4426-b6ba-ff05e519f149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138832244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1138832244
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1337663850
Short name T173
Test name
Test status
Simulation time 135591632964 ps
CPU time 222.08 seconds
Started Jul 05 05:03:16 PM PDT 24
Finished Jul 05 05:07:00 PM PDT 24
Peak memory 183128 kb
Host smart-7dd2b1ac-d01d-4551-909a-89bf29f077a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337663850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1337663850
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/179.rv_timer_random.1004637878
Short name T214
Test name
Test status
Simulation time 416762253452 ps
CPU time 611.88 seconds
Started Jul 05 05:08:25 PM PDT 24
Finished Jul 05 05:18:37 PM PDT 24
Peak memory 191328 kb
Host smart-3c0e6d8d-1eb7-4460-9d90-dd86b9f902e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004637878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1004637878
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1040335742
Short name T250
Test name
Test status
Simulation time 163085648243 ps
CPU time 547.79 seconds
Started Jul 05 05:08:31 PM PDT 24
Finished Jul 05 05:17:39 PM PDT 24
Peak memory 191344 kb
Host smart-784454fa-0ac1-4f17-a9b1-8f98f2d72a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040335742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1040335742
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.294581012
Short name T74
Test name
Test status
Simulation time 202279224354 ps
CPU time 293.06 seconds
Started Jul 05 05:03:51 PM PDT 24
Finished Jul 05 05:08:44 PM PDT 24
Peak memory 195748 kb
Host smart-7fd62828-9536-4bc8-8bbb-e0f91c2d3071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294581012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
294581012
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_random.3703201049
Short name T187
Test name
Test status
Simulation time 385304510121 ps
CPU time 1618.55 seconds
Started Jul 05 05:03:49 PM PDT 24
Finished Jul 05 05:30:48 PM PDT 24
Peak memory 191344 kb
Host smart-2b97c1ef-1d9d-44d6-bcea-21017033b840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703201049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3703201049
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/50.rv_timer_random.1979319756
Short name T247
Test name
Test status
Simulation time 133686835798 ps
CPU time 1393.99 seconds
Started Jul 05 05:06:30 PM PDT 24
Finished Jul 05 05:29:45 PM PDT 24
Peak memory 191344 kb
Host smart-22ee83e1-1d6e-41d6-8805-d3da1e99b63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979319756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1979319756
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2660746332
Short name T255
Test name
Test status
Simulation time 144780096349 ps
CPU time 262.76 seconds
Started Jul 05 05:07:06 PM PDT 24
Finished Jul 05 05:11:29 PM PDT 24
Peak memory 191236 kb
Host smart-443f4ade-ef72-4ddb-a71a-9d57b35ec980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660746332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2660746332
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2872182344
Short name T227
Test name
Test status
Simulation time 70247736286 ps
CPU time 133.74 seconds
Started Jul 05 05:07:29 PM PDT 24
Finished Jul 05 05:09:43 PM PDT 24
Peak memory 191348 kb
Host smart-636aee0a-7f93-49a6-9c68-05f1b270bdc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872182344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2872182344
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.560213094
Short name T208
Test name
Test status
Simulation time 445570873259 ps
CPU time 584.31 seconds
Started Jul 05 05:07:37 PM PDT 24
Finished Jul 05 05:17:22 PM PDT 24
Peak memory 191240 kb
Host smart-a02b5b3c-2f2e-4856-ac95-c56e8fa0acf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560213094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.560213094
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1455088315
Short name T323
Test name
Test status
Simulation time 92937888866 ps
CPU time 255.79 seconds
Started Jul 05 05:08:01 PM PDT 24
Finished Jul 05 05:12:17 PM PDT 24
Peak memory 191336 kb
Host smart-871f3532-bd28-4e87-b564-a9140711134a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455088315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1455088315
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.1378354819
Short name T192
Test name
Test status
Simulation time 360955961137 ps
CPU time 723.89 seconds
Started Jul 05 05:03:23 PM PDT 24
Finished Jul 05 05:15:27 PM PDT 24
Peak memory 193628 kb
Host smart-527e924f-13e0-455d-b130-0370cb39eb71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378354819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1378354819
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.451762803
Short name T293
Test name
Test status
Simulation time 314046273245 ps
CPU time 253.17 seconds
Started Jul 05 05:06:16 PM PDT 24
Finished Jul 05 05:10:29 PM PDT 24
Peak memory 183080 kb
Host smart-8635185e-641b-4e09-9028-6bda17cbf961
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451762803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.451762803
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/96.rv_timer_random.1628272839
Short name T138
Test name
Test status
Simulation time 146694955203 ps
CPU time 332.37 seconds
Started Jul 05 05:07:04 PM PDT 24
Finished Jul 05 05:12:37 PM PDT 24
Peak memory 191284 kb
Host smart-de2cbe39-4355-4528-b41a-915880dec265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628272839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1628272839
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4252735154
Short name T85
Test name
Test status
Simulation time 111211357 ps
CPU time 0.61 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 04:34:13 PM PDT 24
Peak memory 191648 kb
Host smart-ac0fc837-5272-474c-8f0d-f67d0f344f60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252735154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4252735154
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1352068155
Short name T329
Test name
Test status
Simulation time 13907057414 ps
CPU time 11.52 seconds
Started Jul 05 05:02:02 PM PDT 24
Finished Jul 05 05:02:14 PM PDT 24
Peak memory 183140 kb
Host smart-23892602-f4cf-4553-ab4e-83c8108f658c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352068155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1352068155
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.4205708051
Short name T333
Test name
Test status
Simulation time 57994113038 ps
CPU time 378 seconds
Started Jul 05 05:07:13 PM PDT 24
Finished Jul 05 05:13:31 PM PDT 24
Peak memory 191276 kb
Host smart-48ee1e3a-545a-44c8-afa0-cd058059a041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205708051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4205708051
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1969231253
Short name T327
Test name
Test status
Simulation time 12842338082 ps
CPU time 20.41 seconds
Started Jul 05 05:07:11 PM PDT 24
Finished Jul 05 05:07:32 PM PDT 24
Peak memory 183140 kb
Host smart-71e0058e-df8f-4863-815a-158d273846df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969231253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1969231253
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1540429025
Short name T358
Test name
Test status
Simulation time 106637159220 ps
CPU time 91.56 seconds
Started Jul 05 05:07:42 PM PDT 24
Finished Jul 05 05:09:14 PM PDT 24
Peak memory 191208 kb
Host smart-b19f1ae2-3bd8-40a2-bcc6-b68b2eda0df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540429025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1540429025
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2967076924
Short name T229
Test name
Test status
Simulation time 291768482445 ps
CPU time 671.12 seconds
Started Jul 05 05:07:50 PM PDT 24
Finished Jul 05 05:19:02 PM PDT 24
Peak memory 191216 kb
Host smart-33ef19a7-1dd0-49dc-9efc-3e1b84eb1168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967076924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2967076924
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.946767758
Short name T287
Test name
Test status
Simulation time 76368921738 ps
CPU time 122.44 seconds
Started Jul 05 05:03:08 PM PDT 24
Finished Jul 05 05:05:11 PM PDT 24
Peak memory 183140 kb
Host smart-6d497387-5a1b-4109-9575-449459921acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946767758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.946767758
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2336472033
Short name T63
Test name
Test status
Simulation time 813551129268 ps
CPU time 456.85 seconds
Started Jul 05 05:03:09 PM PDT 24
Finished Jul 05 05:10:48 PM PDT 24
Peak memory 191260 kb
Host smart-880907c6-9f7f-4373-af1b-2d4cc241a2ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336472033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2336472033
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/187.rv_timer_random.3770808852
Short name T198
Test name
Test status
Simulation time 165003369761 ps
CPU time 157.51 seconds
Started Jul 05 05:08:30 PM PDT 24
Finished Jul 05 05:11:08 PM PDT 24
Peak memory 191248 kb
Host smart-1077b97c-fe82-4522-b0a7-1130c6516b73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770808852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3770808852
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.802997999
Short name T290
Test name
Test status
Simulation time 273543512742 ps
CPU time 185.1 seconds
Started Jul 05 05:02:03 PM PDT 24
Finished Jul 05 05:05:09 PM PDT 24
Peak memory 191216 kb
Host smart-9ee8c9ab-732c-4183-bafe-6904980f0c9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802997999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.802997999
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.2255822855
Short name T124
Test name
Test status
Simulation time 298950761924 ps
CPU time 287.3 seconds
Started Jul 05 05:03:55 PM PDT 24
Finished Jul 05 05:08:43 PM PDT 24
Peak memory 193392 kb
Host smart-ba210c8c-0558-480a-a4e5-3dd4c2477258
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255822855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2255822855
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2971892991
Short name T205
Test name
Test status
Simulation time 190646032708 ps
CPU time 287.84 seconds
Started Jul 05 05:04:03 PM PDT 24
Finished Jul 05 05:08:52 PM PDT 24
Peak memory 191308 kb
Host smart-e9717f8a-d366-4e83-a241-553fcd647ed1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971892991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2971892991
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3189728353
Short name T164
Test name
Test status
Simulation time 415434241098 ps
CPU time 527.39 seconds
Started Jul 05 05:04:16 PM PDT 24
Finished Jul 05 05:13:04 PM PDT 24
Peak memory 191320 kb
Host smart-bdf94bad-5d9a-4c62-8716-41792ae7ef83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189728353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3189728353
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3624280341
Short name T219
Test name
Test status
Simulation time 210247382714 ps
CPU time 280.88 seconds
Started Jul 05 05:05:29 PM PDT 24
Finished Jul 05 05:10:10 PM PDT 24
Peak memory 183108 kb
Host smart-e0340077-e237-4344-ac89-9beda1a66a3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624280341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3624280341
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1133849117
Short name T159
Test name
Test status
Simulation time 470106687671 ps
CPU time 326.71 seconds
Started Jul 05 05:05:47 PM PDT 24
Finished Jul 05 05:11:15 PM PDT 24
Peak memory 183156 kb
Host smart-4d4e68ef-87b5-44f6-81e9-53f5c9df1414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133849117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1133849117
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1633169445
Short name T157
Test name
Test status
Simulation time 102417440003 ps
CPU time 208.38 seconds
Started Jul 05 05:05:48 PM PDT 24
Finished Jul 05 05:09:17 PM PDT 24
Peak memory 191196 kb
Host smart-0d6e7a1b-469a-4588-a430-526ca8078f26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633169445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1633169445
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/62.rv_timer_random.154887456
Short name T156
Test name
Test status
Simulation time 257692066030 ps
CPU time 207.83 seconds
Started Jul 05 05:06:38 PM PDT 24
Finished Jul 05 05:10:06 PM PDT 24
Peak memory 191308 kb
Host smart-572b3246-9f74-4931-a48b-c154725e1ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154887456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.154887456
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1839079048
Short name T59
Test name
Test status
Simulation time 716107814159 ps
CPU time 544.97 seconds
Started Jul 05 05:06:49 PM PDT 24
Finished Jul 05 05:15:54 PM PDT 24
Peak memory 191216 kb
Host smart-80a5839d-5fb5-44ef-85cf-43672eb6e6fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839079048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1839079048
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.429754222
Short name T115
Test name
Test status
Simulation time 187274664 ps
CPU time 1.29 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:04 PM PDT 24
Peak memory 194848 kb
Host smart-777ae7d1-eb20-49bc-aa0a-cba0048b05e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429754222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.429754222
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.4021291810
Short name T283
Test name
Test status
Simulation time 911948399732 ps
CPU time 1375.15 seconds
Started Jul 05 05:02:44 PM PDT 24
Finished Jul 05 05:25:40 PM PDT 24
Peak memory 183096 kb
Host smart-a16df3a1-b188-4d35-b9bd-bdaf852db5c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021291810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.4021291810
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/103.rv_timer_random.2573472403
Short name T66
Test name
Test status
Simulation time 82078861320 ps
CPU time 249.93 seconds
Started Jul 05 05:07:12 PM PDT 24
Finished Jul 05 05:11:22 PM PDT 24
Peak memory 191332 kb
Host smart-3a97c83b-c941-443c-909c-0534a84adad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573472403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2573472403
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.4217738696
Short name T171
Test name
Test status
Simulation time 359559921403 ps
CPU time 301.03 seconds
Started Jul 05 05:07:12 PM PDT 24
Finished Jul 05 05:12:13 PM PDT 24
Peak memory 191284 kb
Host smart-e49a4646-d5bc-498d-95d6-c9b45b77ed33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217738696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4217738696
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3085053636
Short name T224
Test name
Test status
Simulation time 27970109422 ps
CPU time 49.71 seconds
Started Jul 05 05:07:16 PM PDT 24
Finished Jul 05 05:08:06 PM PDT 24
Peak memory 191240 kb
Host smart-11776e51-4299-4f5e-8927-f5d2b03ba889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085053636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3085053636
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2955714823
Short name T252
Test name
Test status
Simulation time 766501103259 ps
CPU time 739.02 seconds
Started Jul 05 05:07:19 PM PDT 24
Finished Jul 05 05:19:38 PM PDT 24
Peak memory 191348 kb
Host smart-ef48a5b1-a8e9-40e2-97e5-5f2fe45a567b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955714823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2955714823
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1305241478
Short name T71
Test name
Test status
Simulation time 117633898216 ps
CPU time 194.06 seconds
Started Jul 05 05:07:24 PM PDT 24
Finished Jul 05 05:10:39 PM PDT 24
Peak memory 191284 kb
Host smart-5839fee2-6455-4436-90c4-b4a324819302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305241478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1305241478
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.83462788
Short name T78
Test name
Test status
Simulation time 91184702519 ps
CPU time 333 seconds
Started Jul 05 05:07:29 PM PDT 24
Finished Jul 05 05:13:02 PM PDT 24
Peak memory 194116 kb
Host smart-2374bfca-62dc-4f58-abab-edc25e5780f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83462788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.83462788
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1043044116
Short name T218
Test name
Test status
Simulation time 332066092325 ps
CPU time 3514.6 seconds
Started Jul 05 05:07:36 PM PDT 24
Finished Jul 05 06:06:11 PM PDT 24
Peak memory 191292 kb
Host smart-fed79e68-fc19-4760-8a69-bddbd364fad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043044116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1043044116
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1580454093
Short name T361
Test name
Test status
Simulation time 105851602632 ps
CPU time 49.19 seconds
Started Jul 05 05:07:35 PM PDT 24
Finished Jul 05 05:08:25 PM PDT 24
Peak memory 183064 kb
Host smart-6d132e77-05f3-4f79-a989-50964276ec48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580454093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1580454093
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.980478112
Short name T314
Test name
Test status
Simulation time 48875004250 ps
CPU time 43.37 seconds
Started Jul 05 05:03:02 PM PDT 24
Finished Jul 05 05:03:46 PM PDT 24
Peak memory 183012 kb
Host smart-ff986912-2d52-486a-ba3a-fd91e3b186a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980478112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.980478112
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.240219878
Short name T288
Test name
Test status
Simulation time 644915873857 ps
CPU time 423.33 seconds
Started Jul 05 05:07:50 PM PDT 24
Finished Jul 05 05:14:54 PM PDT 24
Peak memory 191296 kb
Host smart-1a69e072-6d7c-4074-8bf7-4e3a74965f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240219878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.240219878
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.4000371784
Short name T180
Test name
Test status
Simulation time 268894034892 ps
CPU time 227.53 seconds
Started Jul 05 05:08:00 PM PDT 24
Finished Jul 05 05:11:48 PM PDT 24
Peak memory 191344 kb
Host smart-0454a48f-0af3-400a-8f5d-e9e6738bece5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000371784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.4000371784
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.703355726
Short name T131
Test name
Test status
Simulation time 60091774642 ps
CPU time 33.84 seconds
Started Jul 05 05:03:09 PM PDT 24
Finished Jul 05 05:03:44 PM PDT 24
Peak memory 183084 kb
Host smart-7b76b51b-4971-424a-b827-6da8e4a70d62
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703355726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.703355726
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.407064451
Short name T183
Test name
Test status
Simulation time 1634287816982 ps
CPU time 2333.92 seconds
Started Jul 05 05:03:10 PM PDT 24
Finished Jul 05 05:42:05 PM PDT 24
Peak memory 195204 kb
Host smart-e8985692-b729-4138-b108-e6761052e65b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407064451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
407064451
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/154.rv_timer_random.53020693
Short name T234
Test name
Test status
Simulation time 94702140510 ps
CPU time 142.99 seconds
Started Jul 05 05:08:01 PM PDT 24
Finished Jul 05 05:10:25 PM PDT 24
Peak memory 191344 kb
Host smart-f365161c-cbeb-4d0a-9a78-c45e536bd766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53020693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.53020693
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.1096902130
Short name T231
Test name
Test status
Simulation time 50906279635 ps
CPU time 135.96 seconds
Started Jul 05 05:08:06 PM PDT 24
Finished Jul 05 05:10:22 PM PDT 24
Peak memory 191348 kb
Host smart-191bce34-9eb8-46da-9a15-1557b430d83b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096902130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1096902130
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3363850242
Short name T162
Test name
Test status
Simulation time 891684363310 ps
CPU time 417.45 seconds
Started Jul 05 05:08:25 PM PDT 24
Finished Jul 05 05:15:23 PM PDT 24
Peak memory 191340 kb
Host smart-12853e58-43aa-43a4-b94b-9c9b91ab8b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363850242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3363850242
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3488821412
Short name T62
Test name
Test status
Simulation time 1640378631129 ps
CPU time 634.14 seconds
Started Jul 05 05:04:10 PM PDT 24
Finished Jul 05 05:14:45 PM PDT 24
Peak memory 195524 kb
Host smart-494d2388-d059-43f8-9df4-c85086fa1f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488821412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3488821412
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.962854250
Short name T320
Test name
Test status
Simulation time 129390052064 ps
CPU time 101.18 seconds
Started Jul 05 05:04:33 PM PDT 24
Finished Jul 05 05:06:15 PM PDT 24
Peak memory 194568 kb
Host smart-89353928-f79b-4f84-9147-ec60c9adf879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962854250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.962854250
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1527219212
Short name T48
Test name
Test status
Simulation time 18551298170 ps
CPU time 11.04 seconds
Started Jul 05 05:02:05 PM PDT 24
Finished Jul 05 05:02:17 PM PDT 24
Peak memory 183068 kb
Host smart-addd8397-afcf-4dfb-a526-8aa6fd5996ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527219212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1527219212
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3994635403
Short name T330
Test name
Test status
Simulation time 1358054279200 ps
CPU time 682.09 seconds
Started Jul 05 05:05:10 PM PDT 24
Finished Jul 05 05:16:32 PM PDT 24
Peak memory 183028 kb
Host smart-e0c85415-1fa7-4458-a2a9-aaca2b9ffa72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994635403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3994635403
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3018460319
Short name T281
Test name
Test status
Simulation time 34848701206 ps
CPU time 34.85 seconds
Started Jul 05 05:05:15 PM PDT 24
Finished Jul 05 05:05:51 PM PDT 24
Peak memory 183128 kb
Host smart-07d25c57-1ca5-4177-94bd-ef1b6250536d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018460319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3018460319
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3685780350
Short name T128
Test name
Test status
Simulation time 42583553377 ps
CPU time 241.71 seconds
Started Jul 05 05:02:10 PM PDT 24
Finished Jul 05 05:06:12 PM PDT 24
Peak memory 191344 kb
Host smart-48a802df-6a3b-4427-9acf-b19302e695aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685780350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3685780350
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_random.1415095952
Short name T10
Test name
Test status
Simulation time 108760335375 ps
CPU time 311.3 seconds
Started Jul 05 05:05:50 PM PDT 24
Finished Jul 05 05:11:02 PM PDT 24
Peak memory 191340 kb
Host smart-bd9375fa-bf91-4fbb-bb20-aa7465544c80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415095952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1415095952
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1390917597
Short name T203
Test name
Test status
Simulation time 3778346013 ps
CPU time 7.08 seconds
Started Jul 05 05:06:10 PM PDT 24
Finished Jul 05 05:06:18 PM PDT 24
Peak memory 183132 kb
Host smart-730380e4-c982-46a8-a95b-98570c04a008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390917597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1390917597
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/52.rv_timer_random.1616352412
Short name T108
Test name
Test status
Simulation time 393259707814 ps
CPU time 1343.24 seconds
Started Jul 05 05:06:29 PM PDT 24
Finished Jul 05 05:28:53 PM PDT 24
Peak memory 191348 kb
Host smart-9a17476b-3a9e-4b36-942d-8f5fb821303e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616352412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1616352412
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1144449669
Short name T310
Test name
Test status
Simulation time 4778523024301 ps
CPU time 1452.19 seconds
Started Jul 05 05:02:20 PM PDT 24
Finished Jul 05 05:26:33 PM PDT 24
Peak memory 183136 kb
Host smart-630b6ce5-6131-4191-8846-9098895a484e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144449669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1144449669
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/72.rv_timer_random.1241023529
Short name T46
Test name
Test status
Simulation time 165908098990 ps
CPU time 120.06 seconds
Started Jul 05 05:06:44 PM PDT 24
Finished Jul 05 05:08:44 PM PDT 24
Peak memory 191296 kb
Host smart-f8a62b39-5631-47ed-9a76-ad642982d731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241023529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1241023529
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.562431196
Short name T347
Test name
Test status
Simulation time 22366787765 ps
CPU time 33.19 seconds
Started Jul 05 05:02:32 PM PDT 24
Finished Jul 05 05:03:06 PM PDT 24
Peak memory 183156 kb
Host smart-a80294a2-8b30-4c42-b27b-b23c4ecdbdbe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562431196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.562431196
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3094269232
Short name T96
Test name
Test status
Simulation time 28777181 ps
CPU time 0.68 seconds
Started Jul 05 04:34:10 PM PDT 24
Finished Jul 05 04:34:15 PM PDT 24
Peak memory 191520 kb
Host smart-71da5f5b-4d68-40af-8b8b-00b556db3d53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094269232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3094269232
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.1872270980
Short name T554
Test name
Test status
Simulation time 814888830 ps
CPU time 3.58 seconds
Started Jul 05 04:34:29 PM PDT 24
Finished Jul 05 04:34:34 PM PDT 24
Peak memory 190668 kb
Host smart-d5bca055-2668-48de-bd7c-cf7dc4a9094e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872270980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.1872270980
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3232159456
Short name T94
Test name
Test status
Simulation time 40531079 ps
CPU time 0.56 seconds
Started Jul 05 04:33:47 PM PDT 24
Finished Jul 05 04:33:49 PM PDT 24
Peak memory 182324 kb
Host smart-309fc762-3957-428d-8c6a-19b883b7279f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232159456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3232159456
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2580260505
Short name T463
Test name
Test status
Simulation time 31498256 ps
CPU time 1.19 seconds
Started Jul 05 04:33:50 PM PDT 24
Finished Jul 05 04:33:52 PM PDT 24
Peak memory 197048 kb
Host smart-28a1f512-6885-4b07-b1a0-5a41d7fd7b9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580260505 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2580260505
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1082326417
Short name T95
Test name
Test status
Simulation time 28434740 ps
CPU time 0.56 seconds
Started Jul 05 04:33:46 PM PDT 24
Finished Jul 05 04:33:49 PM PDT 24
Peak memory 182260 kb
Host smart-24ca6dd1-43cd-4dac-8586-234b569efab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082326417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1082326417
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3345296479
Short name T506
Test name
Test status
Simulation time 14013849 ps
CPU time 0.55 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:33:48 PM PDT 24
Peak memory 182180 kb
Host smart-3887513b-17d0-4744-8283-121a8febe6ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345296479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3345296479
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.669693016
Short name T582
Test name
Test status
Simulation time 77071648 ps
CPU time 0.62 seconds
Started Jul 05 04:34:03 PM PDT 24
Finished Jul 05 04:34:07 PM PDT 24
Peak memory 191496 kb
Host smart-64be1e19-0502-4fe6-a4b0-3c7f56afe12d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669693016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.669693016
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.4184547574
Short name T571
Test name
Test status
Simulation time 149721876 ps
CPU time 1.45 seconds
Started Jul 05 04:34:03 PM PDT 24
Finished Jul 05 04:34:07 PM PDT 24
Peak memory 197068 kb
Host smart-3ea8294a-1a4e-457c-8d9a-a2b638c5ecc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184547574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.4184547574
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4212701498
Short name T512
Test name
Test status
Simulation time 115651113 ps
CPU time 1.36 seconds
Started Jul 05 04:33:45 PM PDT 24
Finished Jul 05 04:33:49 PM PDT 24
Peak memory 194960 kb
Host smart-43e48d29-963c-4e64-981f-f7733f0b38e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212701498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.4212701498
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3195087132
Short name T495
Test name
Test status
Simulation time 1091781749 ps
CPU time 1.59 seconds
Started Jul 05 04:33:46 PM PDT 24
Finished Jul 05 04:33:50 PM PDT 24
Peak memory 190672 kb
Host smart-3fd102a2-12ac-49fb-8bd8-32509313931f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195087132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3195087132
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3109652528
Short name T31
Test name
Test status
Simulation time 12513920 ps
CPU time 0.57 seconds
Started Jul 05 04:33:50 PM PDT 24
Finished Jul 05 04:33:51 PM PDT 24
Peak memory 182272 kb
Host smart-f2eb3e15-167b-4d03-8851-186d510fdb57
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109652528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3109652528
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4294336168
Short name T482
Test name
Test status
Simulation time 39449619 ps
CPU time 0.87 seconds
Started Jul 05 04:33:51 PM PDT 24
Finished Jul 05 04:33:53 PM PDT 24
Peak memory 196172 kb
Host smart-eafe0a85-8129-4955-9071-28771422cab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294336168 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4294336168
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.458159396
Short name T98
Test name
Test status
Simulation time 35103247 ps
CPU time 0.55 seconds
Started Jul 05 04:34:00 PM PDT 24
Finished Jul 05 04:34:04 PM PDT 24
Peak memory 182240 kb
Host smart-0901bf20-7589-40ef-9f6b-aaadbe2a02fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458159396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.458159396
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.4138115404
Short name T491
Test name
Test status
Simulation time 48615650 ps
CPU time 0.53 seconds
Started Jul 05 04:33:56 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 182216 kb
Host smart-811bc010-8d44-4433-8556-e33dbefcf6f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138115404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.4138115404
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2219147347
Short name T489
Test name
Test status
Simulation time 71433614 ps
CPU time 0.88 seconds
Started Jul 05 04:33:46 PM PDT 24
Finished Jul 05 04:33:50 PM PDT 24
Peak memory 194136 kb
Host smart-aa195f04-472b-409a-bc45-0dc78ed7aba3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219147347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2219147347
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2245158030
Short name T557
Test name
Test status
Simulation time 82251466 ps
CPU time 1.14 seconds
Started Jul 05 04:33:46 PM PDT 24
Finished Jul 05 04:33:49 PM PDT 24
Peak memory 193760 kb
Host smart-3676c51d-2ecf-4d36-981c-5929904c8ebc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245158030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2245158030
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.2204235054
Short name T541
Test name
Test status
Simulation time 39001723 ps
CPU time 0.97 seconds
Started Jul 05 04:33:56 PM PDT 24
Finished Jul 05 04:33:59 PM PDT 24
Peak memory 196464 kb
Host smart-a5f1ac8b-a1dc-48fb-8dba-e3d372630d06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204235054 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.2204235054
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.2472370134
Short name T50
Test name
Test status
Simulation time 18891311 ps
CPU time 0.6 seconds
Started Jul 05 04:33:55 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 182272 kb
Host smart-182d46f0-e2c9-40b5-bf43-27101c6323e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472370134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.2472370134
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2163025466
Short name T466
Test name
Test status
Simulation time 45943470 ps
CPU time 0.56 seconds
Started Jul 05 04:33:57 PM PDT 24
Finished Jul 05 04:33:59 PM PDT 24
Peak memory 182172 kb
Host smart-2f6a2dff-0307-44cc-880f-8df3248185bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163025466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2163025466
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4288768935
Short name T513
Test name
Test status
Simulation time 82869534 ps
CPU time 0.68 seconds
Started Jul 05 04:33:52 PM PDT 24
Finished Jul 05 04:33:54 PM PDT 24
Peak memory 191696 kb
Host smart-460cc0fc-dba8-4f05-a25a-f8efc744ef15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288768935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4288768935
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2025261934
Short name T458
Test name
Test status
Simulation time 279296910 ps
CPU time 1.49 seconds
Started Jul 05 04:33:52 PM PDT 24
Finished Jul 05 04:33:54 PM PDT 24
Peak memory 197116 kb
Host smart-c6693477-a8b2-4fab-a826-bc9c9c519f8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025261934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2025261934
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3008847762
Short name T531
Test name
Test status
Simulation time 135232152 ps
CPU time 0.84 seconds
Started Jul 05 04:33:54 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 193464 kb
Host smart-9da815a2-3e8b-4ee6-8e4c-cb5ba10dac44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008847762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3008847762
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1480569976
Short name T504
Test name
Test status
Simulation time 291230043 ps
CPU time 0.7 seconds
Started Jul 05 04:33:54 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 195224 kb
Host smart-394cee7c-a034-4908-a09a-43b3654b65ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480569976 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1480569976
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2861354011
Short name T475
Test name
Test status
Simulation time 108300858 ps
CPU time 0.58 seconds
Started Jul 05 04:34:07 PM PDT 24
Finished Jul 05 04:34:11 PM PDT 24
Peak memory 182268 kb
Host smart-0915f053-c611-4ec1-bb4b-003f9941a8d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861354011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2861354011
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.560457463
Short name T490
Test name
Test status
Simulation time 13326277 ps
CPU time 0.56 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:02 PM PDT 24
Peak memory 182116 kb
Host smart-dd592dfb-04eb-4708-b49e-336dd335a2a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560457463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.560457463
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3146524221
Short name T572
Test name
Test status
Simulation time 76151673 ps
CPU time 0.62 seconds
Started Jul 05 04:34:06 PM PDT 24
Finished Jul 05 04:34:10 PM PDT 24
Peak memory 191252 kb
Host smart-f81956e6-4500-4122-a8de-0db590f9ffa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146524221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3146524221
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2083729399
Short name T532
Test name
Test status
Simulation time 238938273 ps
CPU time 2.36 seconds
Started Jul 05 04:34:08 PM PDT 24
Finished Jul 05 04:34:13 PM PDT 24
Peak memory 190604 kb
Host smart-f327a406-e7b7-4a28-9899-06ac859d952a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083729399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2083729399
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3119518412
Short name T564
Test name
Test status
Simulation time 90338632 ps
CPU time 0.78 seconds
Started Jul 05 04:33:52 PM PDT 24
Finished Jul 05 04:33:53 PM PDT 24
Peak memory 193524 kb
Host smart-d23341e8-1ea9-47ab-8903-a13bd0f56db5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119518412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3119518412
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3270727558
Short name T468
Test name
Test status
Simulation time 54516343 ps
CPU time 0.75 seconds
Started Jul 05 04:34:05 PM PDT 24
Finished Jul 05 04:34:09 PM PDT 24
Peak memory 194692 kb
Host smart-f7057d87-73af-44dc-9b6c-73f01563b7b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270727558 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3270727558
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4266902299
Short name T494
Test name
Test status
Simulation time 12365502 ps
CPU time 0.58 seconds
Started Jul 05 04:34:01 PM PDT 24
Finished Jul 05 04:34:05 PM PDT 24
Peak memory 182324 kb
Host smart-b81877ea-86c3-47af-aca9-0355974336f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266902299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4266902299
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2744746158
Short name T547
Test name
Test status
Simulation time 41282557 ps
CPU time 0.59 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 04:34:20 PM PDT 24
Peak memory 182208 kb
Host smart-b1a64f67-9a2c-4746-8f32-9da6e23cfad3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744746158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2744746158
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.151518493
Short name T493
Test name
Test status
Simulation time 39767671 ps
CPU time 1.83 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:18 PM PDT 24
Peak memory 197112 kb
Host smart-299591be-2c4c-4741-b278-dde91112a50d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151518493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.151518493
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1925728997
Short name T114
Test name
Test status
Simulation time 103305735 ps
CPU time 1.26 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 04:34:14 PM PDT 24
Peak memory 195000 kb
Host smart-6d9e559d-359e-4cf8-9fe0-360765824afd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925728997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1925728997
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.4026858451
Short name T527
Test name
Test status
Simulation time 61037868 ps
CPU time 0.72 seconds
Started Jul 05 04:34:10 PM PDT 24
Finished Jul 05 04:34:15 PM PDT 24
Peak memory 193852 kb
Host smart-fb168f6a-8635-435f-8e1b-822391022ea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026858451 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.4026858451
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3211263024
Short name T467
Test name
Test status
Simulation time 71704763 ps
CPU time 0.58 seconds
Started Jul 05 04:34:02 PM PDT 24
Finished Jul 05 04:34:05 PM PDT 24
Peak memory 182296 kb
Host smart-523be051-321d-46c1-8a03-c3740a3a92b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211263024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3211263024
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1409637932
Short name T520
Test name
Test status
Simulation time 29993205 ps
CPU time 0.56 seconds
Started Jul 05 04:34:01 PM PDT 24
Finished Jul 05 04:34:05 PM PDT 24
Peak memory 182240 kb
Host smart-6e3f964b-fab6-4d0d-a221-46aea4df10d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409637932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1409637932
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.419959911
Short name T103
Test name
Test status
Simulation time 17148853 ps
CPU time 0.74 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:03 PM PDT 24
Peak memory 191884 kb
Host smart-b67371db-2069-43e7-8465-a22fc8fd2e48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419959911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.419959911
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2037822199
Short name T556
Test name
Test status
Simulation time 45422858 ps
CPU time 1.1 seconds
Started Jul 05 04:34:29 PM PDT 24
Finished Jul 05 04:34:30 PM PDT 24
Peak memory 196768 kb
Host smart-3efe72a8-c549-4f78-9265-c0922cc7055b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037822199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2037822199
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2383394231
Short name T569
Test name
Test status
Simulation time 138754499 ps
CPU time 0.82 seconds
Started Jul 05 04:34:10 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 182656 kb
Host smart-c8079594-96e7-4725-92db-bc97f14849a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383394231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2383394231
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3977087691
Short name T474
Test name
Test status
Simulation time 50548983 ps
CPU time 0.65 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 194268 kb
Host smart-737f5762-54f7-48bc-991e-c6a4824803ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977087691 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3977087691
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3384515354
Short name T551
Test name
Test status
Simulation time 15380698 ps
CPU time 0.6 seconds
Started Jul 05 04:34:10 PM PDT 24
Finished Jul 05 04:34:15 PM PDT 24
Peak memory 182092 kb
Host smart-c4f678d4-ff17-45c1-a54e-d4d2a8c7a550
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384515354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3384515354
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2825089977
Short name T552
Test name
Test status
Simulation time 40809851 ps
CPU time 0.56 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:02 PM PDT 24
Peak memory 182244 kb
Host smart-2e9f009b-f6c1-481e-ad49-f5516cb7926e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825089977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2825089977
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.4080695748
Short name T55
Test name
Test status
Simulation time 69781806 ps
CPU time 0.6 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:02 PM PDT 24
Peak memory 191108 kb
Host smart-4ee1ea23-79da-422c-9c1b-ae211d914ba3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080695748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.4080695748
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2718820160
Short name T555
Test name
Test status
Simulation time 95900325 ps
CPU time 1.03 seconds
Started Jul 05 04:34:00 PM PDT 24
Finished Jul 05 04:34:04 PM PDT 24
Peak memory 196764 kb
Host smart-fe4d196b-f70d-4453-ac71-6109a573f655
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718820160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2718820160
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4125426624
Short name T576
Test name
Test status
Simulation time 378210510 ps
CPU time 1.34 seconds
Started Jul 05 04:34:19 PM PDT 24
Finished Jul 05 04:34:24 PM PDT 24
Peak memory 194996 kb
Host smart-d33ab0c4-574e-4a48-9060-9afaf2b8f725
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125426624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4125426624
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3769331036
Short name T538
Test name
Test status
Simulation time 76861362 ps
CPU time 0.72 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:18 PM PDT 24
Peak memory 194220 kb
Host smart-ff239a83-0115-4468-9438-eff64eefaae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769331036 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3769331036
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1987106645
Short name T581
Test name
Test status
Simulation time 15445295 ps
CPU time 0.65 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 04:34:14 PM PDT 24
Peak memory 191480 kb
Host smart-3535e11e-5fca-4344-9e8c-5b8519f2fdbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987106645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1987106645
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1765155222
Short name T519
Test name
Test status
Simulation time 18798152 ps
CPU time 0.54 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 04:34:13 PM PDT 24
Peak memory 181820 kb
Host smart-20dd615f-d648-4cac-8f85-61aeb25e12b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765155222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1765155222
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1383680331
Short name T517
Test name
Test status
Simulation time 27198147 ps
CPU time 0.78 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:02 PM PDT 24
Peak memory 191280 kb
Host smart-0b069beb-8101-423a-9bd0-65ba7c4a55ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383680331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1383680331
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.849094060
Short name T505
Test name
Test status
Simulation time 180093120 ps
CPU time 2.05 seconds
Started Jul 05 04:34:22 PM PDT 24
Finished Jul 05 04:34:25 PM PDT 24
Peak memory 197088 kb
Host smart-7224673c-9df1-466d-929c-be25e113d6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849094060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.849094060
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.944418130
Short name T562
Test name
Test status
Simulation time 128801218 ps
CPU time 0.93 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 192836 kb
Host smart-4a8109a7-cd4f-491f-bea3-03bbb418fad0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944418130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.944418130
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2851579348
Short name T460
Test name
Test status
Simulation time 36400143 ps
CPU time 0.89 seconds
Started Jul 05 04:34:06 PM PDT 24
Finished Jul 05 04:34:10 PM PDT 24
Peak memory 196456 kb
Host smart-24dff006-bd0b-4614-b175-4e76f5055f50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851579348 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2851579348
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.741790695
Short name T539
Test name
Test status
Simulation time 47728340 ps
CPU time 0.57 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 182216 kb
Host smart-d3290402-afb7-4dcf-896c-df5f6e82ff22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741790695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.741790695
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2652377734
Short name T502
Test name
Test status
Simulation time 12652411 ps
CPU time 0.51 seconds
Started Jul 05 04:34:10 PM PDT 24
Finished Jul 05 04:34:15 PM PDT 24
Peak memory 181608 kb
Host smart-0281cdd5-7157-46ae-8716-0e125e584c42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652377734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2652377734
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2568722280
Short name T102
Test name
Test status
Simulation time 36226242 ps
CPU time 0.73 seconds
Started Jul 05 04:34:01 PM PDT 24
Finished Jul 05 04:34:06 PM PDT 24
Peak memory 191232 kb
Host smart-a32d6339-808a-4085-ae6a-5ee4d40747f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568722280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2568722280
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3591854436
Short name T471
Test name
Test status
Simulation time 522871901 ps
CPU time 1.82 seconds
Started Jul 05 04:34:06 PM PDT 24
Finished Jul 05 04:34:11 PM PDT 24
Peak memory 197052 kb
Host smart-bbaa7b00-40d1-4929-a02e-506d939da17d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591854436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3591854436
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.476147317
Short name T29
Test name
Test status
Simulation time 47506472 ps
CPU time 0.89 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 04:34:14 PM PDT 24
Peak memory 182628 kb
Host smart-31fe9c50-713f-4850-8b74-409ef1cbd54b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476147317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.476147317
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2445398803
Short name T525
Test name
Test status
Simulation time 28268834 ps
CPU time 1.21 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 04:34:14 PM PDT 24
Peak memory 197084 kb
Host smart-efc10c35-9550-479d-81d2-080a1d2df4f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445398803 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2445398803
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.837951922
Short name T51
Test name
Test status
Simulation time 115451541 ps
CPU time 0.55 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 182324 kb
Host smart-afe7039a-d24c-4744-99fa-9742881a570f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837951922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.837951922
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3735123770
Short name T528
Test name
Test status
Simulation time 17083555 ps
CPU time 0.56 seconds
Started Jul 05 04:34:24 PM PDT 24
Finished Jul 05 04:34:25 PM PDT 24
Peak memory 182212 kb
Host smart-48a41e3f-1b53-45be-a404-78567b456864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735123770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3735123770
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3641248894
Short name T101
Test name
Test status
Simulation time 19016457 ps
CPU time 0.7 seconds
Started Jul 05 04:34:04 PM PDT 24
Finished Jul 05 04:34:07 PM PDT 24
Peak memory 191284 kb
Host smart-f502056a-857a-4b0f-942e-e3b8d52e3355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641248894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3641248894
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.524408811
Short name T507
Test name
Test status
Simulation time 74676103 ps
CPU time 1.07 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 04:34:20 PM PDT 24
Peak memory 196948 kb
Host smart-12e345a8-7a26-4b67-b844-8182dbfff69a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524408811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.524408811
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1675247568
Short name T30
Test name
Test status
Simulation time 159943618 ps
CPU time 0.86 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 182624 kb
Host smart-f7e2ab0c-dc6c-4d35-8f44-6a7b71d87c6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675247568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1675247568
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.4156297437
Short name T523
Test name
Test status
Simulation time 284531545 ps
CPU time 1.27 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 04:34:14 PM PDT 24
Peak memory 197052 kb
Host smart-1b025f6d-9cc5-4e7d-8db8-d4c3793b6828
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156297437 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.4156297437
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2328466212
Short name T90
Test name
Test status
Simulation time 16417976 ps
CPU time 0.55 seconds
Started Jul 05 04:34:05 PM PDT 24
Finished Jul 05 04:34:09 PM PDT 24
Peak memory 182216 kb
Host smart-0c9aee17-fdc4-42d1-b0f8-63d4bdafd727
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328466212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2328466212
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.221773463
Short name T461
Test name
Test status
Simulation time 19704423 ps
CPU time 0.56 seconds
Started Jul 05 04:34:01 PM PDT 24
Finished Jul 05 04:34:05 PM PDT 24
Peak memory 182228 kb
Host smart-e4f6131c-80d3-4422-96f3-17d704672b0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221773463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.221773463
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.659732873
Short name T53
Test name
Test status
Simulation time 115119222 ps
CPU time 0.75 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 192296 kb
Host smart-45a27f5c-d60b-4cbb-b21b-78a1f4da6453
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659732873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.659732873
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1723111057
Short name T559
Test name
Test status
Simulation time 76004221 ps
CPU time 1.04 seconds
Started Jul 05 04:34:10 PM PDT 24
Finished Jul 05 04:34:16 PM PDT 24
Peak memory 196860 kb
Host smart-61edc568-955a-4118-b89c-13ebb24dd313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723111057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1723111057
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2551015490
Short name T33
Test name
Test status
Simulation time 32370564 ps
CPU time 0.77 seconds
Started Jul 05 04:34:10 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 195852 kb
Host smart-7fb2d6ee-2283-4810-9a68-a29c3ca1ae2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551015490 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2551015490
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.713042236
Short name T92
Test name
Test status
Simulation time 33713278 ps
CPU time 0.56 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 182260 kb
Host smart-7d3fcf63-1b24-44ec-a5c9-4a19ea9d8492
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713042236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.713042236
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1652942564
Short name T464
Test name
Test status
Simulation time 14395531 ps
CPU time 0.58 seconds
Started Jul 05 04:34:01 PM PDT 24
Finished Jul 05 04:34:05 PM PDT 24
Peak memory 182136 kb
Host smart-1539ecd7-ee64-4084-b65f-9ddaf194949a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652942564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1652942564
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1853145129
Short name T52
Test name
Test status
Simulation time 525985703 ps
CPU time 0.83 seconds
Started Jul 05 04:34:04 PM PDT 24
Finished Jul 05 04:34:08 PM PDT 24
Peak memory 193060 kb
Host smart-76bb4c11-ff5c-40c6-8ee2-e361fb81e3ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853145129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1853145129
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2987905372
Short name T577
Test name
Test status
Simulation time 98844817 ps
CPU time 1.83 seconds
Started Jul 05 04:34:07 PM PDT 24
Finished Jul 05 04:34:12 PM PDT 24
Peak memory 196884 kb
Host smart-45cbd5cd-d86c-4fa2-bf97-3c4aacc36d3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987905372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2987905372
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.4282392005
Short name T508
Test name
Test status
Simulation time 128305549 ps
CPU time 1.05 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:03 PM PDT 24
Peak memory 182796 kb
Host smart-4ebeb849-f324-43a0-a8b3-c94ec36491ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282392005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.4282392005
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3214059425
Short name T567
Test name
Test status
Simulation time 34847692 ps
CPU time 0.81 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 04:34:21 PM PDT 24
Peak memory 182300 kb
Host smart-b6a4f66c-6498-44cf-b387-c4f442c5a9f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214059425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3214059425
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1194711735
Short name T97
Test name
Test status
Simulation time 1627968424 ps
CPU time 3.73 seconds
Started Jul 05 04:33:53 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 190648 kb
Host smart-f66f6738-1f0a-4167-8116-a0595873a91f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194711735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1194711735
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3831604421
Short name T81
Test name
Test status
Simulation time 48054538 ps
CPU time 0.57 seconds
Started Jul 05 04:33:51 PM PDT 24
Finished Jul 05 04:33:53 PM PDT 24
Peak memory 182284 kb
Host smart-8ff9d60c-a902-4606-9152-2efb6a0c5157
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831604421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3831604421
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2930907204
Short name T488
Test name
Test status
Simulation time 50243038 ps
CPU time 0.58 seconds
Started Jul 05 04:33:56 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 192532 kb
Host smart-222cb217-1462-47c9-b04a-858cadf61eda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930907204 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2930907204
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1240724760
Short name T570
Test name
Test status
Simulation time 80422111 ps
CPU time 0.55 seconds
Started Jul 05 04:33:58 PM PDT 24
Finished Jul 05 04:34:01 PM PDT 24
Peak memory 182260 kb
Host smart-8c950d1c-d2b0-48c9-8b9a-d1a49a7111a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240724760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1240724760
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.967754162
Short name T544
Test name
Test status
Simulation time 12459109 ps
CPU time 0.6 seconds
Started Jul 05 04:33:58 PM PDT 24
Finished Jul 05 04:34:02 PM PDT 24
Peak memory 181668 kb
Host smart-6e0d4bea-a8ba-47ac-84c9-bc48fa2c78c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967754162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.967754162
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2034731642
Short name T84
Test name
Test status
Simulation time 20766935 ps
CPU time 0.79 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 191256 kb
Host smart-7fa77cc2-b0d4-4b20-a096-0ccce9a774a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034731642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2034731642
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2204046927
Short name T535
Test name
Test status
Simulation time 163435577 ps
CPU time 2.9 seconds
Started Jul 05 04:33:49 PM PDT 24
Finished Jul 05 04:33:53 PM PDT 24
Peak memory 191332 kb
Host smart-7b17e8d3-b140-48ae-b5ff-a132cb270c9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204046927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2204046927
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1724855102
Short name T579
Test name
Test status
Simulation time 436549876 ps
CPU time 1.36 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:04 PM PDT 24
Peak memory 182680 kb
Host smart-891fba5d-3f65-4697-8288-46d2d6ce7ab0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724855102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1724855102
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1956680999
Short name T536
Test name
Test status
Simulation time 14284295 ps
CPU time 0.55 seconds
Started Jul 05 04:34:00 PM PDT 24
Finished Jul 05 04:34:03 PM PDT 24
Peak memory 181688 kb
Host smart-aa7d9598-e135-4a20-8892-c0587235b241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956680999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1956680999
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.34575506
Short name T549
Test name
Test status
Simulation time 14353721 ps
CPU time 0.57 seconds
Started Jul 05 04:34:08 PM PDT 24
Finished Jul 05 04:34:12 PM PDT 24
Peak memory 182252 kb
Host smart-c8d9bdbc-a578-45b1-af65-c52990549a5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34575506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.34575506
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2131610052
Short name T568
Test name
Test status
Simulation time 19146546 ps
CPU time 0.56 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:18 PM PDT 24
Peak memory 182200 kb
Host smart-36e1c851-8f9e-49b7-a869-722c88a8b14a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131610052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2131610052
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3745758451
Short name T548
Test name
Test status
Simulation time 17018234 ps
CPU time 0.52 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 181824 kb
Host smart-b2c5a000-7c3f-42c9-91a3-5bf08b262e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745758451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3745758451
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1310187893
Short name T558
Test name
Test status
Simulation time 32873307 ps
CPU time 0.55 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 181568 kb
Host smart-1c21e62d-d8b9-439c-8088-0f7279d80261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310187893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1310187893
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4050904205
Short name T470
Test name
Test status
Simulation time 49263267 ps
CPU time 0.58 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 182156 kb
Host smart-d461c319-b54a-4b87-95b2-0db57f50373a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050904205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4050904205
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1506763588
Short name T580
Test name
Test status
Simulation time 34300132 ps
CPU time 0.56 seconds
Started Jul 05 04:34:08 PM PDT 24
Finished Jul 05 04:34:12 PM PDT 24
Peak memory 182196 kb
Host smart-e5d10315-1e66-4fff-bfc2-acadd4ebe0dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506763588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1506763588
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1690609291
Short name T537
Test name
Test status
Simulation time 11056905 ps
CPU time 0.54 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 182112 kb
Host smart-afb53d25-73fd-4c53-986d-b8b228beb982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690609291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1690609291
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2435532078
Short name T563
Test name
Test status
Simulation time 47549679 ps
CPU time 0.57 seconds
Started Jul 05 04:34:08 PM PDT 24
Finished Jul 05 04:34:12 PM PDT 24
Peak memory 182212 kb
Host smart-6f70afbb-a65d-440e-b89c-937f1210bae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435532078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2435532078
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3877517919
Short name T514
Test name
Test status
Simulation time 13726321 ps
CPU time 0.57 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:18 PM PDT 24
Peak memory 182180 kb
Host smart-c0b51a57-dc65-4e9d-a607-db304bcee949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877517919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3877517919
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.4193877505
Short name T543
Test name
Test status
Simulation time 157584130 ps
CPU time 0.8 seconds
Started Jul 05 04:34:06 PM PDT 24
Finished Jul 05 04:34:10 PM PDT 24
Peak memory 191960 kb
Host smart-c54773a4-8ee5-4f44-952e-6b8506c66878
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193877505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.4193877505
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3834439666
Short name T476
Test name
Test status
Simulation time 61945446 ps
CPU time 2.34 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:04 PM PDT 24
Peak memory 190672 kb
Host smart-f94b9f15-6c49-4a06-88e3-0c9ebc81cd93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834439666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3834439666
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.2826258890
Short name T86
Test name
Test status
Simulation time 31054259 ps
CPU time 0.59 seconds
Started Jul 05 04:33:56 PM PDT 24
Finished Jul 05 04:33:59 PM PDT 24
Peak memory 181824 kb
Host smart-3a55000b-2517-4053-b9a2-de236e686902
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826258890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.2826258890
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2995058196
Short name T49
Test name
Test status
Simulation time 42033620 ps
CPU time 0.96 seconds
Started Jul 05 04:33:56 PM PDT 24
Finished Jul 05 04:33:59 PM PDT 24
Peak memory 196700 kb
Host smart-a1dc6fb2-727a-41d8-aa8c-9fa2a98fc774
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995058196 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2995058196
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.948829128
Short name T534
Test name
Test status
Simulation time 15974786 ps
CPU time 0.58 seconds
Started Jul 05 04:34:05 PM PDT 24
Finished Jul 05 04:34:08 PM PDT 24
Peak memory 182304 kb
Host smart-7f2fe65a-3535-40c4-81c5-c46de3cf2ea2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948829128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.948829128
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2071795871
Short name T578
Test name
Test status
Simulation time 58803518 ps
CPU time 0.58 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:02 PM PDT 24
Peak memory 182164 kb
Host smart-113807a5-e43d-42e6-8d3d-5704c3c8a4a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071795871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2071795871
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2318921217
Short name T522
Test name
Test status
Simulation time 174417681 ps
CPU time 0.85 seconds
Started Jul 05 04:33:53 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 193096 kb
Host smart-ea31573a-9851-468d-8901-5b4787d38972
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318921217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2318921217
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1689134466
Short name T521
Test name
Test status
Simulation time 250271146 ps
CPU time 2.52 seconds
Started Jul 05 04:34:01 PM PDT 24
Finished Jul 05 04:34:07 PM PDT 24
Peak memory 191748 kb
Host smart-b7652845-fb28-42bd-beb3-8755e99840a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689134466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1689134466
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.984721886
Short name T496
Test name
Test status
Simulation time 328610481 ps
CPU time 1.11 seconds
Started Jul 05 04:33:57 PM PDT 24
Finished Jul 05 04:34:00 PM PDT 24
Peak memory 194876 kb
Host smart-4e202c80-6b9f-4250-9dac-92df357e7d28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984721886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.984721886
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3107192881
Short name T501
Test name
Test status
Simulation time 48689146 ps
CPU time 0.55 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 182188 kb
Host smart-8ba703c9-3eb0-423f-b6bb-dbdf048cc8eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107192881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3107192881
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3458267695
Short name T480
Test name
Test status
Simulation time 13835674 ps
CPU time 0.53 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 181652 kb
Host smart-54a3bc11-bb03-4ce1-b8c4-7274d74ccc30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458267695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3458267695
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1185157535
Short name T477
Test name
Test status
Simulation time 23819554 ps
CPU time 0.58 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:18 PM PDT 24
Peak memory 182136 kb
Host smart-91d08e57-d733-462c-a604-95fa9a795100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185157535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1185157535
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3441113047
Short name T533
Test name
Test status
Simulation time 44189346 ps
CPU time 0.55 seconds
Started Jul 05 04:34:05 PM PDT 24
Finished Jul 05 04:34:08 PM PDT 24
Peak memory 182248 kb
Host smart-ee3716b7-ae67-4de5-9759-3f5758ff34eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441113047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3441113047
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.4291647972
Short name T483
Test name
Test status
Simulation time 30792294 ps
CPU time 0.53 seconds
Started Jul 05 04:34:01 PM PDT 24
Finished Jul 05 04:34:05 PM PDT 24
Peak memory 181672 kb
Host smart-469c53d0-c905-4cc2-8573-634680e1257e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291647972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.4291647972
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2918735707
Short name T565
Test name
Test status
Simulation time 57107351 ps
CPU time 0.54 seconds
Started Jul 05 04:34:15 PM PDT 24
Finished Jul 05 04:34:21 PM PDT 24
Peak memory 182204 kb
Host smart-0fe07928-d1bc-446e-adbc-bf87d05b61f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918735707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2918735707
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.101249749
Short name T469
Test name
Test status
Simulation time 20349435 ps
CPU time 0.59 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 182204 kb
Host smart-2606bf3b-cff2-46c1-b82b-6ad7bd7b16cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101249749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.101249749
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2176751494
Short name T526
Test name
Test status
Simulation time 20886883 ps
CPU time 0.55 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 181620 kb
Host smart-fad6dcdb-c6b3-4f4a-a1ee-2f92c412c0cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176751494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2176751494
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3276923096
Short name T550
Test name
Test status
Simulation time 114310459 ps
CPU time 0.6 seconds
Started Jul 05 04:34:08 PM PDT 24
Finished Jul 05 04:34:12 PM PDT 24
Peak memory 182204 kb
Host smart-ce40239b-c90d-4c5a-8824-9eccaa49501c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276923096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3276923096
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.325943132
Short name T524
Test name
Test status
Simulation time 14762527 ps
CPU time 0.59 seconds
Started Jul 05 04:34:14 PM PDT 24
Finished Jul 05 04:34:20 PM PDT 24
Peak memory 181852 kb
Host smart-9f719702-1062-4735-8d06-fcdc6135bb0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325943132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.325943132
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3085145362
Short name T87
Test name
Test status
Simulation time 54835723 ps
CPU time 0.7 seconds
Started Jul 05 04:33:55 PM PDT 24
Finished Jul 05 04:33:56 PM PDT 24
Peak memory 191744 kb
Host smart-998c8ff8-d17e-4db9-a6db-c5b794ea7efd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085145362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3085145362
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.929580823
Short name T566
Test name
Test status
Simulation time 167832708 ps
CPU time 2.21 seconds
Started Jul 05 04:34:02 PM PDT 24
Finished Jul 05 04:34:08 PM PDT 24
Peak memory 191912 kb
Host smart-90578a6b-7ae6-4a0e-904f-b90a51fca570
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929580823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.929580823
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1655148681
Short name T553
Test name
Test status
Simulation time 67087414 ps
CPU time 0.63 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 182248 kb
Host smart-df9987e2-c7e0-4484-8fa7-41d8116d61b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655148681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1655148681
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.313042854
Short name T542
Test name
Test status
Simulation time 99497815 ps
CPU time 0.64 seconds
Started Jul 05 04:34:04 PM PDT 24
Finished Jul 05 04:34:07 PM PDT 24
Peak memory 193248 kb
Host smart-404e0535-39db-4f41-9b12-b243dd56e72b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313042854 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.313042854
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2656965657
Short name T529
Test name
Test status
Simulation time 14880181 ps
CPU time 0.54 seconds
Started Jul 05 04:34:08 PM PDT 24
Finished Jul 05 04:34:12 PM PDT 24
Peak memory 182192 kb
Host smart-04cc52fd-5bd3-4c91-85bb-29355957f7cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656965657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2656965657
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1615486756
Short name T486
Test name
Test status
Simulation time 14489462 ps
CPU time 0.57 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 04:34:13 PM PDT 24
Peak memory 181684 kb
Host smart-d37ae102-7525-4712-91ce-4c3787e98403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615486756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1615486756
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2095570556
Short name T575
Test name
Test status
Simulation time 30696408 ps
CPU time 0.72 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 192872 kb
Host smart-00532a04-5970-447f-b2bb-bc7bb15a5645
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095570556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2095570556
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3306005395
Short name T462
Test name
Test status
Simulation time 866732218 ps
CPU time 3.12 seconds
Started Jul 05 04:34:08 PM PDT 24
Finished Jul 05 04:34:14 PM PDT 24
Peak memory 197060 kb
Host smart-7eceb4c5-3183-4c06-b9ed-5da27c2ac4c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306005395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3306005395
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.363665497
Short name T499
Test name
Test status
Simulation time 470560842 ps
CPU time 1.45 seconds
Started Jul 05 04:33:58 PM PDT 24
Finished Jul 05 04:34:03 PM PDT 24
Peak memory 194720 kb
Host smart-cbae340f-ff5b-45e5-89fd-a86b9dc0e311
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363665497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.363665497
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1853662213
Short name T511
Test name
Test status
Simulation time 11792747 ps
CPU time 0.54 seconds
Started Jul 05 04:34:06 PM PDT 24
Finished Jul 05 04:34:10 PM PDT 24
Peak memory 181688 kb
Host smart-2b3d2aad-aec4-4928-a2e0-f7de9345f7ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853662213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1853662213
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1613980914
Short name T465
Test name
Test status
Simulation time 15065906 ps
CPU time 0.56 seconds
Started Jul 05 04:34:10 PM PDT 24
Finished Jul 05 04:34:15 PM PDT 24
Peak memory 182240 kb
Host smart-16ccd655-ff4e-4484-807b-ae308404a2e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613980914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1613980914
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2112779925
Short name T510
Test name
Test status
Simulation time 14220504 ps
CPU time 0.56 seconds
Started Jul 05 04:34:06 PM PDT 24
Finished Jul 05 04:34:10 PM PDT 24
Peak memory 182248 kb
Host smart-1e13e1f4-ad5c-4f1d-abbf-7fdff7c6b1dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112779925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2112779925
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3686120303
Short name T540
Test name
Test status
Simulation time 27770597 ps
CPU time 0.59 seconds
Started Jul 05 04:34:13 PM PDT 24
Finished Jul 05 04:34:20 PM PDT 24
Peak memory 181688 kb
Host smart-f974b919-7b73-4255-9da8-65aaba5cd277
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686120303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3686120303
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2311593813
Short name T481
Test name
Test status
Simulation time 28373722 ps
CPU time 0.56 seconds
Started Jul 05 04:34:19 PM PDT 24
Finished Jul 05 04:34:23 PM PDT 24
Peak memory 182164 kb
Host smart-a5335e52-aa0a-4089-8882-0edffeaa63f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311593813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2311593813
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.241517115
Short name T503
Test name
Test status
Simulation time 13553503 ps
CPU time 0.54 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 181684 kb
Host smart-e3a61bb1-0636-488a-9912-9a5e2dd1123f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241517115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.241517115
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3296059578
Short name T546
Test name
Test status
Simulation time 25782400 ps
CPU time 0.56 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:18 PM PDT 24
Peak memory 182176 kb
Host smart-8a90f40c-c9a5-4582-9095-134d2c200db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296059578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3296059578
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.295936996
Short name T472
Test name
Test status
Simulation time 39588804 ps
CPU time 0.57 seconds
Started Jul 05 04:34:34 PM PDT 24
Finished Jul 05 04:34:36 PM PDT 24
Peak memory 182160 kb
Host smart-758bc140-9b6b-4a23-916c-192d1209e356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295936996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.295936996
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1909866092
Short name T516
Test name
Test status
Simulation time 66124873 ps
CPU time 0.59 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 182244 kb
Host smart-2909a1bb-a9eb-4513-9118-fd646a139d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909866092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1909866092
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.3657137087
Short name T498
Test name
Test status
Simulation time 12637668 ps
CPU time 0.56 seconds
Started Jul 05 04:34:28 PM PDT 24
Finished Jul 05 04:34:29 PM PDT 24
Peak memory 182184 kb
Host smart-cdcdd5ee-3452-4df1-9341-0cec0ba088e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657137087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.3657137087
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2981478685
Short name T497
Test name
Test status
Simulation time 31927917 ps
CPU time 0.91 seconds
Started Jul 05 04:33:58 PM PDT 24
Finished Jul 05 04:34:01 PM PDT 24
Peak memory 196948 kb
Host smart-0cb80804-a4cc-489f-a693-660063d755ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981478685 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2981478685
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3241075716
Short name T88
Test name
Test status
Simulation time 22724283 ps
CPU time 0.54 seconds
Started Jul 05 04:34:11 PM PDT 24
Finished Jul 05 04:34:17 PM PDT 24
Peak memory 182320 kb
Host smart-6e36cc08-d770-4a8e-b107-75a44afd034e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241075716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3241075716
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3876466558
Short name T473
Test name
Test status
Simulation time 47026707 ps
CPU time 0.57 seconds
Started Jul 05 04:34:04 PM PDT 24
Finished Jul 05 04:34:07 PM PDT 24
Peak memory 182164 kb
Host smart-d0ef8d03-ca6b-4066-a6e0-0d529838b843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876466558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3876466558
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3699569501
Short name T560
Test name
Test status
Simulation time 31000706 ps
CPU time 0.72 seconds
Started Jul 05 04:34:12 PM PDT 24
Finished Jul 05 04:34:19 PM PDT 24
Peak memory 191160 kb
Host smart-adb861ad-5681-4f03-98c5-62fa4e01aa67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699569501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3699569501
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2423966088
Short name T561
Test name
Test status
Simulation time 499106146 ps
CPU time 2.09 seconds
Started Jul 05 04:33:53 PM PDT 24
Finished Jul 05 04:33:56 PM PDT 24
Peak memory 197120 kb
Host smart-4fbc3965-91cc-4d31-8e25-5f5a9ccca719
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423966088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2423966088
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2181267733
Short name T492
Test name
Test status
Simulation time 93502891 ps
CPU time 1.04 seconds
Started Jul 05 04:34:08 PM PDT 24
Finished Jul 05 04:34:13 PM PDT 24
Peak memory 194788 kb
Host smart-916d43b1-838c-46cd-9856-2de985a8b32a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181267733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2181267733
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3384159087
Short name T484
Test name
Test status
Simulation time 26256168 ps
CPU time 0.75 seconds
Started Jul 05 04:33:58 PM PDT 24
Finished Jul 05 04:34:02 PM PDT 24
Peak memory 194120 kb
Host smart-637ffc5c-c59a-474b-8e16-83db59596f61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384159087 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3384159087
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1807472458
Short name T93
Test name
Test status
Simulation time 17989303 ps
CPU time 0.57 seconds
Started Jul 05 04:34:03 PM PDT 24
Finished Jul 05 04:34:06 PM PDT 24
Peak memory 182344 kb
Host smart-557e1739-d0a4-4919-8250-4547d22cd5c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807472458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1807472458
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3493743077
Short name T515
Test name
Test status
Simulation time 29947504 ps
CPU time 0.57 seconds
Started Jul 05 04:34:09 PM PDT 24
Finished Jul 05 04:34:15 PM PDT 24
Peak memory 182160 kb
Host smart-444fc078-364d-4034-b7b4-76d728497e00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493743077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3493743077
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3092433382
Short name T82
Test name
Test status
Simulation time 26970617 ps
CPU time 0.58 seconds
Started Jul 05 04:34:01 PM PDT 24
Finished Jul 05 04:34:04 PM PDT 24
Peak memory 190720 kb
Host smart-3cce8547-2f5a-41bb-86b9-b226940c5c0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092433382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3092433382
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3069622998
Short name T459
Test name
Test status
Simulation time 539751094 ps
CPU time 2.95 seconds
Started Jul 05 04:33:56 PM PDT 24
Finished Jul 05 04:34:01 PM PDT 24
Peak memory 196960 kb
Host smart-f7d32767-ac3a-4fd2-b9f3-b4c666dccf82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069622998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3069622998
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2146155338
Short name T500
Test name
Test status
Simulation time 19670696 ps
CPU time 0.81 seconds
Started Jul 05 04:34:01 PM PDT 24
Finished Jul 05 04:34:05 PM PDT 24
Peak memory 195616 kb
Host smart-0a585112-b4a0-496d-81e3-64a11d67f22e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146155338 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2146155338
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2678489474
Short name T89
Test name
Test status
Simulation time 63407479 ps
CPU time 0.55 seconds
Started Jul 05 04:33:56 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 182264 kb
Host smart-4c8e7a67-5587-4eb5-b312-43cc1d4c92b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678489474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2678489474
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2802623037
Short name T485
Test name
Test status
Simulation time 15405821 ps
CPU time 0.57 seconds
Started Jul 05 04:33:52 PM PDT 24
Finished Jul 05 04:33:54 PM PDT 24
Peak memory 182124 kb
Host smart-773e1f64-605e-49e6-84fd-500f7959c937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802623037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2802623037
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1114773813
Short name T54
Test name
Test status
Simulation time 176520557 ps
CPU time 0.84 seconds
Started Jul 05 04:33:59 PM PDT 24
Finished Jul 05 04:34:03 PM PDT 24
Peak memory 192924 kb
Host smart-633b09f1-a871-4436-b33f-ebcccf033450
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114773813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1114773813
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.36185941
Short name T573
Test name
Test status
Simulation time 208828562 ps
CPU time 1.55 seconds
Started Jul 05 04:33:51 PM PDT 24
Finished Jul 05 04:33:54 PM PDT 24
Peak memory 197104 kb
Host smart-c5133cbb-f2b1-4a72-9875-48762784b1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36185941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.36185941
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.687328313
Short name T530
Test name
Test status
Simulation time 93808688 ps
CPU time 0.88 seconds
Started Jul 05 04:33:58 PM PDT 24
Finished Jul 05 04:34:01 PM PDT 24
Peak memory 193324 kb
Host smart-64cc3cd5-dc60-47d2-b3cb-6aa65f0735a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687328313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.687328313
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1639550212
Short name T487
Test name
Test status
Simulation time 21568291 ps
CPU time 1.01 seconds
Started Jul 05 04:34:15 PM PDT 24
Finished Jul 05 04:34:21 PM PDT 24
Peak memory 196848 kb
Host smart-b38a01db-ecea-4a41-9bf2-17a4c70cabee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639550212 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1639550212
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.461506136
Short name T478
Test name
Test status
Simulation time 14724910 ps
CPU time 0.57 seconds
Started Jul 05 04:33:58 PM PDT 24
Finished Jul 05 04:34:01 PM PDT 24
Peak memory 182264 kb
Host smart-ecf282cc-4f31-4514-8be1-6e6468f68720
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461506136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.461506136
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1065460396
Short name T545
Test name
Test status
Simulation time 49501989 ps
CPU time 0.61 seconds
Started Jul 05 04:33:58 PM PDT 24
Finished Jul 05 04:34:01 PM PDT 24
Peak memory 182132 kb
Host smart-7b221cce-5d62-4355-a58a-439b26f85df9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065460396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1065460396
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3080811225
Short name T100
Test name
Test status
Simulation time 14524096 ps
CPU time 0.64 seconds
Started Jul 05 04:33:54 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 191548 kb
Host smart-7513ea73-e4a0-4447-bdc0-0969a6498c38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080811225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3080811225
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1512983684
Short name T509
Test name
Test status
Simulation time 50483600 ps
CPU time 2.5 seconds
Started Jul 05 04:33:55 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 197052 kb
Host smart-e66ec4e6-2e49-4b6f-aaa7-5a47ba27983a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512983684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1512983684
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4279657820
Short name T116
Test name
Test status
Simulation time 226481454 ps
CPU time 1.02 seconds
Started Jul 05 04:33:57 PM PDT 24
Finished Jul 05 04:34:01 PM PDT 24
Peak memory 182800 kb
Host smart-05b8bb86-c3f9-4d99-826a-c0a342810a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279657820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.4279657820
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1154744877
Short name T518
Test name
Test status
Simulation time 38718845 ps
CPU time 0.65 seconds
Started Jul 05 04:33:55 PM PDT 24
Finished Jul 05 04:33:57 PM PDT 24
Peak memory 193836 kb
Host smart-98bdff9c-d62a-462e-a80a-ebb4140522a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154744877 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1154744877
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1526453434
Short name T99
Test name
Test status
Simulation time 26096480 ps
CPU time 0.57 seconds
Started Jul 05 04:34:03 PM PDT 24
Finished Jul 05 04:34:07 PM PDT 24
Peak memory 182348 kb
Host smart-c263b4c5-e76c-4127-a839-75928a515eb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526453434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1526453434
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.514807375
Short name T457
Test name
Test status
Simulation time 119364565 ps
CPU time 0.52 seconds
Started Jul 05 04:33:53 PM PDT 24
Finished Jul 05 04:33:55 PM PDT 24
Peak memory 181708 kb
Host smart-c87f47c0-4868-436a-aae7-2f60a014ce45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514807375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.514807375
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2857147412
Short name T83
Test name
Test status
Simulation time 65970084 ps
CPU time 0.74 seconds
Started Jul 05 04:33:56 PM PDT 24
Finished Jul 05 04:33:58 PM PDT 24
Peak memory 192844 kb
Host smart-3fa3799c-28ff-4f23-995c-62704ba7d6ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857147412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2857147412
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3907415258
Short name T574
Test name
Test status
Simulation time 20703071 ps
CPU time 1.04 seconds
Started Jul 05 04:34:08 PM PDT 24
Finished Jul 05 04:34:13 PM PDT 24
Peak memory 196912 kb
Host smart-f91ef41e-3046-4f49-88a3-9a3738d2ecf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907415258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3907415258
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1885592302
Short name T479
Test name
Test status
Simulation time 764411034 ps
CPU time 1.38 seconds
Started Jul 05 04:34:03 PM PDT 24
Finished Jul 05 04:34:07 PM PDT 24
Peak memory 195068 kb
Host smart-d73fccb8-e167-42bf-86ad-e67c916a3abd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885592302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1885592302
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2006196124
Short name T448
Test name
Test status
Simulation time 35854579758 ps
CPU time 22.08 seconds
Started Jul 05 05:01:33 PM PDT 24
Finished Jul 05 05:01:55 PM PDT 24
Peak memory 183084 kb
Host smart-64577975-a351-4ea4-8779-cdd741354853
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006196124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2006196124
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3407580509
Short name T443
Test name
Test status
Simulation time 100842935925 ps
CPU time 127.85 seconds
Started Jul 05 05:01:33 PM PDT 24
Finished Jul 05 05:03:41 PM PDT 24
Peak memory 183132 kb
Host smart-17150bbc-c835-4bf8-9a2f-e2a2f5f21fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407580509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3407580509
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3663235039
Short name T367
Test name
Test status
Simulation time 213413001 ps
CPU time 1.11 seconds
Started Jul 05 05:01:35 PM PDT 24
Finished Jul 05 05:01:36 PM PDT 24
Peak memory 182892 kb
Host smart-bc1a5bfa-5fa8-429c-a86f-de32dfa19e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663235039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3663235039
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.39760047
Short name T24
Test name
Test status
Simulation time 6699098694 ps
CPU time 10.25 seconds
Started Jul 05 05:02:05 PM PDT 24
Finished Jul 05 05:02:16 PM PDT 24
Peak memory 183048 kb
Host smart-eae2f52a-b07d-447d-bfb3-67ab088ed086
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39760047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
rv_timer_cfg_update_on_fly.39760047
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1780409161
Short name T403
Test name
Test status
Simulation time 459367227240 ps
CPU time 185.57 seconds
Started Jul 05 05:02:02 PM PDT 24
Finished Jul 05 05:05:08 PM PDT 24
Peak memory 183128 kb
Host smart-98b29f7d-3e4d-4d92-ab4a-7d8484c5430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780409161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1780409161
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2055931693
Short name T17
Test name
Test status
Simulation time 318114488 ps
CPU time 0.9 seconds
Started Jul 05 05:02:19 PM PDT 24
Finished Jul 05 05:02:20 PM PDT 24
Peak memory 214432 kb
Host smart-00d2731e-0241-403d-a0d3-6214ede7070a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055931693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2055931693
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3608862079
Short name T80
Test name
Test status
Simulation time 19359510523 ps
CPU time 30.53 seconds
Started Jul 05 05:02:04 PM PDT 24
Finished Jul 05 05:02:36 PM PDT 24
Peak memory 183140 kb
Host smart-70dbcb12-4fd9-487f-a11c-c4cd3152c13c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608862079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3608862079
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random.2304300064
Short name T200
Test name
Test status
Simulation time 137010680768 ps
CPU time 288.07 seconds
Started Jul 05 05:02:33 PM PDT 24
Finished Jul 05 05:07:22 PM PDT 24
Peak memory 191300 kb
Host smart-343f851c-46d0-4c39-8c23-0aad0bca17f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304300064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2304300064
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2212977500
Short name T338
Test name
Test status
Simulation time 141074621215 ps
CPU time 124.88 seconds
Started Jul 05 05:02:40 PM PDT 24
Finished Jul 05 05:04:45 PM PDT 24
Peak memory 194932 kb
Host smart-5885d9ef-1505-4995-842b-9a306e07675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212977500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2212977500
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1117511297
Short name T365
Test name
Test status
Simulation time 320037532644 ps
CPU time 310.72 seconds
Started Jul 05 05:02:54 PM PDT 24
Finished Jul 05 05:08:06 PM PDT 24
Peak memory 191312 kb
Host smart-f1d29750-ff1b-4c35-99b7-2f629588022a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117511297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1117511297
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.545295606
Short name T35
Test name
Test status
Simulation time 26791004032 ps
CPU time 225.28 seconds
Started Jul 05 05:02:40 PM PDT 24
Finished Jul 05 05:06:25 PM PDT 24
Peak memory 197880 kb
Host smart-1cbe48dd-d835-49da-bf68-2007a287fd66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545295606 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.545295606
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.1434937895
Short name T447
Test name
Test status
Simulation time 209526309232 ps
CPU time 190.5 seconds
Started Jul 05 05:07:01 PM PDT 24
Finished Jul 05 05:10:12 PM PDT 24
Peak memory 193564 kb
Host smart-aaf2424e-1fb7-4fe4-86f4-26f466193ccd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434937895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1434937895
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.727896070
Short name T140
Test name
Test status
Simulation time 55276851601 ps
CPU time 410.26 seconds
Started Jul 05 05:07:09 PM PDT 24
Finished Jul 05 05:14:00 PM PDT 24
Peak memory 191228 kb
Host smart-d5d3ef76-cb21-4088-8399-b54d194607c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727896070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.727896070
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.4209717713
Short name T413
Test name
Test status
Simulation time 238133847089 ps
CPU time 304.84 seconds
Started Jul 05 05:07:09 PM PDT 24
Finished Jul 05 05:12:14 PM PDT 24
Peak memory 191348 kb
Host smart-c28b88c7-1db3-46ad-a02c-c0c5c58bcb89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209717713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.4209717713
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.543812139
Short name T284
Test name
Test status
Simulation time 190225380615 ps
CPU time 137.37 seconds
Started Jul 05 05:07:11 PM PDT 24
Finished Jul 05 05:09:28 PM PDT 24
Peak memory 191344 kb
Host smart-ae0063d6-a5f4-407e-8bd3-096d243d80c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543812139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.543812139
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3894867490
Short name T251
Test name
Test status
Simulation time 74210293001 ps
CPU time 830.41 seconds
Started Jul 05 05:07:13 PM PDT 24
Finished Jul 05 05:21:04 PM PDT 24
Peak memory 191276 kb
Host smart-9f64715a-1da3-48fe-99cb-ca31098e36f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894867490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3894867490
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2658474073
Short name T42
Test name
Test status
Simulation time 282398150942 ps
CPU time 217.9 seconds
Started Jul 05 05:07:12 PM PDT 24
Finished Jul 05 05:10:50 PM PDT 24
Peak memory 191340 kb
Host smart-19f304fd-8a58-4703-a556-c1587df2cda8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658474073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2658474073
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2733166408
Short name T245
Test name
Test status
Simulation time 169265156142 ps
CPU time 88.42 seconds
Started Jul 05 05:02:54 PM PDT 24
Finished Jul 05 05:04:23 PM PDT 24
Peak memory 183092 kb
Host smart-dd6bd84f-0457-43a4-ab89-24d69e502e7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733166408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2733166408
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2719108014
Short name T422
Test name
Test status
Simulation time 39890982323 ps
CPU time 57.6 seconds
Started Jul 05 05:02:49 PM PDT 24
Finished Jul 05 05:03:47 PM PDT 24
Peak memory 183056 kb
Host smart-8c74b295-dc22-4828-8015-8dde9234690e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719108014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2719108014
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.1655076508
Short name T294
Test name
Test status
Simulation time 39428318088 ps
CPU time 116.33 seconds
Started Jul 05 05:02:54 PM PDT 24
Finished Jul 05 05:04:51 PM PDT 24
Peak memory 183144 kb
Host smart-8005b772-8dff-4f85-980e-8e3d3df497a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655076508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1655076508
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.188753963
Short name T336
Test name
Test status
Simulation time 435339167027 ps
CPU time 162.16 seconds
Started Jul 05 05:02:49 PM PDT 24
Finished Jul 05 05:05:32 PM PDT 24
Peak memory 183124 kb
Host smart-bfa5db3d-f0bb-46ed-b3a2-c1fe1325bd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188753963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.188753963
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.252970947
Short name T34
Test name
Test status
Simulation time 17875459723 ps
CPU time 182.24 seconds
Started Jul 05 05:02:49 PM PDT 24
Finished Jul 05 05:05:51 PM PDT 24
Peak memory 197844 kb
Host smart-638b3579-21f3-4421-9ad7-0032f1035c25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252970947 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.252970947
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.277900926
Short name T248
Test name
Test status
Simulation time 106396653252 ps
CPU time 207.03 seconds
Started Jul 05 05:07:16 PM PDT 24
Finished Jul 05 05:10:43 PM PDT 24
Peak memory 191344 kb
Host smart-f665a0be-b7df-4acf-8cdc-3a2a9cbe7f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277900926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.277900926
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1259162533
Short name T349
Test name
Test status
Simulation time 147320073440 ps
CPU time 99.53 seconds
Started Jul 05 05:07:16 PM PDT 24
Finished Jul 05 05:08:56 PM PDT 24
Peak memory 191284 kb
Host smart-44d1461b-6d5b-4df8-8631-97065f01ef2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259162533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1259162533
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.3426958797
Short name T419
Test name
Test status
Simulation time 213353059849 ps
CPU time 68.57 seconds
Started Jul 05 05:07:15 PM PDT 24
Finished Jul 05 05:08:24 PM PDT 24
Peak memory 191332 kb
Host smart-3ef8d639-17e2-471c-b1ef-17dca932b86a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426958797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3426958797
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4058103738
Short name T292
Test name
Test status
Simulation time 722063192856 ps
CPU time 1728.16 seconds
Started Jul 05 05:07:16 PM PDT 24
Finished Jul 05 05:36:05 PM PDT 24
Peak memory 193564 kb
Host smart-d67482b0-e83c-49ab-8d77-f847c4551102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058103738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4058103738
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.970186204
Short name T264
Test name
Test status
Simulation time 479070769332 ps
CPU time 354.89 seconds
Started Jul 05 05:07:23 PM PDT 24
Finished Jul 05 05:13:18 PM PDT 24
Peak memory 191312 kb
Host smart-4dab83a4-5aa7-4eb2-ab6a-a465b3f3a3b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970186204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.970186204
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.571558278
Short name T455
Test name
Test status
Simulation time 244362393364 ps
CPU time 218.18 seconds
Started Jul 05 05:02:50 PM PDT 24
Finished Jul 05 05:06:29 PM PDT 24
Peak memory 183132 kb
Host smart-0c162596-e25e-4ff4-8184-f52ad137b725
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571558278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.571558278
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1346220907
Short name T441
Test name
Test status
Simulation time 64745476077 ps
CPU time 86.66 seconds
Started Jul 05 05:02:49 PM PDT 24
Finished Jul 05 05:04:16 PM PDT 24
Peak memory 183112 kb
Host smart-58cac7dd-c03f-41e5-9a34-6a9f2a955459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346220907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1346220907
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.4061314677
Short name T263
Test name
Test status
Simulation time 119418990365 ps
CPU time 189.31 seconds
Started Jul 05 05:02:54 PM PDT 24
Finished Jul 05 05:06:04 PM PDT 24
Peak memory 191336 kb
Host smart-31833a79-0b7d-4609-baa3-6b23f15e7c0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061314677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4061314677
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.324525622
Short name T428
Test name
Test status
Simulation time 35155126025 ps
CPU time 58.48 seconds
Started Jul 05 05:02:49 PM PDT 24
Finished Jul 05 05:03:48 PM PDT 24
Peak memory 183084 kb
Host smart-5ef0b850-1d96-4ccf-a2de-f22300ed1441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324525622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.324525622
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3763382376
Short name T23
Test name
Test status
Simulation time 72812977 ps
CPU time 0.6 seconds
Started Jul 05 05:02:50 PM PDT 24
Finished Jul 05 05:02:51 PM PDT 24
Peak memory 182980 kb
Host smart-db3088e8-7fbe-49df-a6bc-e8c415722fea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763382376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3763382376
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.2616753922
Short name T57
Test name
Test status
Simulation time 67253983182 ps
CPU time 105.39 seconds
Started Jul 05 05:07:24 PM PDT 24
Finished Jul 05 05:09:10 PM PDT 24
Peak memory 191348 kb
Host smart-9cda57f6-b58f-485f-bbc3-e4c1f6940d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616753922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2616753922
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.631058737
Short name T188
Test name
Test status
Simulation time 879897471770 ps
CPU time 345.99 seconds
Started Jul 05 05:07:24 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 191304 kb
Host smart-c627a490-b649-409f-b362-8ea04e5d8332
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631058737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.631058737
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2373941772
Short name T206
Test name
Test status
Simulation time 38879025834 ps
CPU time 64.31 seconds
Started Jul 05 05:07:22 PM PDT 24
Finished Jul 05 05:08:27 PM PDT 24
Peak memory 195016 kb
Host smart-7110d040-9bcb-4f8d-b4ca-1d2529e0b58d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373941772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2373941772
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3741547036
Short name T400
Test name
Test status
Simulation time 113833644651 ps
CPU time 56.4 seconds
Started Jul 05 05:07:28 PM PDT 24
Finished Jul 05 05:08:25 PM PDT 24
Peak memory 183140 kb
Host smart-4181ff18-5c38-4304-b576-14bec962293c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741547036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3741547036
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3461419696
Short name T325
Test name
Test status
Simulation time 407484984101 ps
CPU time 88.44 seconds
Started Jul 05 05:07:32 PM PDT 24
Finished Jul 05 05:09:01 PM PDT 24
Peak memory 183148 kb
Host smart-71a43058-6106-4226-8099-bcab22291309
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461419696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3461419696
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1926587624
Short name T246
Test name
Test status
Simulation time 100930055522 ps
CPU time 45.76 seconds
Started Jul 05 05:07:30 PM PDT 24
Finished Jul 05 05:08:16 PM PDT 24
Peak memory 183144 kb
Host smart-3e90c255-d2f9-46bc-9075-1bdd9bac9343
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926587624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1926587624
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1479763305
Short name T289
Test name
Test status
Simulation time 58372039569 ps
CPU time 1312.15 seconds
Started Jul 05 05:07:30 PM PDT 24
Finished Jul 05 05:29:23 PM PDT 24
Peak memory 191240 kb
Host smart-26f64a6c-5a98-429b-b81f-5df50d491089
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479763305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1479763305
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1720413373
Short name T117
Test name
Test status
Simulation time 106626558566 ps
CPU time 61.98 seconds
Started Jul 05 05:02:54 PM PDT 24
Finished Jul 05 05:03:56 PM PDT 24
Peak memory 183120 kb
Host smart-9a78ba4e-81b5-4105-8e81-d1d8623bbf1f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720413373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1720413373
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1165324644
Short name T373
Test name
Test status
Simulation time 239899077391 ps
CPU time 182.67 seconds
Started Jul 05 05:02:54 PM PDT 24
Finished Jul 05 05:05:57 PM PDT 24
Peak memory 183068 kb
Host smart-fcfc1ebf-58ba-48fa-8c58-1a084361976f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165324644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1165324644
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.4157321571
Short name T416
Test name
Test status
Simulation time 21391829861 ps
CPU time 19.11 seconds
Started Jul 05 05:02:56 PM PDT 24
Finished Jul 05 05:03:15 PM PDT 24
Peak memory 191332 kb
Host smart-678116ca-94fe-460b-a063-0e97afa20e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157321571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.4157321571
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2039607147
Short name T424
Test name
Test status
Simulation time 1368103591921 ps
CPU time 210.28 seconds
Started Jul 05 05:02:55 PM PDT 24
Finished Jul 05 05:06:26 PM PDT 24
Peak memory 183140 kb
Host smart-9f9bd0a4-6c81-4ef9-bc21-6c2ad8ef0efd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039607147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2039607147
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.3895005277
Short name T215
Test name
Test status
Simulation time 233077943864 ps
CPU time 90.3 seconds
Started Jul 05 05:07:36 PM PDT 24
Finished Jul 05 05:09:06 PM PDT 24
Peak memory 194588 kb
Host smart-6d22351c-acfd-4647-8a17-3b1ffdffaea0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895005277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3895005277
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1301075671
Short name T228
Test name
Test status
Simulation time 175669205515 ps
CPU time 621.91 seconds
Started Jul 05 05:07:37 PM PDT 24
Finished Jul 05 05:17:59 PM PDT 24
Peak memory 191344 kb
Host smart-87efd02b-4cc9-497e-9ab3-227d6c235997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301075671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1301075671
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.957786365
Short name T348
Test name
Test status
Simulation time 24203380022 ps
CPU time 19.58 seconds
Started Jul 05 05:07:37 PM PDT 24
Finished Jul 05 05:07:58 PM PDT 24
Peak memory 183084 kb
Host smart-a336bd8c-4fe9-4acf-a821-080dc044a0be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957786365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.957786365
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.878241461
Short name T176
Test name
Test status
Simulation time 666693353956 ps
CPU time 532.61 seconds
Started Jul 05 05:07:43 PM PDT 24
Finished Jul 05 05:16:36 PM PDT 24
Peak memory 193684 kb
Host smart-7f7a04be-2e29-42b2-8492-d57f4d27a919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878241461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.878241461
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3200500241
Short name T182
Test name
Test status
Simulation time 542307402058 ps
CPU time 301.84 seconds
Started Jul 05 05:07:49 PM PDT 24
Finished Jul 05 05:12:52 PM PDT 24
Peak memory 191264 kb
Host smart-3f89a341-469e-4767-8639-08423d6fd61e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200500241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3200500241
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3836565260
Short name T440
Test name
Test status
Simulation time 21877930614 ps
CPU time 13.47 seconds
Started Jul 05 05:03:01 PM PDT 24
Finished Jul 05 05:03:15 PM PDT 24
Peak memory 183032 kb
Host smart-13465319-f49c-4a2d-b59c-6a259696de7d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836565260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3836565260
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3627128355
Short name T411
Test name
Test status
Simulation time 177060211517 ps
CPU time 242.99 seconds
Started Jul 05 05:03:00 PM PDT 24
Finished Jul 05 05:07:04 PM PDT 24
Peak memory 183008 kb
Host smart-70aaa36e-49ad-4761-9dbe-3123d062f5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627128355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3627128355
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3176103821
Short name T56
Test name
Test status
Simulation time 197481965431 ps
CPU time 237.59 seconds
Started Jul 05 05:03:01 PM PDT 24
Finished Jul 05 05:06:59 PM PDT 24
Peak memory 193376 kb
Host smart-70f17f4e-3c9b-4a05-b393-aa5f127c4e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176103821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3176103821
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.2528043326
Short name T213
Test name
Test status
Simulation time 69281858386 ps
CPU time 401.68 seconds
Started Jul 05 05:07:50 PM PDT 24
Finished Jul 05 05:14:32 PM PDT 24
Peak memory 191248 kb
Host smart-b1b86fc6-ad45-4825-9c11-13c2279ddc24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528043326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2528043326
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.2513258391
Short name T238
Test name
Test status
Simulation time 122379280070 ps
CPU time 913.15 seconds
Started Jul 05 05:07:52 PM PDT 24
Finished Jul 05 05:23:06 PM PDT 24
Peak memory 194880 kb
Host smart-6f7384a4-2e99-43e3-ba54-44b041d25895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513258391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.2513258391
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1809018684
Short name T328
Test name
Test status
Simulation time 125616855172 ps
CPU time 46.31 seconds
Started Jul 05 05:07:58 PM PDT 24
Finished Jul 05 05:08:45 PM PDT 24
Peak memory 183096 kb
Host smart-716c7da5-82c2-4e4c-9ca3-fc33c8b6d4c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809018684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1809018684
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3924169373
Short name T437
Test name
Test status
Simulation time 29118617591 ps
CPU time 40.85 seconds
Started Jul 05 05:07:59 PM PDT 24
Finished Jul 05 05:08:40 PM PDT 24
Peak memory 183148 kb
Host smart-727e614b-f1b6-4e54-ba15-73f2776b94d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924169373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3924169373
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.4268674963
Short name T69
Test name
Test status
Simulation time 394716679136 ps
CPU time 1528.6 seconds
Started Jul 05 05:07:57 PM PDT 24
Finished Jul 05 05:33:27 PM PDT 24
Peak memory 191348 kb
Host smart-87901619-0b28-4e38-8e95-be0a1d1edf5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268674963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.4268674963
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1718491821
Short name T167
Test name
Test status
Simulation time 307304302041 ps
CPU time 756.18 seconds
Started Jul 05 05:08:00 PM PDT 24
Finished Jul 05 05:20:37 PM PDT 24
Peak memory 191348 kb
Host smart-5de9e753-533c-4456-ad79-2fc16b0db6ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718491821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1718491821
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1541043503
Short name T450
Test name
Test status
Simulation time 718634231039 ps
CPU time 291.03 seconds
Started Jul 05 05:03:04 PM PDT 24
Finished Jul 05 05:07:55 PM PDT 24
Peak memory 183092 kb
Host smart-746b7fc2-950b-4ad5-87f3-600b6d6a0c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541043503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1541043503
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3873362140
Short name T311
Test name
Test status
Simulation time 77146149602 ps
CPU time 71.36 seconds
Started Jul 05 05:03:03 PM PDT 24
Finished Jul 05 05:04:14 PM PDT 24
Peak memory 191344 kb
Host smart-7be2b6fd-41b0-45bd-bdc7-d9e954d3ce14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873362140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3873362140
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.534942041
Short name T13
Test name
Test status
Simulation time 158968816591 ps
CPU time 437.89 seconds
Started Jul 05 05:03:07 PM PDT 24
Finished Jul 05 05:10:25 PM PDT 24
Peak memory 207024 kb
Host smart-d64b7f57-1633-4010-a457-2f1326f1b40e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534942041 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.534942041
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.3262746121
Short name T19
Test name
Test status
Simulation time 15732406197 ps
CPU time 26.39 seconds
Started Jul 05 05:07:54 PM PDT 24
Finished Jul 05 05:08:21 PM PDT 24
Peak memory 183044 kb
Host smart-f79f94b7-2bfc-42eb-b198-395550146774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262746121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3262746121
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2192534085
Short name T222
Test name
Test status
Simulation time 926324771024 ps
CPU time 435.15 seconds
Started Jul 05 05:07:56 PM PDT 24
Finished Jul 05 05:15:12 PM PDT 24
Peak memory 191344 kb
Host smart-160f172b-274b-4279-82e3-fa42202ea7dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192534085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2192534085
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3552465420
Short name T326
Test name
Test status
Simulation time 553703293951 ps
CPU time 163.07 seconds
Started Jul 05 05:07:57 PM PDT 24
Finished Jul 05 05:10:41 PM PDT 24
Peak memory 191300 kb
Host smart-b16cefb5-e6bb-4063-af62-edcba6c1bae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552465420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3552465420
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1903334481
Short name T249
Test name
Test status
Simulation time 45582146674 ps
CPU time 79.81 seconds
Started Jul 05 05:07:56 PM PDT 24
Finished Jul 05 05:09:17 PM PDT 24
Peak memory 183144 kb
Host smart-1ad418a9-0066-438b-a19a-95229713cb6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903334481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1903334481
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1581961917
Short name T125
Test name
Test status
Simulation time 59992007506 ps
CPU time 88.51 seconds
Started Jul 05 05:07:56 PM PDT 24
Finished Jul 05 05:09:26 PM PDT 24
Peak memory 191240 kb
Host smart-65f3838d-8db5-4df7-b640-a6c2aaa0136a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581961917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1581961917
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.762377702
Short name T174
Test name
Test status
Simulation time 749418030422 ps
CPU time 846.2 seconds
Started Jul 05 05:08:03 PM PDT 24
Finished Jul 05 05:22:10 PM PDT 24
Peak memory 191304 kb
Host smart-a4845c6c-b353-4a61-a355-e2db9f063667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762377702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.762377702
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3634487614
Short name T321
Test name
Test status
Simulation time 480899278570 ps
CPU time 311.99 seconds
Started Jul 05 05:08:01 PM PDT 24
Finished Jul 05 05:13:14 PM PDT 24
Peak memory 191248 kb
Host smart-fe659641-8390-48af-b730-77b8e6995987
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634487614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3634487614
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1976689027
Short name T210
Test name
Test status
Simulation time 751169747300 ps
CPU time 612.56 seconds
Started Jul 05 05:03:08 PM PDT 24
Finished Jul 05 05:13:21 PM PDT 24
Peak memory 183092 kb
Host smart-413c4d08-3c8e-441c-85d3-56c2fbe909c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976689027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1976689027
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3180161485
Short name T385
Test name
Test status
Simulation time 149831916941 ps
CPU time 189.04 seconds
Started Jul 05 05:03:07 PM PDT 24
Finished Jul 05 05:06:17 PM PDT 24
Peak memory 183112 kb
Host smart-0c4e3bc8-3e00-4176-9d6b-47f32b477cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180161485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3180161485
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2794395061
Short name T194
Test name
Test status
Simulation time 94979374704 ps
CPU time 144.12 seconds
Started Jul 05 05:03:10 PM PDT 24
Finished Jul 05 05:05:35 PM PDT 24
Peak memory 191248 kb
Host smart-e957cda2-99ed-4e5b-8fc2-b43438877ed9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794395061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2794395061
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2752826094
Short name T179
Test name
Test status
Simulation time 290424406624 ps
CPU time 54.8 seconds
Started Jul 05 05:03:08 PM PDT 24
Finished Jul 05 05:04:04 PM PDT 24
Peak memory 191296 kb
Host smart-10e0d64b-ae91-4a3d-affb-0cb6db3b5ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752826094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2752826094
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.2395947551
Short name T127
Test name
Test status
Simulation time 491384577271 ps
CPU time 358.78 seconds
Started Jul 05 05:08:04 PM PDT 24
Finished Jul 05 05:14:03 PM PDT 24
Peak memory 191316 kb
Host smart-fcb6b60f-7ac8-4881-9541-e4d0a8b36791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395947551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2395947551
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.3017240957
Short name T109
Test name
Test status
Simulation time 609213553437 ps
CPU time 274.31 seconds
Started Jul 05 05:08:03 PM PDT 24
Finished Jul 05 05:12:38 PM PDT 24
Peak memory 191336 kb
Host smart-3187483c-2f6c-4202-a9f8-28ead05fe5d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017240957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3017240957
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3899817969
Short name T306
Test name
Test status
Simulation time 1393205280442 ps
CPU time 720.79 seconds
Started Jul 05 05:08:04 PM PDT 24
Finished Jul 05 05:20:05 PM PDT 24
Peak memory 191300 kb
Host smart-e5bdc651-d71a-4913-87fc-6c6582d1dc32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899817969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3899817969
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1211213644
Short name T355
Test name
Test status
Simulation time 174452558206 ps
CPU time 124.38 seconds
Started Jul 05 05:08:12 PM PDT 24
Finished Jul 05 05:10:16 PM PDT 24
Peak memory 192364 kb
Host smart-c4e0c5e5-2bfd-41d3-8089-b7ed12d536f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211213644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1211213644
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1053881030
Short name T298
Test name
Test status
Simulation time 130611030966 ps
CPU time 61.84 seconds
Started Jul 05 05:08:10 PM PDT 24
Finished Jul 05 05:09:12 PM PDT 24
Peak memory 191336 kb
Host smart-35c8df2a-d252-42b6-8a42-a1529cf53a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053881030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1053881030
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2883500807
Short name T197
Test name
Test status
Simulation time 675672071696 ps
CPU time 435.67 seconds
Started Jul 05 05:08:11 PM PDT 24
Finished Jul 05 05:15:27 PM PDT 24
Peak memory 191336 kb
Host smart-0cdaecd3-4c85-46d8-96f6-6ba1bcaa937b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883500807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2883500807
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1386044746
Short name T318
Test name
Test status
Simulation time 102304703774 ps
CPU time 146.91 seconds
Started Jul 05 05:08:48 PM PDT 24
Finished Jul 05 05:11:16 PM PDT 24
Peak memory 191276 kb
Host smart-0d150566-d096-4182-a610-4b88a075329d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386044746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1386044746
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.56190965
Short name T122
Test name
Test status
Simulation time 95997858630 ps
CPU time 50.8 seconds
Started Jul 05 05:08:17 PM PDT 24
Finished Jul 05 05:09:08 PM PDT 24
Peak memory 191308 kb
Host smart-368cb1cd-f1cf-444d-b747-57943407c2b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56190965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.56190965
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1456636518
Short name T165
Test name
Test status
Simulation time 960266444904 ps
CPU time 1079.06 seconds
Started Jul 05 05:08:17 PM PDT 24
Finished Jul 05 05:26:17 PM PDT 24
Peak memory 191340 kb
Host smart-66a007ca-873a-437b-ae22-2e950c18a393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456636518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1456636518
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.93200296
Short name T72
Test name
Test status
Simulation time 108646814182 ps
CPU time 157.65 seconds
Started Jul 05 05:03:09 PM PDT 24
Finished Jul 05 05:05:48 PM PDT 24
Peak memory 183124 kb
Host smart-2c671e64-4c33-4362-83d4-fb88e52d5318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93200296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.93200296
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.858060808
Short name T276
Test name
Test status
Simulation time 495091892742 ps
CPU time 589.09 seconds
Started Jul 05 05:03:10 PM PDT 24
Finished Jul 05 05:13:01 PM PDT 24
Peak memory 194628 kb
Host smart-a91467c4-8ad3-4bc2-bf05-3930bdbe174f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858060808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.858060808
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.294951144
Short name T152
Test name
Test status
Simulation time 526185304630 ps
CPU time 489.06 seconds
Started Jul 05 05:08:19 PM PDT 24
Finished Jul 05 05:16:29 PM PDT 24
Peak memory 191348 kb
Host smart-bf4f0c2d-7712-4d80-b912-5e3e94f42ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294951144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.294951144
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2841742344
Short name T303
Test name
Test status
Simulation time 128148697456 ps
CPU time 68.01 seconds
Started Jul 05 05:08:20 PM PDT 24
Finished Jul 05 05:09:28 PM PDT 24
Peak memory 183148 kb
Host smart-645f654a-53a4-4e3f-afef-6e4a644ab8d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841742344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2841742344
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.54242031
Short name T256
Test name
Test status
Simulation time 1036316076477 ps
CPU time 621.46 seconds
Started Jul 05 05:08:20 PM PDT 24
Finished Jul 05 05:18:42 PM PDT 24
Peak memory 191308 kb
Host smart-83864588-8b95-4ad4-8bf9-fc7145afc396
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54242031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.54242031
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.615366116
Short name T235
Test name
Test status
Simulation time 35613938787 ps
CPU time 23.68 seconds
Started Jul 05 05:08:18 PM PDT 24
Finished Jul 05 05:08:42 PM PDT 24
Peak memory 183144 kb
Host smart-f7ba7398-f495-4ffc-b83c-32fe67e0dbad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615366116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.615366116
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3974307857
Short name T244
Test name
Test status
Simulation time 168323663191 ps
CPU time 125.6 seconds
Started Jul 05 05:08:24 PM PDT 24
Finished Jul 05 05:10:30 PM PDT 24
Peak memory 191216 kb
Host smart-113615a7-9a2d-48d4-a78f-882e293f3965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974307857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3974307857
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2958515476
Short name T154
Test name
Test status
Simulation time 255699567473 ps
CPU time 778.99 seconds
Started Jul 05 05:08:23 PM PDT 24
Finished Jul 05 05:21:23 PM PDT 24
Peak memory 191288 kb
Host smart-eeeabee8-c8a2-40f8-9e79-56e8f0b3d68e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958515476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2958515476
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3007671798
Short name T132
Test name
Test status
Simulation time 163969694220 ps
CPU time 87.29 seconds
Started Jul 05 05:08:28 PM PDT 24
Finished Jul 05 05:09:56 PM PDT 24
Peak memory 191284 kb
Host smart-8b2cfa29-84f9-468b-9de7-1286d959c424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007671798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3007671798
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.309457030
Short name T315
Test name
Test status
Simulation time 437057182536 ps
CPU time 351.3 seconds
Started Jul 05 05:08:24 PM PDT 24
Finished Jul 05 05:14:16 PM PDT 24
Peak memory 191244 kb
Host smart-e73a6996-eaaf-4c12-aebf-f4ec4f60829d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309457030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.309457030
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2653500730
Short name T302
Test name
Test status
Simulation time 1349182515731 ps
CPU time 1144.62 seconds
Started Jul 05 05:03:16 PM PDT 24
Finished Jul 05 05:22:22 PM PDT 24
Peak memory 183128 kb
Host smart-0234170b-fb79-4b3a-8cdc-69b414ecd8da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653500730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2653500730
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1466200110
Short name T410
Test name
Test status
Simulation time 474017061279 ps
CPU time 157.67 seconds
Started Jul 05 05:03:16 PM PDT 24
Finished Jul 05 05:05:55 PM PDT 24
Peak memory 183128 kb
Host smart-f8c22105-67b1-47f2-a9fc-fbb11a0b2313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466200110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1466200110
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3276611299
Short name T275
Test name
Test status
Simulation time 63619137619 ps
CPU time 61.86 seconds
Started Jul 05 05:03:16 PM PDT 24
Finished Jul 05 05:04:19 PM PDT 24
Peak memory 191348 kb
Host smart-73b887ea-b432-4e0c-8e94-584b05a51dca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276611299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3276611299
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1048488121
Short name T291
Test name
Test status
Simulation time 97585940972 ps
CPU time 1238.89 seconds
Started Jul 05 05:03:16 PM PDT 24
Finished Jul 05 05:23:56 PM PDT 24
Peak memory 183144 kb
Host smart-d4efeacf-7a94-4c38-9ee4-fdd834482694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048488121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1048488121
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4146614049
Short name T236
Test name
Test status
Simulation time 197263756960 ps
CPU time 1299.37 seconds
Started Jul 05 05:03:16 PM PDT 24
Finished Jul 05 05:24:57 PM PDT 24
Peak memory 195240 kb
Host smart-6a457c4c-3c4b-4443-bff8-5df79ee0245b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146614049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4146614049
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.3458049106
Short name T269
Test name
Test status
Simulation time 188713443866 ps
CPU time 110.45 seconds
Started Jul 05 05:08:32 PM PDT 24
Finished Jul 05 05:10:24 PM PDT 24
Peak memory 183028 kb
Host smart-1154d975-9e7a-4c0c-b374-d1de6c7fdc8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458049106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3458049106
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2551038953
Short name T195
Test name
Test status
Simulation time 516807846491 ps
CPU time 426.22 seconds
Started Jul 05 05:08:34 PM PDT 24
Finished Jul 05 05:15:41 PM PDT 24
Peak memory 191348 kb
Host smart-d4300b2e-4dce-40b2-9d5e-a10da2147991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551038953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2551038953
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3497827742
Short name T351
Test name
Test status
Simulation time 152491397528 ps
CPU time 565.12 seconds
Started Jul 05 05:08:31 PM PDT 24
Finished Jul 05 05:17:57 PM PDT 24
Peak memory 191204 kb
Host smart-502dde61-329a-4cb4-b2a0-5e69a4197fb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497827742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3497827742
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2198632897
Short name T68
Test name
Test status
Simulation time 53829705069 ps
CPU time 97.77 seconds
Started Jul 05 05:08:32 PM PDT 24
Finished Jul 05 05:10:11 PM PDT 24
Peak memory 191348 kb
Host smart-b5ca4caa-12e7-4148-9aa6-d3a03482d587
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198632897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2198632897
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3364419078
Short name T170
Test name
Test status
Simulation time 370095056439 ps
CPU time 352.83 seconds
Started Jul 05 05:08:33 PM PDT 24
Finished Jul 05 05:14:27 PM PDT 24
Peak memory 191344 kb
Host smart-f85e7cec-a450-4988-9e98-f76185454ea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364419078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3364419078
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.653271275
Short name T217
Test name
Test status
Simulation time 185564044473 ps
CPU time 393.16 seconds
Started Jul 05 05:08:32 PM PDT 24
Finished Jul 05 05:15:06 PM PDT 24
Peak memory 191344 kb
Host smart-0448da21-dadf-4acf-912c-8017de797d0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653271275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.653271275
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1582103588
Short name T299
Test name
Test status
Simulation time 62023445169 ps
CPU time 98.1 seconds
Started Jul 05 05:08:34 PM PDT 24
Finished Jul 05 05:10:13 PM PDT 24
Peak memory 191344 kb
Host smart-dab49a72-d6d6-4dfb-9d4b-542e8088add7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582103588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1582103588
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3284845643
Short name T168
Test name
Test status
Simulation time 13075292445 ps
CPU time 22.17 seconds
Started Jul 05 05:03:24 PM PDT 24
Finished Jul 05 05:03:46 PM PDT 24
Peak memory 183128 kb
Host smart-d64b417a-27f7-4d48-afc5-2aef86d3a5a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284845643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3284845643
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3470645101
Short name T370
Test name
Test status
Simulation time 170866086284 ps
CPU time 264.94 seconds
Started Jul 05 05:03:22 PM PDT 24
Finished Jul 05 05:07:47 PM PDT 24
Peak memory 183088 kb
Host smart-ba69ca0e-9e40-4a6f-98f7-9da109765f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470645101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3470645101
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2458950842
Short name T76
Test name
Test status
Simulation time 109234065015 ps
CPU time 35.51 seconds
Started Jul 05 05:03:22 PM PDT 24
Finished Jul 05 05:03:58 PM PDT 24
Peak memory 193840 kb
Host smart-1fd85979-5727-451d-95da-9b84e39d77ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458950842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2458950842
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.4054999714
Short name T4
Test name
Test status
Simulation time 1941391192489 ps
CPU time 1950.73 seconds
Started Jul 05 05:03:30 PM PDT 24
Finished Jul 05 05:36:02 PM PDT 24
Peak memory 194740 kb
Host smart-437b8e8b-8b32-4f0d-8aef-f3c91802f4b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054999714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.4054999714
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.4117247492
Short name T376
Test name
Test status
Simulation time 14048642328 ps
CPU time 23.42 seconds
Started Jul 05 05:08:33 PM PDT 24
Finished Jul 05 05:08:57 PM PDT 24
Peak memory 183040 kb
Host smart-47e05cf8-45e7-4324-9359-78d3edc61f16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117247492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4117247492
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1851573252
Short name T151
Test name
Test status
Simulation time 435502589963 ps
CPU time 719.36 seconds
Started Jul 05 05:08:31 PM PDT 24
Finished Jul 05 05:20:31 PM PDT 24
Peak memory 191340 kb
Host smart-20cf6d65-950c-41a3-b144-103e24a07c83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851573252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1851573252
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.2273029477
Short name T268
Test name
Test status
Simulation time 386259815561 ps
CPU time 183.09 seconds
Started Jul 05 05:08:31 PM PDT 24
Finished Jul 05 05:11:34 PM PDT 24
Peak memory 191284 kb
Host smart-26380067-828d-44a0-b448-4c08bb50934d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273029477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.2273029477
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1872327407
Short name T304
Test name
Test status
Simulation time 176651178786 ps
CPU time 250.82 seconds
Started Jul 05 05:08:39 PM PDT 24
Finished Jul 05 05:12:51 PM PDT 24
Peak memory 191344 kb
Host smart-ce9ccb7a-a4a6-4f66-8518-8e5c5d2deb53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872327407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1872327407
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3489998823
Short name T172
Test name
Test status
Simulation time 189046896194 ps
CPU time 272.02 seconds
Started Jul 05 05:08:38 PM PDT 24
Finished Jul 05 05:13:11 PM PDT 24
Peak memory 191348 kb
Host smart-6441bdb2-924f-45ca-ad0e-549018593ab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489998823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3489998823
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3272954434
Short name T191
Test name
Test status
Simulation time 256948258670 ps
CPU time 132.46 seconds
Started Jul 05 05:08:39 PM PDT 24
Finished Jul 05 05:10:52 PM PDT 24
Peak memory 191244 kb
Host smart-f459ea53-5529-4872-99e0-ebc38e26ddb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272954434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3272954434
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3808853448
Short name T449
Test name
Test status
Simulation time 247629065857 ps
CPU time 252.66 seconds
Started Jul 05 05:08:45 PM PDT 24
Finished Jul 05 05:12:58 PM PDT 24
Peak memory 191244 kb
Host smart-7d834b60-a75e-488e-aab0-61a725b21b49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808853448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3808853448
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1495959148
Short name T260
Test name
Test status
Simulation time 526263678310 ps
CPU time 350.4 seconds
Started Jul 05 05:08:40 PM PDT 24
Finished Jul 05 05:14:31 PM PDT 24
Peak memory 191340 kb
Host smart-845a322f-2873-426d-a1a9-4d8a68f12fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495959148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1495959148
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3151733540
Short name T153
Test name
Test status
Simulation time 385851792938 ps
CPU time 1291.51 seconds
Started Jul 05 05:08:39 PM PDT 24
Finished Jul 05 05:30:12 PM PDT 24
Peak memory 191344 kb
Host smart-ce463500-0871-44ba-bbc6-ed5b19ea414f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151733540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3151733540
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1781396521
Short name T282
Test name
Test status
Simulation time 788019634 ps
CPU time 2.07 seconds
Started Jul 05 05:02:05 PM PDT 24
Finished Jul 05 05:02:07 PM PDT 24
Peak memory 182968 kb
Host smart-ec118268-4506-415e-aa14-370b6d7b29bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781396521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1781396521
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.4136562248
Short name T391
Test name
Test status
Simulation time 402078714001 ps
CPU time 163.07 seconds
Started Jul 05 05:02:05 PM PDT 24
Finished Jul 05 05:04:49 PM PDT 24
Peak memory 183036 kb
Host smart-aaf9497f-4c29-4dba-ba85-83bcf1ec8e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136562248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.4136562248
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3776794892
Short name T120
Test name
Test status
Simulation time 4358522888 ps
CPU time 26.29 seconds
Started Jul 05 05:02:03 PM PDT 24
Finished Jul 05 05:02:31 PM PDT 24
Peak memory 183148 kb
Host smart-de3f1b44-8fa5-4cf5-81cf-546f0978acd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776794892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3776794892
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1337710976
Short name T18
Test name
Test status
Simulation time 167262924 ps
CPU time 0.9 seconds
Started Jul 05 05:02:03 PM PDT 24
Finished Jul 05 05:02:05 PM PDT 24
Peak memory 214376 kb
Host smart-19c0be52-6128-4fa6-9fcc-619051c50e36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337710976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1337710976
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3372562307
Short name T225
Test name
Test status
Simulation time 246097339961 ps
CPU time 210.06 seconds
Started Jul 05 05:03:29 PM PDT 24
Finished Jul 05 05:07:00 PM PDT 24
Peak memory 183124 kb
Host smart-2e7e6e68-e68f-452f-a7f8-b4723c14af12
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372562307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3372562307
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.554189158
Short name T375
Test name
Test status
Simulation time 111759993239 ps
CPU time 168.4 seconds
Started Jul 05 05:03:28 PM PDT 24
Finished Jul 05 05:06:17 PM PDT 24
Peak memory 183096 kb
Host smart-ab22a322-3ef3-4f56-bf15-1c2e9acd2f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554189158 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.554189158
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.2354971617
Short name T339
Test name
Test status
Simulation time 109226791242 ps
CPU time 57.61 seconds
Started Jul 05 05:03:28 PM PDT 24
Finished Jul 05 05:04:26 PM PDT 24
Peak memory 191236 kb
Host smart-572c9bb1-b2a5-4274-9388-8c5111e63535
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354971617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2354971617
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3918909354
Short name T313
Test name
Test status
Simulation time 111154946920 ps
CPU time 325.78 seconds
Started Jul 05 05:03:29 PM PDT 24
Finished Jul 05 05:08:56 PM PDT 24
Peak memory 195064 kb
Host smart-b10e3405-59e6-4b35-83f7-0fec10206047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918909354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3918909354
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1972020832
Short name T432
Test name
Test status
Simulation time 62756343822 ps
CPU time 109.4 seconds
Started Jul 05 05:03:35 PM PDT 24
Finished Jul 05 05:05:26 PM PDT 24
Peak memory 183128 kb
Host smart-9bd69c2c-7b6b-44e3-bba1-78814b217951
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972020832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1972020832
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1085923725
Short name T412
Test name
Test status
Simulation time 172786420850 ps
CPU time 238.13 seconds
Started Jul 05 05:03:35 PM PDT 24
Finished Jul 05 05:07:34 PM PDT 24
Peak memory 183108 kb
Host smart-5636eaa1-1903-47dc-8458-f9d477a13078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085923725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1085923725
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3307448001
Short name T337
Test name
Test status
Simulation time 613801131102 ps
CPU time 524.87 seconds
Started Jul 05 05:03:35 PM PDT 24
Finished Jul 05 05:12:21 PM PDT 24
Peak memory 191264 kb
Host smart-ac2dbfb5-b662-477c-b178-9b2853b8bab5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307448001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3307448001
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1629687898
Short name T300
Test name
Test status
Simulation time 49441051917 ps
CPU time 318 seconds
Started Jul 05 05:03:35 PM PDT 24
Finished Jul 05 05:08:54 PM PDT 24
Peak memory 183156 kb
Host smart-abf05fae-0765-4e89-8eea-7360206001ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629687898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1629687898
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1147518988
Short name T196
Test name
Test status
Simulation time 2220020771940 ps
CPU time 2803.13 seconds
Started Jul 05 05:03:43 PM PDT 24
Finished Jul 05 05:50:26 PM PDT 24
Peak memory 191340 kb
Host smart-00b5fdb8-8483-4ee3-9fe4-88916670c5f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147518988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1147518988
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1669520149
Short name T134
Test name
Test status
Simulation time 93990981765 ps
CPU time 143.15 seconds
Started Jul 05 05:03:50 PM PDT 24
Finished Jul 05 05:06:14 PM PDT 24
Peak memory 183024 kb
Host smart-b1b581a7-24de-4af0-9e5c-55bc4331e21b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669520149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1669520149
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2082896314
Short name T394
Test name
Test status
Simulation time 87081329128 ps
CPU time 133.87 seconds
Started Jul 05 05:03:50 PM PDT 24
Finished Jul 05 05:06:04 PM PDT 24
Peak memory 183044 kb
Host smart-f1ca2473-f326-4fa1-9a45-2901976dbf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082896314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2082896314
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3654233493
Short name T75
Test name
Test status
Simulation time 123981202715 ps
CPU time 251.41 seconds
Started Jul 05 05:03:44 PM PDT 24
Finished Jul 05 05:07:56 PM PDT 24
Peak memory 183044 kb
Host smart-66d91b8f-7195-4a4b-8e78-c342c03cd6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654233493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3654233493
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1450888778
Short name T359
Test name
Test status
Simulation time 212462964115 ps
CPU time 80.62 seconds
Started Jul 05 05:03:51 PM PDT 24
Finished Jul 05 05:05:12 PM PDT 24
Peak memory 191268 kb
Host smart-89b55f5c-34fe-49c5-91d9-295658395508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450888778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1450888778
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1920873446
Short name T126
Test name
Test status
Simulation time 58415277095 ps
CPU time 34.35 seconds
Started Jul 05 05:03:54 PM PDT 24
Finished Jul 05 05:04:29 PM PDT 24
Peak memory 183008 kb
Host smart-c396180f-c18e-4a16-9600-4f0e26912e34
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920873446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1920873446
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2407904789
Short name T406
Test name
Test status
Simulation time 416047631956 ps
CPU time 236.18 seconds
Started Jul 05 05:03:55 PM PDT 24
Finished Jul 05 05:07:52 PM PDT 24
Peak memory 183140 kb
Host smart-c01e2d32-af9f-418e-a904-2592467971cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407904789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2407904789
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1778824676
Short name T26
Test name
Test status
Simulation time 399757868334 ps
CPU time 592.82 seconds
Started Jul 05 05:03:56 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 191336 kb
Host smart-c31a9e2f-8047-4fc1-b9e5-003e337307d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778824676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1778824676
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2045298949
Short name T113
Test name
Test status
Simulation time 388698844578 ps
CPU time 923.61 seconds
Started Jul 05 05:03:56 PM PDT 24
Finished Jul 05 05:19:20 PM PDT 24
Peak memory 206076 kb
Host smart-e5d3c572-354e-4c2f-b15f-33bfd9bfe04f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045298949 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2045298949
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1423665017
Short name T451
Test name
Test status
Simulation time 293300204724 ps
CPU time 161.53 seconds
Started Jul 05 05:03:54 PM PDT 24
Finished Jul 05 05:06:36 PM PDT 24
Peak memory 183028 kb
Host smart-1c914352-da94-423c-8ceb-6283edda0272
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423665017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1423665017
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3564643351
Short name T404
Test name
Test status
Simulation time 254752960156 ps
CPU time 111.58 seconds
Started Jul 05 05:03:55 PM PDT 24
Finished Jul 05 05:05:47 PM PDT 24
Peak memory 183040 kb
Host smart-31b81b95-b85e-46b4-93e0-ff60e28b5e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564643351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3564643351
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1104836782
Short name T334
Test name
Test status
Simulation time 13200678284 ps
CPU time 8.45 seconds
Started Jul 05 05:03:56 PM PDT 24
Finished Jul 05 05:04:05 PM PDT 24
Peak memory 194544 kb
Host smart-df4c5610-a82b-4fab-ac24-d6044e93382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104836782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1104836782
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.678445386
Short name T233
Test name
Test status
Simulation time 202768495858 ps
CPU time 105.05 seconds
Started Jul 05 05:04:11 PM PDT 24
Finished Jul 05 05:05:57 PM PDT 24
Peak memory 183132 kb
Host smart-d33a03bc-2e64-4971-bf04-ff25ea2db963
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678445386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.678445386
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1584295439
Short name T44
Test name
Test status
Simulation time 135980251643 ps
CPU time 103.72 seconds
Started Jul 05 05:04:10 PM PDT 24
Finished Jul 05 05:05:54 PM PDT 24
Peak memory 183100 kb
Host smart-8fc7e32d-1bf6-4606-84f4-b43150299b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584295439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1584295439
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.90012022
Short name T118
Test name
Test status
Simulation time 274257164902 ps
CPU time 108.16 seconds
Started Jul 05 05:04:12 PM PDT 24
Finished Jul 05 05:06:00 PM PDT 24
Peak memory 191300 kb
Host smart-34be8a22-09e4-45ae-bf5d-f37526a047c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90012022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.90012022
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.1511071303
Short name T386
Test name
Test status
Simulation time 1048885804 ps
CPU time 1.79 seconds
Started Jul 05 05:04:12 PM PDT 24
Finished Jul 05 05:04:15 PM PDT 24
Peak memory 191276 kb
Host smart-681dd37e-989c-48b2-afaf-7fb4268e6a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511071303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.1511071303
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3485217932
Short name T190
Test name
Test status
Simulation time 35546086747 ps
CPU time 52.16 seconds
Started Jul 05 05:04:17 PM PDT 24
Finished Jul 05 05:05:10 PM PDT 24
Peak memory 183120 kb
Host smart-ede9f53e-7d8d-4cfb-b1d8-ea3c8cc11f8e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485217932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3485217932
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.899020914
Short name T401
Test name
Test status
Simulation time 607475400456 ps
CPU time 240.7 seconds
Started Jul 05 05:04:18 PM PDT 24
Finished Jul 05 05:08:19 PM PDT 24
Peak memory 183096 kb
Host smart-b2ad5a59-8319-441b-abbd-5588cdaf6ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899020914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.899020914
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.640713103
Short name T309
Test name
Test status
Simulation time 17261982081 ps
CPU time 76.88 seconds
Started Jul 05 05:04:17 PM PDT 24
Finished Jul 05 05:05:34 PM PDT 24
Peak memory 191348 kb
Host smart-b6d1cea3-eb2c-401c-adac-c4d16ace7ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640713103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.640713103
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.771960272
Short name T435
Test name
Test status
Simulation time 5075951834 ps
CPU time 9.39 seconds
Started Jul 05 05:04:25 PM PDT 24
Finished Jul 05 05:04:35 PM PDT 24
Peak memory 183096 kb
Host smart-65bf5171-d71d-43e3-ba85-442ab2a423ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771960272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.rv_timer_cfg_update_on_fly.771960272
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2418984819
Short name T402
Test name
Test status
Simulation time 273990041048 ps
CPU time 116.2 seconds
Started Jul 05 05:04:28 PM PDT 24
Finished Jul 05 05:06:25 PM PDT 24
Peak memory 183144 kb
Host smart-ae2fbd37-ca67-4c80-8d80-2b412b1da3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418984819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2418984819
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2494050353
Short name T446
Test name
Test status
Simulation time 39070460165 ps
CPU time 60.69 seconds
Started Jul 05 05:04:21 PM PDT 24
Finished Jul 05 05:05:22 PM PDT 24
Peak memory 183044 kb
Host smart-e70fcbf4-4cd7-4a3d-b530-68c3881ac856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494050353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2494050353
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2884771208
Short name T308
Test name
Test status
Simulation time 61741927708 ps
CPU time 91.06 seconds
Started Jul 05 05:04:28 PM PDT 24
Finished Jul 05 05:06:00 PM PDT 24
Peak memory 191312 kb
Host smart-3734b47a-1988-48a0-aaae-21fbba6a0216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884771208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2884771208
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2903703875
Short name T297
Test name
Test status
Simulation time 2341796480322 ps
CPU time 3680.36 seconds
Started Jul 05 05:04:24 PM PDT 24
Finished Jul 05 06:05:45 PM PDT 24
Peak memory 196468 kb
Host smart-85a600b4-c6fa-4da2-8266-16fe846c0bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903703875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2903703875
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2555915229
Short name T346
Test name
Test status
Simulation time 10395008400 ps
CPU time 5.89 seconds
Started Jul 05 05:04:25 PM PDT 24
Finished Jul 05 05:04:32 PM PDT 24
Peak memory 183104 kb
Host smart-55faa58d-d9b8-4255-90e9-07b4853b4e9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555915229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2555915229
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.151430720
Short name T429
Test name
Test status
Simulation time 275438842135 ps
CPU time 199.85 seconds
Started Jul 05 05:04:25 PM PDT 24
Finished Jul 05 05:07:45 PM PDT 24
Peak memory 183124 kb
Host smart-e45986fd-d371-4036-91fa-6792435218b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151430720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.151430720
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.4049966319
Short name T242
Test name
Test status
Simulation time 286200038453 ps
CPU time 579.24 seconds
Started Jul 05 05:04:27 PM PDT 24
Finished Jul 05 05:14:07 PM PDT 24
Peak memory 191340 kb
Host smart-a1d63633-f8d1-401e-89b7-c053add6286b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049966319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4049966319
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1965524866
Short name T388
Test name
Test status
Simulation time 14245485 ps
CPU time 0.58 seconds
Started Jul 05 05:04:26 PM PDT 24
Finished Jul 05 05:04:27 PM PDT 24
Peak memory 182848 kb
Host smart-ed056ecd-0aa5-4cae-89f6-493505f5e1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965524866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1965524866
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3529947368
Short name T379
Test name
Test status
Simulation time 35206977 ps
CPU time 0.53 seconds
Started Jul 05 05:04:33 PM PDT 24
Finished Jul 05 05:04:34 PM PDT 24
Peak memory 182508 kb
Host smart-6c68b7c2-128d-46d8-960b-4622b19cc4c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529947368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3529947368
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2023491468
Short name T12
Test name
Test status
Simulation time 55798903771 ps
CPU time 490.39 seconds
Started Jul 05 05:04:24 PM PDT 24
Finished Jul 05 05:12:35 PM PDT 24
Peak memory 206096 kb
Host smart-ef87bc2b-0d86-477c-be1c-ed90f7019b5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023491468 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2023491468
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3404938906
Short name T27
Test name
Test status
Simulation time 279501605887 ps
CPU time 239.49 seconds
Started Jul 05 05:04:35 PM PDT 24
Finished Jul 05 05:08:35 PM PDT 24
Peak memory 183020 kb
Host smart-f973a6fd-0563-4b81-93a1-08a8ac3c62bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404938906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3404938906
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2278783014
Short name T420
Test name
Test status
Simulation time 212714655629 ps
CPU time 70.76 seconds
Started Jul 05 05:04:36 PM PDT 24
Finished Jul 05 05:05:47 PM PDT 24
Peak memory 183044 kb
Host smart-f0d87cc4-017c-4364-8a40-7a829193fa07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278783014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2278783014
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.4227825035
Short name T279
Test name
Test status
Simulation time 358485781225 ps
CPU time 334.63 seconds
Started Jul 05 05:04:33 PM PDT 24
Finished Jul 05 05:10:09 PM PDT 24
Peak memory 191304 kb
Host smart-814efeee-a0bd-4238-8bbf-17af048e52a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227825035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.4227825035
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.142245688
Short name T372
Test name
Test status
Simulation time 255146909313 ps
CPU time 155.2 seconds
Started Jul 05 05:04:36 PM PDT 24
Finished Jul 05 05:07:12 PM PDT 24
Peak memory 194492 kb
Host smart-da0944bc-f06d-4f2a-acfb-88adc1967ff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142245688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
142245688
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2682156492
Short name T38
Test name
Test status
Simulation time 123985184136 ps
CPU time 245.06 seconds
Started Jul 05 05:04:33 PM PDT 24
Finished Jul 05 05:08:39 PM PDT 24
Peak memory 197852 kb
Host smart-0a72b2ca-be59-4a7c-92ec-5e6dd5ab2175
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682156492 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2682156492
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3359116719
Short name T445
Test name
Test status
Simulation time 163660919935 ps
CPU time 168.68 seconds
Started Jul 05 05:02:07 PM PDT 24
Finished Jul 05 05:04:56 PM PDT 24
Peak memory 183092 kb
Host smart-205fddab-2cfd-4dd6-9d59-9c6371eb7138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359116719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3359116719
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.531429341
Short name T352
Test name
Test status
Simulation time 16838840087 ps
CPU time 29.96 seconds
Started Jul 05 05:02:05 PM PDT 24
Finished Jul 05 05:02:36 PM PDT 24
Peak memory 183148 kb
Host smart-505f7386-bc43-4525-9e4b-77cc71ea016a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531429341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.531429341
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3995189577
Short name T371
Test name
Test status
Simulation time 43900829317 ps
CPU time 23.39 seconds
Started Jul 05 05:02:07 PM PDT 24
Finished Jul 05 05:02:31 PM PDT 24
Peak memory 191336 kb
Host smart-7f83428f-5976-42f6-a5bf-ac7e61ddebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995189577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3995189577
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1004628038
Short name T15
Test name
Test status
Simulation time 346354404 ps
CPU time 0.75 seconds
Started Jul 05 05:02:06 PM PDT 24
Finished Jul 05 05:02:07 PM PDT 24
Peak memory 213396 kb
Host smart-9edbf1b9-2d68-4b15-8f8b-b2ed881d3ca7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004628038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1004628038
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4076966352
Short name T368
Test name
Test status
Simulation time 52832267457 ps
CPU time 69.31 seconds
Started Jul 05 05:02:07 PM PDT 24
Finished Jul 05 05:03:17 PM PDT 24
Peak memory 183132 kb
Host smart-31b367dd-241a-4ce1-b3b3-b424014b79b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076966352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4076966352
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3066405007
Short name T442
Test name
Test status
Simulation time 35515572143 ps
CPU time 268.95 seconds
Started Jul 05 05:02:06 PM PDT 24
Finished Jul 05 05:06:36 PM PDT 24
Peak memory 205948 kb
Host smart-fe7dc8a8-ecca-4a3c-a2a0-c4e5af80be2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066405007 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3066405007
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.395837181
Short name T254
Test name
Test status
Simulation time 311685561648 ps
CPU time 266.22 seconds
Started Jul 05 05:04:39 PM PDT 24
Finished Jul 05 05:09:05 PM PDT 24
Peak memory 183132 kb
Host smart-3889048b-51ac-4e61-95de-4179455ee245
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395837181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.395837181
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.439450599
Short name T392
Test name
Test status
Simulation time 429323127737 ps
CPU time 169.11 seconds
Started Jul 05 05:04:39 PM PDT 24
Finished Jul 05 05:07:28 PM PDT 24
Peak memory 183076 kb
Host smart-b64308a9-ee1d-4aff-bcf0-d239915ec43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439450599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.439450599
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1479436012
Short name T345
Test name
Test status
Simulation time 39888189093 ps
CPU time 76.98 seconds
Started Jul 05 05:04:40 PM PDT 24
Finished Jul 05 05:05:58 PM PDT 24
Peak memory 191348 kb
Host smart-12a0a89e-8ccb-4de1-b418-77d068fe6022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479436012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1479436012
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1677081584
Short name T439
Test name
Test status
Simulation time 36868847688 ps
CPU time 1351.04 seconds
Started Jul 05 05:04:41 PM PDT 24
Finished Jul 05 05:27:12 PM PDT 24
Peak memory 183008 kb
Host smart-5ad652a0-04f4-4fc6-8ae9-fa28797f489b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677081584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1677081584
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1611156297
Short name T407
Test name
Test status
Simulation time 127545966638 ps
CPU time 193.08 seconds
Started Jul 05 05:04:41 PM PDT 24
Finished Jul 05 05:07:55 PM PDT 24
Peak memory 191232 kb
Host smart-f33bf418-cc2b-404a-b3b1-445d7ac0686e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611156297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1611156297
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.347145567
Short name T121
Test name
Test status
Simulation time 974327783886 ps
CPU time 475.23 seconds
Started Jul 05 05:04:49 PM PDT 24
Finished Jul 05 05:12:45 PM PDT 24
Peak memory 183068 kb
Host smart-f83573bc-5c80-4337-a193-ae4cb824c802
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347145567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.347145567
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.378849564
Short name T21
Test name
Test status
Simulation time 124664059335 ps
CPU time 103.63 seconds
Started Jul 05 05:04:48 PM PDT 24
Finished Jul 05 05:06:32 PM PDT 24
Peak memory 183024 kb
Host smart-1269c9d0-2999-4f29-ab52-267962ee6000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378849564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.378849564
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3208593004
Short name T212
Test name
Test status
Simulation time 151309115404 ps
CPU time 122.39 seconds
Started Jul 05 05:04:40 PM PDT 24
Finished Jul 05 05:06:43 PM PDT 24
Peak memory 191304 kb
Host smart-e4130478-98ff-40d4-a5a2-e75dda1a5546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208593004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3208593004
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1686864680
Short name T335
Test name
Test status
Simulation time 192934350475 ps
CPU time 1227.42 seconds
Started Jul 05 05:04:49 PM PDT 24
Finished Jul 05 05:25:17 PM PDT 24
Peak memory 191336 kb
Host smart-18b51fc7-d920-4bd4-88bf-d9676f1e5f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686864680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1686864680
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1933474732
Short name T61
Test name
Test status
Simulation time 108507812222 ps
CPU time 160.57 seconds
Started Jul 05 05:04:47 PM PDT 24
Finished Jul 05 05:07:29 PM PDT 24
Peak memory 194432 kb
Host smart-073dc76b-84f3-4954-93ad-162d2bf30a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933474732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1933474732
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1434861295
Short name T130
Test name
Test status
Simulation time 336596530713 ps
CPU time 177.19 seconds
Started Jul 05 05:04:56 PM PDT 24
Finished Jul 05 05:07:54 PM PDT 24
Peak memory 183136 kb
Host smart-41efaf9c-a91b-4419-8243-c404b55c1271
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434861295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1434861295
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2541836784
Short name T393
Test name
Test status
Simulation time 143557471217 ps
CPU time 199.01 seconds
Started Jul 05 05:04:48 PM PDT 24
Finished Jul 05 05:08:08 PM PDT 24
Peak memory 183036 kb
Host smart-cab01ebb-d23c-4fa2-9157-d4c08d2be00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541836784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2541836784
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3991760491
Short name T111
Test name
Test status
Simulation time 1773218993189 ps
CPU time 583.51 seconds
Started Jul 05 05:04:47 PM PDT 24
Finished Jul 05 05:14:31 PM PDT 24
Peak memory 191340 kb
Host smart-32de5deb-a66a-49ff-80ee-866445339523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991760491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3991760491
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2447254574
Short name T364
Test name
Test status
Simulation time 37113964874 ps
CPU time 54.27 seconds
Started Jul 05 05:04:57 PM PDT 24
Finished Jul 05 05:05:52 PM PDT 24
Peak memory 191360 kb
Host smart-1f2788c1-51ee-42a4-8506-52e698f05e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447254574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2447254574
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1398833140
Short name T211
Test name
Test status
Simulation time 50922033397 ps
CPU time 47.68 seconds
Started Jul 05 05:04:57 PM PDT 24
Finished Jul 05 05:05:46 PM PDT 24
Peak memory 183120 kb
Host smart-14606144-a547-4d33-abaa-dab59795085f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398833140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1398833140
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.782092048
Short name T79
Test name
Test status
Simulation time 316385674045 ps
CPU time 70.32 seconds
Started Jul 05 05:04:56 PM PDT 24
Finished Jul 05 05:06:07 PM PDT 24
Peak memory 183076 kb
Host smart-b8bd7746-5ae9-4cb9-85f1-3a67f5b06f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782092048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.782092048
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.331709282
Short name T223
Test name
Test status
Simulation time 542144221471 ps
CPU time 550.28 seconds
Started Jul 05 05:04:56 PM PDT 24
Finished Jul 05 05:14:08 PM PDT 24
Peak memory 191292 kb
Host smart-f95dc15c-5e8d-46ca-a240-1de4529e353b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331709282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.331709282
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3669646523
Short name T149
Test name
Test status
Simulation time 66163857485 ps
CPU time 259.52 seconds
Started Jul 05 05:04:55 PM PDT 24
Finished Jul 05 05:09:15 PM PDT 24
Peak memory 193420 kb
Host smart-72d868dd-44df-4514-8466-932560693d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669646523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3669646523
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1976416524
Short name T36
Test name
Test status
Simulation time 141096417514 ps
CPU time 209.73 seconds
Started Jul 05 05:04:55 PM PDT 24
Finished Jul 05 05:08:26 PM PDT 24
Peak memory 208272 kb
Host smart-ca97e33d-9b71-4db4-9640-2427a5b7e174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976416524 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1976416524
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2533932955
Short name T261
Test name
Test status
Simulation time 2635014742749 ps
CPU time 1059.89 seconds
Started Jul 05 05:05:02 PM PDT 24
Finished Jul 05 05:22:43 PM PDT 24
Peak memory 183072 kb
Host smart-d118f8f7-3eeb-476d-be96-0674e8fcaf6a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533932955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2533932955
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1505974776
Short name T421
Test name
Test status
Simulation time 316484353155 ps
CPU time 91.48 seconds
Started Jul 05 05:05:03 PM PDT 24
Finished Jul 05 05:06:35 PM PDT 24
Peak memory 183144 kb
Host smart-234f45ee-c9f3-4cd5-a673-7c9e6f2ef1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505974776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1505974776
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3651629482
Short name T241
Test name
Test status
Simulation time 55691173065 ps
CPU time 138.62 seconds
Started Jul 05 05:05:02 PM PDT 24
Finished Jul 05 05:07:22 PM PDT 24
Peak memory 191308 kb
Host smart-e8a344f2-78de-4b2e-a449-ba12a9fad8c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651629482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3651629482
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3542075421
Short name T104
Test name
Test status
Simulation time 175502671781 ps
CPU time 924.17 seconds
Started Jul 05 05:05:02 PM PDT 24
Finished Jul 05 05:20:26 PM PDT 24
Peak memory 192912 kb
Host smart-1b91b3d8-ca74-417a-a398-5178c2ddb403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542075421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3542075421
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2266731172
Short name T150
Test name
Test status
Simulation time 349686373285 ps
CPU time 527.3 seconds
Started Jul 05 05:05:03 PM PDT 24
Finished Jul 05 05:13:52 PM PDT 24
Peak memory 191072 kb
Host smart-2d60a860-5d76-4a3d-9460-704cb53ff040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266731172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2266731172
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1045411284
Short name T112
Test name
Test status
Simulation time 280036507245 ps
CPU time 441.63 seconds
Started Jul 05 05:05:02 PM PDT 24
Finished Jul 05 05:12:25 PM PDT 24
Peak memory 183080 kb
Host smart-a0fafe2e-183f-4e34-aa3b-1434b9513d93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045411284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1045411284
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2491929479
Short name T390
Test name
Test status
Simulation time 387388568176 ps
CPU time 163.59 seconds
Started Jul 05 05:05:06 PM PDT 24
Finished Jul 05 05:07:50 PM PDT 24
Peak memory 183128 kb
Host smart-5c073e68-8d72-4694-81ab-95d00312e82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491929479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2491929479
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2548404117
Short name T301
Test name
Test status
Simulation time 25819808519 ps
CPU time 39.2 seconds
Started Jul 05 05:05:03 PM PDT 24
Finished Jul 05 05:05:44 PM PDT 24
Peak memory 182940 kb
Host smart-278dbbc3-d9be-4885-b11b-97f8ee3b954f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548404117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2548404117
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4153414516
Short name T1
Test name
Test status
Simulation time 42627296617 ps
CPU time 76.55 seconds
Started Jul 05 05:05:15 PM PDT 24
Finished Jul 05 05:06:33 PM PDT 24
Peak memory 191340 kb
Host smart-963532c1-22fe-4df6-8e9a-fe4c182c8d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153414516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4153414516
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.769030348
Short name T384
Test name
Test status
Simulation time 116222116716 ps
CPU time 38.71 seconds
Started Jul 05 05:05:15 PM PDT 24
Finished Jul 05 05:05:55 PM PDT 24
Peak memory 183140 kb
Host smart-970c4a8a-bd23-4be4-b907-419e67a32034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769030348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.769030348
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2905074372
Short name T186
Test name
Test status
Simulation time 108484129342 ps
CPU time 474.09 seconds
Started Jul 05 05:05:10 PM PDT 24
Finished Jul 05 05:13:05 PM PDT 24
Peak memory 191292 kb
Host smart-7c20bff4-daeb-4c5b-ad02-36e2e92824cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905074372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2905074372
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3874204547
Short name T405
Test name
Test status
Simulation time 16512084294 ps
CPU time 26.87 seconds
Started Jul 05 05:05:08 PM PDT 24
Finished Jul 05 05:05:35 PM PDT 24
Peak memory 183136 kb
Host smart-4871c40a-66e7-4010-952f-bf5eb46526be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874204547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3874204547
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.1141896673
Short name T60
Test name
Test status
Simulation time 359319164593 ps
CPU time 470.2 seconds
Started Jul 05 05:05:07 PM PDT 24
Finished Jul 05 05:12:57 PM PDT 24
Peak memory 191236 kb
Host smart-b175959f-92a6-441e-9664-2090cf67af22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141896673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.1141896673
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3850396935
Short name T415
Test name
Test status
Simulation time 116837751321 ps
CPU time 160.64 seconds
Started Jul 05 05:05:09 PM PDT 24
Finished Jul 05 05:07:50 PM PDT 24
Peak memory 183140 kb
Host smart-78e87aba-e729-407a-865f-28789c8de9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850396935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3850396935
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3076514952
Short name T272
Test name
Test status
Simulation time 404246027014 ps
CPU time 937.39 seconds
Started Jul 05 05:05:09 PM PDT 24
Finished Jul 05 05:20:48 PM PDT 24
Peak memory 191316 kb
Host smart-b985e036-82c7-412d-888a-5f5489e1d887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076514952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3076514952
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1693712694
Short name T417
Test name
Test status
Simulation time 42545191963 ps
CPU time 70.38 seconds
Started Jul 05 05:05:17 PM PDT 24
Finished Jul 05 05:06:27 PM PDT 24
Peak memory 183160 kb
Host smart-01640bb8-1a0e-40e1-a53a-8a1df32b220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693712694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1693712694
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.937807664
Short name T343
Test name
Test status
Simulation time 470838237040 ps
CPU time 906.05 seconds
Started Jul 05 05:05:16 PM PDT 24
Finished Jul 05 05:20:22 PM PDT 24
Peak memory 210752 kb
Host smart-e283ef81-da1a-4b91-8808-1d08dc492687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937807664 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.937807664
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2013933244
Short name T340
Test name
Test status
Simulation time 1164739151988 ps
CPU time 500.52 seconds
Started Jul 05 05:05:25 PM PDT 24
Finished Jul 05 05:13:46 PM PDT 24
Peak memory 183096 kb
Host smart-a3af43b9-719a-4c61-8a29-a6d826355914
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013933244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2013933244
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.43238684
Short name T436
Test name
Test status
Simulation time 462772685693 ps
CPU time 174.65 seconds
Started Jul 05 05:05:17 PM PDT 24
Finished Jul 05 05:08:11 PM PDT 24
Peak memory 183008 kb
Host smart-e4183497-8d5e-4b71-a872-e08b50a2497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43238684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.43238684
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2465822701
Short name T193
Test name
Test status
Simulation time 577588593913 ps
CPU time 683.37 seconds
Started Jul 05 05:05:16 PM PDT 24
Finished Jul 05 05:16:40 PM PDT 24
Peak memory 193624 kb
Host smart-fd52c17b-5cef-4b44-ba90-be0c35d3aa60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465822701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2465822701
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.523374373
Short name T136
Test name
Test status
Simulation time 278069111020 ps
CPU time 158.11 seconds
Started Jul 05 05:05:21 PM PDT 24
Finished Jul 05 05:08:00 PM PDT 24
Peak memory 191312 kb
Host smart-964f5039-ec23-47ed-8a3e-f1f7ee142d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523374373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.523374373
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1104095778
Short name T107
Test name
Test status
Simulation time 495403573864 ps
CPU time 199.72 seconds
Started Jul 05 05:05:32 PM PDT 24
Finished Jul 05 05:08:53 PM PDT 24
Peak memory 194556 kb
Host smart-3fb0ab09-e418-428c-be04-c1962f11e16b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104095778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1104095778
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.4264818727
Short name T20
Test name
Test status
Simulation time 343314115502 ps
CPU time 298.19 seconds
Started Jul 05 05:05:22 PM PDT 24
Finished Jul 05 05:10:21 PM PDT 24
Peak memory 182984 kb
Host smart-d3dcb0b9-8a56-4e3f-956b-a02772145f8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264818727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.4264818727
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1232428413
Short name T380
Test name
Test status
Simulation time 317982204039 ps
CPU time 110.83 seconds
Started Jul 05 05:05:23 PM PDT 24
Finished Jul 05 05:07:14 PM PDT 24
Peak memory 183144 kb
Host smart-06744507-93c0-436f-a156-eb2e7e675968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232428413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1232428413
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.100737155
Short name T360
Test name
Test status
Simulation time 313535915852 ps
CPU time 2466.92 seconds
Started Jul 05 05:05:26 PM PDT 24
Finished Jul 05 05:46:33 PM PDT 24
Peak memory 191316 kb
Host smart-95b2583b-eb79-4fd2-9b01-b2e439d0185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100737155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.100737155
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3103362280
Short name T220
Test name
Test status
Simulation time 25600209358 ps
CPU time 13.98 seconds
Started Jul 05 05:02:09 PM PDT 24
Finished Jul 05 05:02:24 PM PDT 24
Peak memory 183104 kb
Host smart-2eba4f91-ad4c-4bb8-8c1c-f004d4ab4f9d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103362280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3103362280
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.718474238
Short name T399
Test name
Test status
Simulation time 365071396496 ps
CPU time 163.47 seconds
Started Jul 05 05:02:09 PM PDT 24
Finished Jul 05 05:04:53 PM PDT 24
Peak memory 183140 kb
Host smart-2052c39a-cc20-42cb-bb07-1ce6d5e52ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718474238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.718474238
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2138049123
Short name T207
Test name
Test status
Simulation time 94355038486 ps
CPU time 532.78 seconds
Started Jul 05 05:02:11 PM PDT 24
Finished Jul 05 05:11:05 PM PDT 24
Peak memory 191304 kb
Host smart-5b29c212-0e6a-4058-8e8a-c8dd23a12fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138049123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2138049123
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.986711894
Short name T14
Test name
Test status
Simulation time 59126452 ps
CPU time 0.83 seconds
Started Jul 05 05:02:08 PM PDT 24
Finished Jul 05 05:02:09 PM PDT 24
Peak memory 213364 kb
Host smart-86300782-4cb4-4b6f-aa2a-8de6c0ed3520
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986711894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.986711894
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2124685534
Short name T216
Test name
Test status
Simulation time 1582073664934 ps
CPU time 730.62 seconds
Started Jul 05 05:02:09 PM PDT 24
Finished Jul 05 05:14:20 PM PDT 24
Peak memory 191296 kb
Host smart-3eda2398-4030-4611-90f0-562bfae75b56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124685534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2124685534
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.2254975824
Short name T39
Test name
Test status
Simulation time 85214581210 ps
CPU time 154.56 seconds
Started Jul 05 05:02:10 PM PDT 24
Finished Jul 05 05:04:45 PM PDT 24
Peak memory 205940 kb
Host smart-78da1d55-bf48-4eb3-9229-cb6cbf579062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254975824 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.2254975824
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.4224637638
Short name T382
Test name
Test status
Simulation time 240836533244 ps
CPU time 82.28 seconds
Started Jul 05 05:05:29 PM PDT 24
Finished Jul 05 05:06:52 PM PDT 24
Peak memory 183056 kb
Host smart-857ae554-88ad-49d0-a2d2-7fcebb8681be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224637638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.4224637638
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1858259670
Short name T70
Test name
Test status
Simulation time 118735874 ps
CPU time 1.44 seconds
Started Jul 05 05:05:31 PM PDT 24
Finished Jul 05 05:05:33 PM PDT 24
Peak memory 191252 kb
Host smart-9d4d4f60-000f-4273-a5ae-98ca764422ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858259670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1858259670
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1709898018
Short name T274
Test name
Test status
Simulation time 89312193639 ps
CPU time 144.53 seconds
Started Jul 05 05:05:36 PM PDT 24
Finished Jul 05 05:08:01 PM PDT 24
Peak memory 183084 kb
Host smart-b1902426-faf2-4492-b474-e7be1d982638
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709898018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1709898018
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.775795469
Short name T387
Test name
Test status
Simulation time 152860105830 ps
CPU time 188.47 seconds
Started Jul 05 05:05:27 PM PDT 24
Finished Jul 05 05:08:37 PM PDT 24
Peak memory 183036 kb
Host smart-c0f821de-55c8-4cbc-b341-ea6a87b2b358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775795469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.775795469
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3602122860
Short name T366
Test name
Test status
Simulation time 678713317 ps
CPU time 2.76 seconds
Started Jul 05 05:05:36 PM PDT 24
Finished Jul 05 05:05:40 PM PDT 24
Peak memory 182980 kb
Host smart-4bab339c-3eaa-4545-9847-627b9cc42892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602122860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3602122860
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.643635516
Short name T278
Test name
Test status
Simulation time 1614909410398 ps
CPU time 1378.25 seconds
Started Jul 05 05:05:35 PM PDT 24
Finished Jul 05 05:28:34 PM PDT 24
Peak memory 191292 kb
Host smart-7cf43f18-2f1e-4c2e-aa83-96358798b6fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643635516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
643635516
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3721772752
Short name T316
Test name
Test status
Simulation time 39568447524 ps
CPU time 37.64 seconds
Started Jul 05 05:05:44 PM PDT 24
Finished Jul 05 05:06:22 PM PDT 24
Peak memory 183124 kb
Host smart-97e62ac4-2818-4d91-b27a-587a5e21b175
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721772752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3721772752
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1638261226
Short name T369
Test name
Test status
Simulation time 629676220405 ps
CPU time 249.31 seconds
Started Jul 05 05:05:43 PM PDT 24
Finished Jul 05 05:09:53 PM PDT 24
Peak memory 183132 kb
Host smart-7a1699aa-d3b0-45be-ba2a-822601c684eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638261226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1638261226
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1806557791
Short name T43
Test name
Test status
Simulation time 239619767716 ps
CPU time 407.13 seconds
Started Jul 05 05:05:52 PM PDT 24
Finished Jul 05 05:12:40 PM PDT 24
Peak memory 183124 kb
Host smart-5a736da9-8661-4c5f-8106-06d582e44d46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806557791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1806557791
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2872287243
Short name T427
Test name
Test status
Simulation time 694271489016 ps
CPU time 247.14 seconds
Started Jul 05 05:05:49 PM PDT 24
Finished Jul 05 05:09:57 PM PDT 24
Peak memory 183128 kb
Host smart-3e27e3b5-c1fd-4078-9676-85866ad47dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872287243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2872287243
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2142277436
Short name T341
Test name
Test status
Simulation time 440638499893 ps
CPU time 259.36 seconds
Started Jul 05 05:05:49 PM PDT 24
Finished Jul 05 05:10:09 PM PDT 24
Peak memory 191292 kb
Host smart-2ee0b29d-2698-4583-9c35-a2da9d3663df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142277436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2142277436
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3056653450
Short name T444
Test name
Test status
Simulation time 37715626021 ps
CPU time 325.87 seconds
Started Jul 05 05:05:52 PM PDT 24
Finished Jul 05 05:11:19 PM PDT 24
Peak memory 183148 kb
Host smart-77d07f49-e9b5-4932-a012-9d6ec433f035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056653450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3056653450
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1370052316
Short name T65
Test name
Test status
Simulation time 368395711863 ps
CPU time 616.96 seconds
Started Jul 05 05:05:49 PM PDT 24
Finished Jul 05 05:16:06 PM PDT 24
Peak memory 191340 kb
Host smart-43b739ee-9625-4bdf-b5cf-f3e79c5bffb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370052316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1370052316
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.1694178079
Short name T40
Test name
Test status
Simulation time 30179311905 ps
CPU time 307.34 seconds
Started Jul 05 05:05:50 PM PDT 24
Finished Jul 05 05:10:58 PM PDT 24
Peak memory 207132 kb
Host smart-1d09f727-3660-479d-88c0-5554eeccee9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694178079 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.1694178079
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3414131656
Short name T41
Test name
Test status
Simulation time 254377507646 ps
CPU time 424.02 seconds
Started Jul 05 05:05:57 PM PDT 24
Finished Jul 05 05:13:01 PM PDT 24
Peak memory 183120 kb
Host smart-def193a6-c193-4820-a91b-48253f3c6797
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414131656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3414131656
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.257160230
Short name T408
Test name
Test status
Simulation time 142156228128 ps
CPU time 186.77 seconds
Started Jul 05 05:05:56 PM PDT 24
Finished Jul 05 05:09:04 PM PDT 24
Peak memory 183128 kb
Host smart-ea1b7e29-bf14-4708-af31-215d2130c2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257160230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.257160230
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1537868255
Short name T45
Test name
Test status
Simulation time 78460496295 ps
CPU time 15.05 seconds
Started Jul 05 05:05:56 PM PDT 24
Finished Jul 05 05:06:11 PM PDT 24
Peak memory 191224 kb
Host smart-1216d8c0-da5b-47ac-8c9f-9d978c044cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537868255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1537868255
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.447054540
Short name T438
Test name
Test status
Simulation time 298100004004 ps
CPU time 517.91 seconds
Started Jul 05 05:06:10 PM PDT 24
Finished Jul 05 05:14:48 PM PDT 24
Peak memory 183068 kb
Host smart-12e1d699-6796-44a0-bde6-7ee39665b14f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447054540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.447054540
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2196283461
Short name T423
Test name
Test status
Simulation time 294658786381 ps
CPU time 231.94 seconds
Started Jul 05 05:06:04 PM PDT 24
Finished Jul 05 05:09:56 PM PDT 24
Peak memory 183120 kb
Host smart-2e1e033f-3dbc-4424-b654-1236665634d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196283461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2196283461
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3430952507
Short name T353
Test name
Test status
Simulation time 368438964225 ps
CPU time 192.25 seconds
Started Jul 05 05:06:03 PM PDT 24
Finished Jul 05 05:09:16 PM PDT 24
Peak memory 191220 kb
Host smart-2fcb6710-8c7d-44f8-87a2-d4d100c1334e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430952507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3430952507
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3201697492
Short name T431
Test name
Test status
Simulation time 175804553 ps
CPU time 0.69 seconds
Started Jul 05 05:06:10 PM PDT 24
Finished Jul 05 05:06:11 PM PDT 24
Peak memory 191648 kb
Host smart-9e9f3da1-d98a-4ac9-aa42-efb280038172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201697492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3201697492
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3902593095
Short name T433
Test name
Test status
Simulation time 42257653253 ps
CPU time 64.49 seconds
Started Jul 05 05:06:12 PM PDT 24
Finished Jul 05 05:07:17 PM PDT 24
Peak memory 183096 kb
Host smart-f71a3ec4-7bab-46b9-94fa-eeaa514c1dc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902593095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3902593095
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.3415549771
Short name T169
Test name
Test status
Simulation time 11587898647 ps
CPU time 14.79 seconds
Started Jul 05 05:06:10 PM PDT 24
Finished Jul 05 05:06:25 PM PDT 24
Peak memory 183084 kb
Host smart-a8209c94-b561-45ba-a4be-dcb8760c6205
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415549771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.3415549771
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.4079569278
Short name T426
Test name
Test status
Simulation time 183538348100 ps
CPU time 140.84 seconds
Started Jul 05 05:06:11 PM PDT 24
Finished Jul 05 05:08:32 PM PDT 24
Peak memory 183120 kb
Host smart-df942c26-4fd1-4d08-a009-3081552a8c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079569278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.4079569278
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1049695070
Short name T363
Test name
Test status
Simulation time 32592098674 ps
CPU time 48.17 seconds
Started Jul 05 05:06:10 PM PDT 24
Finished Jul 05 05:06:59 PM PDT 24
Peak memory 183148 kb
Host smart-6bd67e61-1612-4c38-9d18-f694eed1f4d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049695070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1049695070
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2206216972
Short name T350
Test name
Test status
Simulation time 88326288098 ps
CPU time 344.83 seconds
Started Jul 05 05:06:17 PM PDT 24
Finished Jul 05 05:12:02 PM PDT 24
Peak memory 191328 kb
Host smart-d3450f29-e67b-4ad3-95f4-e2c3fd601b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206216972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2206216972
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all_with_rand_reset.4011093822
Short name T37
Test name
Test status
Simulation time 19666070342 ps
CPU time 223.42 seconds
Started Jul 05 05:06:11 PM PDT 24
Finished Jul 05 05:09:55 PM PDT 24
Peak memory 206072 kb
Host smart-070773ce-11ab-4730-bdeb-2f1f59ca93bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011093822 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all_with_rand_reset.4011093822
Directory /workspace/46.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3962595714
Short name T453
Test name
Test status
Simulation time 22719649914 ps
CPU time 8.27 seconds
Started Jul 05 05:06:15 PM PDT 24
Finished Jul 05 05:06:24 PM PDT 24
Peak memory 183020 kb
Host smart-53a7f333-a8e2-48b4-8935-cf80f4ddcab8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962595714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3962595714
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.4163326806
Short name T378
Test name
Test status
Simulation time 374588213389 ps
CPU time 280.35 seconds
Started Jul 05 05:06:21 PM PDT 24
Finished Jul 05 05:11:02 PM PDT 24
Peak memory 183140 kb
Host smart-d22cec8f-3660-478a-b602-087b604b0173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163326806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.4163326806
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.547092435
Short name T202
Test name
Test status
Simulation time 8354211883 ps
CPU time 13.97 seconds
Started Jul 05 05:06:21 PM PDT 24
Finished Jul 05 05:06:35 PM PDT 24
Peak memory 183148 kb
Host smart-899563ec-93b6-43ff-abaa-05c668bc1119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547092435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.547092435
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3860853125
Short name T396
Test name
Test status
Simulation time 965049596 ps
CPU time 1.01 seconds
Started Jul 05 05:06:21 PM PDT 24
Finished Jul 05 05:06:22 PM PDT 24
Peak memory 192784 kb
Host smart-681fb215-52a1-4fad-a33a-083966c61eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860853125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3860853125
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3949684146
Short name T377
Test name
Test status
Simulation time 84891167026 ps
CPU time 34.28 seconds
Started Jul 05 05:06:17 PM PDT 24
Finished Jul 05 05:06:51 PM PDT 24
Peak memory 183136 kb
Host smart-6e0ca1ca-73d6-451d-88a1-e0d77c8a7120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949684146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3949684146
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3067496297
Short name T144
Test name
Test status
Simulation time 35122576041 ps
CPU time 63.58 seconds
Started Jul 05 05:06:21 PM PDT 24
Finished Jul 05 05:07:25 PM PDT 24
Peak memory 194112 kb
Host smart-1ccd74d1-02ae-4fba-a20b-7b2a127996d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067496297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3067496297
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.930067403
Short name T456
Test name
Test status
Simulation time 28356487392 ps
CPU time 14.26 seconds
Started Jul 05 05:06:16 PM PDT 24
Finished Jul 05 05:06:31 PM PDT 24
Peak memory 183024 kb
Host smart-3d2fb1cd-1fd3-4ca2-a0e8-ea04ce81d71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930067403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.930067403
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2103362921
Short name T398
Test name
Test status
Simulation time 162856225445 ps
CPU time 246.49 seconds
Started Jul 05 05:06:23 PM PDT 24
Finished Jul 05 05:10:30 PM PDT 24
Peak memory 191240 kb
Host smart-f4a4ac62-a5a7-4275-a859-969bef578a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103362921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2103362921
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3337026763
Short name T324
Test name
Test status
Simulation time 235288078397 ps
CPU time 407.11 seconds
Started Jul 05 05:06:24 PM PDT 24
Finished Jul 05 05:13:12 PM PDT 24
Peak memory 183104 kb
Host smart-747dfdd2-0cdc-4658-b8b9-9002a24c6d95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337026763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3337026763
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.4208495507
Short name T374
Test name
Test status
Simulation time 445528857941 ps
CPU time 191.25 seconds
Started Jul 05 05:06:22 PM PDT 24
Finished Jul 05 05:09:34 PM PDT 24
Peak memory 183136 kb
Host smart-8a43c4eb-f90f-438c-ba7b-799654d53815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208495507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.4208495507
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2276922487
Short name T332
Test name
Test status
Simulation time 34123500492 ps
CPU time 53.34 seconds
Started Jul 05 05:06:27 PM PDT 24
Finished Jul 05 05:07:20 PM PDT 24
Peak memory 183148 kb
Host smart-411e01d0-d082-4277-851a-703ddb7bf592
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276922487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2276922487
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1947252114
Short name T258
Test name
Test status
Simulation time 33708712646 ps
CPU time 47.5 seconds
Started Jul 05 05:06:24 PM PDT 24
Finished Jul 05 05:07:12 PM PDT 24
Peak memory 183120 kb
Host smart-0f3c0293-9e47-4cd1-96c0-02e6df9b3eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947252114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1947252114
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3629614349
Short name T271
Test name
Test status
Simulation time 199143616120 ps
CPU time 275.22 seconds
Started Jul 05 05:06:31 PM PDT 24
Finished Jul 05 05:11:07 PM PDT 24
Peak memory 183140 kb
Host smart-3225a779-36c5-4f5e-a3d3-29eac4e0032a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629614349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3629614349
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2232503243
Short name T397
Test name
Test status
Simulation time 137720607192 ps
CPU time 137.05 seconds
Started Jul 05 05:02:11 PM PDT 24
Finished Jul 05 05:04:28 PM PDT 24
Peak memory 183136 kb
Host smart-980f6d90-e4f1-4b76-8bb1-72d40ce941b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232503243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2232503243
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.825489653
Short name T418
Test name
Test status
Simulation time 88139243787 ps
CPU time 66.01 seconds
Started Jul 05 05:02:10 PM PDT 24
Finished Jul 05 05:03:17 PM PDT 24
Peak memory 183140 kb
Host smart-ed1a64bc-191b-45d9-bd80-cbf38868e41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825489653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.825489653
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3424085638
Short name T280
Test name
Test status
Simulation time 100251507295 ps
CPU time 58.05 seconds
Started Jul 05 05:02:10 PM PDT 24
Finished Jul 05 05:03:09 PM PDT 24
Peak memory 183040 kb
Host smart-41038c8c-8369-4c73-8144-9b7b6bf80863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424085638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3424085638
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.906233091
Short name T161
Test name
Test status
Simulation time 53779177752 ps
CPU time 187.34 seconds
Started Jul 05 05:02:11 PM PDT 24
Finished Jul 05 05:05:19 PM PDT 24
Peak memory 191336 kb
Host smart-f06cf685-8a10-430a-ba5d-d7c55f17ce83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906233091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.906233091
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2624193454
Short name T277
Test name
Test status
Simulation time 215154019420 ps
CPU time 425.98 seconds
Started Jul 05 05:02:13 PM PDT 24
Finished Jul 05 05:09:19 PM PDT 24
Peak memory 191336 kb
Host smart-0378d6a0-1496-49e5-a674-314f13dd4a16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624193454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2624193454
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.379483984
Short name T139
Test name
Test status
Simulation time 58866471801 ps
CPU time 92.49 seconds
Started Jul 05 05:06:30 PM PDT 24
Finished Jul 05 05:08:02 PM PDT 24
Peak memory 191204 kb
Host smart-9d6827e3-115d-4235-84e4-f601fbc4a5f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379483984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.379483984
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2397352678
Short name T342
Test name
Test status
Simulation time 93372123865 ps
CPU time 73.41 seconds
Started Jul 05 05:06:29 PM PDT 24
Finished Jul 05 05:07:43 PM PDT 24
Peak memory 183044 kb
Host smart-9d6d5778-592f-4315-a26e-eb1498f1b680
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397352678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2397352678
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2673963550
Short name T185
Test name
Test status
Simulation time 143711319089 ps
CPU time 248.43 seconds
Started Jul 05 05:06:30 PM PDT 24
Finished Jul 05 05:10:39 PM PDT 24
Peak memory 191336 kb
Host smart-74cfc325-9e15-40a0-bd33-f94ac500f7eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673963550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2673963550
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.142012712
Short name T199
Test name
Test status
Simulation time 92627330935 ps
CPU time 222.92 seconds
Started Jul 05 05:06:30 PM PDT 24
Finished Jul 05 05:10:13 PM PDT 24
Peak memory 191248 kb
Host smart-7e973062-b42c-4aa8-9c01-3e9fbba77062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142012712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.142012712
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.643382619
Short name T266
Test name
Test status
Simulation time 458214934409 ps
CPU time 963.85 seconds
Started Jul 05 05:06:36 PM PDT 24
Finished Jul 05 05:22:40 PM PDT 24
Peak memory 191344 kb
Host smart-24d5b722-59a9-4a38-8dad-c59357d70a1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643382619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.643382619
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.4117828634
Short name T119
Test name
Test status
Simulation time 488863260421 ps
CPU time 856.62 seconds
Started Jul 05 05:06:39 PM PDT 24
Finished Jul 05 05:20:56 PM PDT 24
Peak memory 191344 kb
Host smart-174cc9fa-7131-4d4e-9ec6-2392340abf85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117828634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.4117828634
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.5895154
Short name T3
Test name
Test status
Simulation time 113591178509 ps
CPU time 154.46 seconds
Started Jul 05 05:02:11 PM PDT 24
Finished Jul 05 05:04:46 PM PDT 24
Peak memory 183036 kb
Host smart-c26ee0c6-99a7-438b-b9b9-c68eaa47f69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5895154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.5895154
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3095473373
Short name T395
Test name
Test status
Simulation time 82228283993 ps
CPU time 77.88 seconds
Started Jul 05 05:02:19 PM PDT 24
Finished Jul 05 05:03:37 PM PDT 24
Peak memory 183144 kb
Host smart-cb3d0123-3449-4b44-aaaf-c42bd815f35d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095473373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3095473373
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1861444389
Short name T409
Test name
Test status
Simulation time 23785443954 ps
CPU time 10.96 seconds
Started Jul 05 05:02:15 PM PDT 24
Finished Jul 05 05:02:27 PM PDT 24
Peak memory 183124 kb
Host smart-d2a08a94-b2a7-4a2b-8a83-8feccf2266bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861444389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1861444389
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.845304091
Short name T434
Test name
Test status
Simulation time 245732742130 ps
CPU time 318.51 seconds
Started Jul 05 05:02:20 PM PDT 24
Finished Jul 05 05:07:39 PM PDT 24
Peak memory 191292 kb
Host smart-87ecb750-1cbc-4207-b8f7-273c7a4803e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845304091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.845304091
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.1067044344
Short name T73
Test name
Test status
Simulation time 207355269789 ps
CPU time 608.25 seconds
Started Jul 05 05:02:16 PM PDT 24
Finished Jul 05 05:12:24 PM PDT 24
Peak memory 211380 kb
Host smart-9a1ca3e4-9294-4ccc-9a4c-348fefd891f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067044344 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.1067044344
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.2267522603
Short name T160
Test name
Test status
Simulation time 71631641680 ps
CPU time 64.15 seconds
Started Jul 05 05:06:37 PM PDT 24
Finished Jul 05 05:07:42 PM PDT 24
Peak memory 183144 kb
Host smart-22889614-bb8a-40af-95f3-1192ef900d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267522603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2267522603
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.50156801
Short name T305
Test name
Test status
Simulation time 1733938158 ps
CPU time 0.87 seconds
Started Jul 05 05:06:36 PM PDT 24
Finished Jul 05 05:06:37 PM PDT 24
Peak memory 182984 kb
Host smart-0792378c-4837-4318-a239-e0cdfa650b15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50156801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.50156801
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2027209843
Short name T454
Test name
Test status
Simulation time 198319344500 ps
CPU time 206.53 seconds
Started Jul 05 05:06:36 PM PDT 24
Finished Jul 05 05:10:04 PM PDT 24
Peak memory 191316 kb
Host smart-2cbcda2b-c26e-4a71-bfa8-8b08a708331f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027209843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2027209843
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2860286814
Short name T259
Test name
Test status
Simulation time 82810962606 ps
CPU time 127.87 seconds
Started Jul 05 05:06:38 PM PDT 24
Finished Jul 05 05:08:46 PM PDT 24
Peak memory 191344 kb
Host smart-7a3e6465-4cdf-4709-b89f-72acc6b2756a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860286814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2860286814
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1208845014
Short name T267
Test name
Test status
Simulation time 1027117010067 ps
CPU time 257.91 seconds
Started Jul 05 05:06:35 PM PDT 24
Finished Jul 05 05:10:53 PM PDT 24
Peak memory 191348 kb
Host smart-c72adbb0-505d-4395-a2ea-f0b053dfc0b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208845014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1208845014
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.4013959994
Short name T158
Test name
Test status
Simulation time 367894081154 ps
CPU time 596.8 seconds
Started Jul 05 05:06:35 PM PDT 24
Finished Jul 05 05:16:33 PM PDT 24
Peak memory 191608 kb
Host smart-81e972b7-d924-47ae-93f7-52b5afa11925
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013959994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.4013959994
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2145919942
Short name T204
Test name
Test status
Simulation time 133504586348 ps
CPU time 62.8 seconds
Started Jul 05 05:06:38 PM PDT 24
Finished Jul 05 05:07:41 PM PDT 24
Peak memory 183036 kb
Host smart-e5a3d6e1-9c2f-4e8a-badb-ebdd7ff83bad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145919942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2145919942
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2882682459
Short name T143
Test name
Test status
Simulation time 153013821306 ps
CPU time 339.09 seconds
Started Jul 05 05:06:37 PM PDT 24
Finished Jul 05 05:12:17 PM PDT 24
Peak memory 191348 kb
Host smart-4fbfffa8-d565-4b0b-b35e-411cf5f30c71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882682459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2882682459
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2826465260
Short name T189
Test name
Test status
Simulation time 248247453863 ps
CPU time 367.82 seconds
Started Jul 05 05:02:15 PM PDT 24
Finished Jul 05 05:08:23 PM PDT 24
Peak memory 183124 kb
Host smart-083c0f05-3f8a-4a85-b153-5df0d2b0e182
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826465260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2826465260
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1856298328
Short name T389
Test name
Test status
Simulation time 182452363553 ps
CPU time 143.75 seconds
Started Jul 05 05:02:18 PM PDT 24
Finished Jul 05 05:04:42 PM PDT 24
Peak memory 183144 kb
Host smart-7b66368b-f77d-4cd4-80c4-df5af372308e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856298328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1856298328
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3280553028
Short name T354
Test name
Test status
Simulation time 149196835182 ps
CPU time 319.71 seconds
Started Jul 05 05:02:18 PM PDT 24
Finished Jul 05 05:07:38 PM PDT 24
Peak memory 183016 kb
Host smart-5ff67052-1598-4ed3-8dc2-72e05f918b8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280553028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3280553028
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1905108462
Short name T240
Test name
Test status
Simulation time 55238151588 ps
CPU time 137.45 seconds
Started Jul 05 05:02:19 PM PDT 24
Finished Jul 05 05:04:36 PM PDT 24
Peak memory 183084 kb
Host smart-ebc439c5-1a16-4992-b829-a29a97d2ab26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905108462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1905108462
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3135625973
Short name T64
Test name
Test status
Simulation time 603072220182 ps
CPU time 521.08 seconds
Started Jul 05 05:02:20 PM PDT 24
Finished Jul 05 05:11:01 PM PDT 24
Peak memory 191340 kb
Host smart-3bbed2e2-9ac7-405a-9c19-fb9596fb6fe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135625973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3135625973
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.17337612
Short name T307
Test name
Test status
Simulation time 351270206891 ps
CPU time 430.9 seconds
Started Jul 05 05:06:38 PM PDT 24
Finished Jul 05 05:13:49 PM PDT 24
Peak memory 191232 kb
Host smart-5e927b53-522c-4efb-b797-b052831916ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17337612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.17337612
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3102202168
Short name T319
Test name
Test status
Simulation time 48223730447 ps
CPU time 277.27 seconds
Started Jul 05 05:06:35 PM PDT 24
Finished Jul 05 05:11:13 PM PDT 24
Peak memory 183408 kb
Host smart-2fe5460d-710f-4829-80bc-b6fb298a78b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102202168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3102202168
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.892255541
Short name T6
Test name
Test status
Simulation time 21604044982 ps
CPU time 33.38 seconds
Started Jul 05 05:06:43 PM PDT 24
Finished Jul 05 05:07:17 PM PDT 24
Peak memory 183136 kb
Host smart-ee37d2af-88eb-49ef-b461-544273b003b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892255541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.892255541
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3979862300
Short name T148
Test name
Test status
Simulation time 90597306128 ps
CPU time 883.12 seconds
Started Jul 05 05:06:43 PM PDT 24
Finished Jul 05 05:21:27 PM PDT 24
Peak memory 191248 kb
Host smart-fc8bb50f-9a15-46b7-99de-33bd04139c50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979862300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3979862300
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.4286975312
Short name T356
Test name
Test status
Simulation time 101346013308 ps
CPU time 202.66 seconds
Started Jul 05 05:06:46 PM PDT 24
Finished Jul 05 05:10:09 PM PDT 24
Peak memory 191344 kb
Host smart-ed33d46c-483b-4266-8217-c815471198f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286975312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.4286975312
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2375153447
Short name T141
Test name
Test status
Simulation time 1688166810120 ps
CPU time 1739.13 seconds
Started Jul 05 05:06:44 PM PDT 24
Finished Jul 05 05:35:44 PM PDT 24
Peak memory 191324 kb
Host smart-23e9fa23-75e7-4a2b-b756-8aaa7e56053c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375153447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2375153447
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.358435058
Short name T110
Test name
Test status
Simulation time 41334594359 ps
CPU time 58.4 seconds
Started Jul 05 05:06:48 PM PDT 24
Finished Jul 05 05:07:47 PM PDT 24
Peak memory 191260 kb
Host smart-4da068ba-11ce-4676-be4f-61fcffec2d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358435058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.358435058
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1699040568
Short name T58
Test name
Test status
Simulation time 6322496816 ps
CPU time 10.93 seconds
Started Jul 05 05:02:28 PM PDT 24
Finished Jul 05 05:02:39 PM PDT 24
Peak memory 183076 kb
Host smart-d74eb4d2-7b32-4693-969f-1a952c67964f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699040568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1699040568
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2777127207
Short name T381
Test name
Test status
Simulation time 115800293169 ps
CPU time 144.84 seconds
Started Jul 05 05:02:27 PM PDT 24
Finished Jul 05 05:04:53 PM PDT 24
Peak memory 183096 kb
Host smart-a8f95fb8-90b8-41de-aa61-bf493e67862b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777127207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2777127207
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3188932545
Short name T105
Test name
Test status
Simulation time 395029764473 ps
CPU time 522.49 seconds
Started Jul 05 05:02:26 PM PDT 24
Finished Jul 05 05:11:09 PM PDT 24
Peak memory 191340 kb
Host smart-0e26aea6-0c18-4885-89db-0708ec241ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188932545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3188932545
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3289159540
Short name T362
Test name
Test status
Simulation time 181691661198 ps
CPU time 98.21 seconds
Started Jul 05 05:02:27 PM PDT 24
Finished Jul 05 05:04:06 PM PDT 24
Peak memory 183144 kb
Host smart-5be70adb-de80-4893-b750-c30bf0c6025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289159540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3289159540
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1730187723
Short name T25
Test name
Test status
Simulation time 428255195984 ps
CPU time 712.41 seconds
Started Jul 05 05:02:26 PM PDT 24
Finished Jul 05 05:14:19 PM PDT 24
Peak memory 191252 kb
Host smart-1f907f4a-f0cd-4bf2-a935-ec7eac447a8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730187723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1730187723
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.23378566
Short name T209
Test name
Test status
Simulation time 1793756159634 ps
CPU time 1132.16 seconds
Started Jul 05 05:06:50 PM PDT 24
Finished Jul 05 05:25:42 PM PDT 24
Peak memory 191340 kb
Host smart-ab495866-d793-4208-bfa0-339e005a5d6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23378566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.23378566
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2181685751
Short name T430
Test name
Test status
Simulation time 39884546047 ps
CPU time 23.27 seconds
Started Jul 05 05:06:48 PM PDT 24
Finished Jul 05 05:07:12 PM PDT 24
Peak memory 183148 kb
Host smart-e053d008-5bc0-4c39-ba2e-2904fbd4c4a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181685751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2181685751
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2453296381
Short name T322
Test name
Test status
Simulation time 376015138457 ps
CPU time 211.83 seconds
Started Jul 05 05:06:49 PM PDT 24
Finished Jul 05 05:10:21 PM PDT 24
Peak memory 191344 kb
Host smart-4b9adb8f-12cd-4bc1-81a6-5b837272c8e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453296381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2453296381
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.165586604
Short name T77
Test name
Test status
Simulation time 79743848206 ps
CPU time 1449.86 seconds
Started Jul 05 05:06:51 PM PDT 24
Finished Jul 05 05:31:01 PM PDT 24
Peak memory 183128 kb
Host smart-b2df295e-37e6-44f9-9c64-458e9548df5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165586604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.165586604
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2831648545
Short name T331
Test name
Test status
Simulation time 171257955710 ps
CPU time 130.15 seconds
Started Jul 05 05:06:59 PM PDT 24
Finished Jul 05 05:09:10 PM PDT 24
Peak memory 191344 kb
Host smart-718b8f7e-0c68-4e18-8d2c-f03ab3766182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831648545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2831648545
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.727373312
Short name T270
Test name
Test status
Simulation time 118323567130 ps
CPU time 218.88 seconds
Started Jul 05 05:06:58 PM PDT 24
Finished Jul 05 05:10:37 PM PDT 24
Peak memory 191356 kb
Host smart-3063aa67-3292-4edf-8d44-35454aba5085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727373312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.727373312
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.789226767
Short name T425
Test name
Test status
Simulation time 487934358662 ps
CPU time 186.96 seconds
Started Jul 05 05:02:32 PM PDT 24
Finished Jul 05 05:05:40 PM PDT 24
Peak memory 183144 kb
Host smart-94693f1f-1556-4741-b974-5ead6877810e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789226767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.789226767
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2937700653
Short name T357
Test name
Test status
Simulation time 546948387442 ps
CPU time 478.31 seconds
Started Jul 05 05:02:26 PM PDT 24
Finished Jul 05 05:10:25 PM PDT 24
Peak memory 191340 kb
Host smart-3eaa9c8d-c16f-48b9-a5aa-ae2323cdd64a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937700653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2937700653
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3105252096
Short name T383
Test name
Test status
Simulation time 770306572 ps
CPU time 0.78 seconds
Started Jul 05 05:02:35 PM PDT 24
Finished Jul 05 05:02:37 PM PDT 24
Peak memory 191568 kb
Host smart-ffadc23d-5f9e-4de2-972e-4823c20153d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105252096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3105252096
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2964679419
Short name T243
Test name
Test status
Simulation time 459560947886 ps
CPU time 273.36 seconds
Started Jul 05 05:06:57 PM PDT 24
Finished Jul 05 05:11:31 PM PDT 24
Peak memory 191296 kb
Host smart-316c00de-329f-4630-8261-2de48f863169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964679419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2964679419
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.450625587
Short name T253
Test name
Test status
Simulation time 432462068071 ps
CPU time 1402.99 seconds
Started Jul 05 05:06:55 PM PDT 24
Finished Jul 05 05:30:19 PM PDT 24
Peak memory 191256 kb
Host smart-ba7f6e19-71f3-460b-ab3d-f5a5516b209a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450625587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.450625587
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3963204436
Short name T239
Test name
Test status
Simulation time 123106171301 ps
CPU time 215.58 seconds
Started Jul 05 05:07:03 PM PDT 24
Finished Jul 05 05:10:40 PM PDT 24
Peak memory 191340 kb
Host smart-9355efe3-b808-4fb1-aa44-5e8d118c71d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963204436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3963204436
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3360624868
Short name T452
Test name
Test status
Simulation time 25985328914 ps
CPU time 946.9 seconds
Started Jul 05 05:07:04 PM PDT 24
Finished Jul 05 05:22:51 PM PDT 24
Peak memory 183148 kb
Host smart-090a4970-d63a-4cb9-a00d-985b54c29959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360624868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3360624868
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.457560146
Short name T7
Test name
Test status
Simulation time 53074489727 ps
CPU time 1491.76 seconds
Started Jul 05 05:07:06 PM PDT 24
Finished Jul 05 05:31:59 PM PDT 24
Peak memory 191304 kb
Host smart-4d4974e2-03a9-4a59-883b-f5c660da6775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457560146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.457560146
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3422607262
Short name T257
Test name
Test status
Simulation time 76731279840 ps
CPU time 382.69 seconds
Started Jul 05 05:07:02 PM PDT 24
Finished Jul 05 05:13:25 PM PDT 24
Peak memory 191344 kb
Host smart-1f0f474e-3d53-47e2-b138-38f23a584e09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422607262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3422607262
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1351982985
Short name T414
Test name
Test status
Simulation time 264322220898 ps
CPU time 275.42 seconds
Started Jul 05 05:07:02 PM PDT 24
Finished Jul 05 05:11:38 PM PDT 24
Peak memory 192508 kb
Host smart-4bf8aa2c-db5a-45c8-a15a-ac59a12864d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351982985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1351982985
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2421641744
Short name T312
Test name
Test status
Simulation time 111135865609 ps
CPU time 337.47 seconds
Started Jul 05 05:07:06 PM PDT 24
Finished Jul 05 05:12:44 PM PDT 24
Peak memory 191348 kb
Host smart-8c894abc-e893-4393-aad2-a0f1d630ce43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421641744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2421641744
Directory /workspace/99.rv_timer_random/latest
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