Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.55 99.36 98.73 100.00 100.00 100.00 99.21


Total test records in report: 582
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T96 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3162383886 Jul 06 04:57:31 PM PDT 24 Jul 06 04:57:32 PM PDT 24 104639607 ps
T510 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1735401691 Jul 06 04:57:43 PM PDT 24 Jul 06 04:57:44 PM PDT 24 42385725 ps
T511 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3368068102 Jul 06 04:57:33 PM PDT 24 Jul 06 04:57:34 PM PDT 24 11719498 ps
T512 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.353340516 Jul 06 04:57:38 PM PDT 24 Jul 06 04:57:39 PM PDT 24 154952343 ps
T513 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1921097812 Jul 06 04:57:42 PM PDT 24 Jul 06 04:57:44 PM PDT 24 117985253 ps
T514 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2365583512 Jul 06 04:57:31 PM PDT 24 Jul 06 04:57:32 PM PDT 24 31361950 ps
T515 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.555796504 Jul 06 04:57:44 PM PDT 24 Jul 06 04:57:45 PM PDT 24 66531789 ps
T97 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1123299175 Jul 06 04:57:04 PM PDT 24 Jul 06 04:57:05 PM PDT 24 15551911 ps
T516 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4170472824 Jul 06 04:57:41 PM PDT 24 Jul 06 04:57:42 PM PDT 24 148146624 ps
T517 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2819294381 Jul 06 04:57:42 PM PDT 24 Jul 06 04:57:43 PM PDT 24 21466501 ps
T98 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1859062421 Jul 06 04:56:56 PM PDT 24 Jul 06 04:56:57 PM PDT 24 14533591 ps
T92 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3033288500 Jul 06 04:57:06 PM PDT 24 Jul 06 04:57:07 PM PDT 24 280730861 ps
T518 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.132430995 Jul 06 04:57:28 PM PDT 24 Jul 06 04:57:29 PM PDT 24 38243845 ps
T519 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3038385463 Jul 06 04:57:44 PM PDT 24 Jul 06 04:57:45 PM PDT 24 23229623 ps
T520 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1687501541 Jul 06 04:57:30 PM PDT 24 Jul 06 04:57:32 PM PDT 24 336542739 ps
T521 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2755584290 Jul 06 04:57:51 PM PDT 24 Jul 06 04:57:51 PM PDT 24 16231137 ps
T522 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3180598433 Jul 06 04:57:24 PM PDT 24 Jul 06 04:57:25 PM PDT 24 22008432 ps
T110 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2027538982 Jul 06 04:57:24 PM PDT 24 Jul 06 04:57:26 PM PDT 24 194640896 ps
T523 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3467529015 Jul 06 04:57:31 PM PDT 24 Jul 06 04:57:34 PM PDT 24 117364394 ps
T524 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4166313452 Jul 06 04:57:09 PM PDT 24 Jul 06 04:57:10 PM PDT 24 32450734 ps
T525 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.466875104 Jul 06 04:56:49 PM PDT 24 Jul 06 04:56:51 PM PDT 24 127301157 ps
T526 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.900172011 Jul 06 04:57:38 PM PDT 24 Jul 06 04:57:40 PM PDT 24 15288496 ps
T527 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.352327200 Jul 06 04:57:39 PM PDT 24 Jul 06 04:57:40 PM PDT 24 59031643 ps
T528 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3570976319 Jul 06 04:57:44 PM PDT 24 Jul 06 04:57:45 PM PDT 24 36524825 ps
T529 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3444718685 Jul 06 04:57:21 PM PDT 24 Jul 06 04:57:23 PM PDT 24 26246541 ps
T530 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3193222100 Jul 06 04:57:19 PM PDT 24 Jul 06 04:57:20 PM PDT 24 33207774 ps
T112 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2469142417 Jul 06 04:57:31 PM PDT 24 Jul 06 04:57:33 PM PDT 24 213506384 ps
T531 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3565667567 Jul 06 04:57:45 PM PDT 24 Jul 06 04:57:46 PM PDT 24 49669569 ps
T532 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3902707043 Jul 06 04:57:00 PM PDT 24 Jul 06 04:57:02 PM PDT 24 25669721 ps
T533 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.976402233 Jul 06 04:57:38 PM PDT 24 Jul 06 04:57:39 PM PDT 24 19459227 ps
T534 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1969307006 Jul 06 04:57:13 PM PDT 24 Jul 06 04:57:14 PM PDT 24 100972943 ps
T535 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.757265798 Jul 06 04:57:31 PM PDT 24 Jul 06 04:57:33 PM PDT 24 240912220 ps
T536 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.537531966 Jul 06 04:57:43 PM PDT 24 Jul 06 04:57:44 PM PDT 24 23705563 ps
T537 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3031405182 Jul 06 04:56:50 PM PDT 24 Jul 06 04:56:51 PM PDT 24 19792675 ps
T538 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4007502830 Jul 06 04:57:05 PM PDT 24 Jul 06 04:57:08 PM PDT 24 566420752 ps
T539 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2482100791 Jul 06 04:57:37 PM PDT 24 Jul 06 04:57:38 PM PDT 24 39545122 ps
T540 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2176423643 Jul 06 04:57:45 PM PDT 24 Jul 06 04:57:46 PM PDT 24 14112571 ps
T541 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2927973151 Jul 06 04:57:32 PM PDT 24 Jul 06 04:57:33 PM PDT 24 38076372 ps
T542 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1420606344 Jul 06 04:57:38 PM PDT 24 Jul 06 04:57:40 PM PDT 24 59055864 ps
T543 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1853879109 Jul 06 04:57:31 PM PDT 24 Jul 06 04:57:33 PM PDT 24 244299186 ps
T544 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3170903419 Jul 06 04:57:13 PM PDT 24 Jul 06 04:57:14 PM PDT 24 19602051 ps
T545 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4039561741 Jul 06 04:57:32 PM PDT 24 Jul 06 04:57:33 PM PDT 24 36401209 ps
T546 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1520574370 Jul 06 04:57:19 PM PDT 24 Jul 06 04:57:20 PM PDT 24 476377650 ps
T547 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2472840548 Jul 06 04:57:20 PM PDT 24 Jul 06 04:57:21 PM PDT 24 118771354 ps
T548 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2080777944 Jul 06 04:57:18 PM PDT 24 Jul 06 04:57:19 PM PDT 24 20416660 ps
T549 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2891487297 Jul 06 04:57:41 PM PDT 24 Jul 06 04:57:44 PM PDT 24 192702815 ps
T550 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1038624657 Jul 06 04:56:54 PM PDT 24 Jul 06 04:56:55 PM PDT 24 17931987 ps
T551 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2947286742 Jul 06 04:57:44 PM PDT 24 Jul 06 04:57:45 PM PDT 24 25432506 ps
T552 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2736270455 Jul 06 04:57:00 PM PDT 24 Jul 06 04:57:02 PM PDT 24 239808049 ps
T553 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.427843545 Jul 06 04:56:45 PM PDT 24 Jul 06 04:56:48 PM PDT 24 224001364 ps
T90 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2358261915 Jul 06 04:57:19 PM PDT 24 Jul 06 04:57:20 PM PDT 24 14248822 ps
T554 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2392044086 Jul 06 04:57:56 PM PDT 24 Jul 06 04:57:56 PM PDT 24 45114325 ps
T555 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4023124114 Jul 06 04:57:39 PM PDT 24 Jul 06 04:57:40 PM PDT 24 74898998 ps
T556 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1094888241 Jul 06 04:57:03 PM PDT 24 Jul 06 04:57:04 PM PDT 24 36167818 ps
T557 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3191697450 Jul 06 04:57:26 PM PDT 24 Jul 06 04:57:27 PM PDT 24 13346362 ps
T558 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4040863943 Jul 06 04:57:06 PM PDT 24 Jul 06 04:57:09 PM PDT 24 91732918 ps
T559 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3938433955 Jul 06 04:57:08 PM PDT 24 Jul 06 04:57:09 PM PDT 24 21435926 ps
T560 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3028037707 Jul 06 04:57:07 PM PDT 24 Jul 06 04:57:08 PM PDT 24 76800176 ps
T561 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3166510047 Jul 06 04:57:25 PM PDT 24 Jul 06 04:57:26 PM PDT 24 158121531 ps
T562 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2435007424 Jul 06 04:57:39 PM PDT 24 Jul 06 04:57:42 PM PDT 24 235661322 ps
T563 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1005893056 Jul 06 04:56:51 PM PDT 24 Jul 06 04:56:51 PM PDT 24 41668324 ps
T564 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1366029486 Jul 06 04:57:30 PM PDT 24 Jul 06 04:57:31 PM PDT 24 10919623 ps
T565 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1438158897 Jul 06 04:57:11 PM PDT 24 Jul 06 04:57:12 PM PDT 24 52055415 ps
T566 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2764215955 Jul 06 04:57:33 PM PDT 24 Jul 06 04:57:34 PM PDT 24 16443563 ps
T567 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2338881221 Jul 06 04:57:06 PM PDT 24 Jul 06 04:57:07 PM PDT 24 14063255 ps
T568 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2494395231 Jul 06 04:57:12 PM PDT 24 Jul 06 04:57:13 PM PDT 24 18571752 ps
T569 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1371605762 Jul 06 04:57:42 PM PDT 24 Jul 06 04:57:44 PM PDT 24 134936455 ps
T570 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.679919468 Jul 06 04:56:55 PM PDT 24 Jul 06 04:56:56 PM PDT 24 46792697 ps
T571 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.394852146 Jul 06 04:57:06 PM PDT 24 Jul 06 04:57:09 PM PDT 24 478102466 ps
T572 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.550820553 Jul 06 04:57:30 PM PDT 24 Jul 06 04:57:31 PM PDT 24 16029469 ps
T573 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2915996212 Jul 06 04:57:49 PM PDT 24 Jul 06 04:57:50 PM PDT 24 160087262 ps
T111 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.202637178 Jul 06 04:57:15 PM PDT 24 Jul 06 04:57:17 PM PDT 24 546992513 ps
T574 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3016347949 Jul 06 04:57:13 PM PDT 24 Jul 06 04:57:15 PM PDT 24 25699531 ps
T91 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2553513162 Jul 06 04:57:09 PM PDT 24 Jul 06 04:57:10 PM PDT 24 34838717 ps
T575 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3244617457 Jul 06 04:57:01 PM PDT 24 Jul 06 04:57:04 PM PDT 24 745131062 ps
T576 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1787252512 Jul 06 04:57:18 PM PDT 24 Jul 06 04:57:19 PM PDT 24 40590567 ps
T577 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2235526878 Jul 06 04:57:26 PM PDT 24 Jul 06 04:57:28 PM PDT 24 560428464 ps
T578 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.221941111 Jul 06 04:57:19 PM PDT 24 Jul 06 04:57:20 PM PDT 24 535906910 ps
T579 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.440066156 Jul 06 04:57:33 PM PDT 24 Jul 06 04:57:34 PM PDT 24 25726408 ps
T580 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.572465809 Jul 06 04:57:31 PM PDT 24 Jul 06 04:57:32 PM PDT 24 10929864 ps
T581 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3873129934 Jul 06 04:56:50 PM PDT 24 Jul 06 04:56:51 PM PDT 24 193399301 ps
T582 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3581194532 Jul 06 04:56:55 PM PDT 24 Jul 06 04:56:57 PM PDT 24 480366774 ps

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3821126906
Short name T1
Test name
Test status
Simulation time 83759898746 ps
CPU time 470.48 seconds
Started Jul 06 04:59:54 PM PDT 24
Finished Jul 06 05:07:45 PM PDT 24
Peak memory 206064 kb
Host smart-5ccee981-11e0-449f-80e1-79823a9a731a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821126906 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3821126906
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2946920699
Short name T129
Test name
Test status
Simulation time 209255775419 ps
CPU time 553.43 seconds
Started Jul 06 05:00:27 PM PDT 24
Finished Jul 06 05:09:41 PM PDT 24
Peak memory 191348 kb
Host smart-f7dfc6dc-7d53-4e7f-bee6-579e6c7db6c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946920699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2946920699
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/184.rv_timer_random.2286625920
Short name T5
Test name
Test status
Simulation time 135194069900 ps
CPU time 199.93 seconds
Started Jul 06 05:02:07 PM PDT 24
Finished Jul 06 05:05:27 PM PDT 24
Peak memory 191324 kb
Host smart-760bc5c8-92b7-44d6-95f0-8dfd158b2b68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286625920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2286625920
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3071975332
Short name T188
Test name
Test status
Simulation time 3509869603966 ps
CPU time 3250.22 seconds
Started Jul 06 04:59:19 PM PDT 24
Finished Jul 06 05:53:30 PM PDT 24
Peak memory 197004 kb
Host smart-cbf404c3-5778-4dc9-8001-6799e74a587a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071975332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3071975332
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.815258476
Short name T61
Test name
Test status
Simulation time 4385584252397 ps
CPU time 1999.21 seconds
Started Jul 06 04:59:31 PM PDT 24
Finished Jul 06 05:32:51 PM PDT 24
Peak memory 191344 kb
Host smart-1467ba96-bdfb-435f-9dc6-89acbf888f11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815258476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
815258476
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.133679288
Short name T29
Test name
Test status
Simulation time 50109334 ps
CPU time 0.85 seconds
Started Jul 06 04:57:32 PM PDT 24
Finished Jul 06 04:57:33 PM PDT 24
Peak memory 193272 kb
Host smart-3c3a72aa-2992-4fa4-8c5f-2077e64dcc6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133679288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.133679288
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1451082486
Short name T193
Test name
Test status
Simulation time 915245928457 ps
CPU time 1889.68 seconds
Started Jul 06 04:58:22 PM PDT 24
Finished Jul 06 05:29:52 PM PDT 24
Peak memory 196976 kb
Host smart-774db5b5-dce5-487a-9085-bfd6096bff14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451082486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1451082486
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1912430021
Short name T212
Test name
Test status
Simulation time 1608558927027 ps
CPU time 1047.85 seconds
Started Jul 06 04:58:49 PM PDT 24
Finished Jul 06 05:16:17 PM PDT 24
Peak memory 191324 kb
Host smart-2883e3f0-1b94-4058-9003-bf72e922582c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912430021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1912430021
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.64209222
Short name T32
Test name
Test status
Simulation time 12785393 ps
CPU time 0.59 seconds
Started Jul 06 04:56:50 PM PDT 24
Finished Jul 06 04:56:51 PM PDT 24
Peak memory 182304 kb
Host smart-dcadcb64-5c97-49e2-b9f5-9038339e441c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64209222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.64209222
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.858262595
Short name T179
Test name
Test status
Simulation time 2129457841799 ps
CPU time 1803.32 seconds
Started Jul 06 04:58:14 PM PDT 24
Finished Jul 06 05:28:18 PM PDT 24
Peak memory 191312 kb
Host smart-f6bbe376-861f-4678-b72e-7b2a8ea91bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858262595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
858262595
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3023108739
Short name T163
Test name
Test status
Simulation time 682360268282 ps
CPU time 1229.11 seconds
Started Jul 06 04:58:07 PM PDT 24
Finished Jul 06 05:18:37 PM PDT 24
Peak memory 191320 kb
Host smart-158163d0-e674-4084-80cb-a0a662bcb852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023108739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3023108739
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1626296545
Short name T182
Test name
Test status
Simulation time 1512768337296 ps
CPU time 2009.49 seconds
Started Jul 06 04:58:22 PM PDT 24
Finished Jul 06 05:31:52 PM PDT 24
Peak memory 191352 kb
Host smart-45c4fd56-e967-4c4f-b345-e9f7893a40a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626296545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1626296545
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.407920712
Short name T246
Test name
Test status
Simulation time 1163704044419 ps
CPU time 922.03 seconds
Started Jul 06 04:58:28 PM PDT 24
Finished Jul 06 05:13:50 PM PDT 24
Peak memory 191332 kb
Host smart-f59ed914-17c6-4816-abbd-bcac3c3db6b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407920712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
407920712
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1231572680
Short name T18
Test name
Test status
Simulation time 112025921 ps
CPU time 0.84 seconds
Started Jul 06 04:57:56 PM PDT 24
Finished Jul 06 04:57:57 PM PDT 24
Peak memory 214016 kb
Host smart-729d2777-4811-4445-8bb4-f638cda3a084
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231572680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1231572680
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/115.rv_timer_random.1151439669
Short name T138
Test name
Test status
Simulation time 1022571359956 ps
CPU time 362.35 seconds
Started Jul 06 05:01:21 PM PDT 24
Finished Jul 06 05:07:24 PM PDT 24
Peak memory 191320 kb
Host smart-6f099fb9-eb43-42fd-bf67-ab224ba44d90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151439669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1151439669
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1708947802
Short name T64
Test name
Test status
Simulation time 1069813993314 ps
CPU time 1459.05 seconds
Started Jul 06 04:58:10 PM PDT 24
Finished Jul 06 05:22:30 PM PDT 24
Peak memory 195880 kb
Host smart-9d36cdcc-75e1-40ca-9ded-569dbf839484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708947802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1708947802
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/103.rv_timer_random.2339616578
Short name T118
Test name
Test status
Simulation time 158475472551 ps
CPU time 662.61 seconds
Started Jul 06 05:01:17 PM PDT 24
Finished Jul 06 05:12:20 PM PDT 24
Peak memory 191248 kb
Host smart-a7b1dfda-2726-4e2b-82d9-15533e835f6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339616578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2339616578
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.4191604806
Short name T204
Test name
Test status
Simulation time 283076421991 ps
CPU time 881.11 seconds
Started Jul 06 05:01:17 PM PDT 24
Finished Jul 06 05:15:59 PM PDT 24
Peak memory 191320 kb
Host smart-9c103ea3-e40a-4c3f-ae9c-f1b3742d9b66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191604806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.4191604806
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.140735799
Short name T190
Test name
Test status
Simulation time 685034015920 ps
CPU time 610.07 seconds
Started Jul 06 05:01:34 PM PDT 24
Finished Jul 06 05:11:44 PM PDT 24
Peak memory 191336 kb
Host smart-1d7b9602-97f6-4769-b55b-0eda581da053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140735799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.140735799
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1294088564
Short name T127
Test name
Test status
Simulation time 108497805599 ps
CPU time 189.94 seconds
Started Jul 06 05:02:05 PM PDT 24
Finished Jul 06 05:05:15 PM PDT 24
Peak memory 191316 kb
Host smart-89f319e3-76b7-47d3-bb1c-48e2aabf7922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294088564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1294088564
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.605662322
Short name T66
Test name
Test status
Simulation time 1675260213125 ps
CPU time 1470.16 seconds
Started Jul 06 05:00:03 PM PDT 24
Finished Jul 06 05:24:33 PM PDT 24
Peak memory 191248 kb
Host smart-45b0b46c-bcbb-405f-bd65-47897aa16eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605662322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
605662322
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1963642216
Short name T24
Test name
Test status
Simulation time 1712159931936 ps
CPU time 712.17 seconds
Started Jul 06 04:58:22 PM PDT 24
Finished Jul 06 05:10:15 PM PDT 24
Peak memory 183028 kb
Host smart-de77648a-5811-406b-9220-2b00b09fd118
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963642216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1963642216
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1053856180
Short name T195
Test name
Test status
Simulation time 1621517747226 ps
CPU time 1291.27 seconds
Started Jul 06 05:00:35 PM PDT 24
Finished Jul 06 05:22:06 PM PDT 24
Peak memory 191248 kb
Host smart-650187f2-e0c9-4432-bc61-f533d7bfea67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053856180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1053856180
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/102.rv_timer_random.3564528631
Short name T247
Test name
Test status
Simulation time 449262420340 ps
CPU time 558.56 seconds
Started Jul 06 05:01:17 PM PDT 24
Finished Jul 06 05:10:36 PM PDT 24
Peak memory 191232 kb
Host smart-0a9c4112-231f-49f7-8d9f-2c015c4f314a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564528631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3564528631
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1638522752
Short name T157
Test name
Test status
Simulation time 798776860924 ps
CPU time 1466.17 seconds
Started Jul 06 05:01:21 PM PDT 24
Finished Jul 06 05:25:48 PM PDT 24
Peak memory 193484 kb
Host smart-ad788119-952f-42a0-8a52-d1f6964bbf44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638522752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1638522752
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1546572357
Short name T222
Test name
Test status
Simulation time 475478581794 ps
CPU time 686.84 seconds
Started Jul 06 05:01:27 PM PDT 24
Finished Jul 06 05:12:54 PM PDT 24
Peak memory 191344 kb
Host smart-99112e91-aa95-4539-9ee7-e27167c2dd87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546572357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1546572357
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3369601695
Short name T187
Test name
Test status
Simulation time 279882962142 ps
CPU time 880.65 seconds
Started Jul 06 04:59:13 PM PDT 24
Finished Jul 06 05:13:54 PM PDT 24
Peak memory 191316 kb
Host smart-0377ef2b-f3ec-4c08-a2ad-f4f5d2b1ee71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369601695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3369601695
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random.257101150
Short name T310
Test name
Test status
Simulation time 475457889996 ps
CPU time 532.5 seconds
Started Jul 06 04:58:12 PM PDT 24
Finished Jul 06 05:07:05 PM PDT 24
Peak memory 191288 kb
Host smart-aac17f5d-abb4-4c19-95ab-5d6222287468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257101150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.257101150
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.1894136449
Short name T437
Test name
Test status
Simulation time 2242964139952 ps
CPU time 744.77 seconds
Started Jul 06 04:58:21 PM PDT 24
Finished Jul 06 05:10:47 PM PDT 24
Peak memory 191340 kb
Host smart-257644a6-fb88-481b-a19c-b92c39a11359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894136449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1894136449
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1659828620
Short name T173
Test name
Test status
Simulation time 243971513387 ps
CPU time 382.38 seconds
Started Jul 06 04:58:21 PM PDT 24
Finished Jul 06 05:04:44 PM PDT 24
Peak memory 195724 kb
Host smart-47a62ef9-4f25-4dff-a53a-213d16e4427f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659828620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1659828620
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/65.rv_timer_random.2093916495
Short name T221
Test name
Test status
Simulation time 206595158930 ps
CPU time 222.55 seconds
Started Jul 06 05:00:54 PM PDT 24
Finished Jul 06 05:04:37 PM PDT 24
Peak memory 191252 kb
Host smart-7a36d2d0-7c53-4284-bcda-c1e882ed1891
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093916495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2093916495
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1159654433
Short name T87
Test name
Test status
Simulation time 46656220 ps
CPU time 0.59 seconds
Started Jul 06 04:57:38 PM PDT 24
Finished Jul 06 04:57:39 PM PDT 24
Peak memory 182196 kb
Host smart-460aa3db-9ce6-4a97-9e5b-f73d0d039934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159654433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1159654433
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/149.rv_timer_random.1449260276
Short name T225
Test name
Test status
Simulation time 286174940259 ps
CPU time 345.26 seconds
Started Jul 06 05:01:43 PM PDT 24
Finished Jul 06 05:07:29 PM PDT 24
Peak memory 191348 kb
Host smart-8a3abb88-dc03-497e-82c0-a70676510bee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449260276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1449260276
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.2007995047
Short name T115
Test name
Test status
Simulation time 245868792401 ps
CPU time 118.8 seconds
Started Jul 06 05:01:47 PM PDT 24
Finished Jul 06 05:03:46 PM PDT 24
Peak memory 191244 kb
Host smart-5ad75113-8e7a-4eef-b20f-fca871928cc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007995047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2007995047
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2952537731
Short name T239
Test name
Test status
Simulation time 124511482031 ps
CPU time 187.66 seconds
Started Jul 06 05:01:45 PM PDT 24
Finished Jul 06 05:04:53 PM PDT 24
Peak memory 191328 kb
Host smart-e73a04b4-b3c1-47b6-aff4-a92eea6b0959
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952537731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2952537731
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2461204147
Short name T21
Test name
Test status
Simulation time 363284080645 ps
CPU time 291.61 seconds
Started Jul 06 05:02:12 PM PDT 24
Finished Jul 06 05:07:04 PM PDT 24
Peak memory 191224 kb
Host smart-a27e803c-9404-4b9d-b582-d7edae27d705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461204147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2461204147
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3610521862
Short name T130
Test name
Test status
Simulation time 121187537666 ps
CPU time 539.24 seconds
Started Jul 06 05:00:01 PM PDT 24
Finished Jul 06 05:09:00 PM PDT 24
Peak memory 191324 kb
Host smart-99e9d94f-908f-4989-831b-d5af0d5a1051
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610521862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3610521862
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2730133677
Short name T50
Test name
Test status
Simulation time 554477097506 ps
CPU time 1196.04 seconds
Started Jul 06 04:58:09 PM PDT 24
Finished Jul 06 05:18:06 PM PDT 24
Peak memory 191316 kb
Host smart-11ea9590-008a-425c-8cce-ab9b2136c350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730133677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2730133677
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.805556935
Short name T278
Test name
Test status
Simulation time 242627792250 ps
CPU time 919.52 seconds
Started Jul 06 04:58:00 PM PDT 24
Finished Jul 06 05:13:20 PM PDT 24
Peak memory 195932 kb
Host smart-8dd8ee3b-ca35-41d7-b9fd-d7b7b581776c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805556935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.805556935
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/147.rv_timer_random.3857394736
Short name T299
Test name
Test status
Simulation time 61536947508 ps
CPU time 1009.1 seconds
Started Jul 06 05:01:40 PM PDT 24
Finished Jul 06 05:18:29 PM PDT 24
Peak memory 191344 kb
Host smart-78a09c52-3ba5-4db1-8e32-0d0f406aa35b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857394736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3857394736
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2185178169
Short name T354
Test name
Test status
Simulation time 615818787698 ps
CPU time 306.91 seconds
Started Jul 06 05:02:16 PM PDT 24
Finished Jul 06 05:07:23 PM PDT 24
Peak memory 191340 kb
Host smart-47e9821f-27c7-463c-9cf5-fff6536a6414
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185178169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2185178169
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.16929136
Short name T197
Test name
Test status
Simulation time 2639321363297 ps
CPU time 1128.62 seconds
Started Jul 06 04:59:32 PM PDT 24
Finished Jul 06 05:18:21 PM PDT 24
Peak memory 191336 kb
Host smart-dc4d293b-0471-4445-9c26-bbe8bfa6a4f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16929136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.16929136
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_random.253709841
Short name T231
Test name
Test status
Simulation time 501927247112 ps
CPU time 978.34 seconds
Started Jul 06 05:00:35 PM PDT 24
Finished Jul 06 05:16:53 PM PDT 24
Peak memory 191236 kb
Host smart-89b2df36-3f24-40a5-b1d7-645faa0bc3a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253709841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.253709841
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2299996857
Short name T109
Test name
Test status
Simulation time 71939517 ps
CPU time 1.04 seconds
Started Jul 06 04:57:05 PM PDT 24
Finished Jul 06 04:57:06 PM PDT 24
Peak memory 194760 kb
Host smart-ec0cbb15-0e56-4a8d-aa12-77dc7b0e9429
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299996857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2299996857
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/100.rv_timer_random.3312728993
Short name T169
Test name
Test status
Simulation time 738258619923 ps
CPU time 437.47 seconds
Started Jul 06 05:01:10 PM PDT 24
Finished Jul 06 05:08:28 PM PDT 24
Peak memory 191316 kb
Host smart-e1b9e4aa-c7a6-4f19-92cb-0dc721afc80f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312728993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3312728993
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3305322404
Short name T218
Test name
Test status
Simulation time 3234537413001 ps
CPU time 926.03 seconds
Started Jul 06 05:01:21 PM PDT 24
Finished Jul 06 05:16:47 PM PDT 24
Peak memory 191164 kb
Host smart-60fd4e3e-7b98-465d-a608-ba73be72e4b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305322404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3305322404
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1306589156
Short name T206
Test name
Test status
Simulation time 306100681432 ps
CPU time 488.63 seconds
Started Jul 06 05:01:21 PM PDT 24
Finished Jul 06 05:09:30 PM PDT 24
Peak memory 191308 kb
Host smart-b5f0fa5a-8269-4de5-9396-3382e43da6e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306589156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1306589156
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.448588610
Short name T263
Test name
Test status
Simulation time 756522864481 ps
CPU time 323.44 seconds
Started Jul 06 05:01:29 PM PDT 24
Finished Jul 06 05:06:53 PM PDT 24
Peak memory 191296 kb
Host smart-e066c12d-de48-4b20-abad-4eb6634e501b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448588610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.448588610
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.3052455801
Short name T121
Test name
Test status
Simulation time 151048056448 ps
CPU time 633.69 seconds
Started Jul 06 05:01:28 PM PDT 24
Finished Jul 06 05:12:02 PM PDT 24
Peak memory 191308 kb
Host smart-032bc59f-fa5e-411c-816b-4c7fa711dbe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052455801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.3052455801
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.308766044
Short name T167
Test name
Test status
Simulation time 78089092570 ps
CPU time 126.94 seconds
Started Jul 06 05:01:27 PM PDT 24
Finished Jul 06 05:03:35 PM PDT 24
Peak memory 183040 kb
Host smart-5bcaf92f-6b16-435e-b1d4-5e79add37e77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308766044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.308766044
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.429255317
Short name T325
Test name
Test status
Simulation time 259357163137 ps
CPU time 140.24 seconds
Started Jul 06 04:58:21 PM PDT 24
Finished Jul 06 05:00:42 PM PDT 24
Peak memory 191292 kb
Host smart-a0a806fd-9c60-4c4c-8ff6-cf73ddc28a37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429255317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.429255317
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1580058755
Short name T269
Test name
Test status
Simulation time 443351293517 ps
CPU time 257.59 seconds
Started Jul 06 05:01:52 PM PDT 24
Finished Jul 06 05:06:10 PM PDT 24
Peak memory 191228 kb
Host smart-26dcf7b8-82d9-4fa7-9f94-972205009646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580058755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1580058755
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.142161203
Short name T201
Test name
Test status
Simulation time 90973359705 ps
CPU time 86.78 seconds
Started Jul 06 05:02:12 PM PDT 24
Finished Jul 06 05:03:39 PM PDT 24
Peak memory 194640 kb
Host smart-779e098c-c989-4732-968a-522e91d136e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142161203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.142161203
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.4272985771
Short name T26
Test name
Test status
Simulation time 48106082365 ps
CPU time 76.38 seconds
Started Jul 06 04:59:07 PM PDT 24
Finished Jul 06 05:00:24 PM PDT 24
Peak memory 183012 kb
Host smart-a384ef5d-76c4-4f62-9543-f4d5e899a8f6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272985771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.4272985771
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/96.rv_timer_random.1329780855
Short name T348
Test name
Test status
Simulation time 80680694283 ps
CPU time 204.1 seconds
Started Jul 06 05:01:09 PM PDT 24
Finished Jul 06 05:04:33 PM PDT 24
Peak memory 191316 kb
Host smart-1070383c-9788-48b7-93e3-3353fd96ee3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329780855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1329780855
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2127658203
Short name T4
Test name
Test status
Simulation time 116526759546 ps
CPU time 1248.91 seconds
Started Jul 06 04:58:14 PM PDT 24
Finished Jul 06 05:19:03 PM PDT 24
Peak memory 191220 kb
Host smart-2c8b5d1e-4be4-4c83-8586-6a509e8519e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127658203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2127658203
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/122.rv_timer_random.1647770404
Short name T256
Test name
Test status
Simulation time 402306115683 ps
CPU time 1666.94 seconds
Started Jul 06 05:01:22 PM PDT 24
Finished Jul 06 05:29:09 PM PDT 24
Peak memory 191212 kb
Host smart-52e04906-e64f-4b8c-8dfe-55065c28d786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647770404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1647770404
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3761105972
Short name T58
Test name
Test status
Simulation time 157146027693 ps
CPU time 309.26 seconds
Started Jul 06 05:01:28 PM PDT 24
Finished Jul 06 05:06:38 PM PDT 24
Peak memory 192532 kb
Host smart-b9b5b18d-e8f4-408d-83d5-ab3e9939a7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761105972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3761105972
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3474368833
Short name T178
Test name
Test status
Simulation time 137287817145 ps
CPU time 753.83 seconds
Started Jul 06 05:01:34 PM PDT 24
Finished Jul 06 05:14:08 PM PDT 24
Peak memory 191324 kb
Host smart-0a876085-acd3-409c-8a96-841268c37d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474368833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3474368833
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.3227116979
Short name T191
Test name
Test status
Simulation time 156708367605 ps
CPU time 279.65 seconds
Started Jul 06 05:01:37 PM PDT 24
Finished Jul 06 05:06:17 PM PDT 24
Peak memory 191320 kb
Host smart-84ad0b87-10aa-458d-8105-65f5027b5012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227116979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3227116979
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.1299858459
Short name T25
Test name
Test status
Simulation time 136868035839 ps
CPU time 199.9 seconds
Started Jul 06 04:58:20 PM PDT 24
Finished Jul 06 05:01:40 PM PDT 24
Peak memory 194908 kb
Host smart-12a9ddd3-b57c-4921-ab85-29577dc440bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299858459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1299858459
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.1372343305
Short name T351
Test name
Test status
Simulation time 1130824329888 ps
CPU time 556.52 seconds
Started Jul 06 04:58:36 PM PDT 24
Finished Jul 06 05:07:53 PM PDT 24
Peak memory 183076 kb
Host smart-33eca089-d1bf-44c7-aacc-86ac93e05320
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372343305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.1372343305
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2609162240
Short name T180
Test name
Test status
Simulation time 1122551737439 ps
CPU time 1797.82 seconds
Started Jul 06 04:59:06 PM PDT 24
Finished Jul 06 05:29:05 PM PDT 24
Peak memory 191344 kb
Host smart-e6c9e949-5287-4da0-a819-54f81ee6bc72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609162240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2609162240
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/54.rv_timer_random.2184159366
Short name T155
Test name
Test status
Simulation time 14388288102 ps
CPU time 107.07 seconds
Started Jul 06 05:00:45 PM PDT 24
Finished Jul 06 05:02:33 PM PDT 24
Peak memory 182988 kb
Host smart-9cac162c-d164-480d-8205-d6aaccf45069
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184159366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2184159366
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2166976637
Short name T330
Test name
Test status
Simulation time 159278324694 ps
CPU time 181.86 seconds
Started Jul 06 04:57:56 PM PDT 24
Finished Jul 06 05:00:58 PM PDT 24
Peak memory 183040 kb
Host smart-2a1322d2-14a7-4b23-a158-bad46591c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166976637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2166976637
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/108.rv_timer_random.2234145812
Short name T175
Test name
Test status
Simulation time 161648450351 ps
CPU time 360.19 seconds
Started Jul 06 05:01:21 PM PDT 24
Finished Jul 06 05:07:22 PM PDT 24
Peak memory 191284 kb
Host smart-0534569d-3d98-44e8-874c-f0568709285d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234145812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2234145812
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.1587238403
Short name T81
Test name
Test status
Simulation time 117977999924 ps
CPU time 186.49 seconds
Started Jul 06 04:58:17 PM PDT 24
Finished Jul 06 05:01:24 PM PDT 24
Peak memory 194084 kb
Host smart-ce696c9a-31f2-4eb2-afe5-77d7fada0815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587238403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1587238403
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.290216810
Short name T267
Test name
Test status
Simulation time 91145493859 ps
CPU time 146.17 seconds
Started Jul 06 04:58:16 PM PDT 24
Finished Jul 06 05:00:42 PM PDT 24
Peak memory 183092 kb
Host smart-847f65d1-5647-4677-b541-7a1071addcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290216810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.290216810
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/125.rv_timer_random.1546486482
Short name T306
Test name
Test status
Simulation time 42241689074 ps
CPU time 68.5 seconds
Started Jul 06 05:01:27 PM PDT 24
Finished Jul 06 05:02:36 PM PDT 24
Peak memory 191344 kb
Host smart-4dc8ac2c-1d56-42e3-83a8-eb9227d1b6ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546486482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1546486482
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.2523038660
Short name T314
Test name
Test status
Simulation time 382157941294 ps
CPU time 1878.71 seconds
Started Jul 06 04:58:21 PM PDT 24
Finished Jul 06 05:29:40 PM PDT 24
Peak memory 191292 kb
Host smart-046755c8-8593-420c-b71b-c95db18ce65e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523038660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2523038660
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.1072347497
Short name T257
Test name
Test status
Simulation time 407657075941 ps
CPU time 447.51 seconds
Started Jul 06 04:58:17 PM PDT 24
Finished Jul 06 05:05:45 PM PDT 24
Peak memory 191244 kb
Host smart-e3dc1960-e676-43a1-86f4-ee48d4702a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072347497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.1072347497
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3641385944
Short name T280
Test name
Test status
Simulation time 80115256738 ps
CPU time 91.19 seconds
Started Jul 06 05:04:00 PM PDT 24
Finished Jul 06 05:05:31 PM PDT 24
Peak memory 183032 kb
Host smart-ba1beda8-9df6-4646-ab4a-c85734c07a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641385944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3641385944
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3744548921
Short name T279
Test name
Test status
Simulation time 244071569046 ps
CPU time 328.24 seconds
Started Jul 06 05:01:34 PM PDT 24
Finished Jul 06 05:07:03 PM PDT 24
Peak memory 191336 kb
Host smart-175bf3c7-c65c-4855-bd44-657a6affb10b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744548921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3744548921
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3944487192
Short name T260
Test name
Test status
Simulation time 790209124479 ps
CPU time 2912.7 seconds
Started Jul 06 05:01:40 PM PDT 24
Finished Jul 06 05:50:13 PM PDT 24
Peak memory 191176 kb
Host smart-f07fa1c4-3136-4662-a6a3-ec7100dc2367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944487192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3944487192
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1317852671
Short name T301
Test name
Test status
Simulation time 299732588118 ps
CPU time 1850.39 seconds
Started Jul 06 05:01:46 PM PDT 24
Finished Jul 06 05:32:37 PM PDT 24
Peak memory 191284 kb
Host smart-4160dd1a-5ecf-4427-aad2-9076c0327d08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317852671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1317852671
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3905758608
Short name T100
Test name
Test status
Simulation time 156308888942 ps
CPU time 2001.09 seconds
Started Jul 06 05:01:53 PM PDT 24
Finished Jul 06 05:35:15 PM PDT 24
Peak memory 191188 kb
Host smart-7656c483-c26b-41b7-980f-126213a3ce40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905758608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3905758608
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.2518341932
Short name T345
Test name
Test status
Simulation time 282656819824 ps
CPU time 395.97 seconds
Started Jul 06 04:58:20 PM PDT 24
Finished Jul 06 05:04:56 PM PDT 24
Peak memory 191316 kb
Host smart-5106909b-4561-44b6-b5dd-a7c88b79a4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518341932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2518341932
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.3956767131
Short name T227
Test name
Test status
Simulation time 499588258200 ps
CPU time 778.09 seconds
Started Jul 06 05:01:52 PM PDT 24
Finished Jul 06 05:14:51 PM PDT 24
Peak memory 191232 kb
Host smart-be866f66-3cc4-4d0b-8bb9-78b7a21cce85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956767131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3956767131
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.212018674
Short name T331
Test name
Test status
Simulation time 46560522685 ps
CPU time 312.34 seconds
Started Jul 06 05:01:51 PM PDT 24
Finished Jul 06 05:07:04 PM PDT 24
Peak memory 183036 kb
Host smart-6d44da94-da5c-48b9-8bae-bea57ea99fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212018674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.212018674
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3765475658
Short name T289
Test name
Test status
Simulation time 811039996320 ps
CPU time 298.67 seconds
Started Jul 06 05:01:58 PM PDT 24
Finished Jul 06 05:06:57 PM PDT 24
Peak memory 191340 kb
Host smart-6df60161-3ce4-434a-80ac-80dad801812f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765475658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3765475658
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.580225412
Short name T70
Test name
Test status
Simulation time 112607155498 ps
CPU time 247.01 seconds
Started Jul 06 05:02:02 PM PDT 24
Finished Jul 06 05:06:09 PM PDT 24
Peak memory 191340 kb
Host smart-f5c09d5f-e755-466e-ac7b-523262b06d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580225412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.580225412
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1179059366
Short name T334
Test name
Test status
Simulation time 169661309103 ps
CPU time 187.93 seconds
Started Jul 06 05:02:16 PM PDT 24
Finished Jul 06 05:05:24 PM PDT 24
Peak memory 191348 kb
Host smart-2ce3c54c-ebbb-48be-abaf-209b9ba8de9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179059366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1179059366
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1571755456
Short name T343
Test name
Test status
Simulation time 1716389873 ps
CPU time 3.36 seconds
Started Jul 06 04:58:24 PM PDT 24
Finished Jul 06 04:58:28 PM PDT 24
Peak memory 182968 kb
Host smart-a13fb423-0776-489a-b84d-720dda7c51dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571755456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1571755456
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_random.404345195
Short name T71
Test name
Test status
Simulation time 348966522572 ps
CPU time 168.19 seconds
Started Jul 06 04:58:27 PM PDT 24
Finished Jul 06 05:01:15 PM PDT 24
Peak memory 191224 kb
Host smart-a11188bb-92bc-4acf-b0ea-8d8f6452c6f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404345195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.404345195
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.1006967691
Short name T296
Test name
Test status
Simulation time 198080315180 ps
CPU time 1177.86 seconds
Started Jul 06 04:58:02 PM PDT 24
Finished Jul 06 05:17:40 PM PDT 24
Peak memory 191212 kb
Host smart-1b5b110b-6976-4bcc-b2e6-b310d8cafc10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006967691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.1006967691
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.547999501
Short name T174
Test name
Test status
Simulation time 1017897196432 ps
CPU time 600.62 seconds
Started Jul 06 05:00:55 PM PDT 24
Finished Jul 06 05:10:56 PM PDT 24
Peak memory 191236 kb
Host smart-1c48439a-380d-40c3-b965-7b5b1473484b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547999501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.547999501
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.3518243697
Short name T135
Test name
Test status
Simulation time 541813196063 ps
CPU time 295.21 seconds
Started Jul 06 04:58:13 PM PDT 24
Finished Jul 06 05:03:09 PM PDT 24
Peak memory 183140 kb
Host smart-5549aaf4-6c91-4e97-b24d-001fd9fee0d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518243697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.3518243697
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1238549658
Short name T46
Test name
Test status
Simulation time 56653456 ps
CPU time 0.63 seconds
Started Jul 06 04:56:49 PM PDT 24
Finished Jul 06 04:56:50 PM PDT 24
Peak memory 182236 kb
Host smart-cb3269bf-2efb-42c7-87b8-ab1c0a66b701
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238549658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1238549658
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.466875104
Short name T525
Test name
Test status
Simulation time 127301157 ps
CPU time 1.53 seconds
Started Jul 06 04:56:49 PM PDT 24
Finished Jul 06 04:56:51 PM PDT 24
Peak memory 193544 kb
Host smart-e2eeb87d-e21e-4d3a-91f6-cc3fdd834024
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466875104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.466875104
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3031405182
Short name T537
Test name
Test status
Simulation time 19792675 ps
CPU time 0.55 seconds
Started Jul 06 04:56:50 PM PDT 24
Finished Jul 06 04:56:51 PM PDT 24
Peak memory 181856 kb
Host smart-1826b81d-4868-499c-98a5-bfeb17515be9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031405182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3031405182
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.132430995
Short name T518
Test name
Test status
Simulation time 38243845 ps
CPU time 0.96 seconds
Started Jul 06 04:57:28 PM PDT 24
Finished Jul 06 04:57:29 PM PDT 24
Peak memory 196880 kb
Host smart-e385ad35-069e-47ba-9a92-6f89ce318a46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132430995 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.132430995
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1005893056
Short name T563
Test name
Test status
Simulation time 41668324 ps
CPU time 0.55 seconds
Started Jul 06 04:56:51 PM PDT 24
Finished Jul 06 04:56:51 PM PDT 24
Peak memory 182216 kb
Host smart-5972d132-49dc-4100-8de2-3578d35c5656
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005893056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1005893056
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.347872346
Short name T77
Test name
Test status
Simulation time 73409731 ps
CPU time 0.66 seconds
Started Jul 06 04:56:49 PM PDT 24
Finished Jul 06 04:56:50 PM PDT 24
Peak memory 191640 kb
Host smart-d12a92d0-2bf9-4085-9d39-c5057a7e2663
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347872346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.347872346
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.427843545
Short name T553
Test name
Test status
Simulation time 224001364 ps
CPU time 2.48 seconds
Started Jul 06 04:56:45 PM PDT 24
Finished Jul 06 04:56:48 PM PDT 24
Peak memory 196976 kb
Host smart-e72e2ec5-7dd3-4c26-95ed-f8d5b0eb7546
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427843545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.427843545
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3873129934
Short name T581
Test name
Test status
Simulation time 193399301 ps
CPU time 1.06 seconds
Started Jul 06 04:56:50 PM PDT 24
Finished Jul 06 04:56:51 PM PDT 24
Peak memory 194564 kb
Host smart-8cb49dd3-2df9-49c1-80af-2fbc9e2e9bec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873129934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3873129934
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1392397295
Short name T33
Test name
Test status
Simulation time 76180856 ps
CPU time 0.62 seconds
Started Jul 06 04:56:56 PM PDT 24
Finished Jul 06 04:56:57 PM PDT 24
Peak memory 191544 kb
Host smart-818d496c-d9da-40d1-aeaa-3e6ab147d94d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392397295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1392397295
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4182804894
Short name T47
Test name
Test status
Simulation time 1930034487 ps
CPU time 3.79 seconds
Started Jul 06 04:56:56 PM PDT 24
Finished Jul 06 04:57:00 PM PDT 24
Peak memory 193532 kb
Host smart-56f1ae63-c41b-4a77-a9a1-cd0202bcd3b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182804894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.4182804894
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3538346208
Short name T75
Test name
Test status
Simulation time 13343861 ps
CPU time 0.55 seconds
Started Jul 06 04:56:55 PM PDT 24
Finished Jul 06 04:56:56 PM PDT 24
Peak memory 181952 kb
Host smart-09a5dafe-0c70-4e88-9baf-d46ffadd8bd0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538346208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3538346208
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1768993022
Short name T471
Test name
Test status
Simulation time 108071114 ps
CPU time 0.87 seconds
Started Jul 06 04:56:55 PM PDT 24
Finished Jul 06 04:56:57 PM PDT 24
Peak memory 196228 kb
Host smart-be759cff-d1b0-4a74-80a5-e7f58fd066b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768993022 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1768993022
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.2660955332
Short name T86
Test name
Test status
Simulation time 14821261 ps
CPU time 0.58 seconds
Started Jul 06 04:56:57 PM PDT 24
Finished Jul 06 04:56:57 PM PDT 24
Peak memory 182240 kb
Host smart-a68ea1a0-f644-4ca2-8ff4-a9f2f8bf96f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660955332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.2660955332
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1038624657
Short name T550
Test name
Test status
Simulation time 17931987 ps
CPU time 0.57 seconds
Started Jul 06 04:56:54 PM PDT 24
Finished Jul 06 04:56:55 PM PDT 24
Peak memory 182200 kb
Host smart-795e06fb-81ee-4d95-a8bb-33418ed27bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038624657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1038624657
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1859062421
Short name T98
Test name
Test status
Simulation time 14533591 ps
CPU time 0.64 seconds
Started Jul 06 04:56:56 PM PDT 24
Finished Jul 06 04:56:57 PM PDT 24
Peak memory 190948 kb
Host smart-8eebddf6-78ce-47a2-89eb-8e25ad1ac033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859062421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1859062421
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.2159697319
Short name T495
Test name
Test status
Simulation time 611608355 ps
CPU time 2.05 seconds
Started Jul 06 04:56:54 PM PDT 24
Finished Jul 06 04:56:56 PM PDT 24
Peak memory 197116 kb
Host smart-ee717c72-1c35-4d2c-96b5-c38818f3bcfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159697319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.2159697319
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3581194532
Short name T582
Test name
Test status
Simulation time 480366774 ps
CPU time 1.07 seconds
Started Jul 06 04:56:55 PM PDT 24
Finished Jul 06 04:56:57 PM PDT 24
Peak memory 194840 kb
Host smart-9addef8d-2b13-4521-a6b0-83e8941211bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581194532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3581194532
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1835531391
Short name T458
Test name
Test status
Simulation time 69685003 ps
CPU time 0.85 seconds
Started Jul 06 04:57:31 PM PDT 24
Finished Jul 06 04:57:32 PM PDT 24
Peak memory 196864 kb
Host smart-fdc3c0b0-61cd-44aa-967f-315f035257dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835531391 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1835531391
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.982966429
Short name T494
Test name
Test status
Simulation time 24671330 ps
CPU time 0.56 seconds
Started Jul 06 04:57:24 PM PDT 24
Finished Jul 06 04:57:24 PM PDT 24
Peak memory 182268 kb
Host smart-1a30df9d-872a-4892-9c84-a8a909e712c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982966429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.982966429
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1366029486
Short name T564
Test name
Test status
Simulation time 10919623 ps
CPU time 0.59 seconds
Started Jul 06 04:57:30 PM PDT 24
Finished Jul 06 04:57:31 PM PDT 24
Peak memory 181696 kb
Host smart-a975aca3-521b-4ece-b9bd-08d85ce69383
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366029486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1366029486
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3162383886
Short name T96
Test name
Test status
Simulation time 104639607 ps
CPU time 0.6 seconds
Started Jul 06 04:57:31 PM PDT 24
Finished Jul 06 04:57:32 PM PDT 24
Peak memory 191556 kb
Host smart-93a3eb5e-0f5f-4395-a5e6-1755a233fba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162383886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3162383886
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.2235526878
Short name T577
Test name
Test status
Simulation time 560428464 ps
CPU time 2.05 seconds
Started Jul 06 04:57:26 PM PDT 24
Finished Jul 06 04:57:28 PM PDT 24
Peak memory 197056 kb
Host smart-9e1372a0-5436-465f-b121-bfc212bfc02d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235526878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.2235526878
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3738631445
Short name T30
Test name
Test status
Simulation time 101232995 ps
CPU time 1.4 seconds
Started Jul 06 04:57:23 PM PDT 24
Finished Jul 06 04:57:25 PM PDT 24
Peak memory 195192 kb
Host smart-de74e115-aa00-4b56-9422-4c9e09840bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738631445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3738631445
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1843842219
Short name T493
Test name
Test status
Simulation time 27131857 ps
CPU time 0.83 seconds
Started Jul 06 04:57:26 PM PDT 24
Finished Jul 06 04:57:27 PM PDT 24
Peak memory 196264 kb
Host smart-a12862b3-8324-4743-a868-61adc93ae7a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843842219 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1843842219
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3338125897
Short name T492
Test name
Test status
Simulation time 13771585 ps
CPU time 0.59 seconds
Started Jul 06 04:57:32 PM PDT 24
Finished Jul 06 04:57:33 PM PDT 24
Peak memory 182100 kb
Host smart-296c4055-aa18-48a5-b26b-66761c52e53a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338125897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3338125897
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.572465809
Short name T580
Test name
Test status
Simulation time 10929864 ps
CPU time 0.54 seconds
Started Jul 06 04:57:31 PM PDT 24
Finished Jul 06 04:57:32 PM PDT 24
Peak memory 181692 kb
Host smart-00656e2c-884d-4af9-88f7-1a8cc3e0eb2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572465809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.572465809
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.3180598433
Short name T522
Test name
Test status
Simulation time 22008432 ps
CPU time 0.64 seconds
Started Jul 06 04:57:24 PM PDT 24
Finished Jul 06 04:57:25 PM PDT 24
Peak memory 191480 kb
Host smart-cf7c161d-ea37-4379-856e-73297f238914
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180598433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.3180598433
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1687501541
Short name T520
Test name
Test status
Simulation time 336542739 ps
CPU time 1.86 seconds
Started Jul 06 04:57:30 PM PDT 24
Finished Jul 06 04:57:32 PM PDT 24
Peak memory 197060 kb
Host smart-fad96ea7-67ec-44af-bc24-3747f42bb6fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687501541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1687501541
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3182378745
Short name T465
Test name
Test status
Simulation time 30615954 ps
CPU time 1.31 seconds
Started Jul 06 04:57:33 PM PDT 24
Finished Jul 06 04:57:35 PM PDT 24
Peak memory 197084 kb
Host smart-a50f1139-1cf4-49c6-9ef3-bb5f222d2d39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182378745 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3182378745
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.371533768
Short name T487
Test name
Test status
Simulation time 25906299 ps
CPU time 0.53 seconds
Started Jul 06 04:57:33 PM PDT 24
Finished Jul 06 04:57:33 PM PDT 24
Peak memory 182096 kb
Host smart-4d214af6-12d3-4804-bb09-0c2c186827aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371533768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.371533768
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2526260372
Short name T486
Test name
Test status
Simulation time 13059884 ps
CPU time 0.52 seconds
Started Jul 06 04:57:26 PM PDT 24
Finished Jul 06 04:57:27 PM PDT 24
Peak memory 181824 kb
Host smart-d0e7e622-025a-4656-af31-929deb0166a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526260372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2526260372
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.550820553
Short name T572
Test name
Test status
Simulation time 16029469 ps
CPU time 0.61 seconds
Started Jul 06 04:57:30 PM PDT 24
Finished Jul 06 04:57:31 PM PDT 24
Peak memory 191544 kb
Host smart-8210eae8-14de-49c0-aa87-ebd9044877ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550820553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.550820553
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.845421941
Short name T456
Test name
Test status
Simulation time 185770955 ps
CPU time 1.94 seconds
Started Jul 06 04:57:32 PM PDT 24
Finished Jul 06 04:57:35 PM PDT 24
Peak memory 197124 kb
Host smart-8d37698e-338a-4e37-b15c-8e4dc18f09b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845421941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.845421941
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2027538982
Short name T110
Test name
Test status
Simulation time 194640896 ps
CPU time 1.09 seconds
Started Jul 06 04:57:24 PM PDT 24
Finished Jul 06 04:57:26 PM PDT 24
Peak memory 194468 kb
Host smart-15243683-90f1-40fd-a99a-2c6de79aced1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027538982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2027538982
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1943915481
Short name T467
Test name
Test status
Simulation time 18259849 ps
CPU time 0.66 seconds
Started Jul 06 04:57:31 PM PDT 24
Finished Jul 06 04:57:33 PM PDT 24
Peak memory 193604 kb
Host smart-be652f26-a077-48f3-bab7-497d2ee99924
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943915481 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1943915481
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2365583512
Short name T514
Test name
Test status
Simulation time 31361950 ps
CPU time 0.57 seconds
Started Jul 06 04:57:31 PM PDT 24
Finished Jul 06 04:57:32 PM PDT 24
Peak memory 182328 kb
Host smart-edf29612-242d-4c4f-bb9a-a79d1be4f322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365583512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2365583512
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2764215955
Short name T566
Test name
Test status
Simulation time 16443563 ps
CPU time 0.57 seconds
Started Jul 06 04:57:33 PM PDT 24
Finished Jul 06 04:57:34 PM PDT 24
Peak memory 182160 kb
Host smart-3eaf359f-31d1-469a-aed5-98d170d290bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764215955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2764215955
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.4039561741
Short name T545
Test name
Test status
Simulation time 36401209 ps
CPU time 0.78 seconds
Started Jul 06 04:57:32 PM PDT 24
Finished Jul 06 04:57:33 PM PDT 24
Peak memory 192928 kb
Host smart-7417af5e-bff5-4acb-bbe1-ddf66ee051cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039561741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.4039561741
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1316863634
Short name T59
Test name
Test status
Simulation time 121585454 ps
CPU time 2.17 seconds
Started Jul 06 04:57:31 PM PDT 24
Finished Jul 06 04:57:34 PM PDT 24
Peak memory 197104 kb
Host smart-9558d0b6-1610-456a-b654-cb82f40253eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316863634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1316863634
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.757265798
Short name T535
Test name
Test status
Simulation time 240912220 ps
CPU time 1.07 seconds
Started Jul 06 04:57:31 PM PDT 24
Finished Jul 06 04:57:33 PM PDT 24
Peak memory 194520 kb
Host smart-25329165-4ee2-4488-9ff2-f943e016f26c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757265798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.757265798
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3554262113
Short name T476
Test name
Test status
Simulation time 21214808 ps
CPU time 0.95 seconds
Started Jul 06 04:57:33 PM PDT 24
Finished Jul 06 04:57:35 PM PDT 24
Peak memory 196964 kb
Host smart-1c1155ae-f1c5-4cc3-9d5e-8ee9b4716f43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554262113 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3554262113
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3368068102
Short name T511
Test name
Test status
Simulation time 11719498 ps
CPU time 0.56 seconds
Started Jul 06 04:57:33 PM PDT 24
Finished Jul 06 04:57:34 PM PDT 24
Peak memory 182320 kb
Host smart-693a699e-4f74-4613-89df-71fb283eae25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368068102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3368068102
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2927973151
Short name T541
Test name
Test status
Simulation time 38076372 ps
CPU time 0.54 seconds
Started Jul 06 04:57:32 PM PDT 24
Finished Jul 06 04:57:33 PM PDT 24
Peak memory 182128 kb
Host smart-c2081ab1-88f4-4d3f-9302-b36417fac1a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927973151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2927973151
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.440066156
Short name T579
Test name
Test status
Simulation time 25726408 ps
CPU time 0.73 seconds
Started Jul 06 04:57:33 PM PDT 24
Finished Jul 06 04:57:34 PM PDT 24
Peak memory 192868 kb
Host smart-cf9afb55-1dd1-4785-98d8-a6943f35d006
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440066156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.440066156
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1853879109
Short name T543
Test name
Test status
Simulation time 244299186 ps
CPU time 2.48 seconds
Started Jul 06 04:57:31 PM PDT 24
Finished Jul 06 04:57:33 PM PDT 24
Peak memory 197080 kb
Host smart-1d8b9db6-8f0f-46a3-8458-b67d38de9740
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853879109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1853879109
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2466702178
Short name T500
Test name
Test status
Simulation time 330803285 ps
CPU time 1.06 seconds
Started Jul 06 04:57:33 PM PDT 24
Finished Jul 06 04:57:34 PM PDT 24
Peak memory 194688 kb
Host smart-cc5a91f1-6b4a-4a2b-bb7a-9bc869849b78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466702178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2466702178
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.353340516
Short name T512
Test name
Test status
Simulation time 154952343 ps
CPU time 1.02 seconds
Started Jul 06 04:57:38 PM PDT 24
Finished Jul 06 04:57:39 PM PDT 24
Peak memory 196860 kb
Host smart-a8baac3b-f9af-4027-88dd-55e13aeb7f2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353340516 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.353340516
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2482100791
Short name T539
Test name
Test status
Simulation time 39545122 ps
CPU time 0.55 seconds
Started Jul 06 04:57:37 PM PDT 24
Finished Jul 06 04:57:38 PM PDT 24
Peak memory 182240 kb
Host smart-4581b114-f9a5-4a7b-b81c-a90cf70688c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482100791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2482100791
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.352327200
Short name T527
Test name
Test status
Simulation time 59031643 ps
CPU time 0.7 seconds
Started Jul 06 04:57:39 PM PDT 24
Finished Jul 06 04:57:40 PM PDT 24
Peak memory 192868 kb
Host smart-265ae7c9-8931-4fd0-9e89-ba904805f1d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352327200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_ti
mer_same_csr_outstanding.352327200
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3467529015
Short name T523
Test name
Test status
Simulation time 117364394 ps
CPU time 2.31 seconds
Started Jul 06 04:57:31 PM PDT 24
Finished Jul 06 04:57:34 PM PDT 24
Peak memory 197084 kb
Host smart-4088fb23-13e0-4e0a-905f-7a1734c75feb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467529015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3467529015
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2469142417
Short name T112
Test name
Test status
Simulation time 213506384 ps
CPU time 1.44 seconds
Started Jul 06 04:57:31 PM PDT 24
Finished Jul 06 04:57:33 PM PDT 24
Peak memory 194548 kb
Host smart-3503b835-f4da-4da2-9127-0827d75aa99b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469142417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2469142417
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.900172011
Short name T526
Test name
Test status
Simulation time 15288496 ps
CPU time 0.62 seconds
Started Jul 06 04:57:38 PM PDT 24
Finished Jul 06 04:57:40 PM PDT 24
Peak memory 193096 kb
Host smart-8c6e7111-15e3-4533-8743-fb6f4d39c699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900172011 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.900172011
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.4170472824
Short name T516
Test name
Test status
Simulation time 148146624 ps
CPU time 0.58 seconds
Started Jul 06 04:57:41 PM PDT 24
Finished Jul 06 04:57:42 PM PDT 24
Peak memory 182344 kb
Host smart-820203b7-8d91-4666-a860-c5bf9b94fcbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170472824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.4170472824
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.136478589
Short name T457
Test name
Test status
Simulation time 37060400 ps
CPU time 0.55 seconds
Started Jul 06 04:57:38 PM PDT 24
Finished Jul 06 04:57:39 PM PDT 24
Peak memory 182116 kb
Host smart-f52c90fe-1184-4af9-9c0b-be5bd5bbd46d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136478589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.136478589
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.976402233
Short name T533
Test name
Test status
Simulation time 19459227 ps
CPU time 0.78 seconds
Started Jul 06 04:57:38 PM PDT 24
Finished Jul 06 04:57:39 PM PDT 24
Peak memory 193148 kb
Host smart-d7b543dc-7273-4652-ab7d-595f8a703e10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976402233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.976402233
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2891487297
Short name T549
Test name
Test status
Simulation time 192702815 ps
CPU time 2.92 seconds
Started Jul 06 04:57:41 PM PDT 24
Finished Jul 06 04:57:44 PM PDT 24
Peak memory 197072 kb
Host smart-a1678ca8-594c-42be-806e-e7b877a3c841
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891487297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2891487297
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2633416846
Short name T28
Test name
Test status
Simulation time 66976669 ps
CPU time 1.06 seconds
Started Jul 06 04:57:39 PM PDT 24
Finished Jul 06 04:57:40 PM PDT 24
Peak memory 194596 kb
Host smart-c651ef79-024b-40c8-ade6-c85b44fa598e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633416846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2633416846
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3333256147
Short name T505
Test name
Test status
Simulation time 27903817 ps
CPU time 1.25 seconds
Started Jul 06 04:57:38 PM PDT 24
Finished Jul 06 04:57:40 PM PDT 24
Peak memory 197072 kb
Host smart-f6950c62-48bf-4e29-965c-9d66bc579ab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333256147 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3333256147
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.3056183772
Short name T464
Test name
Test status
Simulation time 11636040 ps
CPU time 0.57 seconds
Started Jul 06 04:57:40 PM PDT 24
Finished Jul 06 04:57:41 PM PDT 24
Peak memory 182284 kb
Host smart-6c7f63ff-47e6-437a-a660-a39962bac570
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056183772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.3056183772
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.860399103
Short name T498
Test name
Test status
Simulation time 16260603 ps
CPU time 0.56 seconds
Started Jul 06 04:57:39 PM PDT 24
Finished Jul 06 04:57:40 PM PDT 24
Peak memory 182184 kb
Host smart-792b5972-f830-4c4e-a7af-98b65af70125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860399103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.860399103
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2090805763
Short name T74
Test name
Test status
Simulation time 72320759 ps
CPU time 0.78 seconds
Started Jul 06 04:57:38 PM PDT 24
Finished Jul 06 04:57:39 PM PDT 24
Peak memory 191256 kb
Host smart-06301d21-0c91-432b-9403-252eda48c156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090805763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2090805763
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2435007424
Short name T562
Test name
Test status
Simulation time 235661322 ps
CPU time 2.33 seconds
Started Jul 06 04:57:39 PM PDT 24
Finished Jul 06 04:57:42 PM PDT 24
Peak memory 197032 kb
Host smart-b47125cb-7df6-4306-9228-7ed4c6dbbc15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435007424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2435007424
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3842709871
Short name T488
Test name
Test status
Simulation time 83918147 ps
CPU time 0.83 seconds
Started Jul 06 04:57:37 PM PDT 24
Finished Jul 06 04:57:39 PM PDT 24
Peak memory 193044 kb
Host smart-f8736f9f-e2b7-4a48-8f7b-ede9845aa8cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842709871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3842709871
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3354514607
Short name T454
Test name
Test status
Simulation time 148518192 ps
CPU time 0.82 seconds
Started Jul 06 04:57:43 PM PDT 24
Finished Jul 06 04:57:44 PM PDT 24
Peak memory 196656 kb
Host smart-1e162be9-0c12-4c56-8cc0-025214d21564
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354514607 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3354514607
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3513387842
Short name T490
Test name
Test status
Simulation time 15450733 ps
CPU time 0.59 seconds
Started Jul 06 04:57:37 PM PDT 24
Finished Jul 06 04:57:38 PM PDT 24
Peak memory 182264 kb
Host smart-af742bbf-e7e9-4201-98c7-64594b55a3ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513387842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3513387842
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4002169313
Short name T479
Test name
Test status
Simulation time 14411412 ps
CPU time 0.56 seconds
Started Jul 06 04:57:38 PM PDT 24
Finished Jul 06 04:57:39 PM PDT 24
Peak memory 181844 kb
Host smart-cd47c3c7-0f63-47c6-a9ea-62d89e6eadec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002169313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.4002169313
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1420606344
Short name T542
Test name
Test status
Simulation time 59055864 ps
CPU time 0.71 seconds
Started Jul 06 04:57:38 PM PDT 24
Finished Jul 06 04:57:40 PM PDT 24
Peak memory 192856 kb
Host smart-a079254a-58db-4d91-b59b-d1eb78b8f6bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420606344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1420606344
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1371605762
Short name T569
Test name
Test status
Simulation time 134936455 ps
CPU time 2.31 seconds
Started Jul 06 04:57:42 PM PDT 24
Finished Jul 06 04:57:44 PM PDT 24
Peak memory 197088 kb
Host smart-9496b822-f348-42dc-b5c9-bf6da4fe2b15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371605762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1371605762
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.4023124114
Short name T555
Test name
Test status
Simulation time 74898998 ps
CPU time 1.08 seconds
Started Jul 06 04:57:39 PM PDT 24
Finished Jul 06 04:57:40 PM PDT 24
Peak memory 182692 kb
Host smart-363bab5c-0730-4317-9db7-1f415b766a5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023124114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.4023124114
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4020728854
Short name T60
Test name
Test status
Simulation time 19653487 ps
CPU time 0.65 seconds
Started Jul 06 04:57:43 PM PDT 24
Finished Jul 06 04:57:44 PM PDT 24
Peak memory 193656 kb
Host smart-19f702a3-18c8-42b8-b0e8-10278e105aff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020728854 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4020728854
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.946742303
Short name T93
Test name
Test status
Simulation time 36741475 ps
CPU time 0.56 seconds
Started Jul 06 04:57:45 PM PDT 24
Finished Jul 06 04:57:46 PM PDT 24
Peak memory 182240 kb
Host smart-43ee84c5-30e4-4c80-aa1f-3c3bc8946794
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946742303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.946742303
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2819294381
Short name T517
Test name
Test status
Simulation time 21466501 ps
CPU time 0.54 seconds
Started Jul 06 04:57:42 PM PDT 24
Finished Jul 06 04:57:43 PM PDT 24
Peak memory 181664 kb
Host smart-a4427a6a-f426-48a4-88ab-3d0e07805b79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819294381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2819294381
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2431129900
Short name T95
Test name
Test status
Simulation time 56340006 ps
CPU time 0.76 seconds
Started Jul 06 04:57:45 PM PDT 24
Finished Jul 06 04:57:46 PM PDT 24
Peak memory 191204 kb
Host smart-721c714e-e064-4391-8c7f-7a88d9930a24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431129900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2431129900
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1022968732
Short name T452
Test name
Test status
Simulation time 29347015 ps
CPU time 1.23 seconds
Started Jul 06 04:57:45 PM PDT 24
Finished Jul 06 04:57:46 PM PDT 24
Peak memory 196840 kb
Host smart-42297cc9-af05-449a-8867-c0f0a959e3a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022968732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1022968732
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1921097812
Short name T513
Test name
Test status
Simulation time 117985253 ps
CPU time 1.4 seconds
Started Jul 06 04:57:42 PM PDT 24
Finished Jul 06 04:57:44 PM PDT 24
Peak memory 193904 kb
Host smart-f0422ca1-2bad-4f85-ad96-9ddcb2e20d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921097812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1921097812
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.92477588
Short name T88
Test name
Test status
Simulation time 42476008 ps
CPU time 0.72 seconds
Started Jul 06 04:57:02 PM PDT 24
Finished Jul 06 04:57:03 PM PDT 24
Peak memory 191548 kb
Host smart-24bb8b60-9ab5-4ab0-b7b5-0ad5b7d42983
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92477588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_aliasi
ng.92477588
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3244617457
Short name T575
Test name
Test status
Simulation time 745131062 ps
CPU time 2.48 seconds
Started Jul 06 04:57:01 PM PDT 24
Finished Jul 06 04:57:04 PM PDT 24
Peak memory 190640 kb
Host smart-ec5d3e3a-2729-4f5a-bbb1-3981ba80d03d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244617457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3244617457
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.679919468
Short name T570
Test name
Test status
Simulation time 46792697 ps
CPU time 0.58 seconds
Started Jul 06 04:56:55 PM PDT 24
Finished Jul 06 04:56:56 PM PDT 24
Peak memory 182208 kb
Host smart-be0f06ab-5693-48df-8295-b369c9d34821
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679919468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.679919468
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.266232006
Short name T459
Test name
Test status
Simulation time 93893695 ps
CPU time 1.15 seconds
Started Jul 06 04:57:00 PM PDT 24
Finished Jul 06 04:57:02 PM PDT 24
Peak memory 197100 kb
Host smart-dc76a2b1-f008-4990-84a6-e5a9543d0023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266232006 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.266232006
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3902707043
Short name T532
Test name
Test status
Simulation time 25669721 ps
CPU time 0.59 seconds
Started Jul 06 04:57:00 PM PDT 24
Finished Jul 06 04:57:02 PM PDT 24
Peak memory 182312 kb
Host smart-77246680-b4a1-4489-808b-7cf677acddc3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902707043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3902707043
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.54200379
Short name T482
Test name
Test status
Simulation time 21296236 ps
CPU time 0.53 seconds
Started Jul 06 04:56:54 PM PDT 24
Finished Jul 06 04:56:55 PM PDT 24
Peak memory 182116 kb
Host smart-7d03c73f-3fdd-4cb5-8907-07867db20046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54200379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.54200379
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1123299175
Short name T97
Test name
Test status
Simulation time 15551911 ps
CPU time 0.72 seconds
Started Jul 06 04:57:04 PM PDT 24
Finished Jul 06 04:57:05 PM PDT 24
Peak memory 192560 kb
Host smart-a8ae9013-21c3-46ee-a700-a57ecc02b10e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123299175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1123299175
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3524128432
Short name T483
Test name
Test status
Simulation time 586752310 ps
CPU time 2.55 seconds
Started Jul 06 04:56:54 PM PDT 24
Finished Jul 06 04:56:57 PM PDT 24
Peak memory 197068 kb
Host smart-3060f93d-7075-4660-b3ea-a4272be019ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524128432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3524128432
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2771500591
Short name T501
Test name
Test status
Simulation time 307561211 ps
CPU time 1.02 seconds
Started Jul 06 04:56:57 PM PDT 24
Finished Jul 06 04:56:58 PM PDT 24
Peak memory 182888 kb
Host smart-f520c05a-dfb3-471a-ba38-aebe600a0582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771500591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2771500591
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3038385463
Short name T519
Test name
Test status
Simulation time 23229623 ps
CPU time 0.53 seconds
Started Jul 06 04:57:44 PM PDT 24
Finished Jul 06 04:57:45 PM PDT 24
Peak memory 182248 kb
Host smart-d6a4bfd5-a037-433d-ae97-6b16c2f7bb8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038385463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3038385463
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2176423643
Short name T540
Test name
Test status
Simulation time 14112571 ps
CPU time 0.57 seconds
Started Jul 06 04:57:45 PM PDT 24
Finished Jul 06 04:57:46 PM PDT 24
Peak memory 182192 kb
Host smart-3efe8639-4c3a-4a5e-8c6b-3471c223da85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176423643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2176423643
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3570976319
Short name T528
Test name
Test status
Simulation time 36524825 ps
CPU time 0.53 seconds
Started Jul 06 04:57:44 PM PDT 24
Finished Jul 06 04:57:45 PM PDT 24
Peak memory 181632 kb
Host smart-9387c521-787c-4bb1-b2cf-f9ebcb0194a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570976319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3570976319
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2915996212
Short name T573
Test name
Test status
Simulation time 160087262 ps
CPU time 0.54 seconds
Started Jul 06 04:57:49 PM PDT 24
Finished Jul 06 04:57:50 PM PDT 24
Peak memory 181620 kb
Host smart-70a1589b-3c86-4987-aa41-028f3f903d21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915996212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2915996212
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1735401691
Short name T510
Test name
Test status
Simulation time 42385725 ps
CPU time 0.57 seconds
Started Jul 06 04:57:43 PM PDT 24
Finished Jul 06 04:57:44 PM PDT 24
Peak memory 182108 kb
Host smart-9a3790f0-68a0-4492-8b78-c8a9cae89fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735401691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1735401691
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.180772577
Short name T507
Test name
Test status
Simulation time 43920094 ps
CPU time 0.55 seconds
Started Jul 06 04:57:46 PM PDT 24
Finished Jul 06 04:57:47 PM PDT 24
Peak memory 181692 kb
Host smart-708cd4cf-7c5f-4135-8a96-5e896a6a1164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180772577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.180772577
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2947286742
Short name T551
Test name
Test status
Simulation time 25432506 ps
CPU time 0.61 seconds
Started Jul 06 04:57:44 PM PDT 24
Finished Jul 06 04:57:45 PM PDT 24
Peak memory 182200 kb
Host smart-a24750c4-e871-4ea0-92c5-a0981045876c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947286742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2947286742
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3319436392
Short name T481
Test name
Test status
Simulation time 36730256 ps
CPU time 0.53 seconds
Started Jul 06 04:57:42 PM PDT 24
Finished Jul 06 04:57:43 PM PDT 24
Peak memory 181808 kb
Host smart-0726b07d-0497-44ba-9010-6d59f550810b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319436392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3319436392
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1856860191
Short name T475
Test name
Test status
Simulation time 16716734 ps
CPU time 0.52 seconds
Started Jul 06 04:57:42 PM PDT 24
Finished Jul 06 04:57:43 PM PDT 24
Peak memory 181904 kb
Host smart-8a126538-c3bf-4049-a7fb-4c1646b7e8eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856860191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1856860191
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2017996632
Short name T462
Test name
Test status
Simulation time 222297513 ps
CPU time 0.52 seconds
Started Jul 06 04:57:45 PM PDT 24
Finished Jul 06 04:57:46 PM PDT 24
Peak memory 182248 kb
Host smart-156342e5-680b-4c95-a941-e486e9da179b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017996632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2017996632
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.191474621
Short name T502
Test name
Test status
Simulation time 109007955 ps
CPU time 0.72 seconds
Started Jul 06 04:57:08 PM PDT 24
Finished Jul 06 04:57:09 PM PDT 24
Peak memory 192028 kb
Host smart-3b624f36-0e15-4c96-a60e-002c9568ccc4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191474621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.191474621
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3033288500
Short name T92
Test name
Test status
Simulation time 280730861 ps
CPU time 1.56 seconds
Started Jul 06 04:57:06 PM PDT 24
Finished Jul 06 04:57:07 PM PDT 24
Peak memory 182444 kb
Host smart-f253e803-89f9-481d-89d8-48724bf8c473
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033288500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3033288500
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3801065881
Short name T509
Test name
Test status
Simulation time 16346189 ps
CPU time 0.63 seconds
Started Jul 06 04:57:01 PM PDT 24
Finished Jul 06 04:57:02 PM PDT 24
Peak memory 182264 kb
Host smart-53b451fe-3a9a-4863-9c34-ab5b9efa7781
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801065881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3801065881
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4166313452
Short name T524
Test name
Test status
Simulation time 32450734 ps
CPU time 0.71 seconds
Started Jul 06 04:57:09 PM PDT 24
Finished Jul 06 04:57:10 PM PDT 24
Peak memory 194656 kb
Host smart-ecfa1ee5-7c49-419a-9d77-8940c4962777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166313452 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.4166313452
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.839920827
Short name T89
Test name
Test status
Simulation time 18102234 ps
CPU time 0.58 seconds
Started Jul 06 04:57:06 PM PDT 24
Finished Jul 06 04:57:07 PM PDT 24
Peak memory 182228 kb
Host smart-825f6464-2e5c-49b1-87e4-3a8ac792a983
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839920827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.839920827
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1094888241
Short name T556
Test name
Test status
Simulation time 36167818 ps
CPU time 0.59 seconds
Started Jul 06 04:57:03 PM PDT 24
Finished Jul 06 04:57:04 PM PDT 24
Peak memory 182156 kb
Host smart-cb8fc69e-a564-4fae-a5e6-9aef03b8d289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094888241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1094888241
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3028037707
Short name T560
Test name
Test status
Simulation time 76800176 ps
CPU time 0.68 seconds
Started Jul 06 04:57:07 PM PDT 24
Finished Jul 06 04:57:08 PM PDT 24
Peak memory 191516 kb
Host smart-e1444cf2-859e-4658-8295-2eab557af62f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028037707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3028037707
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.487523943
Short name T496
Test name
Test status
Simulation time 702994201 ps
CPU time 2.45 seconds
Started Jul 06 04:57:01 PM PDT 24
Finished Jul 06 04:57:04 PM PDT 24
Peak memory 190680 kb
Host smart-dbef12b4-d49c-431f-a5a9-763a449b34fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487523943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.487523943
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2736270455
Short name T552
Test name
Test status
Simulation time 239808049 ps
CPU time 0.81 seconds
Started Jul 06 04:57:00 PM PDT 24
Finished Jul 06 04:57:02 PM PDT 24
Peak memory 182508 kb
Host smart-57b58e36-6774-42e2-a068-ca6270f3e838
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736270455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2736270455
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.713239990
Short name T470
Test name
Test status
Simulation time 16075088 ps
CPU time 0.61 seconds
Started Jul 06 04:57:43 PM PDT 24
Finished Jul 06 04:57:44 PM PDT 24
Peak memory 182168 kb
Host smart-5ea39dc0-ac1c-4167-817a-04d78cb13bcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713239990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.713239990
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1474270676
Short name T460
Test name
Test status
Simulation time 16535021 ps
CPU time 0.55 seconds
Started Jul 06 04:57:42 PM PDT 24
Finished Jul 06 04:57:43 PM PDT 24
Peak memory 182208 kb
Host smart-082f4d95-c5c0-4a7d-a6ff-2f4c47d41942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474270676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1474270676
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.4256327891
Short name T489
Test name
Test status
Simulation time 15667771 ps
CPU time 0.55 seconds
Started Jul 06 04:57:44 PM PDT 24
Finished Jul 06 04:57:45 PM PDT 24
Peak memory 182140 kb
Host smart-d4dd120d-877a-4fdc-ae61-f9dcf173ebaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256327891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.4256327891
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3565667567
Short name T531
Test name
Test status
Simulation time 49669569 ps
CPU time 0.54 seconds
Started Jul 06 04:57:45 PM PDT 24
Finished Jul 06 04:57:46 PM PDT 24
Peak memory 182168 kb
Host smart-f824fbd7-e56a-43c7-b76d-938eddf08356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565667567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3565667567
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.537531966
Short name T536
Test name
Test status
Simulation time 23705563 ps
CPU time 0.53 seconds
Started Jul 06 04:57:43 PM PDT 24
Finished Jul 06 04:57:44 PM PDT 24
Peak memory 181652 kb
Host smart-45bc9060-520e-4420-adfa-d28f0c47675c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537531966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.537531966
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.413847632
Short name T506
Test name
Test status
Simulation time 41169565 ps
CPU time 0.56 seconds
Started Jul 06 04:57:45 PM PDT 24
Finished Jul 06 04:57:46 PM PDT 24
Peak memory 182228 kb
Host smart-a7c3c90a-34b8-4764-8fa6-4c8971eb7930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413847632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.413847632
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.555796504
Short name T515
Test name
Test status
Simulation time 66531789 ps
CPU time 0.56 seconds
Started Jul 06 04:57:44 PM PDT 24
Finished Jul 06 04:57:45 PM PDT 24
Peak memory 182164 kb
Host smart-c85acd44-0129-4f61-ab0b-7779f438aa9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555796504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.555796504
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.4151577072
Short name T478
Test name
Test status
Simulation time 15734254 ps
CPU time 0.56 seconds
Started Jul 06 04:57:49 PM PDT 24
Finished Jul 06 04:57:50 PM PDT 24
Peak memory 182076 kb
Host smart-65547923-233b-4a11-8d76-d04e66f6496c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151577072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.4151577072
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.408408869
Short name T463
Test name
Test status
Simulation time 37458775 ps
CPU time 0.53 seconds
Started Jul 06 04:57:49 PM PDT 24
Finished Jul 06 04:57:50 PM PDT 24
Peak memory 181688 kb
Host smart-bcab22db-a7c3-4686-9bb5-15fcddd59bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408408869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.408408869
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3252490612
Short name T499
Test name
Test status
Simulation time 17643231 ps
CPU time 0.53 seconds
Started Jul 06 04:57:50 PM PDT 24
Finished Jul 06 04:57:51 PM PDT 24
Peak memory 181640 kb
Host smart-1cd7e2c7-017a-44ca-b373-6d660eeca6bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252490612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3252490612
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3518300754
Short name T31
Test name
Test status
Simulation time 228170266 ps
CPU time 0.63 seconds
Started Jul 06 04:57:08 PM PDT 24
Finished Jul 06 04:57:09 PM PDT 24
Peak memory 191448 kb
Host smart-887e6d47-3624-47e8-94a2-cb94ed925dc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518300754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3518300754
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.394852146
Short name T571
Test name
Test status
Simulation time 478102466 ps
CPU time 2.31 seconds
Started Jul 06 04:57:06 PM PDT 24
Finished Jul 06 04:57:09 PM PDT 24
Peak memory 190564 kb
Host smart-cf0d1dca-853b-4830-9fc4-909605322973
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394852146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.394852146
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.3938433955
Short name T559
Test name
Test status
Simulation time 21435926 ps
CPU time 0.52 seconds
Started Jul 06 04:57:08 PM PDT 24
Finished Jul 06 04:57:09 PM PDT 24
Peak memory 181820 kb
Host smart-c1ae4b8e-4e90-4541-b2c9-41ceb7ca26e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938433955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.3938433955
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1001489344
Short name T473
Test name
Test status
Simulation time 67197224 ps
CPU time 0.92 seconds
Started Jul 06 04:57:06 PM PDT 24
Finished Jul 06 04:57:07 PM PDT 24
Peak memory 196796 kb
Host smart-a1f957b8-dd70-4dfc-b398-88c89d6ecca6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001489344 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1001489344
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2430546361
Short name T484
Test name
Test status
Simulation time 48886295 ps
CPU time 0.56 seconds
Started Jul 06 04:57:05 PM PDT 24
Finished Jul 06 04:57:06 PM PDT 24
Peak memory 182288 kb
Host smart-26a9a160-bd17-4969-9ef5-49bb0cb1b4ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430546361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2430546361
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2338881221
Short name T567
Test name
Test status
Simulation time 14063255 ps
CPU time 0.53 seconds
Started Jul 06 04:57:06 PM PDT 24
Finished Jul 06 04:57:07 PM PDT 24
Peak memory 181624 kb
Host smart-d6bbd80e-fd54-490b-9f23-8bc3008ba9dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338881221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2338881221
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3883101446
Short name T94
Test name
Test status
Simulation time 91602704 ps
CPU time 0.7 seconds
Started Jul 06 04:57:08 PM PDT 24
Finished Jul 06 04:57:09 PM PDT 24
Peak memory 191260 kb
Host smart-45aba56b-078d-4c1a-aadb-12b79816e55d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883101446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3883101446
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4007502830
Short name T538
Test name
Test status
Simulation time 566420752 ps
CPU time 2.54 seconds
Started Jul 06 04:57:05 PM PDT 24
Finished Jul 06 04:57:08 PM PDT 24
Peak memory 197064 kb
Host smart-269ac9b0-ccef-4a14-8765-d953ea6a41aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007502830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.4007502830
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.203859480
Short name T485
Test name
Test status
Simulation time 14580088 ps
CPU time 0.55 seconds
Started Jul 06 04:57:50 PM PDT 24
Finished Jul 06 04:57:51 PM PDT 24
Peak memory 181576 kb
Host smart-d9af2ff6-ce41-4270-bd9d-c60cb365ac50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203859480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.203859480
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3089073996
Short name T461
Test name
Test status
Simulation time 12628633 ps
CPU time 0.54 seconds
Started Jul 06 04:57:49 PM PDT 24
Finished Jul 06 04:57:50 PM PDT 24
Peak memory 182216 kb
Host smart-87548f45-91de-45e9-b312-3d6012255189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089073996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3089073996
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.339253793
Short name T468
Test name
Test status
Simulation time 13527680 ps
CPU time 0.57 seconds
Started Jul 06 04:57:49 PM PDT 24
Finished Jul 06 04:57:50 PM PDT 24
Peak memory 181824 kb
Host smart-ff73931d-c20a-4dbd-9e47-4e228fc40ccd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339253793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.339253793
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3414928809
Short name T453
Test name
Test status
Simulation time 71238720 ps
CPU time 0.54 seconds
Started Jul 06 04:57:52 PM PDT 24
Finished Jul 06 04:57:53 PM PDT 24
Peak memory 182152 kb
Host smart-99fc36f8-e387-4c9b-9a8d-533c4eeeb055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414928809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3414928809
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4229403960
Short name T466
Test name
Test status
Simulation time 66378925 ps
CPU time 0.59 seconds
Started Jul 06 04:57:49 PM PDT 24
Finished Jul 06 04:57:50 PM PDT 24
Peak memory 182268 kb
Host smart-0e9053ef-b7d5-4d97-aba6-1fa16780b1ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229403960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4229403960
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.744881193
Short name T497
Test name
Test status
Simulation time 103005578 ps
CPU time 0.59 seconds
Started Jul 06 04:57:51 PM PDT 24
Finished Jul 06 04:57:52 PM PDT 24
Peak memory 182256 kb
Host smart-0d7ba887-2b57-4eb7-b773-6bc4c2e8bcc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744881193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.744881193
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3040810439
Short name T469
Test name
Test status
Simulation time 22888430 ps
CPU time 0.55 seconds
Started Jul 06 04:57:51 PM PDT 24
Finished Jul 06 04:57:52 PM PDT 24
Peak memory 182152 kb
Host smart-0daf211c-80d8-4226-93f0-83e642185a12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040810439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3040810439
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2755584290
Short name T521
Test name
Test status
Simulation time 16231137 ps
CPU time 0.55 seconds
Started Jul 06 04:57:51 PM PDT 24
Finished Jul 06 04:57:51 PM PDT 24
Peak memory 182212 kb
Host smart-7b13cb8c-ce8d-4497-b9c7-528d56ac2add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755584290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2755584290
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.2392044086
Short name T554
Test name
Test status
Simulation time 45114325 ps
CPU time 0.57 seconds
Started Jul 06 04:57:56 PM PDT 24
Finished Jul 06 04:57:56 PM PDT 24
Peak memory 182136 kb
Host smart-acf5d9be-b609-4380-8205-1f8616f3efba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392044086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.2392044086
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.923148551
Short name T480
Test name
Test status
Simulation time 17961685 ps
CPU time 0.54 seconds
Started Jul 06 04:57:56 PM PDT 24
Finished Jul 06 04:57:57 PM PDT 24
Peak memory 181604 kb
Host smart-314ab4f3-145e-482b-aee3-8523ce3afc61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923148551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.923148551
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.311344981
Short name T45
Test name
Test status
Simulation time 122934595 ps
CPU time 0.83 seconds
Started Jul 06 04:57:14 PM PDT 24
Finished Jul 06 04:57:15 PM PDT 24
Peak memory 195060 kb
Host smart-b7b2864d-3864-47cd-8929-54592a0c5748
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311344981 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.311344981
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2553513162
Short name T91
Test name
Test status
Simulation time 34838717 ps
CPU time 0.58 seconds
Started Jul 06 04:57:09 PM PDT 24
Finished Jul 06 04:57:10 PM PDT 24
Peak memory 182328 kb
Host smart-abadb613-e3d7-4c23-9a9c-5a4b4cc27830
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553513162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2553513162
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1491516210
Short name T474
Test name
Test status
Simulation time 12889235 ps
CPU time 0.52 seconds
Started Jul 06 04:57:06 PM PDT 24
Finished Jul 06 04:57:07 PM PDT 24
Peak memory 181640 kb
Host smart-4bb2e738-92bf-4857-a6f8-5bbc6a1c2ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491516210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1491516210
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2494395231
Short name T568
Test name
Test status
Simulation time 18571752 ps
CPU time 0.6 seconds
Started Jul 06 04:57:12 PM PDT 24
Finished Jul 06 04:57:13 PM PDT 24
Peak memory 191564 kb
Host smart-39ff3970-86d9-4193-a337-626f37b9e473
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494395231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2494395231
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4040863943
Short name T558
Test name
Test status
Simulation time 91732918 ps
CPU time 2.48 seconds
Started Jul 06 04:57:06 PM PDT 24
Finished Jul 06 04:57:09 PM PDT 24
Peak memory 197096 kb
Host smart-88fdc65c-85c7-4cc0-b268-765c107e00c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040863943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4040863943
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2865710924
Short name T48
Test name
Test status
Simulation time 261563796 ps
CPU time 1.35 seconds
Started Jul 06 04:57:07 PM PDT 24
Finished Jul 06 04:57:09 PM PDT 24
Peak memory 195072 kb
Host smart-621405db-6da7-4d9d-8720-43330580700b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865710924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2865710924
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3016347949
Short name T574
Test name
Test status
Simulation time 25699531 ps
CPU time 1.12 seconds
Started Jul 06 04:57:13 PM PDT 24
Finished Jul 06 04:57:15 PM PDT 24
Peak memory 197052 kb
Host smart-efb69c0a-4d70-4c10-bb1c-08f76259d0b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016347949 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3016347949
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1877718015
Short name T472
Test name
Test status
Simulation time 43791990 ps
CPU time 0.57 seconds
Started Jul 06 04:57:13 PM PDT 24
Finished Jul 06 04:57:14 PM PDT 24
Peak memory 182268 kb
Host smart-860e4502-a0ca-499a-b7b8-d124c8b4cddb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877718015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1877718015
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3170903419
Short name T544
Test name
Test status
Simulation time 19602051 ps
CPU time 0.55 seconds
Started Jul 06 04:57:13 PM PDT 24
Finished Jul 06 04:57:14 PM PDT 24
Peak memory 181888 kb
Host smart-64739d5f-78e6-4dba-a4c1-59279851f7dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170903419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3170903419
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.1969307006
Short name T534
Test name
Test status
Simulation time 100972943 ps
CPU time 0.72 seconds
Started Jul 06 04:57:13 PM PDT 24
Finished Jul 06 04:57:14 PM PDT 24
Peak memory 191272 kb
Host smart-1c3ad580-f064-46f9-a171-57c86255625d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969307006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.1969307006
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1438158897
Short name T565
Test name
Test status
Simulation time 52055415 ps
CPU time 1.14 seconds
Started Jul 06 04:57:11 PM PDT 24
Finished Jul 06 04:57:12 PM PDT 24
Peak memory 196636 kb
Host smart-78e492f3-0ee2-4518-97e0-8d88f34b4a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438158897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1438158897
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.202637178
Short name T111
Test name
Test status
Simulation time 546992513 ps
CPU time 1.39 seconds
Started Jul 06 04:57:15 PM PDT 24
Finished Jul 06 04:57:17 PM PDT 24
Peak memory 194940 kb
Host smart-fbd63ae6-17c3-4bae-9f06-b107e32d3386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202637178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.202637178
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3162317563
Short name T503
Test name
Test status
Simulation time 80074791 ps
CPU time 0.74 seconds
Started Jul 06 04:57:19 PM PDT 24
Finished Jul 06 04:57:21 PM PDT 24
Peak memory 193956 kb
Host smart-c330e126-64f4-4350-9e11-c805e5477211
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162317563 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3162317563
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2358261915
Short name T90
Test name
Test status
Simulation time 14248822 ps
CPU time 0.54 seconds
Started Jul 06 04:57:19 PM PDT 24
Finished Jul 06 04:57:20 PM PDT 24
Peak memory 182296 kb
Host smart-be5450e5-9d2f-49aa-9614-b940447009d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358261915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2358261915
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1787252512
Short name T576
Test name
Test status
Simulation time 40590567 ps
CPU time 0.54 seconds
Started Jul 06 04:57:18 PM PDT 24
Finished Jul 06 04:57:19 PM PDT 24
Peak memory 182208 kb
Host smart-be4c3a1c-7467-4735-8970-c20f02633580
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787252512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1787252512
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3193222100
Short name T530
Test name
Test status
Simulation time 33207774 ps
CPU time 0.7 seconds
Started Jul 06 04:57:19 PM PDT 24
Finished Jul 06 04:57:20 PM PDT 24
Peak memory 191780 kb
Host smart-6a980aae-da04-467d-9ee4-8c6f5ca04f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193222100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3193222100
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4116043097
Short name T491
Test name
Test status
Simulation time 85619321 ps
CPU time 1.74 seconds
Started Jul 06 04:57:19 PM PDT 24
Finished Jul 06 04:57:21 PM PDT 24
Peak memory 197080 kb
Host smart-c2d8a5de-b632-461b-9926-dc4f6a3a0fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116043097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4116043097
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2472840548
Short name T547
Test name
Test status
Simulation time 118771354 ps
CPU time 1.06 seconds
Started Jul 06 04:57:20 PM PDT 24
Finished Jul 06 04:57:21 PM PDT 24
Peak memory 194768 kb
Host smart-f866fe77-139d-4cc7-85b3-7cb8f4e1af64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472840548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2472840548
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3166510047
Short name T561
Test name
Test status
Simulation time 158121531 ps
CPU time 0.85 seconds
Started Jul 06 04:57:25 PM PDT 24
Finished Jul 06 04:57:26 PM PDT 24
Peak memory 196064 kb
Host smart-fb4e15e3-e544-42fd-af3f-fbe192a4c119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166510047 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3166510047
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1734753203
Short name T508
Test name
Test status
Simulation time 44857597 ps
CPU time 0.53 seconds
Started Jul 06 04:57:18 PM PDT 24
Finished Jul 06 04:57:20 PM PDT 24
Peak memory 182172 kb
Host smart-8acb9904-ffab-4142-80c6-d37f658d818f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734753203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1734753203
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1225190616
Short name T455
Test name
Test status
Simulation time 11402711 ps
CPU time 0.61 seconds
Started Jul 06 04:57:18 PM PDT 24
Finished Jul 06 04:57:20 PM PDT 24
Peak memory 182168 kb
Host smart-0bdd0f96-6884-436b-a5c7-0aac9682c9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225190616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1225190616
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2080777944
Short name T548
Test name
Test status
Simulation time 20416660 ps
CPU time 0.67 seconds
Started Jul 06 04:57:18 PM PDT 24
Finished Jul 06 04:57:19 PM PDT 24
Peak memory 191488 kb
Host smart-d176bb29-3366-4be6-b119-28988b8524c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080777944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2080777944
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3444718685
Short name T529
Test name
Test status
Simulation time 26246541 ps
CPU time 1.17 seconds
Started Jul 06 04:57:21 PM PDT 24
Finished Jul 06 04:57:23 PM PDT 24
Peak memory 190676 kb
Host smart-06ae1dec-eeb4-4ddc-a2ec-94065ff67778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444718685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3444718685
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.221941111
Short name T578
Test name
Test status
Simulation time 535906910 ps
CPU time 1.1 seconds
Started Jul 06 04:57:19 PM PDT 24
Finished Jul 06 04:57:20 PM PDT 24
Peak memory 194808 kb
Host smart-c3738cc5-ebbc-43bf-9483-d02a66b10b50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221941111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.221941111
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2127502659
Short name T477
Test name
Test status
Simulation time 84037490 ps
CPU time 0.78 seconds
Started Jul 06 04:57:24 PM PDT 24
Finished Jul 06 04:57:25 PM PDT 24
Peak memory 195524 kb
Host smart-143aa787-5050-430a-abe3-9b7816c0eac5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127502659 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2127502659
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2330075098
Short name T504
Test name
Test status
Simulation time 24234237 ps
CPU time 0.61 seconds
Started Jul 06 04:57:32 PM PDT 24
Finished Jul 06 04:57:33 PM PDT 24
Peak memory 182328 kb
Host smart-bb1ce2ca-84ff-4fec-a574-31e0ec4975a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330075098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2330075098
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3191697450
Short name T557
Test name
Test status
Simulation time 13346362 ps
CPU time 0.56 seconds
Started Jul 06 04:57:26 PM PDT 24
Finished Jul 06 04:57:27 PM PDT 24
Peak memory 182192 kb
Host smart-7b3e9362-8f36-4f9c-9628-2b5a4c04f788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191697450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3191697450
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1034521549
Short name T76
Test name
Test status
Simulation time 195609819 ps
CPU time 0.69 seconds
Started Jul 06 04:57:24 PM PDT 24
Finished Jul 06 04:57:26 PM PDT 24
Peak memory 191268 kb
Host smart-a4eb389b-7ef5-4411-9a4a-09de4962a562
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034521549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1034521549
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1738670049
Short name T49
Test name
Test status
Simulation time 111472310 ps
CPU time 1.85 seconds
Started Jul 06 04:57:18 PM PDT 24
Finished Jul 06 04:57:20 PM PDT 24
Peak memory 197036 kb
Host smart-23863809-5476-4be0-b48d-20b87d33a69b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738670049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1738670049
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1520574370
Short name T546
Test name
Test status
Simulation time 476377650 ps
CPU time 1.36 seconds
Started Jul 06 04:57:19 PM PDT 24
Finished Jul 06 04:57:20 PM PDT 24
Peak memory 193984 kb
Host smart-bc48e2fa-e447-40e2-978c-52199efae502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520574370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1520574370
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.4235523709
Short name T137
Test name
Test status
Simulation time 486898722487 ps
CPU time 253.39 seconds
Started Jul 06 04:57:57 PM PDT 24
Finished Jul 06 05:02:11 PM PDT 24
Peak memory 183128 kb
Host smart-b53e169e-4ea9-4487-8574-fdd4b0fa7445
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235523709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.4235523709
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random.3048441846
Short name T442
Test name
Test status
Simulation time 17503536741 ps
CPU time 109.16 seconds
Started Jul 06 04:57:57 PM PDT 24
Finished Jul 06 04:59:47 PM PDT 24
Peak memory 183044 kb
Host smart-af5f5520-e8d0-4aa0-afdc-7afbf4b94d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048441846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3048441846
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.781307139
Short name T327
Test name
Test status
Simulation time 431881082122 ps
CPU time 1246.63 seconds
Started Jul 06 04:57:56 PM PDT 24
Finished Jul 06 05:18:44 PM PDT 24
Peak memory 194620 kb
Host smart-64470c0c-12b5-43ed-b3f8-64fef4485c0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781307139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.781307139
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1163711854
Short name T27
Test name
Test status
Simulation time 23701839118 ps
CPU time 23.86 seconds
Started Jul 06 04:57:56 PM PDT 24
Finished Jul 06 04:58:20 PM PDT 24
Peak memory 182960 kb
Host smart-155bbe52-e9de-42b2-bf9c-cec1148da5da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163711854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1163711854
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1291998317
Short name T82
Test name
Test status
Simulation time 79166785306 ps
CPU time 111.94 seconds
Started Jul 06 04:57:57 PM PDT 24
Finished Jul 06 04:59:50 PM PDT 24
Peak memory 183092 kb
Host smart-b7cbe4b4-25c5-4ee9-ab4d-b2cf1c851f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291998317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1291998317
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3817316541
Short name T291
Test name
Test status
Simulation time 58648379500 ps
CPU time 44.61 seconds
Started Jul 06 04:57:56 PM PDT 24
Finished Jul 06 04:58:41 PM PDT 24
Peak memory 182908 kb
Host smart-290f09e5-1a41-4565-8afe-6520d0c7153e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817316541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3817316541
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2856779797
Short name T248
Test name
Test status
Simulation time 44428900382 ps
CPU time 1568.5 seconds
Started Jul 06 04:57:56 PM PDT 24
Finished Jul 06 05:24:05 PM PDT 24
Peak memory 183120 kb
Host smart-87701ec0-a2bc-4910-b69a-8ed63d4d9e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856779797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2856779797
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2672549373
Short name T15
Test name
Test status
Simulation time 38486039 ps
CPU time 0.74 seconds
Started Jul 06 04:57:57 PM PDT 24
Finished Jul 06 04:57:58 PM PDT 24
Peak memory 213292 kb
Host smart-173374cb-9df8-4ee6-a4f9-d01faffd2204
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672549373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2672549373
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3447455195
Short name T318
Test name
Test status
Simulation time 26909303739 ps
CPU time 32 seconds
Started Jul 06 04:58:10 PM PDT 24
Finished Jul 06 04:58:42 PM PDT 24
Peak memory 183104 kb
Host smart-648ea495-aabf-4481-ba9a-081123de9e54
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447455195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3447455195
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.2598993321
Short name T407
Test name
Test status
Simulation time 94595765417 ps
CPU time 140.08 seconds
Started Jul 06 04:58:13 PM PDT 24
Finished Jul 06 05:00:33 PM PDT 24
Peak memory 183048 kb
Host smart-7d3ef167-6286-46a7-ae2c-851f6b13dab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598993321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.2598993321
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3282590737
Short name T411
Test name
Test status
Simulation time 25814243322 ps
CPU time 37.69 seconds
Started Jul 06 04:58:15 PM PDT 24
Finished Jul 06 04:58:53 PM PDT 24
Peak memory 191336 kb
Host smart-5945535c-34cd-4a1a-88b5-036ac4d2b329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282590737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3282590737
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.3682063891
Short name T37
Test name
Test status
Simulation time 55807634958 ps
CPU time 200.34 seconds
Started Jul 06 04:58:14 PM PDT 24
Finished Jul 06 05:01:34 PM PDT 24
Peak memory 197856 kb
Host smart-8d346ffe-1f89-4969-9685-c5d7bf77026d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682063891 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.3682063891
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.1651299976
Short name T241
Test name
Test status
Simulation time 65363512094 ps
CPU time 99.89 seconds
Started Jul 06 05:01:18 PM PDT 24
Finished Jul 06 05:02:58 PM PDT 24
Peak memory 191348 kb
Host smart-37f1e07f-3506-4e46-a437-b5e5c267675c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651299976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1651299976
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.4041013489
Short name T148
Test name
Test status
Simulation time 313825739439 ps
CPU time 1758.61 seconds
Started Jul 06 05:01:17 PM PDT 24
Finished Jul 06 05:30:36 PM PDT 24
Peak memory 191344 kb
Host smart-46f1e2ea-ca50-402e-a3d3-a3d3827ebde5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041013489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.4041013489
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3067042653
Short name T105
Test name
Test status
Simulation time 30950771280 ps
CPU time 260.67 seconds
Started Jul 06 05:01:18 PM PDT 24
Finished Jul 06 05:05:39 PM PDT 24
Peak memory 183108 kb
Host smart-420ca2af-5c72-4efb-bc37-bc2d58040858
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067042653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3067042653
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3691741081
Short name T141
Test name
Test status
Simulation time 45141319347 ps
CPU time 79.83 seconds
Started Jul 06 05:01:18 PM PDT 24
Finished Jul 06 05:02:38 PM PDT 24
Peak memory 191312 kb
Host smart-da187a36-c63e-4f72-afc0-da57c65e96aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691741081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3691741081
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3760683555
Short name T444
Test name
Test status
Simulation time 35863755950 ps
CPU time 49.43 seconds
Started Jul 06 05:01:23 PM PDT 24
Finished Jul 06 05:02:12 PM PDT 24
Peak memory 183044 kb
Host smart-6fcc1c6f-4bc2-4018-ad08-57efa3983b2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760683555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3760683555
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3849875579
Short name T281
Test name
Test status
Simulation time 233154583175 ps
CPU time 388.76 seconds
Started Jul 06 04:58:18 PM PDT 24
Finished Jul 06 05:04:47 PM PDT 24
Peak memory 183100 kb
Host smart-de18128a-29a8-4b07-8925-1f9a89029d65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849875579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3849875579
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1092642166
Short name T404
Test name
Test status
Simulation time 124243442297 ps
CPU time 196.93 seconds
Started Jul 06 04:58:22 PM PDT 24
Finished Jul 06 05:01:40 PM PDT 24
Peak memory 183148 kb
Host smart-c1f722a3-807c-42ea-978c-52fb43c76ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092642166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1092642166
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2892586388
Short name T205
Test name
Test status
Simulation time 173199184202 ps
CPU time 585.98 seconds
Started Jul 06 04:58:18 PM PDT 24
Finished Jul 06 05:08:04 PM PDT 24
Peak memory 191316 kb
Host smart-899ba209-ceb8-42cf-8324-2d145cb42ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892586388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2892586388
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.2998784469
Short name T158
Test name
Test status
Simulation time 193225182061 ps
CPU time 325.56 seconds
Started Jul 06 05:01:23 PM PDT 24
Finished Jul 06 05:06:49 PM PDT 24
Peak memory 194972 kb
Host smart-f21dc933-4af9-4f67-a6bc-bc8419130d33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998784469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2998784469
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2188264310
Short name T428
Test name
Test status
Simulation time 82632761650 ps
CPU time 400.44 seconds
Started Jul 06 05:01:22 PM PDT 24
Finished Jul 06 05:08:02 PM PDT 24
Peak memory 192972 kb
Host smart-7cb6d737-4036-4520-8a3a-f836c61284d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188264310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2188264310
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.4051934840
Short name T418
Test name
Test status
Simulation time 223115728576 ps
CPU time 2653.38 seconds
Started Jul 06 05:01:22 PM PDT 24
Finished Jul 06 05:45:36 PM PDT 24
Peak memory 191316 kb
Host smart-7473fe57-6d03-4eae-abbb-1fda19561d6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051934840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.4051934840
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2491387216
Short name T283
Test name
Test status
Simulation time 132420458641 ps
CPU time 822.57 seconds
Started Jul 06 05:01:23 PM PDT 24
Finished Jul 06 05:15:05 PM PDT 24
Peak memory 191320 kb
Host smart-240b306a-4ded-494b-a502-85c3d6e0f0f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491387216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2491387216
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.775768593
Short name T292
Test name
Test status
Simulation time 16926521896 ps
CPU time 26.93 seconds
Started Jul 06 05:01:21 PM PDT 24
Finished Jul 06 05:01:48 PM PDT 24
Peak memory 191284 kb
Host smart-34a36d75-7fd8-4487-a305-efd660ef6241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775768593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.775768593
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.4129841011
Short name T350
Test name
Test status
Simulation time 569519071403 ps
CPU time 324.59 seconds
Started Jul 06 04:58:16 PM PDT 24
Finished Jul 06 05:03:41 PM PDT 24
Peak memory 183120 kb
Host smart-0b956d10-a154-454d-843a-347d6d21708b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129841011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.4129841011
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1044790698
Short name T340
Test name
Test status
Simulation time 377713756793 ps
CPU time 480.3 seconds
Started Jul 06 04:58:17 PM PDT 24
Finished Jul 06 05:06:17 PM PDT 24
Peak memory 195736 kb
Host smart-f42ffb12-7f11-46a7-a3ca-43ee0d1d34b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044790698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1044790698
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.3272875658
Short name T268
Test name
Test status
Simulation time 19871029872 ps
CPU time 30.78 seconds
Started Jul 06 05:01:21 PM PDT 24
Finished Jul 06 05:01:52 PM PDT 24
Peak memory 183024 kb
Host smart-da5f34b0-bf46-47eb-901a-d156ead90789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272875658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3272875658
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1450840533
Short name T323
Test name
Test status
Simulation time 20279047564 ps
CPU time 33.24 seconds
Started Jul 06 05:01:22 PM PDT 24
Finished Jul 06 05:01:56 PM PDT 24
Peak memory 183024 kb
Host smart-46c1f498-313c-40e7-b368-935a9fbaed52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450840533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1450840533
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3640429039
Short name T54
Test name
Test status
Simulation time 124693089803 ps
CPU time 128.08 seconds
Started Jul 06 05:01:27 PM PDT 24
Finished Jul 06 05:03:36 PM PDT 24
Peak memory 183052 kb
Host smart-f0032d91-4a94-453e-b4f2-196213e39825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640429039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3640429039
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3594132017
Short name T266
Test name
Test status
Simulation time 249398340480 ps
CPU time 148.33 seconds
Started Jul 06 05:01:30 PM PDT 24
Finished Jul 06 05:03:59 PM PDT 24
Peak memory 191236 kb
Host smart-73aff7c2-2859-4160-ac6f-46b8be8f7183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594132017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3594132017
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.4140358461
Short name T254
Test name
Test status
Simulation time 104145101523 ps
CPU time 113.28 seconds
Started Jul 06 05:01:27 PM PDT 24
Finished Jul 06 05:03:20 PM PDT 24
Peak memory 191320 kb
Host smart-11d5d7f3-4a09-4983-808c-dc93ce5c4881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140358461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.4140358461
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1512308637
Short name T427
Test name
Test status
Simulation time 296774646854 ps
CPU time 158.6 seconds
Started Jul 06 04:58:22 PM PDT 24
Finished Jul 06 05:01:01 PM PDT 24
Peak memory 182548 kb
Host smart-eedd03bd-4c51-41f8-b265-3b761ef4a56a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512308637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1512308637
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2231402025
Short name T362
Test name
Test status
Simulation time 159737087480 ps
CPU time 210.08 seconds
Started Jul 06 04:58:15 PM PDT 24
Finished Jul 06 05:01:46 PM PDT 24
Peak memory 183092 kb
Host smart-bf7525d2-5127-4914-9b2d-2c5d6fdea35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231402025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2231402025
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2365589190
Short name T177
Test name
Test status
Simulation time 2467847404747 ps
CPU time 1625.82 seconds
Started Jul 06 04:58:13 PM PDT 24
Finished Jul 06 05:25:20 PM PDT 24
Peak memory 195528 kb
Host smart-c5adf918-7615-480e-97ce-1136fd9cc41c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365589190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2365589190
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/133.rv_timer_random.2795223397
Short name T114
Test name
Test status
Simulation time 178202368601 ps
CPU time 367.13 seconds
Started Jul 06 05:01:33 PM PDT 24
Finished Jul 06 05:07:40 PM PDT 24
Peak memory 191340 kb
Host smart-36ce4293-cd81-4bd9-86e9-efb8d2ebc84d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795223397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2795223397
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.1444238376
Short name T336
Test name
Test status
Simulation time 22917200674 ps
CPU time 33.94 seconds
Started Jul 06 05:01:33 PM PDT 24
Finished Jul 06 05:02:08 PM PDT 24
Peak memory 183020 kb
Host smart-3addad85-6fbb-4f58-944b-12fbb6020de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444238376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.1444238376
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2908970777
Short name T9
Test name
Test status
Simulation time 652279246644 ps
CPU time 2754.58 seconds
Started Jul 06 05:01:34 PM PDT 24
Finished Jul 06 05:47:29 PM PDT 24
Peak memory 191344 kb
Host smart-8203dee4-718d-4480-9093-78178deb77db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908970777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2908970777
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3061199357
Short name T166
Test name
Test status
Simulation time 110235445710 ps
CPU time 271.39 seconds
Started Jul 06 05:01:37 PM PDT 24
Finished Jul 06 05:06:09 PM PDT 24
Peak memory 191244 kb
Host smart-0419f6e8-0f06-4666-ae6f-52427b103d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061199357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3061199357
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.441696604
Short name T120
Test name
Test status
Simulation time 701193349039 ps
CPU time 569.39 seconds
Started Jul 06 05:01:36 PM PDT 24
Finished Jul 06 05:11:06 PM PDT 24
Peak memory 191244 kb
Host smart-002c440e-d012-45cf-8253-455d5ddedc76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441696604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.441696604
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3675406437
Short name T424
Test name
Test status
Simulation time 86393976017 ps
CPU time 381.44 seconds
Started Jul 06 05:01:36 PM PDT 24
Finished Jul 06 05:07:58 PM PDT 24
Peak memory 191244 kb
Host smart-60f8477f-fdc0-45a9-884b-d297c70c0bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675406437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3675406437
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3102841928
Short name T293
Test name
Test status
Simulation time 2283062810333 ps
CPU time 745.6 seconds
Started Jul 06 04:58:22 PM PDT 24
Finished Jul 06 05:10:48 PM PDT 24
Peak memory 183024 kb
Host smart-ea1375a4-ad7a-44c5-a811-326df6d27d87
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102841928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3102841928
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.533805198
Short name T435
Test name
Test status
Simulation time 855943349057 ps
CPU time 146.71 seconds
Started Jul 06 04:58:19 PM PDT 24
Finished Jul 06 05:00:46 PM PDT 24
Peak memory 183012 kb
Host smart-83a737d2-ddb4-4580-8480-c2b8d6bbf445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533805198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.533805198
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3721269397
Short name T414
Test name
Test status
Simulation time 27285758379 ps
CPU time 13.26 seconds
Started Jul 06 04:58:24 PM PDT 24
Finished Jul 06 04:58:38 PM PDT 24
Peak memory 191340 kb
Host smart-931dd626-3dcf-4a6b-b7a7-dac24a0b2a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721269397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3721269397
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1614181252
Short name T392
Test name
Test status
Simulation time 271744909856 ps
CPU time 64.21 seconds
Started Jul 06 04:58:19 PM PDT 24
Finished Jul 06 04:59:24 PM PDT 24
Peak memory 194888 kb
Host smart-29a4c44f-7cb5-4dd5-a630-a884c3054598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614181252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1614181252
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.4050276609
Short name T83
Test name
Test status
Simulation time 15923422886 ps
CPU time 186.76 seconds
Started Jul 06 05:01:34 PM PDT 24
Finished Jul 06 05:04:41 PM PDT 24
Peak memory 183144 kb
Host smart-b0fddfca-3f2e-4797-838a-375d058caa0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050276609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4050276609
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1879175553
Short name T271
Test name
Test status
Simulation time 27595525502 ps
CPU time 41.88 seconds
Started Jul 06 05:01:37 PM PDT 24
Finished Jul 06 05:02:19 PM PDT 24
Peak memory 183036 kb
Host smart-f5c3752a-dd9e-4f24-bcf3-0757e4a2b2b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879175553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1879175553
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.1929510065
Short name T73
Test name
Test status
Simulation time 819786051910 ps
CPU time 238.54 seconds
Started Jul 06 05:01:39 PM PDT 24
Finished Jul 06 05:05:38 PM PDT 24
Peak memory 191244 kb
Host smart-78758717-5075-43a4-9f57-ce577965183e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929510065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1929510065
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2848386905
Short name T143
Test name
Test status
Simulation time 80039088835 ps
CPU time 328.62 seconds
Started Jul 06 05:01:40 PM PDT 24
Finished Jul 06 05:07:09 PM PDT 24
Peak memory 191180 kb
Host smart-0d32b928-9a82-405f-ba7e-52228e4d246c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848386905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2848386905
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3128706607
Short name T199
Test name
Test status
Simulation time 51813910093 ps
CPU time 79.01 seconds
Started Jul 06 05:01:41 PM PDT 24
Finished Jul 06 05:03:00 PM PDT 24
Peak memory 191344 kb
Host smart-1cdbdc75-4ad5-493a-bd56-65b05d2d6c01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128706607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3128706607
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.287841881
Short name T214
Test name
Test status
Simulation time 165775499355 ps
CPU time 739.5 seconds
Started Jul 06 05:01:40 PM PDT 24
Finished Jul 06 05:14:00 PM PDT 24
Peak memory 182988 kb
Host smart-d36a7cbb-802d-4273-9e20-4389f87c5d29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287841881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.287841881
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.49449318
Short name T400
Test name
Test status
Simulation time 351923807993 ps
CPU time 121.85 seconds
Started Jul 06 04:58:21 PM PDT 24
Finished Jul 06 05:00:23 PM PDT 24
Peak memory 182972 kb
Host smart-482b17ff-9f35-4f8c-ba5c-495521d9df5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49449318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.rv_timer_cfg_update_on_fly.49449318
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.126909551
Short name T371
Test name
Test status
Simulation time 86927399044 ps
CPU time 29.12 seconds
Started Jul 06 04:58:24 PM PDT 24
Finished Jul 06 04:58:54 PM PDT 24
Peak memory 183136 kb
Host smart-b49642f0-57e1-4860-960c-86e64bb2bd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126909551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.126909551
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.100597420
Short name T99
Test name
Test status
Simulation time 72602012 ps
CPU time 1.22 seconds
Started Jul 06 04:58:22 PM PDT 24
Finished Jul 06 04:58:24 PM PDT 24
Peak memory 182980 kb
Host smart-12c19b53-0194-40d3-9b55-a6570a372169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100597420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.100597420
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.2555928676
Short name T412
Test name
Test status
Simulation time 31592795537 ps
CPU time 122.59 seconds
Started Jul 06 05:01:42 PM PDT 24
Finished Jul 06 05:03:45 PM PDT 24
Peak memory 191348 kb
Host smart-6dc31c72-df83-46ad-b1da-adcc5696327a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555928676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2555928676
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3372198631
Short name T198
Test name
Test status
Simulation time 124528228393 ps
CPU time 959.74 seconds
Started Jul 06 05:01:41 PM PDT 24
Finished Jul 06 05:17:41 PM PDT 24
Peak memory 195304 kb
Host smart-5f93fca0-3b12-467c-a0dc-759614e32a69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372198631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3372198631
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3282883154
Short name T152
Test name
Test status
Simulation time 335154640626 ps
CPU time 412.53 seconds
Started Jul 06 05:01:40 PM PDT 24
Finished Jul 06 05:08:33 PM PDT 24
Peak memory 193364 kb
Host smart-c7ac9c41-3efe-4198-a229-71867f8f0e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282883154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3282883154
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.392178517
Short name T276
Test name
Test status
Simulation time 107590159309 ps
CPU time 141.69 seconds
Started Jul 06 05:01:46 PM PDT 24
Finished Jul 06 05:04:08 PM PDT 24
Peak memory 191288 kb
Host smart-3b9cad76-50ac-466c-a725-9f44e824ff40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392178517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.392178517
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1582196767
Short name T240
Test name
Test status
Simulation time 123876905772 ps
CPU time 226.61 seconds
Started Jul 06 05:01:47 PM PDT 24
Finished Jul 06 05:05:34 PM PDT 24
Peak memory 191344 kb
Host smart-8c8ae02f-fff3-4714-bdcd-1662a7eef53b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582196767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1582196767
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1755056573
Short name T335
Test name
Test status
Simulation time 188718182796 ps
CPU time 490.93 seconds
Started Jul 06 05:01:47 PM PDT 24
Finished Jul 06 05:09:58 PM PDT 24
Peak memory 191348 kb
Host smart-d26ee4e5-3881-4450-ac92-30bae5dbca77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755056573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1755056573
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.886037039
Short name T258
Test name
Test status
Simulation time 150956413666 ps
CPU time 407.16 seconds
Started Jul 06 05:01:47 PM PDT 24
Finished Jul 06 05:08:35 PM PDT 24
Peak memory 191336 kb
Host smart-e2ff01b2-c559-463f-8be8-ef25b2cf320f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886037039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.886037039
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.386081208
Short name T134
Test name
Test status
Simulation time 72739193853 ps
CPU time 141.54 seconds
Started Jul 06 05:01:47 PM PDT 24
Finished Jul 06 05:04:09 PM PDT 24
Peak memory 194820 kb
Host smart-9f4573e7-3952-4259-907e-b856eaa25c47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386081208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.386081208
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.990652680
Short name T151
Test name
Test status
Simulation time 252722912514 ps
CPU time 229.63 seconds
Started Jul 06 04:58:22 PM PDT 24
Finished Jul 06 05:02:12 PM PDT 24
Peak memory 182956 kb
Host smart-833f4af2-ed98-4d55-b68e-e9bcc75121e4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990652680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.990652680
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3395702083
Short name T384
Test name
Test status
Simulation time 322316473589 ps
CPU time 109.02 seconds
Started Jul 06 04:58:20 PM PDT 24
Finished Jul 06 05:00:10 PM PDT 24
Peak memory 182980 kb
Host smart-77db329e-b76b-427e-a176-effde392fe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395702083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3395702083
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.1940511077
Short name T244
Test name
Test status
Simulation time 2432241953680 ps
CPU time 474.22 seconds
Started Jul 06 04:58:21 PM PDT 24
Finished Jul 06 05:06:15 PM PDT 24
Peak memory 191184 kb
Host smart-525ed31c-7a91-470b-aaba-c7d73ecbbfb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940511077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.1940511077
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2428405090
Short name T85
Test name
Test status
Simulation time 525264289 ps
CPU time 0.96 seconds
Started Jul 06 04:58:21 PM PDT 24
Finished Jul 06 04:58:22 PM PDT 24
Peak memory 182892 kb
Host smart-49087b40-2e8b-43e6-99ab-2017f48765c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428405090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2428405090
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1005472293
Short name T215
Test name
Test status
Simulation time 748234729017 ps
CPU time 716.35 seconds
Started Jul 06 04:58:20 PM PDT 24
Finished Jul 06 05:10:17 PM PDT 24
Peak memory 191340 kb
Host smart-50eabcd2-a8a1-4457-90ca-431a464e2c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005472293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1005472293
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.4231647421
Short name T297
Test name
Test status
Simulation time 493673309142 ps
CPU time 721.24 seconds
Started Jul 06 05:01:47 PM PDT 24
Finished Jul 06 05:13:49 PM PDT 24
Peak memory 191208 kb
Host smart-6a43c3a5-e329-4ff9-92c8-99418f7b5981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231647421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.4231647421
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2396308346
Short name T341
Test name
Test status
Simulation time 62330283561 ps
CPU time 90.17 seconds
Started Jul 06 05:01:48 PM PDT 24
Finished Jul 06 05:03:18 PM PDT 24
Peak memory 191228 kb
Host smart-32d5170a-ae5c-44e2-b502-0a7f248b044b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396308346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2396308346
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3804851302
Short name T150
Test name
Test status
Simulation time 185653835207 ps
CPU time 177.56 seconds
Started Jul 06 05:01:48 PM PDT 24
Finished Jul 06 05:04:46 PM PDT 24
Peak memory 191324 kb
Host smart-fbe17384-c1d6-4a93-9cb8-22f58ebb177f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804851302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3804851302
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1375960077
Short name T69
Test name
Test status
Simulation time 105988276634 ps
CPU time 168.12 seconds
Started Jul 06 05:01:53 PM PDT 24
Finished Jul 06 05:04:41 PM PDT 24
Peak memory 191340 kb
Host smart-ef2d3844-ecd5-4011-8669-6505c70792dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375960077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1375960077
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1998464476
Short name T237
Test name
Test status
Simulation time 102092379043 ps
CPU time 2168.11 seconds
Started Jul 06 05:01:53 PM PDT 24
Finished Jul 06 05:38:01 PM PDT 24
Peak memory 191340 kb
Host smart-cb99eea9-9edf-4b62-8f47-6381adc16ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998464476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1998464476
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.187433738
Short name T208
Test name
Test status
Simulation time 83691974500 ps
CPU time 68 seconds
Started Jul 06 05:01:53 PM PDT 24
Finished Jul 06 05:03:01 PM PDT 24
Peak memory 183032 kb
Host smart-a038ee70-e377-49c7-9e6a-9f0047df5752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187433738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.187433738
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.134406411
Short name T170
Test name
Test status
Simulation time 448264822547 ps
CPU time 449.75 seconds
Started Jul 06 04:58:21 PM PDT 24
Finished Jul 06 05:05:51 PM PDT 24
Peak memory 183092 kb
Host smart-f7e7fed2-dada-4c71-b611-7208dba69147
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134406411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.134406411
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2616621425
Short name T396
Test name
Test status
Simulation time 166729962313 ps
CPU time 113.54 seconds
Started Jul 06 04:58:24 PM PDT 24
Finished Jul 06 05:00:18 PM PDT 24
Peak memory 183136 kb
Host smart-fef7899d-349f-4b6d-b702-b6ab37a9b333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616621425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2616621425
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.3024030915
Short name T342
Test name
Test status
Simulation time 252759749675 ps
CPU time 129.6 seconds
Started Jul 06 04:58:20 PM PDT 24
Finished Jul 06 05:00:30 PM PDT 24
Peak memory 183112 kb
Host smart-2f996989-44d4-4891-aa87-b0014c337011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024030915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.3024030915
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/172.rv_timer_random.475448990
Short name T288
Test name
Test status
Simulation time 1218959769896 ps
CPU time 829.03 seconds
Started Jul 06 05:01:52 PM PDT 24
Finished Jul 06 05:15:41 PM PDT 24
Peak memory 191292 kb
Host smart-83db77ea-e5f6-4e69-947c-a91db466afe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475448990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.475448990
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.605530744
Short name T228
Test name
Test status
Simulation time 100714288336 ps
CPU time 32.12 seconds
Started Jul 06 05:01:52 PM PDT 24
Finished Jul 06 05:02:24 PM PDT 24
Peak memory 183144 kb
Host smart-44c360cb-fef0-4b58-bc19-3a779935db41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605530744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.605530744
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2012471426
Short name T242
Test name
Test status
Simulation time 110866078479 ps
CPU time 178.25 seconds
Started Jul 06 05:01:59 PM PDT 24
Finished Jul 06 05:04:57 PM PDT 24
Peak memory 191224 kb
Host smart-04d165f1-9254-4d9b-827d-55b782ac6f03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012471426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2012471426
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1354531065
Short name T286
Test name
Test status
Simulation time 73389670908 ps
CPU time 126.29 seconds
Started Jul 06 05:02:00 PM PDT 24
Finished Jul 06 05:04:06 PM PDT 24
Peak memory 191348 kb
Host smart-5d086500-fb98-4077-9593-7c20cd488ac2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354531065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1354531065
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.291522274
Short name T53
Test name
Test status
Simulation time 150336014626 ps
CPU time 2098.57 seconds
Started Jul 06 05:02:02 PM PDT 24
Finished Jul 06 05:37:01 PM PDT 24
Peak memory 191340 kb
Host smart-47cd8516-a44e-48cb-a67a-11c742af760b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291522274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.291522274
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.995484726
Short name T140
Test name
Test status
Simulation time 183119720667 ps
CPU time 1621.5 seconds
Started Jul 06 05:01:59 PM PDT 24
Finished Jul 06 05:29:00 PM PDT 24
Peak memory 191212 kb
Host smart-f5d34962-6efd-4bcb-83d5-3da3fbf0c840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995484726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.995484726
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.4094667841
Short name T386
Test name
Test status
Simulation time 202127262221 ps
CPU time 140.26 seconds
Started Jul 06 04:58:21 PM PDT 24
Finished Jul 06 05:00:42 PM PDT 24
Peak memory 183040 kb
Host smart-101d7fe5-2299-41c4-8c3b-ef90f9899648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094667841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.4094667841
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.3925090212
Short name T216
Test name
Test status
Simulation time 436749046665 ps
CPU time 314.59 seconds
Started Jul 06 04:58:20 PM PDT 24
Finished Jul 06 05:03:35 PM PDT 24
Peak memory 191240 kb
Host smart-73e881c6-7cea-4d29-a77e-5ef4137b7791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925090212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3925090212
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.148398344
Short name T430
Test name
Test status
Simulation time 313590301485 ps
CPU time 146.88 seconds
Started Jul 06 04:58:21 PM PDT 24
Finished Jul 06 05:00:48 PM PDT 24
Peak memory 191320 kb
Host smart-34dfb7de-62b0-4b5f-961a-f5ac530dee2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148398344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.148398344
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3409509095
Short name T367
Test name
Test status
Simulation time 553404174766 ps
CPU time 221.42 seconds
Started Jul 06 04:58:24 PM PDT 24
Finished Jul 06 05:02:05 PM PDT 24
Peak memory 191340 kb
Host smart-12794ae5-08ac-4b9b-9cc1-cb18e939ce0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409509095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3409509095
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.113861477
Short name T19
Test name
Test status
Simulation time 447243276521 ps
CPU time 282.33 seconds
Started Jul 06 05:02:02 PM PDT 24
Finished Jul 06 05:06:45 PM PDT 24
Peak memory 191340 kb
Host smart-38ac8d66-390b-4578-a01c-5ce3c900494f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113861477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.113861477
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.65079723
Short name T154
Test name
Test status
Simulation time 114717117872 ps
CPU time 179.08 seconds
Started Jul 06 05:01:59 PM PDT 24
Finished Jul 06 05:04:58 PM PDT 24
Peak memory 191236 kb
Host smart-b58389a8-623f-4b63-96d2-358463973a57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65079723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.65079723
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3009979648
Short name T282
Test name
Test status
Simulation time 158133447166 ps
CPU time 99.13 seconds
Started Jul 06 05:01:59 PM PDT 24
Finished Jul 06 05:03:38 PM PDT 24
Peak memory 183000 kb
Host smart-38ce1b8d-5d14-4026-8c80-ceb2c842ae8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009979648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3009979648
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.346101386
Short name T353
Test name
Test status
Simulation time 220212139221 ps
CPU time 1161.06 seconds
Started Jul 06 05:02:07 PM PDT 24
Finished Jul 06 05:21:28 PM PDT 24
Peak memory 191316 kb
Host smart-4864ecad-7582-4230-b37b-7b3c53eb5453
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346101386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.346101386
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1678861652
Short name T217
Test name
Test status
Simulation time 315778740313 ps
CPU time 180.27 seconds
Started Jul 06 05:02:04 PM PDT 24
Finished Jul 06 05:05:05 PM PDT 24
Peak memory 191340 kb
Host smart-44717268-dae5-48f9-bffe-60017540df3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678861652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1678861652
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2105893719
Short name T52
Test name
Test status
Simulation time 303547975969 ps
CPU time 1638.91 seconds
Started Jul 06 05:02:07 PM PDT 24
Finished Jul 06 05:29:27 PM PDT 24
Peak memory 191324 kb
Host smart-23f7ddd2-47fe-4c72-b3f5-e5e99af81919
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105893719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2105893719
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1524395803
Short name T298
Test name
Test status
Simulation time 52148148813 ps
CPU time 34.17 seconds
Started Jul 06 05:02:11 PM PDT 24
Finished Jul 06 05:02:45 PM PDT 24
Peak memory 183380 kb
Host smart-8a6458f9-6d80-491a-94cd-631a7ce6dd2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524395803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1524395803
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1113306276
Short name T405
Test name
Test status
Simulation time 135770186392 ps
CPU time 227.66 seconds
Started Jul 06 04:58:22 PM PDT 24
Finished Jul 06 05:02:10 PM PDT 24
Peak memory 183120 kb
Host smart-f078ffa8-f730-4feb-9f48-f92f42e73f19
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113306276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1113306276
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2287175577
Short name T364
Test name
Test status
Simulation time 97935608281 ps
CPU time 140.36 seconds
Started Jul 06 04:58:23 PM PDT 24
Finished Jul 06 05:00:43 PM PDT 24
Peak memory 183140 kb
Host smart-ede6186e-1512-40aa-9c98-ea4da9fbdae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287175577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2287175577
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3651792427
Short name T290
Test name
Test status
Simulation time 128182553534 ps
CPU time 360.32 seconds
Started Jul 06 04:58:26 PM PDT 24
Finished Jul 06 05:04:27 PM PDT 24
Peak memory 195028 kb
Host smart-b5885e81-bd8c-4d08-b695-dd40d9c16b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651792427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3651792427
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.2639841404
Short name T132
Test name
Test status
Simulation time 1627177823018 ps
CPU time 697.77 seconds
Started Jul 06 05:02:10 PM PDT 24
Finished Jul 06 05:13:48 PM PDT 24
Peak memory 191240 kb
Host smart-8b21bfe3-23ba-47e9-a069-0a509e4e94f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639841404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2639841404
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.1200066491
Short name T128
Test name
Test status
Simulation time 198760628091 ps
CPU time 1911.86 seconds
Started Jul 06 05:02:11 PM PDT 24
Finished Jul 06 05:34:03 PM PDT 24
Peak memory 194952 kb
Host smart-73368846-85c3-4897-8a9b-bbe3092c0e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200066491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.1200066491
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3234352564
Short name T183
Test name
Test status
Simulation time 107002809458 ps
CPU time 686.4 seconds
Started Jul 06 05:02:11 PM PDT 24
Finished Jul 06 05:13:38 PM PDT 24
Peak memory 191232 kb
Host smart-7d1455e3-2d7a-435d-b0fe-f64d5d135509
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234352564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3234352564
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3973381660
Short name T313
Test name
Test status
Simulation time 95818964298 ps
CPU time 269.24 seconds
Started Jul 06 05:02:16 PM PDT 24
Finished Jul 06 05:06:45 PM PDT 24
Peak memory 191180 kb
Host smart-f5bdfbbe-5334-4237-817b-5924040dba2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973381660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3973381660
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1572374044
Short name T104
Test name
Test status
Simulation time 77853567097 ps
CPU time 97.25 seconds
Started Jul 06 05:02:16 PM PDT 24
Finished Jul 06 05:03:53 PM PDT 24
Peak memory 183052 kb
Host smart-15145c47-2247-430e-b01c-0dd2cce913f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572374044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1572374044
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1500124063
Short name T284
Test name
Test status
Simulation time 1771642642348 ps
CPU time 723.95 seconds
Started Jul 06 05:02:19 PM PDT 24
Finished Jul 06 05:14:23 PM PDT 24
Peak memory 191324 kb
Host smart-89e7edea-030c-465d-9fb7-dbbf418aa02a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500124063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1500124063
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.893980459
Short name T67
Test name
Test status
Simulation time 456167365717 ps
CPU time 839.39 seconds
Started Jul 06 05:02:17 PM PDT 24
Finished Jul 06 05:16:17 PM PDT 24
Peak memory 191244 kb
Host smart-d1522c59-4c74-4c64-8449-aff9900a4315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893980459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.893980459
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1990104429
Short name T311
Test name
Test status
Simulation time 434913848861 ps
CPU time 221.5 seconds
Started Jul 06 04:57:57 PM PDT 24
Finished Jul 06 05:01:39 PM PDT 24
Peak memory 183124 kb
Host smart-af196f53-922c-4c86-a85b-6f9bbf0e544b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990104429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1990104429
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3438416057
Short name T365
Test name
Test status
Simulation time 384148945580 ps
CPU time 147.37 seconds
Started Jul 06 04:57:57 PM PDT 24
Finished Jul 06 05:00:24 PM PDT 24
Peak memory 182988 kb
Host smart-605156a7-9b59-422b-a4d1-20a1fe379710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438416057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3438416057
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1410973660
Short name T321
Test name
Test status
Simulation time 133097086599 ps
CPU time 77.21 seconds
Started Jul 06 04:57:57 PM PDT 24
Finished Jul 06 04:59:14 PM PDT 24
Peak memory 191224 kb
Host smart-3e6c5538-5c23-4c12-9b4f-9f691ba8cf10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410973660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1410973660
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1490825709
Short name T361
Test name
Test status
Simulation time 73311248121 ps
CPU time 179.82 seconds
Started Jul 06 04:57:58 PM PDT 24
Finished Jul 06 05:00:58 PM PDT 24
Peak memory 183132 kb
Host smart-3c8429e5-1058-45cd-9964-76e747753996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490825709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1490825709
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1669698079
Short name T16
Test name
Test status
Simulation time 516160155 ps
CPU time 1 seconds
Started Jul 06 04:58:03 PM PDT 24
Finished Jul 06 04:58:04 PM PDT 24
Peak memory 214476 kb
Host smart-86d670f0-8ebc-44f1-b323-a44a17d4e700
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669698079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1669698079
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1399007968
Short name T388
Test name
Test status
Simulation time 172632180649 ps
CPU time 213.72 seconds
Started Jul 06 04:58:06 PM PDT 24
Finished Jul 06 05:01:40 PM PDT 24
Peak memory 191096 kb
Host smart-034ae3a2-e9d7-41b1-a2ce-cba439ad9146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399007968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1399007968
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2064686297
Short name T338
Test name
Test status
Simulation time 643732974697 ps
CPU time 642.09 seconds
Started Jul 06 04:58:25 PM PDT 24
Finished Jul 06 05:09:08 PM PDT 24
Peak memory 183028 kb
Host smart-c51508eb-4ff9-4fc0-b2fb-6f748fad5d88
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064686297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2064686297
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4244371428
Short name T401
Test name
Test status
Simulation time 172310408839 ps
CPU time 215.93 seconds
Started Jul 06 04:58:25 PM PDT 24
Finished Jul 06 05:02:02 PM PDT 24
Peak memory 183116 kb
Host smart-1aa282e6-83a2-4ad5-9a01-8b11f72f80eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244371428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4244371428
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.537621052
Short name T320
Test name
Test status
Simulation time 28315788078 ps
CPU time 47.97 seconds
Started Jul 06 04:58:25 PM PDT 24
Finished Jul 06 04:59:13 PM PDT 24
Peak memory 183140 kb
Host smart-b42b8263-6453-47f8-a22f-696ee2fa8d58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537621052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.537621052
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.624486588
Short name T80
Test name
Test status
Simulation time 30335226712 ps
CPU time 39.42 seconds
Started Jul 06 04:58:25 PM PDT 24
Finished Jul 06 04:59:05 PM PDT 24
Peak memory 193240 kb
Host smart-e846de00-53dd-40b0-9ce2-de58c9addfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624486588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.624486588
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.335840829
Short name T156
Test name
Test status
Simulation time 142451614942 ps
CPU time 824.56 seconds
Started Jul 06 04:58:25 PM PDT 24
Finished Jul 06 05:12:10 PM PDT 24
Peak memory 191228 kb
Host smart-75e5f80f-e02e-490f-9deb-dad6605db9a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335840829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
335840829
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.2297653403
Short name T51
Test name
Test status
Simulation time 707325219422 ps
CPU time 110.25 seconds
Started Jul 06 04:58:25 PM PDT 24
Finished Jul 06 05:00:15 PM PDT 24
Peak memory 183124 kb
Host smart-42c7a3ac-2024-4734-9da8-12e6f8e89995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297653403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.2297653403
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1871923137
Short name T168
Test name
Test status
Simulation time 39831609382 ps
CPU time 32.95 seconds
Started Jul 06 04:58:25 PM PDT 24
Finished Jul 06 04:58:59 PM PDT 24
Peak memory 191228 kb
Host smart-4db84410-e7c5-4e3d-930c-2b2279fc2e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871923137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1871923137
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1885015811
Short name T63
Test name
Test status
Simulation time 3795685360959 ps
CPU time 820 seconds
Started Jul 06 04:58:33 PM PDT 24
Finished Jul 06 05:12:14 PM PDT 24
Peak memory 195700 kb
Host smart-87077eea-6b99-45a2-b544-c0a727b80a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885015811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1885015811
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1991447293
Short name T23
Test name
Test status
Simulation time 31970188730 ps
CPU time 35.33 seconds
Started Jul 06 04:58:32 PM PDT 24
Finished Jul 06 04:59:07 PM PDT 24
Peak memory 183012 kb
Host smart-4892adf6-7b7f-4b96-a34b-504067bf18c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991447293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1991447293
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3456223821
Short name T381
Test name
Test status
Simulation time 150302634974 ps
CPU time 68.35 seconds
Started Jul 06 04:58:32 PM PDT 24
Finished Jul 06 04:59:41 PM PDT 24
Peak memory 183124 kb
Host smart-96e03b0e-e862-470a-b622-795a6f8c5928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456223821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3456223821
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3626362763
Short name T184
Test name
Test status
Simulation time 300270709827 ps
CPU time 392.35 seconds
Started Jul 06 04:58:35 PM PDT 24
Finished Jul 06 05:05:07 PM PDT 24
Peak memory 191248 kb
Host smart-c155d39c-2981-493e-8593-752861d0e90d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626362763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3626362763
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1597481421
Short name T273
Test name
Test status
Simulation time 177130606458 ps
CPU time 459.03 seconds
Started Jul 06 04:58:32 PM PDT 24
Finished Jul 06 05:06:11 PM PDT 24
Peak memory 193324 kb
Host smart-98101583-fe23-461d-8d38-5454365fe507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597481421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1597481421
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.4238222617
Short name T211
Test name
Test status
Simulation time 572472969948 ps
CPU time 1119.88 seconds
Started Jul 06 04:58:34 PM PDT 24
Finished Jul 06 05:17:14 PM PDT 24
Peak memory 195804 kb
Host smart-057279f4-300f-4c85-926f-1d649184a9c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238222617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.4238222617
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1452089703
Short name T436
Test name
Test status
Simulation time 124806214025 ps
CPU time 96.77 seconds
Started Jul 06 04:58:37 PM PDT 24
Finished Jul 06 05:00:14 PM PDT 24
Peak memory 183004 kb
Host smart-318bddd2-caed-4999-933a-950d51374246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452089703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1452089703
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1096920280
Short name T265
Test name
Test status
Simulation time 677380321727 ps
CPU time 428.22 seconds
Started Jul 06 04:58:36 PM PDT 24
Finished Jul 06 05:05:45 PM PDT 24
Peak memory 194960 kb
Host smart-a136d1b2-9df1-443f-9aef-a14925471dda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096920280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1096920280
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.813016568
Short name T307
Test name
Test status
Simulation time 152395525031 ps
CPU time 77.15 seconds
Started Jul 06 04:58:37 PM PDT 24
Finished Jul 06 04:59:55 PM PDT 24
Peak memory 193564 kb
Host smart-423be3b3-1dce-4629-a70c-5029d78bbd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813016568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.813016568
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.114780697
Short name T122
Test name
Test status
Simulation time 1116245167763 ps
CPU time 475.04 seconds
Started Jul 06 04:58:37 PM PDT 24
Finished Jul 06 05:06:32 PM PDT 24
Peak memory 196448 kb
Host smart-f73202fd-9dad-4dc1-9e32-c0da6c07f0d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114780697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
114780697
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.1488486430
Short name T38
Test name
Test status
Simulation time 117465066463 ps
CPU time 910.42 seconds
Started Jul 06 04:58:36 PM PDT 24
Finished Jul 06 05:13:47 PM PDT 24
Peak memory 205968 kb
Host smart-e77c6abf-8c99-422e-aabd-b4a8981ad5d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488486430 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.1488486430
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3905745327
Short name T275
Test name
Test status
Simulation time 38635399079 ps
CPU time 30.93 seconds
Started Jul 06 04:58:42 PM PDT 24
Finished Jul 06 04:59:13 PM PDT 24
Peak memory 182996 kb
Host smart-a520f002-c8f7-4c54-bd57-485b0ca34ba5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905745327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3905745327
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4207411709
Short name T402
Test name
Test status
Simulation time 57962088865 ps
CPU time 22.57 seconds
Started Jul 06 04:58:45 PM PDT 24
Finished Jul 06 04:59:08 PM PDT 24
Peak memory 182996 kb
Host smart-26a5b151-cd6a-4490-aa94-fe6c085b5358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207411709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4207411709
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3437212242
Short name T439
Test name
Test status
Simulation time 97766278905 ps
CPU time 88.5 seconds
Started Jul 06 04:58:42 PM PDT 24
Finished Jul 06 05:00:11 PM PDT 24
Peak memory 183116 kb
Host smart-035e80c8-e278-463e-9c62-a7f00dca6a47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437212242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3437212242
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.986349126
Short name T55
Test name
Test status
Simulation time 36844847371 ps
CPU time 63.48 seconds
Started Jul 06 04:58:45 PM PDT 24
Finished Jul 06 04:59:49 PM PDT 24
Peak memory 183008 kb
Host smart-0df85dcd-a1ca-4635-b646-7543986c1267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986349126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.986349126
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2246145525
Short name T117
Test name
Test status
Simulation time 2382488969752 ps
CPU time 661.55 seconds
Started Jul 06 04:58:41 PM PDT 24
Finished Jul 06 05:09:43 PM PDT 24
Peak memory 195312 kb
Host smart-64eb0bb8-9b96-4ef5-917b-f7c0456d94b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246145525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2246145525
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.2191296961
Short name T41
Test name
Test status
Simulation time 123412556478 ps
CPU time 1008.31 seconds
Started Jul 06 04:58:42 PM PDT 24
Finished Jul 06 05:15:31 PM PDT 24
Peak memory 206016 kb
Host smart-7b4bbe27-b9ae-4ba1-a07e-b804295de2e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191296961 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.2191296961
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2261680899
Short name T153
Test name
Test status
Simulation time 18293067134 ps
CPU time 29.93 seconds
Started Jul 06 04:58:50 PM PDT 24
Finished Jul 06 04:59:20 PM PDT 24
Peak memory 183028 kb
Host smart-cb202021-2613-4700-a8c0-25eeeae8d9a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261680899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2261680899
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2626566892
Short name T378
Test name
Test status
Simulation time 76306440335 ps
CPU time 104.37 seconds
Started Jul 06 04:58:48 PM PDT 24
Finished Jul 06 05:00:32 PM PDT 24
Peak memory 183024 kb
Host smart-e96b8212-7eac-4545-af80-a847029ea737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626566892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2626566892
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3316121428
Short name T287
Test name
Test status
Simulation time 1027245581718 ps
CPU time 457.29 seconds
Started Jul 06 04:58:42 PM PDT 24
Finished Jul 06 05:06:19 PM PDT 24
Peak memory 192344 kb
Host smart-09e3dd44-1c47-4c4d-8d98-4ea258ba2ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316121428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3316121428
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2865097749
Short name T312
Test name
Test status
Simulation time 48590216633 ps
CPU time 41.32 seconds
Started Jul 06 04:58:50 PM PDT 24
Finished Jul 06 04:59:32 PM PDT 24
Peak memory 191316 kb
Host smart-17f5dc4c-5b4a-480b-9f01-9fcd50bfb85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865097749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2865097749
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3414451245
Short name T262
Test name
Test status
Simulation time 30926427406 ps
CPU time 30.42 seconds
Started Jul 06 04:58:54 PM PDT 24
Finished Jul 06 04:59:24 PM PDT 24
Peak memory 182984 kb
Host smart-377ce3ff-f101-405b-83fa-4da4ed70a120
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414451245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3414451245
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_random.2600410603
Short name T274
Test name
Test status
Simulation time 108794682320 ps
CPU time 568.29 seconds
Started Jul 06 04:58:49 PM PDT 24
Finished Jul 06 05:08:17 PM PDT 24
Peak memory 191344 kb
Host smart-df3a74d0-6f3d-466b-8ffe-028d2e77bc2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600410603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2600410603
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3861732013
Short name T373
Test name
Test status
Simulation time 175857342 ps
CPU time 0.64 seconds
Started Jul 06 04:58:54 PM PDT 24
Finished Jul 06 04:58:55 PM PDT 24
Peak memory 182988 kb
Host smart-21837bb1-dd5a-4036-981a-fb0f00122d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861732013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3861732013
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1163513400
Short name T374
Test name
Test status
Simulation time 394434701407 ps
CPU time 163.98 seconds
Started Jul 06 04:58:54 PM PDT 24
Finished Jul 06 05:01:39 PM PDT 24
Peak memory 183112 kb
Host smart-04a913f2-756f-418f-a695-55a9b289bd96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163513400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1163513400
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3349077184
Short name T448
Test name
Test status
Simulation time 170439116386 ps
CPU time 152.59 seconds
Started Jul 06 04:59:01 PM PDT 24
Finished Jul 06 05:01:34 PM PDT 24
Peak memory 183108 kb
Host smart-86b9c803-491b-46f3-8239-91f7cb340062
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349077184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3349077184
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2534027965
Short name T369
Test name
Test status
Simulation time 35461459446 ps
CPU time 54.53 seconds
Started Jul 06 04:59:03 PM PDT 24
Finished Jul 06 04:59:57 PM PDT 24
Peak memory 183040 kb
Host smart-ea1c2182-ee02-4e8f-a836-377e310fe61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534027965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2534027965
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3064301939
Short name T441
Test name
Test status
Simulation time 9353496569 ps
CPU time 16.07 seconds
Started Jul 06 04:58:54 PM PDT 24
Finished Jul 06 04:59:10 PM PDT 24
Peak memory 183124 kb
Host smart-34de02e2-1fff-4e24-982b-230bb190e306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064301939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3064301939
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2839872896
Short name T8
Test name
Test status
Simulation time 49645271140 ps
CPU time 97.46 seconds
Started Jul 06 04:59:01 PM PDT 24
Finished Jul 06 05:00:39 PM PDT 24
Peak memory 191344 kb
Host smart-92debfa2-a584-47d0-be17-184654aabd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839872896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2839872896
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.456971375
Short name T232
Test name
Test status
Simulation time 169897221596 ps
CPU time 498.22 seconds
Started Jul 06 04:59:00 PM PDT 24
Finished Jul 06 05:07:19 PM PDT 24
Peak memory 194860 kb
Host smart-3a4d10fb-df82-454c-9bd1-3e6eb43a5a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456971375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
456971375
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.847024790
Short name T12
Test name
Test status
Simulation time 31126610028 ps
CPU time 226.07 seconds
Started Jul 06 04:59:02 PM PDT 24
Finished Jul 06 05:02:49 PM PDT 24
Peak memory 197772 kb
Host smart-b18788e3-5901-4172-8938-9141eeff6a22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847024790 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.847024790
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1908358251
Short name T164
Test name
Test status
Simulation time 115694275699 ps
CPU time 52.1 seconds
Started Jul 06 04:59:01 PM PDT 24
Finished Jul 06 04:59:54 PM PDT 24
Peak memory 183124 kb
Host smart-422f6ab6-7b08-42f9-9089-52d9503b05e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908358251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1908358251
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.487253206
Short name T375
Test name
Test status
Simulation time 92512453169 ps
CPU time 138.3 seconds
Started Jul 06 04:59:03 PM PDT 24
Finished Jul 06 05:01:22 PM PDT 24
Peak memory 183008 kb
Host smart-5a255f76-621c-4e78-8645-6c1f598bfdb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487253206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.487253206
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.868743328
Short name T68
Test name
Test status
Simulation time 273570908583 ps
CPU time 125.75 seconds
Started Jul 06 04:59:01 PM PDT 24
Finished Jul 06 05:01:08 PM PDT 24
Peak memory 191180 kb
Host smart-29db925f-4fca-45f8-8a3e-1fdfe13a0f4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868743328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.868743328
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2004074955
Short name T382
Test name
Test status
Simulation time 766532872 ps
CPU time 1.05 seconds
Started Jul 06 04:59:01 PM PDT 24
Finished Jul 06 04:59:02 PM PDT 24
Peak memory 191540 kb
Host smart-76dc7325-833e-4863-9b96-952b4e3dff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004074955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2004074955
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.32374367
Short name T406
Test name
Test status
Simulation time 264706595783 ps
CPU time 115.55 seconds
Started Jul 06 04:59:02 PM PDT 24
Finished Jul 06 05:00:57 PM PDT 24
Peak memory 183120 kb
Host smart-2c693dee-540d-4961-81e2-e63b585161eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32374367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.32374367
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.542430487
Short name T35
Test name
Test status
Simulation time 101410327507 ps
CPU time 457.51 seconds
Started Jul 06 04:59:03 PM PDT 24
Finished Jul 06 05:06:41 PM PDT 24
Peak memory 207348 kb
Host smart-d9a6467a-992f-4a62-83ca-cdb7f1e24b1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542430487 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.542430487
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2922191156
Short name T337
Test name
Test status
Simulation time 279240560031 ps
CPU time 473.05 seconds
Started Jul 06 04:59:06 PM PDT 24
Finished Jul 06 05:07:00 PM PDT 24
Peak memory 183096 kb
Host smart-09e142d4-c24a-4ce0-b3e4-9a224eb2bab5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922191156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2922191156
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.111063307
Short name T391
Test name
Test status
Simulation time 235529332996 ps
CPU time 96.45 seconds
Started Jul 06 04:59:07 PM PDT 24
Finished Jul 06 05:00:44 PM PDT 24
Peak memory 183052 kb
Host smart-b9545459-3130-4c0e-a299-0cbf13a77af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111063307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.111063307
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3258032976
Short name T294
Test name
Test status
Simulation time 17626858500 ps
CPU time 21.89 seconds
Started Jul 06 04:59:01 PM PDT 24
Finished Jul 06 04:59:23 PM PDT 24
Peak memory 183032 kb
Host smart-6974c2bb-c120-425a-b218-697d6fa2791b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258032976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3258032976
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2123736463
Short name T303
Test name
Test status
Simulation time 31187118593 ps
CPU time 46.45 seconds
Started Jul 06 04:59:07 PM PDT 24
Finished Jul 06 04:59:53 PM PDT 24
Peak memory 183100 kb
Host smart-d59eb6da-4f6b-4b33-bb3f-32dac7cacdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123736463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2123736463
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3009615164
Short name T108
Test name
Test status
Simulation time 191750278767 ps
CPU time 421.92 seconds
Started Jul 06 04:59:06 PM PDT 24
Finished Jul 06 05:06:08 PM PDT 24
Peak memory 206068 kb
Host smart-e3a28596-b785-4bcd-b9cd-7ce126e51572
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009615164 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3009615164
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.175638797
Short name T102
Test name
Test status
Simulation time 935676278536 ps
CPU time 512.91 seconds
Started Jul 06 04:58:09 PM PDT 24
Finished Jul 06 05:06:43 PM PDT 24
Peak memory 183036 kb
Host smart-e971f2af-035c-44bf-91d7-ea8a967fc637
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175638797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.175638797
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3103002875
Short name T432
Test name
Test status
Simulation time 573947498096 ps
CPU time 199.98 seconds
Started Jul 06 04:58:03 PM PDT 24
Finished Jul 06 05:01:23 PM PDT 24
Peak memory 183024 kb
Host smart-d7ef047c-b81b-47b3-907f-f60ddaea4bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103002875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3103002875
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1065020238
Short name T72
Test name
Test status
Simulation time 19523845380 ps
CPU time 19.6 seconds
Started Jul 06 04:58:02 PM PDT 24
Finished Jul 06 04:58:22 PM PDT 24
Peak memory 183140 kb
Host smart-3b460749-c56f-47e0-8eb7-0ac6f0f89d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065020238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1065020238
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2825076828
Short name T14
Test name
Test status
Simulation time 55374883 ps
CPU time 0.84 seconds
Started Jul 06 04:58:03 PM PDT 24
Finished Jul 06 04:58:04 PM PDT 24
Peak memory 213360 kb
Host smart-67de8621-43ff-4a95-99c6-87406a1eb782
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825076828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2825076828
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1028581709
Short name T233
Test name
Test status
Simulation time 1306306920347 ps
CPU time 282.75 seconds
Started Jul 06 04:58:04 PM PDT 24
Finished Jul 06 05:02:47 PM PDT 24
Peak memory 195276 kb
Host smart-e0eea610-a37b-40b1-88e1-00677653480c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028581709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1028581709
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.241506843
Short name T39
Test name
Test status
Simulation time 22987761822 ps
CPU time 243.43 seconds
Started Jul 06 04:58:02 PM PDT 24
Finished Jul 06 05:02:05 PM PDT 24
Peak memory 197776 kb
Host smart-34dd8fd1-f855-48b8-a5ed-f3bed6e36bb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241506843 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.241506843
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1729895613
Short name T440
Test name
Test status
Simulation time 31756403069 ps
CPU time 43.56 seconds
Started Jul 06 04:59:07 PM PDT 24
Finished Jul 06 04:59:51 PM PDT 24
Peak memory 183128 kb
Host smart-099b72b6-378c-442d-bc84-7403996bc859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729895613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1729895613
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.4275216914
Short name T139
Test name
Test status
Simulation time 155785167593 ps
CPU time 122.89 seconds
Started Jul 06 04:59:07 PM PDT 24
Finished Jul 06 05:01:10 PM PDT 24
Peak memory 191344 kb
Host smart-038fe4e1-d37e-4d0d-a3a6-8a3d99a1a6fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275216914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4275216914
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2238254617
Short name T238
Test name
Test status
Simulation time 61111560536 ps
CPU time 152.79 seconds
Started Jul 06 04:59:13 PM PDT 24
Finished Jul 06 05:01:46 PM PDT 24
Peak memory 191356 kb
Host smart-da71144e-fbc8-4e2f-896a-bde7192f4d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238254617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2238254617
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all_with_rand_reset.1655753875
Short name T13
Test name
Test status
Simulation time 297529688780 ps
CPU time 702.77 seconds
Started Jul 06 04:59:12 PM PDT 24
Finished Jul 06 05:10:55 PM PDT 24
Peak memory 209308 kb
Host smart-3232d48c-b162-4d12-a738-b45d9dd7d089
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655753875 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all_with_rand_reset.1655753875
Directory /workspace/30.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.2752681367
Short name T250
Test name
Test status
Simulation time 928555713104 ps
CPU time 955.36 seconds
Started Jul 06 04:59:13 PM PDT 24
Finished Jul 06 05:15:09 PM PDT 24
Peak memory 183012 kb
Host smart-4cf41b62-6d5f-445b-9d0a-c44a9580c784
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752681367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.2752681367
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1839188968
Short name T394
Test name
Test status
Simulation time 885666155998 ps
CPU time 112.43 seconds
Started Jul 06 04:59:12 PM PDT 24
Finished Jul 06 05:01:05 PM PDT 24
Peak memory 183044 kb
Host smart-bde6e6c5-c926-4096-919c-98461fe78d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839188968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1839188968
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3364873463
Short name T319
Test name
Test status
Simulation time 70117392309 ps
CPU time 484.2 seconds
Started Jul 06 04:59:13 PM PDT 24
Finished Jul 06 05:07:18 PM PDT 24
Peak memory 191240 kb
Host smart-bdacdc46-0bf5-4312-b738-0c3f9716acef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364873463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3364873463
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.170268611
Short name T295
Test name
Test status
Simulation time 2909671260 ps
CPU time 7.88 seconds
Started Jul 06 04:59:13 PM PDT 24
Finished Jul 06 04:59:21 PM PDT 24
Peak memory 183124 kb
Host smart-5ec98cf8-b276-408e-9ebe-295c3e82a1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170268611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.170268611
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3501306952
Short name T285
Test name
Test status
Simulation time 103383400197 ps
CPU time 174.53 seconds
Started Jul 06 04:59:18 PM PDT 24
Finished Jul 06 05:02:13 PM PDT 24
Peak memory 183108 kb
Host smart-43be5bab-7350-4783-aa74-21ec8dd42bfe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501306952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3501306952
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.968362548
Short name T390
Test name
Test status
Simulation time 105416306607 ps
CPU time 159.19 seconds
Started Jul 06 04:59:19 PM PDT 24
Finished Jul 06 05:01:58 PM PDT 24
Peak memory 183140 kb
Host smart-b28eaacc-3cb7-40e2-80e4-edc4f874fdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968362548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.968362548
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.324209034
Short name T302
Test name
Test status
Simulation time 119831227862 ps
CPU time 219.93 seconds
Started Jul 06 04:59:19 PM PDT 24
Finished Jul 06 05:02:59 PM PDT 24
Peak memory 183004 kb
Host smart-93413022-7da5-4725-9a82-63327d1555c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324209034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.324209034
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1594772884
Short name T136
Test name
Test status
Simulation time 34341843810 ps
CPU time 93.18 seconds
Started Jul 06 04:59:26 PM PDT 24
Finished Jul 06 05:01:00 PM PDT 24
Peak memory 191344 kb
Host smart-e5e0c434-26e6-4cee-8fff-2005a7ebbaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594772884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1594772884
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.2410540935
Short name T416
Test name
Test status
Simulation time 5719057320 ps
CPU time 4.67 seconds
Started Jul 06 04:59:25 PM PDT 24
Finished Jul 06 04:59:30 PM PDT 24
Peak memory 193976 kb
Host smart-c407b7e1-0f7d-43a6-b688-43272b08a252
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410540935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.2410540935
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.3889582649
Short name T40
Test name
Test status
Simulation time 92443337974 ps
CPU time 972.23 seconds
Started Jul 06 04:59:25 PM PDT 24
Finished Jul 06 05:15:38 PM PDT 24
Peak memory 205948 kb
Host smart-1cd6bf0a-9b4b-4071-8c5d-6bb0f39ee137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889582649 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.3889582649
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2829835312
Short name T234
Test name
Test status
Simulation time 364757444533 ps
CPU time 410.54 seconds
Started Jul 06 04:59:27 PM PDT 24
Finished Jul 06 05:06:17 PM PDT 24
Peak memory 183120 kb
Host smart-31a2ffb2-0d2a-49d1-b729-4ff2a9c12e89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829835312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2829835312
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2215414023
Short name T101
Test name
Test status
Simulation time 962812173837 ps
CPU time 115.67 seconds
Started Jul 06 04:59:26 PM PDT 24
Finished Jul 06 05:01:22 PM PDT 24
Peak memory 183032 kb
Host smart-258fcef6-a91f-4db1-93ed-1b4d2e062666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215414023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2215414023
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.501036622
Short name T235
Test name
Test status
Simulation time 39567118908 ps
CPU time 58.1 seconds
Started Jul 06 04:59:25 PM PDT 24
Finished Jul 06 05:00:24 PM PDT 24
Peak memory 191308 kb
Host smart-93296402-92a6-451a-beca-e94b8395ea6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501036622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.501036622
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2222316236
Short name T403
Test name
Test status
Simulation time 280864972 ps
CPU time 0.65 seconds
Started Jul 06 04:59:25 PM PDT 24
Finished Jul 06 04:59:26 PM PDT 24
Peak memory 182992 kb
Host smart-19ec84ac-40e5-4868-a2a7-799b5540db47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222316236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2222316236
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3436144172
Short name T79
Test name
Test status
Simulation time 267978773808 ps
CPU time 143.99 seconds
Started Jul 06 04:59:32 PM PDT 24
Finished Jul 06 05:01:56 PM PDT 24
Peak memory 183096 kb
Host smart-f34be363-41d2-4e94-b09e-089b327276c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436144172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3436144172
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.2698306639
Short name T11
Test name
Test status
Simulation time 390445159186 ps
CPU time 165.39 seconds
Started Jul 06 04:59:31 PM PDT 24
Finished Jul 06 05:02:16 PM PDT 24
Peak memory 183132 kb
Host smart-7cf348d9-df26-4526-b9df-6e4e5eb3d90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698306639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.2698306639
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3753641580
Short name T160
Test name
Test status
Simulation time 310217666388 ps
CPU time 636.3 seconds
Started Jul 06 04:59:33 PM PDT 24
Finished Jul 06 05:10:10 PM PDT 24
Peak memory 191340 kb
Host smart-4031f34b-6a9e-4dd9-a977-f19caf3c8f77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753641580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3753641580
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3775053119
Short name T159
Test name
Test status
Simulation time 110734017605 ps
CPU time 100.3 seconds
Started Jul 06 04:59:33 PM PDT 24
Finished Jul 06 05:01:14 PM PDT 24
Peak memory 191344 kb
Host smart-4498eff0-f069-497d-b156-d7ce9c0f2889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775053119 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3775053119
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.801133087
Short name T226
Test name
Test status
Simulation time 42731301260 ps
CPU time 21.53 seconds
Started Jul 06 04:59:37 PM PDT 24
Finished Jul 06 04:59:58 PM PDT 24
Peak memory 183120 kb
Host smart-aa2b3fb9-5552-4ed0-99b0-a27ac54f1869
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801133087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.801133087
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3185492733
Short name T389
Test name
Test status
Simulation time 38101630807 ps
CPU time 58.34 seconds
Started Jul 06 04:59:37 PM PDT 24
Finished Jul 06 05:00:36 PM PDT 24
Peak memory 183028 kb
Host smart-b71d6f0e-fb24-48a6-ba11-cfd369d8dfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185492733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3185492733
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.4132762885
Short name T7
Test name
Test status
Simulation time 76769909483 ps
CPU time 578.66 seconds
Started Jul 06 04:59:36 PM PDT 24
Finished Jul 06 05:09:15 PM PDT 24
Peak memory 191240 kb
Host smart-7ecbf63f-a1dc-418b-a88c-f03d18f83d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132762885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.4132762885
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1338178072
Short name T123
Test name
Test status
Simulation time 49523436023 ps
CPU time 75.29 seconds
Started Jul 06 04:59:37 PM PDT 24
Finished Jul 06 05:00:53 PM PDT 24
Peak memory 191312 kb
Host smart-86cd0abb-3f94-44fc-b32e-5175c3c4f75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338178072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1338178072
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3681854282
Short name T10
Test name
Test status
Simulation time 762505721187 ps
CPU time 337.95 seconds
Started Jul 06 04:59:36 PM PDT 24
Finished Jul 06 05:05:14 PM PDT 24
Peak memory 194876 kb
Host smart-1b843518-19c4-4907-bf14-62baf34c698d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681854282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3681854282
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.3078510490
Short name T399
Test name
Test status
Simulation time 13125643756 ps
CPU time 90.05 seconds
Started Jul 06 04:59:36 PM PDT 24
Finished Jul 06 05:01:07 PM PDT 24
Peak memory 197872 kb
Host smart-f06b82c5-cf37-4751-a33f-cf08875d72f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078510490 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.3078510490
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3579137059
Short name T270
Test name
Test status
Simulation time 5476480857 ps
CPU time 8.44 seconds
Started Jul 06 04:59:42 PM PDT 24
Finished Jul 06 04:59:51 PM PDT 24
Peak memory 183100 kb
Host smart-5cafddf5-ec47-44d4-b53b-18db4fc0c2d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579137059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3579137059
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2583006300
Short name T379
Test name
Test status
Simulation time 95782943271 ps
CPU time 71.24 seconds
Started Jul 06 04:59:43 PM PDT 24
Finished Jul 06 05:00:55 PM PDT 24
Peak memory 183000 kb
Host smart-9d920db7-9d6a-4c01-84c1-4f57aba66155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583006300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2583006300
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.4204531399
Short name T209
Test name
Test status
Simulation time 8284375898 ps
CPU time 35.03 seconds
Started Jul 06 04:59:42 PM PDT 24
Finished Jul 06 05:00:17 PM PDT 24
Peak memory 183144 kb
Host smart-be61bb1c-40d9-4b14-8a34-bfdc3badbde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204531399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.4204531399
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1224775645
Short name T243
Test name
Test status
Simulation time 70941123056 ps
CPU time 264.65 seconds
Started Jul 06 04:59:43 PM PDT 24
Finished Jul 06 05:04:08 PM PDT 24
Peak memory 191296 kb
Host smart-fba323c6-bd57-4f8c-9c92-92914de93dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224775645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1224775645
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3212133665
Short name T259
Test name
Test status
Simulation time 450256717832 ps
CPU time 366.88 seconds
Started Jul 06 04:59:48 PM PDT 24
Finished Jul 06 05:05:55 PM PDT 24
Peak memory 191308 kb
Host smart-ebef20c6-41ad-42ec-a51b-d94e6ed89f8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212133665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3212133665
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.221083245
Short name T149
Test name
Test status
Simulation time 702241478786 ps
CPU time 607.18 seconds
Started Jul 06 04:59:50 PM PDT 24
Finished Jul 06 05:09:58 PM PDT 24
Peak memory 183108 kb
Host smart-7321f4d9-c618-48ba-ae3a-a43df5b6e8ed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221083245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.221083245
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3483072400
Short name T376
Test name
Test status
Simulation time 139331524414 ps
CPU time 96.15 seconds
Started Jul 06 04:59:48 PM PDT 24
Finished Jul 06 05:01:24 PM PDT 24
Peak memory 183016 kb
Host smart-62acd7c0-1547-4a29-925e-0f6692fa4cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483072400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3483072400
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.3970210580
Short name T203
Test name
Test status
Simulation time 136021036750 ps
CPU time 360.41 seconds
Started Jul 06 04:59:50 PM PDT 24
Finished Jul 06 05:05:50 PM PDT 24
Peak memory 191320 kb
Host smart-97d80d76-016a-4e60-a82d-8d87e194ff59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970210580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3970210580
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.564023621
Short name T196
Test name
Test status
Simulation time 45395296857 ps
CPU time 80.77 seconds
Started Jul 06 04:59:48 PM PDT 24
Finished Jul 06 05:01:09 PM PDT 24
Peak memory 183092 kb
Host smart-4138d1d7-3cdd-459e-bfc3-e61ad32f68ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564023621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.564023621
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.615288333
Short name T124
Test name
Test status
Simulation time 269663109619 ps
CPU time 719.48 seconds
Started Jul 06 04:59:49 PM PDT 24
Finished Jul 06 05:11:48 PM PDT 24
Peak memory 194420 kb
Host smart-4b7d3bc7-07c5-4363-9228-91da35c13598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615288333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
615288333
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1598690069
Short name T326
Test name
Test status
Simulation time 126989588662 ps
CPU time 40.78 seconds
Started Jul 06 04:59:49 PM PDT 24
Finished Jul 06 05:00:30 PM PDT 24
Peak memory 183108 kb
Host smart-e1bdf6eb-335f-4b1e-b125-7b7eb047cbe5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598690069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1598690069
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3333236393
Short name T383
Test name
Test status
Simulation time 156260997780 ps
CPU time 112.68 seconds
Started Jul 06 04:59:49 PM PDT 24
Finished Jul 06 05:01:42 PM PDT 24
Peak memory 183032 kb
Host smart-1759181b-26ed-4760-af31-55ff32791a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333236393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3333236393
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2852672493
Short name T230
Test name
Test status
Simulation time 429979391568 ps
CPU time 246.92 seconds
Started Jul 06 04:59:50 PM PDT 24
Finished Jul 06 05:03:57 PM PDT 24
Peak memory 191348 kb
Host smart-af937ef0-a9b0-4614-8ea5-069d846ff0f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852672493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2852672493
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3482604351
Short name T426
Test name
Test status
Simulation time 94120292819 ps
CPU time 285.04 seconds
Started Jul 06 04:59:48 PM PDT 24
Finished Jul 06 05:04:34 PM PDT 24
Peak memory 183100 kb
Host smart-19907c1f-b0b1-4570-bc10-ec939c61e99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482604351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3482604351
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.195490277
Short name T385
Test name
Test status
Simulation time 63208747 ps
CPU time 0.53 seconds
Started Jul 06 04:59:56 PM PDT 24
Finished Jul 06 04:59:56 PM PDT 24
Peak memory 182856 kb
Host smart-002e6d49-e3d0-4f32-ab2f-4abdd4f9bc92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195490277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
195490277
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.3072982591
Short name T42
Test name
Test status
Simulation time 45359851567 ps
CPU time 333.59 seconds
Started Jul 06 04:59:50 PM PDT 24
Finished Jul 06 05:05:24 PM PDT 24
Peak memory 197800 kb
Host smart-e3f1bb77-1bd1-43ad-b9dc-0246f39a2485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072982591 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.3072982591
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2421002277
Short name T329
Test name
Test status
Simulation time 762796116077 ps
CPU time 350.98 seconds
Started Jul 06 04:59:55 PM PDT 24
Finished Jul 06 05:05:46 PM PDT 24
Peak memory 183124 kb
Host smart-ff56d729-e691-47dc-90de-965db8293344
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421002277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2421002277
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2095857751
Short name T3
Test name
Test status
Simulation time 44091788130 ps
CPU time 56.82 seconds
Started Jul 06 04:59:57 PM PDT 24
Finished Jul 06 05:00:54 PM PDT 24
Peak memory 183136 kb
Host smart-72e49034-e132-4b8b-bb54-e1f3a077a553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095857751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2095857751
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2389637171
Short name T255
Test name
Test status
Simulation time 185052520422 ps
CPU time 34.23 seconds
Started Jul 06 04:59:57 PM PDT 24
Finished Jul 06 05:00:31 PM PDT 24
Peak memory 191344 kb
Host smart-cdd0b836-a27c-4c62-8e6c-c95cb87227ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389637171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2389637171
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1339510206
Short name T252
Test name
Test status
Simulation time 156911693520 ps
CPU time 280.58 seconds
Started Jul 06 04:59:55 PM PDT 24
Finished Jul 06 05:04:36 PM PDT 24
Peak memory 182980 kb
Host smart-3a7a1a0e-7707-4d9c-be41-fb2e3f400f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339510206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1339510206
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2971134452
Short name T62
Test name
Test status
Simulation time 196843404898 ps
CPU time 934.6 seconds
Started Jul 06 04:59:57 PM PDT 24
Finished Jul 06 05:15:32 PM PDT 24
Peak memory 194852 kb
Host smart-eb08a838-2f07-4a11-8f6d-ed98bf82fe7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971134452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2971134452
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3676347595
Short name T84
Test name
Test status
Simulation time 1579582380 ps
CPU time 3.19 seconds
Started Jul 06 04:58:06 PM PDT 24
Finished Jul 06 04:58:09 PM PDT 24
Peak memory 182852 kb
Host smart-5a391f23-a14b-4dd2-a0c6-47be7ef72cc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676347595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3676347595
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1487126927
Short name T372
Test name
Test status
Simulation time 188783950517 ps
CPU time 137.87 seconds
Started Jul 06 04:58:04 PM PDT 24
Finished Jul 06 05:00:22 PM PDT 24
Peak memory 183144 kb
Host smart-8777c78d-c099-4e04-a360-6deaf66bae0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487126927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1487126927
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3090783695
Short name T434
Test name
Test status
Simulation time 539278725673 ps
CPU time 578.36 seconds
Started Jul 06 04:58:03 PM PDT 24
Finished Jul 06 05:07:42 PM PDT 24
Peak memory 191320 kb
Host smart-5085a8f9-ce85-4355-88fa-b44ac2f0ffb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090783695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3090783695
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3200484890
Short name T6
Test name
Test status
Simulation time 469460732 ps
CPU time 0.88 seconds
Started Jul 06 04:58:02 PM PDT 24
Finished Jul 06 04:58:04 PM PDT 24
Peak memory 182896 kb
Host smart-a2e4c312-5b73-436b-888c-95b1fa2b6987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200484890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3200484890
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3878042024
Short name T17
Test name
Test status
Simulation time 180941066 ps
CPU time 0.94 seconds
Started Jul 06 04:58:02 PM PDT 24
Finished Jul 06 04:58:04 PM PDT 24
Peak memory 214484 kb
Host smart-c13a317f-c4fb-4eb8-a9c6-2f6bd0be19a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878042024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3878042024
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.611045682
Short name T192
Test name
Test status
Simulation time 311852701831 ps
CPU time 760.95 seconds
Started Jul 06 04:58:04 PM PDT 24
Finished Jul 06 05:10:45 PM PDT 24
Peak memory 195528 kb
Host smart-17268c6a-2d78-4682-b965-23392abba46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611045682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.611045682
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.696387628
Short name T339
Test name
Test status
Simulation time 351311203300 ps
CPU time 179.07 seconds
Started Jul 06 05:00:04 PM PDT 24
Finished Jul 06 05:03:03 PM PDT 24
Peak memory 183036 kb
Host smart-d471c9dd-ed3d-45a1-843b-2b985b0cb2df
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696387628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.rv_timer_cfg_update_on_fly.696387628
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1885747071
Short name T449
Test name
Test status
Simulation time 97432553543 ps
CPU time 68.12 seconds
Started Jul 06 04:59:59 PM PDT 24
Finished Jul 06 05:01:08 PM PDT 24
Peak memory 183148 kb
Host smart-c97a328b-f67e-49d7-b4ed-1c99308a754b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885747071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1885747071
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1254644237
Short name T316
Test name
Test status
Simulation time 49053327237 ps
CPU time 9.55 seconds
Started Jul 06 05:00:04 PM PDT 24
Finished Jul 06 05:00:14 PM PDT 24
Peak memory 182960 kb
Host smart-eb22eba3-291b-4cc6-8f83-eb9c76043933
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254644237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1254644237
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2011654155
Short name T308
Test name
Test status
Simulation time 12037726801 ps
CPU time 21.2 seconds
Started Jul 06 05:00:01 PM PDT 24
Finished Jul 06 05:00:22 PM PDT 24
Peak memory 183108 kb
Host smart-b4d6a68f-b151-42ee-bcc2-9ec87ee4d2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011654155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2011654155
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1816799064
Short name T131
Test name
Test status
Simulation time 517393283537 ps
CPU time 932.13 seconds
Started Jul 06 04:59:59 PM PDT 24
Finished Jul 06 05:15:32 PM PDT 24
Peak memory 183008 kb
Host smart-c39694e9-dfc8-422b-8084-a399c14e93be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816799064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1816799064
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2368553732
Short name T360
Test name
Test status
Simulation time 128544303558 ps
CPU time 109.92 seconds
Started Jul 06 05:00:00 PM PDT 24
Finished Jul 06 05:01:50 PM PDT 24
Peak memory 182972 kb
Host smart-bfee5308-e3a2-4101-be86-564ffe8eb699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368553732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2368553732
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2109830369
Short name T172
Test name
Test status
Simulation time 307811840095 ps
CPU time 1836.61 seconds
Started Jul 06 05:00:01 PM PDT 24
Finished Jul 06 05:30:38 PM PDT 24
Peak memory 191320 kb
Host smart-2dae5d51-3c7e-4286-af40-4aa01afb6574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109830369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2109830369
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3260938296
Short name T245
Test name
Test status
Simulation time 131434632708 ps
CPU time 195.51 seconds
Started Jul 06 05:00:06 PM PDT 24
Finished Jul 06 05:03:22 PM PDT 24
Peak memory 183016 kb
Host smart-a2e0bc0d-0c5a-482f-8212-bea773474cd9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260938296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3260938296
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3795698210
Short name T363
Test name
Test status
Simulation time 607071756269 ps
CPU time 250.87 seconds
Started Jul 06 05:00:58 PM PDT 24
Finished Jul 06 05:05:09 PM PDT 24
Peak memory 183128 kb
Host smart-ff031402-df3f-495e-b948-561e98125af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795698210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3795698210
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.105816812
Short name T125
Test name
Test status
Simulation time 732884763106 ps
CPU time 513.33 seconds
Started Jul 06 05:00:05 PM PDT 24
Finished Jul 06 05:08:38 PM PDT 24
Peak memory 191240 kb
Host smart-2b3b8d92-ba15-4654-bdf5-9b3bbe26e096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105816812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.105816812
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1899426310
Short name T358
Test name
Test status
Simulation time 437007957 ps
CPU time 3.41 seconds
Started Jul 06 05:00:11 PM PDT 24
Finished Jul 06 05:00:14 PM PDT 24
Peak memory 192196 kb
Host smart-7f05e2ac-50af-4037-8dee-1423f9e7f195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899426310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1899426310
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1691928846
Short name T65
Test name
Test status
Simulation time 319470216437 ps
CPU time 128.32 seconds
Started Jul 06 05:00:11 PM PDT 24
Finished Jul 06 05:02:19 PM PDT 24
Peak memory 194676 kb
Host smart-e1f0e378-a7f0-4a01-ba38-939e27078730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691928846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1691928846
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2328273980
Short name T78
Test name
Test status
Simulation time 61684785997 ps
CPU time 24.88 seconds
Started Jul 06 05:00:18 PM PDT 24
Finished Jul 06 05:00:43 PM PDT 24
Peak memory 183012 kb
Host smart-bdf67f06-7760-4311-b401-3030660b5099
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328273980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2328273980
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3711613054
Short name T368
Test name
Test status
Simulation time 20835094526 ps
CPU time 30.92 seconds
Started Jul 06 05:00:18 PM PDT 24
Finished Jul 06 05:00:49 PM PDT 24
Peak memory 183036 kb
Host smart-f76651ba-8738-4c86-a08f-b0b00a79a5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711613054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3711613054
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2434668481
Short name T272
Test name
Test status
Simulation time 430953593411 ps
CPU time 163.15 seconds
Started Jul 06 05:00:18 PM PDT 24
Finished Jul 06 05:03:02 PM PDT 24
Peak memory 191288 kb
Host smart-0abec967-f548-4a1a-9d5a-970953b01d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434668481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2434668481
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2664491795
Short name T450
Test name
Test status
Simulation time 110036971903 ps
CPU time 68.55 seconds
Started Jul 06 05:00:16 PM PDT 24
Finished Jul 06 05:01:24 PM PDT 24
Peak memory 191340 kb
Host smart-6f604a76-6a49-4c4b-a585-99dc433c8733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664491795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2664491795
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.129706627
Short name T34
Test name
Test status
Simulation time 521219031893 ps
CPU time 2564.71 seconds
Started Jul 06 05:00:22 PM PDT 24
Finished Jul 06 05:43:07 PM PDT 24
Peak memory 191332 kb
Host smart-b1f37c96-ed07-4cfd-8d2a-4c525b60e628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129706627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
129706627
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.13971943
Short name T277
Test name
Test status
Simulation time 85958973550 ps
CPU time 146.3 seconds
Started Jul 06 05:00:23 PM PDT 24
Finished Jul 06 05:02:50 PM PDT 24
Peak memory 183100 kb
Host smart-9d50d616-d4ba-460b-822c-43aea0f7d297
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13971943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.rv_timer_cfg_update_on_fly.13971943
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2122508017
Short name T380
Test name
Test status
Simulation time 235624376360 ps
CPU time 166.37 seconds
Started Jul 06 05:00:27 PM PDT 24
Finished Jul 06 05:03:13 PM PDT 24
Peak memory 183124 kb
Host smart-344634ac-a90e-4b2c-88ed-88c82f25c08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122508017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2122508017
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.450616282
Short name T56
Test name
Test status
Simulation time 325468238252 ps
CPU time 128.04 seconds
Started Jul 06 05:00:23 PM PDT 24
Finished Jul 06 05:02:31 PM PDT 24
Peak memory 193796 kb
Host smart-cfaa6d09-f903-49b1-a3af-f5acbba1b274
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450616282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.450616282
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.623537073
Short name T413
Test name
Test status
Simulation time 1028969526 ps
CPU time 1.09 seconds
Started Jul 06 05:00:25 PM PDT 24
Finished Jul 06 05:00:27 PM PDT 24
Peak memory 182868 kb
Host smart-7a26fc79-8509-481c-aebd-021e8ef6d280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623537073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.623537073
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.4100683463
Short name T44
Test name
Test status
Simulation time 65244447991 ps
CPU time 367.22 seconds
Started Jul 06 05:00:27 PM PDT 24
Finished Jul 06 05:06:34 PM PDT 24
Peak memory 197832 kb
Host smart-8e1395fd-219f-42a5-863d-473514f56238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100683463 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.4100683463
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1506597190
Short name T356
Test name
Test status
Simulation time 139179349376 ps
CPU time 133.72 seconds
Started Jul 06 05:00:23 PM PDT 24
Finished Jul 06 05:02:37 PM PDT 24
Peak memory 183032 kb
Host smart-a3ac8069-9f00-405a-b700-d084f10bceac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506597190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1506597190
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3056609566
Short name T395
Test name
Test status
Simulation time 17098868247 ps
CPU time 11.72 seconds
Started Jul 06 05:00:23 PM PDT 24
Finished Jul 06 05:00:35 PM PDT 24
Peak memory 183024 kb
Host smart-18351215-cd39-4f41-a0cf-306a7c4d6f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056609566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3056609566
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3703528763
Short name T223
Test name
Test status
Simulation time 418022181858 ps
CPU time 120.63 seconds
Started Jul 06 05:00:23 PM PDT 24
Finished Jul 06 05:02:24 PM PDT 24
Peak memory 191296 kb
Host smart-48626925-d56a-4987-9785-46322255a544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703528763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3703528763
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1992948736
Short name T133
Test name
Test status
Simulation time 84629951619 ps
CPU time 145.76 seconds
Started Jul 06 05:00:23 PM PDT 24
Finished Jul 06 05:02:49 PM PDT 24
Peak memory 191220 kb
Host smart-23b15131-a5f6-470e-b196-7e86c885a344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992948736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1992948736
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2056780802
Short name T194
Test name
Test status
Simulation time 2412641265037 ps
CPU time 3627.64 seconds
Started Jul 06 05:00:28 PM PDT 24
Finished Jul 06 06:00:57 PM PDT 24
Peak memory 194400 kb
Host smart-a288321a-fcfc-4f40-aa6b-4d7f000c662a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056780802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2056780802
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1595776062
Short name T349
Test name
Test status
Simulation time 3523809150452 ps
CPU time 1757.94 seconds
Started Jul 06 05:00:29 PM PDT 24
Finished Jul 06 05:29:47 PM PDT 24
Peak memory 183124 kb
Host smart-47408e56-cd24-4350-aefb-8211ff1e8de3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595776062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1595776062
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1250316111
Short name T393
Test name
Test status
Simulation time 221913955800 ps
CPU time 164.55 seconds
Started Jul 06 05:00:28 PM PDT 24
Finished Jul 06 05:03:12 PM PDT 24
Peak memory 183124 kb
Host smart-3ac9ebfb-1f55-42a3-abef-8a8cf729b450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250316111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1250316111
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2770407906
Short name T186
Test name
Test status
Simulation time 139737560499 ps
CPU time 338.13 seconds
Started Jul 06 05:00:28 PM PDT 24
Finished Jul 06 05:06:07 PM PDT 24
Peak memory 191316 kb
Host smart-64c17784-bf22-4f35-b032-18392384ec62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770407906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2770407906
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2551606214
Short name T355
Test name
Test status
Simulation time 265945694634 ps
CPU time 413.71 seconds
Started Jul 06 05:00:29 PM PDT 24
Finished Jul 06 05:07:23 PM PDT 24
Peak memory 191296 kb
Host smart-61b60725-0584-4955-aa3f-40783db3331f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551606214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2551606214
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3844435862
Short name T253
Test name
Test status
Simulation time 2945377829416 ps
CPU time 1059.66 seconds
Started Jul 06 05:00:29 PM PDT 24
Finished Jul 06 05:18:09 PM PDT 24
Peak memory 191292 kb
Host smart-fb6d0463-bf6d-4c32-a9e7-f5d667a9bab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844435862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3844435862
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2116634089
Short name T431
Test name
Test status
Simulation time 674048613426 ps
CPU time 287.85 seconds
Started Jul 06 05:00:29 PM PDT 24
Finished Jul 06 05:05:17 PM PDT 24
Peak memory 183028 kb
Host smart-9eefaa12-eace-48ee-ae0e-0359e0ff6d0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116634089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2116634089
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.990931488
Short name T370
Test name
Test status
Simulation time 50879526412 ps
CPU time 74.68 seconds
Started Jul 06 05:00:29 PM PDT 24
Finished Jul 06 05:01:44 PM PDT 24
Peak memory 183116 kb
Host smart-49813206-9433-48e4-8efc-99eb0f6be2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990931488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.990931488
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1916469697
Short name T417
Test name
Test status
Simulation time 63911028411 ps
CPU time 103.58 seconds
Started Jul 06 05:00:28 PM PDT 24
Finished Jul 06 05:02:11 PM PDT 24
Peak memory 191240 kb
Host smart-e9e79482-b324-408e-ae03-6f19d8ae338e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916469697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1916469697
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1901284558
Short name T359
Test name
Test status
Simulation time 126555182 ps
CPU time 1.38 seconds
Started Jul 06 05:00:29 PM PDT 24
Finished Jul 06 05:00:31 PM PDT 24
Peak memory 183020 kb
Host smart-62b2dd92-5705-467f-a6a8-542347a9ae66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901284558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1901284558
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.1656255043
Short name T57
Test name
Test status
Simulation time 79358474 ps
CPU time 0.62 seconds
Started Jul 06 05:00:35 PM PDT 24
Finished Jul 06 05:00:36 PM PDT 24
Peak memory 182968 kb
Host smart-092ede77-0a5f-4431-83ce-5e3cfaad90fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656255043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.1656255043
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1862948594
Short name T219
Test name
Test status
Simulation time 57237131232 ps
CPU time 14.52 seconds
Started Jul 06 05:00:33 PM PDT 24
Finished Jul 06 05:00:48 PM PDT 24
Peak memory 183120 kb
Host smart-f5f27b6f-e4b5-4c3c-8b7c-f6db9f20f455
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862948594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1862948594
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.50615290
Short name T433
Test name
Test status
Simulation time 452672965637 ps
CPU time 96.75 seconds
Started Jul 06 05:00:34 PM PDT 24
Finished Jul 06 05:02:11 PM PDT 24
Peak memory 183136 kb
Host smart-59a1cb31-eceb-4f39-8341-2c403d9a1511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50615290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.50615290
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2564581114
Short name T304
Test name
Test status
Simulation time 291246915106 ps
CPU time 262.04 seconds
Started Jul 06 05:00:36 PM PDT 24
Finished Jul 06 05:04:59 PM PDT 24
Peak memory 191344 kb
Host smart-62369073-22fc-4353-a0c8-afcdfd821420
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564581114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2564581114
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3448939139
Short name T352
Test name
Test status
Simulation time 430036346565 ps
CPU time 2053.28 seconds
Started Jul 06 05:00:36 PM PDT 24
Finished Jul 06 05:34:49 PM PDT 24
Peak memory 191340 kb
Host smart-8e71d321-91c5-462f-8579-1ea7c00a5d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448939139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3448939139
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3260930347
Short name T317
Test name
Test status
Simulation time 17205116244 ps
CPU time 29.97 seconds
Started Jul 06 05:00:42 PM PDT 24
Finished Jul 06 05:01:12 PM PDT 24
Peak memory 183120 kb
Host smart-3424138d-e471-488d-8deb-ee0602b86002
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260930347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3260930347
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1715218787
Short name T447
Test name
Test status
Simulation time 115409734066 ps
CPU time 160.75 seconds
Started Jul 06 05:00:40 PM PDT 24
Finished Jul 06 05:03:21 PM PDT 24
Peak memory 183120 kb
Host smart-82395431-7e53-4d8c-8883-f00a1fa81c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715218787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1715218787
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.2400888556
Short name T446
Test name
Test status
Simulation time 227058607 ps
CPU time 0.6 seconds
Started Jul 06 05:00:40 PM PDT 24
Finished Jul 06 05:00:40 PM PDT 24
Peak memory 191480 kb
Host smart-724e916e-18d7-4517-9bf0-06f52e15c57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400888556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.2400888556
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.228504441
Short name T162
Test name
Test status
Simulation time 273347264884 ps
CPU time 216.9 seconds
Started Jul 06 05:00:40 PM PDT 24
Finished Jul 06 05:04:17 PM PDT 24
Peak memory 191316 kb
Host smart-b0806dcd-c119-436c-80dd-48dbab18c38b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228504441 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
228504441
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3744523120
Short name T377
Test name
Test status
Simulation time 161864107038 ps
CPU time 152.02 seconds
Started Jul 06 04:58:09 PM PDT 24
Finished Jul 06 05:00:41 PM PDT 24
Peak memory 183128 kb
Host smart-a8a5bfce-b865-41bc-bfb7-74d27c55c325
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744523120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3744523120
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1767761145
Short name T387
Test name
Test status
Simulation time 192683032123 ps
CPU time 235.83 seconds
Started Jul 06 04:58:04 PM PDT 24
Finished Jul 06 05:02:00 PM PDT 24
Peak memory 183116 kb
Host smart-b3738559-9ec3-4043-83ee-7e015f9953c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767761145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1767761145
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3833997499
Short name T236
Test name
Test status
Simulation time 101089374011 ps
CPU time 157.66 seconds
Started Jul 06 04:58:02 PM PDT 24
Finished Jul 06 05:00:40 PM PDT 24
Peak memory 191316 kb
Host smart-31905a18-d0df-466a-8ac6-24aa48efda55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833997499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3833997499
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.938609172
Short name T398
Test name
Test status
Simulation time 45643187 ps
CPU time 0.63 seconds
Started Jul 06 04:58:08 PM PDT 24
Finished Jul 06 04:58:09 PM PDT 24
Peak memory 182956 kb
Host smart-7ab98b99-2fdb-4de6-812f-7c7fa5201823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938609172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.938609172
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2324672650
Short name T346
Test name
Test status
Simulation time 895702974948 ps
CPU time 2336.87 seconds
Started Jul 06 04:58:09 PM PDT 24
Finished Jul 06 05:37:07 PM PDT 24
Peak memory 191340 kb
Host smart-b93b73b4-d56c-40f9-a113-325c8e081e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324672650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2324672650
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.108803725
Short name T264
Test name
Test status
Simulation time 678946959366 ps
CPU time 546.16 seconds
Started Jul 06 05:00:41 PM PDT 24
Finished Jul 06 05:09:48 PM PDT 24
Peak memory 191212 kb
Host smart-470cd046-7bc3-4033-bfcb-3a3f45887580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108803725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.108803725
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3542003593
Short name T300
Test name
Test status
Simulation time 509138176117 ps
CPU time 713.4 seconds
Started Jul 06 05:00:41 PM PDT 24
Finished Jul 06 05:12:35 PM PDT 24
Peak memory 191244 kb
Host smart-42f92f84-0c5e-46c4-a495-cc3069ca97e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542003593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3542003593
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.1254777734
Short name T261
Test name
Test status
Simulation time 111968558990 ps
CPU time 87.13 seconds
Started Jul 06 05:00:45 PM PDT 24
Finished Jul 06 05:02:12 PM PDT 24
Peak memory 191212 kb
Host smart-0da024eb-8c74-48b2-a6e2-eb572562ea62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254777734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.1254777734
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.79663318
Short name T451
Test name
Test status
Simulation time 241652492073 ps
CPU time 418.64 seconds
Started Jul 06 05:00:45 PM PDT 24
Finished Jul 06 05:07:44 PM PDT 24
Peak memory 191320 kb
Host smart-2e64d71d-a95c-499b-a40a-bc66898c0e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79663318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.79663318
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.170420270
Short name T438
Test name
Test status
Simulation time 208989781057 ps
CPU time 978.7 seconds
Started Jul 06 05:00:46 PM PDT 24
Finished Jul 06 05:17:05 PM PDT 24
Peak memory 191336 kb
Host smart-5186be4f-9dc6-4ba8-bcaf-7c0b9c0b39f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170420270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.170420270
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3668485781
Short name T408
Test name
Test status
Simulation time 22271736255 ps
CPU time 32.4 seconds
Started Jul 06 05:00:46 PM PDT 24
Finished Jul 06 05:01:18 PM PDT 24
Peak memory 183128 kb
Host smart-902d8df0-fa65-4972-9044-80b5a0e92e3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668485781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3668485781
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1373331662
Short name T397
Test name
Test status
Simulation time 52015160755 ps
CPU time 45.12 seconds
Started Jul 06 05:00:47 PM PDT 24
Finished Jul 06 05:01:32 PM PDT 24
Peak memory 183108 kb
Host smart-b3088a9f-b8d7-41b3-a655-4841c06b7cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373331662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1373331662
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2206401177
Short name T106
Test name
Test status
Simulation time 103934590299 ps
CPU time 85.72 seconds
Started Jul 06 05:00:47 PM PDT 24
Finished Jul 06 05:02:13 PM PDT 24
Peak memory 191240 kb
Host smart-843cb3a2-dd0e-44f3-a2ee-bfb09873dcec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206401177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2206401177
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.500549709
Short name T103
Test name
Test status
Simulation time 297023667758 ps
CPU time 301.72 seconds
Started Jul 06 05:00:47 PM PDT 24
Finished Jul 06 05:05:49 PM PDT 24
Peak memory 194716 kb
Host smart-e0da44d3-9eb4-436c-9a3c-33c77bcfc143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500549709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.500549709
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1409357279
Short name T207
Test name
Test status
Simulation time 502526033685 ps
CPU time 262.04 seconds
Started Jul 06 04:58:13 PM PDT 24
Finished Jul 06 05:02:35 PM PDT 24
Peak memory 183016 kb
Host smart-bb939fe9-8571-4e62-b8c4-2fd2765437dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409357279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1409357279
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.27085777
Short name T421
Test name
Test status
Simulation time 798764848102 ps
CPU time 223.24 seconds
Started Jul 06 04:58:11 PM PDT 24
Finished Jul 06 05:01:54 PM PDT 24
Peak memory 183144 kb
Host smart-34eb9d1a-ac9f-4955-a30e-8c00ea999c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27085777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.27085777
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3353863157
Short name T210
Test name
Test status
Simulation time 648235495525 ps
CPU time 337.49 seconds
Started Jul 06 04:58:13 PM PDT 24
Finished Jul 06 05:03:51 PM PDT 24
Peak memory 191216 kb
Host smart-fe5bd153-e32e-4ee3-a214-a5e6836ae8ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353863157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3353863157
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2997985917
Short name T146
Test name
Test status
Simulation time 318243646783 ps
CPU time 173.98 seconds
Started Jul 06 04:58:09 PM PDT 24
Finished Jul 06 05:01:04 PM PDT 24
Peak memory 191252 kb
Host smart-3b508e26-34fd-4b13-b5cf-20e05ed8552a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997985917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2997985917
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.2536729166
Short name T309
Test name
Test status
Simulation time 106639951660 ps
CPU time 212.65 seconds
Started Jul 06 05:00:45 PM PDT 24
Finished Jul 06 05:04:18 PM PDT 24
Peak memory 191212 kb
Host smart-4be470fb-6449-4cb7-ab33-a4adafc61def
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536729166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2536729166
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2236366827
Short name T176
Test name
Test status
Simulation time 62739375394 ps
CPU time 364.48 seconds
Started Jul 06 05:00:55 PM PDT 24
Finished Jul 06 05:07:00 PM PDT 24
Peak memory 191284 kb
Host smart-9f3452f7-2ebe-485e-beef-36390a41644f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236366827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2236366827
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3629650491
Short name T328
Test name
Test status
Simulation time 30479026705 ps
CPU time 92.88 seconds
Started Jul 06 05:00:55 PM PDT 24
Finished Jul 06 05:02:28 PM PDT 24
Peak memory 191344 kb
Host smart-40304378-1db8-4c8e-9880-a02c6cf65a80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629650491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3629650491
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.2023419861
Short name T224
Test name
Test status
Simulation time 30171901254 ps
CPU time 104.24 seconds
Started Jul 06 05:00:54 PM PDT 24
Finished Jul 06 05:02:39 PM PDT 24
Peak memory 183004 kb
Host smart-e9dbdf6b-b3bc-480d-bb08-2da36395d392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023419861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.2023419861
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3651997459
Short name T142
Test name
Test status
Simulation time 167898561337 ps
CPU time 366.96 seconds
Started Jul 06 05:00:55 PM PDT 24
Finished Jul 06 05:07:02 PM PDT 24
Peak memory 191284 kb
Host smart-f9877d2a-6cf0-410d-82fe-05aefffcc876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651997459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3651997459
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3837615820
Short name T116
Test name
Test status
Simulation time 506677586409 ps
CPU time 329.38 seconds
Started Jul 06 05:00:56 PM PDT 24
Finished Jul 06 05:06:25 PM PDT 24
Peak memory 194868 kb
Host smart-5b313903-d020-456f-bd88-5f04aba9871e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837615820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3837615820
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.168361670
Short name T220
Test name
Test status
Simulation time 248019910151 ps
CPU time 275.03 seconds
Started Jul 06 05:00:56 PM PDT 24
Finished Jul 06 05:05:31 PM PDT 24
Peak memory 191312 kb
Host smart-d2c54d42-a8f6-4126-bb88-0dabd525766e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168361670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.168361670
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2926869344
Short name T410
Test name
Test status
Simulation time 175517180829 ps
CPU time 81.26 seconds
Started Jul 06 05:00:54 PM PDT 24
Finished Jul 06 05:02:16 PM PDT 24
Peak memory 183140 kb
Host smart-51fecbfb-3d67-474b-94d8-6e3d706b8633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926869344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2926869344
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.831127794
Short name T2
Test name
Test status
Simulation time 280350308738 ps
CPU time 166.78 seconds
Started Jul 06 05:00:54 PM PDT 24
Finished Jul 06 05:03:41 PM PDT 24
Peak memory 191304 kb
Host smart-553b6ba3-350d-4d48-a51c-2ccbd0e8fe65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831127794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.831127794
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1505690242
Short name T113
Test name
Test status
Simulation time 62906599069 ps
CPU time 109.42 seconds
Started Jul 06 04:58:10 PM PDT 24
Finished Jul 06 05:00:00 PM PDT 24
Peak memory 183004 kb
Host smart-3ef357e0-83dc-4ded-b5fd-6e5e5d179197
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505690242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1505690242
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.426023532
Short name T443
Test name
Test status
Simulation time 118765767987 ps
CPU time 167.88 seconds
Started Jul 06 04:58:10 PM PDT 24
Finished Jul 06 05:00:59 PM PDT 24
Peak memory 183144 kb
Host smart-435c6820-164d-454d-a7a4-4f8d174a2475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426023532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.426023532
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3066978122
Short name T213
Test name
Test status
Simulation time 159777449254 ps
CPU time 258.59 seconds
Started Jul 06 04:58:09 PM PDT 24
Finished Jul 06 05:02:29 PM PDT 24
Peak memory 191272 kb
Host smart-976259b8-8e65-471b-9e8f-4d880fc29ab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066978122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3066978122
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.187730537
Short name T366
Test name
Test status
Simulation time 533636218 ps
CPU time 1.96 seconds
Started Jul 06 04:58:12 PM PDT 24
Finished Jul 06 04:58:14 PM PDT 24
Peak memory 183028 kb
Host smart-1dcad10e-7fcf-40be-8240-e3566ef413a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187730537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.187730537
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1877925227
Short name T429
Test name
Test status
Simulation time 88151837 ps
CPU time 0.59 seconds
Started Jul 06 04:58:10 PM PDT 24
Finished Jul 06 04:58:11 PM PDT 24
Peak memory 182932 kb
Host smart-1cbf3b5b-81ea-4c0a-96c8-67e7e66c2e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877925227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1877925227
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.395719846
Short name T409
Test name
Test status
Simulation time 34698680751 ps
CPU time 357.45 seconds
Started Jul 06 04:58:10 PM PDT 24
Finished Jul 06 05:04:08 PM PDT 24
Peak memory 197704 kb
Host smart-0da2179d-961d-4ef6-ac3a-e57025803cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395719846 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.395719846
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2063194091
Short name T181
Test name
Test status
Simulation time 190147980166 ps
CPU time 1611.94 seconds
Started Jul 06 05:00:54 PM PDT 24
Finished Jul 06 05:27:46 PM PDT 24
Peak memory 191208 kb
Host smart-4db79f6e-a61d-49ee-9897-685642f02bb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063194091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2063194091
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.4222383370
Short name T445
Test name
Test status
Simulation time 518959513904 ps
CPU time 207.14 seconds
Started Jul 06 05:00:54 PM PDT 24
Finished Jul 06 05:04:22 PM PDT 24
Peak memory 191224 kb
Host smart-c1f6d51e-0c6e-470b-a22a-58e081895291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222383370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.4222383370
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1221375978
Short name T415
Test name
Test status
Simulation time 146150818585 ps
CPU time 216.74 seconds
Started Jul 06 05:00:55 PM PDT 24
Finished Jul 06 05:04:32 PM PDT 24
Peak memory 193688 kb
Host smart-c933dcd5-ef4c-4fd6-8c3c-58679f60e736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221375978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1221375978
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3270182472
Short name T126
Test name
Test status
Simulation time 731759394963 ps
CPU time 497.67 seconds
Started Jul 06 05:00:56 PM PDT 24
Finished Jul 06 05:09:14 PM PDT 24
Peak memory 191336 kb
Host smart-198170a2-e438-4c21-8952-bb3ae1338246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270182472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3270182472
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1736870876
Short name T423
Test name
Test status
Simulation time 63772742351 ps
CPU time 235.13 seconds
Started Jul 06 05:00:58 PM PDT 24
Finished Jul 06 05:04:54 PM PDT 24
Peak memory 183032 kb
Host smart-7d680750-ab0c-46b4-95aa-1ddbbd9c0474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736870876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1736870876
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.932729049
Short name T305
Test name
Test status
Simulation time 262739296175 ps
CPU time 120.09 seconds
Started Jul 06 05:00:58 PM PDT 24
Finished Jul 06 05:02:58 PM PDT 24
Peak memory 191308 kb
Host smart-77f89b6d-3796-4a24-a9ec-5660fad71e54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932729049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.932729049
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.4204859926
Short name T161
Test name
Test status
Simulation time 33511909880 ps
CPU time 55.34 seconds
Started Jul 06 05:00:58 PM PDT 24
Finished Jul 06 05:01:54 PM PDT 24
Peak memory 183036 kb
Host smart-3a1ace1f-a288-4dbd-a635-0d2c3a7979be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204859926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4204859926
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.403807310
Short name T20
Test name
Test status
Simulation time 567021103456 ps
CPU time 249.78 seconds
Started Jul 06 05:00:59 PM PDT 24
Finished Jul 06 05:05:09 PM PDT 24
Peak memory 194848 kb
Host smart-ef1566ba-595b-498b-b956-8b70e64b8035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403807310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.403807310
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2694275357
Short name T425
Test name
Test status
Simulation time 59781960447 ps
CPU time 101.91 seconds
Started Jul 06 05:00:57 PM PDT 24
Finished Jul 06 05:02:39 PM PDT 24
Peak memory 191284 kb
Host smart-832f8492-9c13-44a9-86a9-02a0f98a8cfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694275357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2694275357
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2798526702
Short name T145
Test name
Test status
Simulation time 16874659357 ps
CPU time 26.28 seconds
Started Jul 06 04:58:13 PM PDT 24
Finished Jul 06 04:58:39 PM PDT 24
Peak memory 183112 kb
Host smart-4d526e07-103d-4939-8e24-8d541850fca4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798526702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2798526702
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.797597728
Short name T107
Test name
Test status
Simulation time 8272622389 ps
CPU time 12.45 seconds
Started Jul 06 04:58:11 PM PDT 24
Finished Jul 06 04:58:24 PM PDT 24
Peak memory 182988 kb
Host smart-9245e46d-e280-4eb0-9675-1e64f9c26158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797597728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.797597728
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.169594914
Short name T419
Test name
Test status
Simulation time 309139167536 ps
CPU time 111.84 seconds
Started Jul 06 04:58:13 PM PDT 24
Finished Jul 06 05:00:05 PM PDT 24
Peak memory 191316 kb
Host smart-1fbe38a1-4202-4bf0-99e0-91d3c6eea657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169594914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.169594914
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2631975270
Short name T420
Test name
Test status
Simulation time 26996706546 ps
CPU time 43.25 seconds
Started Jul 06 04:58:10 PM PDT 24
Finished Jul 06 04:58:54 PM PDT 24
Peak memory 191340 kb
Host smart-008ffcb1-7d4c-407d-845d-8547a1d4b3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631975270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2631975270
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.3944411539
Short name T43
Test name
Test status
Simulation time 62435685298 ps
CPU time 228.72 seconds
Started Jul 06 04:58:08 PM PDT 24
Finished Jul 06 05:01:57 PM PDT 24
Peak memory 197812 kb
Host smart-289655f2-8c42-411b-b17c-f635eb6ff20d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944411539 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.3944411539
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.2737387131
Short name T333
Test name
Test status
Simulation time 111456518957 ps
CPU time 306.7 seconds
Started Jul 06 05:00:58 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 194712 kb
Host smart-3d891b90-991e-4651-9c79-11e5a6e14676
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737387131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2737387131
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2588116134
Short name T147
Test name
Test status
Simulation time 425601240065 ps
CPU time 156.23 seconds
Started Jul 06 05:00:58 PM PDT 24
Finished Jul 06 05:03:34 PM PDT 24
Peak memory 191180 kb
Host smart-30be88f1-af29-408f-bde9-9377d2e41a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588116134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2588116134
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2341407926
Short name T315
Test name
Test status
Simulation time 145415283022 ps
CPU time 71.27 seconds
Started Jul 06 05:00:58 PM PDT 24
Finished Jul 06 05:02:09 PM PDT 24
Peak memory 183116 kb
Host smart-6f8ff24d-6496-4682-b57a-15a00f0d2895
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341407926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2341407926
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1410594282
Short name T171
Test name
Test status
Simulation time 130895182674 ps
CPU time 30.33 seconds
Started Jul 06 05:00:58 PM PDT 24
Finished Jul 06 05:01:29 PM PDT 24
Peak memory 183024 kb
Host smart-aa6eafb7-e5e2-4901-9e3b-6dd3347291ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410594282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1410594282
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.258474932
Short name T324
Test name
Test status
Simulation time 34739806861 ps
CPU time 13.3 seconds
Started Jul 06 05:00:56 PM PDT 24
Finished Jul 06 05:01:10 PM PDT 24
Peak memory 183132 kb
Host smart-09e6fbd9-e77e-4422-983a-86580fabce27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258474932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.258474932
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.691576319
Short name T189
Test name
Test status
Simulation time 627439756720 ps
CPU time 495.28 seconds
Started Jul 06 05:00:59 PM PDT 24
Finished Jul 06 05:09:14 PM PDT 24
Peak memory 191244 kb
Host smart-2e745524-0e27-421e-a6b8-307a40bb5f06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691576319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.691576319
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3205699325
Short name T165
Test name
Test status
Simulation time 72477616408 ps
CPU time 143.73 seconds
Started Jul 06 05:01:04 PM PDT 24
Finished Jul 06 05:03:28 PM PDT 24
Peak memory 183148 kb
Host smart-af23f0a1-fa03-4a84-9aed-91516c57069f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205699325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3205699325
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3970066903
Short name T332
Test name
Test status
Simulation time 454892941585 ps
CPU time 697.83 seconds
Started Jul 06 05:01:04 PM PDT 24
Finished Jul 06 05:12:42 PM PDT 24
Peak memory 191336 kb
Host smart-07f99280-a1f7-4bb6-9a83-6235b17864dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970066903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3970066903
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3693521595
Short name T344
Test name
Test status
Simulation time 48472094732 ps
CPU time 1815.91 seconds
Started Jul 06 05:01:05 PM PDT 24
Finished Jul 06 05:31:22 PM PDT 24
Peak memory 182980 kb
Host smart-84b97fa7-3c8a-412c-9ab9-b7ee66a6daae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693521595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3693521595
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3881933373
Short name T200
Test name
Test status
Simulation time 235995535766 ps
CPU time 316.2 seconds
Started Jul 06 05:01:03 PM PDT 24
Finished Jul 06 05:06:19 PM PDT 24
Peak memory 191184 kb
Host smart-35767721-d596-4ae4-a2bf-6f63d645d143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881933373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3881933373
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2143070378
Short name T422
Test name
Test status
Simulation time 112687387010 ps
CPU time 172.3 seconds
Started Jul 06 04:58:12 PM PDT 24
Finished Jul 06 05:01:04 PM PDT 24
Peak memory 182988 kb
Host smart-ab43f329-ee95-4cf2-9103-51dc359d2a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143070378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2143070378
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3901769647
Short name T347
Test name
Test status
Simulation time 41967883136 ps
CPU time 121.92 seconds
Started Jul 06 04:58:13 PM PDT 24
Finished Jul 06 05:00:15 PM PDT 24
Peak memory 191224 kb
Host smart-f247d981-3cf0-4699-9a75-575d3c309694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901769647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3901769647
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1490904055
Short name T144
Test name
Test status
Simulation time 240078675801 ps
CPU time 107.37 seconds
Started Jul 06 04:58:10 PM PDT 24
Finished Jul 06 04:59:58 PM PDT 24
Peak memory 183136 kb
Host smart-8867fb26-5856-4da8-84f8-a2eaa9edd290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490904055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1490904055
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2188440665
Short name T36
Test name
Test status
Simulation time 36645520772 ps
CPU time 183.86 seconds
Started Jul 06 04:58:11 PM PDT 24
Finished Jul 06 05:01:15 PM PDT 24
Peak memory 197776 kb
Host smart-a3e09bf5-9fcc-4c2e-9926-5b5dbf4d0ab5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188440665 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2188440665
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.904295549
Short name T229
Test name
Test status
Simulation time 472708477602 ps
CPU time 693.55 seconds
Started Jul 06 05:01:04 PM PDT 24
Finished Jul 06 05:12:37 PM PDT 24
Peak memory 191316 kb
Host smart-0eedf43c-5544-4bf0-9d87-5e0000c553ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904295549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.904295549
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.4192135904
Short name T251
Test name
Test status
Simulation time 370569104685 ps
CPU time 1154.58 seconds
Started Jul 06 05:01:09 PM PDT 24
Finished Jul 06 05:20:24 PM PDT 24
Peak memory 191212 kb
Host smart-b95368dc-cf90-404e-9427-a2430ccd10f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192135904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.4192135904
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3846417954
Short name T202
Test name
Test status
Simulation time 73068136968 ps
CPU time 31.26 seconds
Started Jul 06 05:01:10 PM PDT 24
Finished Jul 06 05:01:41 PM PDT 24
Peak memory 183116 kb
Host smart-11a14657-9a47-4b5e-a3b4-f9f0dc7f50e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846417954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3846417954
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.583480687
Short name T185
Test name
Test status
Simulation time 317707548309 ps
CPU time 302.76 seconds
Started Jul 06 05:01:09 PM PDT 24
Finished Jul 06 05:06:12 PM PDT 24
Peak memory 191308 kb
Host smart-ab445a6d-4707-443d-a220-92085f7cfa26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583480687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.583480687
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2495817909
Short name T357
Test name
Test status
Simulation time 325111464298 ps
CPU time 296.19 seconds
Started Jul 06 05:01:08 PM PDT 24
Finished Jul 06 05:06:05 PM PDT 24
Peak memory 183088 kb
Host smart-3ba0389d-23f6-4d63-b0ea-0da0df3c7afb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495817909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2495817909
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2075582453
Short name T249
Test name
Test status
Simulation time 728063521867 ps
CPU time 1397.8 seconds
Started Jul 06 05:01:09 PM PDT 24
Finished Jul 06 05:24:27 PM PDT 24
Peak memory 191344 kb
Host smart-ca897455-59cd-4b2e-b22a-9b115e4f5a10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075582453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2075582453
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3953748096
Short name T22
Test name
Test status
Simulation time 771606347780 ps
CPU time 1369.3 seconds
Started Jul 06 05:01:10 PM PDT 24
Finished Jul 06 05:24:00 PM PDT 24
Peak memory 182988 kb
Host smart-4e488512-b981-493e-a745-9bf3028f98bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953748096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3953748096
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2447363962
Short name T322
Test name
Test status
Simulation time 152302903155 ps
CPU time 416.26 seconds
Started Jul 06 05:01:10 PM PDT 24
Finished Jul 06 05:08:07 PM PDT 24
Peak memory 191344 kb
Host smart-46e13b34-c757-4759-a790-8fd74c09fadd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447363962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2447363962
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2041096498
Short name T119
Test name
Test status
Simulation time 406930999721 ps
CPU time 201.57 seconds
Started Jul 06 05:01:09 PM PDT 24
Finished Jul 06 05:04:31 PM PDT 24
Peak memory 191224 kb
Host smart-0f430d60-eb37-4661-8386-3f8eb41d289e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041096498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2041096498
Directory /workspace/99.rv_timer_random/latest
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