Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00
Crosses 6 0 6 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 1 0 1 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 6 0 6 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 1391 1 T2 28 T4 10 T13 20



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 733 1 T2 24 T4 3 T13 12
auto[1] 658 1 T2 4 T4 7 T13 8



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 522 1 T2 9 T4 6 T13 5
auto[1] 869 1 T2 19 T4 4 T13 15



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 796 1 T2 15 T4 7 T13 10
auto[1] 595 1 T2 13 T4 3 T13 10



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 264 1 T2 8 T4 1 T13 3
all_values[0] auto[0] auto[0] auto[1] 142 1 T2 5 T13 3 T97 4
all_values[0] auto[0] auto[1] auto[0] 258 1 T2 1 T4 5 T13 2
all_values[0] auto[0] auto[1] auto[1] 132 1 T2 1 T4 1 T13 2
all_values[0] auto[1] auto[0] auto[1] 327 1 T2 11 T4 2 T13 6
all_values[0] auto[1] auto[1] auto[1] 268 1 T2 2 T4 1 T13 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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