Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.53 99.36 98.73 100.00 100.00 100.00 99.09


Total test records in report: 581
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T507 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3175694077 Jul 07 06:00:13 PM PDT 24 Jul 07 06:00:15 PM PDT 24 142778482 ps
T508 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.365247997 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:11 PM PDT 24 38972068 ps
T509 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.888299184 Jul 07 06:00:23 PM PDT 24 Jul 07 06:00:24 PM PDT 24 72356742 ps
T510 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3854530292 Jul 07 06:00:11 PM PDT 24 Jul 07 06:00:13 PM PDT 24 162530565 ps
T511 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.749965751 Jul 07 06:00:00 PM PDT 24 Jul 07 06:00:01 PM PDT 24 96410466 ps
T512 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2232941254 Jul 07 06:00:06 PM PDT 24 Jul 07 06:00:07 PM PDT 24 19122360 ps
T513 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2828938382 Jul 07 06:00:28 PM PDT 24 Jul 07 06:00:29 PM PDT 24 15865950 ps
T514 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3827290863 Jul 07 06:00:04 PM PDT 24 Jul 07 06:00:08 PM PDT 24 45424964 ps
T515 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.359770793 Jul 07 06:00:15 PM PDT 24 Jul 07 06:00:17 PM PDT 24 157162577 ps
T516 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3411520631 Jul 07 06:00:19 PM PDT 24 Jul 07 06:00:20 PM PDT 24 16634176 ps
T71 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3259291005 Jul 07 06:00:04 PM PDT 24 Jul 07 06:00:09 PM PDT 24 2266550330 ps
T517 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.908280862 Jul 07 06:00:12 PM PDT 24 Jul 07 06:00:14 PM PDT 24 125155785 ps
T518 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2434807293 Jul 07 06:00:22 PM PDT 24 Jul 07 06:00:23 PM PDT 24 13802407 ps
T519 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2337257031 Jul 07 06:00:27 PM PDT 24 Jul 07 06:00:28 PM PDT 24 15328445 ps
T70 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4169124243 Jul 07 06:00:17 PM PDT 24 Jul 07 06:00:18 PM PDT 24 33879273 ps
T520 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4039940115 Jul 07 06:00:01 PM PDT 24 Jul 07 06:00:05 PM PDT 24 61170842 ps
T93 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2198844096 Jul 07 06:00:14 PM PDT 24 Jul 07 06:00:17 PM PDT 24 220766975 ps
T521 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.879878825 Jul 07 06:00:15 PM PDT 24 Jul 07 06:00:17 PM PDT 24 59246706 ps
T522 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2829360656 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:10 PM PDT 24 92975996 ps
T523 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1567166054 Jul 07 06:00:11 PM PDT 24 Jul 07 06:00:13 PM PDT 24 525825443 ps
T524 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1756768003 Jul 07 06:00:15 PM PDT 24 Jul 07 06:00:20 PM PDT 24 623195668 ps
T525 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1975024187 Jul 07 06:00:23 PM PDT 24 Jul 07 06:00:24 PM PDT 24 21864089 ps
T526 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.500265898 Jul 07 06:00:25 PM PDT 24 Jul 07 06:00:26 PM PDT 24 11125343 ps
T527 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1031414682 Jul 07 06:00:19 PM PDT 24 Jul 07 06:00:20 PM PDT 24 46725128 ps
T528 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3548955132 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:10 PM PDT 24 23529579 ps
T529 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2839141992 Jul 07 06:00:11 PM PDT 24 Jul 07 06:00:12 PM PDT 24 59983307 ps
T530 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3772636481 Jul 07 06:00:16 PM PDT 24 Jul 07 06:00:19 PM PDT 24 817195001 ps
T531 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3102275823 Jul 07 06:00:10 PM PDT 24 Jul 07 06:00:11 PM PDT 24 17043940 ps
T72 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.117574494 Jul 07 06:00:02 PM PDT 24 Jul 07 06:00:03 PM PDT 24 111277744 ps
T532 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2785404995 Jul 07 06:00:04 PM PDT 24 Jul 07 06:00:05 PM PDT 24 236852961 ps
T533 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.668308763 Jul 07 06:00:00 PM PDT 24 Jul 07 06:00:01 PM PDT 24 145272815 ps
T534 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1791519998 Jul 07 06:00:29 PM PDT 24 Jul 07 06:00:30 PM PDT 24 24075326 ps
T535 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1412044568 Jul 07 06:00:15 PM PDT 24 Jul 07 06:00:18 PM PDT 24 115815504 ps
T536 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1765259889 Jul 07 06:00:10 PM PDT 24 Jul 07 06:00:12 PM PDT 24 47313270 ps
T74 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1100327892 Jul 07 06:00:09 PM PDT 24 Jul 07 06:00:10 PM PDT 24 33952064 ps
T73 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3242406757 Jul 07 06:00:06 PM PDT 24 Jul 07 06:00:09 PM PDT 24 1187235268 ps
T537 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3186906707 Jul 07 06:00:05 PM PDT 24 Jul 07 06:00:09 PM PDT 24 1604477067 ps
T538 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3412725046 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:10 PM PDT 24 25081676 ps
T539 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.79094963 Jul 07 06:00:02 PM PDT 24 Jul 07 06:00:03 PM PDT 24 17016965 ps
T540 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1038974327 Jul 07 06:00:14 PM PDT 24 Jul 07 06:00:15 PM PDT 24 24003136 ps
T541 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3343787053 Jul 07 06:00:16 PM PDT 24 Jul 07 06:00:18 PM PDT 24 18422105 ps
T542 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2256164620 Jul 07 06:00:21 PM PDT 24 Jul 07 06:00:21 PM PDT 24 12222649 ps
T543 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2364664569 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:10 PM PDT 24 31427544 ps
T544 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.555985483 Jul 07 06:00:03 PM PDT 24 Jul 07 06:00:05 PM PDT 24 276872531 ps
T545 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1084878100 Jul 07 06:00:18 PM PDT 24 Jul 07 06:00:20 PM PDT 24 34002888 ps
T546 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1537262431 Jul 07 06:00:12 PM PDT 24 Jul 07 06:00:15 PM PDT 24 124914350 ps
T547 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3389607361 Jul 07 06:00:24 PM PDT 24 Jul 07 06:00:26 PM PDT 24 57207954 ps
T548 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.913155691 Jul 07 06:00:13 PM PDT 24 Jul 07 06:00:15 PM PDT 24 124954672 ps
T549 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.400811031 Jul 07 06:00:03 PM PDT 24 Jul 07 06:00:04 PM PDT 24 32127630 ps
T550 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3554253292 Jul 07 06:00:00 PM PDT 24 Jul 07 06:00:01 PM PDT 24 33131620 ps
T551 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2984483533 Jul 07 06:00:01 PM PDT 24 Jul 07 06:00:04 PM PDT 24 201179384 ps
T552 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4261020276 Jul 07 06:00:22 PM PDT 24 Jul 07 06:00:23 PM PDT 24 33273467 ps
T553 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1477242436 Jul 07 06:00:16 PM PDT 24 Jul 07 06:00:17 PM PDT 24 49736595 ps
T554 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.735622026 Jul 07 06:00:13 PM PDT 24 Jul 07 06:00:14 PM PDT 24 163894571 ps
T555 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1602793537 Jul 07 06:00:26 PM PDT 24 Jul 07 06:00:27 PM PDT 24 43791959 ps
T556 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3109930523 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:10 PM PDT 24 41098461 ps
T557 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.617818730 Jul 07 06:00:09 PM PDT 24 Jul 07 06:00:10 PM PDT 24 23683921 ps
T558 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3449416082 Jul 07 06:00:20 PM PDT 24 Jul 07 06:00:21 PM PDT 24 26961077 ps
T559 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2385287956 Jul 07 06:00:13 PM PDT 24 Jul 07 06:00:15 PM PDT 24 291306603 ps
T560 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1967681179 Jul 07 06:00:26 PM PDT 24 Jul 07 06:00:27 PM PDT 24 21096832 ps
T561 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3733375691 Jul 07 06:00:10 PM PDT 24 Jul 07 06:00:11 PM PDT 24 32514113 ps
T562 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1693045323 Jul 07 06:00:01 PM PDT 24 Jul 07 06:00:01 PM PDT 24 34304356 ps
T563 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2348129369 Jul 07 06:00:15 PM PDT 24 Jul 07 06:00:18 PM PDT 24 367054533 ps
T564 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1334085603 Jul 07 06:00:22 PM PDT 24 Jul 07 06:00:23 PM PDT 24 38312417 ps
T565 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2866407138 Jul 07 06:00:10 PM PDT 24 Jul 07 06:00:12 PM PDT 24 40887937 ps
T566 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2304090128 Jul 07 06:00:18 PM PDT 24 Jul 07 06:00:20 PM PDT 24 75620358 ps
T567 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1643316557 Jul 07 06:00:29 PM PDT 24 Jul 07 06:00:29 PM PDT 24 23354524 ps
T568 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1831576881 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:10 PM PDT 24 151715444 ps
T569 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.112286653 Jul 07 06:00:15 PM PDT 24 Jul 07 06:00:17 PM PDT 24 40169765 ps
T570 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3349034646 Jul 07 06:00:14 PM PDT 24 Jul 07 06:00:17 PM PDT 24 351811810 ps
T571 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2032728950 Jul 07 05:59:59 PM PDT 24 Jul 07 06:00:00 PM PDT 24 49494259 ps
T572 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3972878739 Jul 07 06:00:13 PM PDT 24 Jul 07 06:00:14 PM PDT 24 16443990 ps
T573 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1715030291 Jul 07 06:00:23 PM PDT 24 Jul 07 06:00:24 PM PDT 24 42427938 ps
T574 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1623824280 Jul 07 06:00:13 PM PDT 24 Jul 07 06:00:15 PM PDT 24 311749161 ps
T575 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2472822607 Jul 07 06:00:13 PM PDT 24 Jul 07 06:00:14 PM PDT 24 20459784 ps
T576 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1838695899 Jul 07 06:00:24 PM PDT 24 Jul 07 06:00:25 PM PDT 24 35196638 ps
T577 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2117102644 Jul 07 06:00:04 PM PDT 24 Jul 07 06:00:07 PM PDT 24 242158971 ps
T578 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.608379562 Jul 07 06:00:24 PM PDT 24 Jul 07 06:00:25 PM PDT 24 25000791 ps
T579 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.325474230 Jul 07 06:00:17 PM PDT 24 Jul 07 06:00:18 PM PDT 24 36845643 ps
T580 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1743403965 Jul 07 06:00:19 PM PDT 24 Jul 07 06:00:20 PM PDT 24 24854930 ps
T581 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.891587862 Jul 07 06:00:23 PM PDT 24 Jul 07 06:00:24 PM PDT 24 175368982 ps

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.58090242
Short name T2
Test name
Test status
Simulation time 44877383367 ps
CPU time 110.48 seconds
Started Jul 07 06:07:49 PM PDT 24
Finished Jul 07 06:09:40 PM PDT 24
Peak memory 197876 kb
Host smart-6ef75e9c-f5be-44b3-9581-5eb920dc1f4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58090242 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.58090242
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.rv_timer_random.2600446397
Short name T99
Test name
Test status
Simulation time 939604849268 ps
CPU time 765.91 seconds
Started Jul 07 06:06:04 PM PDT 24
Finished Jul 07 06:18:50 PM PDT 24
Peak memory 191364 kb
Host smart-856662a3-7b7f-4a52-8bd7-58c2c0017f47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600446397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2600446397
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2068390689
Short name T1
Test name
Test status
Simulation time 382742676180 ps
CPU time 983.91 seconds
Started Jul 07 06:07:43 PM PDT 24
Finished Jul 07 06:24:07 PM PDT 24
Peak memory 183140 kb
Host smart-e5ae4ec3-2595-4c5c-a7a0-0b5510800683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068390689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2068390689
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2594872542
Short name T149
Test name
Test status
Simulation time 2236375603916 ps
CPU time 3073.9 seconds
Started Jul 07 06:05:50 PM PDT 24
Finished Jul 07 06:57:04 PM PDT 24
Peak memory 196152 kb
Host smart-5a3d29d2-8d8a-40a2-938e-84f91542978c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594872542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2594872542
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2629055453
Short name T22
Test name
Test status
Simulation time 77616517 ps
CPU time 0.87 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:18 PM PDT 24
Peak memory 193140 kb
Host smart-cb314e8a-6733-4826-9244-787c2e08182c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629055453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2629055453
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.61328201
Short name T57
Test name
Test status
Simulation time 1145472810268 ps
CPU time 2237.15 seconds
Started Jul 07 06:06:28 PM PDT 24
Finished Jul 07 06:43:46 PM PDT 24
Peak memory 191212 kb
Host smart-9eb7880d-7cf4-473e-b41a-1025b958cf0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61328201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.61328201
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3772246143
Short name T170
Test name
Test status
Simulation time 899567720047 ps
CPU time 1908.65 seconds
Started Jul 07 06:07:46 PM PDT 24
Finished Jul 07 06:39:35 PM PDT 24
Peak memory 191284 kb
Host smart-82c8630d-518a-4e7a-afc0-18bb7ec4cdcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772246143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3772246143
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.4274481641
Short name T260
Test name
Test status
Simulation time 610119053388 ps
CPU time 3070.38 seconds
Started Jul 07 06:05:55 PM PDT 24
Finished Jul 07 06:57:06 PM PDT 24
Peak memory 191588 kb
Host smart-3b4e9ba0-fa20-49b2-a1f4-2d2879351b97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274481641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
4274481641
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.1439234376
Short name T50
Test name
Test status
Simulation time 805962871019 ps
CPU time 1451.86 seconds
Started Jul 07 06:08:05 PM PDT 24
Finished Jul 07 06:32:18 PM PDT 24
Peak memory 195244 kb
Host smart-29ed5ec1-1699-4af2-ba85-27bfe834224e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439234376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.1439234376
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1941815739
Short name T26
Test name
Test status
Simulation time 14401399 ps
CPU time 0.61 seconds
Started Jul 07 06:00:02 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 182320 kb
Host smart-d823f3aa-0acf-4f17-b184-62f171229498
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941815739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1941815739
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2287627363
Short name T185
Test name
Test status
Simulation time 2169840464748 ps
CPU time 1713.97 seconds
Started Jul 07 06:05:31 PM PDT 24
Finished Jul 07 06:34:05 PM PDT 24
Peak memory 191312 kb
Host smart-4f47790e-050b-4471-a946-889356029aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287627363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2287627363
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.645614961
Short name T291
Test name
Test status
Simulation time 558401286311 ps
CPU time 1673.83 seconds
Started Jul 07 06:06:48 PM PDT 24
Finished Jul 07 06:34:42 PM PDT 24
Peak memory 191320 kb
Host smart-2f2329a3-6a27-47c1-9f50-421105f0ed38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645614961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
645614961
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1223677206
Short name T123
Test name
Test status
Simulation time 1478327674127 ps
CPU time 1822.51 seconds
Started Jul 07 06:05:43 PM PDT 24
Finished Jul 07 06:36:06 PM PDT 24
Peak memory 191320 kb
Host smart-ca623c99-50b0-448c-a09f-1383c2c1f2aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223677206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1223677206
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3335878446
Short name T18
Test name
Test status
Simulation time 368578405 ps
CPU time 0.83 seconds
Started Jul 07 06:05:23 PM PDT 24
Finished Jul 07 06:05:25 PM PDT 24
Peak memory 213496 kb
Host smart-388f3e24-091f-404e-a93f-b2d12ce4cae3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335878446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3335878446
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/196.rv_timer_random.2967511742
Short name T153
Test name
Test status
Simulation time 109306900430 ps
CPU time 196.61 seconds
Started Jul 07 06:09:58 PM PDT 24
Finished Jul 07 06:13:15 PM PDT 24
Peak memory 191368 kb
Host smart-1312e931-b00b-4e93-a5c7-b55b164c43eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967511742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2967511742
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4077236494
Short name T109
Test name
Test status
Simulation time 225052478821 ps
CPU time 467.69 seconds
Started Jul 07 06:07:19 PM PDT 24
Finished Jul 07 06:15:07 PM PDT 24
Peak memory 191368 kb
Host smart-643e1d7a-8d1e-41c6-a16f-0eb6a9c554d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077236494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4077236494
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.590533293
Short name T39
Test name
Test status
Simulation time 31382887 ps
CPU time 0.69 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 191876 kb
Host smart-1b2f811e-4f50-47f4-80f8-f667b752d326
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590533293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.590533293
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3108711228
Short name T51
Test name
Test status
Simulation time 401921449643 ps
CPU time 525.21 seconds
Started Jul 07 06:08:16 PM PDT 24
Finished Jul 07 06:17:01 PM PDT 24
Peak memory 191344 kb
Host smart-368673db-c10c-4428-8d64-4c9e3b3a67c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108711228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3108711228
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_random.899642375
Short name T8
Test name
Test status
Simulation time 172623314641 ps
CPU time 268.13 seconds
Started Jul 07 06:08:16 PM PDT 24
Finished Jul 07 06:12:44 PM PDT 24
Peak memory 191276 kb
Host smart-8459bbfd-518d-4a1a-bbdb-e224e93131a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899642375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.899642375
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.830101654
Short name T160
Test name
Test status
Simulation time 869592200781 ps
CPU time 2969 seconds
Started Jul 07 06:08:19 PM PDT 24
Finished Jul 07 06:57:49 PM PDT 24
Peak memory 196752 kb
Host smart-925540f1-1f55-4da3-8b89-32c5c929b8d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830101654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
830101654
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/169.rv_timer_random.2471029164
Short name T271
Test name
Test status
Simulation time 218957912517 ps
CPU time 342.11 seconds
Started Jul 07 06:09:39 PM PDT 24
Finished Jul 07 06:15:21 PM PDT 24
Peak memory 191328 kb
Host smart-01a27b43-8adf-4686-b8da-5a0fd877451a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471029164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.2471029164
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3813159945
Short name T295
Test name
Test status
Simulation time 532863263558 ps
CPU time 1976.48 seconds
Started Jul 07 06:06:10 PM PDT 24
Finished Jul 07 06:39:06 PM PDT 24
Peak memory 191592 kb
Host smart-799f4bfa-5b53-4ac1-80db-c2ddd54602e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813159945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3813159945
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3901616657
Short name T152
Test name
Test status
Simulation time 452173387799 ps
CPU time 1020.56 seconds
Started Jul 07 06:06:40 PM PDT 24
Finished Jul 07 06:23:41 PM PDT 24
Peak memory 195528 kb
Host smart-7af89418-4cee-4558-9330-17c1fcfa8aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901616657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3901616657
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/193.rv_timer_random.1490041771
Short name T213
Test name
Test status
Simulation time 570966512951 ps
CPU time 834.44 seconds
Started Jul 07 06:09:59 PM PDT 24
Finished Jul 07 06:23:53 PM PDT 24
Peak memory 191272 kb
Host smart-be870462-1207-468a-be8c-6e6951a1aff9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490041771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1490041771
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.1171553557
Short name T246
Test name
Test status
Simulation time 216875570481 ps
CPU time 662.08 seconds
Started Jul 07 06:08:53 PM PDT 24
Finished Jul 07 06:19:56 PM PDT 24
Peak memory 195276 kb
Host smart-2c51650c-1ff7-450f-a8e8-f2f778a6df2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171553557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.1171553557
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.777344299
Short name T192
Test name
Test status
Simulation time 686457613479 ps
CPU time 359.43 seconds
Started Jul 07 06:09:34 PM PDT 24
Finished Jul 07 06:15:34 PM PDT 24
Peak memory 191324 kb
Host smart-3cb7344b-c4ef-4d4f-91a6-684a4a7d9784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777344299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.777344299
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1815518273
Short name T135
Test name
Test status
Simulation time 463373852020 ps
CPU time 251.17 seconds
Started Jul 07 06:06:30 PM PDT 24
Finished Jul 07 06:10:42 PM PDT 24
Peak memory 183100 kb
Host smart-893e90a5-fc6c-4dcc-a8b6-08e1273fe36a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815518273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1815518273
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.87241646
Short name T180
Test name
Test status
Simulation time 115268179774 ps
CPU time 184.39 seconds
Started Jul 07 06:08:56 PM PDT 24
Finished Jul 07 06:12:00 PM PDT 24
Peak memory 191296 kb
Host smart-7a8f5137-37c4-45a2-9fbc-80bcb851012d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87241646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.87241646
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3071000612
Short name T105
Test name
Test status
Simulation time 1027549114111 ps
CPU time 1635.84 seconds
Started Jul 07 06:06:29 PM PDT 24
Finished Jul 07 06:33:46 PM PDT 24
Peak memory 191328 kb
Host smart-02d8b23a-64ad-424c-9b12-c6703ce14ab7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071000612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3071000612
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/173.rv_timer_random.4013704664
Short name T248
Test name
Test status
Simulation time 217317935552 ps
CPU time 223.45 seconds
Started Jul 07 06:09:46 PM PDT 24
Finished Jul 07 06:13:30 PM PDT 24
Peak memory 191328 kb
Host smart-bc9e6f30-dfe1-4635-9915-95deaf8ca038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013704664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.4013704664
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3628364456
Short name T47
Test name
Test status
Simulation time 198625455582 ps
CPU time 1142.08 seconds
Started Jul 07 06:07:54 PM PDT 24
Finished Jul 07 06:26:57 PM PDT 24
Peak memory 195728 kb
Host smart-9f864c90-cb52-403e-972a-29ecaa46a53e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628364456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3628364456
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2366270801
Short name T114
Test name
Test status
Simulation time 382261558249 ps
CPU time 212.62 seconds
Started Jul 07 06:08:19 PM PDT 24
Finished Jul 07 06:11:52 PM PDT 24
Peak memory 183128 kb
Host smart-8af5bd7b-8a37-44e2-9f7c-037cfc4aa998
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366270801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2366270801
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/117.rv_timer_random.2545808896
Short name T163
Test name
Test status
Simulation time 361307357003 ps
CPU time 356.12 seconds
Started Jul 07 06:09:06 PM PDT 24
Finished Jul 07 06:15:03 PM PDT 24
Peak memory 191324 kb
Host smart-ba703954-b565-41e2-aaa4-0a5f41d91ecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545808896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.2545808896
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3770548086
Short name T58
Test name
Test status
Simulation time 1116099154723 ps
CPU time 414.58 seconds
Started Jul 07 06:07:32 PM PDT 24
Finished Jul 07 06:14:27 PM PDT 24
Peak memory 195392 kb
Host smart-94b5a37f-3906-4d62-9079-1a0ba7a7e846
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770548086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3770548086
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/69.rv_timer_random.1927496277
Short name T289
Test name
Test status
Simulation time 258565963096 ps
CPU time 733.03 seconds
Started Jul 07 06:08:30 PM PDT 24
Finished Jul 07 06:20:44 PM PDT 24
Peak memory 191344 kb
Host smart-ad2747ec-f3cd-4c73-8258-d1b68207ba1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927496277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1927496277
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1448737344
Short name T302
Test name
Test status
Simulation time 195128172567 ps
CPU time 251.81 seconds
Started Jul 07 06:09:19 PM PDT 24
Finished Jul 07 06:13:31 PM PDT 24
Peak memory 191332 kb
Host smart-ab9ba496-54dc-4f46-b439-a798ca7070e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448737344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1448737344
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2996791814
Short name T196
Test name
Test status
Simulation time 65133074240 ps
CPU time 107.29 seconds
Started Jul 07 06:06:32 PM PDT 24
Finished Jul 07 06:08:20 PM PDT 24
Peak memory 191332 kb
Host smart-022752fc-369c-44a6-b912-bfed12a7be37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996791814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2996791814
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_random.2150669055
Short name T164
Test name
Test status
Simulation time 944061728268 ps
CPU time 962.78 seconds
Started Jul 07 06:07:57 PM PDT 24
Finished Jul 07 06:24:00 PM PDT 24
Peak memory 191288 kb
Host smart-d74418e1-579d-4725-8e78-374850f2382e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150669055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2150669055
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.672837935
Short name T162
Test name
Test status
Simulation time 278372393030 ps
CPU time 573.99 seconds
Started Jul 07 06:06:04 PM PDT 24
Finished Jul 07 06:15:38 PM PDT 24
Peak memory 191328 kb
Host smart-4c3a1620-d975-430e-99c8-82e9b23ed11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672837935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.672837935
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3349529363
Short name T240
Test name
Test status
Simulation time 305880020382 ps
CPU time 389.88 seconds
Started Jul 07 06:09:23 PM PDT 24
Finished Jul 07 06:15:53 PM PDT 24
Peak memory 191300 kb
Host smart-5b54b112-3f61-48f9-b7a9-28359a1006c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349529363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3349529363
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.949968271
Short name T307
Test name
Test status
Simulation time 372786138958 ps
CPU time 203.56 seconds
Started Jul 07 06:06:28 PM PDT 24
Finished Jul 07 06:09:52 PM PDT 24
Peak memory 193504 kb
Host smart-b101f4b2-f42d-4acd-bf5b-b50c109721c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949968271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.949968271
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2108906143
Short name T120
Test name
Test status
Simulation time 366209212148 ps
CPU time 397.2 seconds
Started Jul 07 06:09:54 PM PDT 24
Finished Jul 07 06:16:32 PM PDT 24
Peak memory 191312 kb
Host smart-8ed8807f-8002-4b11-8cb3-fdc1e06afe07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108906143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2108906143
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1633097246
Short name T189
Test name
Test status
Simulation time 205666526712 ps
CPU time 1047.09 seconds
Started Jul 07 06:10:01 PM PDT 24
Finished Jul 07 06:27:29 PM PDT 24
Peak memory 191292 kb
Host smart-ecf302d7-2e9d-4231-a91e-336297b3c0a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633097246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1633097246
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random.1266702379
Short name T206
Test name
Test status
Simulation time 169805531677 ps
CPU time 286.22 seconds
Started Jul 07 06:07:26 PM PDT 24
Finished Jul 07 06:12:12 PM PDT 24
Peak memory 193868 kb
Host smart-38700161-8d45-4c88-8d21-4054c9c28c1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266702379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1266702379
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1730776255
Short name T138
Test name
Test status
Simulation time 523143752229 ps
CPU time 607.09 seconds
Started Jul 07 06:07:34 PM PDT 24
Finished Jul 07 06:17:42 PM PDT 24
Peak memory 191344 kb
Host smart-7ae3a1a9-9623-4e01-8b7c-04c1ff80bcaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730776255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1730776255
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/68.rv_timer_random.4027018644
Short name T137
Test name
Test status
Simulation time 132202803268 ps
CPU time 359.09 seconds
Started Jul 07 06:08:31 PM PDT 24
Finished Jul 07 06:14:31 PM PDT 24
Peak memory 191320 kb
Host smart-9ae8a144-113c-4bfd-8e1c-819583fc1631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027018644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4027018644
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.550700479
Short name T451
Test name
Test status
Simulation time 1810926258040 ps
CPU time 1445.5 seconds
Started Jul 07 06:05:27 PM PDT 24
Finished Jul 07 06:29:33 PM PDT 24
Peak memory 191340 kb
Host smart-d46af3b3-836d-4447-8928-7067d9fe3ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550700479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.550700479
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/108.rv_timer_random.2818976755
Short name T275
Test name
Test status
Simulation time 115468476520 ps
CPU time 466.42 seconds
Started Jul 07 06:08:57 PM PDT 24
Finished Jul 07 06:16:43 PM PDT 24
Peak memory 191368 kb
Host smart-9e6234fa-c8ce-430a-b3fd-d71586fb73a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818976755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2818976755
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1671574447
Short name T56
Test name
Test status
Simulation time 1495101171966 ps
CPU time 651.73 seconds
Started Jul 07 06:06:34 PM PDT 24
Finished Jul 07 06:17:26 PM PDT 24
Peak memory 191276 kb
Host smart-f5885ba8-1e3b-4d99-848f-596e866e5301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671574447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1671574447
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/177.rv_timer_random.4014852370
Short name T209
Test name
Test status
Simulation time 630609711125 ps
CPU time 473.34 seconds
Started Jul 07 06:09:46 PM PDT 24
Finished Jul 07 06:17:40 PM PDT 24
Peak memory 191344 kb
Host smart-4f03ced6-f689-4b40-9625-70a399f78607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014852370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.4014852370
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1316598181
Short name T193
Test name
Test status
Simulation time 364600439508 ps
CPU time 1026.79 seconds
Started Jul 07 06:09:45 PM PDT 24
Finished Jul 07 06:26:52 PM PDT 24
Peak memory 191324 kb
Host smart-2a1ace38-5668-4404-8ae0-c89b5f212675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316598181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1316598181
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.3113592182
Short name T171
Test name
Test status
Simulation time 204855167521 ps
CPU time 725.02 seconds
Started Jul 07 06:07:07 PM PDT 24
Finished Jul 07 06:19:13 PM PDT 24
Peak memory 194804 kb
Host smart-533b4693-132e-4e31-befc-76f9b8a65997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113592182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3113592182
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random.4205840572
Short name T101
Test name
Test status
Simulation time 163074790554 ps
CPU time 179.26 seconds
Started Jul 07 06:07:24 PM PDT 24
Finished Jul 07 06:10:24 PM PDT 24
Peak memory 191324 kb
Host smart-069ab815-1e84-4657-9443-8df5937e9b36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205840572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4205840572
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2167281626
Short name T266
Test name
Test status
Simulation time 194839974085 ps
CPU time 175.51 seconds
Started Jul 07 06:06:03 PM PDT 24
Finished Jul 07 06:08:59 PM PDT 24
Peak memory 183084 kb
Host smart-0bb28582-dd2d-48d7-b27a-e16c6d1bf9f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167281626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2167281626
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.2641299284
Short name T225
Test name
Test status
Simulation time 320277369937 ps
CPU time 1375.12 seconds
Started Jul 07 06:06:03 PM PDT 24
Finished Jul 07 06:28:59 PM PDT 24
Peak memory 191308 kb
Host smart-bb5a8f9a-7e7b-4742-84ca-8c3b1bbffa48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641299284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
2641299284
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3430193549
Short name T197
Test name
Test status
Simulation time 540117446464 ps
CPU time 331.37 seconds
Started Jul 07 06:08:44 PM PDT 24
Finished Jul 07 06:14:15 PM PDT 24
Peak memory 191344 kb
Host smart-5664981f-0b4a-47ca-a36e-f772d15fa757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430193549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3430193549
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2198844096
Short name T93
Test name
Test status
Simulation time 220766975 ps
CPU time 1.33 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 194972 kb
Host smart-d5e32da5-c1c8-4482-8ff9-58da3e1e889d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198844096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2198844096
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.815768266
Short name T175
Test name
Test status
Simulation time 7675390201381 ps
CPU time 1204.33 seconds
Started Jul 07 06:06:11 PM PDT 24
Finished Jul 07 06:26:15 PM PDT 24
Peak memory 191296 kb
Host smart-e7dd35c6-84be-4954-95a0-0bbff8db0eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815768266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
815768266
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.1479938881
Short name T112
Test name
Test status
Simulation time 414818712981 ps
CPU time 1181.55 seconds
Started Jul 07 06:09:07 PM PDT 24
Finished Jul 07 06:28:49 PM PDT 24
Peak memory 191348 kb
Host smart-7797efc3-900d-431a-ae1d-3d2d7e049ffc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479938881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1479938881
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3048019444
Short name T283
Test name
Test status
Simulation time 1049260004315 ps
CPU time 831.35 seconds
Started Jul 07 06:06:23 PM PDT 24
Finished Jul 07 06:20:15 PM PDT 24
Peak memory 183120 kb
Host smart-ee41adce-91be-495c-96b4-111ea250516e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048019444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3048019444
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/142.rv_timer_random.2522884323
Short name T320
Test name
Test status
Simulation time 57033007836 ps
CPU time 104.25 seconds
Started Jul 07 06:09:21 PM PDT 24
Finished Jul 07 06:11:05 PM PDT 24
Peak memory 194956 kb
Host smart-c593746a-731e-4ec6-a196-b7dcfab2261c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522884323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2522884323
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1138921095
Short name T230
Test name
Test status
Simulation time 165309462140 ps
CPU time 280.5 seconds
Started Jul 07 06:09:35 PM PDT 24
Finished Jul 07 06:14:16 PM PDT 24
Peak memory 183160 kb
Host smart-4763635b-f605-4c21-970b-e3b55f4be502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138921095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1138921095
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1941721801
Short name T200
Test name
Test status
Simulation time 105666405262 ps
CPU time 197.69 seconds
Started Jul 07 06:09:34 PM PDT 24
Finished Jul 07 06:12:52 PM PDT 24
Peak memory 191324 kb
Host smart-785420eb-e161-4100-b0d1-f6349dbdc101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941721801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1941721801
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3460627076
Short name T280
Test name
Test status
Simulation time 2692651447613 ps
CPU time 1376.33 seconds
Started Jul 07 06:06:30 PM PDT 24
Finished Jul 07 06:29:26 PM PDT 24
Peak memory 183092 kb
Host smart-c6346630-cf85-435e-8088-6ee9205694d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460627076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3460627076
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/184.rv_timer_random.949933876
Short name T310
Test name
Test status
Simulation time 220754454503 ps
CPU time 90.08 seconds
Started Jul 07 06:09:48 PM PDT 24
Finished Jul 07 06:11:18 PM PDT 24
Peak memory 191336 kb
Host smart-6c798f9e-2dc0-405a-9225-8288bc782e5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949933876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.949933876
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3366797585
Short name T232
Test name
Test status
Simulation time 95684979967 ps
CPU time 134.07 seconds
Started Jul 07 06:06:40 PM PDT 24
Finished Jul 07 06:08:55 PM PDT 24
Peak memory 183128 kb
Host smart-cf5f28e9-78a8-4913-8616-dd1a19ed67b8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366797585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3366797585
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2093766784
Short name T155
Test name
Test status
Simulation time 276327008417 ps
CPU time 200.32 seconds
Started Jul 07 06:06:57 PM PDT 24
Finished Jul 07 06:10:18 PM PDT 24
Peak memory 183120 kb
Host smart-682dda57-609e-4ab6-afbe-c97bc31dbeae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093766784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2093766784
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.337821584
Short name T178
Test name
Test status
Simulation time 218296913365 ps
CPU time 383.38 seconds
Started Jul 07 06:07:12 PM PDT 24
Finished Jul 07 06:13:35 PM PDT 24
Peak memory 183144 kb
Host smart-a146e007-655f-499d-9ca0-c5ff536271f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337821584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.rv_timer_cfg_update_on_fly.337821584
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3556186152
Short name T207
Test name
Test status
Simulation time 628702101558 ps
CPU time 558.49 seconds
Started Jul 07 06:07:46 PM PDT 24
Finished Jul 07 06:17:04 PM PDT 24
Peak memory 191316 kb
Host smart-3b64709d-46c6-4ce1-aec3-5aa1ed941541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556186152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3556186152
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/63.rv_timer_random.1318064487
Short name T184
Test name
Test status
Simulation time 465879839383 ps
CPU time 397.46 seconds
Started Jul 07 06:08:30 PM PDT 24
Finished Jul 07 06:15:07 PM PDT 24
Peak memory 191320 kb
Host smart-4921f16a-57a3-4920-b7a7-07fece6ddb71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318064487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1318064487
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.337933589
Short name T276
Test name
Test status
Simulation time 128055049481 ps
CPU time 74.51 seconds
Started Jul 07 06:08:37 PM PDT 24
Finished Jul 07 06:09:52 PM PDT 24
Peak memory 191340 kb
Host smart-4a5adfb7-1113-4d50-bcef-ff7de4430599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337933589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.337933589
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.1609971
Short name T303
Test name
Test status
Simulation time 101040600857 ps
CPU time 85.89 seconds
Started Jul 07 06:05:20 PM PDT 24
Finished Jul 07 06:06:47 PM PDT 24
Peak memory 191344 kb
Host smart-887c0ddc-ad5f-46b6-8642-5e6e102d9580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.1609971
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2578882210
Short name T244
Test name
Test status
Simulation time 302970265659 ps
CPU time 149.6 seconds
Started Jul 07 06:06:09 PM PDT 24
Finished Jul 07 06:08:39 PM PDT 24
Peak memory 183112 kb
Host smart-f37ea52e-8c3e-4e3d-ac7f-c6d672d5c70d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578882210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2578882210
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/102.rv_timer_random.3460038004
Short name T127
Test name
Test status
Simulation time 2563420257544 ps
CPU time 2495.38 seconds
Started Jul 07 06:08:53 PM PDT 24
Finished Jul 07 06:50:29 PM PDT 24
Peak memory 191344 kb
Host smart-49d5d1f9-9c99-4b15-9e74-5ee3cd42df48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460038004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3460038004
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.4009555759
Short name T212
Test name
Test status
Simulation time 89227311718 ps
CPU time 504.29 seconds
Started Jul 07 06:08:53 PM PDT 24
Finished Jul 07 06:17:18 PM PDT 24
Peak memory 191328 kb
Host smart-c1b29e1e-7cd5-45d9-af52-ef48de885889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009555759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.4009555759
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1430493690
Short name T139
Test name
Test status
Simulation time 26370334233 ps
CPU time 284.96 seconds
Started Jul 07 06:06:11 PM PDT 24
Finished Jul 07 06:10:56 PM PDT 24
Peak memory 194880 kb
Host smart-d7b07d43-5b7a-4ff9-9bbe-f98db8388b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430493690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1430493690
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/114.rv_timer_random.769808910
Short name T220
Test name
Test status
Simulation time 147502813573 ps
CPU time 295.41 seconds
Started Jul 07 06:09:03 PM PDT 24
Finished Jul 07 06:13:59 PM PDT 24
Peak memory 191288 kb
Host smart-742c1686-750e-4cb8-aefa-4da35923f6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769808910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.769808910
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.595091348
Short name T181
Test name
Test status
Simulation time 305716939551 ps
CPU time 1553.24 seconds
Started Jul 07 06:09:08 PM PDT 24
Finished Jul 07 06:35:02 PM PDT 24
Peak memory 191344 kb
Host smart-d3ec0d66-e317-4908-8829-41582893c7ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595091348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.595091348
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2854628423
Short name T347
Test name
Test status
Simulation time 18886091859 ps
CPU time 28.02 seconds
Started Jul 07 06:09:10 PM PDT 24
Finished Jul 07 06:09:38 PM PDT 24
Peak memory 193516 kb
Host smart-1d399746-3622-4c20-95eb-fa0257884840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854628423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2854628423
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3388738309
Short name T191
Test name
Test status
Simulation time 909222231572 ps
CPU time 459.35 seconds
Started Jul 07 06:06:15 PM PDT 24
Finished Jul 07 06:13:54 PM PDT 24
Peak memory 191336 kb
Host smart-1e2e8090-9744-4ecc-9ebc-994f467ca1d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388738309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3388738309
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2917353226
Short name T308
Test name
Test status
Simulation time 31144690606 ps
CPU time 84.31 seconds
Started Jul 07 06:06:18 PM PDT 24
Finished Jul 07 06:07:42 PM PDT 24
Peak memory 183160 kb
Host smart-70437801-e51f-4f9f-becd-87ec0318fc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917353226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2917353226
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.882334646
Short name T53
Test name
Test status
Simulation time 6106364845669 ps
CPU time 1092.39 seconds
Started Jul 07 06:06:19 PM PDT 24
Finished Jul 07 06:24:31 PM PDT 24
Peak memory 191276 kb
Host smart-845b2eac-178a-4126-9fe4-a32e23375946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882334646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
882334646
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/135.rv_timer_random.3687999744
Short name T257
Test name
Test status
Simulation time 98933130742 ps
CPU time 518.91 seconds
Started Jul 07 06:09:19 PM PDT 24
Finished Jul 07 06:17:58 PM PDT 24
Peak memory 183172 kb
Host smart-5e2abf8c-41db-4b1a-b42d-7eeb645d34ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687999744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3687999744
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.4096333994
Short name T104
Test name
Test status
Simulation time 139049348675 ps
CPU time 463.23 seconds
Started Jul 07 06:09:21 PM PDT 24
Finished Jul 07 06:17:04 PM PDT 24
Peak memory 191324 kb
Host smart-22d38336-90dc-4b4f-9f55-450ec8889921
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096333994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.4096333994
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.806413253
Short name T45
Test name
Test status
Simulation time 217132088371 ps
CPU time 113.38 seconds
Started Jul 07 06:06:22 PM PDT 24
Finished Jul 07 06:08:15 PM PDT 24
Peak memory 183144 kb
Host smart-5598a760-6b40-4398-992c-8b4d812adcd8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806413253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.806413253
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/153.rv_timer_random.4129768395
Short name T238
Test name
Test status
Simulation time 197781272899 ps
CPU time 722.74 seconds
Started Jul 07 06:09:29 PM PDT 24
Finished Jul 07 06:21:32 PM PDT 24
Peak memory 191320 kb
Host smart-7f5d37d3-3f58-4494-a45c-e20a17dfc241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129768395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.4129768395
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2272484137
Short name T169
Test name
Test status
Simulation time 69377565278 ps
CPU time 168.36 seconds
Started Jul 07 06:06:27 PM PDT 24
Finished Jul 07 06:09:15 PM PDT 24
Peak memory 191352 kb
Host smart-ae05c757-748d-454d-9f33-0c7e07b035c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272484137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2272484137
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/161.rv_timer_random.2065796648
Short name T435
Test name
Test status
Simulation time 488951167420 ps
CPU time 455.47 seconds
Started Jul 07 06:09:34 PM PDT 24
Finished Jul 07 06:17:10 PM PDT 24
Peak memory 191612 kb
Host smart-c19fcab0-00c4-435c-bf97-95f0429af1a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065796648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.2065796648
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2025418064
Short name T190
Test name
Test status
Simulation time 370260352235 ps
CPU time 296.1 seconds
Started Jul 07 06:09:45 PM PDT 24
Finished Jul 07 06:14:42 PM PDT 24
Peak memory 191332 kb
Host smart-35586e9b-059f-4efd-9321-bce113c690d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025418064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2025418064
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.119695664
Short name T119
Test name
Test status
Simulation time 127976071054 ps
CPU time 552.57 seconds
Started Jul 07 06:09:47 PM PDT 24
Finished Jul 07 06:19:00 PM PDT 24
Peak memory 191360 kb
Host smart-2dcddbdb-ca80-4f98-adad-ea6256530cce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119695664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.119695664
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1423572042
Short name T42
Test name
Test status
Simulation time 752069004805 ps
CPU time 86.71 seconds
Started Jul 07 06:09:53 PM PDT 24
Finished Jul 07 06:11:20 PM PDT 24
Peak memory 191312 kb
Host smart-99d66976-d2dd-4c88-b354-803cb8b6a8ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423572042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1423572042
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.381667616
Short name T229
Test name
Test status
Simulation time 120971209929 ps
CPU time 692.6 seconds
Started Jul 07 06:10:01 PM PDT 24
Finished Jul 07 06:21:34 PM PDT 24
Peak memory 193456 kb
Host smart-8a98bbaa-0a8f-41c1-aff8-fd24812a070f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381667616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.381667616
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2546248016
Short name T97
Test name
Test status
Simulation time 1049960456123 ps
CPU time 3289.29 seconds
Started Jul 07 06:06:55 PM PDT 24
Finished Jul 07 07:01:45 PM PDT 24
Peak memory 191592 kb
Host smart-bc4203be-48c4-4530-b07e-fb25ea61d11b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546248016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2546248016
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_random.2578201250
Short name T210
Test name
Test status
Simulation time 18622187013 ps
CPU time 11 seconds
Started Jul 07 06:07:08 PM PDT 24
Finished Jul 07 06:07:19 PM PDT 24
Peak memory 183108 kb
Host smart-a1fd51db-30ec-4856-896f-711b717e8da8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578201250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2578201250
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.847261136
Short name T301
Test name
Test status
Simulation time 94426831766 ps
CPU time 149.3 seconds
Started Jul 07 06:07:10 PM PDT 24
Finished Jul 07 06:09:40 PM PDT 24
Peak memory 183144 kb
Host smart-86733119-94bc-4363-9d14-bdc039b39872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847261136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.847261136
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.274743001
Short name T90
Test name
Test status
Simulation time 113790327622 ps
CPU time 881.8 seconds
Started Jul 07 06:07:14 PM PDT 24
Finished Jul 07 06:21:56 PM PDT 24
Peak memory 209072 kb
Host smart-48a4cb48-7e54-47a6-b572-ed022ef3ac74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274743001 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.274743001
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3150634285
Short name T252
Test name
Test status
Simulation time 1109586110298 ps
CPU time 475.04 seconds
Started Jul 07 06:07:23 PM PDT 24
Finished Jul 07 06:15:18 PM PDT 24
Peak memory 191312 kb
Host smart-33993f17-97d4-4905-85fd-b39f52841dd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150634285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3150634285
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.4279787497
Short name T81
Test name
Test status
Simulation time 629058241377 ps
CPU time 353.98 seconds
Started Jul 07 06:07:23 PM PDT 24
Finished Jul 07 06:13:17 PM PDT 24
Peak memory 183112 kb
Host smart-736a4a1a-ab72-4437-a913-9e40fa283316
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279787497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.4279787497
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.5166184
Short name T333
Test name
Test status
Simulation time 638845304185 ps
CPU time 804.7 seconds
Started Jul 07 06:07:26 PM PDT 24
Finished Jul 07 06:20:51 PM PDT 24
Peak memory 191328 kb
Host smart-bbacf915-1470-4c72-b68c-dfa93599fb04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5166184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.5166184
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_random.1526481129
Short name T174
Test name
Test status
Simulation time 824344263097 ps
CPU time 404.79 seconds
Started Jul 07 06:07:37 PM PDT 24
Finished Jul 07 06:14:22 PM PDT 24
Peak memory 191336 kb
Host smart-c5ff6534-2227-4447-b846-d45d8eb61bb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526481129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1526481129
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2800631774
Short name T265
Test name
Test status
Simulation time 33825004420 ps
CPU time 30.51 seconds
Started Jul 07 06:07:55 PM PDT 24
Finished Jul 07 06:08:26 PM PDT 24
Peak memory 183100 kb
Host smart-3d565388-6f7a-49cf-9913-8c40723a7799
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800631774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2800631774
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/56.rv_timer_random.3671351741
Short name T313
Test name
Test status
Simulation time 481150281402 ps
CPU time 383.04 seconds
Started Jul 07 06:08:26 PM PDT 24
Finished Jul 07 06:14:50 PM PDT 24
Peak memory 191336 kb
Host smart-98a22b51-ac99-439b-867b-c2408a992a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671351741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3671351741
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1737095117
Short name T142
Test name
Test status
Simulation time 90175018019 ps
CPU time 147.17 seconds
Started Jul 07 06:08:34 PM PDT 24
Finished Jul 07 06:11:02 PM PDT 24
Peak memory 191252 kb
Host smart-f4174465-3556-4c31-bcfe-10db893769b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737095117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1737095117
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random.2051488557
Short name T259
Test name
Test status
Simulation time 91823148292 ps
CPU time 186.36 seconds
Started Jul 07 06:05:57 PM PDT 24
Finished Jul 07 06:09:04 PM PDT 24
Peak memory 194864 kb
Host smart-28cbcc53-53e8-480f-8905-431718c38470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051488557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2051488557
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3289160276
Short name T131
Test name
Test status
Simulation time 211851974995 ps
CPU time 250.51 seconds
Started Jul 07 06:08:43 PM PDT 24
Finished Jul 07 06:12:54 PM PDT 24
Peak memory 191332 kb
Host smart-7eb8cd94-0250-4021-afc8-10de7b850ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289160276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3289160276
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4253424154
Short name T91
Test name
Test status
Simulation time 48145197 ps
CPU time 0.73 seconds
Started Jul 07 06:00:01 PM PDT 24
Finished Jul 07 06:00:02 PM PDT 24
Peak memory 182268 kb
Host smart-ce345b53-cce7-4800-9b2b-4d8459566f78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253424154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4253424154
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2555936419
Short name T65
Test name
Test status
Simulation time 285586868 ps
CPU time 1.64 seconds
Started Jul 07 06:00:02 PM PDT 24
Finished Jul 07 06:00:04 PM PDT 24
Peak memory 190672 kb
Host smart-213ddd0b-aa19-4ab0-8658-9dd70a8c4d1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555936419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2555936419
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1693045323
Short name T562
Test name
Test status
Simulation time 34304356 ps
CPU time 0.54 seconds
Started Jul 07 06:00:01 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 181992 kb
Host smart-27e5f4f1-556f-45c9-a844-bb07661fb7dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693045323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1693045323
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.668308763
Short name T533
Test name
Test status
Simulation time 145272815 ps
CPU time 1.13 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 197056 kb
Host smart-787314f6-bea9-43bf-8b96-e3246393b1d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668308763 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.668308763
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3667897362
Short name T480
Test name
Test status
Simulation time 27620158 ps
CPU time 0.57 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 182304 kb
Host smart-1874d94b-e35d-4baf-8417-e45d804d3ce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667897362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3667897362
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2032728950
Short name T571
Test name
Test status
Simulation time 49494259 ps
CPU time 0.52 seconds
Started Jul 07 05:59:59 PM PDT 24
Finished Jul 07 06:00:00 PM PDT 24
Peak memory 182204 kb
Host smart-8d83f068-6d1a-4791-8cd0-68aec912a623
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032728950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2032728950
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1069041421
Short name T503
Test name
Test status
Simulation time 32506163 ps
CPU time 0.73 seconds
Started Jul 07 06:00:01 PM PDT 24
Finished Jul 07 06:00:02 PM PDT 24
Peak memory 191584 kb
Host smart-b1f4f01a-b32a-4a05-a62f-83b98fe0a68c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069041421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1069041421
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2117102644
Short name T577
Test name
Test status
Simulation time 242158971 ps
CPU time 1.22 seconds
Started Jul 07 06:00:04 PM PDT 24
Finished Jul 07 06:00:07 PM PDT 24
Peak memory 196964 kb
Host smart-fc6d2187-15da-4b1d-af16-316832c931bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117102644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2117102644
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.863327973
Short name T468
Test name
Test status
Simulation time 316726872 ps
CPU time 1.14 seconds
Started Jul 07 06:00:02 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 182964 kb
Host smart-2296d5a2-76f8-47e0-8710-821284501d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863327973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.863327973
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.117574494
Short name T72
Test name
Test status
Simulation time 111277744 ps
CPU time 0.72 seconds
Started Jul 07 06:00:02 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 192228 kb
Host smart-d2e227f2-1c4f-4bd7-a2ed-eee255ac0cde
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117574494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.117574494
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2984483533
Short name T551
Test name
Test status
Simulation time 201179384 ps
CPU time 3.45 seconds
Started Jul 07 06:00:01 PM PDT 24
Finished Jul 07 06:00:04 PM PDT 24
Peak memory 193904 kb
Host smart-06e8a1fc-453c-4365-be55-9391e2e7cb89
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984483533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2984483533
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1360810644
Short name T470
Test name
Test status
Simulation time 192900187 ps
CPU time 0.61 seconds
Started Jul 07 06:00:02 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 182268 kb
Host smart-94122ee0-2606-4ec2-9856-c22d60f69012
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360810644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1360810644
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.2195108201
Short name T498
Test name
Test status
Simulation time 47651649 ps
CPU time 0.64 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 192804 kb
Host smart-16256dbc-52f2-4603-a393-6e5cd9407d4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195108201 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.2195108201
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3453737873
Short name T66
Test name
Test status
Simulation time 57186489 ps
CPU time 0.6 seconds
Started Jul 07 06:00:01 PM PDT 24
Finished Jul 07 06:00:02 PM PDT 24
Peak memory 182244 kb
Host smart-d34cd423-b34f-4fef-884c-57ebd458f04d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453737873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3453737873
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3554253292
Short name T550
Test name
Test status
Simulation time 33131620 ps
CPU time 0.57 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 182200 kb
Host smart-3d7a4d19-3e47-4140-a844-ec9155ab3393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554253292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3554253292
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2350514019
Short name T76
Test name
Test status
Simulation time 297029160 ps
CPU time 0.77 seconds
Started Jul 07 06:00:04 PM PDT 24
Finished Jul 07 06:00:06 PM PDT 24
Peak memory 193080 kb
Host smart-9022b4c1-6725-43f8-8bdf-0c092e499bf2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350514019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2350514019
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3827290863
Short name T514
Test name
Test status
Simulation time 45424964 ps
CPU time 2.1 seconds
Started Jul 07 06:00:04 PM PDT 24
Finished Jul 07 06:00:08 PM PDT 24
Peak memory 197120 kb
Host smart-f33230e4-1eb4-4d6f-b26f-ae5601170e8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827290863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3827290863
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.749965751
Short name T511
Test name
Test status
Simulation time 96410466 ps
CPU time 1.17 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 194032 kb
Host smart-b75b341c-ddc8-44da-bcf8-f02bcd57b793
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749965751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_int
g_err.749965751
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.908280862
Short name T517
Test name
Test status
Simulation time 125155785 ps
CPU time 1.23 seconds
Started Jul 07 06:00:12 PM PDT 24
Finished Jul 07 06:00:14 PM PDT 24
Peak memory 197120 kb
Host smart-72fd9e88-a9eb-4b36-90ce-4e8500f7279a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908280862 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.908280862
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3343787053
Short name T541
Test name
Test status
Simulation time 18422105 ps
CPU time 0.59 seconds
Started Jul 07 06:00:16 PM PDT 24
Finished Jul 07 06:00:18 PM PDT 24
Peak memory 182276 kb
Host smart-b13f61cb-0423-44d2-a15c-7210e2239c16
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343787053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3343787053
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.3972878739
Short name T572
Test name
Test status
Simulation time 16443990 ps
CPU time 0.61 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:14 PM PDT 24
Peak memory 182204 kb
Host smart-f8518463-6938-4538-9064-ec923ce6a1f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972878739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.3972878739
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3733375691
Short name T561
Test name
Test status
Simulation time 32514113 ps
CPU time 0.72 seconds
Started Jul 07 06:00:10 PM PDT 24
Finished Jul 07 06:00:11 PM PDT 24
Peak memory 191316 kb
Host smart-13284715-b142-4de4-a484-2d4755a7098b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733375691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3733375691
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.225133361
Short name T485
Test name
Test status
Simulation time 50494231 ps
CPU time 1.43 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:15 PM PDT 24
Peak memory 195712 kb
Host smart-d3d8307b-db68-4a6c-b9d5-4a7074a1798a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225133361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.225133361
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1436853986
Short name T504
Test name
Test status
Simulation time 184570449 ps
CPU time 0.97 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:16 PM PDT 24
Peak memory 196960 kb
Host smart-bb7df089-3e79-4548-aad2-dace3c365d1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436853986 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1436853986
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.112286653
Short name T569
Test name
Test status
Simulation time 40169765 ps
CPU time 0.6 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 182328 kb
Host smart-4be79fae-9dce-406a-9baa-74f6acf5267e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112286653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.112286653
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3872244942
Short name T461
Test name
Test status
Simulation time 18038927 ps
CPU time 0.59 seconds
Started Jul 07 06:00:11 PM PDT 24
Finished Jul 07 06:00:12 PM PDT 24
Peak memory 182440 kb
Host smart-326996ce-5de5-4fa4-95ee-05c9baa621f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872244942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3872244942
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.4019594774
Short name T79
Test name
Test status
Simulation time 21344467 ps
CPU time 0.82 seconds
Started Jul 07 06:00:11 PM PDT 24
Finished Jul 07 06:00:12 PM PDT 24
Peak memory 191236 kb
Host smart-dc591d47-ee61-480c-98aa-5ddc2d665f5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019594774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.4019594774
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1756768003
Short name T524
Test name
Test status
Simulation time 623195668 ps
CPU time 2.77 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:20 PM PDT 24
Peak memory 191764 kb
Host smart-f8053970-6bf5-48df-949f-26e5ee978d76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756768003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1756768003
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2292457489
Short name T476
Test name
Test status
Simulation time 95176937 ps
CPU time 0.85 seconds
Started Jul 07 06:00:16 PM PDT 24
Finished Jul 07 06:00:19 PM PDT 24
Peak memory 193456 kb
Host smart-89891604-8e0b-4a1b-93f5-227ea4db7a1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292457489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2292457489
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1412044568
Short name T535
Test name
Test status
Simulation time 115815504 ps
CPU time 0.75 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:18 PM PDT 24
Peak memory 194576 kb
Host smart-d394dba5-73e7-4894-b2c4-f3dabb1f4090
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412044568 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1412044568
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.4169124243
Short name T70
Test name
Test status
Simulation time 33879273 ps
CPU time 0.55 seconds
Started Jul 07 06:00:17 PM PDT 24
Finished Jul 07 06:00:18 PM PDT 24
Peak memory 182328 kb
Host smart-ec94982b-a8d3-48d6-bf9e-511ffcc7a1ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169124243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.4169124243
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2296412236
Short name T496
Test name
Test status
Simulation time 14965725 ps
CPU time 0.59 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 182228 kb
Host smart-84b8b1f5-32da-43d9-af2f-9a098329bd47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296412236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2296412236
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1765259889
Short name T536
Test name
Test status
Simulation time 47313270 ps
CPU time 0.91 seconds
Started Jul 07 06:00:10 PM PDT 24
Finished Jul 07 06:00:12 PM PDT 24
Peak memory 194240 kb
Host smart-c9f05a33-a115-46e3-9e19-c2608cb7e98c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765259889 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1765259889
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.3175694077
Short name T507
Test name
Test status
Simulation time 142778482 ps
CPU time 1.79 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:15 PM PDT 24
Peak memory 197056 kb
Host smart-b0e0429c-74e9-470e-9163-ea28f384f651
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175694077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.3175694077
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1567166054
Short name T523
Test name
Test status
Simulation time 525825443 ps
CPU time 1.12 seconds
Started Jul 07 06:00:11 PM PDT 24
Finished Jul 07 06:00:13 PM PDT 24
Peak memory 182804 kb
Host smart-53b4fcae-2f60-4ef0-ae4f-bfbd3c8a5db3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567166054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1567166054
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.735622026
Short name T554
Test name
Test status
Simulation time 163894571 ps
CPU time 1.06 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:14 PM PDT 24
Peak memory 196892 kb
Host smart-976df05a-6c50-4201-a712-e10f10776223
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735622026 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.735622026
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1200628244
Short name T67
Test name
Test status
Simulation time 12192668 ps
CPU time 0.55 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:16 PM PDT 24
Peak memory 182320 kb
Host smart-ee7cfee6-b4fa-4d4c-b9b1-2f633c3fa68f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200628244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1200628244
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.3609756431
Short name T484
Test name
Test status
Simulation time 91318552 ps
CPU time 0.56 seconds
Started Jul 07 06:00:11 PM PDT 24
Finished Jul 07 06:00:12 PM PDT 24
Peak memory 181704 kb
Host smart-be77d23e-087f-4eeb-9307-8e6cf3c4eb0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609756431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.3609756431
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2472822607
Short name T575
Test name
Test status
Simulation time 20459784 ps
CPU time 0.66 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:14 PM PDT 24
Peak memory 191636 kb
Host smart-266d480f-ddf0-4ca4-937c-bbec0b7777cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472822607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2472822607
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1537262431
Short name T546
Test name
Test status
Simulation time 124914350 ps
CPU time 2.64 seconds
Started Jul 07 06:00:12 PM PDT 24
Finished Jul 07 06:00:15 PM PDT 24
Peak memory 197100 kb
Host smart-ac9f8cee-eaa1-4255-a2b9-4716340202fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537262431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1537262431
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1309844740
Short name T94
Test name
Test status
Simulation time 71493874 ps
CPU time 0.88 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 192840 kb
Host smart-c16db64c-222e-4eac-9c63-879186e4a5dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309844740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1309844740
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4191005839
Short name T38
Test name
Test status
Simulation time 158163436 ps
CPU time 0.94 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 196748 kb
Host smart-cd0ed4c8-0ccc-4db3-bc8b-16d58f8b0363
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191005839 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4191005839
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.325474230
Short name T579
Test name
Test status
Simulation time 36845643 ps
CPU time 0.56 seconds
Started Jul 07 06:00:17 PM PDT 24
Finished Jul 07 06:00:18 PM PDT 24
Peak memory 182320 kb
Host smart-27684eff-97d6-46b1-a69d-f21586717b83
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325474230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.325474230
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3590067189
Short name T466
Test name
Test status
Simulation time 18797884 ps
CPU time 0.53 seconds
Started Jul 07 06:00:17 PM PDT 24
Finished Jul 07 06:00:19 PM PDT 24
Peak memory 181664 kb
Host smart-5b2f2e47-9ba9-4f1e-9b14-b10b59d016ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590067189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3590067189
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1510491721
Short name T78
Test name
Test status
Simulation time 34425646 ps
CPU time 0.76 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 191276 kb
Host smart-389c29b9-cfd2-4af7-bbdf-b8f55712f1cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510491721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1510491721
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.142975132
Short name T36
Test name
Test status
Simulation time 206313663 ps
CPU time 3.26 seconds
Started Jul 07 06:00:16 PM PDT 24
Finished Jul 07 06:00:21 PM PDT 24
Peak memory 197100 kb
Host smart-ddb9c063-53db-420e-a1c7-32154783c4cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142975132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.142975132
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.913155691
Short name T548
Test name
Test status
Simulation time 124954672 ps
CPU time 0.82 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:15 PM PDT 24
Peak memory 193040 kb
Host smart-569f0b28-e761-41ff-b3a5-14002ec6b306
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913155691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.913155691
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.591691059
Short name T59
Test name
Test status
Simulation time 40646740 ps
CPU time 0.72 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:16 PM PDT 24
Peak memory 194568 kb
Host smart-374693cd-8dee-4034-9c25-2a557158aebf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591691059 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.591691059
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3749172958
Short name T25
Test name
Test status
Simulation time 15131817 ps
CPU time 0.63 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:16 PM PDT 24
Peak memory 182288 kb
Host smart-71141cc9-667b-4379-9a65-81eeabf87036
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749172958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3749172958
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2727610076
Short name T460
Test name
Test status
Simulation time 18692228 ps
CPU time 0.58 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:14 PM PDT 24
Peak memory 182496 kb
Host smart-8686bd9d-72ce-4e57-b8dc-4494eeec5168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727610076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2727610076
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2385287956
Short name T559
Test name
Test status
Simulation time 291306603 ps
CPU time 0.68 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:15 PM PDT 24
Peak memory 191816 kb
Host smart-80ea75ae-14a5-4c32-ae5a-5d626818e84e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385287956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2385287956
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3349034646
Short name T570
Test name
Test status
Simulation time 351811810 ps
CPU time 2.16 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 197088 kb
Host smart-8238c83c-e981-409f-a5d3-81c4678fad35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349034646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3349034646
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2996270632
Short name T478
Test name
Test status
Simulation time 42845403 ps
CPU time 0.87 seconds
Started Jul 07 06:00:16 PM PDT 24
Finished Jul 07 06:00:19 PM PDT 24
Peak memory 182672 kb
Host smart-3b81c4b7-84c5-490a-ae94-72f49e85307a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996270632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2996270632
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2304090128
Short name T566
Test name
Test status
Simulation time 75620358 ps
CPU time 0.85 seconds
Started Jul 07 06:00:18 PM PDT 24
Finished Jul 07 06:00:20 PM PDT 24
Peak memory 196396 kb
Host smart-13865e67-f6af-4794-b788-8291c9a8ac65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304090128 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2304090128
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1548459702
Short name T489
Test name
Test status
Simulation time 81022576 ps
CPU time 0.56 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:14 PM PDT 24
Peak memory 182324 kb
Host smart-37077038-3729-4915-af4f-888300450f58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548459702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1548459702
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2910268588
Short name T457
Test name
Test status
Simulation time 11583170 ps
CPU time 0.62 seconds
Started Jul 07 06:00:16 PM PDT 24
Finished Jul 07 06:00:18 PM PDT 24
Peak memory 182188 kb
Host smart-dfc69591-b300-4556-b874-9a265285df6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910268588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2910268588
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1084878100
Short name T545
Test name
Test status
Simulation time 34002888 ps
CPU time 0.79 seconds
Started Jul 07 06:00:18 PM PDT 24
Finished Jul 07 06:00:20 PM PDT 24
Peak memory 193088 kb
Host smart-42e08279-31e8-4c8c-8a35-ad61f723e4cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084878100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1084878100
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2348129369
Short name T563
Test name
Test status
Simulation time 367054533 ps
CPU time 2.31 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:18 PM PDT 24
Peak memory 197116 kb
Host smart-00519c8c-5553-4415-a931-bd6df32ed9b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348129369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2348129369
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.3772636481
Short name T530
Test name
Test status
Simulation time 817195001 ps
CPU time 1.13 seconds
Started Jul 07 06:00:16 PM PDT 24
Finished Jul 07 06:00:19 PM PDT 24
Peak memory 194844 kb
Host smart-5f157646-b2b2-408d-b54c-44aff1d2e954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772636481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.3772636481
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3345059504
Short name T40
Test name
Test status
Simulation time 113774674 ps
CPU time 0.78 seconds
Started Jul 07 06:00:18 PM PDT 24
Finished Jul 07 06:00:19 PM PDT 24
Peak memory 194828 kb
Host smart-c94b73cc-b25d-4765-a4f3-ec3f3cf77381
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345059504 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3345059504
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.786829367
Short name T477
Test name
Test status
Simulation time 26317012 ps
CPU time 0.61 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 182320 kb
Host smart-fe84d3dd-ac77-4b53-ab59-40d3d16fdafb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786829367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.786829367
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3913710200
Short name T502
Test name
Test status
Simulation time 30509004 ps
CPU time 0.57 seconds
Started Jul 07 06:00:21 PM PDT 24
Finished Jul 07 06:00:22 PM PDT 24
Peak memory 182128 kb
Host smart-ebe8b7fa-77df-40d3-b0b0-4cc814360f35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913710200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3913710200
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3454067800
Short name T75
Test name
Test status
Simulation time 186515583 ps
CPU time 0.66 seconds
Started Jul 07 06:00:19 PM PDT 24
Finished Jul 07 06:00:20 PM PDT 24
Peak memory 191116 kb
Host smart-ae59acd0-ab43-4c7c-9287-741939b1944f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454067800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3454067800
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.125579716
Short name T49
Test name
Test status
Simulation time 144462800 ps
CPU time 2.48 seconds
Started Jul 07 06:00:17 PM PDT 24
Finished Jul 07 06:00:21 PM PDT 24
Peak memory 196992 kb
Host smart-9e66bd59-c0a3-4ee6-8e46-3b92330a1d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125579716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.125579716
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1248120168
Short name T500
Test name
Test status
Simulation time 124176139 ps
CPU time 1.37 seconds
Started Jul 07 06:00:16 PM PDT 24
Finished Jul 07 06:00:19 PM PDT 24
Peak memory 194772 kb
Host smart-a394d373-b3f3-4a7c-91ec-e6dfe29304fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248120168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1248120168
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3221730558
Short name T472
Test name
Test status
Simulation time 21967755 ps
CPU time 0.79 seconds
Started Jul 07 06:00:18 PM PDT 24
Finished Jul 07 06:00:19 PM PDT 24
Peak memory 194548 kb
Host smart-3f2692dc-4a87-469f-a434-8060acac0ddc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221730558 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3221730558
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4081544782
Short name T495
Test name
Test status
Simulation time 14472772 ps
CPU time 0.56 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 182184 kb
Host smart-f3864d5b-926d-4bdc-80ba-a9765b5653ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081544782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.4081544782
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1477242436
Short name T553
Test name
Test status
Simulation time 49736595 ps
CPU time 0.55 seconds
Started Jul 07 06:00:16 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 182220 kb
Host smart-92c92ac6-d3f1-460a-bd7f-5e2c7d04c70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477242436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1477242436
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1791262806
Short name T27
Test name
Test status
Simulation time 29126231 ps
CPU time 0.62 seconds
Started Jul 07 06:00:16 PM PDT 24
Finished Jul 07 06:00:18 PM PDT 24
Peak memory 191552 kb
Host smart-35849e13-6e56-43f3-8afb-ed6d75545c99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791262806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1791262806
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.90300990
Short name T462
Test name
Test status
Simulation time 519953673 ps
CPU time 2.64 seconds
Started Jul 07 06:00:17 PM PDT 24
Finished Jul 07 06:00:20 PM PDT 24
Peak memory 197088 kb
Host smart-796a9113-549c-42c4-a843-8fc503757a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90300990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.90300990
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.359770793
Short name T515
Test name
Test status
Simulation time 157162577 ps
CPU time 1.07 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 182708 kb
Host smart-cfb9adf0-9997-4f87-8401-e297d3a8c7ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359770793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.359770793
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.2282556612
Short name T494
Test name
Test status
Simulation time 149526536 ps
CPU time 0.85 seconds
Started Jul 07 06:00:20 PM PDT 24
Finished Jul 07 06:00:21 PM PDT 24
Peak memory 196016 kb
Host smart-bb5e2e8e-198c-4888-9b40-6c7ebf25aa7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282556612 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.2282556612
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.3411520631
Short name T516
Test name
Test status
Simulation time 16634176 ps
CPU time 0.61 seconds
Started Jul 07 06:00:19 PM PDT 24
Finished Jul 07 06:00:20 PM PDT 24
Peak memory 182208 kb
Host smart-6b6e486f-254f-4238-90db-05582960efd9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411520631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.3411520631
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.879878825
Short name T521
Test name
Test status
Simulation time 59246706 ps
CPU time 0.57 seconds
Started Jul 07 06:00:15 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 182212 kb
Host smart-446c7878-a6f1-4c5f-8e97-090200c05c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879878825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.879878825
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3389607361
Short name T547
Test name
Test status
Simulation time 57207954 ps
CPU time 0.78 seconds
Started Jul 07 06:00:24 PM PDT 24
Finished Jul 07 06:00:26 PM PDT 24
Peak memory 191248 kb
Host smart-571bbb86-4904-4818-b300-beae1db4fcba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389607361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3389607361
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.891587862
Short name T581
Test name
Test status
Simulation time 175368982 ps
CPU time 1.1 seconds
Started Jul 07 06:00:23 PM PDT 24
Finished Jul 07 06:00:24 PM PDT 24
Peak memory 196952 kb
Host smart-8e0dba5a-4982-422e-b4a2-7e27772f4fec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891587862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.891587862
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1797877902
Short name T497
Test name
Test status
Simulation time 78557916 ps
CPU time 1.2 seconds
Started Jul 07 06:00:20 PM PDT 24
Finished Jul 07 06:00:22 PM PDT 24
Peak memory 182988 kb
Host smart-a074a1e8-342c-44fe-9825-b6d154de9357
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797877902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1797877902
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3186906707
Short name T537
Test name
Test status
Simulation time 1604477067 ps
CPU time 3.66 seconds
Started Jul 07 06:00:05 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 193244 kb
Host smart-63bcb778-74d7-4dd2-a268-452f5e48f318
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186906707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3186906707
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3294390323
Short name T483
Test name
Test status
Simulation time 49887341 ps
CPU time 0.63 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:08 PM PDT 24
Peak memory 182280 kb
Host smart-409b9670-bce6-4645-9bf7-1f68019e03d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294390323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3294390323
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.4156390280
Short name T463
Test name
Test status
Simulation time 21799677 ps
CPU time 0.89 seconds
Started Jul 07 06:00:04 PM PDT 24
Finished Jul 07 06:00:05 PM PDT 24
Peak memory 196952 kb
Host smart-c938d094-d23e-4498-b37a-73910844cc6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156390280 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.4156390280
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.2666176862
Short name T68
Test name
Test status
Simulation time 92224644 ps
CPU time 0.59 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:08 PM PDT 24
Peak memory 191552 kb
Host smart-5cf9cca4-19d3-4e9e-913d-28134412a585
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666176862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.2666176862
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3109930523
Short name T556
Test name
Test status
Simulation time 41098461 ps
CPU time 0.56 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 182152 kb
Host smart-147e5928-3f16-4317-82dc-8465c241453f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109930523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3109930523
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2785404995
Short name T532
Test name
Test status
Simulation time 236852961 ps
CPU time 0.78 seconds
Started Jul 07 06:00:04 PM PDT 24
Finished Jul 07 06:00:05 PM PDT 24
Peak memory 191280 kb
Host smart-b188e96a-4871-4a37-9b5a-3dc22cf3dde6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785404995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2785404995
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4039940115
Short name T520
Test name
Test status
Simulation time 61170842 ps
CPU time 2.92 seconds
Started Jul 07 06:00:01 PM PDT 24
Finished Jul 07 06:00:05 PM PDT 24
Peak memory 197096 kb
Host smart-cb731506-59f4-4712-9caa-4eb05262c5f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039940115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4039940115
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3343795762
Short name T92
Test name
Test status
Simulation time 79901711 ps
CPU time 1.09 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 182752 kb
Host smart-349261b6-ad14-4927-a327-c250a2222af9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343795762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3343795762
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.3449416082
Short name T558
Test name
Test status
Simulation time 26961077 ps
CPU time 0.62 seconds
Started Jul 07 06:00:20 PM PDT 24
Finished Jul 07 06:00:21 PM PDT 24
Peak memory 182208 kb
Host smart-da72c58d-5c28-4018-aff2-d134bd6288a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449416082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.3449416082
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1054129938
Short name T493
Test name
Test status
Simulation time 173031526 ps
CPU time 0.54 seconds
Started Jul 07 06:00:19 PM PDT 24
Finished Jul 07 06:00:20 PM PDT 24
Peak memory 182200 kb
Host smart-72c2df75-2b03-4a9e-a01f-d7b5ddb1d5ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054129938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1054129938
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.888299184
Short name T509
Test name
Test status
Simulation time 72356742 ps
CPU time 0.57 seconds
Started Jul 07 06:00:23 PM PDT 24
Finished Jul 07 06:00:24 PM PDT 24
Peak memory 182196 kb
Host smart-b92b17a9-1142-44a5-be6d-59629a0bc119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888299184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.888299184
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.3462536945
Short name T482
Test name
Test status
Simulation time 11274382 ps
CPU time 0.57 seconds
Started Jul 07 06:00:25 PM PDT 24
Finished Jul 07 06:00:27 PM PDT 24
Peak memory 182228 kb
Host smart-16dcb158-e40e-4b9d-8662-30495680d820
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462536945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.3462536945
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2434807293
Short name T518
Test name
Test status
Simulation time 13802407 ps
CPU time 0.58 seconds
Started Jul 07 06:00:22 PM PDT 24
Finished Jul 07 06:00:23 PM PDT 24
Peak memory 182228 kb
Host smart-4f98e526-be14-46ee-8ff6-4b3d1c086531
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434807293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2434807293
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3881287041
Short name T479
Test name
Test status
Simulation time 24795896 ps
CPU time 0.54 seconds
Started Jul 07 06:00:22 PM PDT 24
Finished Jul 07 06:00:23 PM PDT 24
Peak memory 182232 kb
Host smart-37e03a4c-dafd-4930-805b-2fe3f2b9dcbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881287041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3881287041
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2362726323
Short name T492
Test name
Test status
Simulation time 23608602 ps
CPU time 0.56 seconds
Started Jul 07 06:00:22 PM PDT 24
Finished Jul 07 06:00:23 PM PDT 24
Peak memory 181868 kb
Host smart-6275e2a8-2f03-43e2-ad8f-80f8c2d0f0bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362726323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2362726323
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1334085603
Short name T564
Test name
Test status
Simulation time 38312417 ps
CPU time 0.56 seconds
Started Jul 07 06:00:22 PM PDT 24
Finished Jul 07 06:00:23 PM PDT 24
Peak memory 182164 kb
Host smart-d7466507-f842-4aac-8544-0ea4e18eb0c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334085603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1334085603
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.500265898
Short name T526
Test name
Test status
Simulation time 11125343 ps
CPU time 0.55 seconds
Started Jul 07 06:00:25 PM PDT 24
Finished Jul 07 06:00:26 PM PDT 24
Peak memory 181668 kb
Host smart-6c82ac7b-bd28-498e-8e18-ec6e1f296e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500265898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.500265898
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1031414682
Short name T527
Test name
Test status
Simulation time 46725128 ps
CPU time 0.58 seconds
Started Jul 07 06:00:19 PM PDT 24
Finished Jul 07 06:00:20 PM PDT 24
Peak memory 182196 kb
Host smart-8fd6704b-0607-44b7-87e2-9329b029496c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031414682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1031414682
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2857486831
Short name T60
Test name
Test status
Simulation time 34650992 ps
CPU time 0.8 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 192204 kb
Host smart-949ea044-fbd7-4328-831d-8918459965f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857486831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2857486831
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3259291005
Short name T71
Test name
Test status
Simulation time 2266550330 ps
CPU time 3.65 seconds
Started Jul 07 06:00:04 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 190684 kb
Host smart-5feffbd0-7a38-4c92-a140-dcda72ac3e5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259291005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3259291005
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3873514299
Short name T63
Test name
Test status
Simulation time 61625301 ps
CPU time 0.58 seconds
Started Jul 07 06:00:05 PM PDT 24
Finished Jul 07 06:00:06 PM PDT 24
Peak memory 182324 kb
Host smart-9b75bde3-4992-435a-a76b-f1b45e249482
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873514299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3873514299
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.365247997
Short name T508
Test name
Test status
Simulation time 38972068 ps
CPU time 1.93 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:11 PM PDT 24
Peak memory 197124 kb
Host smart-7c9e7f46-6397-4631-ae8c-25c4a6803807
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365247997 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.365247997
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2576199567
Short name T490
Test name
Test status
Simulation time 15468281 ps
CPU time 0.6 seconds
Started Jul 07 06:00:04 PM PDT 24
Finished Jul 07 06:00:06 PM PDT 24
Peak memory 182324 kb
Host smart-6ec4737c-bca2-4051-a776-23d4b330fff7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576199567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2576199567
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.79094963
Short name T539
Test name
Test status
Simulation time 17016965 ps
CPU time 0.5 seconds
Started Jul 07 06:00:02 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 181632 kb
Host smart-4ccd9bc2-c187-48dd-ad1e-ba6029a37a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79094963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.79094963
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1831576881
Short name T568
Test name
Test status
Simulation time 151715444 ps
CPU time 0.85 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 193132 kb
Host smart-394d17b7-fcd9-4784-833b-6167b74e6774
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831576881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1831576881
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3412725046
Short name T538
Test name
Test status
Simulation time 25081676 ps
CPU time 0.79 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 193740 kb
Host smart-47ba789c-ad6c-45d3-824f-1f5d2587eb53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412725046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3412725046
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2209413941
Short name T95
Test name
Test status
Simulation time 367797413 ps
CPU time 1.39 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 183116 kb
Host smart-e55ede02-4678-4ee0-9149-92fd543471b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209413941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2209413941
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2256164620
Short name T542
Test name
Test status
Simulation time 12222649 ps
CPU time 0.54 seconds
Started Jul 07 06:00:21 PM PDT 24
Finished Jul 07 06:00:21 PM PDT 24
Peak memory 181660 kb
Host smart-0954bb40-8e75-4164-8ef8-c6edde960d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256164620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2256164620
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3582048303
Short name T465
Test name
Test status
Simulation time 19422896 ps
CPU time 0.56 seconds
Started Jul 07 06:00:20 PM PDT 24
Finished Jul 07 06:00:21 PM PDT 24
Peak memory 182236 kb
Host smart-6af31b4a-847a-4ec4-9646-079feaf69dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582048303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3582048303
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1715030291
Short name T573
Test name
Test status
Simulation time 42427938 ps
CPU time 0.6 seconds
Started Jul 07 06:00:23 PM PDT 24
Finished Jul 07 06:00:24 PM PDT 24
Peak memory 182260 kb
Host smart-576964d9-0908-4388-8293-a82ca2c5d127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715030291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1715030291
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3772920799
Short name T474
Test name
Test status
Simulation time 112059273 ps
CPU time 0.57 seconds
Started Jul 07 06:00:23 PM PDT 24
Finished Jul 07 06:00:24 PM PDT 24
Peak memory 181620 kb
Host smart-874612bf-db5d-44cc-a214-8fb8a80d098e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772920799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3772920799
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1602793537
Short name T555
Test name
Test status
Simulation time 43791959 ps
CPU time 0.54 seconds
Started Jul 07 06:00:26 PM PDT 24
Finished Jul 07 06:00:27 PM PDT 24
Peak memory 181756 kb
Host smart-b681c5b6-0439-4bd7-bf3d-ebc32cd86a2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602793537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1602793537
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.608379562
Short name T578
Test name
Test status
Simulation time 25000791 ps
CPU time 0.53 seconds
Started Jul 07 06:00:24 PM PDT 24
Finished Jul 07 06:00:25 PM PDT 24
Peak memory 181800 kb
Host smart-878aaca6-40c0-400f-8123-1470bf182f94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608379562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.608379562
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.4261020276
Short name T552
Test name
Test status
Simulation time 33273467 ps
CPU time 0.57 seconds
Started Jul 07 06:00:22 PM PDT 24
Finished Jul 07 06:00:23 PM PDT 24
Peak memory 181680 kb
Host smart-09b3c434-0ff2-4b9a-97b5-affb6c5c34ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261020276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.4261020276
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3466717528
Short name T501
Test name
Test status
Simulation time 12118845 ps
CPU time 0.56 seconds
Started Jul 07 06:00:23 PM PDT 24
Finished Jul 07 06:00:24 PM PDT 24
Peak memory 182172 kb
Host smart-4d19665c-8835-4140-ba5b-62b1b4bb1cc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466717528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3466717528
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3737938559
Short name T458
Test name
Test status
Simulation time 28208060 ps
CPU time 0.55 seconds
Started Jul 07 06:00:24 PM PDT 24
Finished Jul 07 06:00:25 PM PDT 24
Peak memory 181852 kb
Host smart-114fde93-937d-4a2a-89c2-96a13274d423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737938559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3737938559
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1643316557
Short name T567
Test name
Test status
Simulation time 23354524 ps
CPU time 0.58 seconds
Started Jul 07 06:00:29 PM PDT 24
Finished Jul 07 06:00:29 PM PDT 24
Peak memory 182240 kb
Host smart-e5b9dd5b-119d-4bfd-b81c-f17b964d45f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643316557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1643316557
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2315319928
Short name T61
Test name
Test status
Simulation time 111688631 ps
CPU time 0.84 seconds
Started Jul 07 06:00:05 PM PDT 24
Finished Jul 07 06:00:07 PM PDT 24
Peak memory 182328 kb
Host smart-67514f4b-e827-440c-9009-c5829cbc22d7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315319928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2315319928
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3242406757
Short name T73
Test name
Test status
Simulation time 1187235268 ps
CPU time 3.46 seconds
Started Jul 07 06:00:06 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 190672 kb
Host smart-3be16c7d-cf96-4140-8800-143edd3d164e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242406757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3242406757
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2372153972
Short name T499
Test name
Test status
Simulation time 21295155 ps
CPU time 0.57 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:08 PM PDT 24
Peak memory 182328 kb
Host smart-046bd2da-f1dd-46e1-97e2-e81a86abdfca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372153972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2372153972
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2364664569
Short name T543
Test name
Test status
Simulation time 31427544 ps
CPU time 1.38 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 197056 kb
Host smart-8c697802-8d08-4e53-8cd6-c99f9f317ac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364664569 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2364664569
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2232941254
Short name T512
Test name
Test status
Simulation time 19122360 ps
CPU time 0.56 seconds
Started Jul 07 06:00:06 PM PDT 24
Finished Jul 07 06:00:07 PM PDT 24
Peak memory 182080 kb
Host smart-1edc02f0-9f0f-49d4-ba1c-c2e50cea204a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232941254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2232941254
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1641091787
Short name T464
Test name
Test status
Simulation time 19568508 ps
CPU time 0.56 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:08 PM PDT 24
Peak memory 182160 kb
Host smart-33006b2d-665d-4b01-bb8f-bb99feab43ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641091787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1641091787
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.255862627
Short name T80
Test name
Test status
Simulation time 18423170 ps
CPU time 0.75 seconds
Started Jul 07 06:00:10 PM PDT 24
Finished Jul 07 06:00:11 PM PDT 24
Peak memory 191224 kb
Host smart-11c19a51-71a2-4f3f-8b25-0597a8752b05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255862627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.255862627
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.400811031
Short name T549
Test name
Test status
Simulation time 32127630 ps
CPU time 0.91 seconds
Started Jul 07 06:00:03 PM PDT 24
Finished Jul 07 06:00:04 PM PDT 24
Peak memory 194836 kb
Host smart-39fe7df9-a7d1-45a1-ab67-bcd4bd45be63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400811031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.400811031
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.555985483
Short name T544
Test name
Test status
Simulation time 276872531 ps
CPU time 1.08 seconds
Started Jul 07 06:00:03 PM PDT 24
Finished Jul 07 06:00:05 PM PDT 24
Peak memory 194872 kb
Host smart-e459ece1-9375-401b-ad25-c7bb45d955c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555985483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.555985483
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.2522274199
Short name T469
Test name
Test status
Simulation time 55233745 ps
CPU time 0.58 seconds
Started Jul 07 06:00:23 PM PDT 24
Finished Jul 07 06:00:24 PM PDT 24
Peak memory 182168 kb
Host smart-d0904888-ed7f-4ed4-942a-c1157533a4f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522274199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.2522274199
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.1743403965
Short name T580
Test name
Test status
Simulation time 24854930 ps
CPU time 0.52 seconds
Started Jul 07 06:00:19 PM PDT 24
Finished Jul 07 06:00:20 PM PDT 24
Peak memory 181668 kb
Host smart-7656fbb4-a7a0-4334-bea5-91e8c8e22796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743403965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.1743403965
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1583762313
Short name T487
Test name
Test status
Simulation time 10990110 ps
CPU time 0.55 seconds
Started Jul 07 06:00:24 PM PDT 24
Finished Jul 07 06:00:25 PM PDT 24
Peak memory 182212 kb
Host smart-6d8da478-f38c-4eb3-8b19-3701e9cc1e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583762313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1583762313
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1967681179
Short name T560
Test name
Test status
Simulation time 21096832 ps
CPU time 0.57 seconds
Started Jul 07 06:00:26 PM PDT 24
Finished Jul 07 06:00:27 PM PDT 24
Peak memory 181848 kb
Host smart-2af74ccc-f07f-4303-aa0b-c8df76942e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967681179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1967681179
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2337257031
Short name T519
Test name
Test status
Simulation time 15328445 ps
CPU time 0.55 seconds
Started Jul 07 06:00:27 PM PDT 24
Finished Jul 07 06:00:28 PM PDT 24
Peak memory 182144 kb
Host smart-7779bc69-20ff-4376-b396-8e396dd0bfb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337257031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2337257031
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1975024187
Short name T525
Test name
Test status
Simulation time 21864089 ps
CPU time 0.54 seconds
Started Jul 07 06:00:23 PM PDT 24
Finished Jul 07 06:00:24 PM PDT 24
Peak memory 181860 kb
Host smart-9334b1e9-c808-4839-b29b-dba35ebe6430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975024187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1975024187
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2828938382
Short name T513
Test name
Test status
Simulation time 15865950 ps
CPU time 0.55 seconds
Started Jul 07 06:00:28 PM PDT 24
Finished Jul 07 06:00:29 PM PDT 24
Peak memory 182168 kb
Host smart-891ea91f-f8a9-4805-a100-c6a7740c9884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828938382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2828938382
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1838695899
Short name T576
Test name
Test status
Simulation time 35196638 ps
CPU time 0.57 seconds
Started Jul 07 06:00:24 PM PDT 24
Finished Jul 07 06:00:25 PM PDT 24
Peak memory 182212 kb
Host smart-945572be-355b-44a1-a89d-3be79f8dba59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838695899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1838695899
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1791519998
Short name T534
Test name
Test status
Simulation time 24075326 ps
CPU time 0.62 seconds
Started Jul 07 06:00:29 PM PDT 24
Finished Jul 07 06:00:30 PM PDT 24
Peak memory 182216 kb
Host smart-f681dd52-f770-4aa3-a432-a41e2a024268
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791519998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1791519998
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2096568253
Short name T467
Test name
Test status
Simulation time 12994271 ps
CPU time 0.52 seconds
Started Jul 07 06:00:30 PM PDT 24
Finished Jul 07 06:00:31 PM PDT 24
Peak memory 181664 kb
Host smart-56020510-e568-4f4b-b701-de261873d506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096568253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2096568253
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.74043463
Short name T486
Test name
Test status
Simulation time 49983149 ps
CPU time 0.74 seconds
Started Jul 07 06:00:06 PM PDT 24
Finished Jul 07 06:00:07 PM PDT 24
Peak memory 193880 kb
Host smart-e03fdd75-c2bf-4b3f-8ac9-172b232c1cc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74043463 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.74043463
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2584739920
Short name T69
Test name
Test status
Simulation time 43336497 ps
CPU time 0.56 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 182112 kb
Host smart-67143ff3-203d-4c9c-aff8-e68631ded857
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584739920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2584739920
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.711477270
Short name T459
Test name
Test status
Simulation time 18425523 ps
CPU time 0.54 seconds
Started Jul 07 06:00:11 PM PDT 24
Finished Jul 07 06:00:12 PM PDT 24
Peak memory 181684 kb
Host smart-8a5573f9-4189-45cc-8604-5d9ad63fee56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711477270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.711477270
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2839141992
Short name T529
Test name
Test status
Simulation time 59983307 ps
CPU time 0.67 seconds
Started Jul 07 06:00:11 PM PDT 24
Finished Jul 07 06:00:12 PM PDT 24
Peak memory 191596 kb
Host smart-ea06d158-dfa4-4e13-a18b-32d595011e4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839141992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2839141992
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.1414878326
Short name T471
Test name
Test status
Simulation time 37264328 ps
CPU time 1.82 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 197016 kb
Host smart-74d4c062-89b2-42b8-87a4-49a7f232baac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414878326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.1414878326
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1572313425
Short name T23
Test name
Test status
Simulation time 146174345 ps
CPU time 1.09 seconds
Started Jul 07 06:00:06 PM PDT 24
Finished Jul 07 06:00:08 PM PDT 24
Peak memory 182852 kb
Host smart-722273e4-4be0-4170-97ad-0663f40e2a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572313425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1572313425
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1038974327
Short name T540
Test name
Test status
Simulation time 24003136 ps
CPU time 0.71 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:15 PM PDT 24
Peak memory 194208 kb
Host smart-12cc977f-f9e0-4a9c-88be-fc2e13171dbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038974327 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1038974327
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3102275823
Short name T531
Test name
Test status
Simulation time 17043940 ps
CPU time 0.54 seconds
Started Jul 07 06:00:10 PM PDT 24
Finished Jul 07 06:00:11 PM PDT 24
Peak memory 182268 kb
Host smart-1a112df6-7fa6-4886-948b-8f401d114a7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102275823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3102275823
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2866407138
Short name T565
Test name
Test status
Simulation time 40887937 ps
CPU time 0.62 seconds
Started Jul 07 06:00:10 PM PDT 24
Finished Jul 07 06:00:12 PM PDT 24
Peak memory 182196 kb
Host smart-82155cb7-f23b-4bbf-8d81-cd3f13cbc571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866407138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2866407138
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.454172591
Short name T77
Test name
Test status
Simulation time 16327111 ps
CPU time 0.7 seconds
Started Jul 07 06:00:09 PM PDT 24
Finished Jul 07 06:00:11 PM PDT 24
Peak memory 191004 kb
Host smart-153c9825-de1d-40d5-aa00-eeb8c07a3e78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454172591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.454172591
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1623824280
Short name T574
Test name
Test status
Simulation time 311749161 ps
CPU time 2.2 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:15 PM PDT 24
Peak memory 197104 kb
Host smart-103859ac-5017-4b59-84a0-77da0277944f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623824280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1623824280
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.169933645
Short name T41
Test name
Test status
Simulation time 775938114 ps
CPU time 1.43 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 194820 kb
Host smart-77bcc0ff-977c-4546-9021-843bb9a3727c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169933645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_int
g_err.169933645
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.617818730
Short name T557
Test name
Test status
Simulation time 23683921 ps
CPU time 1.01 seconds
Started Jul 07 06:00:09 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 196840 kb
Host smart-b64c25ee-7b69-40f3-aaf0-19934b9ab530
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617818730 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.617818730
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1100327892
Short name T74
Test name
Test status
Simulation time 33952064 ps
CPU time 0.56 seconds
Started Jul 07 06:00:09 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 182312 kb
Host smart-3f5a0e07-c6ae-45cf-9707-de76411c4ee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100327892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1100327892
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.552972061
Short name T491
Test name
Test status
Simulation time 41188603 ps
CPU time 0.54 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 181940 kb
Host smart-23886236-fffe-4133-84c6-1324b66eb2cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552972061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.552972061
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.240910104
Short name T475
Test name
Test status
Simulation time 75356765 ps
CPU time 1.95 seconds
Started Jul 07 06:00:13 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 197092 kb
Host smart-6b6e7823-0f77-4389-91de-72955f976443
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240910104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.240910104
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3491239851
Short name T37
Test name
Test status
Simulation time 25663209 ps
CPU time 0.62 seconds
Started Jul 07 06:00:05 PM PDT 24
Finished Jul 07 06:00:06 PM PDT 24
Peak memory 192580 kb
Host smart-b7022f40-f4cc-4c33-9455-a18dee175f30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491239851 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3491239851
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1004892953
Short name T488
Test name
Test status
Simulation time 43872003 ps
CPU time 0.53 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 182288 kb
Host smart-dbbc4a4a-332f-41c3-b5ad-8d28b66128fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004892953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1004892953
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3548955132
Short name T528
Test name
Test status
Simulation time 23529579 ps
CPU time 0.58 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 182200 kb
Host smart-8a37ad4b-1248-4b51-85d3-6e23b9750e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548955132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3548955132
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2304917572
Short name T506
Test name
Test status
Simulation time 143023896 ps
CPU time 0.66 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 191244 kb
Host smart-bc049fa3-8a78-460c-bc9b-36ced3a77b18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304917572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2304917572
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3854530292
Short name T510
Test name
Test status
Simulation time 162530565 ps
CPU time 1.16 seconds
Started Jul 07 06:00:11 PM PDT 24
Finished Jul 07 06:00:13 PM PDT 24
Peak memory 197076 kb
Host smart-012022f5-6b9e-44f0-82be-9172dfeb4f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854530292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3854530292
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.1612411667
Short name T24
Test name
Test status
Simulation time 90638254 ps
CPU time 1.18 seconds
Started Jul 07 06:00:10 PM PDT 24
Finished Jul 07 06:00:12 PM PDT 24
Peak memory 194404 kb
Host smart-7499f4d0-1797-40ae-8b4f-f4d54ddc3def
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612411667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.1612411667
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3582591215
Short name T473
Test name
Test status
Simulation time 51793551 ps
CPU time 0.71 seconds
Started Jul 07 06:00:09 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 194700 kb
Host smart-f7662074-abb3-426b-8358-1b994450117c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582591215 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3582591215
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1786998497
Short name T64
Test name
Test status
Simulation time 17010094 ps
CPU time 0.57 seconds
Started Jul 07 06:00:10 PM PDT 24
Finished Jul 07 06:00:12 PM PDT 24
Peak memory 182324 kb
Host smart-99a1f766-7c82-4a2d-960b-cb182779c3b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786998497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1786998497
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2628869275
Short name T481
Test name
Test status
Simulation time 35973661 ps
CPU time 0.52 seconds
Started Jul 07 06:00:10 PM PDT 24
Finished Jul 07 06:00:11 PM PDT 24
Peak memory 181900 kb
Host smart-93a369fe-8d0b-44de-b4c7-78b830096d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628869275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2628869275
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3177087677
Short name T62
Test name
Test status
Simulation time 68391077 ps
CPU time 0.8 seconds
Started Jul 07 06:00:12 PM PDT 24
Finished Jul 07 06:00:13 PM PDT 24
Peak memory 191244 kb
Host smart-ccf3dd49-9239-41e6-9f46-67566e16118f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177087677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3177087677
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2829360656
Short name T522
Test name
Test status
Simulation time 92975996 ps
CPU time 1.24 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 196984 kb
Host smart-1a520649-39b9-4bff-ad83-398ae4e664ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829360656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2829360656
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1088567288
Short name T505
Test name
Test status
Simulation time 470046272 ps
CPU time 0.84 seconds
Started Jul 07 06:00:14 PM PDT 24
Finished Jul 07 06:00:17 PM PDT 24
Peak memory 182520 kb
Host smart-d328f71d-f962-498d-bec3-7d352829a159
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088567288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1088567288
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2063166343
Short name T7
Test name
Test status
Simulation time 28360634485 ps
CPU time 15.72 seconds
Started Jul 07 06:05:20 PM PDT 24
Finished Jul 07 06:05:37 PM PDT 24
Peak memory 183140 kb
Host smart-77e5c492-1d09-4f1b-9d3e-feca8ae4c271
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063166343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2063166343
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.395435124
Short name T453
Test name
Test status
Simulation time 78017410434 ps
CPU time 64.27 seconds
Started Jul 07 06:05:20 PM PDT 24
Finished Jul 07 06:06:25 PM PDT 24
Peak memory 183140 kb
Host smart-45802cda-c554-4bd8-bdd8-4d1585d7939f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395435124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.395435124
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.1292986831
Short name T421
Test name
Test status
Simulation time 503036815144 ps
CPU time 144.82 seconds
Started Jul 07 06:05:20 PM PDT 24
Finished Jul 07 06:07:46 PM PDT 24
Peak memory 183112 kb
Host smart-4059cd91-33be-4ab3-8c42-77907fa01dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292986831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1292986831
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.3562202424
Short name T286
Test name
Test status
Simulation time 135741456587 ps
CPU time 66.85 seconds
Started Jul 07 06:05:34 PM PDT 24
Finished Jul 07 06:06:41 PM PDT 24
Peak memory 183144 kb
Host smart-875e0197-94ec-4709-a98f-e1353bd76378
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562202424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.3562202424
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3597142025
Short name T397
Test name
Test status
Simulation time 94012267517 ps
CPU time 130.18 seconds
Started Jul 07 06:05:27 PM PDT 24
Finished Jul 07 06:07:38 PM PDT 24
Peak memory 183084 kb
Host smart-59db6546-bd8a-4fbd-b7d9-ba6c4d257945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597142025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3597142025
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3739908535
Short name T103
Test name
Test status
Simulation time 134889572656 ps
CPU time 99.22 seconds
Started Jul 07 06:05:23 PM PDT 24
Finished Jul 07 06:07:03 PM PDT 24
Peak memory 191288 kb
Host smart-2e65d6c2-0be9-470b-b738-45f503148005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739908535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3739908535
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.544363826
Short name T437
Test name
Test status
Simulation time 37235099781 ps
CPU time 322.23 seconds
Started Jul 07 06:05:27 PM PDT 24
Finished Jul 07 06:10:50 PM PDT 24
Peak memory 183156 kb
Host smart-6a9721b0-caef-45e5-a4f8-1865529922f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544363826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.544363826
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2194536784
Short name T16
Test name
Test status
Simulation time 38004671 ps
CPU time 0.74 seconds
Started Jul 07 06:05:30 PM PDT 24
Finished Jul 07 06:05:32 PM PDT 24
Peak memory 213348 kb
Host smart-5e2ddc1b-69e3-4c35-928e-55e625a1b44b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194536784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2194536784
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1278094180
Short name T404
Test name
Test status
Simulation time 572289992203 ps
CPU time 64.29 seconds
Started Jul 07 06:06:06 PM PDT 24
Finished Jul 07 06:07:11 PM PDT 24
Peak memory 183100 kb
Host smart-ef2a1235-6f77-4ec0-a39b-2e78ec351dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278094180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1278094180
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.4267004931
Short name T194
Test name
Test status
Simulation time 19954989719 ps
CPU time 14.77 seconds
Started Jul 07 06:06:10 PM PDT 24
Finished Jul 07 06:06:25 PM PDT 24
Peak memory 183152 kb
Host smart-43e59799-ec68-4a42-8be7-fe542468fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267004931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.4267004931
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.2040801016
Short name T31
Test name
Test status
Simulation time 105423332744 ps
CPU time 658.15 seconds
Started Jul 07 06:06:09 PM PDT 24
Finished Jul 07 06:17:07 PM PDT 24
Peak memory 207584 kb
Host smart-704cea08-b3bf-4c73-962a-f43921fe47db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040801016 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.2040801016
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.1612565948
Short name T296
Test name
Test status
Simulation time 540819552324 ps
CPU time 2098.78 seconds
Started Jul 07 06:08:56 PM PDT 24
Finished Jul 07 06:43:56 PM PDT 24
Peak memory 191328 kb
Host smart-c3317825-d1cd-4bac-b9dd-3a14aef9c44c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612565948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1612565948
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3588735322
Short name T449
Test name
Test status
Simulation time 116713204193 ps
CPU time 181.13 seconds
Started Jul 07 06:08:57 PM PDT 24
Finished Jul 07 06:11:59 PM PDT 24
Peak memory 191340 kb
Host smart-bcd394ef-2f01-471e-9daf-65ce17b05053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588735322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3588735322
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.422743105
Short name T327
Test name
Test status
Simulation time 87674652429 ps
CPU time 195.73 seconds
Started Jul 07 06:08:57 PM PDT 24
Finished Jul 07 06:12:13 PM PDT 24
Peak memory 191320 kb
Host smart-409b4844-e924-4c70-aef0-7a69dab58a23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422743105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.422743105
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1274979386
Short name T20
Test name
Test status
Simulation time 60456456942 ps
CPU time 78.59 seconds
Started Jul 07 06:08:57 PM PDT 24
Finished Jul 07 06:10:16 PM PDT 24
Peak memory 191332 kb
Host smart-ec310c11-905c-4790-bf78-56c586ae94ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274979386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1274979386
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.146952488
Short name T221
Test name
Test status
Simulation time 22084853938 ps
CPU time 33.96 seconds
Started Jul 07 06:08:54 PM PDT 24
Finished Jul 07 06:09:29 PM PDT 24
Peak memory 183144 kb
Host smart-45f177eb-51ec-4c34-b0cb-3b49f6fdca5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146952488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.146952488
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1787983479
Short name T405
Test name
Test status
Simulation time 369815308831 ps
CPU time 566.71 seconds
Started Jul 07 06:09:05 PM PDT 24
Finished Jul 07 06:18:32 PM PDT 24
Peak memory 191304 kb
Host smart-defca8fe-be5d-41d2-ad9d-6da1d4997b2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787983479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1787983479
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3705240605
Short name T393
Test name
Test status
Simulation time 166156925134 ps
CPU time 242.34 seconds
Started Jul 07 06:06:10 PM PDT 24
Finished Jul 07 06:10:13 PM PDT 24
Peak memory 183120 kb
Host smart-66371dbc-ba11-44ac-8e1d-ee6902c39563
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705240605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3705240605
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3667273954
Short name T407
Test name
Test status
Simulation time 92440005017 ps
CPU time 87.48 seconds
Started Jul 07 06:06:10 PM PDT 24
Finished Jul 07 06:07:38 PM PDT 24
Peak memory 183092 kb
Host smart-300c51aa-8fe4-407d-b9bc-8a27657f3602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667273954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3667273954
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.3553491654
Short name T10
Test name
Test status
Simulation time 88954148227 ps
CPU time 48.85 seconds
Started Jul 07 06:06:13 PM PDT 24
Finished Jul 07 06:07:02 PM PDT 24
Peak memory 183108 kb
Host smart-ef99e5dc-c4e0-4569-97b5-1dc3bfd7f2ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553491654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3553491654
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1267306981
Short name T417
Test name
Test status
Simulation time 57544234 ps
CPU time 0.57 seconds
Started Jul 07 06:06:15 PM PDT 24
Finished Jul 07 06:06:16 PM PDT 24
Peak memory 182876 kb
Host smart-e675be7d-d5a1-4b6e-ba81-faea89cbf1cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267306981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1267306981
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.2345299084
Short name T108
Test name
Test status
Simulation time 538098816957 ps
CPU time 371.73 seconds
Started Jul 07 06:09:04 PM PDT 24
Finished Jul 07 06:15:16 PM PDT 24
Peak memory 191316 kb
Host smart-45916f89-cf7d-4d98-aa89-c420eb916501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345299084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2345299084
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1656648396
Short name T258
Test name
Test status
Simulation time 241394600374 ps
CPU time 307.72 seconds
Started Jul 07 06:09:04 PM PDT 24
Finished Jul 07 06:14:12 PM PDT 24
Peak memory 193384 kb
Host smart-e1129382-da6e-4c34-aa65-fda43ac331a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656648396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1656648396
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2040795209
Short name T86
Test name
Test status
Simulation time 726939343173 ps
CPU time 234.26 seconds
Started Jul 07 06:09:04 PM PDT 24
Finished Jul 07 06:12:59 PM PDT 24
Peak memory 191316 kb
Host smart-84cb49ec-d36d-4a3c-90bc-496ac16c6235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040795209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2040795209
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.11149053
Short name T43
Test name
Test status
Simulation time 246105164956 ps
CPU time 1622.39 seconds
Started Jul 07 06:09:04 PM PDT 24
Finished Jul 07 06:36:06 PM PDT 24
Peak memory 191304 kb
Host smart-fe1716fc-4312-4e55-a05f-9eb562c002bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11149053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.11149053
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2155051134
Short name T323
Test name
Test status
Simulation time 262525139445 ps
CPU time 1428.61 seconds
Started Jul 07 06:09:06 PM PDT 24
Finished Jul 07 06:32:55 PM PDT 24
Peak memory 191336 kb
Host smart-e0d00906-2de3-4c98-8a50-07cf04de9986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155051134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2155051134
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.859207099
Short name T341
Test name
Test status
Simulation time 828277830433 ps
CPU time 1105.58 seconds
Started Jul 07 06:09:04 PM PDT 24
Finished Jul 07 06:27:30 PM PDT 24
Peak memory 191320 kb
Host smart-ab4e7e9f-b4e9-4706-83ec-623e635bb2e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859207099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.859207099
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.149237425
Short name T338
Test name
Test status
Simulation time 16256397021 ps
CPU time 7.04 seconds
Started Jul 07 06:09:07 PM PDT 24
Finished Jul 07 06:09:15 PM PDT 24
Peak memory 183056 kb
Host smart-5b292cee-5306-4f86-b684-760a18d3f7cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149237425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.149237425
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.3517296558
Short name T121
Test name
Test status
Simulation time 1720262259516 ps
CPU time 905.26 seconds
Started Jul 07 06:06:15 PM PDT 24
Finished Jul 07 06:21:20 PM PDT 24
Peak memory 183116 kb
Host smart-4ce71b4c-beac-469b-894e-548b18578819
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517296558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.3517296558
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2094850337
Short name T375
Test name
Test status
Simulation time 208214740745 ps
CPU time 278.39 seconds
Started Jul 07 06:06:15 PM PDT 24
Finished Jul 07 06:10:54 PM PDT 24
Peak memory 183112 kb
Host smart-e2c0ea2c-976d-4760-b975-54aa869123da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094850337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2094850337
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1186572454
Short name T297
Test name
Test status
Simulation time 167842396669 ps
CPU time 86.43 seconds
Started Jul 07 06:06:10 PM PDT 24
Finished Jul 07 06:07:37 PM PDT 24
Peak memory 191312 kb
Host smart-cee319d7-4ac2-4422-aaeb-89cc8ee365ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186572454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1186572454
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1166177104
Short name T420
Test name
Test status
Simulation time 615088883199 ps
CPU time 410.59 seconds
Started Jul 07 06:06:17 PM PDT 24
Finished Jul 07 06:13:07 PM PDT 24
Peak memory 191356 kb
Host smart-68260447-c092-48ee-a40e-78608c66baa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166177104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1166177104
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.4069935482
Short name T274
Test name
Test status
Simulation time 238555495413 ps
CPU time 2004.87 seconds
Started Jul 07 06:09:08 PM PDT 24
Finished Jul 07 06:42:33 PM PDT 24
Peak memory 191348 kb
Host smart-0ae06193-ac9b-43a5-8729-8f2dad756777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069935482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.4069935482
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.779768174
Short name T427
Test name
Test status
Simulation time 76113095613 ps
CPU time 54.96 seconds
Started Jul 07 06:09:07 PM PDT 24
Finished Jul 07 06:10:02 PM PDT 24
Peak memory 191348 kb
Host smart-63447273-0bfb-4b58-bcbc-158a01b7fe86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779768174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.779768174
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.4050882175
Short name T111
Test name
Test status
Simulation time 52836678047 ps
CPU time 111.44 seconds
Started Jul 07 06:09:12 PM PDT 24
Finished Jul 07 06:11:03 PM PDT 24
Peak memory 191316 kb
Host smart-817897d0-1348-4116-bc97-49bf9e3b70bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050882175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.4050882175
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1336418559
Short name T455
Test name
Test status
Simulation time 238951531702 ps
CPU time 1836.95 seconds
Started Jul 07 06:09:10 PM PDT 24
Finished Jul 07 06:39:48 PM PDT 24
Peak memory 191332 kb
Host smart-4b7df823-90aa-41c2-90d8-471a0a091625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336418559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1336418559
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2938198447
Short name T165
Test name
Test status
Simulation time 249699679415 ps
CPU time 852.05 seconds
Started Jul 07 06:09:10 PM PDT 24
Finished Jul 07 06:23:22 PM PDT 24
Peak memory 191284 kb
Host smart-e3fe1412-0df5-4152-a8b2-c92b0a653c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938198447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2938198447
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3808736066
Short name T439
Test name
Test status
Simulation time 88998515884 ps
CPU time 301.11 seconds
Started Jul 07 06:09:15 PM PDT 24
Finished Jul 07 06:14:16 PM PDT 24
Peak memory 191336 kb
Host smart-c150a1a3-46a1-451b-95a3-b320948fbae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808736066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3808736066
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2175758149
Short name T85
Test name
Test status
Simulation time 798217772454 ps
CPU time 314.29 seconds
Started Jul 07 06:09:17 PM PDT 24
Finished Jul 07 06:14:32 PM PDT 24
Peak memory 191276 kb
Host smart-9cf1ac77-4c6c-4500-bc50-f039cf12d0d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175758149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2175758149
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3381662812
Short name T353
Test name
Test status
Simulation time 50419079366 ps
CPU time 37.67 seconds
Started Jul 07 06:09:17 PM PDT 24
Finished Jul 07 06:09:55 PM PDT 24
Peak memory 194696 kb
Host smart-6a4e1354-f3a6-43fe-9f52-e07b0abfcf49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381662812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3381662812
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2267334456
Short name T195
Test name
Test status
Simulation time 112208226770 ps
CPU time 179.79 seconds
Started Jul 07 06:06:17 PM PDT 24
Finished Jul 07 06:09:17 PM PDT 24
Peak memory 183116 kb
Host smart-3d325fb3-f26c-4ebf-859a-3471689ad8fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267334456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2267334456
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1896851581
Short name T378
Test name
Test status
Simulation time 69696406921 ps
CPU time 103.76 seconds
Started Jul 07 06:06:14 PM PDT 24
Finished Jul 07 06:07:58 PM PDT 24
Peak memory 183004 kb
Host smart-5d83d45c-3473-4652-babe-7090397fd0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896851581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1896851581
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/130.rv_timer_random.2288172738
Short name T255
Test name
Test status
Simulation time 87543406108 ps
CPU time 80.4 seconds
Started Jul 07 06:09:12 PM PDT 24
Finished Jul 07 06:10:33 PM PDT 24
Peak memory 193624 kb
Host smart-635588be-761c-4146-a056-e4f253121a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288172738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2288172738
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3491834544
Short name T132
Test name
Test status
Simulation time 92547973276 ps
CPU time 49.28 seconds
Started Jul 07 06:09:15 PM PDT 24
Finished Jul 07 06:10:04 PM PDT 24
Peak memory 183136 kb
Host smart-1bee3edc-7d1e-47e0-9441-beab9af32967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491834544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3491834544
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3432640801
Short name T202
Test name
Test status
Simulation time 73417663066 ps
CPU time 121.02 seconds
Started Jul 07 06:09:17 PM PDT 24
Finished Jul 07 06:11:19 PM PDT 24
Peak memory 194912 kb
Host smart-7b7113bc-f926-4bbe-9847-26e71ccf56c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432640801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3432640801
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.917805426
Short name T349
Test name
Test status
Simulation time 122347939788 ps
CPU time 103.24 seconds
Started Jul 07 06:09:21 PM PDT 24
Finished Jul 07 06:11:05 PM PDT 24
Peak memory 193740 kb
Host smart-35bea124-9f14-44ed-9a40-80f956ed42ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917805426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.917805426
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.130594955
Short name T179
Test name
Test status
Simulation time 368085545296 ps
CPU time 202.31 seconds
Started Jul 07 06:09:17 PM PDT 24
Finished Jul 07 06:12:39 PM PDT 24
Peak memory 191304 kb
Host smart-e2c1b926-e813-4780-888e-de3f6cda22c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130594955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.130594955
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2573429368
Short name T154
Test name
Test status
Simulation time 272084318534 ps
CPU time 149.87 seconds
Started Jul 07 06:09:20 PM PDT 24
Finished Jul 07 06:11:50 PM PDT 24
Peak memory 191332 kb
Host smart-7982c2bb-956e-44f5-9eb2-e54d6b02c7f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573429368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2573429368
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.654067699
Short name T237
Test name
Test status
Simulation time 395945948778 ps
CPU time 182.09 seconds
Started Jul 07 06:09:24 PM PDT 24
Finished Jul 07 06:12:26 PM PDT 24
Peak memory 191368 kb
Host smart-9801eb56-25f3-4a0a-afbf-6168d9929064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654067699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.654067699
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2522537683
Short name T358
Test name
Test status
Simulation time 148281674130 ps
CPU time 223.52 seconds
Started Jul 07 06:06:17 PM PDT 24
Finished Jul 07 06:10:01 PM PDT 24
Peak memory 183100 kb
Host smart-7ff6a4a9-60e0-4eb0-a713-db74a88c9c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522537683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2522537683
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.962616524
Short name T335
Test name
Test status
Simulation time 858721813631 ps
CPU time 1049.13 seconds
Started Jul 07 06:06:15 PM PDT 24
Finished Jul 07 06:23:44 PM PDT 24
Peak memory 191340 kb
Host smart-40071b25-aa3d-4a5b-9252-f37662734cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962616524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.962616524
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3517175141
Short name T269
Test name
Test status
Simulation time 35058742642 ps
CPU time 213.66 seconds
Started Jul 07 06:06:21 PM PDT 24
Finished Jul 07 06:09:55 PM PDT 24
Peak memory 191356 kb
Host smart-b2213149-a953-4ee2-89cf-c2283193d4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517175141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3517175141
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.2987043857
Short name T136
Test name
Test status
Simulation time 999049937694 ps
CPU time 1285.68 seconds
Started Jul 07 06:06:18 PM PDT 24
Finished Jul 07 06:27:44 PM PDT 24
Peak memory 191328 kb
Host smart-05364f94-b551-48d7-bb8a-7d161dbcde5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987043857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.2987043857
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.1088089354
Short name T285
Test name
Test status
Simulation time 15362977268 ps
CPU time 23.65 seconds
Started Jul 07 06:09:20 PM PDT 24
Finished Jul 07 06:09:44 PM PDT 24
Peak memory 183020 kb
Host smart-c7209d97-f292-4cb2-9c02-ea1d588154c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088089354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1088089354
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1642123626
Short name T21
Test name
Test status
Simulation time 837529464350 ps
CPU time 376.63 seconds
Started Jul 07 06:09:23 PM PDT 24
Finished Jul 07 06:15:39 PM PDT 24
Peak memory 191296 kb
Host smart-39792a6c-dc7b-43bd-a55a-129118bad8ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642123626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1642123626
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3639497685
Short name T452
Test name
Test status
Simulation time 264589696127 ps
CPU time 495.59 seconds
Started Jul 07 06:09:23 PM PDT 24
Finished Jul 07 06:17:39 PM PDT 24
Peak memory 191604 kb
Host smart-2bfbc8c4-f44e-4b8c-9cfc-1187eb6ac84d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639497685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3639497685
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2834469599
Short name T218
Test name
Test status
Simulation time 110806713566 ps
CPU time 170.42 seconds
Started Jul 07 06:09:29 PM PDT 24
Finished Jul 07 06:12:20 PM PDT 24
Peak memory 191320 kb
Host smart-fc5c6e9f-88de-4023-98c3-078efbc48b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834469599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2834469599
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3693382859
Short name T187
Test name
Test status
Simulation time 189159068587 ps
CPU time 727.72 seconds
Started Jul 07 06:09:23 PM PDT 24
Finished Jul 07 06:21:31 PM PDT 24
Peak memory 191312 kb
Host smart-408619bc-b91a-4458-9514-684a8f19e2db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693382859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3693382859
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.1058216160
Short name T262
Test name
Test status
Simulation time 151708746140 ps
CPU time 173.91 seconds
Started Jul 07 06:09:23 PM PDT 24
Finished Jul 07 06:12:17 PM PDT 24
Peak memory 191324 kb
Host smart-e8c0754d-2941-4e17-9a7a-280a2fd78ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058216160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1058216160
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2312376416
Short name T235
Test name
Test status
Simulation time 260511162155 ps
CPU time 223.51 seconds
Started Jul 07 06:09:26 PM PDT 24
Finished Jul 07 06:13:10 PM PDT 24
Peak memory 191208 kb
Host smart-913bcaf8-b346-4fc7-90f8-d0ae1b5eab6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312376416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2312376416
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3467349709
Short name T328
Test name
Test status
Simulation time 129305347560 ps
CPU time 458.59 seconds
Started Jul 07 06:09:30 PM PDT 24
Finished Jul 07 06:17:08 PM PDT 24
Peak memory 191248 kb
Host smart-bca677ab-13da-4d1a-bc4c-729bad027b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467349709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3467349709
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1610224866
Short name T444
Test name
Test status
Simulation time 19741609303 ps
CPU time 28.57 seconds
Started Jul 07 06:06:21 PM PDT 24
Finished Jul 07 06:06:50 PM PDT 24
Peak memory 183128 kb
Host smart-e77b9bd6-8793-48a8-a718-ad0c5a15cb1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610224866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1610224866
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.1856106106
Short name T345
Test name
Test status
Simulation time 16880177417 ps
CPU time 16.71 seconds
Started Jul 07 06:06:18 PM PDT 24
Finished Jul 07 06:06:35 PM PDT 24
Peak memory 183076 kb
Host smart-134396be-f945-48f2-ab3d-6c06a7370379
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856106106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1856106106
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.193105308
Short name T147
Test name
Test status
Simulation time 747548807636 ps
CPU time 318.56 seconds
Started Jul 07 06:06:25 PM PDT 24
Finished Jul 07 06:11:44 PM PDT 24
Peak memory 183144 kb
Host smart-9a8858a6-eae0-438e-b03e-20da51c240be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193105308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.193105308
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3221123663
Short name T32
Test name
Test status
Simulation time 9374480544 ps
CPU time 67.83 seconds
Started Jul 07 06:06:27 PM PDT 24
Finished Jul 07 06:07:35 PM PDT 24
Peak memory 197812 kb
Host smart-498d661e-db0f-4b86-a2c9-14801a85bb4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221123663 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3221123663
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.3158954113
Short name T348
Test name
Test status
Simulation time 54231568077 ps
CPU time 381.17 seconds
Started Jul 07 06:09:30 PM PDT 24
Finished Jul 07 06:15:51 PM PDT 24
Peak memory 183140 kb
Host smart-2c62fc24-40b7-4fe7-9f67-82452e56c723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158954113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3158954113
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3200686458
Short name T125
Test name
Test status
Simulation time 672443028075 ps
CPU time 1102.91 seconds
Started Jul 07 06:09:30 PM PDT 24
Finished Jul 07 06:27:53 PM PDT 24
Peak memory 191312 kb
Host smart-f0e0418b-ed74-4506-8db2-44b174464a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200686458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3200686458
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.1879181766
Short name T322
Test name
Test status
Simulation time 65092505347 ps
CPU time 399.64 seconds
Started Jul 07 06:09:31 PM PDT 24
Finished Jul 07 06:16:11 PM PDT 24
Peak memory 191360 kb
Host smart-684ccdd9-f8e8-42d1-a9ca-f51420ec3a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879181766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.1879181766
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3924056675
Short name T158
Test name
Test status
Simulation time 515945639386 ps
CPU time 510.75 seconds
Started Jul 07 06:09:31 PM PDT 24
Finished Jul 07 06:18:02 PM PDT 24
Peak memory 191328 kb
Host smart-38cc79a1-2f94-48eb-935c-1873dfd3c1e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924056675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3924056675
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.2792599788
Short name T129
Test name
Test status
Simulation time 54549163811 ps
CPU time 82.17 seconds
Started Jul 07 06:09:35 PM PDT 24
Finished Jul 07 06:10:58 PM PDT 24
Peak memory 191256 kb
Host smart-1d3f1519-aa05-47d2-90e7-6a913ddb2a23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792599788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.2792599788
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1674164049
Short name T336
Test name
Test status
Simulation time 113604046118 ps
CPU time 102.21 seconds
Started Jul 07 06:09:37 PM PDT 24
Finished Jul 07 06:11:19 PM PDT 24
Peak memory 183084 kb
Host smart-02d65214-fd2b-4a79-9cf9-30e9e2acaa17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674164049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1674164049
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2036574240
Short name T284
Test name
Test status
Simulation time 184386302566 ps
CPU time 263.41 seconds
Started Jul 07 06:06:28 PM PDT 24
Finished Jul 07 06:10:52 PM PDT 24
Peak memory 183096 kb
Host smart-897ffa77-c6e2-4fdb-8f84-e173ba90965b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036574240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2036574240
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.57136929
Short name T388
Test name
Test status
Simulation time 378062940303 ps
CPU time 82.09 seconds
Started Jul 07 06:06:28 PM PDT 24
Finished Jul 07 06:07:51 PM PDT 24
Peak memory 183108 kb
Host smart-a0f837ca-512d-4a8b-b2c3-96f7dc2b5e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57136929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.57136929
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3915519106
Short name T321
Test name
Test status
Simulation time 9568571976 ps
CPU time 5.89 seconds
Started Jul 07 06:06:25 PM PDT 24
Finished Jul 07 06:06:32 PM PDT 24
Peak memory 191316 kb
Host smart-23b7171c-74db-4e41-bbcb-5293c8e1207a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915519106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3915519106
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.4063835922
Short name T172
Test name
Test status
Simulation time 28313210228 ps
CPU time 68.54 seconds
Started Jul 07 06:09:35 PM PDT 24
Finished Jul 07 06:10:44 PM PDT 24
Peak memory 183160 kb
Host smart-d46fee9e-cf80-41d7-910a-d24db6eef805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063835922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.4063835922
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.992155139
Short name T292
Test name
Test status
Simulation time 74323401697 ps
CPU time 46.29 seconds
Started Jul 07 06:09:34 PM PDT 24
Finished Jul 07 06:10:20 PM PDT 24
Peak memory 191296 kb
Host smart-ae4b0993-6cf6-4f5c-b923-a4fc814719f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992155139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.992155139
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.3521048986
Short name T261
Test name
Test status
Simulation time 94374961860 ps
CPU time 208.03 seconds
Started Jul 07 06:09:36 PM PDT 24
Finished Jul 07 06:13:04 PM PDT 24
Peak memory 191332 kb
Host smart-4d3b431f-172a-4411-b6e0-17c30c07af88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521048986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.3521048986
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.923443456
Short name T161
Test name
Test status
Simulation time 243614438588 ps
CPU time 303.8 seconds
Started Jul 07 06:09:37 PM PDT 24
Finished Jul 07 06:14:41 PM PDT 24
Peak memory 183124 kb
Host smart-db47b32e-3687-4620-bd67-8550ab6731bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923443456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.923443456
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2862243611
Short name T173
Test name
Test status
Simulation time 149359961561 ps
CPU time 79.27 seconds
Started Jul 07 06:09:37 PM PDT 24
Finished Jul 07 06:10:56 PM PDT 24
Peak memory 191348 kb
Host smart-146308a8-ba26-4f08-83f3-b1e342803fd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862243611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2862243611
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.6306034
Short name T273
Test name
Test status
Simulation time 153114007741 ps
CPU time 772.99 seconds
Started Jul 07 06:09:37 PM PDT 24
Finished Jul 07 06:22:30 PM PDT 24
Peak memory 191340 kb
Host smart-4e315782-a212-4532-8633-ffec351a07ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6306034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.6306034
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.515964656
Short name T340
Test name
Test status
Simulation time 57020049954 ps
CPU time 410.05 seconds
Started Jul 07 06:09:39 PM PDT 24
Finished Jul 07 06:16:29 PM PDT 24
Peak memory 191332 kb
Host smart-3c305621-30f9-479f-b7fe-5e5a4b0ad5b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515964656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.515964656
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.581128155
Short name T288
Test name
Test status
Simulation time 178407738837 ps
CPU time 571.41 seconds
Started Jul 07 06:09:36 PM PDT 24
Finished Jul 07 06:19:08 PM PDT 24
Peak memory 191348 kb
Host smart-36346012-c7b0-4667-a3c6-35044d799926
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581128155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.581128155
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1380699641
Short name T432
Test name
Test status
Simulation time 266686379883 ps
CPU time 152.5 seconds
Started Jul 07 06:06:32 PM PDT 24
Finished Jul 07 06:09:05 PM PDT 24
Peak memory 183152 kb
Host smart-2a380a18-e516-4c1c-840d-d15d32f52235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380699641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1380699641
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1402968161
Short name T264
Test name
Test status
Simulation time 196457143182 ps
CPU time 153.39 seconds
Started Jul 07 06:06:30 PM PDT 24
Finished Jul 07 06:09:04 PM PDT 24
Peak memory 191368 kb
Host smart-fbe9e45b-e044-4e93-bb0d-e758fc1c5ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402968161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1402968161
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.908671989
Short name T14
Test name
Test status
Simulation time 18032589316 ps
CPU time 100.38 seconds
Started Jul 07 06:06:30 PM PDT 24
Finished Jul 07 06:08:11 PM PDT 24
Peak memory 197824 kb
Host smart-fb4bdc3e-bc28-4880-8da3-9f9244e4a3f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908671989 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.908671989
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.1665838461
Short name T239
Test name
Test status
Simulation time 197142007357 ps
CPU time 172.65 seconds
Started Jul 07 06:09:43 PM PDT 24
Finished Jul 07 06:12:36 PM PDT 24
Peak memory 191360 kb
Host smart-722be88c-3d7c-4593-85b4-7f4b4b3f4c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665838461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1665838461
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3374887771
Short name T352
Test name
Test status
Simulation time 449078587699 ps
CPU time 283.16 seconds
Started Jul 07 06:09:45 PM PDT 24
Finished Jul 07 06:14:28 PM PDT 24
Peak memory 191328 kb
Host smart-18184849-a91a-4f20-9821-1a4e673fcafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374887771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3374887771
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3309521059
Short name T116
Test name
Test status
Simulation time 660091474148 ps
CPU time 426.65 seconds
Started Jul 07 06:09:46 PM PDT 24
Finished Jul 07 06:16:53 PM PDT 24
Peak memory 191332 kb
Host smart-c5e6e08c-ecd0-448f-9a03-387023b66a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309521059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3309521059
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3437004155
Short name T150
Test name
Test status
Simulation time 622666795881 ps
CPU time 1823.93 seconds
Started Jul 07 06:09:44 PM PDT 24
Finished Jul 07 06:40:08 PM PDT 24
Peak memory 191336 kb
Host smart-832210f0-e630-418e-aa39-ea3bd12197ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437004155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3437004155
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3993749630
Short name T199
Test name
Test status
Simulation time 100791683693 ps
CPU time 1616.77 seconds
Started Jul 07 06:09:48 PM PDT 24
Finished Jul 07 06:36:46 PM PDT 24
Peak memory 191320 kb
Host smart-72dd86fa-32da-4c44-bf77-83356e485462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993749630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3993749630
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2328329508
Short name T98
Test name
Test status
Simulation time 415443552162 ps
CPU time 190.6 seconds
Started Jul 07 06:09:44 PM PDT 24
Finished Jul 07 06:12:55 PM PDT 24
Peak memory 191300 kb
Host smart-d2534cf4-d1fa-48c6-a0dc-a7351a68a0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328329508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2328329508
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3172546901
Short name T299
Test name
Test status
Simulation time 164136168435 ps
CPU time 304.63 seconds
Started Jul 07 06:09:47 PM PDT 24
Finished Jul 07 06:14:52 PM PDT 24
Peak memory 194056 kb
Host smart-1016a2de-8dec-4e9b-9863-cd813327ea70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172546901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3172546901
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.315305961
Short name T226
Test name
Test status
Simulation time 46170393020 ps
CPU time 223.4 seconds
Started Jul 07 06:06:30 PM PDT 24
Finished Jul 07 06:10:14 PM PDT 24
Peak memory 191308 kb
Host smart-b5bfe607-f51f-4db1-a59b-e930ccf197fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315305961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.315305961
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1088865128
Short name T442
Test name
Test status
Simulation time 43745065144 ps
CPU time 340.42 seconds
Started Jul 07 06:09:43 PM PDT 24
Finished Jul 07 06:15:24 PM PDT 24
Peak memory 183028 kb
Host smart-a7419492-6d1d-4e45-bf91-c19f4a76aad8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088865128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1088865128
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1262936743
Short name T216
Test name
Test status
Simulation time 100093350080 ps
CPU time 1482.66 seconds
Started Jul 07 06:09:49 PM PDT 24
Finished Jul 07 06:34:32 PM PDT 24
Peak memory 191612 kb
Host smart-32558485-caeb-4046-8c2d-00e1883d8ead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262936743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1262936743
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.576761165
Short name T124
Test name
Test status
Simulation time 1578212317 ps
CPU time 3 seconds
Started Jul 07 06:09:47 PM PDT 24
Finished Jul 07 06:09:50 PM PDT 24
Peak memory 183000 kb
Host smart-58077fbb-5938-4e44-8b3a-1c4e60e1ee34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576761165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.576761165
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3745489786
Short name T96
Test name
Test status
Simulation time 91187135762 ps
CPU time 135.56 seconds
Started Jul 07 06:09:51 PM PDT 24
Finished Jul 07 06:12:07 PM PDT 24
Peak memory 194044 kb
Host smart-c56c39a8-0ce3-4209-930c-e10f88fb8c6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745489786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3745489786
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.469903093
Short name T205
Test name
Test status
Simulation time 115242187409 ps
CPU time 284.84 seconds
Started Jul 07 06:09:51 PM PDT 24
Finished Jul 07 06:14:36 PM PDT 24
Peak memory 191332 kb
Host smart-f9722739-7393-4762-90a3-dd8277054a6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469903093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.469903093
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.1608830829
Short name T118
Test name
Test status
Simulation time 1168794861204 ps
CPU time 200.31 seconds
Started Jul 07 06:06:36 PM PDT 24
Finished Jul 07 06:09:56 PM PDT 24
Peak memory 191252 kb
Host smart-b44035d9-6f2f-45a0-be02-83ccf9e2cf83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608830829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1608830829
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3687831423
Short name T319
Test name
Test status
Simulation time 75035815767 ps
CPU time 105.24 seconds
Started Jul 07 06:06:37 PM PDT 24
Finished Jul 07 06:08:23 PM PDT 24
Peak memory 191364 kb
Host smart-f9db3ef6-3d2e-4238-a917-ed504882e7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687831423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3687831423
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.17378363
Short name T305
Test name
Test status
Simulation time 51590198736 ps
CPU time 51.65 seconds
Started Jul 07 06:06:44 PM PDT 24
Finished Jul 07 06:07:36 PM PDT 24
Peak memory 183132 kb
Host smart-c9f38249-6494-40ff-ac23-0386e87c7527
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17378363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.17378363
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1152534170
Short name T324
Test name
Test status
Simulation time 108955858041 ps
CPU time 556.25 seconds
Started Jul 07 06:09:53 PM PDT 24
Finished Jul 07 06:19:10 PM PDT 24
Peak memory 191324 kb
Host smart-70eb5676-7182-4a03-b121-fe794524ccf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152534170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1152534170
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2880981691
Short name T249
Test name
Test status
Simulation time 83594265358 ps
CPU time 983.57 seconds
Started Jul 07 06:10:00 PM PDT 24
Finished Jul 07 06:26:24 PM PDT 24
Peak memory 194464 kb
Host smart-a4b2188c-593b-40b9-b443-05b046aa2594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880981691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2880981691
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3233141565
Short name T166
Test name
Test status
Simulation time 625742296042 ps
CPU time 381.17 seconds
Started Jul 07 06:10:00 PM PDT 24
Finished Jul 07 06:16:22 PM PDT 24
Peak memory 191328 kb
Host smart-c907b3ab-5b9b-45c7-b2e7-0a1984005e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233141565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3233141565
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2381393495
Short name T134
Test name
Test status
Simulation time 80999783084 ps
CPU time 1078.38 seconds
Started Jul 07 06:10:00 PM PDT 24
Finished Jul 07 06:27:59 PM PDT 24
Peak memory 183128 kb
Host smart-40e501dc-8630-4eea-8b38-f8c7f5746823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381393495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2381393495
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.414127619
Short name T256
Test name
Test status
Simulation time 52390819250 ps
CPU time 86.87 seconds
Started Jul 07 06:09:58 PM PDT 24
Finished Jul 07 06:11:25 PM PDT 24
Peak memory 183120 kb
Host smart-4e92a4ea-9d76-4515-b135-7ed8137dc57f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414127619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.414127619
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.222042573
Short name T411
Test name
Test status
Simulation time 279187889924 ps
CPU time 76.6 seconds
Started Jul 07 06:09:58 PM PDT 24
Finished Jul 07 06:11:14 PM PDT 24
Peak memory 183128 kb
Host smart-2c60b7f9-2883-4c67-917c-f5f50e939f45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222042573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.222042573
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2749459191
Short name T253
Test name
Test status
Simulation time 454348191670 ps
CPU time 637.39 seconds
Started Jul 07 06:05:39 PM PDT 24
Finished Jul 07 06:16:17 PM PDT 24
Peak memory 183084 kb
Host smart-8940dbf7-821c-4899-bc42-4af3fbb2ef21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749459191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2749459191
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.725356247
Short name T454
Test name
Test status
Simulation time 35950341863 ps
CPU time 47.57 seconds
Started Jul 07 06:05:36 PM PDT 24
Finished Jul 07 06:06:24 PM PDT 24
Peak memory 183160 kb
Host smart-64ff8beb-c40a-441b-a7a0-1c5b013941e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725356247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.725356247
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.2577781249
Short name T267
Test name
Test status
Simulation time 134705808336 ps
CPU time 69.68 seconds
Started Jul 07 06:05:40 PM PDT 24
Finished Jul 07 06:06:50 PM PDT 24
Peak memory 183088 kb
Host smart-363b71bf-0648-47fe-8b05-e71c4033c770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577781249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2577781249
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.237646002
Short name T242
Test name
Test status
Simulation time 71693758569 ps
CPU time 83.02 seconds
Started Jul 07 06:05:39 PM PDT 24
Finished Jul 07 06:07:02 PM PDT 24
Peak memory 191292 kb
Host smart-cbe9e388-0866-46c1-b3ef-a27442406c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237646002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.237646002
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.4257556318
Short name T5
Test name
Test status
Simulation time 61475696 ps
CPU time 0.82 seconds
Started Jul 07 06:05:39 PM PDT 24
Finished Jul 07 06:05:40 PM PDT 24
Peak memory 213408 kb
Host smart-caea565a-6a07-4b9e-8458-3f8c8d8f0ad4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257556318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.4257556318
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3588807921
Short name T396
Test name
Test status
Simulation time 20287505 ps
CPU time 0.56 seconds
Started Jul 07 06:05:39 PM PDT 24
Finished Jul 07 06:05:40 PM PDT 24
Peak memory 182960 kb
Host smart-89cd4939-60d1-4a67-ac9d-c3df4d35e591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588807921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3588807921
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.3884313518
Short name T365
Test name
Test status
Simulation time 104688833514 ps
CPU time 34.31 seconds
Started Jul 07 06:06:40 PM PDT 24
Finished Jul 07 06:07:14 PM PDT 24
Peak memory 183160 kb
Host smart-61869937-a89a-413f-84e6-67317ead3bb4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884313518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.3884313518
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.531327335
Short name T377
Test name
Test status
Simulation time 104697478488 ps
CPU time 146.08 seconds
Started Jul 07 06:06:44 PM PDT 24
Finished Jul 07 06:09:10 PM PDT 24
Peak memory 183148 kb
Host smart-6e49605d-42c5-4f7f-97c1-ac58103b1ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531327335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.531327335
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1778236357
Short name T208
Test name
Test status
Simulation time 197273347843 ps
CPU time 314.38 seconds
Started Jul 07 06:06:38 PM PDT 24
Finished Jul 07 06:11:53 PM PDT 24
Peak memory 191348 kb
Host smart-bf386d8d-8863-4fa5-b9d0-f4d50ef2850f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778236357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1778236357
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3230359007
Short name T383
Test name
Test status
Simulation time 397703518 ps
CPU time 0.67 seconds
Started Jul 07 06:06:41 PM PDT 24
Finished Jul 07 06:06:42 PM PDT 24
Peak memory 191680 kb
Host smart-c5980ae5-ad37-4047-a240-02af1068b2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230359007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3230359007
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3860758536
Short name T401
Test name
Test status
Simulation time 77971042817 ps
CPU time 855.36 seconds
Started Jul 07 06:06:46 PM PDT 24
Finished Jul 07 06:21:02 PM PDT 24
Peak memory 212668 kb
Host smart-720d14ea-20d3-4d3e-8118-f17b5de4f791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860758536 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3860758536
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.774845434
Short name T157
Test name
Test status
Simulation time 306345057441 ps
CPU time 514.98 seconds
Started Jul 07 06:06:50 PM PDT 24
Finished Jul 07 06:15:26 PM PDT 24
Peak memory 183148 kb
Host smart-d901497f-537b-47ff-8bca-f738f0edfbd5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774845434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.774845434
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3105183544
Short name T434
Test name
Test status
Simulation time 139536225720 ps
CPU time 209.28 seconds
Started Jul 07 06:06:47 PM PDT 24
Finished Jul 07 06:10:17 PM PDT 24
Peak memory 183160 kb
Host smart-ea3e8f90-b82b-474d-93cf-41e2f13adc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105183544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3105183544
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.2927157762
Short name T128
Test name
Test status
Simulation time 205715620739 ps
CPU time 80.84 seconds
Started Jul 07 06:06:47 PM PDT 24
Finished Jul 07 06:08:09 PM PDT 24
Peak memory 183144 kb
Host smart-a4207003-ab7b-42d8-be54-9c164cbe0b7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927157762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2927157762
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3397963302
Short name T360
Test name
Test status
Simulation time 890929549 ps
CPU time 0.82 seconds
Started Jul 07 06:06:50 PM PDT 24
Finished Jul 07 06:06:51 PM PDT 24
Peak memory 183016 kb
Host smart-fb4a2d21-a81a-4219-90e5-b9a868e33d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397963302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3397963302
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.751834554
Short name T376
Test name
Test status
Simulation time 683003051371 ps
CPU time 137.21 seconds
Started Jul 07 06:06:51 PM PDT 24
Finished Jul 07 06:09:08 PM PDT 24
Peak memory 194592 kb
Host smart-40ce2a8d-0f4a-424a-9bc1-b6c6794054b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751834554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
751834554
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.162757454
Short name T144
Test name
Test status
Simulation time 9861302471 ps
CPU time 16.75 seconds
Started Jul 07 06:06:58 PM PDT 24
Finished Jul 07 06:07:15 PM PDT 24
Peak memory 183124 kb
Host smart-0abbc8bf-cbdf-43f9-a686-043bd2c89853
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162757454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.rv_timer_cfg_update_on_fly.162757454
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3506590421
Short name T391
Test name
Test status
Simulation time 667382926619 ps
CPU time 88.6 seconds
Started Jul 07 06:06:53 PM PDT 24
Finished Jul 07 06:08:22 PM PDT 24
Peak memory 183156 kb
Host smart-bf676143-76ce-47e0-8739-61a56eaa8847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506590421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3506590421
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.3225948340
Short name T217
Test name
Test status
Simulation time 57143072544 ps
CPU time 66.09 seconds
Started Jul 07 06:06:52 PM PDT 24
Finished Jul 07 06:07:58 PM PDT 24
Peak memory 183152 kb
Host smart-22a16c9a-62f4-4130-880f-3cfca86ba28a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225948340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3225948340
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3097058731
Short name T351
Test name
Test status
Simulation time 291726430 ps
CPU time 0.93 seconds
Started Jul 07 06:06:54 PM PDT 24
Finished Jul 07 06:06:55 PM PDT 24
Peak memory 182976 kb
Host smart-ac91a1aa-61b0-4a42-9230-607139ba8d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097058731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3097058731
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1389710824
Short name T390
Test name
Test status
Simulation time 93179891443 ps
CPU time 131.46 seconds
Started Jul 07 06:06:56 PM PDT 24
Finished Jul 07 06:09:08 PM PDT 24
Peak memory 183156 kb
Host smart-f8e5c4d1-38f2-47f6-9e70-cf71bd92ae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389710824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1389710824
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3821133761
Short name T423
Test name
Test status
Simulation time 40429717664 ps
CPU time 54.31 seconds
Started Jul 07 06:06:57 PM PDT 24
Finished Jul 07 06:07:52 PM PDT 24
Peak memory 183120 kb
Host smart-d26f6f1f-c847-4147-8c10-73faeb4e205b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821133761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3821133761
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2122746792
Short name T83
Test name
Test status
Simulation time 48080258175 ps
CPU time 82.34 seconds
Started Jul 07 06:06:57 PM PDT 24
Finished Jul 07 06:08:20 PM PDT 24
Peak memory 191332 kb
Host smart-a0e08c2f-6b99-4c26-96a3-4bc64483552a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122746792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2122746792
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1631190231
Short name T87
Test name
Test status
Simulation time 387745172339 ps
CPU time 375.21 seconds
Started Jul 07 06:06:57 PM PDT 24
Finished Jul 07 06:13:12 PM PDT 24
Peak memory 191340 kb
Host smart-091d9f14-0751-4d77-9edb-2c5f5ed8abfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631190231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1631190231
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.2686772825
Short name T33
Test name
Test status
Simulation time 29567921307 ps
CPU time 226.43 seconds
Started Jul 07 06:07:04 PM PDT 24
Finished Jul 07 06:10:50 PM PDT 24
Peak memory 197844 kb
Host smart-d0bdf02a-390e-4fca-8ed1-7942bfd81ef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686772825 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.2686772825
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2907943260
Short name T46
Test name
Test status
Simulation time 738046584019 ps
CPU time 389.39 seconds
Started Jul 07 06:07:05 PM PDT 24
Finished Jul 07 06:13:35 PM PDT 24
Peak memory 183076 kb
Host smart-612e29d5-b2e4-4f8f-9deb-6fb477b3489b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907943260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2907943260
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.929380097
Short name T418
Test name
Test status
Simulation time 694380608453 ps
CPU time 108.09 seconds
Started Jul 07 06:06:57 PM PDT 24
Finished Jul 07 06:08:46 PM PDT 24
Peak memory 183136 kb
Host smart-47e88a20-b128-49ac-bf41-9940032d7c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929380097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.929380097
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2945265392
Short name T315
Test name
Test status
Simulation time 246165937878 ps
CPU time 158.17 seconds
Started Jul 07 06:07:00 PM PDT 24
Finished Jul 07 06:09:38 PM PDT 24
Peak memory 191288 kb
Host smart-87c502cf-3fa0-4dfc-93fa-96a13cf977a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945265392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2945265392
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2518951611
Short name T372
Test name
Test status
Simulation time 730265582 ps
CPU time 1.4 seconds
Started Jul 07 06:07:06 PM PDT 24
Finished Jul 07 06:07:08 PM PDT 24
Peak memory 182904 kb
Host smart-c375c602-dd5b-4dac-a8de-4f4fd19fe50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518951611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2518951611
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.180298278
Short name T290
Test name
Test status
Simulation time 1309647172305 ps
CPU time 519.9 seconds
Started Jul 07 06:07:03 PM PDT 24
Finished Jul 07 06:15:43 PM PDT 24
Peak memory 191340 kb
Host smart-220ea535-157c-4dac-80d6-3a463a5c59aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180298278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
180298278
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.4046296464
Short name T201
Test name
Test status
Simulation time 291624068560 ps
CPU time 242.56 seconds
Started Jul 07 06:07:02 PM PDT 24
Finished Jul 07 06:11:05 PM PDT 24
Peak memory 183128 kb
Host smart-996c8f59-e697-40dc-b5b6-582ddcd14f7b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046296464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.4046296464
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1706907571
Short name T369
Test name
Test status
Simulation time 12831342077 ps
CPU time 4.04 seconds
Started Jul 07 06:07:03 PM PDT 24
Finished Jul 07 06:07:07 PM PDT 24
Peak memory 183148 kb
Host smart-d820cecd-19c6-4e57-92b8-46f7a461da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706907571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1706907571
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.4173638312
Short name T115
Test name
Test status
Simulation time 120011550914 ps
CPU time 1409.09 seconds
Started Jul 07 06:07:04 PM PDT 24
Finished Jul 07 06:30:33 PM PDT 24
Peak memory 191316 kb
Host smart-eb6195e9-bf0e-4e17-92c4-df5cc9ff4ee0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173638312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.4173638312
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.459814026
Short name T325
Test name
Test status
Simulation time 268717260054 ps
CPU time 48.07 seconds
Started Jul 07 06:07:07 PM PDT 24
Finished Jul 07 06:07:55 PM PDT 24
Peak memory 195072 kb
Host smart-d9ee7326-b0f5-4bfa-a92e-8114ba877c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459814026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.459814026
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1232818066
Short name T52
Test name
Test status
Simulation time 17421957881 ps
CPU time 25.39 seconds
Started Jul 07 06:07:05 PM PDT 24
Finished Jul 07 06:07:31 PM PDT 24
Peak memory 194664 kb
Host smart-0f377d5a-1e3d-4638-bfbc-ae519e70fefe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232818066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1232818066
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3183790241
Short name T107
Test name
Test status
Simulation time 240441516271 ps
CPU time 120.2 seconds
Started Jul 07 06:07:08 PM PDT 24
Finished Jul 07 06:09:08 PM PDT 24
Peak memory 183124 kb
Host smart-60420055-4555-43b8-ba33-1c67dc39ab00
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183790241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3183790241
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3433864770
Short name T419
Test name
Test status
Simulation time 176456644751 ps
CPU time 234.33 seconds
Started Jul 07 06:07:04 PM PDT 24
Finished Jul 07 06:10:58 PM PDT 24
Peak memory 183108 kb
Host smart-e3e96a01-701e-4368-a102-089044751f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433864770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3433864770
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.363453529
Short name T55
Test name
Test status
Simulation time 65251001491 ps
CPU time 97.99 seconds
Started Jul 07 06:07:07 PM PDT 24
Finished Jul 07 06:08:45 PM PDT 24
Peak memory 191296 kb
Host smart-df8b260d-91f0-4cd7-af01-61612cfb5d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363453529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
363453529
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1637709631
Short name T12
Test name
Test status
Simulation time 52944782740 ps
CPU time 27.57 seconds
Started Jul 07 06:07:10 PM PDT 24
Finished Jul 07 06:07:38 PM PDT 24
Peak memory 183108 kb
Host smart-c458e81b-2648-445a-8e03-cb930b1f0283
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637709631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1637709631
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1881461947
Short name T361
Test name
Test status
Simulation time 30661345575 ps
CPU time 48.58 seconds
Started Jul 07 06:07:09 PM PDT 24
Finished Jul 07 06:07:57 PM PDT 24
Peak memory 183124 kb
Host smart-0bca1467-31aa-40f2-8619-71f604c57044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881461947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1881461947
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2619761395
Short name T233
Test name
Test status
Simulation time 165558782547 ps
CPU time 111.87 seconds
Started Jul 07 06:07:11 PM PDT 24
Finished Jul 07 06:09:03 PM PDT 24
Peak memory 183124 kb
Host smart-c497567b-70f0-4997-bed4-e9b1932dc7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619761395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2619761395
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.95236588
Short name T367
Test name
Test status
Simulation time 418451355870 ps
CPU time 639.3 seconds
Started Jul 07 06:07:14 PM PDT 24
Finished Jul 07 06:17:54 PM PDT 24
Peak memory 191320 kb
Host smart-634eb96d-f1ea-4a6a-a6c3-83156e368db8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95236588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.95236588
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.89521073
Short name T413
Test name
Test status
Simulation time 11892010031 ps
CPU time 14.23 seconds
Started Jul 07 06:07:14 PM PDT 24
Finished Jul 07 06:07:28 PM PDT 24
Peak memory 183160 kb
Host smart-3516e389-1d08-4d7f-baa0-e0c02c099aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89521073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.89521073
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.4087256117
Short name T130
Test name
Test status
Simulation time 148638017834 ps
CPU time 93.75 seconds
Started Jul 07 06:07:15 PM PDT 24
Finished Jul 07 06:08:49 PM PDT 24
Peak memory 183124 kb
Host smart-234cc3e0-b58e-4765-a72c-ff7fb61da142
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087256117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4087256117
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.368347978
Short name T409
Test name
Test status
Simulation time 64177451 ps
CPU time 0.61 seconds
Started Jul 07 06:07:13 PM PDT 24
Finished Jul 07 06:07:14 PM PDT 24
Peak memory 183012 kb
Host smart-c9c30f08-09ab-4d1e-872c-4c8caf93bb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368347978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.368347978
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.1441289870
Short name T28
Test name
Test status
Simulation time 71443461576 ps
CPU time 650.61 seconds
Started Jul 07 06:07:15 PM PDT 24
Finished Jul 07 06:18:06 PM PDT 24
Peak memory 198288 kb
Host smart-6f28ab7c-6e66-4bb7-8162-3d04e04791cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441289870 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.1441289870
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.82531348
Short name T214
Test name
Test status
Simulation time 344878103275 ps
CPU time 565.75 seconds
Started Jul 07 06:07:20 PM PDT 24
Finished Jul 07 06:16:46 PM PDT 24
Peak memory 183100 kb
Host smart-423f502e-ff59-423e-a7bd-2a9111ed9daa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82531348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.rv_timer_cfg_update_on_fly.82531348
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.582967601
Short name T357
Test name
Test status
Simulation time 52669042752 ps
CPU time 76.86 seconds
Started Jul 07 06:07:20 PM PDT 24
Finished Jul 07 06:08:37 PM PDT 24
Peak memory 183152 kb
Host smart-8748e3e4-a936-48c6-980d-15e9217509a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582967601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.582967601
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3280495779
Short name T245
Test name
Test status
Simulation time 428598030199 ps
CPU time 227.79 seconds
Started Jul 07 06:07:19 PM PDT 24
Finished Jul 07 06:11:07 PM PDT 24
Peak memory 191316 kb
Host smart-f3a48ba4-8ccf-4157-8c9f-17848b12a751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280495779 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3280495779
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.1333816166
Short name T436
Test name
Test status
Simulation time 26249948838 ps
CPU time 45.71 seconds
Started Jul 07 06:07:18 PM PDT 24
Finished Jul 07 06:08:04 PM PDT 24
Peak memory 183148 kb
Host smart-0c85b202-4569-4b3f-8268-8117c4c4f265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333816166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.1333816166
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.3006561499
Short name T13
Test name
Test status
Simulation time 22463173527 ps
CPU time 254.92 seconds
Started Jul 07 06:07:18 PM PDT 24
Finished Jul 07 06:11:33 PM PDT 24
Peak memory 197804 kb
Host smart-b5cf6089-1f6d-4b89-af1d-e3499d4fd71c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006561499 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.3006561499
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1916291226
Short name T133
Test name
Test status
Simulation time 1627251248407 ps
CPU time 1348.36 seconds
Started Jul 07 06:05:37 PM PDT 24
Finished Jul 07 06:28:06 PM PDT 24
Peak memory 183124 kb
Host smart-b57e9e62-8a7c-4df0-b654-b23c2049a8f1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916291226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1916291226
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3973474573
Short name T389
Test name
Test status
Simulation time 185322333726 ps
CPU time 253.82 seconds
Started Jul 07 06:05:39 PM PDT 24
Finished Jul 07 06:09:53 PM PDT 24
Peak memory 183140 kb
Host smart-5350b2f7-2ca7-4c33-8dda-f1633d1bea69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973474573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3973474573
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.103059335
Short name T168
Test name
Test status
Simulation time 24817471326 ps
CPU time 39.74 seconds
Started Jul 07 06:05:37 PM PDT 24
Finished Jul 07 06:06:17 PM PDT 24
Peak memory 183136 kb
Host smart-3f95f5f4-7285-4a1d-a20d-f28f1fd234d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103059335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.103059335
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1372927558
Short name T385
Test name
Test status
Simulation time 7724936441 ps
CPU time 13.88 seconds
Started Jul 07 06:05:40 PM PDT 24
Finished Jul 07 06:05:54 PM PDT 24
Peak memory 191296 kb
Host smart-a7202c5c-51b8-4da2-87ae-1c9c9803ab9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372927558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1372927558
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1251451989
Short name T17
Test name
Test status
Simulation time 74514864 ps
CPU time 0.74 seconds
Started Jul 07 06:05:38 PM PDT 24
Finished Jul 07 06:05:39 PM PDT 24
Peak memory 213320 kb
Host smart-7da9d8b2-f8ba-44a7-8d73-d5ebb1932659
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251451989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1251451989
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.384412531
Short name T44
Test name
Test status
Simulation time 739732159164 ps
CPU time 207.64 seconds
Started Jul 07 06:07:23 PM PDT 24
Finished Jul 07 06:10:51 PM PDT 24
Peak memory 183124 kb
Host smart-a5eaa68e-29e6-4b1c-a469-cd360a6b9258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384412531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.384412531
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1886424774
Short name T167
Test name
Test status
Simulation time 380344209407 ps
CPU time 774.82 seconds
Started Jul 07 06:07:24 PM PDT 24
Finished Jul 07 06:20:19 PM PDT 24
Peak memory 191320 kb
Host smart-05fa7b74-4d02-49df-8c4e-bcd70f2939ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886424774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1886424774
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2225988730
Short name T126
Test name
Test status
Simulation time 111844641581 ps
CPU time 91.66 seconds
Started Jul 07 06:07:26 PM PDT 24
Finished Jul 07 06:08:58 PM PDT 24
Peak memory 191328 kb
Host smart-0302959e-2b72-4ada-820f-e7022afa3f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225988730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2225988730
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3532524429
Short name T268
Test name
Test status
Simulation time 1290912732121 ps
CPU time 663.53 seconds
Started Jul 07 06:07:24 PM PDT 24
Finished Jul 07 06:18:28 PM PDT 24
Peak memory 183112 kb
Host smart-821f4b33-21e9-41c8-b0f3-dba6a86a1ec8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532524429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3532524429
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.387567583
Short name T48
Test name
Test status
Simulation time 121172994699 ps
CPU time 104.69 seconds
Started Jul 07 06:07:22 PM PDT 24
Finished Jul 07 06:09:07 PM PDT 24
Peak memory 183160 kb
Host smart-213cd97d-b01c-400c-8d2e-ae3aad1b6a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387567583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.387567583
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2683553391
Short name T117
Test name
Test status
Simulation time 44673669067 ps
CPU time 69.47 seconds
Started Jul 07 06:07:27 PM PDT 24
Finished Jul 07 06:08:37 PM PDT 24
Peak memory 194952 kb
Host smart-80fc917d-0047-4315-9046-d4c6c1bb7f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683553391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2683553391
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2532972103
Short name T4
Test name
Test status
Simulation time 3500035296 ps
CPU time 3.55 seconds
Started Jul 07 06:07:28 PM PDT 24
Finished Jul 07 06:07:32 PM PDT 24
Peak memory 183128 kb
Host smart-fb061237-f10a-4dda-a941-4e8aa5eb92f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532972103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2532972103
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.202165122
Short name T35
Test name
Test status
Simulation time 45025926932 ps
CPU time 329.64 seconds
Started Jul 07 06:07:26 PM PDT 24
Finished Jul 07 06:12:56 PM PDT 24
Peak memory 206008 kb
Host smart-9b76014e-308e-4970-9bea-e099b50d04b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202165122 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.202165122
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1260475381
Short name T314
Test name
Test status
Simulation time 18265037694 ps
CPU time 31.78 seconds
Started Jul 07 06:07:29 PM PDT 24
Finished Jul 07 06:08:02 PM PDT 24
Peak memory 183080 kb
Host smart-c884496d-19aa-445e-91c7-60762fbfa3dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260475381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1260475381
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1893876669
Short name T362
Test name
Test status
Simulation time 130993390306 ps
CPU time 153.58 seconds
Started Jul 07 06:07:26 PM PDT 24
Finished Jul 07 06:10:00 PM PDT 24
Peak memory 183112 kb
Host smart-d73c6faa-7f6f-4dca-ad54-bcb6937f13b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893876669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1893876669
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3238945936
Short name T344
Test name
Test status
Simulation time 25963852634 ps
CPU time 251.54 seconds
Started Jul 07 06:07:30 PM PDT 24
Finished Jul 07 06:11:42 PM PDT 24
Peak memory 191352 kb
Host smart-86be9565-dfee-40b1-a8a6-cbf9201175ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238945936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3238945936
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3789959471
Short name T380
Test name
Test status
Simulation time 40189417885 ps
CPU time 62.47 seconds
Started Jul 07 06:07:32 PM PDT 24
Finished Jul 07 06:08:35 PM PDT 24
Peak memory 183144 kb
Host smart-7e1ac882-7a69-4c25-bf4a-75700bbd05a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789959471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3789959471
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.799707286
Short name T428
Test name
Test status
Simulation time 16140363540 ps
CPU time 167.39 seconds
Started Jul 07 06:07:29 PM PDT 24
Finished Jul 07 06:10:17 PM PDT 24
Peak memory 197824 kb
Host smart-239156c8-a359-4755-a053-826d024d648e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799707286 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.799707286
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3400948418
Short name T182
Test name
Test status
Simulation time 171833809241 ps
CPU time 286.03 seconds
Started Jul 07 06:07:30 PM PDT 24
Finished Jul 07 06:12:16 PM PDT 24
Peak memory 183140 kb
Host smart-fb260bab-c1f7-43e2-9704-cccbe3ce9c18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400948418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3400948418
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2117113563
Short name T359
Test name
Test status
Simulation time 92870010592 ps
CPU time 130.67 seconds
Started Jul 07 06:07:32 PM PDT 24
Finished Jul 07 06:09:43 PM PDT 24
Peak memory 183140 kb
Host smart-27f030ad-65a2-48d0-9bba-74c9aad434bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117113563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2117113563
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1438320651
Short name T277
Test name
Test status
Simulation time 44430390262 ps
CPU time 120.38 seconds
Started Jul 07 06:07:30 PM PDT 24
Finished Jul 07 06:09:31 PM PDT 24
Peak memory 191324 kb
Host smart-e60c09a7-c4fc-4b17-a283-1974ca506c59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438320651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1438320651
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.2938858275
Short name T332
Test name
Test status
Simulation time 49156150410 ps
CPU time 84 seconds
Started Jul 07 06:07:30 PM PDT 24
Finished Jul 07 06:08:54 PM PDT 24
Peak memory 183020 kb
Host smart-144ed5b7-27c7-4615-aee8-cf6b98d84ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938858275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.2938858275
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.4223869133
Short name T448
Test name
Test status
Simulation time 391653483643 ps
CPU time 169.51 seconds
Started Jul 07 06:07:35 PM PDT 24
Finished Jul 07 06:10:25 PM PDT 24
Peak memory 183112 kb
Host smart-b8d60081-2301-4bbe-b9f7-3bc7d0f40ea9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223869133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.4223869133
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.4073575293
Short name T3
Test name
Test status
Simulation time 11340209986 ps
CPU time 15.7 seconds
Started Jul 07 06:07:32 PM PDT 24
Finished Jul 07 06:07:48 PM PDT 24
Peak memory 183156 kb
Host smart-315c10b0-df3c-49f7-a099-a6ce803a8efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073575293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.4073575293
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.663985358
Short name T424
Test name
Test status
Simulation time 48944986556 ps
CPU time 76.16 seconds
Started Jul 07 06:07:36 PM PDT 24
Finished Jul 07 06:08:53 PM PDT 24
Peak memory 183152 kb
Host smart-50aaa447-fdd9-4e01-9437-4f74f9dfd854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663985358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.663985358
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1511728918
Short name T294
Test name
Test status
Simulation time 797954080047 ps
CPU time 491.12 seconds
Started Jul 07 06:07:38 PM PDT 24
Finished Jul 07 06:15:49 PM PDT 24
Peak memory 183120 kb
Host smart-40f00d72-bbfb-4b73-a974-ade9a9baa45d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511728918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1511728918
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3530882413
Short name T381
Test name
Test status
Simulation time 524451665614 ps
CPU time 252 seconds
Started Jul 07 06:07:36 PM PDT 24
Finished Jul 07 06:11:48 PM PDT 24
Peak memory 183152 kb
Host smart-35027518-30a6-4f57-bef4-ccb9427f93c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530882413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3530882413
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1482617914
Short name T204
Test name
Test status
Simulation time 139983106564 ps
CPU time 59.75 seconds
Started Jul 07 06:07:34 PM PDT 24
Finished Jul 07 06:08:34 PM PDT 24
Peak memory 183080 kb
Host smart-f0a1528a-8e79-41f7-9824-b267e7e52f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482617914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1482617914
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.3431688195
Short name T370
Test name
Test status
Simulation time 25110955 ps
CPU time 0.58 seconds
Started Jul 07 06:07:39 PM PDT 24
Finished Jul 07 06:07:40 PM PDT 24
Peak memory 182896 kb
Host smart-c18dbf54-8c65-44fc-98b1-03567e7af3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431688195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.3431688195
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3992027659
Short name T11
Test name
Test status
Simulation time 134166798721 ps
CPU time 73.63 seconds
Started Jul 07 06:07:44 PM PDT 24
Finished Jul 07 06:08:58 PM PDT 24
Peak memory 183072 kb
Host smart-e2b137f7-7d2b-4e5e-a174-e25fb352d119
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992027659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3992027659
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3484040631
Short name T408
Test name
Test status
Simulation time 514933298283 ps
CPU time 215.41 seconds
Started Jul 07 06:07:42 PM PDT 24
Finished Jul 07 06:11:18 PM PDT 24
Peak memory 183032 kb
Host smart-275ee954-f5c3-475f-8189-f7263fa1528c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484040631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3484040631
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3215167187
Short name T300
Test name
Test status
Simulation time 51621129311 ps
CPU time 127.16 seconds
Started Jul 07 06:07:43 PM PDT 24
Finished Jul 07 06:09:51 PM PDT 24
Peak memory 191276 kb
Host smart-948a6229-81a9-4800-984c-222fda308633
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215167187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3215167187
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3198574520
Short name T382
Test name
Test status
Simulation time 408801266172 ps
CPU time 1334.2 seconds
Started Jul 07 06:07:49 PM PDT 24
Finished Jul 07 06:30:04 PM PDT 24
Peak memory 183140 kb
Host smart-954e1c75-14f3-40e4-b432-60d895ff53aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198574520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3198574520
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.2198302858
Short name T34
Test name
Test status
Simulation time 97410367306 ps
CPU time 692.02 seconds
Started Jul 07 06:07:44 PM PDT 24
Finished Jul 07 06:19:16 PM PDT 24
Peak memory 206056 kb
Host smart-3270b228-a727-4c8d-84e7-444533c9f647
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198302858 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.2198302858
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1843163587
Short name T148
Test name
Test status
Simulation time 578485335479 ps
CPU time 844.35 seconds
Started Jul 07 06:07:45 PM PDT 24
Finished Jul 07 06:21:50 PM PDT 24
Peak memory 183096 kb
Host smart-dbea82b2-c296-4ef8-8988-4e6df0aa1c5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843163587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1843163587
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.2697647141
Short name T429
Test name
Test status
Simulation time 49069692792 ps
CPU time 66.84 seconds
Started Jul 07 06:07:46 PM PDT 24
Finished Jul 07 06:08:53 PM PDT 24
Peak memory 183168 kb
Host smart-02dd254d-0a99-4d07-a925-41987d9b93c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697647141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.2697647141
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1045731176
Short name T215
Test name
Test status
Simulation time 104395793034 ps
CPU time 188.66 seconds
Started Jul 07 06:07:45 PM PDT 24
Finished Jul 07 06:10:54 PM PDT 24
Peak memory 190820 kb
Host smart-a66f6de5-4b34-4abb-ac1b-7fbe428179d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045731176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1045731176
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1425613228
Short name T330
Test name
Test status
Simulation time 43196450414 ps
CPU time 50.36 seconds
Started Jul 07 06:07:45 PM PDT 24
Finished Jul 07 06:08:35 PM PDT 24
Peak memory 182628 kb
Host smart-617007a9-5c28-4013-8679-21092f2956c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425613228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1425613228
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2100642186
Short name T438
Test name
Test status
Simulation time 145060853262 ps
CPU time 200.38 seconds
Started Jul 07 06:07:50 PM PDT 24
Finished Jul 07 06:11:11 PM PDT 24
Peak memory 191324 kb
Host smart-cb7cd285-f71a-40eb-9ec7-f221fb53e0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100642186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2100642186
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3512166697
Short name T19
Test name
Test status
Simulation time 115454734536 ps
CPU time 99.48 seconds
Started Jul 07 06:07:49 PM PDT 24
Finished Jul 07 06:09:29 PM PDT 24
Peak memory 183120 kb
Host smart-bc7fc0ed-3cb3-421f-ac8d-7449c72ad69c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512166697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3512166697
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2254424778
Short name T399
Test name
Test status
Simulation time 249656836625 ps
CPU time 109.64 seconds
Started Jul 07 06:07:51 PM PDT 24
Finished Jul 07 06:09:41 PM PDT 24
Peak memory 183100 kb
Host smart-82cf6216-012c-4462-8c4a-5f2cc1b24fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254424778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2254424778
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1872717885
Short name T272
Test name
Test status
Simulation time 34624282913 ps
CPU time 23.43 seconds
Started Jul 07 06:07:49 PM PDT 24
Finished Jul 07 06:08:13 PM PDT 24
Peak memory 183128 kb
Host smart-6202a6f9-cbf5-495f-a155-3096fa938525
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872717885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1872717885
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1800664768
Short name T433
Test name
Test status
Simulation time 276172913989 ps
CPU time 193.24 seconds
Started Jul 07 06:07:48 PM PDT 24
Finished Jul 07 06:11:01 PM PDT 24
Peak memory 191348 kb
Host smart-adcc579a-76c9-4ff4-98d3-dd79a3639432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800664768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1800664768
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.2284732589
Short name T6
Test name
Test status
Simulation time 609162606063 ps
CPU time 269.74 seconds
Started Jul 07 06:07:50 PM PDT 24
Finished Jul 07 06:12:20 PM PDT 24
Peak memory 183128 kb
Host smart-ddf06094-e1cb-43ac-9600-3cb66eec755e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284732589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.2284732589
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1133690333
Short name T366
Test name
Test status
Simulation time 188605808419 ps
CPU time 85.61 seconds
Started Jul 07 06:07:48 PM PDT 24
Finished Jul 07 06:09:14 PM PDT 24
Peak memory 183148 kb
Host smart-4bde41d4-4c55-4b54-8e58-d17ec0bcdce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133690333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1133690333
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.4157846785
Short name T106
Test name
Test status
Simulation time 176083389015 ps
CPU time 273.61 seconds
Started Jul 07 06:07:51 PM PDT 24
Finished Jul 07 06:12:25 PM PDT 24
Peak memory 191324 kb
Host smart-f050c384-506b-431c-b804-38446200d70d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157846785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4157846785
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.278549667
Short name T140
Test name
Test status
Simulation time 28211895777 ps
CPU time 41.27 seconds
Started Jul 07 06:07:49 PM PDT 24
Finished Jul 07 06:08:30 PM PDT 24
Peak memory 183096 kb
Host smart-f95596e8-ff98-4cf5-94fa-d5d85e53ff26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278549667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.278549667
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2939495488
Short name T198
Test name
Test status
Simulation time 67087371938 ps
CPU time 55.88 seconds
Started Jul 07 06:05:45 PM PDT 24
Finished Jul 07 06:06:41 PM PDT 24
Peak memory 183112 kb
Host smart-b4bc4217-7165-44a8-9cd2-0db3066facae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939495488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2939495488
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2552893639
Short name T386
Test name
Test status
Simulation time 31709130272 ps
CPU time 41.25 seconds
Started Jul 07 06:05:44 PM PDT 24
Finished Jul 07 06:06:26 PM PDT 24
Peak memory 183136 kb
Host smart-ff525fc3-f69c-4c70-9b32-4f86d3efd3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552893639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2552893639
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2001689218
Short name T431
Test name
Test status
Simulation time 70973782248 ps
CPU time 141.03 seconds
Started Jul 07 06:05:42 PM PDT 24
Finished Jul 07 06:08:04 PM PDT 24
Peak memory 183124 kb
Host smart-a8afbbe6-5565-4148-ab70-813fe5d10360
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001689218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2001689218
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3745896218
Short name T400
Test name
Test status
Simulation time 2136496625 ps
CPU time 3.12 seconds
Started Jul 07 06:05:45 PM PDT 24
Finished Jul 07 06:05:49 PM PDT 24
Peak memory 182972 kb
Host smart-4877c862-ddc9-41a7-ad08-dad22dd912b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745896218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3745896218
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2405343766
Short name T15
Test name
Test status
Simulation time 101141116 ps
CPU time 0.87 seconds
Started Jul 07 06:05:42 PM PDT 24
Finished Jul 07 06:05:43 PM PDT 24
Peak memory 214484 kb
Host smart-d286789c-2546-471d-b7e7-004e8ed438a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405343766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2405343766
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.2630976351
Short name T392
Test name
Test status
Simulation time 345531577206 ps
CPU time 115.6 seconds
Started Jul 07 06:05:46 PM PDT 24
Finished Jul 07 06:07:41 PM PDT 24
Peak memory 183012 kb
Host smart-9a10eb6e-d481-4873-a27a-d52c8538571e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630976351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
2630976351
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2091652467
Short name T337
Test name
Test status
Simulation time 187137484351 ps
CPU time 166.1 seconds
Started Jul 07 06:07:54 PM PDT 24
Finished Jul 07 06:10:40 PM PDT 24
Peak memory 183156 kb
Host smart-06041745-cfeb-46e0-9d54-a7469c9548e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091652467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2091652467
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1232743021
Short name T406
Test name
Test status
Simulation time 97863246069 ps
CPU time 136.65 seconds
Started Jul 07 06:07:49 PM PDT 24
Finished Jul 07 06:10:06 PM PDT 24
Peak memory 183152 kb
Host smart-f122e817-ff68-430a-a4fe-ff402bc83bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232743021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1232743021
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3412598938
Short name T100
Test name
Test status
Simulation time 21832207639 ps
CPU time 17.59 seconds
Started Jul 07 06:07:51 PM PDT 24
Finished Jul 07 06:08:09 PM PDT 24
Peak memory 183044 kb
Host smart-f525a47a-7927-4957-bf87-655d1fd1dc22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412598938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3412598938
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1127682164
Short name T355
Test name
Test status
Simulation time 1081281162 ps
CPU time 2.08 seconds
Started Jul 07 06:07:50 PM PDT 24
Finished Jul 07 06:07:52 PM PDT 24
Peak memory 194184 kb
Host smart-1c774f5c-e6a3-4f2a-a726-504d1d25ce7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127682164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1127682164
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.4055385144
Short name T441
Test name
Test status
Simulation time 1389976624905 ps
CPU time 988.77 seconds
Started Jul 07 06:07:49 PM PDT 24
Finished Jul 07 06:24:18 PM PDT 24
Peak memory 191316 kb
Host smart-04eae082-ac4d-411e-9516-5a9c6895ddc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055385144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.4055385144
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1358662700
Short name T416
Test name
Test status
Simulation time 93871811944 ps
CPU time 136.75 seconds
Started Jul 07 06:07:50 PM PDT 24
Finished Jul 07 06:10:07 PM PDT 24
Peak memory 183148 kb
Host smart-db86723f-b1ed-4197-a559-fc016b8a7e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358662700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1358662700
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3211431570
Short name T312
Test name
Test status
Simulation time 142705184490 ps
CPU time 144.6 seconds
Started Jul 07 06:07:52 PM PDT 24
Finished Jul 07 06:10:16 PM PDT 24
Peak memory 191316 kb
Host smart-4587afb8-90e4-4c59-a8c1-677279166f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211431570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3211431570
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.833564608
Short name T311
Test name
Test status
Simulation time 192736550700 ps
CPU time 516.89 seconds
Started Jul 07 06:07:52 PM PDT 24
Finished Jul 07 06:16:29 PM PDT 24
Peak memory 191352 kb
Host smart-dbc6676c-415e-4cd4-bb78-720d8b016279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833564608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.833564608
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2242306905
Short name T156
Test name
Test status
Simulation time 620780779419 ps
CPU time 246.19 seconds
Started Jul 07 06:07:52 PM PDT 24
Finished Jul 07 06:11:58 PM PDT 24
Peak memory 191344 kb
Host smart-97e308e6-014f-4450-93c0-1120f95df7b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242306905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2242306905
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2607618892
Short name T122
Test name
Test status
Simulation time 541188881993 ps
CPU time 282.34 seconds
Started Jul 07 06:07:56 PM PDT 24
Finished Jul 07 06:12:38 PM PDT 24
Peak memory 183116 kb
Host smart-7098a4ba-ab36-4672-91c0-d6fe7c3359fd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607618892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2607618892
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2441114406
Short name T89
Test name
Test status
Simulation time 509585449210 ps
CPU time 193.49 seconds
Started Jul 07 06:07:58 PM PDT 24
Finished Jul 07 06:11:12 PM PDT 24
Peak memory 183012 kb
Host smart-5c900748-8686-4741-9205-cad772973a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441114406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2441114406
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.601883599
Short name T384
Test name
Test status
Simulation time 63863323871 ps
CPU time 210.3 seconds
Started Jul 07 06:08:02 PM PDT 24
Finished Jul 07 06:11:33 PM PDT 24
Peak memory 191348 kb
Host smart-9b5674d7-b3c8-433a-8681-623385630aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601883599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.601883599
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2695056877
Short name T387
Test name
Test status
Simulation time 1947965839127 ps
CPU time 727.22 seconds
Started Jul 07 06:07:59 PM PDT 24
Finished Jul 07 06:20:06 PM PDT 24
Peak memory 195708 kb
Host smart-f7bd1fa6-fe1c-46cd-898c-2f2c50635e21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695056877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2695056877
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.4169804367
Short name T183
Test name
Test status
Simulation time 274276292658 ps
CPU time 391.39 seconds
Started Jul 07 06:08:05 PM PDT 24
Finished Jul 07 06:14:37 PM PDT 24
Peak memory 183080 kb
Host smart-b176258d-22b1-4047-9820-f722d764645f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169804367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.4169804367
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.3358078476
Short name T263
Test name
Test status
Simulation time 47490250042 ps
CPU time 188.91 seconds
Started Jul 07 06:08:00 PM PDT 24
Finished Jul 07 06:11:10 PM PDT 24
Peak memory 191276 kb
Host smart-cbd821ed-34b2-4afc-b687-e212195683a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358078476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3358078476
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3765652728
Short name T279
Test name
Test status
Simulation time 229736531223 ps
CPU time 550.84 seconds
Started Jul 07 06:08:02 PM PDT 24
Finished Jul 07 06:17:13 PM PDT 24
Peak memory 191356 kb
Host smart-b68bf895-aa2b-43b9-9f55-b1e675b47f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765652728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3765652728
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1603345111
Short name T316
Test name
Test status
Simulation time 532879832842 ps
CPU time 926.43 seconds
Started Jul 07 06:08:06 PM PDT 24
Finished Jul 07 06:23:33 PM PDT 24
Peak memory 183120 kb
Host smart-9a20093b-d53f-4208-91ab-cdca4a3ce213
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603345111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1603345111
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2186399573
Short name T368
Test name
Test status
Simulation time 376839450200 ps
CPU time 148.81 seconds
Started Jul 07 06:08:06 PM PDT 24
Finished Jul 07 06:10:35 PM PDT 24
Peak memory 183136 kb
Host smart-061e2fca-2226-4e76-9aa7-b36b0d47acf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186399573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2186399573
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.784427788
Short name T287
Test name
Test status
Simulation time 583862010182 ps
CPU time 98.21 seconds
Started Jul 07 06:08:02 PM PDT 24
Finished Jul 07 06:09:40 PM PDT 24
Peak memory 191596 kb
Host smart-e7176ca9-1ee4-4ba5-a183-eff01640fb62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784427788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.784427788
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.2011399941
Short name T339
Test name
Test status
Simulation time 26197824003 ps
CPU time 41.36 seconds
Started Jul 07 06:08:06 PM PDT 24
Finished Jul 07 06:08:47 PM PDT 24
Peak memory 183416 kb
Host smart-5a099668-1b0b-4045-ad52-ebdf37c934ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011399941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.2011399941
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.450473677
Short name T177
Test name
Test status
Simulation time 847732639664 ps
CPU time 1343.79 seconds
Started Jul 07 06:08:10 PM PDT 24
Finished Jul 07 06:30:34 PM PDT 24
Peak memory 191364 kb
Host smart-6496379a-9b84-4c34-aa6c-e2314485339b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450473677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
450473677
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.507977826
Short name T30
Test name
Test status
Simulation time 208700847987 ps
CPU time 310.59 seconds
Started Jul 07 06:08:09 PM PDT 24
Finished Jul 07 06:13:20 PM PDT 24
Peak memory 197836 kb
Host smart-46727343-663a-4246-a3a5-d1d842c539f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507977826 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.507977826
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3633274455
Short name T395
Test name
Test status
Simulation time 56039336573 ps
CPU time 77.76 seconds
Started Jul 07 06:08:08 PM PDT 24
Finished Jul 07 06:09:26 PM PDT 24
Peak memory 183140 kb
Host smart-fe1ae569-5784-4f6b-a300-bf4ce8ed771f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633274455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3633274455
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3997985169
Short name T363
Test name
Test status
Simulation time 71009788649 ps
CPU time 80.68 seconds
Started Jul 07 06:08:05 PM PDT 24
Finished Jul 07 06:09:26 PM PDT 24
Peak memory 183088 kb
Host smart-93b9075d-e7d3-4d4a-98f4-a2a9218e4c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997985169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3997985169
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2506279276
Short name T141
Test name
Test status
Simulation time 22702793286 ps
CPU time 10.95 seconds
Started Jul 07 06:08:06 PM PDT 24
Finished Jul 07 06:08:17 PM PDT 24
Peak memory 183148 kb
Host smart-30df100d-5bb7-40f1-936b-a6cf56667f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506279276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2506279276
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.848669088
Short name T145
Test name
Test status
Simulation time 62778201886 ps
CPU time 29.31 seconds
Started Jul 07 06:08:15 PM PDT 24
Finished Jul 07 06:08:45 PM PDT 24
Peak memory 191344 kb
Host smart-0c8cb263-59ae-457d-bbf6-224c19081930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848669088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.848669088
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3245658490
Short name T278
Test name
Test status
Simulation time 1563976875083 ps
CPU time 507.16 seconds
Started Jul 07 06:08:14 PM PDT 24
Finished Jul 07 06:16:42 PM PDT 24
Peak memory 191328 kb
Host smart-058e025d-4e7d-4bbb-a70f-8f84f0569fcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245658490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3245658490
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.608097929
Short name T29
Test name
Test status
Simulation time 54180815765 ps
CPU time 743.83 seconds
Started Jul 07 06:08:09 PM PDT 24
Finished Jul 07 06:20:33 PM PDT 24
Peak memory 206020 kb
Host smart-84bb0381-c863-4f00-850a-8fec0c9621f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608097929 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.608097929
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.4019536358
Short name T343
Test name
Test status
Simulation time 126660782174 ps
CPU time 212.67 seconds
Started Jul 07 06:08:11 PM PDT 24
Finished Jul 07 06:11:44 PM PDT 24
Peak memory 183128 kb
Host smart-f7e60039-f284-4cde-b93c-9de79ef3fb86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019536358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.4019536358
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1019701464
Short name T403
Test name
Test status
Simulation time 48205399248 ps
CPU time 75.75 seconds
Started Jul 07 06:08:15 PM PDT 24
Finished Jul 07 06:09:31 PM PDT 24
Peak memory 183148 kb
Host smart-440d0242-92c3-41f2-b090-c222ededc993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019701464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1019701464
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1069326192
Short name T331
Test name
Test status
Simulation time 444494638223 ps
CPU time 225.94 seconds
Started Jul 07 06:08:14 PM PDT 24
Finished Jul 07 06:12:00 PM PDT 24
Peak memory 191332 kb
Host smart-e27a9f72-df1b-44ee-a49b-5dcd782ec487
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069326192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1069326192
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.48776421
Short name T422
Test name
Test status
Simulation time 245057041585 ps
CPU time 666.47 seconds
Started Jul 07 06:08:12 PM PDT 24
Finished Jul 07 06:19:19 PM PDT 24
Peak memory 191320 kb
Host smart-f79e166b-9e5a-43fa-98a4-559f91050e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48776421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.48776421
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1983343404
Short name T54
Test name
Test status
Simulation time 115637587760 ps
CPU time 518.08 seconds
Started Jul 07 06:08:12 PM PDT 24
Finished Jul 07 06:16:51 PM PDT 24
Peak memory 195112 kb
Host smart-72251cb3-ae9d-4d8a-aef7-300cc06adb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983343404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1983343404
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1038190821
Short name T317
Test name
Test status
Simulation time 1067839608667 ps
CPU time 1055.37 seconds
Started Jul 07 06:08:19 PM PDT 24
Finished Jul 07 06:25:54 PM PDT 24
Peak memory 183080 kb
Host smart-7768c283-2d54-4db0-a607-d52be2b4bd47
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038190821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1038190821
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.861399785
Short name T373
Test name
Test status
Simulation time 36922672993 ps
CPU time 26.32 seconds
Started Jul 07 06:08:13 PM PDT 24
Finished Jul 07 06:08:39 PM PDT 24
Peak memory 183140 kb
Host smart-3f301087-0151-4b5e-a92f-532127edf630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861399785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.861399785
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2587207061
Short name T203
Test name
Test status
Simulation time 269644285181 ps
CPU time 83.15 seconds
Started Jul 07 06:08:16 PM PDT 24
Finished Jul 07 06:09:39 PM PDT 24
Peak memory 191340 kb
Host smart-b57c13b2-bd25-4c97-bace-7c0e57afa5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587207061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2587207061
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1947884021
Short name T371
Test name
Test status
Simulation time 403767432676 ps
CPU time 119.07 seconds
Started Jul 07 06:08:19 PM PDT 24
Finished Jul 07 06:10:18 PM PDT 24
Peak memory 183024 kb
Host smart-425d80ea-d1b6-4c9e-94ca-c7a2a38b1204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947884021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1947884021
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2437761292
Short name T151
Test name
Test status
Simulation time 44049059811 ps
CPU time 88.79 seconds
Started Jul 07 06:08:16 PM PDT 24
Finished Jul 07 06:09:45 PM PDT 24
Peak memory 191332 kb
Host smart-23c3af79-a268-4194-8815-700645bdda4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437761292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2437761292
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3657417097
Short name T446
Test name
Test status
Simulation time 14740892 ps
CPU time 0.54 seconds
Started Jul 07 06:08:16 PM PDT 24
Finished Jul 07 06:08:17 PM PDT 24
Peak memory 182964 kb
Host smart-698c68d9-e575-46d0-8bc2-cb1ba368b6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657417097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3657417097
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2978219159
Short name T329
Test name
Test status
Simulation time 6216190489 ps
CPU time 10.1 seconds
Started Jul 07 06:08:23 PM PDT 24
Finished Jul 07 06:08:33 PM PDT 24
Peak memory 183120 kb
Host smart-8bf9eb4d-81ac-4484-9798-f2979f975540
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978219159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2978219159
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3835382677
Short name T379
Test name
Test status
Simulation time 423742361116 ps
CPU time 94.48 seconds
Started Jul 07 06:08:19 PM PDT 24
Finished Jul 07 06:09:54 PM PDT 24
Peak memory 183168 kb
Host smart-0d235e70-142e-4b7c-808b-16d9668ba95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835382677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3835382677
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3400160516
Short name T293
Test name
Test status
Simulation time 133906795980 ps
CPU time 196.71 seconds
Started Jul 07 06:08:19 PM PDT 24
Finished Jul 07 06:11:36 PM PDT 24
Peak memory 191336 kb
Host smart-69330ff9-444e-43b6-88dd-f613bde4a186
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400160516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3400160516
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.661980002
Short name T354
Test name
Test status
Simulation time 18864569884 ps
CPU time 30.13 seconds
Started Jul 07 06:08:21 PM PDT 24
Finished Jul 07 06:08:51 PM PDT 24
Peak memory 191328 kb
Host smart-f8ebbd98-8602-4333-9b72-2395d29d3df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661980002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.661980002
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.4196022287
Short name T414
Test name
Test status
Simulation time 27931279232 ps
CPU time 38.33 seconds
Started Jul 07 06:08:21 PM PDT 24
Finished Jul 07 06:08:59 PM PDT 24
Peak memory 183168 kb
Host smart-a542aa81-2bc1-48d8-a024-e092b431ac58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196022287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.4196022287
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4026041096
Short name T82
Test name
Test status
Simulation time 292719018760 ps
CPU time 464.39 seconds
Started Jul 07 06:05:49 PM PDT 24
Finished Jul 07 06:13:33 PM PDT 24
Peak memory 183136 kb
Host smart-c2d95bf3-198b-4303-a493-77fe84183e38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026041096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.4026041096
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.631433916
Short name T412
Test name
Test status
Simulation time 56951072546 ps
CPU time 89.05 seconds
Started Jul 07 06:05:48 PM PDT 24
Finished Jul 07 06:07:18 PM PDT 24
Peak memory 183124 kb
Host smart-f769a444-d239-4944-b800-40f9987d8e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631433916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.631433916
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1597359281
Short name T326
Test name
Test status
Simulation time 1419294433383 ps
CPU time 647.73 seconds
Started Jul 07 06:05:49 PM PDT 24
Finished Jul 07 06:16:37 PM PDT 24
Peak memory 191372 kb
Host smart-4dca1aa0-ea83-4619-a1b7-5141f38f74b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597359281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1597359281
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3358258384
Short name T374
Test name
Test status
Simulation time 4902647108 ps
CPU time 7.39 seconds
Started Jul 07 06:05:51 PM PDT 24
Finished Jul 07 06:05:59 PM PDT 24
Peak memory 182968 kb
Host smart-a22cdc43-f832-4e5e-ada7-f20b1b8d5916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358258384 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3358258384
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.508560968
Short name T410
Test name
Test status
Simulation time 67553532443 ps
CPU time 307.8 seconds
Started Jul 07 06:05:52 PM PDT 24
Finished Jul 07 06:11:01 PM PDT 24
Peak memory 206036 kb
Host smart-8842a08e-faca-42e7-a169-965f04ea6c59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508560968 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.508560968
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.3859074298
Short name T227
Test name
Test status
Simulation time 92217477632 ps
CPU time 255.3 seconds
Started Jul 07 06:08:22 PM PDT 24
Finished Jul 07 06:12:38 PM PDT 24
Peak memory 191232 kb
Host smart-9154031a-7a8e-44f0-8909-31058c7dc765
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859074298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3859074298
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.917481755
Short name T211
Test name
Test status
Simulation time 602548200924 ps
CPU time 546.68 seconds
Started Jul 07 06:08:27 PM PDT 24
Finished Jul 07 06:17:34 PM PDT 24
Peak memory 191324 kb
Host smart-0a9bece9-8a59-4162-a48a-d4044298f293
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917481755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.917481755
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3424342279
Short name T224
Test name
Test status
Simulation time 144788089162 ps
CPU time 383.33 seconds
Started Jul 07 06:08:23 PM PDT 24
Finished Jul 07 06:14:47 PM PDT 24
Peak memory 191312 kb
Host smart-69315647-395c-4a26-bc5b-5f2e28ede2bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424342279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3424342279
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.4075549605
Short name T394
Test name
Test status
Simulation time 279261329124 ps
CPU time 72.24 seconds
Started Jul 07 06:08:26 PM PDT 24
Finished Jul 07 06:09:39 PM PDT 24
Peak memory 183136 kb
Host smart-2b3361c3-8f52-4467-8b86-fb013e119848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075549605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.4075549605
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1292562719
Short name T188
Test name
Test status
Simulation time 6744032666 ps
CPU time 6.43 seconds
Started Jul 07 06:08:23 PM PDT 24
Finished Jul 07 06:08:29 PM PDT 24
Peak memory 193488 kb
Host smart-3d645494-8b2c-4fcd-93ed-a612552193e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292562719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1292562719
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2477143784
Short name T236
Test name
Test status
Simulation time 29181548315 ps
CPU time 46.52 seconds
Started Jul 07 06:08:24 PM PDT 24
Finished Jul 07 06:09:10 PM PDT 24
Peak memory 183032 kb
Host smart-b26e9795-7631-4974-9d4b-4e82161b4e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477143784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2477143784
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2241574568
Short name T350
Test name
Test status
Simulation time 30368370787 ps
CPU time 41.88 seconds
Started Jul 07 06:08:30 PM PDT 24
Finished Jul 07 06:09:12 PM PDT 24
Peak memory 183132 kb
Host smart-e953292e-5972-4207-80e0-9a916c9a3927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241574568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2241574568
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.4003217311
Short name T450
Test name
Test status
Simulation time 948027927 ps
CPU time 2.17 seconds
Started Jul 07 06:08:30 PM PDT 24
Finished Jul 07 06:08:32 PM PDT 24
Peak memory 182980 kb
Host smart-475fdb64-744a-4006-bb03-3cda5bd03946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003217311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.4003217311
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3521846274
Short name T228
Test name
Test status
Simulation time 268188288566 ps
CPU time 242.36 seconds
Started Jul 07 06:08:28 PM PDT 24
Finished Jul 07 06:12:31 PM PDT 24
Peak memory 191336 kb
Host smart-d6e83916-38f1-4309-98b1-95745c108a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521846274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3521846274
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2616206161
Short name T334
Test name
Test status
Simulation time 166866572224 ps
CPU time 244.23 seconds
Started Jul 07 06:05:52 PM PDT 24
Finished Jul 07 06:09:56 PM PDT 24
Peak memory 183096 kb
Host smart-a216720c-b6c5-427d-ae8b-8f5abde2efe2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616206161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2616206161
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.997912547
Short name T443
Test name
Test status
Simulation time 376022724971 ps
CPU time 275.97 seconds
Started Jul 07 06:05:52 PM PDT 24
Finished Jul 07 06:10:29 PM PDT 24
Peak memory 183128 kb
Host smart-81dc2b57-0884-4498-a091-4fe7815cfaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997912547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.997912547
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3471746731
Short name T176
Test name
Test status
Simulation time 140753319224 ps
CPU time 456.58 seconds
Started Jul 07 06:05:53 PM PDT 24
Finished Jul 07 06:13:29 PM PDT 24
Peak memory 191332 kb
Host smart-f042d955-9408-476d-9a97-ff1601818502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471746731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3471746731
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.337687419
Short name T398
Test name
Test status
Simulation time 436575066776 ps
CPU time 333.24 seconds
Started Jul 07 06:05:50 PM PDT 24
Finished Jul 07 06:11:24 PM PDT 24
Peak memory 195112 kb
Host smart-8d18ead8-078e-476f-9ff1-950ea857feef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337687419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.337687419
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1074074937
Short name T113
Test name
Test status
Simulation time 92017860073 ps
CPU time 43.6 seconds
Started Jul 07 06:08:28 PM PDT 24
Finished Jul 07 06:09:12 PM PDT 24
Peak memory 183136 kb
Host smart-75d44351-69c6-4e51-a35f-6af60fd7a203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074074937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1074074937
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.466550568
Short name T254
Test name
Test status
Simulation time 152059199722 ps
CPU time 730.71 seconds
Started Jul 07 06:08:27 PM PDT 24
Finished Jul 07 06:20:38 PM PDT 24
Peak memory 191328 kb
Host smart-aba6fc34-d659-488a-b022-567c259ada75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466550568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.466550568
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2110566725
Short name T250
Test name
Test status
Simulation time 1507331440903 ps
CPU time 506.78 seconds
Started Jul 07 06:08:26 PM PDT 24
Finished Jul 07 06:16:53 PM PDT 24
Peak memory 191344 kb
Host smart-9107c09e-198e-463d-8ea2-40529d00d0e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110566725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2110566725
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.57999212
Short name T342
Test name
Test status
Simulation time 126103499817 ps
CPU time 58.39 seconds
Started Jul 07 06:08:31 PM PDT 24
Finished Jul 07 06:09:30 PM PDT 24
Peak memory 191320 kb
Host smart-3d243673-3776-4020-8995-c68d0ecfe6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57999212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.57999212
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.555080110
Short name T298
Test name
Test status
Simulation time 32035346127 ps
CPU time 14.11 seconds
Started Jul 07 06:08:26 PM PDT 24
Finished Jul 07 06:08:40 PM PDT 24
Peak memory 183132 kb
Host smart-d93ce700-cc22-4ebd-a61e-8525f9711e3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555080110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.555080110
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1261459964
Short name T440
Test name
Test status
Simulation time 196944435857 ps
CPU time 104.5 seconds
Started Jul 07 06:08:31 PM PDT 24
Finished Jul 07 06:10:16 PM PDT 24
Peak memory 191372 kb
Host smart-c44588d2-dd9c-4824-abcd-d49fe031b221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261459964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1261459964
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2246262524
Short name T426
Test name
Test status
Simulation time 32169007477 ps
CPU time 26.21 seconds
Started Jul 07 06:05:55 PM PDT 24
Finished Jul 07 06:06:21 PM PDT 24
Peak memory 183392 kb
Host smart-c1ec34af-fb59-4633-a098-91e5257fa8b0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246262524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2246262524
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.1239802997
Short name T425
Test name
Test status
Simulation time 154851176537 ps
CPU time 102 seconds
Started Jul 07 06:05:57 PM PDT 24
Finished Jul 07 06:07:39 PM PDT 24
Peak memory 183100 kb
Host smart-07275298-b3ef-4650-8b18-fe50eee857b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239802997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.1239802997
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2412181468
Short name T346
Test name
Test status
Simulation time 264346142711 ps
CPU time 71.51 seconds
Started Jul 07 06:05:56 PM PDT 24
Finished Jul 07 06:07:08 PM PDT 24
Peak memory 191360 kb
Host smart-080fbaf2-7ec7-4889-9463-ff4f704ea95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412181468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2412181468
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.635438535
Short name T364
Test name
Test status
Simulation time 18323208 ps
CPU time 0.55 seconds
Started Jul 07 06:05:57 PM PDT 24
Finished Jul 07 06:05:58 PM PDT 24
Peak memory 182952 kb
Host smart-fd451098-dfb8-47c4-ac16-568411abe123
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635438535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.635438535
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.3271450830
Short name T281
Test name
Test status
Simulation time 57671326585 ps
CPU time 101.98 seconds
Started Jul 07 06:08:30 PM PDT 24
Finished Jul 07 06:10:13 PM PDT 24
Peak memory 191292 kb
Host smart-b9ec657e-7bea-4fed-aea5-26735e983790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271450830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3271450830
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3491170027
Short name T146
Test name
Test status
Simulation time 93306823160 ps
CPU time 134.83 seconds
Started Jul 07 06:08:36 PM PDT 24
Finished Jul 07 06:10:51 PM PDT 24
Peak memory 191220 kb
Host smart-292e87fe-bd04-4a66-a4d9-3087183a9574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491170027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3491170027
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3066676725
Short name T306
Test name
Test status
Simulation time 51150714322 ps
CPU time 83.06 seconds
Started Jul 07 06:08:37 PM PDT 24
Finished Jul 07 06:10:00 PM PDT 24
Peak memory 183144 kb
Host smart-f9f4ea2f-f990-4347-b58e-40aba43966dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066676725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3066676725
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.4154309503
Short name T309
Test name
Test status
Simulation time 410534926984 ps
CPU time 194.61 seconds
Started Jul 07 06:08:38 PM PDT 24
Finished Jul 07 06:11:53 PM PDT 24
Peak memory 191344 kb
Host smart-dcec728a-cf47-481c-b3a5-cc2e1b5a2c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154309503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4154309503
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.4000173266
Short name T223
Test name
Test status
Simulation time 238319194842 ps
CPU time 891.25 seconds
Started Jul 07 06:08:32 PM PDT 24
Finished Jul 07 06:23:24 PM PDT 24
Peak memory 191344 kb
Host smart-e9bf9359-2355-4264-85c9-cd7cb397bd28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000173266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.4000173266
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1640699747
Short name T415
Test name
Test status
Simulation time 165668035232 ps
CPU time 399.67 seconds
Started Jul 07 06:08:37 PM PDT 24
Finished Jul 07 06:15:17 PM PDT 24
Peak memory 192364 kb
Host smart-c92bf1ec-6315-4d9e-b45a-fa0beea9673e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640699747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1640699747
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.2184036601
Short name T282
Test name
Test status
Simulation time 193607503458 ps
CPU time 295.7 seconds
Started Jul 07 06:08:37 PM PDT 24
Finished Jul 07 06:13:33 PM PDT 24
Peak memory 191328 kb
Host smart-09dd3c64-6740-4f07-9539-4a9cb1d831cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184036601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.2184036601
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2018550649
Short name T102
Test name
Test status
Simulation time 222687694297 ps
CPU time 332.84 seconds
Started Jul 07 06:08:39 PM PDT 24
Finished Jul 07 06:14:12 PM PDT 24
Peak memory 191344 kb
Host smart-b3aafd29-fa70-45a1-9fff-79889e751fd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018550649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2018550649
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2788993426
Short name T231
Test name
Test status
Simulation time 464822975224 ps
CPU time 421.02 seconds
Started Jul 07 06:08:44 PM PDT 24
Finished Jul 07 06:15:46 PM PDT 24
Peak memory 191344 kb
Host smart-06fbb25e-bd8d-4201-9350-e1f5bb6c24de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788993426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2788993426
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2424297129
Short name T356
Test name
Test status
Simulation time 244738265746 ps
CPU time 85.5 seconds
Started Jul 07 06:06:04 PM PDT 24
Finished Jul 07 06:07:30 PM PDT 24
Peak memory 183168 kb
Host smart-e9047921-4d87-4b44-9a9f-395dd0e751f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424297129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2424297129
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3983784121
Short name T241
Test name
Test status
Simulation time 591025339145 ps
CPU time 86.85 seconds
Started Jul 07 06:05:56 PM PDT 24
Finished Jul 07 06:07:23 PM PDT 24
Peak memory 191336 kb
Host smart-b55c49ee-4875-4185-b5a6-193f4053d408
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983784121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3983784121
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1668803857
Short name T88
Test name
Test status
Simulation time 47921539525 ps
CPU time 155.83 seconds
Started Jul 07 06:06:00 PM PDT 24
Finished Jul 07 06:08:36 PM PDT 24
Peak memory 191364 kb
Host smart-eec09e96-da9c-4008-86ea-a6be7e386809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668803857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1668803857
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/82.rv_timer_random.4008291139
Short name T234
Test name
Test status
Simulation time 102017369299 ps
CPU time 826.58 seconds
Started Jul 07 06:08:48 PM PDT 24
Finished Jul 07 06:22:35 PM PDT 24
Peak memory 191324 kb
Host smart-32e4c60e-aa5d-4191-8c8d-962c6a6f2c12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008291139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.4008291139
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.2831497957
Short name T9
Test name
Test status
Simulation time 119043704890 ps
CPU time 407 seconds
Started Jul 07 06:08:47 PM PDT 24
Finished Jul 07 06:15:35 PM PDT 24
Peak memory 191324 kb
Host smart-3eccbb00-63bf-4ac2-8809-5f840bda242a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831497957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.2831497957
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1477727548
Short name T430
Test name
Test status
Simulation time 32957915719 ps
CPU time 262.12 seconds
Started Jul 07 06:08:44 PM PDT 24
Finished Jul 07 06:13:07 PM PDT 24
Peak memory 183120 kb
Host smart-c9ed11d7-74c9-4734-ac93-1f2a0e2fe488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477727548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1477727548
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1836971307
Short name T219
Test name
Test status
Simulation time 46802284578 ps
CPU time 39.48 seconds
Started Jul 07 06:08:47 PM PDT 24
Finished Jul 07 06:09:27 PM PDT 24
Peak memory 191340 kb
Host smart-f395a4e1-c88b-4482-a6fe-382cb07d6d28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836971307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1836971307
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1555069324
Short name T251
Test name
Test status
Simulation time 367044509430 ps
CPU time 261.9 seconds
Started Jul 07 06:08:46 PM PDT 24
Finished Jul 07 06:13:08 PM PDT 24
Peak memory 191336 kb
Host smart-bac5799f-3368-4e08-8fe0-faea18e5b6ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555069324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1555069324
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3288588955
Short name T447
Test name
Test status
Simulation time 191234067319 ps
CPU time 325.25 seconds
Started Jul 07 06:08:43 PM PDT 24
Finished Jul 07 06:14:09 PM PDT 24
Peak memory 191332 kb
Host smart-5d92554d-07ba-4bab-8f11-7b03987b2b90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288588955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3288588955
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.2155733777
Short name T110
Test name
Test status
Simulation time 568422515052 ps
CPU time 252.54 seconds
Started Jul 07 06:08:49 PM PDT 24
Finished Jul 07 06:13:01 PM PDT 24
Peak memory 191288 kb
Host smart-5f961205-f9f7-494f-a32a-6992989634ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155733777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2155733777
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3542962070
Short name T159
Test name
Test status
Simulation time 323811349842 ps
CPU time 1514.49 seconds
Started Jul 07 06:08:49 PM PDT 24
Finished Jul 07 06:34:04 PM PDT 24
Peak memory 191328 kb
Host smart-a7db4b6a-b7ee-4349-a167-10f82a089152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542962070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3542962070
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1485594151
Short name T84
Test name
Test status
Simulation time 527141738235 ps
CPU time 423.1 seconds
Started Jul 07 06:06:09 PM PDT 24
Finished Jul 07 06:13:13 PM PDT 24
Peak memory 183104 kb
Host smart-085d5c5c-a891-4221-afed-490c89a05db3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485594151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1485594151
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.4185352476
Short name T318
Test name
Test status
Simulation time 30078844515 ps
CPU time 50.47 seconds
Started Jul 07 06:06:07 PM PDT 24
Finished Jul 07 06:06:58 PM PDT 24
Peak memory 191348 kb
Host smart-b3e45c4e-fb43-4db0-bf02-b98f6aeea069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185352476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.4185352476
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2724158302
Short name T402
Test name
Test status
Simulation time 96394389 ps
CPU time 0.68 seconds
Started Jul 07 06:06:07 PM PDT 24
Finished Jul 07 06:06:08 PM PDT 24
Peak memory 182892 kb
Host smart-5e53deb8-0a4e-4f1d-80e8-8e9a2aaa601e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724158302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2724158302
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.4292109789
Short name T304
Test name
Test status
Simulation time 211466490737 ps
CPU time 3000.97 seconds
Started Jul 07 06:08:48 PM PDT 24
Finished Jul 07 06:58:49 PM PDT 24
Peak memory 191344 kb
Host smart-0eef341f-b1e2-4a01-b61d-ffee8e157c9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292109789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4292109789
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2015206656
Short name T243
Test name
Test status
Simulation time 16270217836 ps
CPU time 28.55 seconds
Started Jul 07 06:08:47 PM PDT 24
Finished Jul 07 06:09:16 PM PDT 24
Peak memory 183068 kb
Host smart-f9941cdd-21e0-4d8c-92b1-f3d65d79a12d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015206656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2015206656
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3586771950
Short name T222
Test name
Test status
Simulation time 73443143549 ps
CPU time 105.46 seconds
Started Jul 07 06:08:50 PM PDT 24
Finished Jul 07 06:10:35 PM PDT 24
Peak memory 193704 kb
Host smart-8050ee46-eca2-4214-9aca-e0198acc9883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586771950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3586771950
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3462011769
Short name T247
Test name
Test status
Simulation time 227007924236 ps
CPU time 204.77 seconds
Started Jul 07 06:08:57 PM PDT 24
Finished Jul 07 06:12:22 PM PDT 24
Peak memory 191344 kb
Host smart-84774a28-580c-4af9-89f9-4fcc3315fb05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462011769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3462011769
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1481022916
Short name T186
Test name
Test status
Simulation time 11863067950 ps
CPU time 272.39 seconds
Started Jul 07 06:08:57 PM PDT 24
Finished Jul 07 06:13:30 PM PDT 24
Peak memory 191344 kb
Host smart-c5ebdce1-25a7-4cc5-976e-d8ff9d6514fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481022916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1481022916
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.3887967494
Short name T456
Test name
Test status
Simulation time 1045732724006 ps
CPU time 454.46 seconds
Started Jul 07 06:08:50 PM PDT 24
Finished Jul 07 06:16:24 PM PDT 24
Peak memory 191304 kb
Host smart-ff3554cd-11b6-4eb9-8b67-69ac67112e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887967494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3887967494
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.837584946
Short name T445
Test name
Test status
Simulation time 30043258202 ps
CPU time 37.75 seconds
Started Jul 07 06:08:57 PM PDT 24
Finished Jul 07 06:09:35 PM PDT 24
Peak memory 183052 kb
Host smart-079ce6d0-8982-4df5-be1a-66b1e8afc4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837584946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.837584946
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1568682880
Short name T270
Test name
Test status
Simulation time 55764114317 ps
CPU time 26.35 seconds
Started Jul 07 06:08:57 PM PDT 24
Finished Jul 07 06:09:24 PM PDT 24
Peak memory 193548 kb
Host smart-5ddf4d93-700c-4587-a543-c243f6198bc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568682880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1568682880
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.578495506
Short name T143
Test name
Test status
Simulation time 238671329310 ps
CPU time 544.32 seconds
Started Jul 07 06:08:56 PM PDT 24
Finished Jul 07 06:18:01 PM PDT 24
Peak memory 191340 kb
Host smart-7e656815-89f2-436f-8426-f5426120ef84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578495506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.578495506
Directory /workspace/98.rv_timer_random/latest
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