Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
122208718 |
1 |
|
T1 |
21 |
|
T2 |
815 |
|
T3 |
43 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
62457619 |
1 |
|
T1 |
12 |
|
T2 |
6 |
|
T3 |
27 |
auto[1] |
59751099 |
1 |
|
T1 |
9 |
|
T2 |
809 |
|
T3 |
16 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
122203046 |
1 |
|
T1 |
14 |
|
T2 |
815 |
|
T3 |
37 |
auto[1] |
5672 |
1 |
|
T1 |
7 |
|
T3 |
6 |
|
T4 |
120 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
62454744 |
1 |
|
T1 |
6 |
|
T2 |
6 |
|
T3 |
21 |
all_values[0] |
auto[0] |
auto[1] |
2875 |
1 |
|
T1 |
6 |
|
T3 |
6 |
|
T4 |
53 |
all_values[0] |
auto[1] |
auto[0] |
59748302 |
1 |
|
T1 |
8 |
|
T2 |
809 |
|
T3 |
16 |
all_values[0] |
auto[1] |
auto[1] |
2797 |
1 |
|
T1 |
1 |
|
T4 |
67 |
|
T6 |
21 |