Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 573
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T509 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1598443899 Jul 09 04:35:09 PM PDT 24 Jul 09 04:35:12 PM PDT 24 742541605 ps
T510 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2230729176 Jul 09 04:35:13 PM PDT 24 Jul 09 04:35:15 PM PDT 24 25590143 ps
T511 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.724421645 Jul 09 04:35:16 PM PDT 24 Jul 09 04:35:18 PM PDT 24 19841394 ps
T512 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.459991996 Jul 09 04:27:17 PM PDT 24 Jul 09 04:27:22 PM PDT 24 67438543 ps
T513 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.308655846 Jul 09 04:35:08 PM PDT 24 Jul 09 04:35:10 PM PDT 24 210124262 ps
T514 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1170294052 Jul 09 04:35:15 PM PDT 24 Jul 09 04:35:18 PM PDT 24 115033171 ps
T515 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1229398789 Jul 09 04:35:09 PM PDT 24 Jul 09 04:35:12 PM PDT 24 99260026 ps
T66 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.877788301 Jul 09 04:27:20 PM PDT 24 Jul 09 04:27:27 PM PDT 24 176087049 ps
T516 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2872889922 Jul 09 04:35:34 PM PDT 24 Jul 09 04:35:35 PM PDT 24 44620261 ps
T517 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3452271826 Jul 09 04:35:21 PM PDT 24 Jul 09 04:35:23 PM PDT 24 45402290 ps
T518 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.248270701 Jul 09 04:35:02 PM PDT 24 Jul 09 04:35:03 PM PDT 24 43395196 ps
T519 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1909065354 Jul 09 04:35:06 PM PDT 24 Jul 09 04:35:08 PM PDT 24 39591829 ps
T67 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.201650478 Jul 09 04:24:49 PM PDT 24 Jul 09 04:24:52 PM PDT 24 65049023 ps
T520 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1731279232 Jul 09 04:35:14 PM PDT 24 Jul 09 04:35:16 PM PDT 24 45388785 ps
T521 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1647992923 Jul 09 04:35:08 PM PDT 24 Jul 09 04:35:11 PM PDT 24 11740487 ps
T522 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3816675053 Jul 09 04:35:13 PM PDT 24 Jul 09 04:35:16 PM PDT 24 452142335 ps
T523 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.444241160 Jul 09 04:35:09 PM PDT 24 Jul 09 04:35:12 PM PDT 24 65002139 ps
T524 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2808389033 Jul 09 04:35:06 PM PDT 24 Jul 09 04:35:09 PM PDT 24 499173657 ps
T525 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2842736517 Jul 09 04:22:44 PM PDT 24 Jul 09 04:22:46 PM PDT 24 21396454 ps
T526 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3757652106 Jul 09 04:35:28 PM PDT 24 Jul 09 04:35:31 PM PDT 24 14470850 ps
T527 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3899281668 Jul 09 04:35:23 PM PDT 24 Jul 09 04:35:24 PM PDT 24 45180954 ps
T528 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4010276936 Jul 09 04:35:12 PM PDT 24 Jul 09 04:35:15 PM PDT 24 36415269 ps
T529 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1018445920 Jul 09 04:35:07 PM PDT 24 Jul 09 04:35:10 PM PDT 24 57465594 ps
T68 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3120585433 Jul 09 04:35:10 PM PDT 24 Jul 09 04:35:13 PM PDT 24 53285700 ps
T530 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3347787866 Jul 09 04:36:47 PM PDT 24 Jul 09 04:36:48 PM PDT 24 17616258 ps
T531 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2701484012 Jul 09 04:35:15 PM PDT 24 Jul 09 04:35:19 PM PDT 24 420198884 ps
T532 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.403618135 Jul 09 04:27:22 PM PDT 24 Jul 09 04:27:27 PM PDT 24 308442674 ps
T533 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3925647077 Jul 09 04:35:17 PM PDT 24 Jul 09 04:35:19 PM PDT 24 20920329 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.643768171 Jul 09 04:27:18 PM PDT 24 Jul 09 04:27:23 PM PDT 24 35888951 ps
T535 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1787128399 Jul 09 04:35:05 PM PDT 24 Jul 09 04:35:07 PM PDT 24 59533622 ps
T536 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3599903806 Jul 09 04:36:22 PM PDT 24 Jul 09 04:36:24 PM PDT 24 94566312 ps
T69 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3843980083 Jul 09 04:26:39 PM PDT 24 Jul 09 04:26:41 PM PDT 24 35994160 ps
T537 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2831495693 Jul 09 04:26:27 PM PDT 24 Jul 09 04:26:28 PM PDT 24 31607436 ps
T538 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1817513735 Jul 09 04:36:22 PM PDT 24 Jul 09 04:36:25 PM PDT 24 189871476 ps
T539 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4112932061 Jul 09 04:35:06 PM PDT 24 Jul 09 04:35:07 PM PDT 24 32240337 ps
T540 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4120629678 Jul 09 04:35:05 PM PDT 24 Jul 09 04:35:07 PM PDT 24 16682468 ps
T541 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2981283066 Jul 09 04:35:12 PM PDT 24 Jul 09 04:35:15 PM PDT 24 19203745 ps
T542 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.979078322 Jul 09 04:35:08 PM PDT 24 Jul 09 04:35:10 PM PDT 24 35323126 ps
T543 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.200530063 Jul 09 04:35:03 PM PDT 24 Jul 09 04:35:04 PM PDT 24 108822455 ps
T544 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2723462732 Jul 09 04:35:09 PM PDT 24 Jul 09 04:35:13 PM PDT 24 398324424 ps
T545 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4256735487 Jul 09 04:35:05 PM PDT 24 Jul 09 04:35:06 PM PDT 24 74784433 ps
T546 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.566743810 Jul 09 04:35:27 PM PDT 24 Jul 09 04:35:30 PM PDT 24 14270676 ps
T547 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2170273565 Jul 09 04:26:54 PM PDT 24 Jul 09 04:27:01 PM PDT 24 169610074 ps
T548 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2960361022 Jul 09 04:35:21 PM PDT 24 Jul 09 04:35:22 PM PDT 24 46824606 ps
T549 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1244747925 Jul 09 04:24:06 PM PDT 24 Jul 09 04:24:07 PM PDT 24 19373102 ps
T80 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3974966895 Jul 09 04:26:55 PM PDT 24 Jul 09 04:27:02 PM PDT 24 132400941 ps
T550 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1731627540 Jul 09 04:35:15 PM PDT 24 Jul 09 04:35:18 PM PDT 24 32483680 ps
T551 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3466089119 Jul 09 04:35:13 PM PDT 24 Jul 09 04:35:16 PM PDT 24 52941652 ps
T552 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.147453252 Jul 09 04:35:09 PM PDT 24 Jul 09 04:35:12 PM PDT 24 15564036 ps
T553 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.158021199 Jul 09 04:35:17 PM PDT 24 Jul 09 04:35:19 PM PDT 24 36536649 ps
T554 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2386373611 Jul 09 04:26:37 PM PDT 24 Jul 09 04:26:39 PM PDT 24 131919812 ps
T555 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1656683961 Jul 09 04:35:07 PM PDT 24 Jul 09 04:35:10 PM PDT 24 17577150 ps
T556 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3526776454 Jul 09 04:35:21 PM PDT 24 Jul 09 04:35:22 PM PDT 24 12281217 ps
T557 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2940046437 Jul 09 04:35:14 PM PDT 24 Jul 09 04:35:17 PM PDT 24 92681077 ps
T83 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1942221429 Jul 09 04:35:03 PM PDT 24 Jul 09 04:35:05 PM PDT 24 452112950 ps
T558 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3572997562 Jul 09 04:27:44 PM PDT 24 Jul 09 04:27:45 PM PDT 24 18628868 ps
T559 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1089236089 Jul 09 04:35:10 PM PDT 24 Jul 09 04:35:13 PM PDT 24 15192924 ps
T70 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.112776680 Jul 09 04:26:36 PM PDT 24 Jul 09 04:26:38 PM PDT 24 67151894 ps
T560 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2684100042 Jul 09 04:35:08 PM PDT 24 Jul 09 04:35:10 PM PDT 24 50525059 ps
T561 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2966831462 Jul 09 04:27:54 PM PDT 24 Jul 09 04:27:56 PM PDT 24 142212647 ps
T84 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4169939144 Jul 09 04:35:01 PM PDT 24 Jul 09 04:35:02 PM PDT 24 53267580 ps
T562 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2342825055 Jul 09 04:27:56 PM PDT 24 Jul 09 04:27:58 PM PDT 24 69976049 ps
T563 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1780326896 Jul 09 04:27:20 PM PDT 24 Jul 09 04:27:24 PM PDT 24 30075773 ps
T564 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3751816195 Jul 09 04:35:28 PM PDT 24 Jul 09 04:35:30 PM PDT 24 11906083 ps
T565 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.424967077 Jul 09 04:35:10 PM PDT 24 Jul 09 04:35:13 PM PDT 24 57349615 ps
T566 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2315222394 Jul 09 04:35:10 PM PDT 24 Jul 09 04:35:13 PM PDT 24 47000547 ps
T567 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.760211149 Jul 09 04:35:26 PM PDT 24 Jul 09 04:35:27 PM PDT 24 12226405 ps
T568 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1596637690 Jul 09 04:26:59 PM PDT 24 Jul 09 04:27:05 PM PDT 24 89860406 ps
T569 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1758879873 Jul 09 04:27:05 PM PDT 24 Jul 09 04:27:13 PM PDT 24 559444339 ps
T570 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.904439266 Jul 09 04:26:40 PM PDT 24 Jul 09 04:26:44 PM PDT 24 153806623 ps
T571 /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3174847907 Jul 09 04:35:05 PM PDT 24 Jul 09 04:35:08 PM PDT 24 472532941 ps
T572 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1717527519 Jul 09 04:35:11 PM PDT 24 Jul 09 04:35:15 PM PDT 24 44229423 ps
T573 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2533059376 Jul 09 04:27:01 PM PDT 24 Jul 09 04:27:08 PM PDT 24 158119196 ps

Test location /workspace/coverage/default/145.rv_timer_random.1241735927
Short name T10
Test name
Test status
Simulation time 149318417595 ps
CPU time 223.97 seconds
Started Jul 09 04:36:25 PM PDT 24
Finished Jul 09 04:40:10 PM PDT 24
Peak memory 191192 kb
Host smart-0ec93267-cd38-40a9-a14d-f6a4bc20e10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241735927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1241735927
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.726744158
Short name T12
Test name
Test status
Simulation time 87975782502 ps
CPU time 291.35 seconds
Started Jul 09 04:27:22 PM PDT 24
Finished Jul 09 04:32:17 PM PDT 24
Peak memory 205840 kb
Host smart-3a442765-3536-4f4d-908b-330c8dfdc2d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726744158 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.726744158
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.96496202
Short name T4
Test name
Test status
Simulation time 519731657524 ps
CPU time 1114.8 seconds
Started Jul 09 04:36:02 PM PDT 24
Finished Jul 09 04:54:38 PM PDT 24
Peak memory 195880 kb
Host smart-a94a6720-c012-4d3e-b9f5-15c7b8beadb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96496202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.96496202
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1069691450
Short name T29
Test name
Test status
Simulation time 309679692 ps
CPU time 1.06 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 194608 kb
Host smart-5dea061f-481a-4377-b87e-8be9ceeaa10f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069691450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1069691450
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1629388814
Short name T94
Test name
Test status
Simulation time 1121540908154 ps
CPU time 1046.34 seconds
Started Jul 09 04:35:37 PM PDT 24
Finished Jul 09 04:53:05 PM PDT 24
Peak memory 191168 kb
Host smart-d5e9a070-9c25-42b0-9abd-3f9a74716fef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629388814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1629388814
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.416160763
Short name T86
Test name
Test status
Simulation time 917870871690 ps
CPU time 1196.89 seconds
Started Jul 09 04:35:39 PM PDT 24
Finished Jul 09 04:55:37 PM PDT 24
Peak memory 191184 kb
Host smart-b6b7884d-baf0-441b-bf17-ddc24dba7ed3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416160763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
416160763
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.304841372
Short name T269
Test name
Test status
Simulation time 2585502211855 ps
CPU time 2447.76 seconds
Started Jul 09 04:35:24 PM PDT 24
Finished Jul 09 05:16:13 PM PDT 24
Peak memory 191144 kb
Host smart-5387ac13-1ff0-4544-8293-b0cdc4bd9729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304841372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
304841372
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2841778421
Short name T108
Test name
Test status
Simulation time 1414726777134 ps
CPU time 1192.39 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:55:23 PM PDT 24
Peak memory 191120 kb
Host smart-70499c89-f501-42de-8623-c82def3b934a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841778421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2841778421
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1524695617
Short name T143
Test name
Test status
Simulation time 743778857467 ps
CPU time 2043.58 seconds
Started Jul 09 04:35:21 PM PDT 24
Finished Jul 09 05:09:26 PM PDT 24
Peak memory 191064 kb
Host smart-0470c4df-bee3-438b-8dc3-d86adcc5954a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524695617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1524695617
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3686797702
Short name T55
Test name
Test status
Simulation time 1297365889790 ps
CPU time 1150.35 seconds
Started Jul 09 04:35:29 PM PDT 24
Finished Jul 09 04:54:41 PM PDT 24
Peak memory 191116 kb
Host smart-00b34f02-6c7e-4dd2-b077-d10a9f73b65e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686797702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3686797702
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1024163535
Short name T51
Test name
Test status
Simulation time 21125187 ps
CPU time 0.59 seconds
Started Jul 09 04:27:13 PM PDT 24
Finished Jul 09 04:27:19 PM PDT 24
Peak memory 182060 kb
Host smart-0061bce3-c296-4792-a83c-4322315a2e74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024163535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1024163535
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2999737876
Short name T93
Test name
Test status
Simulation time 219523482438 ps
CPU time 1486.21 seconds
Started Jul 09 04:35:52 PM PDT 24
Finished Jul 09 05:00:40 PM PDT 24
Peak memory 191184 kb
Host smart-cdf3fb1a-fb31-4bce-be00-ad185c423714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999737876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2999737876
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3599718130
Short name T85
Test name
Test status
Simulation time 1429529645671 ps
CPU time 4043.89 seconds
Started Jul 09 04:35:49 PM PDT 24
Finished Jul 09 05:43:13 PM PDT 24
Peak memory 195936 kb
Host smart-958f0e33-a3b5-48fb-92a6-6f14d022f7ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599718130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3599718130
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1342609676
Short name T172
Test name
Test status
Simulation time 615418512794 ps
CPU time 1601.51 seconds
Started Jul 09 04:35:29 PM PDT 24
Finished Jul 09 05:02:13 PM PDT 24
Peak memory 196012 kb
Host smart-dc13cd2e-eec7-4d76-99de-080895e39f34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342609676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1342609676
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.157457231
Short name T17
Test name
Test status
Simulation time 215052120 ps
CPU time 0.91 seconds
Started Jul 09 04:25:37 PM PDT 24
Finished Jul 09 04:25:38 PM PDT 24
Peak memory 213564 kb
Host smart-d21239d0-0ad0-4e87-8602-eb7075aed88f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157457231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.157457231
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/158.rv_timer_random.1531206902
Short name T11
Test name
Test status
Simulation time 725774115256 ps
CPU time 666.89 seconds
Started Jul 09 04:36:35 PM PDT 24
Finished Jul 09 04:47:42 PM PDT 24
Peak memory 191584 kb
Host smart-0990aa94-53b8-4cb0-8e09-ba3665bdeb6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531206902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1531206902
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.4235648983
Short name T21
Test name
Test status
Simulation time 4797844861639 ps
CPU time 893.98 seconds
Started Jul 09 04:35:44 PM PDT 24
Finished Jul 09 04:50:39 PM PDT 24
Peak memory 191036 kb
Host smart-f4e69f60-a32f-459f-9acc-1d0305e606e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235648983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.4235648983
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3786383618
Short name T244
Test name
Test status
Simulation time 668721348384 ps
CPU time 1187.56 seconds
Started Jul 09 04:26:54 PM PDT 24
Finished Jul 09 04:46:47 PM PDT 24
Peak memory 190860 kb
Host smart-cc0fecc6-a97b-4d1b-9a57-231f345b2147
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786383618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3786383618
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.1911187673
Short name T148
Test name
Test status
Simulation time 293274693420 ps
CPU time 647.22 seconds
Started Jul 09 04:35:25 PM PDT 24
Finished Jul 09 04:46:13 PM PDT 24
Peak memory 191148 kb
Host smart-7a39ac09-c042-47c5-898a-38bee44a178a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911187673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.1911187673
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1572647893
Short name T132
Test name
Test status
Simulation time 258181251001 ps
CPU time 505.47 seconds
Started Jul 09 04:35:38 PM PDT 24
Finished Jul 09 04:44:05 PM PDT 24
Peak memory 195372 kb
Host smart-b630593c-ae35-4640-b2a1-7d55ec94ad15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572647893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1572647893
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/139.rv_timer_random.171242020
Short name T247
Test name
Test status
Simulation time 818994591696 ps
CPU time 227.48 seconds
Started Jul 09 04:36:18 PM PDT 24
Finished Jul 09 04:40:06 PM PDT 24
Peak memory 193788 kb
Host smart-c020d6b4-ed0d-46bb-bb8b-fbd62ddaff85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171242020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.171242020
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1873234607
Short name T54
Test name
Test status
Simulation time 518665093245 ps
CPU time 1051.19 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:53:32 PM PDT 24
Peak memory 196660 kb
Host smart-9678d5ac-a824-4611-80d6-5e0ff84e1b7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873234607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1873234607
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/176.rv_timer_random.1994741743
Short name T28
Test name
Test status
Simulation time 1145525257313 ps
CPU time 2073.4 seconds
Started Jul 09 04:36:30 PM PDT 24
Finished Jul 09 05:11:05 PM PDT 24
Peak memory 191172 kb
Host smart-271b9a1b-ee30-4d71-972c-ca5a7b2bb149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994741743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1994741743
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.1051603369
Short name T264
Test name
Test status
Simulation time 829694191160 ps
CPU time 2369.1 seconds
Started Jul 09 04:35:40 PM PDT 24
Finished Jul 09 05:15:15 PM PDT 24
Peak memory 191196 kb
Host smart-fb8244da-7f30-4122-bb20-f353725a1af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051603369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.1051603369
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1396152009
Short name T199
Test name
Test status
Simulation time 2683541937821 ps
CPU time 1779.97 seconds
Started Jul 09 04:35:23 PM PDT 24
Finished Jul 09 05:05:04 PM PDT 24
Peak memory 191176 kb
Host smart-799746a6-d03a-4331-938f-eda961a47fbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396152009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1396152009
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/149.rv_timer_random.2702224194
Short name T165
Test name
Test status
Simulation time 161323009145 ps
CPU time 286.48 seconds
Started Jul 09 04:36:26 PM PDT 24
Finished Jul 09 04:41:13 PM PDT 24
Peak memory 191280 kb
Host smart-c39a693a-9c3f-45c8-8777-f5677a8984d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702224194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2702224194
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/160.rv_timer_random.690178783
Short name T206
Test name
Test status
Simulation time 259847551099 ps
CPU time 666.53 seconds
Started Jul 09 04:36:24 PM PDT 24
Finished Jul 09 04:47:32 PM PDT 24
Peak memory 191204 kb
Host smart-49227c29-3785-4990-969f-974ab1bc8f26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690178783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.690178783
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.2191232442
Short name T95
Test name
Test status
Simulation time 716426514483 ps
CPU time 251.16 seconds
Started Jul 09 04:35:26 PM PDT 24
Finished Jul 09 04:39:38 PM PDT 24
Peak memory 191144 kb
Host smart-d4a2b8e7-79e4-4aaf-834f-5922eaf87de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191232442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2191232442
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.3931379263
Short name T179
Test name
Test status
Simulation time 130647622775 ps
CPU time 390.44 seconds
Started Jul 09 04:35:26 PM PDT 24
Finished Jul 09 04:41:58 PM PDT 24
Peak memory 191172 kb
Host smart-d3ad522c-8af8-4041-8909-e6de1060c0ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931379263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3931379263
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2336501204
Short name T329
Test name
Test status
Simulation time 603582788080 ps
CPU time 608.7 seconds
Started Jul 09 04:35:49 PM PDT 24
Finished Jul 09 04:45:58 PM PDT 24
Peak memory 182980 kb
Host smart-bff93648-3bae-42d4-b1e8-9072548fe419
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336501204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2336501204
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.766137582
Short name T25
Test name
Test status
Simulation time 470846195446 ps
CPU time 825.11 seconds
Started Jul 09 04:36:02 PM PDT 24
Finished Jul 09 04:49:48 PM PDT 24
Peak memory 182992 kb
Host smart-392419d8-49c3-419a-a3ec-9c7857e38c7b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766137582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.rv_timer_cfg_update_on_fly.766137582
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_random.2247746037
Short name T135
Test name
Test status
Simulation time 415551030580 ps
CPU time 788.11 seconds
Started Jul 09 04:35:27 PM PDT 24
Finished Jul 09 04:48:36 PM PDT 24
Peak memory 194352 kb
Host smart-83fde999-d9fe-4357-a5a9-acb886d1a1f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247746037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2247746037
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.1361605866
Short name T157
Test name
Test status
Simulation time 2759020724680 ps
CPU time 691.21 seconds
Started Jul 09 04:35:29 PM PDT 24
Finished Jul 09 04:47:03 PM PDT 24
Peak memory 191180 kb
Host smart-c87b8823-5512-4dab-99cd-5af46a3c4067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361605866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1361605866
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.3270953569
Short name T220
Test name
Test status
Simulation time 585222497461 ps
CPU time 492.38 seconds
Started Jul 09 04:35:30 PM PDT 24
Finished Jul 09 04:43:45 PM PDT 24
Peak memory 191224 kb
Host smart-9f3a4621-e895-4d06-a968-26329e505760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270953569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3270953569
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.102316144
Short name T229
Test name
Test status
Simulation time 155562644045 ps
CPU time 1369.49 seconds
Started Jul 09 04:36:28 PM PDT 24
Finished Jul 09 04:59:18 PM PDT 24
Peak memory 191116 kb
Host smart-62e87edd-32d5-49d2-8f49-21bb2bbb8acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102316144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.102316144
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.2682209219
Short name T314
Test name
Test status
Simulation time 392687774208 ps
CPU time 364.08 seconds
Started Jul 09 04:27:01 PM PDT 24
Finished Jul 09 04:33:11 PM PDT 24
Peak memory 189432 kb
Host smart-2f4b04ab-07d3-4795-88d4-1d8d3d1973c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682209219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2682209219
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3392219058
Short name T340
Test name
Test status
Simulation time 453618585185 ps
CPU time 764.87 seconds
Started Jul 09 04:36:52 PM PDT 24
Finished Jul 09 04:49:38 PM PDT 24
Peak memory 191104 kb
Host smart-e6f29e75-b019-4b19-a9cc-5db382e1ad93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392219058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3392219058
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/94.rv_timer_random.2506224570
Short name T196
Test name
Test status
Simulation time 211756502523 ps
CPU time 874.19 seconds
Started Jul 09 04:36:13 PM PDT 24
Finished Jul 09 04:50:48 PM PDT 24
Peak memory 191136 kb
Host smart-bfce1ded-9c91-4b7a-ae64-b7759bcc3940
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506224570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2506224570
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random.3505415754
Short name T254
Test name
Test status
Simulation time 159823159013 ps
CPU time 370.59 seconds
Started Jul 09 04:26:53 PM PDT 24
Finished Jul 09 04:33:06 PM PDT 24
Peak memory 190980 kb
Host smart-6e954b88-0658-40e6-8603-9aaadc9f6d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505415754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3505415754
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.660934374
Short name T87
Test name
Test status
Simulation time 213121928793 ps
CPU time 222.46 seconds
Started Jul 09 04:36:18 PM PDT 24
Finished Jul 09 04:40:01 PM PDT 24
Peak memory 191180 kb
Host smart-cb63e15c-b7e8-4982-85a5-5c0bf87be03d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660934374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.660934374
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3268893599
Short name T91
Test name
Test status
Simulation time 179922348198 ps
CPU time 668.98 seconds
Started Jul 09 04:36:22 PM PDT 24
Finished Jul 09 04:47:31 PM PDT 24
Peak memory 191200 kb
Host smart-23021e19-786b-4452-8375-2eb0a81bf322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268893599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3268893599
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3589246302
Short name T139
Test name
Test status
Simulation time 115148564250 ps
CPU time 303.4 seconds
Started Jul 09 04:36:29 PM PDT 24
Finished Jul 09 04:41:33 PM PDT 24
Peak memory 191192 kb
Host smart-c6b58d3e-653f-4120-8da3-eafb7cf4a97d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589246302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3589246302
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3973418312
Short name T142
Test name
Test status
Simulation time 250633764238 ps
CPU time 218.19 seconds
Started Jul 09 04:36:29 PM PDT 24
Finished Jul 09 04:40:08 PM PDT 24
Peak memory 191112 kb
Host smart-05ab5c86-ab35-41bf-9360-97c168a3fe23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973418312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3973418312
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3643208201
Short name T141
Test name
Test status
Simulation time 533307810316 ps
CPU time 635.67 seconds
Started Jul 09 04:36:29 PM PDT 24
Finished Jul 09 04:47:05 PM PDT 24
Peak memory 191204 kb
Host smart-dcdf9e33-ea00-4254-9108-8f01ca6eb937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643208201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3643208201
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1483650857
Short name T89
Test name
Test status
Simulation time 143954232375 ps
CPU time 243.22 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:40:03 PM PDT 24
Peak memory 191204 kb
Host smart-0a5396ea-8788-4a9e-85b7-99d5f2a01a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483650857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1483650857
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.2139056245
Short name T121
Test name
Test status
Simulation time 719818520848 ps
CPU time 275.44 seconds
Started Jul 09 04:26:43 PM PDT 24
Finished Jul 09 04:31:21 PM PDT 24
Peak memory 190940 kb
Host smart-7381c774-bbfc-4a5a-945f-54f4d04c16c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139056245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2139056245
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.3964407238
Short name T437
Test name
Test status
Simulation time 341141275038 ps
CPU time 673.97 seconds
Started Jul 09 04:36:07 PM PDT 24
Finished Jul 09 04:47:21 PM PDT 24
Peak memory 191144 kb
Host smart-742f3885-82fe-4d8d-a17b-d5c7372ed3f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964407238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3964407238
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2744601080
Short name T278
Test name
Test status
Simulation time 82703926950 ps
CPU time 692.37 seconds
Started Jul 09 04:36:10 PM PDT 24
Finished Jul 09 04:47:43 PM PDT 24
Peak memory 194732 kb
Host smart-b2fee8dd-507b-44f1-b9b1-8e3d0eccbc66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744601080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2744601080
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3868425213
Short name T291
Test name
Test status
Simulation time 270519438842 ps
CPU time 191.97 seconds
Started Jul 09 04:36:20 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 194420 kb
Host smart-c1a0a4fb-809b-45dd-9313-51672a59dab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868425213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3868425213
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.976008126
Short name T283
Test name
Test status
Simulation time 159748455422 ps
CPU time 234.88 seconds
Started Jul 09 04:36:26 PM PDT 24
Finished Jul 09 04:40:22 PM PDT 24
Peak memory 191124 kb
Host smart-b4d35405-d1cd-4712-9d99-b7693b1a6c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976008126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.976008126
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1128909735
Short name T232
Test name
Test status
Simulation time 174631932377 ps
CPU time 999.29 seconds
Started Jul 09 04:36:31 PM PDT 24
Finished Jul 09 04:53:11 PM PDT 24
Peak memory 191172 kb
Host smart-4caf1d65-0f38-4268-9a97-9437ba0799fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128909735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1128909735
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.1552363587
Short name T105
Test name
Test status
Simulation time 212380642796 ps
CPU time 1143.36 seconds
Started Jul 09 04:35:32 PM PDT 24
Finished Jul 09 04:54:37 PM PDT 24
Peak memory 191192 kb
Host smart-c1905607-6dcf-413f-a527-7232369b67a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552363587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1552363587
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1337990911
Short name T281
Test name
Test status
Simulation time 1349920885152 ps
CPU time 1576.29 seconds
Started Jul 09 04:35:30 PM PDT 24
Finished Jul 09 05:01:49 PM PDT 24
Peak memory 191200 kb
Host smart-77908e35-e7a0-47b6-8dea-ff5da7efe494
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337990911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1337990911
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_random.3450902586
Short name T280
Test name
Test status
Simulation time 414485325621 ps
CPU time 1533.13 seconds
Started Jul 09 04:35:36 PM PDT 24
Finished Jul 09 05:01:10 PM PDT 24
Peak memory 191168 kb
Host smart-712fe6d0-b76a-4274-a112-0e06cb92fcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450902586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3450902586
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random.2552918757
Short name T313
Test name
Test status
Simulation time 348565701329 ps
CPU time 192.34 seconds
Started Jul 09 04:36:52 PM PDT 24
Finished Jul 09 04:40:05 PM PDT 24
Peak memory 190992 kb
Host smart-ea114fa4-c1ff-42af-8e56-2aeab6690062
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552918757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2552918757
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.189189624
Short name T110
Test name
Test status
Simulation time 47028754468 ps
CPU time 1423.64 seconds
Started Jul 09 04:35:52 PM PDT 24
Finished Jul 09 04:59:37 PM PDT 24
Peak memory 191196 kb
Host smart-eaf23d55-5025-464b-b534-ec57dfb182e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189189624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.189189624
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.31866343
Short name T166
Test name
Test status
Simulation time 369443289924 ps
CPU time 732.33 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:48:10 PM PDT 24
Peak memory 191136 kb
Host smart-8793ff94-2442-4749-92bd-b1fd835cee97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31866343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.31866343
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/57.rv_timer_random.5669208
Short name T241
Test name
Test status
Simulation time 778496190222 ps
CPU time 390.39 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:42:29 PM PDT 24
Peak memory 191180 kb
Host smart-d2acb94a-366f-4f40-a32a-d692bab8b75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5669208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.5669208
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.4087490366
Short name T117
Test name
Test status
Simulation time 167166648955 ps
CPU time 260.87 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:40:22 PM PDT 24
Peak memory 191284 kb
Host smart-29beb6c8-b997-42d3-a139-787d29e17817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087490366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.4087490366
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.1283150216
Short name T195
Test name
Test status
Simulation time 631493699027 ps
CPU time 657.04 seconds
Started Jul 09 04:36:03 PM PDT 24
Finished Jul 09 04:47:01 PM PDT 24
Peak memory 191196 kb
Host smart-3453b5d7-553b-4261-a9d4-31a8aeeb605f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283150216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.1283150216
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2470783515
Short name T72
Test name
Test status
Simulation time 26936375 ps
CPU time 0.7 seconds
Started Jul 09 04:27:06 PM PDT 24
Finished Jul 09 04:27:11 PM PDT 24
Peak memory 191744 kb
Host smart-3a47fe61-d5b0-4447-a653-bd1b106974a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470783515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2470783515
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.201650478
Short name T67
Test name
Test status
Simulation time 65049023 ps
CPU time 2.24 seconds
Started Jul 09 04:24:49 PM PDT 24
Finished Jul 09 04:24:52 PM PDT 24
Peak memory 190560 kb
Host smart-2968b28e-5f09-41a9-92a4-9f0c14103665
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201650478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.201650478
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/124.rv_timer_random.3131841489
Short name T268
Test name
Test status
Simulation time 118427624842 ps
CPU time 203.41 seconds
Started Jul 09 04:36:13 PM PDT 24
Finished Jul 09 04:39:37 PM PDT 24
Peak memory 191248 kb
Host smart-5cad367a-a41f-4edf-92c1-1136c50a4e62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131841489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3131841489
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1274182255
Short name T318
Test name
Test status
Simulation time 889009615779 ps
CPU time 400.84 seconds
Started Jul 09 04:36:13 PM PDT 24
Finished Jul 09 04:42:55 PM PDT 24
Peak memory 191236 kb
Host smart-d42b5b61-9d17-4174-a77b-7b1da1aa82df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274182255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1274182255
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3700691783
Short name T225
Test name
Test status
Simulation time 239843964774 ps
CPU time 277.19 seconds
Started Jul 09 04:36:13 PM PDT 24
Finished Jul 09 04:40:51 PM PDT 24
Peak memory 191176 kb
Host smart-2eee235e-67b4-46c3-8179-1721a54d045b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700691783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3700691783
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.611966513
Short name T238
Test name
Test status
Simulation time 376324434491 ps
CPU time 3155.42 seconds
Started Jul 09 04:36:20 PM PDT 24
Finished Jul 09 05:28:57 PM PDT 24
Peak memory 191164 kb
Host smart-8ef1b355-5447-414b-970c-bd76f191ba72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611966513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.611966513
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.869951443
Short name T184
Test name
Test status
Simulation time 285935411375 ps
CPU time 236.62 seconds
Started Jul 09 04:36:28 PM PDT 24
Finished Jul 09 04:40:26 PM PDT 24
Peak memory 191204 kb
Host smart-d9bdab2c-7b76-4382-8551-11f4562f6aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869951443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.869951443
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2483349205
Short name T8
Test name
Test status
Simulation time 386247923137 ps
CPU time 152.6 seconds
Started Jul 09 04:36:29 PM PDT 24
Finished Jul 09 04:39:03 PM PDT 24
Peak memory 194556 kb
Host smart-0ca7855a-c357-4e8e-8d65-a09381051ff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483349205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2483349205
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1036157035
Short name T107
Test name
Test status
Simulation time 83203343021 ps
CPU time 1290.45 seconds
Started Jul 09 04:36:29 PM PDT 24
Finished Jul 09 04:58:00 PM PDT 24
Peak memory 191164 kb
Host smart-33b46a2c-b009-488e-a9e5-74107893eb8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036157035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1036157035
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.289500966
Short name T204
Test name
Test status
Simulation time 196828749787 ps
CPU time 308.79 seconds
Started Jul 09 04:36:31 PM PDT 24
Finished Jul 09 04:41:40 PM PDT 24
Peak memory 191152 kb
Host smart-8782ae43-6672-439a-8fdb-3ed8d0412313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289500966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.289500966
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2899407371
Short name T321
Test name
Test status
Simulation time 3914756237641 ps
CPU time 1076.59 seconds
Started Jul 09 04:35:33 PM PDT 24
Finished Jul 09 04:53:31 PM PDT 24
Peak memory 182964 kb
Host smart-ab303535-dcd2-44c9-b2f2-4947e7ffac9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899407371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2899407371
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/51.rv_timer_random.1647974974
Short name T316
Test name
Test status
Simulation time 261047932150 ps
CPU time 139.7 seconds
Started Jul 09 04:36:13 PM PDT 24
Finished Jul 09 04:38:33 PM PDT 24
Peak memory 191192 kb
Host smart-f00d9ff2-057c-4b9f-9ffb-fbd6f46a96f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647974974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1647974974
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1166684926
Short name T211
Test name
Test status
Simulation time 100979304579 ps
CPU time 2189.97 seconds
Started Jul 09 04:36:16 PM PDT 24
Finished Jul 09 05:12:46 PM PDT 24
Peak memory 191116 kb
Host smart-1a1b5047-2a31-4316-ace4-3e96b87059a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166684926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1166684926
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2417043290
Short name T160
Test name
Test status
Simulation time 290449028651 ps
CPU time 769.47 seconds
Started Jul 09 04:36:00 PM PDT 24
Finished Jul 09 04:48:51 PM PDT 24
Peak memory 191240 kb
Host smart-1885dba7-c6a1-4c21-87d0-326367330be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417043290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2417043290
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2852832387
Short name T82
Test name
Test status
Simulation time 485618375 ps
CPU time 1.29 seconds
Started Jul 09 04:36:44 PM PDT 24
Finished Jul 09 04:36:45 PM PDT 24
Peak memory 182520 kb
Host smart-cc75ded0-5710-4977-8c76-6f74769282a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852832387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2852832387
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2314301011
Short name T216
Test name
Test status
Simulation time 575102086720 ps
CPU time 639.96 seconds
Started Jul 09 04:23:14 PM PDT 24
Finished Jul 09 04:33:55 PM PDT 24
Peak memory 183060 kb
Host smart-2da5f132-10a6-41b9-930e-9518a57be3cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314301011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2314301011
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/105.rv_timer_random.709180155
Short name T431
Test name
Test status
Simulation time 1053074201276 ps
CPU time 983.58 seconds
Started Jul 09 04:36:14 PM PDT 24
Finished Jul 09 04:52:38 PM PDT 24
Peak memory 191204 kb
Host smart-4e50ba90-277a-4cba-893a-833b906d373e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709180155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.709180155
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2124704402
Short name T250
Test name
Test status
Simulation time 204216361718 ps
CPU time 97.93 seconds
Started Jul 09 04:36:13 PM PDT 24
Finished Jul 09 04:37:52 PM PDT 24
Peak memory 191176 kb
Host smart-f4c62e76-ba86-468d-a10a-e1b3f4c981a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124704402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2124704402
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.169705000
Short name T158
Test name
Test status
Simulation time 183368017787 ps
CPU time 206.6 seconds
Started Jul 09 04:35:25 PM PDT 24
Finished Jul 09 04:38:52 PM PDT 24
Peak memory 194556 kb
Host smart-3d6b48c7-0502-4db4-bd9f-5cf1a4f04826
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169705000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.169705000
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.3718453387
Short name T134
Test name
Test status
Simulation time 221244015472 ps
CPU time 380.27 seconds
Started Jul 09 04:36:14 PM PDT 24
Finished Jul 09 04:42:35 PM PDT 24
Peak memory 191204 kb
Host smart-7b0d75ff-dd55-4d8f-8146-09815fba1fb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718453387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3718453387
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4135512558
Short name T308
Test name
Test status
Simulation time 529219764467 ps
CPU time 235.23 seconds
Started Jul 09 04:36:14 PM PDT 24
Finished Jul 09 04:40:10 PM PDT 24
Peak memory 191164 kb
Host smart-d20a18b8-7556-4330-a8ef-5fd3aea2af34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135512558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4135512558
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.821269122
Short name T326
Test name
Test status
Simulation time 11397256137 ps
CPU time 86.86 seconds
Started Jul 09 04:35:32 PM PDT 24
Finished Jul 09 04:37:00 PM PDT 24
Peak memory 182952 kb
Host smart-2a7ad621-0983-4f6c-89ed-13ad2b39b528
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821269122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.821269122
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2627721928
Short name T258
Test name
Test status
Simulation time 72347832255 ps
CPU time 87.59 seconds
Started Jul 09 04:35:30 PM PDT 24
Finished Jul 09 04:37:00 PM PDT 24
Peak memory 191304 kb
Host smart-333cb816-5c8c-4d58-a34b-d9c77cd0d5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627721928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2627721928
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/154.rv_timer_random.4013246608
Short name T183
Test name
Test status
Simulation time 365212432853 ps
CPU time 436.49 seconds
Started Jul 09 04:36:25 PM PDT 24
Finished Jul 09 04:43:43 PM PDT 24
Peak memory 191184 kb
Host smart-061dcf5a-1d20-441d-949d-a5cb3252ab33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013246608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.4013246608
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4181245613
Short name T128
Test name
Test status
Simulation time 92145315586 ps
CPU time 524.07 seconds
Started Jul 09 04:36:29 PM PDT 24
Finished Jul 09 04:45:14 PM PDT 24
Peak memory 191200 kb
Host smart-4782cbb9-d0eb-4553-a4e0-b6709a506e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181245613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4181245613
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2427024321
Short name T167
Test name
Test status
Simulation time 129962399602 ps
CPU time 109.61 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:37:20 PM PDT 24
Peak memory 182932 kb
Host smart-9d26be25-1e5d-4dfe-b133-b37deaebf2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427024321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2427024321
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/199.rv_timer_random.2774134166
Short name T43
Test name
Test status
Simulation time 297376693903 ps
CPU time 653.19 seconds
Started Jul 09 04:36:40 PM PDT 24
Finished Jul 09 04:47:34 PM PDT 24
Peak memory 182984 kb
Host smart-7860d4b3-9ffd-472d-9b3b-3ed357e8ef2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774134166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2774134166
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3855181566
Short name T317
Test name
Test status
Simulation time 13511040321 ps
CPU time 20.06 seconds
Started Jul 09 04:35:38 PM PDT 24
Finished Jul 09 04:35:59 PM PDT 24
Peak memory 182952 kb
Host smart-ebe84fbc-9b53-462e-ad29-a4ad1a6f309b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855181566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3855181566
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.1839564973
Short name T208
Test name
Test status
Simulation time 468912176803 ps
CPU time 3186.62 seconds
Started Jul 09 04:35:38 PM PDT 24
Finished Jul 09 05:28:46 PM PDT 24
Peak memory 191268 kb
Host smart-3b743f9c-df0b-48ae-97a5-cc7a2766bead
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839564973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.1839564973
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2864631484
Short name T103
Test name
Test status
Simulation time 197823468065 ps
CPU time 159.24 seconds
Started Jul 09 04:35:49 PM PDT 24
Finished Jul 09 04:38:29 PM PDT 24
Peak memory 191196 kb
Host smart-04c613a1-d8f5-4f31-a63a-33ecba8ab54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864631484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2864631484
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.2258071521
Short name T24
Test name
Test status
Simulation time 184306124495 ps
CPU time 249.1 seconds
Started Jul 09 04:35:42 PM PDT 24
Finished Jul 09 04:39:51 PM PDT 24
Peak memory 183016 kb
Host smart-7d16ae20-4cab-4367-aecf-934021b51d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258071521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.2258071521
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1002057523
Short name T348
Test name
Test status
Simulation time 10744132980 ps
CPU time 16.47 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:36:15 PM PDT 24
Peak memory 183064 kb
Host smart-f8bcab49-424d-4f98-ae2a-67f555f7284b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002057523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1002057523
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_random.3933652955
Short name T236
Test name
Test status
Simulation time 257743197861 ps
CPU time 650.89 seconds
Started Jul 09 04:35:50 PM PDT 24
Finished Jul 09 04:46:42 PM PDT 24
Peak memory 191124 kb
Host smart-8c57d2d0-7dd0-43c4-a648-581504a7782b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933652955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3933652955
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1914021967
Short name T310
Test name
Test status
Simulation time 54977743401 ps
CPU time 86.87 seconds
Started Jul 09 04:35:53 PM PDT 24
Finished Jul 09 04:37:21 PM PDT 24
Peak memory 182928 kb
Host smart-662ebd1c-8341-474d-90c7-06e95d39640c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914021967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1914021967
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/55.rv_timer_random.1668773639
Short name T328
Test name
Test status
Simulation time 1662117702210 ps
CPU time 496.7 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:44:17 PM PDT 24
Peak memory 191116 kb
Host smart-2f6ec6db-1463-4936-be6e-45cd649bf6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668773639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1668773639
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.1793754362
Short name T345
Test name
Test status
Simulation time 90687555696 ps
CPU time 132.12 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 191204 kb
Host smart-e21148b6-9120-4c1c-b035-46bf5bb50b59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793754362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1793754362
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4198691833
Short name T171
Test name
Test status
Simulation time 87015298570 ps
CPU time 144.32 seconds
Started Jul 09 04:36:11 PM PDT 24
Finished Jul 09 04:38:36 PM PDT 24
Peak memory 191156 kb
Host smart-7d18f097-f777-4d69-95ca-f2ad85ed1d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198691833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4198691833
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.403618135
Short name T532
Test name
Test status
Simulation time 308442674 ps
CPU time 1.45 seconds
Started Jul 09 04:27:22 PM PDT 24
Finished Jul 09 04:27:27 PM PDT 24
Peak memory 190428 kb
Host smart-5662a1b4-1e3d-41fc-8c1b-c6bc6f7d2ac5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403618135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.403618135
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3572997562
Short name T558
Test name
Test status
Simulation time 18628868 ps
CPU time 0.56 seconds
Started Jul 09 04:27:44 PM PDT 24
Finished Jul 09 04:27:45 PM PDT 24
Peak memory 182092 kb
Host smart-89817e0b-b149-4669-904f-3afed5a5b7e0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572997562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3572997562
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.1444206598
Short name T461
Test name
Test status
Simulation time 105134057 ps
CPU time 1.4 seconds
Started Jul 09 04:25:09 PM PDT 24
Finished Jul 09 04:25:11 PM PDT 24
Peak memory 197268 kb
Host smart-294897a7-b34c-4ef6-8d7b-3cc326b4dcad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444206598 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.1444206598
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1244747925
Short name T549
Test name
Test status
Simulation time 19373102 ps
CPU time 0.59 seconds
Started Jul 09 04:24:06 PM PDT 24
Finished Jul 09 04:24:07 PM PDT 24
Peak memory 182204 kb
Host smart-f16227a9-3e0a-488c-80e1-2eb91fed3528
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244747925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1244747925
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2831495693
Short name T537
Test name
Test status
Simulation time 31607436 ps
CPU time 0.55 seconds
Started Jul 09 04:26:27 PM PDT 24
Finished Jul 09 04:26:28 PM PDT 24
Peak memory 181520 kb
Host smart-e180b613-9d20-4ace-a1d0-59039a13f105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831495693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2831495693
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.949488308
Short name T494
Test name
Test status
Simulation time 79718593 ps
CPU time 1.04 seconds
Started Jul 09 04:28:17 PM PDT 24
Finished Jul 09 04:28:21 PM PDT 24
Peak memory 195748 kb
Host smart-54231ba8-0f13-456e-844d-c95445eee793
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949488308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.949488308
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2170273565
Short name T547
Test name
Test status
Simulation time 169610074 ps
CPU time 0.77 seconds
Started Jul 09 04:26:54 PM PDT 24
Finished Jul 09 04:27:01 PM PDT 24
Peak memory 192912 kb
Host smart-65fc8a87-e9bc-4681-b0d9-7db804126047
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170273565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2170273565
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.904439266
Short name T570
Test name
Test status
Simulation time 153806623 ps
CPU time 0.69 seconds
Started Jul 09 04:26:40 PM PDT 24
Finished Jul 09 04:26:44 PM PDT 24
Peak memory 181468 kb
Host smart-2b6ee143-4e6c-419c-829c-840b39efd440
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904439266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.904439266
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.879097398
Short name T485
Test name
Test status
Simulation time 18314806 ps
CPU time 0.55 seconds
Started Jul 09 04:27:09 PM PDT 24
Finished Jul 09 04:27:16 PM PDT 24
Peak memory 181968 kb
Host smart-1334c6a5-2655-4b6e-a1ae-e47f2d302ae9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879097398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.879097398
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3850364598
Short name T477
Test name
Test status
Simulation time 21385754 ps
CPU time 0.63 seconds
Started Jul 09 04:27:32 PM PDT 24
Finished Jul 09 04:27:39 PM PDT 24
Peak memory 193056 kb
Host smart-dfd21045-4312-4703-b09d-7c982538995f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850364598 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3850364598
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.638809438
Short name T65
Test name
Test status
Simulation time 39415004 ps
CPU time 0.57 seconds
Started Jul 09 04:25:40 PM PDT 24
Finished Jul 09 04:25:41 PM PDT 24
Peak memory 182252 kb
Host smart-5904b088-e622-46dd-9798-0a7979c2a32c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638809438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.638809438
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.2979877791
Short name T447
Test name
Test status
Simulation time 28871130 ps
CPU time 0.53 seconds
Started Jul 09 04:27:17 PM PDT 24
Finished Jul 09 04:27:21 PM PDT 24
Peak memory 181972 kb
Host smart-79861df5-a92c-4479-b86d-0ecd9af7e0e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979877791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.2979877791
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.585910390
Short name T502
Test name
Test status
Simulation time 101829258 ps
CPU time 0.62 seconds
Started Jul 09 04:26:37 PM PDT 24
Finished Jul 09 04:26:38 PM PDT 24
Peak memory 189680 kb
Host smart-e05cbfa3-ca28-42aa-a97d-031c5e3e6fe8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585910390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.585910390
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.459991996
Short name T512
Test name
Test status
Simulation time 67438543 ps
CPU time 1.02 seconds
Started Jul 09 04:27:17 PM PDT 24
Finished Jul 09 04:27:22 PM PDT 24
Peak memory 196692 kb
Host smart-9447f9a6-d53b-4dad-b207-a4894dbf0f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459991996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.459991996
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2533059376
Short name T573
Test name
Test status
Simulation time 158119196 ps
CPU time 1.08 seconds
Started Jul 09 04:27:01 PM PDT 24
Finished Jul 09 04:27:08 PM PDT 24
Peak memory 192884 kb
Host smart-cbd3783c-2d51-47e1-8c79-a317f3c252fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533059376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2533059376
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.145240295
Short name T455
Test name
Test status
Simulation time 98755836 ps
CPU time 1.09 seconds
Started Jul 09 04:35:07 PM PDT 24
Finished Jul 09 04:35:10 PM PDT 24
Peak memory 196888 kb
Host smart-a92e573e-57d5-43f4-b445-42a4ac59b575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145240295 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.145240295
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.724421645
Short name T511
Test name
Test status
Simulation time 19841394 ps
CPU time 0.59 seconds
Started Jul 09 04:35:16 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 182164 kb
Host smart-59e420ff-b309-4c41-b5bf-c5358fc3e1a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724421645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.724421645
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1860657677
Short name T505
Test name
Test status
Simulation time 40757401 ps
CPU time 0.55 seconds
Started Jul 09 04:35:15 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 182088 kb
Host smart-92abbad2-7dd2-4482-8e60-a0817c41faec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860657677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1860657677
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2230729176
Short name T510
Test name
Test status
Simulation time 25590143 ps
CPU time 0.69 seconds
Started Jul 09 04:35:13 PM PDT 24
Finished Jul 09 04:35:15 PM PDT 24
Peak memory 191112 kb
Host smart-c0c33921-09ec-41ed-bea1-9f5eaed359df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230729176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2230729176
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1817513735
Short name T538
Test name
Test status
Simulation time 189871476 ps
CPU time 1.85 seconds
Started Jul 09 04:36:22 PM PDT 24
Finished Jul 09 04:36:25 PM PDT 24
Peak memory 195144 kb
Host smart-3d0b79a9-3bd7-4bbd-8e87-a69d150037d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817513735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1817513735
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.4256735487
Short name T545
Test name
Test status
Simulation time 74784433 ps
CPU time 0.71 seconds
Started Jul 09 04:35:05 PM PDT 24
Finished Jul 09 04:35:06 PM PDT 24
Peak memory 194332 kb
Host smart-7d42c8b1-c847-4774-986a-3e8e2f0f7295
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256735487 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.4256735487
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.332962630
Short name T32
Test name
Test status
Simulation time 17109911 ps
CPU time 0.63 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 182148 kb
Host smart-8d364ede-82a4-4aba-8cc4-a58b5d3db813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332962630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.332962630
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3347787866
Short name T530
Test name
Test status
Simulation time 17616258 ps
CPU time 0.53 seconds
Started Jul 09 04:36:47 PM PDT 24
Finished Jul 09 04:36:48 PM PDT 24
Peak memory 181912 kb
Host smart-3cea264e-5d6a-4e6c-a174-35c01a8c80d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347787866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3347787866
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2261807526
Short name T503
Test name
Test status
Simulation time 14612912 ps
CPU time 0.61 seconds
Started Jul 09 04:35:08 PM PDT 24
Finished Jul 09 04:35:11 PM PDT 24
Peak memory 191000 kb
Host smart-33c1220f-d8f9-446d-a58b-5975f3a15523
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261807526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2261807526
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.4097147271
Short name T460
Test name
Test status
Simulation time 346751937 ps
CPU time 2.67 seconds
Started Jul 09 04:36:43 PM PDT 24
Finished Jul 09 04:36:46 PM PDT 24
Peak memory 196828 kb
Host smart-a21fdcf2-8db0-4511-b086-197656b0cd9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097147271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.4097147271
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2684100042
Short name T560
Test name
Test status
Simulation time 50525059 ps
CPU time 0.62 seconds
Started Jul 09 04:35:08 PM PDT 24
Finished Jul 09 04:35:10 PM PDT 24
Peak memory 193836 kb
Host smart-ce93b2fa-b149-48ba-a94d-0e98be8615dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684100042 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2684100042
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2439216265
Short name T64
Test name
Test status
Simulation time 13513832 ps
CPU time 0.58 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 182460 kb
Host smart-cf9a2225-02af-42b7-9adc-80c6da708663
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439216265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2439216265
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1731279232
Short name T520
Test name
Test status
Simulation time 45388785 ps
CPU time 0.56 seconds
Started Jul 09 04:35:14 PM PDT 24
Finished Jul 09 04:35:16 PM PDT 24
Peak memory 182008 kb
Host smart-5cc45a10-6b27-4e69-b7f0-6d3f53fe7da6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731279232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1731279232
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2288400777
Short name T77
Test name
Test status
Simulation time 129948106 ps
CPU time 0.61 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 190600 kb
Host smart-8eee4e69-83d1-4fd7-ba45-6ae28ee647ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288400777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2288400777
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.4083675278
Short name T49
Test name
Test status
Simulation time 207271004 ps
CPU time 2.26 seconds
Started Jul 09 04:35:13 PM PDT 24
Finished Jul 09 04:35:17 PM PDT 24
Peak memory 197384 kb
Host smart-8c5b871f-a480-409c-bad3-37ca1b84d9f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083675278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.4083675278
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2483170728
Short name T465
Test name
Test status
Simulation time 198622882 ps
CPU time 1.31 seconds
Started Jul 09 04:35:07 PM PDT 24
Finished Jul 09 04:35:10 PM PDT 24
Peak memory 182624 kb
Host smart-032d2d5b-a83b-494a-a4ca-5814fd9f8cb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483170728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2483170728
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.630170615
Short name T462
Test name
Test status
Simulation time 96252852 ps
CPU time 0.93 seconds
Started Jul 09 04:35:11 PM PDT 24
Finished Jul 09 04:35:14 PM PDT 24
Peak memory 196812 kb
Host smart-6994bb19-193c-4716-9bad-5632f6fd1f75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630170615 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.630170615
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.979078322
Short name T542
Test name
Test status
Simulation time 35323126 ps
CPU time 0.59 seconds
Started Jul 09 04:35:08 PM PDT 24
Finished Jul 09 04:35:10 PM PDT 24
Peak memory 182164 kb
Host smart-402f82de-2b52-4b79-83e4-1415fe2539df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979078322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.979078322
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.4010276936
Short name T528
Test name
Test status
Simulation time 36415269 ps
CPU time 0.53 seconds
Started Jul 09 04:35:12 PM PDT 24
Finished Jul 09 04:35:15 PM PDT 24
Peak memory 181728 kb
Host smart-dc39b358-ce05-4e49-81c5-58eb12455d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010276936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.4010276936
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1787128399
Short name T535
Test name
Test status
Simulation time 59533622 ps
CPU time 0.74 seconds
Started Jul 09 04:35:05 PM PDT 24
Finished Jul 09 04:35:07 PM PDT 24
Peak memory 192812 kb
Host smart-6cdbe680-d0db-4386-a32b-7c70f3de5bfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787128399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1787128399
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2808389033
Short name T524
Test name
Test status
Simulation time 499173657 ps
CPU time 2.03 seconds
Started Jul 09 04:35:06 PM PDT 24
Finished Jul 09 04:35:09 PM PDT 24
Peak memory 196892 kb
Host smart-09b8f11f-eb2b-48ff-b1c0-823615dd4458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808389033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2808389033
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2094286828
Short name T81
Test name
Test status
Simulation time 94622640 ps
CPU time 1.04 seconds
Started Jul 09 04:35:05 PM PDT 24
Finished Jul 09 04:35:07 PM PDT 24
Peak memory 194640 kb
Host smart-7a3432ed-97a1-442e-83c9-5e8cc2ad60eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094286828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2094286828
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3174847907
Short name T571
Test name
Test status
Simulation time 472532941 ps
CPU time 1.29 seconds
Started Jul 09 04:35:05 PM PDT 24
Finished Jul 09 04:35:08 PM PDT 24
Peak memory 196944 kb
Host smart-48ce91b2-74ac-4644-bc48-cf0c3527b991
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174847907 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3174847907
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3120585433
Short name T68
Test name
Test status
Simulation time 53285700 ps
CPU time 0.55 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 182148 kb
Host smart-8f40661c-be6d-4870-8c3f-16ef2eef9ad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120585433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3120585433
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1909065354
Short name T519
Test name
Test status
Simulation time 39591829 ps
CPU time 0.54 seconds
Started Jul 09 04:35:06 PM PDT 24
Finished Jul 09 04:35:08 PM PDT 24
Peak memory 182148 kb
Host smart-152ed2d2-9fc1-4f87-8d29-1c0958b92d0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909065354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1909065354
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3105400470
Short name T60
Test name
Test status
Simulation time 33014240 ps
CPU time 0.82 seconds
Started Jul 09 04:35:23 PM PDT 24
Finished Jul 09 04:35:25 PM PDT 24
Peak memory 191516 kb
Host smart-17216814-3b77-43e4-9c8a-7ad1bc8827d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105400470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3105400470
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3984848364
Short name T492
Test name
Test status
Simulation time 697315357 ps
CPU time 2.58 seconds
Started Jul 09 04:35:27 PM PDT 24
Finished Jul 09 04:35:31 PM PDT 24
Peak memory 196920 kb
Host smart-85dfe0d8-b4fb-455e-bca7-b58bb56a4421
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984848364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3984848364
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2066513519
Short name T489
Test name
Test status
Simulation time 109556691 ps
CPU time 1.02 seconds
Started Jul 09 04:35:07 PM PDT 24
Finished Jul 09 04:35:09 PM PDT 24
Peak memory 182560 kb
Host smart-bbc26ed0-21f1-4e7e-bd9b-9a1a2a6fafa8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066513519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2066513519
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3053496803
Short name T508
Test name
Test status
Simulation time 20287586 ps
CPU time 0.68 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 193596 kb
Host smart-acc6a036-6b38-4100-a0a1-fbc27ef09e9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053496803 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3053496803
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.4120629678
Short name T540
Test name
Test status
Simulation time 16682468 ps
CPU time 0.55 seconds
Started Jul 09 04:35:05 PM PDT 24
Finished Jul 09 04:35:07 PM PDT 24
Peak memory 182168 kb
Host smart-77ce2038-514f-416f-9dd2-58d22b8d3276
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120629678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.4120629678
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3127000468
Short name T464
Test name
Test status
Simulation time 40045921 ps
CPU time 0.53 seconds
Started Jul 09 04:35:06 PM PDT 24
Finished Jul 09 04:35:08 PM PDT 24
Peak memory 181524 kb
Host smart-b99a5e15-d961-41b5-86f2-6ea08e5e000f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127000468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3127000468
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2981283066
Short name T541
Test name
Test status
Simulation time 19203745 ps
CPU time 0.6 seconds
Started Jul 09 04:35:12 PM PDT 24
Finished Jul 09 04:35:15 PM PDT 24
Peak memory 191384 kb
Host smart-898c5648-0b3a-47f3-a490-7b82672fc81c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981283066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2981283066
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4271389240
Short name T452
Test name
Test status
Simulation time 130962389 ps
CPU time 1.71 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:35:33 PM PDT 24
Peak memory 196576 kb
Host smart-206cf618-66d4-48bc-b8d3-fb03ae9d7f44
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271389240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4271389240
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3816675053
Short name T522
Test name
Test status
Simulation time 452142335 ps
CPU time 0.83 seconds
Started Jul 09 04:35:13 PM PDT 24
Finished Jul 09 04:35:16 PM PDT 24
Peak memory 192920 kb
Host smart-d3227893-8cc7-4bff-bf83-315e8dfaa1ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816675053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3816675053
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.4010020420
Short name T458
Test name
Test status
Simulation time 49363737 ps
CPU time 1.08 seconds
Started Jul 09 04:35:15 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 196888 kb
Host smart-c9f28190-af95-46d8-b673-d02b7eb1343c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010020420 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.4010020420
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1793477653
Short name T62
Test name
Test status
Simulation time 15282387 ps
CPU time 0.55 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:12 PM PDT 24
Peak memory 182116 kb
Host smart-321bd2a9-b022-45c1-88df-5ce5d7f9ac38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793477653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1793477653
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3902298452
Short name T450
Test name
Test status
Simulation time 14561025 ps
CPU time 0.52 seconds
Started Jul 09 04:35:12 PM PDT 24
Finished Jul 09 04:35:15 PM PDT 24
Peak memory 181488 kb
Host smart-6a68b375-b523-40c6-bfc3-89f883580179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902298452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3902298452
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.511828153
Short name T50
Test name
Test status
Simulation time 107769857 ps
CPU time 0.71 seconds
Started Jul 09 04:35:14 PM PDT 24
Finished Jul 09 04:35:16 PM PDT 24
Peak memory 191060 kb
Host smart-5a486884-5599-496b-a294-d8adc2e9871f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511828153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.511828153
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1640642066
Short name T501
Test name
Test status
Simulation time 68842281 ps
CPU time 1.99 seconds
Started Jul 09 04:35:12 PM PDT 24
Finished Jul 09 04:35:16 PM PDT 24
Peak memory 197024 kb
Host smart-eacd879b-fe41-45e5-93e5-ae18f78ef2db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640642066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1640642066
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2548004954
Short name T466
Test name
Test status
Simulation time 48174344 ps
CPU time 0.84 seconds
Started Jul 09 04:35:16 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 192700 kb
Host smart-3b626c35-3503-4a2c-b394-ff195d61e28e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548004954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2548004954
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3466089119
Short name T551
Test name
Test status
Simulation time 52941652 ps
CPU time 0.8 seconds
Started Jul 09 04:35:13 PM PDT 24
Finished Jul 09 04:35:16 PM PDT 24
Peak memory 194776 kb
Host smart-cb4689bb-aa2f-47d2-b050-03673255301e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466089119 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3466089119
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1089236089
Short name T559
Test name
Test status
Simulation time 15192924 ps
CPU time 0.54 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 181908 kb
Host smart-74b4dcde-1b60-4c00-bb9a-7a5ddaab90d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089236089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1089236089
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.351052835
Short name T493
Test name
Test status
Simulation time 53217826 ps
CPU time 0.51 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:11 PM PDT 24
Peak memory 181528 kb
Host smart-be6ad260-1cc6-4f99-993e-49fbaea84f9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351052835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.351052835
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2945519184
Short name T71
Test name
Test status
Simulation time 184324141 ps
CPU time 0.6 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:12 PM PDT 24
Peak memory 191320 kb
Host smart-9679ce15-053f-4ce7-b166-7314c58b3f73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945519184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2945519184
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2701484012
Short name T531
Test name
Test status
Simulation time 420198884 ps
CPU time 2.23 seconds
Started Jul 09 04:35:15 PM PDT 24
Finished Jul 09 04:35:19 PM PDT 24
Peak memory 196964 kb
Host smart-9021f594-1bf9-4408-8321-b4ce5c67e5a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701484012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2701484012
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2259816417
Short name T500
Test name
Test status
Simulation time 270009523 ps
CPU time 0.81 seconds
Started Jul 09 04:35:12 PM PDT 24
Finished Jul 09 04:35:15 PM PDT 24
Peak memory 193008 kb
Host smart-edb42a87-787f-4f8d-895c-265f8c0aa2cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259816417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2259816417
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1199219213
Short name T468
Test name
Test status
Simulation time 18527168 ps
CPU time 0.73 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 194344 kb
Host smart-82f454cc-46f2-491b-a1ea-543704f4e37d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199219213 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1199219213
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.553868739
Short name T63
Test name
Test status
Simulation time 12279408 ps
CPU time 0.61 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:12 PM PDT 24
Peak memory 182128 kb
Host smart-46f5b097-35b2-43c8-9704-7e36ab058eec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553868739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.553868739
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1527167041
Short name T474
Test name
Test status
Simulation time 11438865 ps
CPU time 0.52 seconds
Started Jul 09 04:35:22 PM PDT 24
Finished Jul 09 04:35:23 PM PDT 24
Peak memory 181720 kb
Host smart-9b628afb-6a14-4235-9e77-4ccd82180609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527167041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1527167041
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1643082897
Short name T57
Test name
Test status
Simulation time 54840822 ps
CPU time 0.77 seconds
Started Jul 09 04:35:21 PM PDT 24
Finished Jul 09 04:35:22 PM PDT 24
Peak memory 192908 kb
Host smart-7abf309e-fca9-4261-9c62-5b08c1eaeec6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643082897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1643082897
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1492330279
Short name T504
Test name
Test status
Simulation time 131388761 ps
CPU time 2.34 seconds
Started Jul 09 04:36:17 PM PDT 24
Finished Jul 09 04:36:21 PM PDT 24
Peak memory 196044 kb
Host smart-8e827daa-f76f-4930-8544-5098a2d3bf5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492330279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1492330279
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2940046437
Short name T557
Test name
Test status
Simulation time 92681077 ps
CPU time 0.8 seconds
Started Jul 09 04:35:14 PM PDT 24
Finished Jul 09 04:35:17 PM PDT 24
Peak memory 193304 kb
Host smart-74d6682b-3936-4ae8-97fe-a738f48c8e42
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940046437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2940046437
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.666629168
Short name T476
Test name
Test status
Simulation time 27521058 ps
CPU time 0.71 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:35:31 PM PDT 24
Peak memory 194508 kb
Host smart-1b5785a6-2742-4f47-a7ee-5131f1c76d3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666629168 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.666629168
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1627776640
Short name T78
Test name
Test status
Simulation time 38400400 ps
CPU time 0.53 seconds
Started Jul 09 04:35:14 PM PDT 24
Finished Jul 09 04:35:16 PM PDT 24
Peak memory 182180 kb
Host smart-9ebd1554-b8b2-498a-add1-76ebf1cf41ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627776640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1627776640
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.765859483
Short name T484
Test name
Test status
Simulation time 16066456 ps
CPU time 0.56 seconds
Started Jul 09 04:35:12 PM PDT 24
Finished Jul 09 04:35:15 PM PDT 24
Peak memory 182004 kb
Host smart-feea1117-56df-4dda-a359-67c930f4ae39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765859483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.765859483
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.444241160
Short name T523
Test name
Test status
Simulation time 65002139 ps
CPU time 0.83 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:12 PM PDT 24
Peak memory 192768 kb
Host smart-79d7a55a-ad80-45b0-b518-88080ae13ae3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444241160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.444241160
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.3599903806
Short name T536
Test name
Test status
Simulation time 94566312 ps
CPU time 1.26 seconds
Started Jul 09 04:36:22 PM PDT 24
Finished Jul 09 04:36:24 PM PDT 24
Peak memory 194124 kb
Host smart-30da4bbb-1df5-4ff1-a5fc-13804d71f3f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599903806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.3599903806
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1717527519
Short name T572
Test name
Test status
Simulation time 44229423 ps
CPU time 0.8 seconds
Started Jul 09 04:35:11 PM PDT 24
Finished Jul 09 04:35:15 PM PDT 24
Peak memory 193204 kb
Host smart-cb0e263d-0431-4725-8aff-ff359c8d66a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717527519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1717527519
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3558764544
Short name T61
Test name
Test status
Simulation time 17995809 ps
CPU time 0.8 seconds
Started Jul 09 04:24:47 PM PDT 24
Finished Jul 09 04:24:48 PM PDT 24
Peak memory 192392 kb
Host smart-f1d0fb75-fd92-43a1-9ae9-9ae4dedd12b0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558764544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3558764544
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1758879873
Short name T569
Test name
Test status
Simulation time 559444339 ps
CPU time 2.89 seconds
Started Jul 09 04:27:05 PM PDT 24
Finished Jul 09 04:27:13 PM PDT 24
Peak memory 191460 kb
Host smart-70a2b99e-69c1-47b8-a23b-2addcb418223
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758879873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1758879873
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2342825055
Short name T562
Test name
Test status
Simulation time 69976049 ps
CPU time 0.55 seconds
Started Jul 09 04:27:56 PM PDT 24
Finished Jul 09 04:27:58 PM PDT 24
Peak memory 182140 kb
Host smart-6aa4d4e3-5585-4d4f-94d5-91e8926a8647
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342825055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2342825055
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2762984450
Short name T471
Test name
Test status
Simulation time 51835256 ps
CPU time 0.76 seconds
Started Jul 09 04:26:51 PM PDT 24
Finished Jul 09 04:26:52 PM PDT 24
Peak memory 195472 kb
Host smart-d562eaa5-7ff3-4ec6-a175-4de352642a8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762984450 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2762984450
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3843980083
Short name T69
Test name
Test status
Simulation time 35994160 ps
CPU time 0.56 seconds
Started Jul 09 04:26:39 PM PDT 24
Finished Jul 09 04:26:41 PM PDT 24
Peak memory 181828 kb
Host smart-ff1cfa39-8086-43cc-8148-b8f38af3f3fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843980083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3843980083
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.3421389175
Short name T486
Test name
Test status
Simulation time 12416539 ps
CPU time 0.53 seconds
Started Jul 09 04:22:13 PM PDT 24
Finished Jul 09 04:22:14 PM PDT 24
Peak memory 181664 kb
Host smart-8aea2833-7e1f-4e52-82fe-98d1e6e973e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421389175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.3421389175
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2966831462
Short name T561
Test name
Test status
Simulation time 142212647 ps
CPU time 0.78 seconds
Started Jul 09 04:27:54 PM PDT 24
Finished Jul 09 04:27:56 PM PDT 24
Peak memory 191020 kb
Host smart-f1114b35-a047-476e-9cfb-c3c0d31524bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966831462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2966831462
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3094957154
Short name T469
Test name
Test status
Simulation time 96600071 ps
CPU time 2.31 seconds
Started Jul 09 04:25:52 PM PDT 24
Finished Jul 09 04:25:55 PM PDT 24
Peak memory 196916 kb
Host smart-f7c8de9f-124c-4b32-ab2e-db4cf98726be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094957154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3094957154
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2386373611
Short name T554
Test name
Test status
Simulation time 131919812 ps
CPU time 1.31 seconds
Started Jul 09 04:26:37 PM PDT 24
Finished Jul 09 04:26:39 PM PDT 24
Peak memory 193684 kb
Host smart-389bd0e3-8a45-4190-a85d-960e73651823
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386373611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2386373611
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.387104392
Short name T448
Test name
Test status
Simulation time 53242991 ps
CPU time 0.56 seconds
Started Jul 09 04:35:27 PM PDT 24
Finished Jul 09 04:35:29 PM PDT 24
Peak memory 182020 kb
Host smart-b90c915d-3b79-45be-a579-272ee2812027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387104392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.387104392
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.238444578
Short name T499
Test name
Test status
Simulation time 14858382 ps
CPU time 0.56 seconds
Started Jul 09 04:35:14 PM PDT 24
Finished Jul 09 04:35:17 PM PDT 24
Peak memory 182088 kb
Host smart-49c3c6cc-cf2c-4d90-9f8c-50fdf9e7faa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238444578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.238444578
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1595729931
Short name T470
Test name
Test status
Simulation time 26899872 ps
CPU time 0.55 seconds
Started Jul 09 04:35:16 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 182092 kb
Host smart-ffee5b3b-0539-4802-8f40-10b78f22c7d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595729931 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1595729931
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.293058939
Short name T482
Test name
Test status
Simulation time 31533857 ps
CPU time 0.51 seconds
Started Jul 09 04:35:29 PM PDT 24
Finished Jul 09 04:35:31 PM PDT 24
Peak memory 181512 kb
Host smart-d7e013b6-ca22-4f30-b763-e74e80aabd11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293058939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.293058939
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2315222394
Short name T566
Test name
Test status
Simulation time 47000547 ps
CPU time 0.53 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 181600 kb
Host smart-0834eddd-4413-45a8-befa-1ecd2393c170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315222394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2315222394
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4119696431
Short name T456
Test name
Test status
Simulation time 22772600 ps
CPU time 0.56 seconds
Started Jul 09 04:35:25 PM PDT 24
Finished Jul 09 04:35:26 PM PDT 24
Peak memory 182072 kb
Host smart-0bb9b77b-2a16-4d0e-9589-415d6cdcbc3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119696431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4119696431
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.424967077
Short name T565
Test name
Test status
Simulation time 57349615 ps
CPU time 0.58 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 182152 kb
Host smart-50b9c06a-e2d0-4d65-97cb-b43e8f43b27f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424967077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.424967077
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1731627540
Short name T550
Test name
Test status
Simulation time 32483680 ps
CPU time 0.51 seconds
Started Jul 09 04:35:15 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 181564 kb
Host smart-bb34b625-39a8-439d-a006-4d15ebb834d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731627540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1731627540
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3795057547
Short name T472
Test name
Test status
Simulation time 11101691 ps
CPU time 0.51 seconds
Started Jul 09 04:35:10 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 181980 kb
Host smart-23d16d89-f69c-4d9f-b863-241a4ba25d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795057547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3795057547
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1661153516
Short name T507
Test name
Test status
Simulation time 45129717 ps
CPU time 0.56 seconds
Started Jul 09 04:35:26 PM PDT 24
Finished Jul 09 04:35:28 PM PDT 24
Peak memory 182064 kb
Host smart-d2df3779-5d4c-457f-82be-28b8a96b488a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661153516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1661153516
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.643768171
Short name T534
Test name
Test status
Simulation time 35888951 ps
CPU time 0.83 seconds
Started Jul 09 04:27:18 PM PDT 24
Finished Jul 09 04:27:23 PM PDT 24
Peak memory 190284 kb
Host smart-948afa17-180c-4d89-8ac7-c2e0b620f8f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643768171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.643768171
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.877788301
Short name T66
Test name
Test status
Simulation time 176087049 ps
CPU time 3.17 seconds
Started Jul 09 04:27:20 PM PDT 24
Finished Jul 09 04:27:27 PM PDT 24
Peak memory 193356 kb
Host smart-dfd878c3-66a1-4696-b614-610e426cb1e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877788301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.877788301
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.112776680
Short name T70
Test name
Test status
Simulation time 67151894 ps
CPU time 0.66 seconds
Started Jul 09 04:26:36 PM PDT 24
Finished Jul 09 04:26:38 PM PDT 24
Peak memory 180772 kb
Host smart-febac7a0-bc73-4449-8ffd-e4affe026845
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112776680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.112776680
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2842736517
Short name T525
Test name
Test status
Simulation time 21396454 ps
CPU time 1.02 seconds
Started Jul 09 04:22:44 PM PDT 24
Finished Jul 09 04:22:46 PM PDT 24
Peak memory 196784 kb
Host smart-8b985472-99f0-4e3b-9bcf-1a554f6455af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842736517 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2842736517
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1780326896
Short name T563
Test name
Test status
Simulation time 30075773 ps
CPU time 0.56 seconds
Started Jul 09 04:27:20 PM PDT 24
Finished Jul 09 04:27:24 PM PDT 24
Peak memory 182140 kb
Host smart-4a3c644f-5567-4971-a94d-f06999042b13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780326896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1780326896
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2213354682
Short name T451
Test name
Test status
Simulation time 75230556 ps
CPU time 0.56 seconds
Started Jul 09 04:24:34 PM PDT 24
Finished Jul 09 04:24:35 PM PDT 24
Peak memory 182116 kb
Host smart-2d1d6e30-4b1a-4cdf-a037-a516b17517fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213354682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2213354682
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3001699582
Short name T74
Test name
Test status
Simulation time 17751974 ps
CPU time 0.61 seconds
Started Jul 09 04:27:10 PM PDT 24
Finished Jul 09 04:27:17 PM PDT 24
Peak memory 191420 kb
Host smart-d1c1ef40-dee9-451c-8586-8fe0b402306a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001699582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3001699582
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1189458371
Short name T39
Test name
Test status
Simulation time 324634313 ps
CPU time 2.55 seconds
Started Jul 09 04:24:33 PM PDT 24
Finished Jul 09 04:24:36 PM PDT 24
Peak memory 196880 kb
Host smart-bebf3472-5585-4ef8-977f-146091086cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189458371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1189458371
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2411769737
Short name T79
Test name
Test status
Simulation time 71116373 ps
CPU time 1.15 seconds
Started Jul 09 04:24:27 PM PDT 24
Finished Jul 09 04:24:29 PM PDT 24
Peak memory 193316 kb
Host smart-bb97dd3c-4468-4dc9-a934-34fff71434c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411769737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2411769737
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.877500381
Short name T459
Test name
Test status
Simulation time 48082609 ps
CPU time 0.57 seconds
Started Jul 09 04:35:26 PM PDT 24
Finished Jul 09 04:35:28 PM PDT 24
Peak memory 182088 kb
Host smart-12bb766a-3755-44dd-8b58-5e565e2a996c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877500381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.877500381
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2872889922
Short name T516
Test name
Test status
Simulation time 44620261 ps
CPU time 0.55 seconds
Started Jul 09 04:35:34 PM PDT 24
Finished Jul 09 04:35:35 PM PDT 24
Peak memory 182040 kb
Host smart-788cce36-e363-41b3-9379-a352b9ab1daa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872889922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2872889922
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3925647077
Short name T533
Test name
Test status
Simulation time 20920329 ps
CPU time 0.56 seconds
Started Jul 09 04:35:17 PM PDT 24
Finished Jul 09 04:35:19 PM PDT 24
Peak memory 182136 kb
Host smart-fde72620-6f67-4968-a467-96139a78d019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925647077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3925647077
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1568386094
Short name T449
Test name
Test status
Simulation time 116480062 ps
CPU time 0.56 seconds
Started Jul 09 04:35:27 PM PDT 24
Finished Jul 09 04:35:29 PM PDT 24
Peak memory 182156 kb
Host smart-df2c5574-6c88-490a-b466-bb537540cf3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568386094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1568386094
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.729029892
Short name T491
Test name
Test status
Simulation time 14083883 ps
CPU time 0.58 seconds
Started Jul 09 04:35:27 PM PDT 24
Finished Jul 09 04:35:28 PM PDT 24
Peak memory 182024 kb
Host smart-12471212-cc00-462c-be2a-ab525e70bb49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729029892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.729029892
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.566743810
Short name T546
Test name
Test status
Simulation time 14270676 ps
CPU time 0.54 seconds
Started Jul 09 04:35:27 PM PDT 24
Finished Jul 09 04:35:30 PM PDT 24
Peak memory 181584 kb
Host smart-83f209cb-2949-4c66-9ceb-0011d7d66023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566743810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.566743810
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3757652106
Short name T526
Test name
Test status
Simulation time 14470850 ps
CPU time 0.59 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:35:31 PM PDT 24
Peak memory 182028 kb
Host smart-c2bb7be9-3ec7-4762-91cc-819b190fe480
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757652106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3757652106
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3751816195
Short name T564
Test name
Test status
Simulation time 11906083 ps
CPU time 0.55 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:35:30 PM PDT 24
Peak memory 182088 kb
Host smart-e2548202-c59b-4f97-80f2-b1149041edc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751816195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3751816195
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.158021199
Short name T553
Test name
Test status
Simulation time 36536649 ps
CPU time 0.51 seconds
Started Jul 09 04:35:17 PM PDT 24
Finished Jul 09 04:35:19 PM PDT 24
Peak memory 181736 kb
Host smart-d071be28-0e22-4774-897c-f50ce5d03d27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158021199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.158021199
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.497088428
Short name T488
Test name
Test status
Simulation time 46001550 ps
CPU time 0.54 seconds
Started Jul 09 04:35:17 PM PDT 24
Finished Jul 09 04:35:19 PM PDT 24
Peak memory 181472 kb
Host smart-3eb80a9c-5d1d-4517-bd53-4bc143188048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497088428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.497088428
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.2853646381
Short name T497
Test name
Test status
Simulation time 23527828 ps
CPU time 0.72 seconds
Started Jul 09 04:35:08 PM PDT 24
Finished Jul 09 04:35:10 PM PDT 24
Peak memory 182272 kb
Host smart-20db6feb-5a0a-41a7-afd4-a17074822c5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853646381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.2853646381
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1428686495
Short name T480
Test name
Test status
Simulation time 101893429 ps
CPU time 1.57 seconds
Started Jul 09 04:35:00 PM PDT 24
Finished Jul 09 04:35:02 PM PDT 24
Peak memory 190500 kb
Host smart-bac7ffbb-fe37-478c-a098-e3084f2c4378
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428686495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1428686495
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1502301771
Short name T33
Test name
Test status
Simulation time 54484677 ps
CPU time 0.54 seconds
Started Jul 09 04:26:58 PM PDT 24
Finished Jul 09 04:27:04 PM PDT 24
Peak memory 182096 kb
Host smart-5a402e28-249d-46c7-8e43-f3c80c9ccf94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502301771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1502301771
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1656683961
Short name T555
Test name
Test status
Simulation time 17577150 ps
CPU time 0.89 seconds
Started Jul 09 04:35:07 PM PDT 24
Finished Jul 09 04:35:10 PM PDT 24
Peak memory 196716 kb
Host smart-ed576914-2d31-4a35-9b90-514ee45d5ca0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656683961 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1656683961
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.779162008
Short name T483
Test name
Test status
Simulation time 18950431 ps
CPU time 0.53 seconds
Started Jul 09 04:35:01 PM PDT 24
Finished Jul 09 04:35:02 PM PDT 24
Peak memory 182164 kb
Host smart-d8eb2b4c-1d46-43c3-944f-140a00a0e464
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779162008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.779162008
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1596637690
Short name T568
Test name
Test status
Simulation time 89860406 ps
CPU time 0.54 seconds
Started Jul 09 04:26:59 PM PDT 24
Finished Jul 09 04:27:05 PM PDT 24
Peak memory 181984 kb
Host smart-7f15ed82-2809-4613-9fe4-bae515da3a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596637690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1596637690
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.1229398789
Short name T515
Test name
Test status
Simulation time 99260026 ps
CPU time 0.7 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:12 PM PDT 24
Peak memory 191148 kb
Host smart-a130d3c0-1bcd-4d7b-ba6d-8af0a8577e17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229398789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.1229398789
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2366890929
Short name T496
Test name
Test status
Simulation time 52726448 ps
CPU time 1.06 seconds
Started Jul 09 04:27:04 PM PDT 24
Finished Jul 09 04:27:11 PM PDT 24
Peak memory 195856 kb
Host smart-e1141907-7c98-4134-90af-5ffb52688769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366890929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2366890929
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3974966895
Short name T80
Test name
Test status
Simulation time 132400941 ps
CPU time 1.13 seconds
Started Jul 09 04:26:55 PM PDT 24
Finished Jul 09 04:27:02 PM PDT 24
Peak memory 193728 kb
Host smart-7e88b62a-9e80-4024-bacd-79eb7e495650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974966895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3974966895
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1933884655
Short name T478
Test name
Test status
Simulation time 13813307 ps
CPU time 0.53 seconds
Started Jul 09 04:35:18 PM PDT 24
Finished Jul 09 04:35:20 PM PDT 24
Peak memory 181960 kb
Host smart-6c9571f6-b561-4694-9ce7-5ecc8c50681f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933884655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1933884655
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3452271826
Short name T517
Test name
Test status
Simulation time 45402290 ps
CPU time 0.56 seconds
Started Jul 09 04:35:21 PM PDT 24
Finished Jul 09 04:35:23 PM PDT 24
Peak memory 181516 kb
Host smart-00778efa-bd4a-42ec-937c-5a589189b02f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452271826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3452271826
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.890526936
Short name T479
Test name
Test status
Simulation time 25455646 ps
CPU time 0.55 seconds
Started Jul 09 04:35:29 PM PDT 24
Finished Jul 09 04:35:31 PM PDT 24
Peak memory 181960 kb
Host smart-88d101fa-46fb-4a65-b835-aa30a2a88714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890526936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.890526936
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2960361022
Short name T548
Test name
Test status
Simulation time 46824606 ps
CPU time 0.57 seconds
Started Jul 09 04:35:21 PM PDT 24
Finished Jul 09 04:35:22 PM PDT 24
Peak memory 182068 kb
Host smart-023a7f65-64ed-4c58-84f6-d591696e1090
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960361022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2960361022
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3899281668
Short name T527
Test name
Test status
Simulation time 45180954 ps
CPU time 0.55 seconds
Started Jul 09 04:35:23 PM PDT 24
Finished Jul 09 04:35:24 PM PDT 24
Peak memory 182032 kb
Host smart-8331d833-aa0d-4ef7-87ed-3aa839fb3483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899281668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3899281668
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3605149435
Short name T454
Test name
Test status
Simulation time 25140779 ps
CPU time 0.56 seconds
Started Jul 09 04:35:22 PM PDT 24
Finished Jul 09 04:35:23 PM PDT 24
Peak memory 182092 kb
Host smart-8d278684-edc9-4006-ba1d-53e6214b6186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605149435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3605149435
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3526776454
Short name T556
Test name
Test status
Simulation time 12281217 ps
CPU time 0.55 seconds
Started Jul 09 04:35:21 PM PDT 24
Finished Jul 09 04:35:22 PM PDT 24
Peak memory 182116 kb
Host smart-e6ca7139-d5f3-4c1a-92f6-70dc94bb0c03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526776454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3526776454
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.803622851
Short name T490
Test name
Test status
Simulation time 10824871 ps
CPU time 0.57 seconds
Started Jul 09 04:35:14 PM PDT 24
Finished Jul 09 04:35:17 PM PDT 24
Peak memory 181560 kb
Host smart-a0e69b63-0380-4e4d-8271-5fb6ba4c7cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803622851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.803622851
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1170294052
Short name T514
Test name
Test status
Simulation time 115033171 ps
CPU time 0.55 seconds
Started Jul 09 04:35:15 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 182060 kb
Host smart-43cc309b-1d63-4ac6-9d28-3afe8b8b0014
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170294052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1170294052
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.760211149
Short name T567
Test name
Test status
Simulation time 12226405 ps
CPU time 0.54 seconds
Started Jul 09 04:35:26 PM PDT 24
Finished Jul 09 04:35:27 PM PDT 24
Peak memory 181992 kb
Host smart-cf6092bf-9754-47f0-8633-b9bce2c73996
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760211149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.760211149
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.348306394
Short name T495
Test name
Test status
Simulation time 144940769 ps
CPU time 0.88 seconds
Started Jul 09 04:35:00 PM PDT 24
Finished Jul 09 04:35:01 PM PDT 24
Peak memory 196848 kb
Host smart-43d440d8-d313-4cb4-9a98-ce64ab3d5add
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348306394 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.348306394
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.964865784
Short name T481
Test name
Test status
Simulation time 20876154 ps
CPU time 0.59 seconds
Started Jul 09 04:35:07 PM PDT 24
Finished Jul 09 04:35:09 PM PDT 24
Peak memory 181936 kb
Host smart-fa339db1-d270-4a0e-be8b-5c723a3ad400
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964865784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.964865784
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.147453252
Short name T552
Test name
Test status
Simulation time 15564036 ps
CPU time 0.55 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:12 PM PDT 24
Peak memory 181976 kb
Host smart-ebd0f29d-84bc-4860-9d94-246b6faad83f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147453252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.147453252
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.356893910
Short name T76
Test name
Test status
Simulation time 19741123 ps
CPU time 0.63 seconds
Started Jul 09 04:35:14 PM PDT 24
Finished Jul 09 04:35:17 PM PDT 24
Peak memory 191488 kb
Host smart-f09b0536-f829-48ed-a194-acee5869b408
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356893910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_tim
er_same_csr_outstanding.356893910
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3186626126
Short name T487
Test name
Test status
Simulation time 592429080 ps
CPU time 2.71 seconds
Started Jul 09 04:35:11 PM PDT 24
Finished Jul 09 04:35:16 PM PDT 24
Peak memory 196980 kb
Host smart-d77ced0e-3797-45ef-a436-d0beda6cdd89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186626126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3186626126
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1942221429
Short name T83
Test name
Test status
Simulation time 452112950 ps
CPU time 1.34 seconds
Started Jul 09 04:35:03 PM PDT 24
Finished Jul 09 04:35:05 PM PDT 24
Peak memory 194800 kb
Host smart-9efc264e-4514-42bd-80ac-304d3d0ff0d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942221429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1942221429
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.4097030681
Short name T52
Test name
Test status
Simulation time 38787013 ps
CPU time 0.89 seconds
Started Jul 09 04:35:11 PM PDT 24
Finished Jul 09 04:35:15 PM PDT 24
Peak memory 196240 kb
Host smart-3805ab73-c939-48c4-9fc2-1f1f2f43b279
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097030681 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.4097030681
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.374768389
Short name T473
Test name
Test status
Simulation time 16832492 ps
CPU time 0.58 seconds
Started Jul 09 04:35:07 PM PDT 24
Finished Jul 09 04:35:09 PM PDT 24
Peak memory 182160 kb
Host smart-5de2e9c3-bf3a-40a2-b6cc-67f468f00caf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374768389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.374768389
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.200530063
Short name T543
Test name
Test status
Simulation time 108822455 ps
CPU time 0.53 seconds
Started Jul 09 04:35:03 PM PDT 24
Finished Jul 09 04:35:04 PM PDT 24
Peak memory 181932 kb
Host smart-7d43cde4-d888-422c-a87a-36989b7bcc8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200530063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.200530063
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.308655846
Short name T513
Test name
Test status
Simulation time 210124262 ps
CPU time 0.59 seconds
Started Jul 09 04:35:08 PM PDT 24
Finished Jul 09 04:35:10 PM PDT 24
Peak memory 191376 kb
Host smart-ce79f459-a1e7-400b-87f7-216eb9f918b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308655846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.308655846
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2528646319
Short name T498
Test name
Test status
Simulation time 180544246 ps
CPU time 3.38 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:15 PM PDT 24
Peak memory 196912 kb
Host smart-09ca2baa-71a4-4a1b-b543-e2a9f798d537
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528646319 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2528646319
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.3262897137
Short name T30
Test name
Test status
Simulation time 158165424 ps
CPU time 1.1 seconds
Started Jul 09 04:35:08 PM PDT 24
Finished Jul 09 04:35:11 PM PDT 24
Peak memory 194344 kb
Host smart-bf3d46a1-cedc-436c-9a09-69c78e5e385e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262897137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.3262897137
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2945928959
Short name T475
Test name
Test status
Simulation time 29160509 ps
CPU time 1.25 seconds
Started Jul 09 04:35:12 PM PDT 24
Finished Jul 09 04:35:16 PM PDT 24
Peak memory 196956 kb
Host smart-731726a6-20f1-426f-9c4e-8a516f808ffc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945928959 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2945928959
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.248270701
Short name T518
Test name
Test status
Simulation time 43395196 ps
CPU time 0.59 seconds
Started Jul 09 04:35:02 PM PDT 24
Finished Jul 09 04:35:03 PM PDT 24
Peak memory 182176 kb
Host smart-a512246a-0ce7-4b3a-beb0-d17458c6497f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248270701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.248270701
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.1647992923
Short name T521
Test name
Test status
Simulation time 11740487 ps
CPU time 0.55 seconds
Started Jul 09 04:35:08 PM PDT 24
Finished Jul 09 04:35:11 PM PDT 24
Peak memory 182084 kb
Host smart-e1a2eb99-18b8-415a-a30e-0de5c29381b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647992923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.1647992923
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3920405992
Short name T75
Test name
Test status
Simulation time 26869173 ps
CPU time 0.69 seconds
Started Jul 09 04:35:02 PM PDT 24
Finished Jul 09 04:35:03 PM PDT 24
Peak memory 192572 kb
Host smart-46a271b7-e239-41ee-be60-dcabcd93e483
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920405992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3920405992
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2723462732
Short name T544
Test name
Test status
Simulation time 398324424 ps
CPU time 2.24 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:13 PM PDT 24
Peak memory 196968 kb
Host smart-1d2bde84-84a0-46ae-a01a-a39fa7e9072f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723462732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2723462732
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1598443899
Short name T509
Test name
Test status
Simulation time 742541605 ps
CPU time 1.05 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:12 PM PDT 24
Peak memory 194716 kb
Host smart-b9e01919-fc26-4a79-a468-aa5a507007d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598443899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1598443899
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1018445920
Short name T529
Test name
Test status
Simulation time 57465594 ps
CPU time 1.48 seconds
Started Jul 09 04:35:07 PM PDT 24
Finished Jul 09 04:35:10 PM PDT 24
Peak memory 196952 kb
Host smart-f7bf76ce-d095-47f1-9538-78c8c983a588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018445920 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1018445920
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.2928523153
Short name T58
Test name
Test status
Simulation time 21971851 ps
CPU time 0.6 seconds
Started Jul 09 04:35:03 PM PDT 24
Finished Jul 09 04:35:04 PM PDT 24
Peak memory 182208 kb
Host smart-9695ca79-eed4-4757-9e1f-5e17bc4510b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928523153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.2928523153
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1729025512
Short name T453
Test name
Test status
Simulation time 14152006 ps
CPU time 0.59 seconds
Started Jul 09 04:35:01 PM PDT 24
Finished Jul 09 04:35:02 PM PDT 24
Peak memory 182068 kb
Host smart-39f71cd1-8e37-4d5c-9c0d-f24cbc444481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729025512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1729025512
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.4112932061
Short name T539
Test name
Test status
Simulation time 32240337 ps
CPU time 0.6 seconds
Started Jul 09 04:35:06 PM PDT 24
Finished Jul 09 04:35:07 PM PDT 24
Peak memory 190936 kb
Host smart-62d521bd-629d-4665-a31c-800191457bde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112932061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.4112932061
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2481924374
Short name T506
Test name
Test status
Simulation time 234050049 ps
CPU time 1.93 seconds
Started Jul 09 04:35:07 PM PDT 24
Finished Jul 09 04:35:11 PM PDT 24
Peak memory 196972 kb
Host smart-2c179d9a-fb9f-49ce-826d-d4456a27ccad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481924374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2481924374
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.4014970597
Short name T31
Test name
Test status
Simulation time 120413854 ps
CPU time 0.9 seconds
Started Jul 09 04:35:02 PM PDT 24
Finished Jul 09 04:35:04 PM PDT 24
Peak memory 193016 kb
Host smart-b607b317-c270-42ba-920c-96bee960f222
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014970597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.4014970597
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.70463357
Short name T467
Test name
Test status
Simulation time 126975275 ps
CPU time 0.81 seconds
Started Jul 09 04:35:07 PM PDT 24
Finished Jul 09 04:35:10 PM PDT 24
Peak memory 196564 kb
Host smart-26b09a25-2469-42ab-8c49-9dd79182b8a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70463357 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.70463357
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2922866446
Short name T59
Test name
Test status
Simulation time 134236495 ps
CPU time 0.57 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:12 PM PDT 24
Peak memory 182112 kb
Host smart-e9f317d1-29d6-41d1-8a1d-373c1ac27726
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922866446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2922866446
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.3379259976
Short name T457
Test name
Test status
Simulation time 40255249 ps
CPU time 0.57 seconds
Started Jul 09 04:35:03 PM PDT 24
Finished Jul 09 04:35:04 PM PDT 24
Peak memory 182060 kb
Host smart-e6464316-8fae-4aa2-bcc9-56c530db0594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379259976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.3379259976
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.4069485246
Short name T73
Test name
Test status
Simulation time 38481714 ps
CPU time 0.84 seconds
Started Jul 09 04:35:09 PM PDT 24
Finished Jul 09 04:35:12 PM PDT 24
Peak memory 192852 kb
Host smart-2abc00be-d651-4231-b8cd-cc524f7418c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069485246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.4069485246
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.51411140
Short name T463
Test name
Test status
Simulation time 69806328 ps
CPU time 1.92 seconds
Started Jul 09 04:35:14 PM PDT 24
Finished Jul 09 04:35:18 PM PDT 24
Peak memory 196876 kb
Host smart-d5ffbec4-1218-4c00-b58d-cf18dce846a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51411140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.51411140
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.4169939144
Short name T84
Test name
Test status
Simulation time 53267580 ps
CPU time 0.84 seconds
Started Jul 09 04:35:01 PM PDT 24
Finished Jul 09 04:35:02 PM PDT 24
Peak memory 193052 kb
Host smart-54d67c5e-79dd-45a9-9f1a-08c25ce0c3d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169939144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.4169939144
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.609051738
Short name T343
Test name
Test status
Simulation time 124460125696 ps
CPU time 198 seconds
Started Jul 09 04:24:15 PM PDT 24
Finished Jul 09 04:27:35 PM PDT 24
Peak memory 182972 kb
Host smart-ebfa1d5c-3569-4f00-88f5-2d3e9b684da6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609051738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.609051738
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.604796994
Short name T382
Test name
Test status
Simulation time 69271852957 ps
CPU time 94.82 seconds
Started Jul 09 04:22:36 PM PDT 24
Finished Jul 09 04:24:12 PM PDT 24
Peak memory 182992 kb
Host smart-b1135ab6-3f00-4036-bf37-9d1334845f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604796994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.604796994
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.4291669694
Short name T387
Test name
Test status
Simulation time 805379676 ps
CPU time 4.36 seconds
Started Jul 09 04:24:15 PM PDT 24
Finished Jul 09 04:24:21 PM PDT 24
Peak memory 183016 kb
Host smart-e5a3439d-a0a1-4e30-a86d-2cd2b09f65c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291669694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.4291669694
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2896047808
Short name T1
Test name
Test status
Simulation time 72654473 ps
CPU time 0.57 seconds
Started Jul 09 04:23:34 PM PDT 24
Finished Jul 09 04:23:36 PM PDT 24
Peak memory 182360 kb
Host smart-2ea59e4b-b936-4380-8831-f7d8a92a7a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896047808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2896047808
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3559906691
Short name T417
Test name
Test status
Simulation time 22481316623 ps
CPU time 31.6 seconds
Started Jul 09 04:26:45 PM PDT 24
Finished Jul 09 04:27:19 PM PDT 24
Peak memory 182992 kb
Host smart-88d85e0d-3670-44b2-abc7-1e453609892a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559906691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3559906691
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2827501190
Short name T349
Test name
Test status
Simulation time 104767474670 ps
CPU time 113.62 seconds
Started Jul 09 04:22:28 PM PDT 24
Finished Jul 09 04:24:22 PM PDT 24
Peak memory 183404 kb
Host smart-97f91981-ca66-4cee-a5f0-c71e1341c70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827501190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2827501190
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1192360869
Short name T19
Test name
Test status
Simulation time 218533047 ps
CPU time 0.88 seconds
Started Jul 09 04:27:42 PM PDT 24
Finished Jul 09 04:27:43 PM PDT 24
Peak memory 213216 kb
Host smart-cb3b2524-8925-487a-984b-e71d441ac74c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192360869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1192360869
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3013887322
Short name T351
Test name
Test status
Simulation time 133725153739 ps
CPU time 40.79 seconds
Started Jul 09 04:35:18 PM PDT 24
Finished Jul 09 04:36:00 PM PDT 24
Peak memory 182964 kb
Host smart-bf531af9-130c-4cd4-b038-8d9fbe32ed97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013887322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3013887322
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1736633152
Short name T424
Test name
Test status
Simulation time 551210591155 ps
CPU time 233.78 seconds
Started Jul 09 04:35:25 PM PDT 24
Finished Jul 09 04:39:20 PM PDT 24
Peak memory 182988 kb
Host smart-5c7938d5-ee5b-4c4b-832e-749205bcf2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736633152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1736633152
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1725439728
Short name T155
Test name
Test status
Simulation time 889827057753 ps
CPU time 720.06 seconds
Started Jul 09 04:35:18 PM PDT 24
Finished Jul 09 04:47:19 PM PDT 24
Peak memory 191184 kb
Host smart-ba8b9131-d88f-47e8-8b7c-fd8671b4edbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725439728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1725439728
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2282003815
Short name T396
Test name
Test status
Simulation time 446999865 ps
CPU time 1.01 seconds
Started Jul 09 04:35:20 PM PDT 24
Finished Jul 09 04:35:22 PM PDT 24
Peak memory 182872 kb
Host smart-559e67d4-8fec-430f-9045-f6c27dc79c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282003815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2282003815
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all_with_rand_reset.166773340
Short name T14
Test name
Test status
Simulation time 85235883013 ps
CPU time 608.53 seconds
Started Jul 09 04:35:22 PM PDT 24
Finished Jul 09 04:45:31 PM PDT 24
Peak memory 206260 kb
Host smart-d3f02fa0-c30d-4c71-ade2-f890f1970982
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166773340 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all_with_rand_reset.166773340
Directory /workspace/10.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/101.rv_timer_random.916935360
Short name T249
Test name
Test status
Simulation time 760433319334 ps
CPU time 498.39 seconds
Started Jul 09 04:36:03 PM PDT 24
Finished Jul 09 04:44:22 PM PDT 24
Peak memory 191164 kb
Host smart-fd3a6e65-2f2b-4ed7-9af0-a283524ea30b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916935360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.916935360
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.1518670241
Short name T218
Test name
Test status
Simulation time 66294043313 ps
CPU time 36.86 seconds
Started Jul 09 04:36:04 PM PDT 24
Finished Jul 09 04:36:42 PM PDT 24
Peak memory 182992 kb
Host smart-5d0d9787-6d7d-4fd9-b507-04570563c5d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518670241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.1518670241
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3588289580
Short name T201
Test name
Test status
Simulation time 295039938320 ps
CPU time 167.14 seconds
Started Jul 09 04:36:04 PM PDT 24
Finished Jul 09 04:38:52 PM PDT 24
Peak memory 191128 kb
Host smart-ae4f90d1-fe17-4afa-96f2-8dd27c2f61cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588289580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3588289580
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2282337571
Short name T324
Test name
Test status
Simulation time 458139039853 ps
CPU time 404.32 seconds
Started Jul 09 04:36:15 PM PDT 24
Finished Jul 09 04:43:00 PM PDT 24
Peak memory 191184 kb
Host smart-412d4995-3a31-448f-9fe7-c460d3d7b228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282337571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2282337571
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2875078012
Short name T120
Test name
Test status
Simulation time 682298454357 ps
CPU time 1998.69 seconds
Started Jul 09 04:36:04 PM PDT 24
Finished Jul 09 05:09:24 PM PDT 24
Peak memory 191124 kb
Host smart-42d8f472-f192-4d7f-82ae-8f94c22e4d88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875078012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2875078012
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.3191150230
Short name T248
Test name
Test status
Simulation time 185341456223 ps
CPU time 94.73 seconds
Started Jul 09 04:36:04 PM PDT 24
Finished Jul 09 04:37:40 PM PDT 24
Peak memory 191184 kb
Host smart-c68add70-91f7-4000-a70b-3394f64942eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191150230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.3191150230
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2930221315
Short name T47
Test name
Test status
Simulation time 236125185496 ps
CPU time 231.42 seconds
Started Jul 09 04:36:08 PM PDT 24
Finished Jul 09 04:40:00 PM PDT 24
Peak memory 191176 kb
Host smart-0f1432de-956d-4145-93a4-0188921499c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930221315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2930221315
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.3025464312
Short name T234
Test name
Test status
Simulation time 809149816161 ps
CPU time 719.52 seconds
Started Jul 09 04:36:13 PM PDT 24
Finished Jul 09 04:48:13 PM PDT 24
Peak memory 191176 kb
Host smart-1d406550-fb13-4115-b239-2af17ef1ce6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025464312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.3025464312
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.831969679
Short name T312
Test name
Test status
Simulation time 363228732476 ps
CPU time 560.8 seconds
Started Jul 09 04:35:29 PM PDT 24
Finished Jul 09 04:44:52 PM PDT 24
Peak memory 182972 kb
Host smart-024403bc-b701-4da3-bb6a-9f4d110a0110
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831969679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.831969679
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1778405638
Short name T392
Test name
Test status
Simulation time 272217863 ps
CPU time 0.66 seconds
Started Jul 09 04:35:23 PM PDT 24
Finished Jul 09 04:35:25 PM PDT 24
Peak memory 182808 kb
Host smart-7cbbc31a-786b-45c8-b248-7a1e3b5f1e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778405638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1778405638
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.2002315429
Short name T395
Test name
Test status
Simulation time 1165461327078 ps
CPU time 427.43 seconds
Started Jul 09 04:35:25 PM PDT 24
Finished Jul 09 04:42:33 PM PDT 24
Peak memory 194972 kb
Host smart-53b6d6e0-b378-4126-b0b8-6cce3deedf54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002315429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.2002315429
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.1266697444
Short name T233
Test name
Test status
Simulation time 105455617461 ps
CPU time 1899.15 seconds
Started Jul 09 04:36:05 PM PDT 24
Finished Jul 09 05:07:45 PM PDT 24
Peak memory 191192 kb
Host smart-9ee821e7-f2b1-410f-84b2-c11057021850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266697444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1266697444
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1026729030
Short name T322
Test name
Test status
Simulation time 8686605108 ps
CPU time 6.64 seconds
Started Jul 09 04:36:03 PM PDT 24
Finished Jul 09 04:36:10 PM PDT 24
Peak memory 183000 kb
Host smart-569a0108-cd3f-4385-9b4b-255df1fb8ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026729030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1026729030
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1527340795
Short name T282
Test name
Test status
Simulation time 10652233616 ps
CPU time 8.91 seconds
Started Jul 09 04:36:04 PM PDT 24
Finished Jul 09 04:36:14 PM PDT 24
Peak memory 182956 kb
Host smart-7e29d9c2-c459-46ca-86ac-fbc66886bfc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527340795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1527340795
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.606748697
Short name T260
Test name
Test status
Simulation time 398833942271 ps
CPU time 1038.56 seconds
Started Jul 09 04:36:13 PM PDT 24
Finished Jul 09 04:53:33 PM PDT 24
Peak memory 191204 kb
Host smart-c90ce9f8-8dee-449a-af7e-6ed45e6bf913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606748697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.606748697
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.4268863697
Short name T152
Test name
Test status
Simulation time 353116520253 ps
CPU time 389.01 seconds
Started Jul 09 04:36:16 PM PDT 24
Finished Jul 09 04:42:46 PM PDT 24
Peak memory 193540 kb
Host smart-47703c9e-7570-4049-8838-a75d12688d34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268863697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4268863697
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3829449829
Short name T125
Test name
Test status
Simulation time 17490764910 ps
CPU time 29.36 seconds
Started Jul 09 04:36:10 PM PDT 24
Finished Jul 09 04:36:40 PM PDT 24
Peak memory 182992 kb
Host smart-2fdc9757-cc47-4966-85f5-f7e4874023ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829449829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3829449829
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.34986376
Short name T438
Test name
Test status
Simulation time 66445189746 ps
CPU time 395.67 seconds
Started Jul 09 04:36:07 PM PDT 24
Finished Jul 09 04:42:43 PM PDT 24
Peak memory 191120 kb
Host smart-3fa29f89-2076-4175-aeac-85a705e67a1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34986376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.34986376
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.739921530
Short name T346
Test name
Test status
Simulation time 461494801158 ps
CPU time 360.01 seconds
Started Jul 09 04:36:07 PM PDT 24
Finished Jul 09 04:42:08 PM PDT 24
Peak memory 191180 kb
Host smart-eb016a5d-7e65-449c-81b9-2d9318d6ba4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739921530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.739921530
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1749050554
Short name T347
Test name
Test status
Simulation time 68935657618 ps
CPU time 99.21 seconds
Started Jul 09 04:35:24 PM PDT 24
Finished Jul 09 04:37:04 PM PDT 24
Peak memory 182928 kb
Host smart-79544e28-86fa-4fa1-952b-306aeaddee56
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749050554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1749050554
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2421563180
Short name T372
Test name
Test status
Simulation time 681406147935 ps
CPU time 140.26 seconds
Started Jul 09 04:35:27 PM PDT 24
Finished Jul 09 04:37:49 PM PDT 24
Peak memory 183016 kb
Host smart-a206782c-5721-49a5-b8ea-11a9fb626f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421563180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2421563180
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1379358253
Short name T414
Test name
Test status
Simulation time 29658364 ps
CPU time 0.56 seconds
Started Jul 09 04:35:24 PM PDT 24
Finished Jul 09 04:35:25 PM PDT 24
Peak memory 182868 kb
Host smart-f47f6369-e7cd-4c06-a781-e6ea653fe3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379358253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1379358253
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.1904518668
Short name T13
Test name
Test status
Simulation time 65980871065 ps
CPU time 460.98 seconds
Started Jul 09 04:35:23 PM PDT 24
Finished Jul 09 04:43:05 PM PDT 24
Peak memory 205856 kb
Host smart-32dea21c-b992-46a8-ab55-a377633c195c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904518668 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.1904518668
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3244967166
Short name T104
Test name
Test status
Simulation time 2248549617182 ps
CPU time 500.98 seconds
Started Jul 09 04:36:11 PM PDT 24
Finished Jul 09 04:44:32 PM PDT 24
Peak memory 191248 kb
Host smart-3d52fc32-bf74-4cac-9865-51274c0684c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244967166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3244967166
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1952404450
Short name T214
Test name
Test status
Simulation time 76756561558 ps
CPU time 172.06 seconds
Started Jul 09 04:36:10 PM PDT 24
Finished Jul 09 04:39:03 PM PDT 24
Peak memory 191172 kb
Host smart-dde813a8-c4f6-4030-a120-617f18f8a24e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952404450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1952404450
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3407457751
Short name T275
Test name
Test status
Simulation time 33447623730 ps
CPU time 64.15 seconds
Started Jul 09 04:36:13 PM PDT 24
Finished Jul 09 04:37:17 PM PDT 24
Peak memory 193408 kb
Host smart-07a9bc32-cbd8-40ab-86a6-d6378dad7161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407457751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3407457751
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.708240196
Short name T115
Test name
Test status
Simulation time 42351808046 ps
CPU time 66.19 seconds
Started Jul 09 04:36:15 PM PDT 24
Finished Jul 09 04:37:22 PM PDT 24
Peak memory 191124 kb
Host smart-c8deb1bb-bc16-4f92-b147-b0b78ad3a634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708240196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.708240196
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2864242508
Short name T174
Test name
Test status
Simulation time 296008426187 ps
CPU time 723.03 seconds
Started Jul 09 04:36:12 PM PDT 24
Finished Jul 09 04:48:16 PM PDT 24
Peak memory 191120 kb
Host smart-0fff48d7-8f1f-40ec-b33b-5a738ff48207
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864242508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2864242508
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.874978934
Short name T226
Test name
Test status
Simulation time 65806090924 ps
CPU time 117.68 seconds
Started Jul 09 04:36:12 PM PDT 24
Finished Jul 09 04:38:10 PM PDT 24
Peak memory 191256 kb
Host smart-d8c9960f-1ae3-4f1b-aef3-894e5d184b33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874978934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.874978934
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3202399804
Short name T300
Test name
Test status
Simulation time 108196889487 ps
CPU time 207.44 seconds
Started Jul 09 04:36:15 PM PDT 24
Finished Jul 09 04:39:43 PM PDT 24
Peak memory 191156 kb
Host smart-c6bbc682-9321-4045-b96f-0329905b4d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202399804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3202399804
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.291698207
Short name T237
Test name
Test status
Simulation time 888989986644 ps
CPU time 432.12 seconds
Started Jul 09 04:35:30 PM PDT 24
Finished Jul 09 04:42:45 PM PDT 24
Peak memory 183080 kb
Host smart-bf915ffd-5974-4fdd-8050-5f319285c587
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291698207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.291698207
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2972312257
Short name T427
Test name
Test status
Simulation time 144430176447 ps
CPU time 182.94 seconds
Started Jul 09 04:35:29 PM PDT 24
Finished Jul 09 04:38:35 PM PDT 24
Peak memory 182976 kb
Host smart-1c947233-b23b-4a77-a0bc-5b3237bf2917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972312257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2972312257
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3316947468
Short name T298
Test name
Test status
Simulation time 144835575382 ps
CPU time 50.35 seconds
Started Jul 09 04:35:23 PM PDT 24
Finished Jul 09 04:36:15 PM PDT 24
Peak memory 183080 kb
Host smart-a33eb1f2-aa3c-435f-acdc-d60fe1ed3240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316947468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3316947468
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/132.rv_timer_random.885467840
Short name T252
Test name
Test status
Simulation time 123439414954 ps
CPU time 111.25 seconds
Started Jul 09 04:36:12 PM PDT 24
Finished Jul 09 04:38:04 PM PDT 24
Peak memory 191144 kb
Host smart-3c715c60-009e-4ecc-9ad5-faacb915e002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885467840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.885467840
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.330105198
Short name T127
Test name
Test status
Simulation time 6880204836 ps
CPU time 10.05 seconds
Started Jul 09 04:36:18 PM PDT 24
Finished Jul 09 04:36:28 PM PDT 24
Peak memory 183004 kb
Host smart-e4923a8e-d142-41b7-a610-37b85a8d7f92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330105198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.330105198
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1409149190
Short name T114
Test name
Test status
Simulation time 42959074627 ps
CPU time 166.72 seconds
Started Jul 09 04:36:17 PM PDT 24
Finished Jul 09 04:39:04 PM PDT 24
Peak memory 182952 kb
Host smart-71f3ae83-6690-45d7-b87f-d733482547cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409149190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1409149190
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2960459414
Short name T231
Test name
Test status
Simulation time 269249256697 ps
CPU time 194.92 seconds
Started Jul 09 04:36:16 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 191256 kb
Host smart-25a41b94-e35e-41c8-8c5e-5ecccd185863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960459414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2960459414
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.4246869343
Short name T131
Test name
Test status
Simulation time 204347513040 ps
CPU time 309.11 seconds
Started Jul 09 04:35:31 PM PDT 24
Finished Jul 09 04:40:42 PM PDT 24
Peak memory 182984 kb
Host smart-80cd3b6a-b1a1-4f88-93e6-219ba54ca084
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246869343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.4246869343
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.587005790
Short name T375
Test name
Test status
Simulation time 155348390209 ps
CPU time 249.19 seconds
Started Jul 09 04:35:23 PM PDT 24
Finished Jul 09 04:39:33 PM PDT 24
Peak memory 182948 kb
Host smart-7146cfee-9060-4400-8b02-1f3021bbcc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587005790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.587005790
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1671042487
Short name T3
Test name
Test status
Simulation time 48592316 ps
CPU time 0.6 seconds
Started Jul 09 04:35:25 PM PDT 24
Finished Jul 09 04:35:26 PM PDT 24
Peak memory 182844 kb
Host smart-9f8a593d-cd6f-41a5-a3d0-f30b0dec6f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671042487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1671042487
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.1533783717
Short name T342
Test name
Test status
Simulation time 83915300436 ps
CPU time 90 seconds
Started Jul 09 04:36:17 PM PDT 24
Finished Jul 09 04:37:48 PM PDT 24
Peak memory 191176 kb
Host smart-45f37896-a182-415a-8401-30ea152b03b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533783717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1533783717
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.4130460347
Short name T122
Test name
Test status
Simulation time 148516512884 ps
CPU time 123.41 seconds
Started Jul 09 04:36:23 PM PDT 24
Finished Jul 09 04:38:27 PM PDT 24
Peak memory 191192 kb
Host smart-97038ffb-2510-49b6-b70f-bd53920ee77b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130460347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.4130460347
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3286397697
Short name T311
Test name
Test status
Simulation time 5097811076 ps
CPU time 166.03 seconds
Started Jul 09 04:36:20 PM PDT 24
Finished Jul 09 04:39:06 PM PDT 24
Peak memory 182976 kb
Host smart-76fdc459-dc2a-4ad3-ab98-36f4061771e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286397697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3286397697
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3719192991
Short name T274
Test name
Test status
Simulation time 293345781988 ps
CPU time 247.8 seconds
Started Jul 09 04:36:26 PM PDT 24
Finished Jul 09 04:40:35 PM PDT 24
Peak memory 191172 kb
Host smart-06e35647-a536-41d3-9cdc-f70b428e073c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719192991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3719192991
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3789612269
Short name T433
Test name
Test status
Simulation time 119480832611 ps
CPU time 92.73 seconds
Started Jul 09 04:36:22 PM PDT 24
Finished Jul 09 04:37:55 PM PDT 24
Peak memory 191164 kb
Host smart-ecd1fad3-7c40-46f7-beca-dd703ad3df56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789612269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3789612269
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2457367773
Short name T44
Test name
Test status
Simulation time 193289094753 ps
CPU time 191.86 seconds
Started Jul 09 04:36:22 PM PDT 24
Finished Jul 09 04:39:34 PM PDT 24
Peak memory 191188 kb
Host smart-6a896dab-ecbf-4d74-b7ff-bda2e0ccc3c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457367773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2457367773
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2554213672
Short name T272
Test name
Test status
Simulation time 655037856332 ps
CPU time 313.82 seconds
Started Jul 09 04:35:35 PM PDT 24
Finished Jul 09 04:40:49 PM PDT 24
Peak memory 182972 kb
Host smart-4f98a1cc-7ad2-427b-ad0d-24e63124556b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554213672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2554213672
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.907570175
Short name T408
Test name
Test status
Simulation time 256395716166 ps
CPU time 87.15 seconds
Started Jul 09 04:35:36 PM PDT 24
Finished Jul 09 04:37:04 PM PDT 24
Peak memory 183052 kb
Host smart-14fe7f9d-a339-4e8d-9f78-53eba3eec7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907570175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.907570175
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.764833216
Short name T361
Test name
Test status
Simulation time 25229714 ps
CPU time 0.53 seconds
Started Jul 09 04:35:32 PM PDT 24
Finished Jul 09 04:35:34 PM PDT 24
Peak memory 182824 kb
Host smart-313b1cf1-4545-4e1c-8097-91eb0d500a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764833216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.764833216
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1892611890
Short name T112
Test name
Test status
Simulation time 161099353211 ps
CPU time 118.74 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:37:28 PM PDT 24
Peak memory 191140 kb
Host smart-cacc793b-80e3-4891-94f4-95af86a67a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892611890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1892611890
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.293379088
Short name T213
Test name
Test status
Simulation time 374685941975 ps
CPU time 472.66 seconds
Started Jul 09 04:36:25 PM PDT 24
Finished Jul 09 04:44:19 PM PDT 24
Peak memory 191172 kb
Host smart-70e5f18f-01c3-4f81-a4bc-a956e4009392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293379088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.293379088
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.703490428
Short name T140
Test name
Test status
Simulation time 734960647391 ps
CPU time 526.41 seconds
Started Jul 09 04:36:23 PM PDT 24
Finished Jul 09 04:45:10 PM PDT 24
Peak memory 191248 kb
Host smart-dbafc68e-2f49-4587-b79e-e90855b6792a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703490428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.703490428
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1227816570
Short name T222
Test name
Test status
Simulation time 8801111401 ps
CPU time 4.04 seconds
Started Jul 09 04:36:25 PM PDT 24
Finished Jul 09 04:36:30 PM PDT 24
Peak memory 182840 kb
Host smart-c4aa0409-5321-427e-8fd1-2fef6eeb711e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227816570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1227816570
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.249088908
Short name T146
Test name
Test status
Simulation time 556584694450 ps
CPU time 1073.63 seconds
Started Jul 09 04:36:24 PM PDT 24
Finished Jul 09 04:54:18 PM PDT 24
Peak memory 191140 kb
Host smart-5148a878-32f8-482c-a4ff-806b11b1bdd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249088908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.249088908
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.548116414
Short name T190
Test name
Test status
Simulation time 54286945284 ps
CPU time 136.48 seconds
Started Jul 09 04:36:26 PM PDT 24
Finished Jul 09 04:38:43 PM PDT 24
Peak memory 191176 kb
Host smart-4b81ec11-f579-4c31-899a-f84d95f0ec69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548116414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.548116414
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4260315679
Short name T287
Test name
Test status
Simulation time 66994049035 ps
CPU time 36.72 seconds
Started Jul 09 04:35:35 PM PDT 24
Finished Jul 09 04:36:12 PM PDT 24
Peak memory 182968 kb
Host smart-471585f3-a733-42ae-9802-d4676267ce2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260315679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.4260315679
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.247454589
Short name T362
Test name
Test status
Simulation time 212971396807 ps
CPU time 299.28 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:40:29 PM PDT 24
Peak memory 182992 kb
Host smart-3596abe8-809a-49d5-9906-7b31212599dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247454589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.247454589
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.168766252
Short name T197
Test name
Test status
Simulation time 163654155260 ps
CPU time 162.84 seconds
Started Jul 09 04:35:30 PM PDT 24
Finished Jul 09 04:38:15 PM PDT 24
Peak memory 191192 kb
Host smart-91f4a060-c412-4012-8f6e-26e01ac47977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168766252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.168766252
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1181822832
Short name T355
Test name
Test status
Simulation time 256615323 ps
CPU time 0.71 seconds
Started Jul 09 04:35:33 PM PDT 24
Finished Jul 09 04:35:35 PM PDT 24
Peak memory 182804 kb
Host smart-4a73c8f5-36dc-4e8e-81b2-6f152994f3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181822832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1181822832
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/162.rv_timer_random.3842553062
Short name T151
Test name
Test status
Simulation time 58370131919 ps
CPU time 335.49 seconds
Started Jul 09 04:36:25 PM PDT 24
Finished Jul 09 04:42:02 PM PDT 24
Peak memory 191204 kb
Host smart-f6b5fe22-2b63-4551-8b1d-7bef6ffab4ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842553062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.3842553062
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3836867562
Short name T402
Test name
Test status
Simulation time 112326388043 ps
CPU time 307.77 seconds
Started Jul 09 04:36:28 PM PDT 24
Finished Jul 09 04:41:36 PM PDT 24
Peak memory 194848 kb
Host smart-9f8f3e02-67f2-49ab-804e-78e4c594e04f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836867562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3836867562
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1318040154
Short name T331
Test name
Test status
Simulation time 320356798020 ps
CPU time 133.8 seconds
Started Jul 09 04:36:30 PM PDT 24
Finished Jul 09 04:38:44 PM PDT 24
Peak memory 191156 kb
Host smart-e22082d7-9209-445a-b259-15270f56078f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318040154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1318040154
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.1449029114
Short name T279
Test name
Test status
Simulation time 340235089014 ps
CPU time 328.29 seconds
Started Jul 09 04:36:31 PM PDT 24
Finished Jul 09 04:42:00 PM PDT 24
Peak memory 191148 kb
Host smart-92aebdb2-be74-4006-8926-e40534364aa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449029114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1449029114
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3611445074
Short name T344
Test name
Test status
Simulation time 175840890521 ps
CPU time 458.78 seconds
Started Jul 09 04:36:30 PM PDT 24
Finished Jul 09 04:44:09 PM PDT 24
Peak memory 191180 kb
Host smart-35935df3-a976-4165-9fa9-fd47d481d2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611445074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3611445074
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.645392107
Short name T350
Test name
Test status
Simulation time 320904989822 ps
CPU time 533.31 seconds
Started Jul 09 04:35:27 PM PDT 24
Finished Jul 09 04:44:21 PM PDT 24
Peak memory 183120 kb
Host smart-e44f56cb-81a6-4136-93bf-2c4844baf180
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645392107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.645392107
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2328097993
Short name T394
Test name
Test status
Simulation time 56528674131 ps
CPU time 78.72 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:36:49 PM PDT 24
Peak memory 182948 kb
Host smart-c6bf379a-0586-4a7f-a6ce-552fa3f4e99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328097993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2328097993
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/170.rv_timer_random.3937775211
Short name T163
Test name
Test status
Simulation time 265471559343 ps
CPU time 381.77 seconds
Started Jul 09 04:36:29 PM PDT 24
Finished Jul 09 04:42:52 PM PDT 24
Peak memory 191128 kb
Host smart-8ca50521-0dd5-44f6-af80-451ae08c698d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937775211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3937775211
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.448929242
Short name T175
Test name
Test status
Simulation time 110059867370 ps
CPU time 57.45 seconds
Started Jul 09 04:36:28 PM PDT 24
Finished Jul 09 04:37:26 PM PDT 24
Peak memory 183012 kb
Host smart-30b1c593-3db2-46e1-bb08-e7bb1c6a9564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448929242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.448929242
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.1827825791
Short name T296
Test name
Test status
Simulation time 529001097150 ps
CPU time 1226.55 seconds
Started Jul 09 04:36:32 PM PDT 24
Finished Jul 09 04:56:59 PM PDT 24
Peak memory 191176 kb
Host smart-142dafc7-e743-4e95-94f3-0dfc8d1d619a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827825791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.1827825791
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.3190365253
Short name T169
Test name
Test status
Simulation time 32821354675 ps
CPU time 50.18 seconds
Started Jul 09 04:36:29 PM PDT 24
Finished Jul 09 04:37:20 PM PDT 24
Peak memory 182952 kb
Host smart-e24ea460-31d5-4d3d-9219-bb32aff94bae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190365253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.3190365253
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.508942419
Short name T400
Test name
Test status
Simulation time 56170248421 ps
CPU time 556.08 seconds
Started Jul 09 04:36:28 PM PDT 24
Finished Jul 09 04:45:44 PM PDT 24
Peak memory 182944 kb
Host smart-f23df8c2-6e9a-4485-aafc-6c63daeb2f6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508942419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.508942419
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.4183912686
Short name T202
Test name
Test status
Simulation time 228965326604 ps
CPU time 144 seconds
Started Jul 09 04:36:28 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 191144 kb
Host smart-171c6a24-998e-4b4e-8d94-599aa98b5815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183912686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.4183912686
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2413375284
Short name T109
Test name
Test status
Simulation time 45007798353 ps
CPU time 17.94 seconds
Started Jul 09 04:35:35 PM PDT 24
Finished Jul 09 04:35:54 PM PDT 24
Peak memory 182868 kb
Host smart-19a259ce-bd26-4ba0-af2a-1d50ddbffeaa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413375284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2413375284
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.1304209791
Short name T354
Test name
Test status
Simulation time 27530338036 ps
CPU time 38.63 seconds
Started Jul 09 04:35:42 PM PDT 24
Finished Jul 09 04:36:22 PM PDT 24
Peak memory 183096 kb
Host smart-be619a6c-27be-4941-849f-9d8c766ccae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304209791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.1304209791
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.468420765
Short name T334
Test name
Test status
Simulation time 274032006701 ps
CPU time 505.18 seconds
Started Jul 09 04:35:29 PM PDT 24
Finished Jul 09 04:43:57 PM PDT 24
Peak memory 191200 kb
Host smart-2a86f734-c12e-4930-a98c-a17cc8214dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468420765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.468420765
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.2078139407
Short name T383
Test name
Test status
Simulation time 102114722 ps
CPU time 0.8 seconds
Started Jul 09 04:35:31 PM PDT 24
Finished Jul 09 04:35:34 PM PDT 24
Peak memory 182904 kb
Host smart-bd01095f-26f6-474e-b146-e97e00fa9458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078139407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.2078139407
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1206856871
Short name T276
Test name
Test status
Simulation time 438927796262 ps
CPU time 1874.97 seconds
Started Jul 09 04:36:33 PM PDT 24
Finished Jul 09 05:07:49 PM PDT 24
Peak memory 191164 kb
Host smart-4497172c-64b1-4cce-8605-85c4a7cc3163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206856871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1206856871
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1990828189
Short name T9
Test name
Test status
Simulation time 142287441885 ps
CPU time 152.81 seconds
Started Jul 09 04:36:32 PM PDT 24
Finished Jul 09 04:39:05 PM PDT 24
Peak memory 195428 kb
Host smart-aa09b446-ed21-4256-bf7f-f50929982ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990828189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1990828189
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3117219901
Short name T293
Test name
Test status
Simulation time 317134865638 ps
CPU time 160.35 seconds
Started Jul 09 04:36:32 PM PDT 24
Finished Jul 09 04:39:13 PM PDT 24
Peak memory 191120 kb
Host smart-b823ff87-899f-4eda-b3d0-b29a966f5a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117219901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3117219901
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1824046950
Short name T123
Test name
Test status
Simulation time 29608113251 ps
CPU time 51.94 seconds
Started Jul 09 04:36:34 PM PDT 24
Finished Jul 09 04:37:26 PM PDT 24
Peak memory 183000 kb
Host smart-e7cc94dc-ab5a-4484-b2a5-936f6b57762e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824046950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1824046950
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2110563867
Short name T88
Test name
Test status
Simulation time 159791520491 ps
CPU time 75.29 seconds
Started Jul 09 04:36:33 PM PDT 24
Finished Jul 09 04:37:49 PM PDT 24
Peak memory 183000 kb
Host smart-f88224c2-07e7-4db1-bac3-7787be8b8c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110563867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2110563867
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1121549884
Short name T187
Test name
Test status
Simulation time 305878373871 ps
CPU time 150.32 seconds
Started Jul 09 04:36:34 PM PDT 24
Finished Jul 09 04:39:05 PM PDT 24
Peak memory 191020 kb
Host smart-3b8ce080-4084-4f29-8dc8-4afd89195618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121549884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1121549884
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3982427511
Short name T239
Test name
Test status
Simulation time 211479109292 ps
CPU time 216.69 seconds
Started Jul 09 04:36:34 PM PDT 24
Finished Jul 09 04:40:11 PM PDT 24
Peak memory 194800 kb
Host smart-a8e49095-1b91-4cc5-aa7b-084a0f074b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982427511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3982427511
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3887629397
Short name T221
Test name
Test status
Simulation time 171939698240 ps
CPU time 138.89 seconds
Started Jul 09 04:36:33 PM PDT 24
Finished Jul 09 04:38:52 PM PDT 24
Peak memory 191072 kb
Host smart-4c0d304a-c615-4c1d-8db6-9aa6dd2a62eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887629397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3887629397
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.37088895
Short name T294
Test name
Test status
Simulation time 429732108479 ps
CPU time 204.17 seconds
Started Jul 09 04:36:34 PM PDT 24
Finished Jul 09 04:39:59 PM PDT 24
Peak memory 191172 kb
Host smart-f423b40e-ef1c-457b-89df-64265650e7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37088895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.37088895
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3388043524
Short name T126
Test name
Test status
Simulation time 30665416919 ps
CPU time 68.05 seconds
Started Jul 09 04:36:43 PM PDT 24
Finished Jul 09 04:37:51 PM PDT 24
Peak memory 182980 kb
Host smart-abfc348a-276f-4b7f-95d9-f4c2d02b7cc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388043524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3388043524
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.1507123704
Short name T399
Test name
Test status
Simulation time 880577459326 ps
CPU time 227.11 seconds
Started Jul 09 04:35:36 PM PDT 24
Finished Jul 09 04:39:24 PM PDT 24
Peak memory 183020 kb
Host smart-6335bebe-6541-4a84-93b4-adb3d1fd835b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507123704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.1507123704
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2973225251
Short name T380
Test name
Test status
Simulation time 154978351730 ps
CPU time 229.43 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:39:19 PM PDT 24
Peak memory 182936 kb
Host smart-9f3437bc-6797-4551-a28d-5fb4ff936ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973225251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2973225251
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.3957471459
Short name T441
Test name
Test status
Simulation time 235270571062 ps
CPU time 427.85 seconds
Started Jul 09 04:35:32 PM PDT 24
Finished Jul 09 04:42:41 PM PDT 24
Peak memory 191252 kb
Host smart-962bc32c-64f4-4a6f-b5a5-27c5e690e749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957471459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3957471459
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3894666579
Short name T46
Test name
Test status
Simulation time 40337313 ps
CPU time 0.53 seconds
Started Jul 09 04:35:32 PM PDT 24
Finished Jul 09 04:35:34 PM PDT 24
Peak memory 182852 kb
Host smart-2581c774-d24d-4dd3-9efc-e840c16569d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894666579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3894666579
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3672782939
Short name T92
Test name
Test status
Simulation time 934656797036 ps
CPU time 773.16 seconds
Started Jul 09 04:35:32 PM PDT 24
Finished Jul 09 04:48:27 PM PDT 24
Peak memory 191152 kb
Host smart-8d43882b-b45b-4c81-b67a-95f166b9f413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672782939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3672782939
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.1715357888
Short name T90
Test name
Test status
Simulation time 1636400534914 ps
CPU time 464.86 seconds
Started Jul 09 04:36:39 PM PDT 24
Finished Jul 09 04:44:24 PM PDT 24
Peak memory 191200 kb
Host smart-4d3c65a0-06ed-492b-8f8d-95a64a9ba531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715357888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1715357888
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3952622291
Short name T207
Test name
Test status
Simulation time 47194926068 ps
CPU time 76.59 seconds
Started Jul 09 04:36:38 PM PDT 24
Finished Jul 09 04:37:55 PM PDT 24
Peak memory 191028 kb
Host smart-c0baa9df-699a-4a52-9c51-3335ac0b8ef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952622291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3952622291
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.1927228674
Short name T40
Test name
Test status
Simulation time 1073867343771 ps
CPU time 333.15 seconds
Started Jul 09 04:36:38 PM PDT 24
Finished Jul 09 04:42:12 PM PDT 24
Peak memory 191176 kb
Host smart-7eb11202-de21-4c60-93f5-ca424ae872c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927228674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.1927228674
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1402854451
Short name T97
Test name
Test status
Simulation time 334605518556 ps
CPU time 159.94 seconds
Started Jul 09 04:36:37 PM PDT 24
Finished Jul 09 04:39:17 PM PDT 24
Peak memory 191192 kb
Host smart-39cc288f-11f1-4327-af77-8f43a52112bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402854451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1402854451
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.2223849363
Short name T436
Test name
Test status
Simulation time 71892456910 ps
CPU time 125.77 seconds
Started Jul 09 04:36:38 PM PDT 24
Finished Jul 09 04:38:44 PM PDT 24
Peak memory 191200 kb
Host smart-7285e884-5a19-4955-b71b-0e55679ff4f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223849363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.2223849363
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.35623350
Short name T305
Test name
Test status
Simulation time 155385110218 ps
CPU time 203.78 seconds
Started Jul 09 04:36:39 PM PDT 24
Finished Jul 09 04:40:03 PM PDT 24
Peak memory 191172 kb
Host smart-6e1358e8-2b7e-4f14-b356-904887063573
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35623350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.35623350
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3857628235
Short name T273
Test name
Test status
Simulation time 23247313715 ps
CPU time 34.5 seconds
Started Jul 09 04:36:37 PM PDT 24
Finished Jul 09 04:37:12 PM PDT 24
Peak memory 183000 kb
Host smart-83fce092-4a05-412b-8e5c-1879e8f97a03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857628235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3857628235
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.1994054771
Short name T42
Test name
Test status
Simulation time 155277558691 ps
CPU time 660.79 seconds
Started Jul 09 04:36:38 PM PDT 24
Finished Jul 09 04:47:39 PM PDT 24
Peak memory 191136 kb
Host smart-479ea0bc-0783-4674-8580-cd64c67af1d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994054771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.1994054771
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3467054212
Short name T409
Test name
Test status
Simulation time 502254400261 ps
CPU time 200.04 seconds
Started Jul 09 04:36:43 PM PDT 24
Finished Jul 09 04:40:04 PM PDT 24
Peak memory 191592 kb
Host smart-6a655afc-b51b-42f5-a93f-2bcd68202c63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467054212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3467054212
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1096915725
Short name T286
Test name
Test status
Simulation time 1404776338894 ps
CPU time 656.57 seconds
Started Jul 09 04:22:40 PM PDT 24
Finished Jul 09 04:33:37 PM PDT 24
Peak memory 182932 kb
Host smart-c59d521c-247e-4653-ac84-a71eb48d7516
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096915725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1096915725
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2899687186
Short name T20
Test name
Test status
Simulation time 220840809198 ps
CPU time 335.48 seconds
Started Jul 09 04:23:41 PM PDT 24
Finished Jul 09 04:29:18 PM PDT 24
Peak memory 182968 kb
Host smart-46b76fe2-8a2c-4b0b-92f7-95fec0dcb5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899687186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2899687186
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1186912530
Short name T180
Test name
Test status
Simulation time 71398305201 ps
CPU time 124.08 seconds
Started Jul 09 04:23:58 PM PDT 24
Finished Jul 09 04:26:03 PM PDT 24
Peak memory 191264 kb
Host smart-116755f1-84c0-4093-864d-9c44d3a65063
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186912530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1186912530
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1638683570
Short name T374
Test name
Test status
Simulation time 48292974 ps
CPU time 0.97 seconds
Started Jul 09 04:27:01 PM PDT 24
Finished Jul 09 04:27:08 PM PDT 24
Peak memory 181304 kb
Host smart-64efde23-c969-412b-9fd6-8d5c93c0e5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638683570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1638683570
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.636023854
Short name T18
Test name
Test status
Simulation time 159421718 ps
CPU time 0.8 seconds
Started Jul 09 04:21:44 PM PDT 24
Finished Jul 09 04:21:46 PM PDT 24
Peak memory 213144 kb
Host smart-b498648b-d64c-4e4a-bb28-1a7c8c2c6ab1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636023854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.636023854
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2087893039
Short name T156
Test name
Test status
Simulation time 220888054209 ps
CPU time 1538.41 seconds
Started Jul 09 04:27:10 PM PDT 24
Finished Jul 09 04:52:55 PM PDT 24
Peak memory 195392 kb
Host smart-9e2d2044-f3df-4d71-87ee-a1077b883077
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087893039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2087893039
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3415081467
Short name T404
Test name
Test status
Simulation time 59640786464 ps
CPU time 47.19 seconds
Started Jul 09 04:35:36 PM PDT 24
Finished Jul 09 04:36:24 PM PDT 24
Peak memory 183016 kb
Host smart-16265ea7-b659-4129-88c5-19d206b22e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415081467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3415081467
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.818909835
Short name T178
Test name
Test status
Simulation time 139026426040 ps
CPU time 93.85 seconds
Started Jul 09 04:35:33 PM PDT 24
Finished Jul 09 04:37:08 PM PDT 24
Peak memory 182988 kb
Host smart-1a42f647-ac03-4897-9c70-53139a0199b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818909835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.818909835
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.887421971
Short name T145
Test name
Test status
Simulation time 388691343372 ps
CPU time 832.4 seconds
Started Jul 09 04:35:35 PM PDT 24
Finished Jul 09 04:49:28 PM PDT 24
Peak memory 191140 kb
Host smart-89f8d67e-8d1e-4384-8407-4728d9c90155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887421971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
887421971
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3294073605
Short name T302
Test name
Test status
Simulation time 1738423606123 ps
CPU time 1019.55 seconds
Started Jul 09 04:35:37 PM PDT 24
Finished Jul 09 04:52:37 PM PDT 24
Peak memory 182972 kb
Host smart-b31ddcb4-12b7-464e-829f-ea894e764377
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294073605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3294073605
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1117361533
Short name T378
Test name
Test status
Simulation time 703274478001 ps
CPU time 245.81 seconds
Started Jul 09 04:35:40 PM PDT 24
Finished Jul 09 04:39:47 PM PDT 24
Peak memory 183008 kb
Host smart-28fcb69f-9664-496a-9c1e-b65f1a814418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117361533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1117361533
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.258533531
Short name T119
Test name
Test status
Simulation time 701162097617 ps
CPU time 471.61 seconds
Started Jul 09 04:35:38 PM PDT 24
Finished Jul 09 04:43:31 PM PDT 24
Peak memory 194372 kb
Host smart-fdc90321-6117-4ccb-8797-ff8bedae59ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258533531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.258533531
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3898654910
Short name T306
Test name
Test status
Simulation time 8180446764 ps
CPU time 151.87 seconds
Started Jul 09 04:35:33 PM PDT 24
Finished Jul 09 04:38:06 PM PDT 24
Peak memory 191180 kb
Host smart-2d71ec0a-664b-4379-b823-caf34aee2459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898654910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3898654910
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1945781030
Short name T53
Test name
Test status
Simulation time 347061067674 ps
CPU time 466.74 seconds
Started Jul 09 04:35:32 PM PDT 24
Finished Jul 09 04:43:20 PM PDT 24
Peak memory 191280 kb
Host smart-ee2a99a4-8f29-4fa1-81c4-d37469c48d65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945781030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1945781030
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all_with_rand_reset.4083087734
Short name T34
Test name
Test status
Simulation time 101101297170 ps
CPU time 117.2 seconds
Started Jul 09 04:35:37 PM PDT 24
Finished Jul 09 04:37:36 PM PDT 24
Peak memory 205908 kb
Host smart-f72483ed-af99-4b9e-b394-25b6efc52579
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083087734 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all_with_rand_reset.4083087734
Directory /workspace/21.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3660464801
Short name T101
Test name
Test status
Simulation time 1138585375553 ps
CPU time 573.33 seconds
Started Jul 09 04:35:38 PM PDT 24
Finished Jul 09 04:45:13 PM PDT 24
Peak memory 182924 kb
Host smart-30ee63e8-c01c-4aea-a00c-985c48b67198
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660464801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3660464801
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1520133893
Short name T379
Test name
Test status
Simulation time 71580748377 ps
CPU time 32.09 seconds
Started Jul 09 04:35:38 PM PDT 24
Finished Jul 09 04:36:11 PM PDT 24
Peak memory 182984 kb
Host smart-68af4e3b-0d0a-4285-91c6-8c5e6d4824fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520133893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1520133893
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1720162818
Short name T341
Test name
Test status
Simulation time 34134593139 ps
CPU time 51.25 seconds
Started Jul 09 04:35:41 PM PDT 24
Finished Jul 09 04:36:33 PM PDT 24
Peak memory 182936 kb
Host smart-8a7c791c-9793-4f62-8d1a-bc07924b7de4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720162818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1720162818
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2867346021
Short name T353
Test name
Test status
Simulation time 77086729 ps
CPU time 0.6 seconds
Started Jul 09 04:35:38 PM PDT 24
Finished Jul 09 04:35:39 PM PDT 24
Peak memory 182820 kb
Host smart-e0d9000b-3b62-4951-bf6b-6b0b595d62dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867346021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2867346021
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.526314618
Short name T325
Test name
Test status
Simulation time 8052344090 ps
CPU time 12.74 seconds
Started Jul 09 04:35:36 PM PDT 24
Finished Jul 09 04:35:49 PM PDT 24
Peak memory 183392 kb
Host smart-32ea1257-08b6-4d63-bacb-b4d660dea15c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526314618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.526314618
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.155536088
Short name T7
Test name
Test status
Simulation time 130543822021 ps
CPU time 205.23 seconds
Started Jul 09 04:35:42 PM PDT 24
Finished Jul 09 04:39:07 PM PDT 24
Peak memory 183096 kb
Host smart-61ff95bc-ae46-4f8d-ba83-c48e356cdd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155536088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.155536088
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.279091609
Short name T133
Test name
Test status
Simulation time 556498144637 ps
CPU time 389.1 seconds
Started Jul 09 04:35:47 PM PDT 24
Finished Jul 09 04:42:17 PM PDT 24
Peak memory 191140 kb
Host smart-fcb77ff2-ba9e-4559-b9d8-e0d7dbbbb365
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279091609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.279091609
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.280047981
Short name T443
Test name
Test status
Simulation time 9901514760 ps
CPU time 4.91 seconds
Started Jul 09 04:35:47 PM PDT 24
Finished Jul 09 04:35:53 PM PDT 24
Peak memory 191168 kb
Host smart-9e2b9c3f-8088-45d6-9077-7d30c502b26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280047981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.280047981
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1533100809
Short name T209
Test name
Test status
Simulation time 53600209081 ps
CPU time 28.15 seconds
Started Jul 09 04:35:39 PM PDT 24
Finished Jul 09 04:36:08 PM PDT 24
Peak memory 182980 kb
Host smart-b9e026d0-4b1a-4a71-860d-5b972dc3d3c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533100809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1533100809
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.281327267
Short name T292
Test name
Test status
Simulation time 138863768030 ps
CPU time 103 seconds
Started Jul 09 04:35:49 PM PDT 24
Finished Jul 09 04:37:32 PM PDT 24
Peak memory 191188 kb
Host smart-5a9920be-bf78-4409-9892-995d1af308cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281327267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.281327267
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.258028199
Short name T337
Test name
Test status
Simulation time 9458587012 ps
CPU time 12.92 seconds
Started Jul 09 04:35:37 PM PDT 24
Finished Jul 09 04:35:51 PM PDT 24
Peak memory 182904 kb
Host smart-3ef92d93-10e3-4df8-8f42-99f50aba7b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258028199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.258028199
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.750567372
Short name T412
Test name
Test status
Simulation time 137934186671 ps
CPU time 46.91 seconds
Started Jul 09 04:35:42 PM PDT 24
Finished Jul 09 04:36:30 PM PDT 24
Peak memory 182936 kb
Host smart-2f9b0dd1-2cdf-4c22-a55d-3004289a8fbf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750567372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.rv_timer_cfg_update_on_fly.750567372
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3904558607
Short name T434
Test name
Test status
Simulation time 430095537704 ps
CPU time 332.9 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:41:34 PM PDT 24
Peak memory 182976 kb
Host smart-58e7bb4b-8927-40df-bc76-4309ce5efdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904558607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3904558607
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.166585985
Short name T332
Test name
Test status
Simulation time 47804878612 ps
CPU time 76.83 seconds
Started Jul 09 04:35:38 PM PDT 24
Finished Jul 09 04:36:56 PM PDT 24
Peak memory 183060 kb
Host smart-ab7ae478-1fe2-4129-ad1f-43bbc2dfe9ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166585985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.166585985
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.4172546503
Short name T369
Test name
Test status
Simulation time 19122026 ps
CPU time 0.53 seconds
Started Jul 09 04:35:37 PM PDT 24
Finished Jul 09 04:35:39 PM PDT 24
Peak memory 182820 kb
Host smart-d06abcb8-48e5-4529-905b-de15e5ceabac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172546503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.4172546503
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1237547162
Short name T188
Test name
Test status
Simulation time 226386631917 ps
CPU time 368.08 seconds
Started Jul 09 04:35:40 PM PDT 24
Finished Jul 09 04:41:49 PM PDT 24
Peak memory 183032 kb
Host smart-c54d676a-58d1-4ddf-aa87-85eb510afad8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237547162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1237547162
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1639977164
Short name T386
Test name
Test status
Simulation time 158377042121 ps
CPU time 221.86 seconds
Started Jul 09 04:35:40 PM PDT 24
Finished Jul 09 04:39:23 PM PDT 24
Peak memory 183084 kb
Host smart-1770ad74-cabd-4263-9544-288b5ea0d2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639977164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1639977164
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3354706975
Short name T352
Test name
Test status
Simulation time 26981457105 ps
CPU time 47.83 seconds
Started Jul 09 04:35:37 PM PDT 24
Finished Jul 09 04:36:26 PM PDT 24
Peak memory 182948 kb
Host smart-12487fe2-7c84-458d-bd68-7b2e731036f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354706975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3354706975
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2528903097
Short name T5
Test name
Test status
Simulation time 117052923074 ps
CPU time 181.17 seconds
Started Jul 09 04:35:37 PM PDT 24
Finished Jul 09 04:38:40 PM PDT 24
Peak memory 183000 kb
Host smart-921b8c30-372c-40f0-8180-88eab438be1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528903097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2528903097
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.1667102589
Short name T38
Test name
Test status
Simulation time 32936869368 ps
CPU time 355.22 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:41:54 PM PDT 24
Peak memory 205876 kb
Host smart-58ed6dbd-bde2-4228-bac4-7b3b1a55da02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667102589 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.1667102589
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2472101183
Short name T219
Test name
Test status
Simulation time 190077035276 ps
CPU time 64.06 seconds
Started Jul 09 04:36:52 PM PDT 24
Finished Jul 09 04:37:57 PM PDT 24
Peak memory 182904 kb
Host smart-a58645e8-ef92-47cb-a6e5-1e040caafa3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472101183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2472101183
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3529007242
Short name T356
Test name
Test status
Simulation time 321198190645 ps
CPU time 196.25 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:39:17 PM PDT 24
Peak memory 182960 kb
Host smart-efdf56a5-8f31-4455-b7cb-e0f34b7c9779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529007242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3529007242
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.2454500689
Short name T177
Test name
Test status
Simulation time 6816410567 ps
CPU time 39.34 seconds
Started Jul 09 04:35:55 PM PDT 24
Finished Jul 09 04:36:35 PM PDT 24
Peak memory 182992 kb
Host smart-d206ece0-1ee2-49ab-a99e-bdd535392fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454500689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.2454500689
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3049428241
Short name T118
Test name
Test status
Simulation time 539885356230 ps
CPU time 145.23 seconds
Started Jul 09 04:35:40 PM PDT 24
Finished Jul 09 04:38:06 PM PDT 24
Peak memory 183024 kb
Host smart-6fe44375-5d3b-4d3a-a032-43fb99f9e7ef
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049428241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3049428241
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2398051039
Short name T363
Test name
Test status
Simulation time 369102662025 ps
CPU time 68.43 seconds
Started Jul 09 04:35:45 PM PDT 24
Finished Jul 09 04:36:54 PM PDT 24
Peak memory 183016 kb
Host smart-60560199-761a-42cd-b774-36c7b6ee9d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398051039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2398051039
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.642207170
Short name T266
Test name
Test status
Simulation time 268966433613 ps
CPU time 135.08 seconds
Started Jul 09 04:36:00 PM PDT 24
Finished Jul 09 04:38:17 PM PDT 24
Peak memory 191168 kb
Host smart-19699daa-70ce-4a3f-b0e8-2cd64efa0c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642207170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.642207170
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.220385971
Short name T253
Test name
Test status
Simulation time 891499592594 ps
CPU time 392.63 seconds
Started Jul 09 04:35:42 PM PDT 24
Finished Jul 09 04:42:15 PM PDT 24
Peak memory 191148 kb
Host smart-e48148e6-b508-4db1-b7da-8c9dcf60c855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220385971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
220385971
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2746193996
Short name T147
Test name
Test status
Simulation time 1400389686115 ps
CPU time 606.85 seconds
Started Jul 09 04:35:41 PM PDT 24
Finished Jul 09 04:45:49 PM PDT 24
Peak memory 182940 kb
Host smart-6e497ed9-e9e2-46de-b44f-7cfba3f52db8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746193996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2746193996
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2615265868
Short name T393
Test name
Test status
Simulation time 226937000684 ps
CPU time 84.69 seconds
Started Jul 09 04:35:40 PM PDT 24
Finished Jul 09 04:37:06 PM PDT 24
Peak memory 182988 kb
Host smart-34d58e73-c8a6-4fd8-ad40-5e03c845b194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615265868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2615265868
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.3849132093
Short name T330
Test name
Test status
Simulation time 465900768016 ps
CPU time 141.63 seconds
Started Jul 09 04:35:44 PM PDT 24
Finished Jul 09 04:38:06 PM PDT 24
Peak memory 191164 kb
Host smart-57fd9737-96b7-451d-9237-048983752af5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849132093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.3849132093
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.729891627
Short name T398
Test name
Test status
Simulation time 53965027435 ps
CPU time 52.7 seconds
Started Jul 09 04:35:50 PM PDT 24
Finished Jul 09 04:36:43 PM PDT 24
Peak memory 191188 kb
Host smart-6a07f1a2-d388-4d17-b0ae-ef3f102ae071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729891627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.729891627
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2207733975
Short name T217
Test name
Test status
Simulation time 429463857349 ps
CPU time 466.74 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:43:48 PM PDT 24
Peak memory 194552 kb
Host smart-349f2b03-ef47-40c8-9ff2-a39d374a77df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207733975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2207733975
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2603215358
Short name T407
Test name
Test status
Simulation time 226599210781 ps
CPU time 362.09 seconds
Started Jul 09 04:27:09 PM PDT 24
Finished Jul 09 04:33:18 PM PDT 24
Peak memory 182908 kb
Host smart-dd22f3b9-3a99-426b-b653-ce90cb22e5cc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603215358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2603215358
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2435470229
Short name T435
Test name
Test status
Simulation time 577647610294 ps
CPU time 247.94 seconds
Started Jul 09 04:27:10 PM PDT 24
Finished Jul 09 04:31:24 PM PDT 24
Peak memory 182928 kb
Host smart-e9836a06-9c7f-4058-aed2-690eee774659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435470229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2435470229
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3756952064
Short name T261
Test name
Test status
Simulation time 43551291830 ps
CPU time 93.96 seconds
Started Jul 09 04:27:04 PM PDT 24
Finished Jul 09 04:28:43 PM PDT 24
Peak memory 190404 kb
Host smart-d05f8ad6-ac10-4e4a-b2a0-87aaa18512f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756952064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3756952064
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3894196619
Short name T15
Test name
Test status
Simulation time 238333636 ps
CPU time 0.96 seconds
Started Jul 09 04:24:52 PM PDT 24
Finished Jul 09 04:24:53 PM PDT 24
Peak memory 213440 kb
Host smart-55d59618-8b00-4ef2-b05e-b90981db9c70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894196619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3894196619
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.4004520962
Short name T205
Test name
Test status
Simulation time 416944855682 ps
CPU time 763.45 seconds
Started Jul 09 04:26:38 PM PDT 24
Finished Jul 09 04:39:22 PM PDT 24
Peak memory 190304 kb
Host smart-b35e287d-9a2e-4427-8cf9-14eb02ade9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004520962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
4004520962
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.148773894
Short name T327
Test name
Test status
Simulation time 440008384180 ps
CPU time 234.1 seconds
Started Jul 09 04:36:52 PM PDT 24
Finished Jul 09 04:40:47 PM PDT 24
Peak memory 182912 kb
Host smart-686854d4-a876-480a-9de3-ec7ef28e6050
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148773894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.148773894
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2585306980
Short name T416
Test name
Test status
Simulation time 391742595864 ps
CPU time 69.67 seconds
Started Jul 09 04:36:52 PM PDT 24
Finished Jul 09 04:38:03 PM PDT 24
Peak memory 182916 kb
Host smart-44c49c6d-9737-4dce-94ff-4aab41e09d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585306980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2585306980
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.4165263836
Short name T193
Test name
Test status
Simulation time 231448467829 ps
CPU time 245.35 seconds
Started Jul 09 04:35:42 PM PDT 24
Finished Jul 09 04:39:48 PM PDT 24
Peak memory 191204 kb
Host smart-954cd994-e920-4e85-866f-123119d22ef8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165263836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.4165263836
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.827136895
Short name T154
Test name
Test status
Simulation time 47116939300 ps
CPU time 102.03 seconds
Started Jul 09 04:36:04 PM PDT 24
Finished Jul 09 04:37:46 PM PDT 24
Peak memory 194168 kb
Host smart-d3b60a45-56f1-479c-940f-4a254f73dc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827136895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.827136895
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1919921045
Short name T22
Test name
Test status
Simulation time 66909807 ps
CPU time 0.5 seconds
Started Jul 09 04:36:50 PM PDT 24
Finished Jul 09 04:36:51 PM PDT 24
Peak memory 182328 kb
Host smart-334aebb6-595c-45ab-8f0c-7df3fcd02f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919921045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1919921045
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3784915534
Short name T182
Test name
Test status
Simulation time 411352760702 ps
CPU time 224.27 seconds
Started Jul 09 04:36:52 PM PDT 24
Finished Jul 09 04:40:37 PM PDT 24
Peak memory 182892 kb
Host smart-5c20b780-dbd5-4d89-a6f6-7266c380bcbc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784915534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3784915534
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3306206475
Short name T401
Test name
Test status
Simulation time 35797724140 ps
CPU time 48.41 seconds
Started Jul 09 04:35:54 PM PDT 24
Finished Jul 09 04:36:43 PM PDT 24
Peak memory 182984 kb
Host smart-985a760c-e690-4b9a-8ba3-d023a321449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306206475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3306206475
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.315092969
Short name T212
Test name
Test status
Simulation time 333532871233 ps
CPU time 434.61 seconds
Started Jul 09 04:36:01 PM PDT 24
Finished Jul 09 04:43:17 PM PDT 24
Peak memory 193648 kb
Host smart-4d4e7ad5-e535-43b8-a84d-3b4a7e43432a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315092969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.315092969
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2617987376
Short name T210
Test name
Test status
Simulation time 1278167438944 ps
CPU time 648.46 seconds
Started Jul 09 04:35:42 PM PDT 24
Finished Jul 09 04:46:31 PM PDT 24
Peak memory 182972 kb
Host smart-523e49e8-915b-4b9a-8ad9-29be60462abd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617987376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2617987376
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.3219707192
Short name T359
Test name
Test status
Simulation time 658365322783 ps
CPU time 245.31 seconds
Started Jul 09 04:36:51 PM PDT 24
Finished Jul 09 04:40:57 PM PDT 24
Peak memory 182924 kb
Host smart-4aae59c6-0f8e-4d19-bb54-bbf2493dfc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219707192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.3219707192
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1093715126
Short name T259
Test name
Test status
Simulation time 94798419080 ps
CPU time 151.13 seconds
Started Jul 09 04:35:42 PM PDT 24
Finished Jul 09 04:38:13 PM PDT 24
Peak memory 191140 kb
Host smart-5386cbe6-b541-46a4-92ad-2f151b393e99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093715126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1093715126
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1844339574
Short name T358
Test name
Test status
Simulation time 195531767 ps
CPU time 2.9 seconds
Started Jul 09 04:35:40 PM PDT 24
Finished Jul 09 04:35:44 PM PDT 24
Peak memory 191160 kb
Host smart-5bc56c9f-8209-4e5c-8a8d-6eed2a25fe87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844339574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1844339574
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3968212327
Short name T284
Test name
Test status
Simulation time 1425476963517 ps
CPU time 956.68 seconds
Started Jul 09 04:35:42 PM PDT 24
Finished Jul 09 04:51:39 PM PDT 24
Peak memory 191200 kb
Host smart-7e98c20e-39cc-4d24-9122-4d143c2d6588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968212327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3968212327
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.135407124
Short name T181
Test name
Test status
Simulation time 28888465209 ps
CPU time 39.59 seconds
Started Jul 09 04:36:52 PM PDT 24
Finished Jul 09 04:37:33 PM PDT 24
Peak memory 182528 kb
Host smart-1ad25589-1ea8-4f91-a49e-e5512720fe7f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135407124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.rv_timer_cfg_update_on_fly.135407124
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3145109696
Short name T440
Test name
Test status
Simulation time 694852512051 ps
CPU time 291.73 seconds
Started Jul 09 04:35:42 PM PDT 24
Finished Jul 09 04:40:34 PM PDT 24
Peak memory 182992 kb
Host smart-fe0065c5-ea4e-42a2-93bb-78a48034ab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145109696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3145109696
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1931087280
Short name T304
Test name
Test status
Simulation time 33610360295 ps
CPU time 57.76 seconds
Started Jul 09 04:35:44 PM PDT 24
Finished Jul 09 04:36:43 PM PDT 24
Peak memory 191072 kb
Host smart-c92be469-6fe4-4591-9736-48bcae1c09f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931087280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1931087280
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3166792330
Short name T420
Test name
Test status
Simulation time 1591705029157 ps
CPU time 674.56 seconds
Started Jul 09 04:35:52 PM PDT 24
Finished Jul 09 04:47:08 PM PDT 24
Peak memory 191200 kb
Host smart-4962e449-a5a1-49d8-ab00-8a469648ba82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166792330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3166792330
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.1436104735
Short name T153
Test name
Test status
Simulation time 460685526284 ps
CPU time 256.2 seconds
Started Jul 09 04:35:56 PM PDT 24
Finished Jul 09 04:40:12 PM PDT 24
Peak memory 182968 kb
Host smart-5b7459fc-c630-4e8b-883c-c682051d23bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436104735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.1436104735
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1073946212
Short name T2
Test name
Test status
Simulation time 12746067679 ps
CPU time 19.7 seconds
Started Jul 09 04:35:47 PM PDT 24
Finished Jul 09 04:36:07 PM PDT 24
Peak memory 183016 kb
Host smart-198a842d-fe5a-451f-8155-8aa05ce78cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073946212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1073946212
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2770021805
Short name T301
Test name
Test status
Simulation time 372158468727 ps
CPU time 174.58 seconds
Started Jul 09 04:35:45 PM PDT 24
Finished Jul 09 04:38:40 PM PDT 24
Peak memory 191256 kb
Host smart-19df676a-d359-451d-8422-d49606917b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770021805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2770021805
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1162046708
Short name T368
Test name
Test status
Simulation time 90629984909 ps
CPU time 38.31 seconds
Started Jul 09 04:35:45 PM PDT 24
Finished Jul 09 04:36:24 PM PDT 24
Peak memory 182936 kb
Host smart-bf3b0c42-fea2-40f5-aa80-2883d917cd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162046708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1162046708
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2454169965
Short name T388
Test name
Test status
Simulation time 10935394381 ps
CPU time 62.77 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:37:04 PM PDT 24
Peak memory 182988 kb
Host smart-f3bbe358-cacc-4f2d-8d18-f6a444f3c6cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454169965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2454169965
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1886843179
Short name T246
Test name
Test status
Simulation time 30926662338 ps
CPU time 124.74 seconds
Started Jul 09 04:35:55 PM PDT 24
Finished Jul 09 04:38:00 PM PDT 24
Peak memory 182956 kb
Host smart-95367043-87fd-4f5b-a2af-15e252ab99ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886843179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1886843179
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2665906048
Short name T413
Test name
Test status
Simulation time 284198823142 ps
CPU time 244.42 seconds
Started Jul 09 04:35:52 PM PDT 24
Finished Jul 09 04:39:57 PM PDT 24
Peak memory 182984 kb
Host smart-c419b93a-db8c-4f68-af68-3ac44ca9dcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665906048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2665906048
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3358647923
Short name T389
Test name
Test status
Simulation time 7288891225 ps
CPU time 7.36 seconds
Started Jul 09 04:35:49 PM PDT 24
Finished Jul 09 04:35:56 PM PDT 24
Peak memory 182968 kb
Host smart-5a51a8ad-de99-4e02-8f1b-8a0ea4091758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358647923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3358647923
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2150660413
Short name T403
Test name
Test status
Simulation time 86466616927 ps
CPU time 91.44 seconds
Started Jul 09 04:35:51 PM PDT 24
Finished Jul 09 04:37:23 PM PDT 24
Peak memory 192616 kb
Host smart-23161fc3-9a35-4ae9-b989-74309512ff2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150660413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2150660413
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.3020222043
Short name T336
Test name
Test status
Simulation time 60087875015 ps
CPU time 34.89 seconds
Started Jul 09 04:36:00 PM PDT 24
Finished Jul 09 04:36:37 PM PDT 24
Peak memory 182948 kb
Host smart-a3b48166-b71c-4403-b09e-b066afaee7d1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020222043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.3020222043
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_random.4184075105
Short name T335
Test name
Test status
Simulation time 56028640714 ps
CPU time 570.46 seconds
Started Jul 09 04:35:47 PM PDT 24
Finished Jul 09 04:45:18 PM PDT 24
Peak memory 191240 kb
Host smart-789bf676-0a53-4543-a73c-35eaaa5acd8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184075105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.4184075105
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1110230018
Short name T170
Test name
Test status
Simulation time 95658969370 ps
CPU time 92.36 seconds
Started Jul 09 04:35:46 PM PDT 24
Finished Jul 09 04:37:18 PM PDT 24
Peak memory 183056 kb
Host smart-e9130dd9-4cb8-4bd3-8bad-a21d86d9f892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110230018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1110230018
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3412986594
Short name T168
Test name
Test status
Simulation time 831821910014 ps
CPU time 449.99 seconds
Started Jul 09 04:35:48 PM PDT 24
Finished Jul 09 04:43:19 PM PDT 24
Peak memory 182932 kb
Host smart-f2072baa-7e75-4362-9a7a-cf099fb4f2ec
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412986594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3412986594
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2470500619
Short name T367
Test name
Test status
Simulation time 522831238282 ps
CPU time 161.35 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:38:39 PM PDT 24
Peak memory 182992 kb
Host smart-b52c53be-fa9d-4ee3-80d9-f2d27897f879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470500619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2470500619
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.277443733
Short name T111
Test name
Test status
Simulation time 869777860059 ps
CPU time 1092.63 seconds
Started Jul 09 04:35:49 PM PDT 24
Finished Jul 09 04:54:03 PM PDT 24
Peak memory 191160 kb
Host smart-c7dc31af-94ca-4ff8-ace8-eb2103a7818b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277443733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.277443733
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2372468533
Short name T391
Test name
Test status
Simulation time 5386841642 ps
CPU time 7.74 seconds
Started Jul 09 04:35:46 PM PDT 24
Finished Jul 09 04:35:54 PM PDT 24
Peak memory 182904 kb
Host smart-d9829db2-f982-46bb-89ec-c99d92b8aed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372468533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2372468533
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1382817879
Short name T245
Test name
Test status
Simulation time 910059356991 ps
CPU time 1047.83 seconds
Started Jul 09 04:35:56 PM PDT 24
Finished Jul 09 04:53:25 PM PDT 24
Peak memory 195064 kb
Host smart-6d3fa065-8ce0-4f67-9c3f-7e47178fc395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382817879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1382817879
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3787779881
Short name T185
Test name
Test status
Simulation time 68214345446 ps
CPU time 106.64 seconds
Started Jul 09 04:35:48 PM PDT 24
Finished Jul 09 04:37:35 PM PDT 24
Peak memory 182968 kb
Host smart-9a84d2bb-78a2-42e5-9603-1259abf601c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787779881 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3787779881
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random.2743722950
Short name T446
Test name
Test status
Simulation time 947207846084 ps
CPU time 360.43 seconds
Started Jul 09 04:35:45 PM PDT 24
Finished Jul 09 04:41:46 PM PDT 24
Peak memory 191180 kb
Host smart-870e56ac-b714-41b5-a277-aeec72ec4d5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743722950 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2743722950
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.963216116
Short name T366
Test name
Test status
Simulation time 197666534 ps
CPU time 0.53 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:36:01 PM PDT 24
Peak memory 182768 kb
Host smart-6e3253a2-7088-420d-938d-49c213974437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963216116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.963216116
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.938633002
Short name T227
Test name
Test status
Simulation time 333886666520 ps
CPU time 217.63 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:39:38 PM PDT 24
Peak memory 191200 kb
Host smart-58339cd2-1efd-4d60-a3a6-669417002789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938633002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
938633002
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2774466460
Short name T271
Test name
Test status
Simulation time 149353996079 ps
CPU time 251.77 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:39:42 PM PDT 24
Peak memory 182948 kb
Host smart-e0f7ae01-7dcd-4faa-9fb0-421a233545c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774466460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2774466460
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2750408075
Short name T418
Test name
Test status
Simulation time 513907144488 ps
CPU time 222.98 seconds
Started Jul 09 04:26:39 PM PDT 24
Finished Jul 09 04:30:25 PM PDT 24
Peak memory 182524 kb
Host smart-da0ee4c1-7385-47e2-b945-9221405a0114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750408075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2750408075
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3969928749
Short name T45
Test name
Test status
Simulation time 75891994085 ps
CPU time 113.35 seconds
Started Jul 09 04:27:21 PM PDT 24
Finished Jul 09 04:29:19 PM PDT 24
Peak memory 191180 kb
Host smart-265b32a2-a265-42d7-bb0d-fe748b26c5ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969928749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3969928749
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.236909138
Short name T339
Test name
Test status
Simulation time 657312102966 ps
CPU time 496.87 seconds
Started Jul 09 04:35:24 PM PDT 24
Finished Jul 09 04:43:42 PM PDT 24
Peak memory 191196 kb
Host smart-d4a1ff1e-f737-4220-b5cb-9367819e85c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236909138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.236909138
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3580845754
Short name T16
Test name
Test status
Simulation time 434415753 ps
CPU time 0.87 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:35:31 PM PDT 24
Peak memory 213292 kb
Host smart-74a8b109-f2cd-4b44-8cab-8b8562a1624a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580845754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3580845754
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3706141345
Short name T138
Test name
Test status
Simulation time 472762045436 ps
CPU time 805.3 seconds
Started Jul 09 04:35:24 PM PDT 24
Finished Jul 09 04:48:50 PM PDT 24
Peak memory 191264 kb
Host smart-b45c539e-7355-4a2c-8cd1-0a6daa800bb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706141345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3706141345
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.896187542
Short name T35
Test name
Test status
Simulation time 18905778982 ps
CPU time 194.82 seconds
Started Jul 09 04:35:17 PM PDT 24
Finished Jul 09 04:38:33 PM PDT 24
Peak memory 197628 kb
Host smart-48908b88-5d6c-4ffb-a9a3-6ffa21bcb468
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896187542 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.896187542
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3007582370
Short name T192
Test name
Test status
Simulation time 545201484555 ps
CPU time 502.41 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:44:24 PM PDT 24
Peak memory 182964 kb
Host smart-96d833a4-cb07-4b94-b299-1777ab7ea0f7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007582370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3007582370
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1982523682
Short name T373
Test name
Test status
Simulation time 346411317668 ps
CPU time 123.46 seconds
Started Jul 09 04:36:02 PM PDT 24
Finished Jul 09 04:38:06 PM PDT 24
Peak memory 182952 kb
Host smart-da547178-322e-4f3f-a1e7-24e527337bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982523682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1982523682
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.344208181
Short name T176
Test name
Test status
Simulation time 204783871607 ps
CPU time 422.62 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:43:02 PM PDT 24
Peak memory 191176 kb
Host smart-fd58e0f6-d6d7-4ed2-be75-6d5d9d71d7be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344208181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.344208181
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1855057244
Short name T215
Test name
Test status
Simulation time 101132079852 ps
CPU time 474.73 seconds
Started Jul 09 04:35:44 PM PDT 24
Finished Jul 09 04:43:39 PM PDT 24
Peak memory 183024 kb
Host smart-49f7b1ad-c177-4cca-8d70-b6a7c88979ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855057244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1855057244
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.625628801
Short name T56
Test name
Test status
Simulation time 246800426946 ps
CPU time 612.86 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:46:13 PM PDT 24
Peak memory 191172 kb
Host smart-df12a076-2c07-4d94-94c2-4df5e70cfbec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625628801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
625628801
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3045410431
Short name T41
Test name
Test status
Simulation time 81656286952 ps
CPU time 131.79 seconds
Started Jul 09 04:35:56 PM PDT 24
Finished Jul 09 04:38:09 PM PDT 24
Peak memory 182940 kb
Host smart-085ff848-b7c2-4ee0-8ad4-fe53ada86406
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045410431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3045410431
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.1549848203
Short name T365
Test name
Test status
Simulation time 566570069433 ps
CPU time 103.63 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:37:43 PM PDT 24
Peak memory 182944 kb
Host smart-0e5a887f-d9d9-4a4c-9f3f-2f2f413b64f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549848203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.1549848203
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1057201812
Short name T100
Test name
Test status
Simulation time 395353526768 ps
CPU time 355.32 seconds
Started Jul 09 04:35:53 PM PDT 24
Finished Jul 09 04:41:49 PM PDT 24
Peak memory 191172 kb
Host smart-5ca3a152-df3a-4591-a772-4a9e1ffc77f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057201812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1057201812
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2153073109
Short name T425
Test name
Test status
Simulation time 96618094355 ps
CPU time 104.55 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:37:42 PM PDT 24
Peak memory 182948 kb
Host smart-d562acff-6e20-442a-a38c-6c040d2e9615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153073109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2153073109
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.1264429023
Short name T385
Test name
Test status
Simulation time 12067919840 ps
CPU time 4.75 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:36:06 PM PDT 24
Peak memory 182944 kb
Host smart-7727b332-8f90-4a61-9264-325e497ca2f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264429023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.1264429023
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3923159874
Short name T333
Test name
Test status
Simulation time 7517489402 ps
CPU time 13.07 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:36:11 PM PDT 24
Peak memory 182396 kb
Host smart-9fba2c19-4af4-47e6-b055-a2d877c16f0d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923159874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3923159874
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2030822104
Short name T419
Test name
Test status
Simulation time 106410299005 ps
CPU time 46.13 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:36:44 PM PDT 24
Peak memory 182888 kb
Host smart-252b8672-5bde-45b9-b885-fd6d85a1c2fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030822104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2030822104
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1367618155
Short name T230
Test name
Test status
Simulation time 126311934807 ps
CPU time 80.86 seconds
Started Jul 09 04:36:00 PM PDT 24
Finished Jul 09 04:37:23 PM PDT 24
Peak memory 191264 kb
Host smart-a7ff3c71-4b7e-4ff4-b51c-69c558546c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367618155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1367618155
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.262588428
Short name T295
Test name
Test status
Simulation time 41022877486 ps
CPU time 61.33 seconds
Started Jul 09 04:35:50 PM PDT 24
Finished Jul 09 04:36:52 PM PDT 24
Peak memory 182968 kb
Host smart-84c27a36-963b-4b9a-8bdd-140c150d0bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262588428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.262588428
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3023335176
Short name T429
Test name
Test status
Simulation time 495735608498 ps
CPU time 167.37 seconds
Started Jul 09 04:36:00 PM PDT 24
Finished Jul 09 04:38:49 PM PDT 24
Peak memory 183388 kb
Host smart-e26a4319-a391-493c-9312-935018432b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023335176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3023335176
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.1716056186
Short name T240
Test name
Test status
Simulation time 316612768040 ps
CPU time 117.66 seconds
Started Jul 09 04:36:04 PM PDT 24
Finished Jul 09 04:38:02 PM PDT 24
Peak memory 183004 kb
Host smart-6b2c1373-d672-4c86-93a6-dece8cff9bac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716056186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.1716056186
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.4028030974
Short name T432
Test name
Test status
Simulation time 367737339868 ps
CPU time 279.09 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:40:38 PM PDT 24
Peak memory 183000 kb
Host smart-925f2bd7-934e-4322-af6f-53c009b24b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028030974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.4028030974
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.185559075
Short name T426
Test name
Test status
Simulation time 46026747 ps
CPU time 0.53 seconds
Started Jul 09 04:35:55 PM PDT 24
Finished Jul 09 04:35:56 PM PDT 24
Peak memory 182796 kb
Host smart-fa138150-4add-43cb-851c-18952fee52a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185559075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.185559075
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2448685589
Short name T405
Test name
Test status
Simulation time 532319701229 ps
CPU time 678.46 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:47:16 PM PDT 24
Peak memory 190528 kb
Host smart-ca84dbbe-6ec3-4698-8145-311506e26df0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448685589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2448685589
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.4172884791
Short name T357
Test name
Test status
Simulation time 89804949408 ps
CPU time 60.1 seconds
Started Jul 09 04:35:52 PM PDT 24
Finished Jul 09 04:36:53 PM PDT 24
Peak memory 182940 kb
Host smart-ab1c2c32-c5ba-43a2-a2a7-72c968c2cf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172884791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4172884791
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1034847009
Short name T99
Test name
Test status
Simulation time 492308085892 ps
CPU time 310.6 seconds
Started Jul 09 04:35:52 PM PDT 24
Finished Jul 09 04:41:04 PM PDT 24
Peak memory 191176 kb
Host smart-54c60114-6874-4354-ac0a-647dbf2dc8bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034847009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1034847009
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3837064495
Short name T23
Test name
Test status
Simulation time 517408939 ps
CPU time 0.73 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:36:05 PM PDT 24
Peak memory 191452 kb
Host smart-1d42e666-38bc-4f53-881e-d60858677dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837064495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3837064495
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2391850788
Short name T370
Test name
Test status
Simulation time 293547432237 ps
CPU time 384.68 seconds
Started Jul 09 04:35:54 PM PDT 24
Finished Jul 09 04:42:20 PM PDT 24
Peak memory 195648 kb
Host smart-b7e7e6de-c4ab-4047-86b0-9cff5b17b909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391850788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2391850788
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.4166547835
Short name T136
Test name
Test status
Simulation time 74081678072 ps
CPU time 113.76 seconds
Started Jul 09 04:36:01 PM PDT 24
Finished Jul 09 04:37:56 PM PDT 24
Peak memory 182912 kb
Host smart-0f04aad9-0182-4947-8d2a-a8dc5ad9b458
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166547835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.4166547835
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2794628638
Short name T384
Test name
Test status
Simulation time 37026683542 ps
CPU time 30.94 seconds
Started Jul 09 04:35:54 PM PDT 24
Finished Jul 09 04:36:26 PM PDT 24
Peak memory 182960 kb
Host smart-d597abaa-cb9d-4cec-be85-8b101268cfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794628638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2794628638
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.2907858114
Short name T243
Test name
Test status
Simulation time 316174749390 ps
CPU time 213.1 seconds
Started Jul 09 04:36:03 PM PDT 24
Finished Jul 09 04:39:37 PM PDT 24
Peak memory 191180 kb
Host smart-24b8d4ef-abee-4fc3-a41c-29bbf707e8aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907858114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.2907858114
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.256206995
Short name T442
Test name
Test status
Simulation time 586255697 ps
CPU time 0.72 seconds
Started Jul 09 04:35:53 PM PDT 24
Finished Jul 09 04:35:55 PM PDT 24
Peak memory 182868 kb
Host smart-d0a479ea-bfb8-4a5c-a216-98992984550e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256206995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.256206995
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3678776599
Short name T144
Test name
Test status
Simulation time 252681621589 ps
CPU time 843.56 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:50:02 PM PDT 24
Peak memory 191200 kb
Host smart-62b3b98e-085b-40af-a179-21d09f5e29a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678776599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3678776599
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1476666160
Short name T48
Test name
Test status
Simulation time 805155326831 ps
CPU time 654.28 seconds
Started Jul 09 04:35:54 PM PDT 24
Finished Jul 09 04:46:49 PM PDT 24
Peak memory 182980 kb
Host smart-05db6457-6d33-44fa-8337-dd0c505c6ceb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476666160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1476666160
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1341056555
Short name T445
Test name
Test status
Simulation time 171922249101 ps
CPU time 248.04 seconds
Started Jul 09 04:35:56 PM PDT 24
Finished Jul 09 04:40:05 PM PDT 24
Peak memory 182984 kb
Host smart-b1b234fb-dc33-4c00-9477-4099dd35bba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341056555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1341056555
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.20513694
Short name T430
Test name
Test status
Simulation time 27151562662 ps
CPU time 43.66 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:36:45 PM PDT 24
Peak memory 182920 kb
Host smart-63a24685-2d01-46bc-9bc2-e4530aa0258a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20513694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.20513694
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.684797307
Short name T410
Test name
Test status
Simulation time 196818633839 ps
CPU time 130.03 seconds
Started Jul 09 04:36:01 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 191280 kb
Host smart-7367845f-2f01-4f7c-a486-dc8d21eae11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684797307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.684797307
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.1381944531
Short name T371
Test name
Test status
Simulation time 155414914941 ps
CPU time 135.06 seconds
Started Jul 09 04:35:50 PM PDT 24
Finished Jul 09 04:38:06 PM PDT 24
Peak memory 182948 kb
Host smart-1a1c07d2-5f2d-448c-a3ea-fc995e0d290e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381944531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.1381944531
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1132516046
Short name T360
Test name
Test status
Simulation time 292956566654 ps
CPU time 83.31 seconds
Started Jul 09 04:35:53 PM PDT 24
Finished Jul 09 04:37:18 PM PDT 24
Peak memory 182960 kb
Host smart-8cc27525-2843-4925-9f08-ba3693ecafd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132516046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1132516046
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.632432567
Short name T320
Test name
Test status
Simulation time 83371235550 ps
CPU time 63.44 seconds
Started Jul 09 04:35:56 PM PDT 24
Finished Jul 09 04:37:01 PM PDT 24
Peak memory 182948 kb
Host smart-26ea499d-5ba4-4ddf-b545-9edaeb71e412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632432567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.632432567
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.1007232213
Short name T129
Test name
Test status
Simulation time 20809124206 ps
CPU time 41.97 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:36:43 PM PDT 24
Peak memory 191112 kb
Host smart-8d8e6629-09f4-4215-bf60-1d2496c925a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007232213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.1007232213
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.387755207
Short name T415
Test name
Test status
Simulation time 12802929674 ps
CPU time 18.73 seconds
Started Jul 09 04:35:50 PM PDT 24
Finished Jul 09 04:36:10 PM PDT 24
Peak memory 183028 kb
Host smart-f2e21a86-88e5-4670-a88e-eb3d290e5873
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387755207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.387755207
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.900865905
Short name T397
Test name
Test status
Simulation time 62688472234 ps
CPU time 79.11 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:37:19 PM PDT 24
Peak memory 183004 kb
Host smart-d73997a3-3fa2-49e2-99d0-2c538a8b3cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900865905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.900865905
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1025868921
Short name T285
Test name
Test status
Simulation time 740744261801 ps
CPU time 248.58 seconds
Started Jul 09 04:35:50 PM PDT 24
Finished Jul 09 04:39:59 PM PDT 24
Peak memory 191176 kb
Host smart-c828f6a5-0bc3-4aef-aebb-a9d7ae8cc447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025868921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1025868921
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1810324789
Short name T338
Test name
Test status
Simulation time 27839636429 ps
CPU time 45.55 seconds
Started Jul 09 04:35:52 PM PDT 24
Finished Jul 09 04:36:38 PM PDT 24
Peak memory 182968 kb
Host smart-b2b4539e-339a-46d9-bc78-9550817046bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810324789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1810324789
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1739763107
Short name T381
Test name
Test status
Simulation time 733357785932 ps
CPU time 294.67 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:40:55 PM PDT 24
Peak memory 183124 kb
Host smart-ac244aff-1eae-4b79-97f3-fec5be00d2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739763107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1739763107
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3636940892
Short name T186
Test name
Test status
Simulation time 364144569771 ps
CPU time 174.49 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 04:38:53 PM PDT 24
Peak memory 183076 kb
Host smart-91e5423b-6903-483c-8f6c-425a20b1a7b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636940892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3636940892
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1622963422
Short name T364
Test name
Test status
Simulation time 7369540002 ps
CPU time 5.42 seconds
Started Jul 09 04:36:04 PM PDT 24
Finished Jul 09 04:36:10 PM PDT 24
Peak memory 182896 kb
Host smart-02a39090-dbd1-49f5-89c0-4f2a098bb291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622963422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1622963422
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.839778665
Short name T255
Test name
Test status
Simulation time 759455663182 ps
CPU time 754.68 seconds
Started Jul 09 04:36:06 PM PDT 24
Finished Jul 09 04:48:41 PM PDT 24
Peak memory 191316 kb
Host smart-c1961adc-98d7-44a8-aad0-3ea75b65aa2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839778665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.839778665
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3128860586
Short name T288
Test name
Test status
Simulation time 517741083629 ps
CPU time 189.96 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:39:10 PM PDT 24
Peak memory 191144 kb
Host smart-44dac9a4-54cd-4455-a7bb-f51d05219a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128860586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3128860586
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.913731672
Short name T251
Test name
Test status
Simulation time 2065460770314 ps
CPU time 829.81 seconds
Started Jul 09 04:35:56 PM PDT 24
Finished Jul 09 04:49:46 PM PDT 24
Peak memory 191280 kb
Host smart-70d6c121-9575-4a49-80a0-39f128cb3d57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913731672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
913731672
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3781772308
Short name T406
Test name
Test status
Simulation time 2928998530 ps
CPU time 5.65 seconds
Started Jul 09 04:35:17 PM PDT 24
Finished Jul 09 04:35:24 PM PDT 24
Peak memory 182932 kb
Host smart-9ac0c57b-1158-4247-9929-56df8e5a8892
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781772308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3781772308
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3712806540
Short name T390
Test name
Test status
Simulation time 882686128345 ps
CPU time 399.18 seconds
Started Jul 09 04:35:26 PM PDT 24
Finished Jul 09 04:42:06 PM PDT 24
Peak memory 182992 kb
Host smart-e3d6e58c-f086-4487-9fbb-4c6d12bfc5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712806540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3712806540
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.4174338822
Short name T98
Test name
Test status
Simulation time 73581781182 ps
CPU time 289.06 seconds
Started Jul 09 04:35:29 PM PDT 24
Finished Jul 09 04:40:21 PM PDT 24
Peak memory 191212 kb
Host smart-63bb3da9-d932-4ba9-af9a-1f43626b2189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174338822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.4174338822
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1454875385
Short name T428
Test name
Test status
Simulation time 1081574730772 ps
CPU time 446.25 seconds
Started Jul 09 04:35:26 PM PDT 24
Finished Jul 09 04:42:53 PM PDT 24
Peak memory 194416 kb
Host smart-4ec04b21-b6a4-4afa-92cf-64cea967f848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454875385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1454875385
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.2249773332
Short name T309
Test name
Test status
Simulation time 165798196197 ps
CPU time 1974.05 seconds
Started Jul 09 04:36:03 PM PDT 24
Finished Jul 09 05:08:57 PM PDT 24
Peak memory 191196 kb
Host smart-095546d2-7791-4afd-8520-ebb326d7cfa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249773332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2249773332
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2954074475
Short name T189
Test name
Test status
Simulation time 722649216617 ps
CPU time 658.61 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:46:59 PM PDT 24
Peak memory 191196 kb
Host smart-41a6e2e5-5912-466b-a89a-8b37cc747c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954074475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2954074475
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2926816483
Short name T200
Test name
Test status
Simulation time 140321703535 ps
CPU time 431.67 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:43:13 PM PDT 24
Peak memory 191240 kb
Host smart-d093d207-cd10-4efe-b84b-c36cef751887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926816483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2926816483
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2030295663
Short name T421
Test name
Test status
Simulation time 251597115614 ps
CPU time 352.78 seconds
Started Jul 09 04:36:01 PM PDT 24
Finished Jul 09 04:41:55 PM PDT 24
Peak memory 191252 kb
Host smart-b66f0ec3-f7b7-478b-9b84-3b0b178027f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030295663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2030295663
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2172655222
Short name T130
Test name
Test status
Simulation time 749437188922 ps
CPU time 223.81 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:39:43 PM PDT 24
Peak memory 191204 kb
Host smart-1cce8f8a-7aed-46f2-a6c2-57c9f3017756
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172655222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2172655222
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.899651672
Short name T161
Test name
Test status
Simulation time 658467969525 ps
CPU time 1435.51 seconds
Started Jul 09 04:35:56 PM PDT 24
Finished Jul 09 04:59:52 PM PDT 24
Peak memory 191324 kb
Host smart-77f20eaa-f6ad-4692-aa6d-4e37a5689206
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899651672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.899651672
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2044644928
Short name T299
Test name
Test status
Simulation time 376328750 ps
CPU time 1.59 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:36:03 PM PDT 24
Peak memory 183244 kb
Host smart-1314c92e-6f9a-4cfa-920e-8ead4dc826c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044644928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2044644928
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.2456735133
Short name T444
Test name
Test status
Simulation time 122813327487 ps
CPU time 98.37 seconds
Started Jul 09 04:35:17 PM PDT 24
Finished Jul 09 04:36:57 PM PDT 24
Peak memory 182932 kb
Host smart-00d6cfa0-1f8e-4bce-9a39-653a02cb766b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456735133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.2456735133
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.846029459
Short name T422
Test name
Test status
Simulation time 35142523544 ps
CPU time 52.39 seconds
Started Jul 09 04:35:30 PM PDT 24
Finished Jul 09 04:36:25 PM PDT 24
Peak memory 182984 kb
Host smart-3419132f-4fe1-4fc0-a28f-981dc9bcb022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846029459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.846029459
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3283613449
Short name T319
Test name
Test status
Simulation time 31962363492 ps
CPU time 53.82 seconds
Started Jul 09 04:35:28 PM PDT 24
Finished Jul 09 04:36:24 PM PDT 24
Peak memory 182976 kb
Host smart-36277d2d-159a-4875-9b05-c677d542304d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283613449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3283613449
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2823337717
Short name T194
Test name
Test status
Simulation time 199830069590 ps
CPU time 88.63 seconds
Started Jul 09 04:35:18 PM PDT 24
Finished Jul 09 04:36:48 PM PDT 24
Peak memory 191148 kb
Host smart-b61ef7e1-177d-4449-aed2-a3cea7f2c402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823337717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2823337717
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2652029562
Short name T36
Test name
Test status
Simulation time 285442161696 ps
CPU time 582.97 seconds
Started Jul 09 04:35:22 PM PDT 24
Finished Jul 09 04:45:06 PM PDT 24
Peak memory 207948 kb
Host smart-08ade70b-7c66-4eeb-a41b-e98485428733
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652029562 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2652029562
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.2416545402
Short name T290
Test name
Test status
Simulation time 73234135785 ps
CPU time 54.16 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:36:54 PM PDT 24
Peak memory 182980 kb
Host smart-9e880b92-1e52-465e-bf99-9b745ec9f276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416545402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2416545402
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3819319928
Short name T307
Test name
Test status
Simulation time 42208793544 ps
CPU time 66.57 seconds
Started Jul 09 04:35:56 PM PDT 24
Finished Jul 09 04:37:03 PM PDT 24
Peak memory 191196 kb
Host smart-515a7be1-c0db-4a58-bb7e-bb9256b0f6f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819319928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3819319928
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.2225379138
Short name T149
Test name
Test status
Simulation time 66610291651 ps
CPU time 105.24 seconds
Started Jul 09 04:36:01 PM PDT 24
Finished Jul 09 04:37:48 PM PDT 24
Peak memory 191204 kb
Host smart-fbb907a8-b43d-4c46-8e8c-667e60eb2102
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225379138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2225379138
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1655555133
Short name T377
Test name
Test status
Simulation time 12479293281 ps
CPU time 22.01 seconds
Started Jul 09 04:36:03 PM PDT 24
Finished Jul 09 04:36:26 PM PDT 24
Peak memory 182992 kb
Host smart-7eece81e-11df-4229-acf1-86a23001a560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655555133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1655555133
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1067518724
Short name T235
Test name
Test status
Simulation time 239204867934 ps
CPU time 222.78 seconds
Started Jul 09 04:36:00 PM PDT 24
Finished Jul 09 04:39:45 PM PDT 24
Peak memory 194640 kb
Host smart-ec75cb91-a792-4df4-9960-1a308c5efd31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067518724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1067518724
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.620579619
Short name T257
Test name
Test status
Simulation time 409035407053 ps
CPU time 1944.91 seconds
Started Jul 09 04:35:57 PM PDT 24
Finished Jul 09 05:08:24 PM PDT 24
Peak memory 191128 kb
Host smart-513c0b3f-ca80-4fb0-9f2a-66f8b624139e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620579619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.620579619
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1188875150
Short name T150
Test name
Test status
Simulation time 262738865431 ps
CPU time 163.18 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:38:44 PM PDT 24
Peak memory 191240 kb
Host smart-880d4864-d176-41ac-b336-57e95a3a6825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188875150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1188875150
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1289717159
Short name T423
Test name
Test status
Simulation time 64720525129 ps
CPU time 39.96 seconds
Started Jul 09 04:35:25 PM PDT 24
Finished Jul 09 04:36:06 PM PDT 24
Peak memory 183000 kb
Host smart-2efd60e9-7c07-4337-a769-b643332d1f99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289717159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1289717159
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3071757425
Short name T376
Test name
Test status
Simulation time 357467478313 ps
CPU time 142.81 seconds
Started Jul 09 04:35:24 PM PDT 24
Finished Jul 09 04:37:48 PM PDT 24
Peak memory 182968 kb
Host smart-2ade6c5c-ea1e-4b8c-add1-28dc3d1f4b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071757425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3071757425
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.447601098
Short name T297
Test name
Test status
Simulation time 58656019950 ps
CPU time 243.49 seconds
Started Jul 09 04:35:27 PM PDT 24
Finished Jul 09 04:39:32 PM PDT 24
Peak memory 191188 kb
Host smart-769de664-87c8-4c87-a0e3-5e6b953875fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447601098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.447601098
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1572839477
Short name T224
Test name
Test status
Simulation time 43273471465 ps
CPU time 47.89 seconds
Started Jul 09 04:35:22 PM PDT 24
Finished Jul 09 04:36:11 PM PDT 24
Peak memory 191216 kb
Host smart-88600c63-8e5d-4fc5-a0dd-a4585f5b2d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572839477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1572839477
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2999032317
Short name T6
Test name
Test status
Simulation time 717442175767 ps
CPU time 517.3 seconds
Started Jul 09 04:35:18 PM PDT 24
Finished Jul 09 04:43:57 PM PDT 24
Peak memory 194576 kb
Host smart-0e4b67e7-2643-42b0-b24d-2ed0fcd31090
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999032317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2999032317
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.4292340338
Short name T96
Test name
Test status
Simulation time 234158784574 ps
CPU time 97.14 seconds
Started Jul 09 04:35:56 PM PDT 24
Finished Jul 09 04:37:34 PM PDT 24
Peak memory 182932 kb
Host smart-a3d421ec-1738-4649-8399-e4a285403c29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292340338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.4292340338
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1748993932
Short name T223
Test name
Test status
Simulation time 141666200130 ps
CPU time 555.72 seconds
Started Jul 09 04:35:58 PM PDT 24
Finished Jul 09 04:45:15 PM PDT 24
Peak memory 193908 kb
Host smart-6bb07c37-3f57-4394-99b4-c4e743ff39c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748993932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1748993932
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.3786739148
Short name T228
Test name
Test status
Simulation time 155768902800 ps
CPU time 454.29 seconds
Started Jul 09 04:36:01 PM PDT 24
Finished Jul 09 04:43:37 PM PDT 24
Peak memory 191260 kb
Host smart-64df29d5-49d8-4224-a4e5-f02c618ed601
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786739148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.3786739148
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.1970185674
Short name T267
Test name
Test status
Simulation time 131379767771 ps
CPU time 210.53 seconds
Started Jul 09 04:36:10 PM PDT 24
Finished Jul 09 04:39:41 PM PDT 24
Peak memory 191176 kb
Host smart-9846dbc1-998a-4cfd-b8a9-0e4f2a496354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970185674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1970185674
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2752297523
Short name T137
Test name
Test status
Simulation time 137476744490 ps
CPU time 198.79 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:39:20 PM PDT 24
Peak memory 191140 kb
Host smart-5f03557b-cea2-46aa-a194-c084e2c9973e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752297523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2752297523
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3910752888
Short name T262
Test name
Test status
Simulation time 63778258949 ps
CPU time 1091.13 seconds
Started Jul 09 04:36:14 PM PDT 24
Finished Jul 09 04:54:26 PM PDT 24
Peak memory 191116 kb
Host smart-ece2583b-bfa0-46a1-bdee-75dcd5ecd56e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910752888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3910752888
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3381763904
Short name T323
Test name
Test status
Simulation time 503047687825 ps
CPU time 828.41 seconds
Started Jul 09 04:36:11 PM PDT 24
Finished Jul 09 04:50:00 PM PDT 24
Peak memory 191196 kb
Host smart-214f04dc-1644-4b8a-a59c-0772f03cbe5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381763904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3381763904
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.2542573633
Short name T270
Test name
Test status
Simulation time 239903132926 ps
CPU time 288.38 seconds
Started Jul 09 04:36:09 PM PDT 24
Finished Jul 09 04:40:58 PM PDT 24
Peak memory 191164 kb
Host smart-1c495ce2-ae43-4b80-b70c-e4989d5dff60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542573633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.2542573633
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2832643150
Short name T256
Test name
Test status
Simulation time 755686688647 ps
CPU time 354.44 seconds
Started Jul 09 04:36:01 PM PDT 24
Finished Jul 09 04:41:57 PM PDT 24
Peak memory 191140 kb
Host smart-d367410f-5095-4f80-8410-4b064e151bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832643150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2832643150
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1612206076
Short name T26
Test name
Test status
Simulation time 112757521065 ps
CPU time 173.4 seconds
Started Jul 09 04:35:30 PM PDT 24
Finished Jul 09 04:38:26 PM PDT 24
Peak memory 183068 kb
Host smart-e60c91e5-3b43-44b3-939a-35248eb635fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612206076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1612206076
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.4104808645
Short name T411
Test name
Test status
Simulation time 579758595508 ps
CPU time 171.62 seconds
Started Jul 09 04:35:31 PM PDT 24
Finished Jul 09 04:38:25 PM PDT 24
Peak memory 182992 kb
Host smart-1c6c3c0b-6d82-450f-aa2b-12645cae1433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104808645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.4104808645
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.707483084
Short name T102
Test name
Test status
Simulation time 90339307936 ps
CPU time 458.67 seconds
Started Jul 09 04:35:23 PM PDT 24
Finished Jul 09 04:43:02 PM PDT 24
Peak memory 191172 kb
Host smart-7c3893db-870d-47a5-908b-3c95fb0edf3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707483084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.707483084
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.167879553
Short name T124
Test name
Test status
Simulation time 6432497408 ps
CPU time 10.02 seconds
Started Jul 09 04:35:27 PM PDT 24
Finished Jul 09 04:35:39 PM PDT 24
Peak memory 182960 kb
Host smart-3c7cd5f8-1d3f-49fb-8fe5-a2074fbc9ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167879553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.167879553
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.854468391
Short name T315
Test name
Test status
Simulation time 1480206767992 ps
CPU time 740.45 seconds
Started Jul 09 04:35:19 PM PDT 24
Finished Jul 09 04:47:40 PM PDT 24
Peak memory 191196 kb
Host smart-f8b3a630-76b4-43bc-a5b3-4a4427dd0d6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854468391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.854468391
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.2078635651
Short name T191
Test name
Test status
Simulation time 282222074903 ps
CPU time 118.68 seconds
Started Jul 09 04:36:05 PM PDT 24
Finished Jul 09 04:38:04 PM PDT 24
Peak memory 191164 kb
Host smart-52d0d840-63f7-410c-a5f7-2e88f43298f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078635651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.2078635651
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1437078659
Short name T106
Test name
Test status
Simulation time 90479980353 ps
CPU time 68.72 seconds
Started Jul 09 04:36:09 PM PDT 24
Finished Jul 09 04:37:18 PM PDT 24
Peak memory 182964 kb
Host smart-2edd985a-3fc2-4e8d-8353-c7170354d431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437078659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1437078659
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.566326417
Short name T303
Test name
Test status
Simulation time 150028290131 ps
CPU time 344.65 seconds
Started Jul 09 04:36:05 PM PDT 24
Finished Jul 09 04:41:51 PM PDT 24
Peak memory 191176 kb
Host smart-5cfd4afd-5263-413b-82e7-807326603aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566326417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.566326417
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3066472067
Short name T27
Test name
Test status
Simulation time 222769559283 ps
CPU time 112.73 seconds
Started Jul 09 04:36:00 PM PDT 24
Finished Jul 09 04:37:54 PM PDT 24
Peak memory 191164 kb
Host smart-211c2779-636c-4e9c-9c02-82a66f476a59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066472067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3066472067
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2577976065
Short name T263
Test name
Test status
Simulation time 18670856001 ps
CPU time 83.34 seconds
Started Jul 09 04:36:11 PM PDT 24
Finished Jul 09 04:37:34 PM PDT 24
Peak memory 182928 kb
Host smart-1466cfdc-d9e6-4263-bf1e-4c38fef1e438
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577976065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2577976065
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.3864677650
Short name T159
Test name
Test status
Simulation time 219361286155 ps
CPU time 2263.95 seconds
Started Jul 09 04:36:07 PM PDT 24
Finished Jul 09 05:13:51 PM PDT 24
Peak memory 191176 kb
Host smart-76bdb175-7f25-4b5b-80e1-0c8f64dc4afd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864677650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.3864677650
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1568175326
Short name T265
Test name
Test status
Simulation time 137626666845 ps
CPU time 128.79 seconds
Started Jul 09 04:36:03 PM PDT 24
Finished Jul 09 04:38:12 PM PDT 24
Peak memory 191596 kb
Host smart-820a50f4-2089-4831-9fca-c3b27db489de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568175326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1568175326
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1145689197
Short name T289
Test name
Test status
Simulation time 368194107214 ps
CPU time 1022.93 seconds
Started Jul 09 04:36:16 PM PDT 24
Finished Jul 09 04:53:19 PM PDT 24
Peak memory 191188 kb
Host smart-685d62b0-c492-4dd6-8c76-0eb1d33a710c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145689197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1145689197
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2450554463
Short name T164
Test name
Test status
Simulation time 18336213822 ps
CPU time 17.94 seconds
Started Jul 09 04:35:18 PM PDT 24
Finished Jul 09 04:35:37 PM PDT 24
Peak memory 183000 kb
Host smart-4d626de8-451b-40f9-a546-1625a41973d8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450554463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2450554463
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2827866717
Short name T439
Test name
Test status
Simulation time 40929916555 ps
CPU time 52.54 seconds
Started Jul 09 04:35:21 PM PDT 24
Finished Jul 09 04:36:15 PM PDT 24
Peak memory 182888 kb
Host smart-05a0391f-ce89-4ddc-ae05-5c9c4bed3c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827866717 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2827866717
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2007570162
Short name T242
Test name
Test status
Simulation time 154509530118 ps
CPU time 66.49 seconds
Started Jul 09 04:35:29 PM PDT 24
Finished Jul 09 04:36:38 PM PDT 24
Peak memory 182952 kb
Host smart-1222463a-4488-45ec-a9ec-f30c3e6bd563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007570162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2007570162
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2498979433
Short name T37
Test name
Test status
Simulation time 27828464322 ps
CPU time 300.26 seconds
Started Jul 09 04:35:32 PM PDT 24
Finished Jul 09 04:40:33 PM PDT 24
Peak memory 205884 kb
Host smart-5108c55b-1e74-427a-bee1-48ffc5a4cb6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498979433 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2498979433
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.3928070671
Short name T203
Test name
Test status
Simulation time 474252372977 ps
CPU time 96.62 seconds
Started Jul 09 04:36:07 PM PDT 24
Finished Jul 09 04:37:44 PM PDT 24
Peak memory 183072 kb
Host smart-1dabc483-521c-43d2-a19a-d8f552e67387
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928070671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.3928070671
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1245957321
Short name T162
Test name
Test status
Simulation time 934865788573 ps
CPU time 633.44 seconds
Started Jul 09 04:36:00 PM PDT 24
Finished Jul 09 04:46:35 PM PDT 24
Peak memory 191140 kb
Host smart-732dcecf-f392-43aa-a3c6-eb5fd122f9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245957321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1245957321
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3140314994
Short name T277
Test name
Test status
Simulation time 303795758837 ps
CPU time 712.55 seconds
Started Jul 09 04:35:59 PM PDT 24
Finished Jul 09 04:47:53 PM PDT 24
Peak memory 191180 kb
Host smart-ab61725a-d450-4a81-bb1e-854faa6ff554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140314994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3140314994
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3922138683
Short name T116
Test name
Test status
Simulation time 84307856189 ps
CPU time 106.01 seconds
Started Jul 09 04:36:12 PM PDT 24
Finished Jul 09 04:37:58 PM PDT 24
Peak memory 191180 kb
Host smart-a5a2cd2f-0a35-405e-9f0e-3f09d9e35578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922138683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3922138683
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.85727647
Short name T173
Test name
Test status
Simulation time 38807842825 ps
CPU time 85.72 seconds
Started Jul 09 04:36:08 PM PDT 24
Finished Jul 09 04:37:35 PM PDT 24
Peak memory 191188 kb
Host smart-b55526d3-caad-42b6-8c28-f51cbb7d71e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85727647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.85727647
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1846119967
Short name T198
Test name
Test status
Simulation time 7776434560 ps
CPU time 11.19 seconds
Started Jul 09 04:36:09 PM PDT 24
Finished Jul 09 04:36:21 PM PDT 24
Peak memory 182972 kb
Host smart-689ec962-82ad-4f5a-9353-c9a2c58b601f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846119967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1846119967
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3546252496
Short name T113
Test name
Test status
Simulation time 180416701594 ps
CPU time 648.59 seconds
Started Jul 09 04:36:08 PM PDT 24
Finished Jul 09 04:46:57 PM PDT 24
Peak memory 191172 kb
Host smart-0714f53b-1997-4602-a027-3cc06fd99d0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546252496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3546252496
Directory /workspace/99.rv_timer_random/latest
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