Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
123693336 |
1 |
|
T1 |
655943 |
|
T2 |
216834 |
|
T3 |
785 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54633377 |
1 |
|
T1 |
82 |
|
T2 |
103128 |
|
T3 |
6 |
auto[1] |
69059959 |
1 |
|
T1 |
655861 |
|
T2 |
113706 |
|
T3 |
779 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
123687532 |
1 |
|
T1 |
655936 |
|
T2 |
216831 |
|
T3 |
785 |
auto[1] |
5804 |
1 |
|
T1 |
7 |
|
T2 |
30 |
|
T5 |
7 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
cp_intr | cp_intr_en | cp_intr_state | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
auto[0] |
auto[0] |
54630439 |
1 |
|
T1 |
80 |
|
T2 |
103127 |
|
T3 |
6 |
all_values[0] |
auto[0] |
auto[1] |
2938 |
1 |
|
T1 |
2 |
|
T2 |
14 |
|
T5 |
4 |
all_values[0] |
auto[1] |
auto[0] |
69057093 |
1 |
|
T1 |
655856 |
|
T2 |
113704 |
|
T3 |
779 |
all_values[0] |
auto[1] |
auto[1] |
2866 |
1 |
|
T1 |
5 |
|
T2 |
16 |
|
T5 |
3 |