Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 576
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2541301986 Jul 10 06:25:10 PM PDT 24 Jul 10 06:25:14 PM PDT 24 320614997 ps
T509 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1165590364 Jul 10 06:25:17 PM PDT 24 Jul 10 06:25:20 PM PDT 24 40774306 ps
T510 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3352704766 Jul 10 06:25:27 PM PDT 24 Jul 10 06:25:32 PM PDT 24 16473367 ps
T511 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4046071131 Jul 10 06:25:24 PM PDT 24 Jul 10 06:25:26 PM PDT 24 44436975 ps
T512 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2644509358 Jul 10 06:25:11 PM PDT 24 Jul 10 06:25:15 PM PDT 24 138293421 ps
T513 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2382786188 Jul 10 06:25:26 PM PDT 24 Jul 10 06:25:31 PM PDT 24 49214010 ps
T514 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.592512923 Jul 10 06:25:23 PM PDT 24 Jul 10 06:25:25 PM PDT 24 26805086 ps
T515 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1783392662 Jul 10 06:25:08 PM PDT 24 Jul 10 06:25:10 PM PDT 24 63682032 ps
T516 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3314075283 Jul 10 06:25:27 PM PDT 24 Jul 10 06:25:34 PM PDT 24 797846455 ps
T517 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.372655445 Jul 10 06:25:16 PM PDT 24 Jul 10 06:25:19 PM PDT 24 32112863 ps
T518 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1601148126 Jul 10 06:25:16 PM PDT 24 Jul 10 06:25:21 PM PDT 24 46733015 ps
T519 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3258442352 Jul 10 06:25:05 PM PDT 24 Jul 10 06:25:06 PM PDT 24 18756147 ps
T520 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3402287830 Jul 10 06:25:11 PM PDT 24 Jul 10 06:25:13 PM PDT 24 38991585 ps
T85 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3198486159 Jul 10 06:25:32 PM PDT 24 Jul 10 06:25:37 PM PDT 24 29073274 ps
T88 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2359581303 Jul 10 06:25:25 PM PDT 24 Jul 10 06:25:28 PM PDT 24 32059355 ps
T521 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2683849246 Jul 10 06:25:28 PM PDT 24 Jul 10 06:25:34 PM PDT 24 16716696 ps
T522 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4098144765 Jul 10 06:25:27 PM PDT 24 Jul 10 06:25:32 PM PDT 24 14307189 ps
T89 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.13583665 Jul 10 06:25:09 PM PDT 24 Jul 10 06:25:10 PM PDT 24 14035826 ps
T523 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2887673028 Jul 10 06:25:24 PM PDT 24 Jul 10 06:25:26 PM PDT 24 14426774 ps
T524 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3518936509 Jul 10 06:25:16 PM PDT 24 Jul 10 06:25:19 PM PDT 24 38990978 ps
T525 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1388235994 Jul 10 06:25:24 PM PDT 24 Jul 10 06:25:27 PM PDT 24 20934471 ps
T526 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1319400432 Jul 10 06:25:17 PM PDT 24 Jul 10 06:25:22 PM PDT 24 80029229 ps
T527 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3157484141 Jul 10 06:25:16 PM PDT 24 Jul 10 06:25:20 PM PDT 24 52525624 ps
T86 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4080920652 Jul 10 06:25:16 PM PDT 24 Jul 10 06:25:19 PM PDT 24 14660827 ps
T528 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2356478266 Jul 10 06:25:19 PM PDT 24 Jul 10 06:25:23 PM PDT 24 123615463 ps
T87 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3532246833 Jul 10 06:25:21 PM PDT 24 Jul 10 06:25:23 PM PDT 24 110169252 ps
T529 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.704829776 Jul 10 06:25:25 PM PDT 24 Jul 10 06:25:29 PM PDT 24 37832009 ps
T530 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3707578586 Jul 10 06:25:16 PM PDT 24 Jul 10 06:25:21 PM PDT 24 384003129 ps
T531 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.665768984 Jul 10 06:25:28 PM PDT 24 Jul 10 06:25:34 PM PDT 24 79336761 ps
T532 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1774826156 Jul 10 06:25:07 PM PDT 24 Jul 10 06:25:09 PM PDT 24 289649421 ps
T533 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2931135510 Jul 10 06:25:06 PM PDT 24 Jul 10 06:25:08 PM PDT 24 426298407 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1719123816 Jul 10 06:25:07 PM PDT 24 Jul 10 06:25:08 PM PDT 24 28832191 ps
T535 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.785419873 Jul 10 06:25:22 PM PDT 24 Jul 10 06:25:24 PM PDT 24 26609003 ps
T536 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.305890695 Jul 10 06:25:07 PM PDT 24 Jul 10 06:25:09 PM PDT 24 42701111 ps
T537 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2763556900 Jul 10 06:25:27 PM PDT 24 Jul 10 06:25:32 PM PDT 24 11918108 ps
T538 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1018561806 Jul 10 06:25:26 PM PDT 24 Jul 10 06:25:31 PM PDT 24 13523563 ps
T539 /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2030573342 Jul 10 06:25:27 PM PDT 24 Jul 10 06:25:33 PM PDT 24 27793770 ps
T540 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.537484205 Jul 10 06:25:23 PM PDT 24 Jul 10 06:25:24 PM PDT 24 156172792 ps
T541 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1401928228 Jul 10 06:25:17 PM PDT 24 Jul 10 06:25:20 PM PDT 24 168147283 ps
T542 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1162690040 Jul 10 06:25:29 PM PDT 24 Jul 10 06:25:36 PM PDT 24 69264712 ps
T543 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1118132165 Jul 10 06:25:29 PM PDT 24 Jul 10 06:25:34 PM PDT 24 10486416 ps
T544 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4146454946 Jul 10 06:25:03 PM PDT 24 Jul 10 06:25:05 PM PDT 24 56424242 ps
T545 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1030227584 Jul 10 06:25:30 PM PDT 24 Jul 10 06:25:35 PM PDT 24 11761454 ps
T546 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1829331851 Jul 10 06:25:27 PM PDT 24 Jul 10 06:25:33 PM PDT 24 144352175 ps
T547 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2109148947 Jul 10 06:25:26 PM PDT 24 Jul 10 06:25:30 PM PDT 24 14301959 ps
T90 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.203498392 Jul 10 06:25:02 PM PDT 24 Jul 10 06:25:04 PM PDT 24 27287420 ps
T548 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1245751738 Jul 10 06:25:29 PM PDT 24 Jul 10 06:25:35 PM PDT 24 27807062 ps
T549 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.595694560 Jul 10 06:25:26 PM PDT 24 Jul 10 06:25:33 PM PDT 24 158236672 ps
T550 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1184520553 Jul 10 06:25:31 PM PDT 24 Jul 10 06:25:36 PM PDT 24 28473355 ps
T551 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2117444546 Jul 10 06:25:17 PM PDT 24 Jul 10 06:25:21 PM PDT 24 67027531 ps
T552 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4221279382 Jul 10 06:25:24 PM PDT 24 Jul 10 06:25:27 PM PDT 24 121250549 ps
T553 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1978818404 Jul 10 06:25:04 PM PDT 24 Jul 10 06:25:08 PM PDT 24 679355556 ps
T91 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2986371860 Jul 10 06:25:03 PM PDT 24 Jul 10 06:25:05 PM PDT 24 53435099 ps
T554 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.452324440 Jul 10 06:25:29 PM PDT 24 Jul 10 06:25:35 PM PDT 24 60327301 ps
T555 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2100059211 Jul 10 06:25:27 PM PDT 24 Jul 10 06:25:32 PM PDT 24 34736868 ps
T556 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1226651979 Jul 10 06:25:25 PM PDT 24 Jul 10 06:25:32 PM PDT 24 729137342 ps
T557 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3708874551 Jul 10 06:25:26 PM PDT 24 Jul 10 06:25:31 PM PDT 24 21588405 ps
T558 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1773045422 Jul 10 06:25:16 PM PDT 24 Jul 10 06:25:20 PM PDT 24 81765490 ps
T559 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3313635153 Jul 10 06:25:25 PM PDT 24 Jul 10 06:25:29 PM PDT 24 28332183 ps
T560 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4203014258 Jul 10 06:25:17 PM PDT 24 Jul 10 06:25:21 PM PDT 24 13256444 ps
T561 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.421356305 Jul 10 06:25:12 PM PDT 24 Jul 10 06:25:14 PM PDT 24 23704197 ps
T562 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1350985152 Jul 10 06:25:04 PM PDT 24 Jul 10 06:25:06 PM PDT 24 96335328 ps
T563 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3987531050 Jul 10 06:25:02 PM PDT 24 Jul 10 06:25:07 PM PDT 24 3862800971 ps
T564 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3667896040 Jul 10 06:25:16 PM PDT 24 Jul 10 06:25:19 PM PDT 24 35422976 ps
T565 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.134562272 Jul 10 06:25:10 PM PDT 24 Jul 10 06:25:12 PM PDT 24 13434977 ps
T566 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1758323219 Jul 10 06:25:16 PM PDT 24 Jul 10 06:25:20 PM PDT 24 111296690 ps
T567 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.83050284 Jul 10 06:25:17 PM PDT 24 Jul 10 06:25:21 PM PDT 24 18467085 ps
T568 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3109227493 Jul 10 06:25:25 PM PDT 24 Jul 10 06:25:29 PM PDT 24 63859902 ps
T569 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1834586820 Jul 10 06:25:29 PM PDT 24 Jul 10 06:25:35 PM PDT 24 14286895 ps
T570 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2672598991 Jul 10 06:25:16 PM PDT 24 Jul 10 06:25:19 PM PDT 24 29166353 ps
T571 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4223127457 Jul 10 06:25:01 PM PDT 24 Jul 10 06:25:02 PM PDT 24 14571088 ps
T572 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.654866216 Jul 10 06:25:26 PM PDT 24 Jul 10 06:25:30 PM PDT 24 47280824 ps
T573 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2309552868 Jul 10 06:25:15 PM PDT 24 Jul 10 06:25:17 PM PDT 24 28228269 ps
T574 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3218286182 Jul 10 06:25:21 PM PDT 24 Jul 10 06:25:23 PM PDT 24 37565125 ps
T575 /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4198268427 Jul 10 06:25:10 PM PDT 24 Jul 10 06:25:12 PM PDT 24 34926754 ps
T576 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2479327673 Jul 10 06:25:25 PM PDT 24 Jul 10 06:25:30 PM PDT 24 458619753 ps

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.3314779576
Short name T6
Test name
Test status
Simulation time 65702240393 ps
CPU time 569.56 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:35:10 PM PDT 24
Peak memory 206392 kb
Host smart-38b184e7-62c2-4eef-903e-5958c6f502b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314779576 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.3314779576
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.4277232408
Short name T42
Test name
Test status
Simulation time 102141442342 ps
CPU time 207.06 seconds
Started Jul 10 06:26:27 PM PDT 24
Finished Jul 10 06:29:55 PM PDT 24
Peak memory 191344 kb
Host smart-0aaf5c27-e802-40c8-9d00-e9561bea23be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277232408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4277232408
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.1156235408
Short name T103
Test name
Test status
Simulation time 508094361263 ps
CPU time 2738.94 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 07:11:45 PM PDT 24
Peak memory 191340 kb
Host smart-2d3b962f-bdc7-4596-9c6e-5d24f28eaac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156235408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.1156235408
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1300983507
Short name T29
Test name
Test status
Simulation time 99155820 ps
CPU time 1.33 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:20 PM PDT 24
Peak memory 195116 kb
Host smart-fd536f58-2336-4a0c-9f83-7656d315d2dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300983507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1300983507
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1021805670
Short name T133
Test name
Test status
Simulation time 6344252649420 ps
CPU time 6064.89 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 08:06:53 PM PDT 24
Peak memory 195860 kb
Host smart-09a284e9-1260-4cca-ac89-4766eee2f7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021805670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1021805670
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.1529786887
Short name T2
Test name
Test status
Simulation time 7126813446850 ps
CPU time 2258.32 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 07:03:20 PM PDT 24
Peak memory 191340 kb
Host smart-e9ada782-5717-47f6-b1ea-2460bc22c184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529786887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
1529786887
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.520863626
Short name T160
Test name
Test status
Simulation time 772695938826 ps
CPU time 2483.93 seconds
Started Jul 10 06:26:00 PM PDT 24
Finished Jul 10 07:07:25 PM PDT 24
Peak memory 195416 kb
Host smart-5d85c968-43e7-45f0-a4da-79d7b66fae53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520863626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
520863626
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2760016427
Short name T69
Test name
Test status
Simulation time 5886964364538 ps
CPU time 1727.31 seconds
Started Jul 10 06:25:50 PM PDT 24
Finished Jul 10 06:54:39 PM PDT 24
Peak memory 191360 kb
Host smart-d2eded39-00d1-4096-a0c9-7fe2eb0260c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760016427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2760016427
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.635453551
Short name T66
Test name
Test status
Simulation time 6537524120517 ps
CPU time 2320.49 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 07:04:52 PM PDT 24
Peak memory 195792 kb
Host smart-7389a973-278f-4c31-ac78-1d538753117b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635453551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.
635453551
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2495455899
Short name T63
Test name
Test status
Simulation time 508856079428 ps
CPU time 791.21 seconds
Started Jul 10 06:26:19 PM PDT 24
Finished Jul 10 06:39:33 PM PDT 24
Peak memory 191368 kb
Host smart-4e118d41-c489-4bc6-9803-b44f623a81ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495455899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2495455899
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2112746592
Short name T153
Test name
Test status
Simulation time 757517091042 ps
CPU time 1855.88 seconds
Started Jul 10 06:25:41 PM PDT 24
Finished Jul 10 06:56:38 PM PDT 24
Peak memory 191336 kb
Host smart-0114832b-4dd2-4bfc-84d4-c1006333e56a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112746592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2112746592
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.891516063
Short name T241
Test name
Test status
Simulation time 2074632666967 ps
CPU time 1435.38 seconds
Started Jul 10 06:25:46 PM PDT 24
Finished Jul 10 06:49:43 PM PDT 24
Peak memory 191336 kb
Host smart-94b3384a-c368-47ea-b02e-69f807bcbfd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891516063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
891516063
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3947700099
Short name T48
Test name
Test status
Simulation time 1184349818 ps
CPU time 2.54 seconds
Started Jul 10 06:25:12 PM PDT 24
Finished Jul 10 06:25:16 PM PDT 24
Peak memory 190668 kb
Host smart-282954ff-8e0e-43a3-ab79-1141a670621d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947700099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3947700099
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2256398577
Short name T216
Test name
Test status
Simulation time 953911231761 ps
CPU time 2440.04 seconds
Started Jul 10 06:25:28 PM PDT 24
Finished Jul 10 07:06:13 PM PDT 24
Peak memory 191372 kb
Host smart-53e98574-d47f-4675-bebc-8107e92d7f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256398577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2256398577
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2399914861
Short name T23
Test name
Test status
Simulation time 1280931992004 ps
CPU time 1103.6 seconds
Started Jul 10 06:25:57 PM PDT 24
Finished Jul 10 06:44:21 PM PDT 24
Peak memory 191392 kb
Host smart-590b3e34-9c46-45fc-87e8-c7ef4f6b35a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399914861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2399914861
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.573833430
Short name T18
Test name
Test status
Simulation time 360637679 ps
CPU time 0.93 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:25:38 PM PDT 24
Peak memory 214488 kb
Host smart-5f647bc6-150b-4d55-88fc-ca518fd8a148
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573833430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.573833430
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3746003521
Short name T68
Test name
Test status
Simulation time 655899947746 ps
CPU time 991.18 seconds
Started Jul 10 06:26:12 PM PDT 24
Finished Jul 10 06:42:47 PM PDT 24
Peak memory 194404 kb
Host smart-bad9e9de-4f19-49a1-8bbc-578ab9584182
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746003521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3746003521
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.118030640
Short name T70
Test name
Test status
Simulation time 305488401807 ps
CPU time 619.19 seconds
Started Jul 10 06:25:54 PM PDT 24
Finished Jul 10 06:36:14 PM PDT 24
Peak memory 196260 kb
Host smart-eb662a22-742f-483f-9d79-dd2867649643
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118030640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
118030640
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/114.rv_timer_random.1675052673
Short name T10
Test name
Test status
Simulation time 2606208139340 ps
CPU time 799.78 seconds
Started Jul 10 06:26:34 PM PDT 24
Finished Jul 10 06:39:54 PM PDT 24
Peak memory 191336 kb
Host smart-6bf6a294-3b95-406d-98bd-4293f841640e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675052673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1675052673
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.3914152151
Short name T167
Test name
Test status
Simulation time 521833084805 ps
CPU time 806.74 seconds
Started Jul 10 06:25:52 PM PDT 24
Finished Jul 10 06:39:20 PM PDT 24
Peak memory 191308 kb
Host smart-754ddc3c-817a-4135-8b6b-760fa277f2c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914152151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.3914152151
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.4100074657
Short name T106
Test name
Test status
Simulation time 548651060864 ps
CPU time 1139.67 seconds
Started Jul 10 06:25:42 PM PDT 24
Finished Jul 10 06:44:43 PM PDT 24
Peak memory 196040 kb
Host smart-aa129c4b-75cb-4508-8aa1-409c0916f591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100074657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.4100074657
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/182.rv_timer_random.3852812019
Short name T162
Test name
Test status
Simulation time 648934855317 ps
CPU time 520.07 seconds
Started Jul 10 06:27:26 PM PDT 24
Finished Jul 10 06:36:07 PM PDT 24
Peak memory 191324 kb
Host smart-51e78671-d4a7-409c-b147-a0548de67f80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852812019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3852812019
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.2544517000
Short name T62
Test name
Test status
Simulation time 1988626382980 ps
CPU time 1775.61 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:55:14 PM PDT 24
Peak memory 191392 kb
Host smart-3bd11abe-7ecf-4367-8dde-4019735b1f70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544517000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
2544517000
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/60.rv_timer_random.4190552198
Short name T118
Test name
Test status
Simulation time 101263677033 ps
CPU time 1400.61 seconds
Started Jul 10 06:26:17 PM PDT 24
Finished Jul 10 06:49:41 PM PDT 24
Peak memory 191332 kb
Host smart-eb6b9826-5aa1-4725-84c8-d86917770a19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190552198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.4190552198
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.432776191
Short name T168
Test name
Test status
Simulation time 49622876990 ps
CPU time 139.98 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:27:58 PM PDT 24
Peak memory 194544 kb
Host smart-e491f09d-d6e6-4e9e-859a-3464d6f6581b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432776191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.432776191
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.2518798242
Short name T206
Test name
Test status
Simulation time 156729386470 ps
CPU time 669.65 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:37:23 PM PDT 24
Peak memory 191236 kb
Host smart-5b425db4-7a0b-4a95-a536-dd9c3e09f6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518798242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2518798242
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.4162313065
Short name T182
Test name
Test status
Simulation time 979867741897 ps
CPU time 928.29 seconds
Started Jul 10 06:26:18 PM PDT 24
Finished Jul 10 06:41:49 PM PDT 24
Peak memory 191340 kb
Host smart-8dd4ccf2-b90c-4530-8174-939f2d851e93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162313065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.4162313065
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.2275293346
Short name T267
Test name
Test status
Simulation time 172568698746 ps
CPU time 903.46 seconds
Started Jul 10 06:26:31 PM PDT 24
Finished Jul 10 06:41:35 PM PDT 24
Peak memory 191336 kb
Host smart-d1687bcc-ba70-4f94-aa8d-bb96817c7663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275293346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2275293346
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.1002850685
Short name T232
Test name
Test status
Simulation time 2909920775531 ps
CPU time 793.59 seconds
Started Jul 10 06:26:36 PM PDT 24
Finished Jul 10 06:39:50 PM PDT 24
Peak memory 191316 kb
Host smart-c35fa3ef-5e2f-4268-a6cb-36b24719b4a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002850685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.1002850685
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.2947920365
Short name T247
Test name
Test status
Simulation time 125176122150 ps
CPU time 216.3 seconds
Started Jul 10 06:25:51 PM PDT 24
Finished Jul 10 06:29:28 PM PDT 24
Peak memory 183140 kb
Host smart-66eb1985-3b6d-4fa6-81c4-23b6e762c62f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947920365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2947920365
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2513807763
Short name T102
Test name
Test status
Simulation time 316975917722 ps
CPU time 513.23 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:34:04 PM PDT 24
Peak memory 182968 kb
Host smart-8a445fe2-7a61-4a1c-94a4-3ee5cb6b0adf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513807763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2513807763
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.107134872
Short name T112
Test name
Test status
Simulation time 689487497361 ps
CPU time 1909.02 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:57:55 PM PDT 24
Peak memory 194856 kb
Host smart-6253b5cb-c658-4bc9-8888-16f4d29dcc6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107134872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
107134872
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/95.rv_timer_random.3344276694
Short name T320
Test name
Test status
Simulation time 488738513996 ps
CPU time 563.11 seconds
Started Jul 10 06:26:25 PM PDT 24
Finished Jul 10 06:35:49 PM PDT 24
Peak memory 191340 kb
Host smart-79b35e19-c3cd-4d97-921b-0f28ae964382
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344276694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.3344276694
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2179222019
Short name T289
Test name
Test status
Simulation time 101765935912 ps
CPU time 163.55 seconds
Started Jul 10 06:26:31 PM PDT 24
Finished Jul 10 06:29:15 PM PDT 24
Peak memory 191348 kb
Host smart-1bda4aab-b9de-43d7-ae8e-53a21d4aa007
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179222019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2179222019
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.848329057
Short name T312
Test name
Test status
Simulation time 984264259127 ps
CPU time 495.03 seconds
Started Jul 10 06:26:31 PM PDT 24
Finished Jul 10 06:34:47 PM PDT 24
Peak memory 191352 kb
Host smart-1f82cd9b-2202-415d-966b-a478cbc39c24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848329057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.848329057
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1030286547
Short name T128
Test name
Test status
Simulation time 177553493577 ps
CPU time 360.15 seconds
Started Jul 10 06:26:31 PM PDT 24
Finished Jul 10 06:32:32 PM PDT 24
Peak memory 194932 kb
Host smart-115c13fb-5376-4a1d-a2fd-5b5355796c45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030286547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1030286547
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random.2863601536
Short name T184
Test name
Test status
Simulation time 498425827588 ps
CPU time 1647.51 seconds
Started Jul 10 06:25:40 PM PDT 24
Finished Jul 10 06:53:10 PM PDT 24
Peak memory 191324 kb
Host smart-3ef0a3dc-5584-42ae-8635-d61e2f7eceb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863601536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2863601536
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.770235835
Short name T116
Test name
Test status
Simulation time 1580625205474 ps
CPU time 2636.98 seconds
Started Jul 10 06:26:48 PM PDT 24
Finished Jul 10 07:10:46 PM PDT 24
Peak memory 191328 kb
Host smart-c7455fe9-fe14-4f38-ba4c-249deefe6cbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770235835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.770235835
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2025297766
Short name T275
Test name
Test status
Simulation time 613837069114 ps
CPU time 336.49 seconds
Started Jul 10 06:25:43 PM PDT 24
Finished Jul 10 06:31:20 PM PDT 24
Peak memory 183128 kb
Host smart-5ef3d6a5-324d-42df-ba6c-544191b5bc92
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025297766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2025297766
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_random.3341881393
Short name T154
Test name
Test status
Simulation time 124132633685 ps
CPU time 885.92 seconds
Started Jul 10 06:26:13 PM PDT 24
Finished Jul 10 06:41:03 PM PDT 24
Peak memory 191340 kb
Host smart-6c6ab97c-c3e2-49ec-bce6-e1932b50e5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341881393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3341881393
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1321988564
Short name T426
Test name
Test status
Simulation time 125669413538 ps
CPU time 1452.58 seconds
Started Jul 10 06:26:20 PM PDT 24
Finished Jul 10 06:50:35 PM PDT 24
Peak memory 191324 kb
Host smart-2fb91085-d326-48f4-b221-760a7f59f9f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321988564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1321988564
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2423356447
Short name T122
Test name
Test status
Simulation time 211582495471 ps
CPU time 441.47 seconds
Started Jul 10 06:26:22 PM PDT 24
Finished Jul 10 06:33:45 PM PDT 24
Peak memory 191332 kb
Host smart-de3189b9-00f2-4532-af35-5cf932606898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423356447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2423356447
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3684790826
Short name T233
Test name
Test status
Simulation time 502442478818 ps
CPU time 2239.44 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 07:03:01 PM PDT 24
Peak memory 191536 kb
Host smart-309adf8b-12ba-433f-a3fc-83a2bec6f3fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684790826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3684790826
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/147.rv_timer_random.1579313579
Short name T221
Test name
Test status
Simulation time 419839097036 ps
CPU time 836.28 seconds
Started Jul 10 06:26:58 PM PDT 24
Finished Jul 10 06:40:55 PM PDT 24
Peak memory 191336 kb
Host smart-c4470ff5-db98-40f9-980a-a88dde1213cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579313579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.1579313579
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.423953538
Short name T252
Test name
Test status
Simulation time 256748638453 ps
CPU time 651.2 seconds
Started Jul 10 06:27:16 PM PDT 24
Finished Jul 10 06:38:09 PM PDT 24
Peak memory 191340 kb
Host smart-d8895e93-bb5d-4b57-9905-8c165409d9fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423953538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.423953538
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3412727820
Short name T308
Test name
Test status
Simulation time 513979642834 ps
CPU time 803.66 seconds
Started Jul 10 06:25:44 PM PDT 24
Finished Jul 10 06:39:08 PM PDT 24
Peak memory 183132 kb
Host smart-4bf6dd66-0883-4993-ada2-6e7cb55b9b58
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412727820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3412727820
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.249269397
Short name T225
Test name
Test status
Simulation time 509200458920 ps
CPU time 1010.59 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:42:21 PM PDT 24
Peak memory 191328 kb
Host smart-cf5567f2-b83c-4cd9-bc47-40b76e8ec00b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249269397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.249269397
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.153297064
Short name T258
Test name
Test status
Simulation time 1685042939200 ps
CPU time 936.01 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:41:43 PM PDT 24
Peak memory 191256 kb
Host smart-dccbe895-3bad-48f9-a9b7-201a78c3584f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153297064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
153297064
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/55.rv_timer_random.2898525653
Short name T59
Test name
Test status
Simulation time 141938294709 ps
CPU time 474.31 seconds
Started Jul 10 06:26:16 PM PDT 24
Finished Jul 10 06:34:14 PM PDT 24
Peak memory 194748 kb
Host smart-623df33f-e38d-4903-9944-fae86cd335c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898525653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2898525653
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.1915664666
Short name T226
Test name
Test status
Simulation time 177633301587 ps
CPU time 921.71 seconds
Started Jul 10 06:26:25 PM PDT 24
Finished Jul 10 06:41:47 PM PDT 24
Peak memory 191344 kb
Host smart-c83f6f11-ffbb-4b2f-a4ca-490be3c9a989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915664666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.1915664666
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.861634981
Short name T76
Test name
Test status
Simulation time 37511278 ps
CPU time 0.6 seconds
Started Jul 10 06:25:02 PM PDT 24
Finished Jul 10 06:25:04 PM PDT 24
Peak memory 182272 kb
Host smart-aad45724-78a5-459a-a6ef-ec7ab16493e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861634981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.861634981
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1126514173
Short name T99
Test name
Test status
Simulation time 599350773 ps
CPU time 1.4 seconds
Started Jul 10 06:25:23 PM PDT 24
Finished Jul 10 06:25:25 PM PDT 24
Peak memory 194052 kb
Host smart-72fd1d7b-1c6f-425b-be15-a91f8a2f19d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126514173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1126514173
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random.1212871075
Short name T111
Test name
Test status
Simulation time 536083097862 ps
CPU time 253.94 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:29:46 PM PDT 24
Peak memory 191340 kb
Host smart-f1be5cd6-22ca-4f8a-ba08-1a323c1a72ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212871075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.1212871075
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.1583271117
Short name T41
Test name
Test status
Simulation time 185389461174 ps
CPU time 371.5 seconds
Started Jul 10 06:26:31 PM PDT 24
Finished Jul 10 06:32:43 PM PDT 24
Peak memory 191340 kb
Host smart-d110ef4c-a921-474b-9e79-9115d5fefafc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583271117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1583271117
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.3817033578
Short name T143
Test name
Test status
Simulation time 196035330195 ps
CPU time 920.56 seconds
Started Jul 10 06:26:33 PM PDT 24
Finished Jul 10 06:41:54 PM PDT 24
Peak memory 191336 kb
Host smart-7e964975-c0d1-46bf-adf3-60c8ae43c8bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817033578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3817033578
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.605159246
Short name T263
Test name
Test status
Simulation time 70799492487 ps
CPU time 111.7 seconds
Started Jul 10 06:26:33 PM PDT 24
Finished Jul 10 06:28:26 PM PDT 24
Peak memory 191332 kb
Host smart-8e5b26b9-9411-4820-8adf-ae3cb3f01c37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605159246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.605159246
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1902984250
Short name T198
Test name
Test status
Simulation time 224486647186 ps
CPU time 195.88 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:29:03 PM PDT 24
Peak memory 195104 kb
Host smart-e2fc555f-e41b-4729-b1b9-593f9afbfd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902984250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1902984250
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/122.rv_timer_random.3339104186
Short name T183
Test name
Test status
Simulation time 513885458345 ps
CPU time 384.21 seconds
Started Jul 10 06:26:38 PM PDT 24
Finished Jul 10 06:33:03 PM PDT 24
Peak memory 183160 kb
Host smart-60296f92-fe97-4d46-8cae-73e22b2437b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339104186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3339104186
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.2837212537
Short name T290
Test name
Test status
Simulation time 293124994563 ps
CPU time 294.31 seconds
Started Jul 10 06:26:42 PM PDT 24
Finished Jul 10 06:31:37 PM PDT 24
Peak memory 191328 kb
Host smart-c9b9f4a0-f9c8-4951-abc7-9e2e25de8ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837212537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2837212537
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3710574576
Short name T311
Test name
Test status
Simulation time 117091841666 ps
CPU time 606.21 seconds
Started Jul 10 06:27:11 PM PDT 24
Finished Jul 10 06:37:19 PM PDT 24
Peak memory 191336 kb
Host smart-12f08051-847b-4c50-ae34-dd6b0a120dd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710574576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3710574576
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1982303052
Short name T337
Test name
Test status
Simulation time 203658122007 ps
CPU time 520.61 seconds
Started Jul 10 06:27:25 PM PDT 24
Finished Jul 10 06:36:06 PM PDT 24
Peak memory 193940 kb
Host smart-d3293355-63ca-4405-a7cc-cceedf72d6a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982303052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1982303052
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.667450556
Short name T211
Test name
Test status
Simulation time 70755497906 ps
CPU time 114.39 seconds
Started Jul 10 06:27:30 PM PDT 24
Finished Jul 10 06:29:26 PM PDT 24
Peak memory 191352 kb
Host smart-b634eb22-e405-478b-9e26-973c13fefb63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667450556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.667450556
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1989318924
Short name T292
Test name
Test status
Simulation time 207471623297 ps
CPU time 1671.86 seconds
Started Jul 10 06:26:01 PM PDT 24
Finished Jul 10 06:53:54 PM PDT 24
Peak memory 191348 kb
Host smart-052a44ad-805d-4e22-9157-b02a23e3c2df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989318924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1989318924
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.806245644
Short name T256
Test name
Test status
Simulation time 92265626227 ps
CPU time 57.69 seconds
Started Jul 10 06:26:09 PM PDT 24
Finished Jul 10 06:27:07 PM PDT 24
Peak memory 183176 kb
Host smart-bd58f2e7-94ea-4614-a403-a24f7f2d6d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806245644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.806245644
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.931801932
Short name T273
Test name
Test status
Simulation time 256607720969 ps
CPU time 419.16 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:33:12 PM PDT 24
Peak memory 183140 kb
Host smart-1d84a1d4-11a3-45d4-88a7-93e72f6e503e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931801932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.931801932
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/65.rv_timer_random.2337063867
Short name T298
Test name
Test status
Simulation time 89692471105 ps
CPU time 126.34 seconds
Started Jul 10 06:26:12 PM PDT 24
Finished Jul 10 06:28:22 PM PDT 24
Peak memory 194672 kb
Host smart-ac995d20-a1a1-4ca1-95c8-76a9c38171e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337063867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2337063867
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.228496206
Short name T293
Test name
Test status
Simulation time 166634304746 ps
CPU time 73.01 seconds
Started Jul 10 06:25:37 PM PDT 24
Finished Jul 10 06:26:52 PM PDT 24
Peak memory 195200 kb
Host smart-ced84328-41c8-43a6-a27d-d97e2d352dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228496206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.228496206
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.2835616470
Short name T223
Test name
Test status
Simulation time 309573150679 ps
CPU time 722.88 seconds
Started Jul 10 06:26:33 PM PDT 24
Finished Jul 10 06:38:36 PM PDT 24
Peak memory 191328 kb
Host smart-182c9118-cc48-4ce7-a6bd-49ff88235eaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835616470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2835616470
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.457140658
Short name T321
Test name
Test status
Simulation time 91873682695 ps
CPU time 70.33 seconds
Started Jul 10 06:26:41 PM PDT 24
Finished Jul 10 06:27:52 PM PDT 24
Peak memory 183200 kb
Host smart-6810c20e-8a36-46e7-941e-c22a1e0c2a85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457140658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.457140658
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3902500087
Short name T352
Test name
Test status
Simulation time 1743251538422 ps
CPU time 394.26 seconds
Started Jul 10 06:25:40 PM PDT 24
Finished Jul 10 06:32:17 PM PDT 24
Peak memory 191540 kb
Host smart-d7312d83-1f7d-4ba4-b514-dafb2fc5ef21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902500087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3902500087
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2328010596
Short name T124
Test name
Test status
Simulation time 362339046747 ps
CPU time 367.98 seconds
Started Jul 10 06:26:42 PM PDT 24
Finished Jul 10 06:32:50 PM PDT 24
Peak memory 191320 kb
Host smart-de402cdd-f4b4-445c-85b4-99449fc52c35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328010596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2328010596
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.4105448349
Short name T56
Test name
Test status
Simulation time 212057244366 ps
CPU time 589.86 seconds
Started Jul 10 06:26:55 PM PDT 24
Finished Jul 10 06:36:46 PM PDT 24
Peak memory 191388 kb
Host smart-e19a70b0-918f-4245-b601-275456cf1c31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105448349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.4105448349
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random.2390627913
Short name T291
Test name
Test status
Simulation time 631847192619 ps
CPU time 581.2 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:35:22 PM PDT 24
Peak memory 191340 kb
Host smart-c072a62a-1806-4abf-8fab-0b4f2dc0be31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390627913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.2390627913
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.2433414095
Short name T310
Test name
Test status
Simulation time 71580278658 ps
CPU time 119.93 seconds
Started Jul 10 06:25:41 PM PDT 24
Finished Jul 10 06:27:43 PM PDT 24
Peak memory 183152 kb
Host smart-1341b053-1014-4ad2-b5aa-a593a03339cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433414095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.2433414095
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/143.rv_timer_random.238645777
Short name T187
Test name
Test status
Simulation time 166511590759 ps
CPU time 233.41 seconds
Started Jul 10 06:26:53 PM PDT 24
Finished Jul 10 06:30:47 PM PDT 24
Peak memory 191340 kb
Host smart-238e4fe0-d74b-4920-bf03-8ea8a923be6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238645777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.238645777
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2589812622
Short name T141
Test name
Test status
Simulation time 131482590346 ps
CPU time 181.87 seconds
Started Jul 10 06:26:55 PM PDT 24
Finished Jul 10 06:29:57 PM PDT 24
Peak memory 193896 kb
Host smart-28cfc89a-2a19-4559-8656-5e4912d93994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589812622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2589812622
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3380907265
Short name T53
Test name
Test status
Simulation time 63362610469 ps
CPU time 433.53 seconds
Started Jul 10 06:27:05 PM PDT 24
Finished Jul 10 06:34:20 PM PDT 24
Peak memory 191324 kb
Host smart-357d8063-46ff-4e01-9f06-615ce63a0bc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380907265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3380907265
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.3936678738
Short name T234
Test name
Test status
Simulation time 260128093864 ps
CPU time 213.73 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:29:21 PM PDT 24
Peak memory 191328 kb
Host smart-2924a00b-9191-4410-9b6f-de9af5e5d5b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936678738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3936678738
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1174769562
Short name T335
Test name
Test status
Simulation time 119262310263 ps
CPU time 128.38 seconds
Started Jul 10 06:27:04 PM PDT 24
Finished Jul 10 06:29:13 PM PDT 24
Peak memory 191336 kb
Host smart-36f523a2-e1e3-40e4-b1af-b13038de6ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174769562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1174769562
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.4109679589
Short name T345
Test name
Test status
Simulation time 61636805026 ps
CPU time 89.73 seconds
Started Jul 10 06:27:10 PM PDT 24
Finished Jul 10 06:28:41 PM PDT 24
Peak memory 191368 kb
Host smart-98f713f4-9202-4168-9d2e-7fa183d0f351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109679589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4109679589
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4096398056
Short name T171
Test name
Test status
Simulation time 325709071579 ps
CPU time 856.87 seconds
Started Jul 10 06:27:26 PM PDT 24
Finished Jul 10 06:41:44 PM PDT 24
Peak memory 194664 kb
Host smart-7f21a67d-e037-4641-9eef-0fc9f051be5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096398056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4096398056
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random.2387033978
Short name T213
Test name
Test status
Simulation time 167544271810 ps
CPU time 315.39 seconds
Started Jul 10 06:25:43 PM PDT 24
Finished Jul 10 06:30:59 PM PDT 24
Peak memory 191372 kb
Host smart-1e14ca4b-da54-4c65-8e39-1b0b24fd8d95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387033978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2387033978
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2513363870
Short name T114
Test name
Test status
Simulation time 423949491765 ps
CPU time 179.01 seconds
Started Jul 10 06:27:30 PM PDT 24
Finished Jul 10 06:30:30 PM PDT 24
Peak memory 191328 kb
Host smart-ab2885fd-4548-4f4a-a956-383883d30d94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513363870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2513363870
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.572973666
Short name T219
Test name
Test status
Simulation time 7709546080 ps
CPU time 2.72 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 183132 kb
Host smart-67627e07-9c86-4c03-8596-04990e1115e2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572973666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.572973666
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.937707138
Short name T107
Test name
Test status
Simulation time 194392615259 ps
CPU time 317.86 seconds
Started Jul 10 06:25:55 PM PDT 24
Finished Jul 10 06:31:14 PM PDT 24
Peak memory 183148 kb
Host smart-7f933877-432d-44a3-83aa-cbc7a2ad3322
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937707138 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.937707138
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.226136302
Short name T201
Test name
Test status
Simulation time 171782525154 ps
CPU time 83.21 seconds
Started Jul 10 06:25:50 PM PDT 24
Finished Jul 10 06:27:14 PM PDT 24
Peak memory 191368 kb
Host smart-42da52dc-95b5-45f8-ba37-f0285b867448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226136302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.226136302
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_random.3113855083
Short name T307
Test name
Test status
Simulation time 154419959773 ps
CPU time 123.75 seconds
Started Jul 10 06:25:56 PM PDT 24
Finished Jul 10 06:28:01 PM PDT 24
Peak memory 191360 kb
Host smart-c0680c3d-645d-4279-b35f-9defc420f381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113855083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3113855083
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.4043715875
Short name T344
Test name
Test status
Simulation time 255798733655 ps
CPU time 403.1 seconds
Started Jul 10 06:26:03 PM PDT 24
Finished Jul 10 06:32:48 PM PDT 24
Peak memory 183144 kb
Host smart-1c99a79e-e99f-44fa-81d4-c22e86acdc65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043715875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.4043715875
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.1208582947
Short name T25
Test name
Test status
Simulation time 437365935597 ps
CPU time 376.55 seconds
Started Jul 10 06:26:03 PM PDT 24
Finished Jul 10 06:32:22 PM PDT 24
Peak memory 191340 kb
Host smart-bdfffe40-7f8d-48f8-b1ba-6c1e36a5c44f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208582947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1208582947
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random.2478843134
Short name T281
Test name
Test status
Simulation time 49378719216 ps
CPU time 71.39 seconds
Started Jul 10 06:26:08 PM PDT 24
Finished Jul 10 06:27:21 PM PDT 24
Peak memory 193504 kb
Host smart-2a4b13ed-e616-4e58-9073-e4f05da18de3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478843134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2478843134
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random.3270658634
Short name T202
Test name
Test status
Simulation time 101708141381 ps
CPU time 396.78 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:32:50 PM PDT 24
Peak memory 195064 kb
Host smart-64035c2b-84cd-4274-ad5a-1b52b1651057
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270658634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3270658634
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2345554358
Short name T248
Test name
Test status
Simulation time 996239011588 ps
CPU time 699.08 seconds
Started Jul 10 06:26:19 PM PDT 24
Finished Jul 10 06:38:01 PM PDT 24
Peak memory 191512 kb
Host smart-529537cd-2da7-43ce-977e-69ad5d801554
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345554358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2345554358
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.4241535069
Short name T36
Test name
Test status
Simulation time 83202676535 ps
CPU time 671.65 seconds
Started Jul 10 06:26:17 PM PDT 24
Finished Jul 10 06:37:31 PM PDT 24
Peak memory 206044 kb
Host smart-1cd55c88-c2af-4c10-a0a3-4cf54a22f9d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241535069 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.4241535069
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.rv_timer_random.2298496083
Short name T151
Test name
Test status
Simulation time 544057379441 ps
CPU time 528.9 seconds
Started Jul 10 06:26:17 PM PDT 24
Finished Jul 10 06:35:09 PM PDT 24
Peak memory 191372 kb
Host smart-478f4c4d-fc5b-46e0-a77f-f497303038d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298496083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2298496083
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1973261240
Short name T249
Test name
Test status
Simulation time 876739181150 ps
CPU time 137.06 seconds
Started Jul 10 06:26:16 PM PDT 24
Finished Jul 10 06:28:36 PM PDT 24
Peak memory 191372 kb
Host smart-f30de4ca-7640-4b40-881b-613c934c4f61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973261240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1973261240
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2297158355
Short name T266
Test name
Test status
Simulation time 730267150236 ps
CPU time 392.16 seconds
Started Jul 10 06:25:35 PM PDT 24
Finished Jul 10 06:32:10 PM PDT 24
Peak memory 183132 kb
Host smart-d2bb14b0-47c0-4fb1-b3f1-05a7aee29ed6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297158355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2297158355
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.250519559
Short name T177
Test name
Test status
Simulation time 68717786628 ps
CPU time 110.13 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:27:27 PM PDT 24
Peak memory 191356 kb
Host smart-85997f2c-2ec4-4fae-b10c-4715f08caab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250519559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.250519559
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.2986371860
Short name T91
Test name
Test status
Simulation time 53435099 ps
CPU time 0.71 seconds
Started Jul 10 06:25:03 PM PDT 24
Finished Jul 10 06:25:05 PM PDT 24
Peak memory 182324 kb
Host smart-8cf111d4-7c7b-4343-8758-c34520e290cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986371860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.2986371860
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3987531050
Short name T563
Test name
Test status
Simulation time 3862800971 ps
CPU time 3.57 seconds
Started Jul 10 06:25:02 PM PDT 24
Finished Jul 10 06:25:07 PM PDT 24
Peak memory 193896 kb
Host smart-20e3477f-415c-4a3b-a2dc-1c7308386b7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987531050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3987531050
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3511620760
Short name T75
Test name
Test status
Simulation time 14212882 ps
CPU time 0.59 seconds
Started Jul 10 06:25:06 PM PDT 24
Finished Jul 10 06:25:07 PM PDT 24
Peak memory 182312 kb
Host smart-8cf36d3a-28e2-473b-aa13-426d076f027c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511620760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.3511620760
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4223127457
Short name T571
Test name
Test status
Simulation time 14571088 ps
CPU time 0.6 seconds
Started Jul 10 06:25:01 PM PDT 24
Finished Jul 10 06:25:02 PM PDT 24
Peak memory 192652 kb
Host smart-b4593849-1993-481d-ad36-e596674667e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223127457 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.4223127457
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1350985152
Short name T562
Test name
Test status
Simulation time 96335328 ps
CPU time 0.52 seconds
Started Jul 10 06:25:04 PM PDT 24
Finished Jul 10 06:25:06 PM PDT 24
Peak memory 181732 kb
Host smart-1a73459b-591f-4d30-849f-ee7f80bd870e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350985152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1350985152
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.421356305
Short name T561
Test name
Test status
Simulation time 23704197 ps
CPU time 0.71 seconds
Started Jul 10 06:25:12 PM PDT 24
Finished Jul 10 06:25:14 PM PDT 24
Peak memory 191920 kb
Host smart-8e9a78c0-d6aa-4417-b8da-f058edaf2090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421356305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.421356305
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1978818404
Short name T553
Test name
Test status
Simulation time 679355556 ps
CPU time 2.87 seconds
Started Jul 10 06:25:04 PM PDT 24
Finished Jul 10 06:25:08 PM PDT 24
Peak memory 197100 kb
Host smart-0da7d518-a283-4e49-860f-7ec4d1e0d65f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978818404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1978818404
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1219604431
Short name T100
Test name
Test status
Simulation time 100480148 ps
CPU time 0.83 seconds
Started Jul 10 06:25:02 PM PDT 24
Finished Jul 10 06:25:04 PM PDT 24
Peak memory 193280 kb
Host smart-66b7857c-f077-406e-b48a-31d91ad967a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219604431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1219604431
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.569962623
Short name T96
Test name
Test status
Simulation time 47854708 ps
CPU time 0.72 seconds
Started Jul 10 06:25:08 PM PDT 24
Finished Jul 10 06:25:10 PM PDT 24
Peak memory 182316 kb
Host smart-b0bd9d4d-4816-499f-98ef-3ceb58fb6a27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569962623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.569962623
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1147068716
Short name T31
Test name
Test status
Simulation time 261988237 ps
CPU time 1.41 seconds
Started Jul 10 06:25:03 PM PDT 24
Finished Jul 10 06:25:06 PM PDT 24
Peak memory 192148 kb
Host smart-c68875ef-c09b-444b-8e9d-aaa855b49837
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147068716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1147068716
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.203498392
Short name T90
Test name
Test status
Simulation time 27287420 ps
CPU time 0.59 seconds
Started Jul 10 06:25:02 PM PDT 24
Finished Jul 10 06:25:04 PM PDT 24
Peak memory 182316 kb
Host smart-94814fd5-011c-411a-a63c-2f3937366758
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203498392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.203498392
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3258442352
Short name T519
Test name
Test status
Simulation time 18756147 ps
CPU time 0.84 seconds
Started Jul 10 06:25:05 PM PDT 24
Finished Jul 10 06:25:06 PM PDT 24
Peak memory 196896 kb
Host smart-3bf318f3-6abf-41a1-886b-81b36effe575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258442352 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3258442352
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.4146454946
Short name T544
Test name
Test status
Simulation time 56424242 ps
CPU time 0.6 seconds
Started Jul 10 06:25:03 PM PDT 24
Finished Jul 10 06:25:05 PM PDT 24
Peak memory 182336 kb
Host smart-aa296612-d19d-4e2c-859c-907aaec4a171
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146454946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.4146454946
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3540670330
Short name T469
Test name
Test status
Simulation time 43687609 ps
CPU time 0.54 seconds
Started Jul 10 06:25:03 PM PDT 24
Finished Jul 10 06:25:05 PM PDT 24
Peak memory 181888 kb
Host smart-a7760fa6-42b4-4fce-9412-9dffe57d0f90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540670330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3540670330
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4198268427
Short name T575
Test name
Test status
Simulation time 34926754 ps
CPU time 0.64 seconds
Started Jul 10 06:25:10 PM PDT 24
Finished Jul 10 06:25:12 PM PDT 24
Peak memory 191144 kb
Host smart-c0cd72e3-024c-4343-874c-123077adc416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198268427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4198268427
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1391851055
Short name T458
Test name
Test status
Simulation time 102983208 ps
CPU time 2.09 seconds
Started Jul 10 06:25:07 PM PDT 24
Finished Jul 10 06:25:09 PM PDT 24
Peak memory 197108 kb
Host smart-5d45171b-fdec-4597-a4b8-e5eabe08930b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391851055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1391851055
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2931135510
Short name T533
Test name
Test status
Simulation time 426298407 ps
CPU time 1.44 seconds
Started Jul 10 06:25:06 PM PDT 24
Finished Jul 10 06:25:08 PM PDT 24
Peak memory 195024 kb
Host smart-673e1d89-5b18-49ee-8331-f218e5da22b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931135510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2931135510
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1773045422
Short name T558
Test name
Test status
Simulation time 81765490 ps
CPU time 0.78 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:20 PM PDT 24
Peak memory 194552 kb
Host smart-4ca5adbf-02ea-4ff1-8216-e0eae3ff857a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773045422 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1773045422
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3532246833
Short name T87
Test name
Test status
Simulation time 110169252 ps
CPU time 0.55 seconds
Started Jul 10 06:25:21 PM PDT 24
Finished Jul 10 06:25:23 PM PDT 24
Peak memory 182324 kb
Host smart-a7a7060f-1ab9-4724-95ca-27141a955d5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532246833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3532246833
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.372655445
Short name T517
Test name
Test status
Simulation time 32112863 ps
CPU time 0.52 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:19 PM PDT 24
Peak memory 181672 kb
Host smart-109a49f5-bf92-4c13-9e81-03b632c8a886
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372655445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.372655445
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2309552868
Short name T573
Test name
Test status
Simulation time 28228269 ps
CPU time 0.71 seconds
Started Jul 10 06:25:15 PM PDT 24
Finished Jul 10 06:25:17 PM PDT 24
Peak memory 192920 kb
Host smart-3e936b33-2c2e-46a8-be31-980ada16f603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309552868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2309552868
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1534414045
Short name T486
Test name
Test status
Simulation time 1002696750 ps
CPU time 2.6 seconds
Started Jul 10 06:25:18 PM PDT 24
Finished Jul 10 06:25:23 PM PDT 24
Peak memory 197112 kb
Host smart-416187f7-dfba-4c68-a637-b04fafc043a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534414045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1534414045
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2117444546
Short name T551
Test name
Test status
Simulation time 67027531 ps
CPU time 0.96 seconds
Started Jul 10 06:25:17 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 196892 kb
Host smart-de2f201b-fdae-4c2c-b26f-56cf75815ff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117444546 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2117444546
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4080920652
Short name T86
Test name
Test status
Simulation time 14660827 ps
CPU time 0.57 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:19 PM PDT 24
Peak memory 182312 kb
Host smart-189f15ee-21b0-4271-a9b8-d243e31ac055
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080920652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4080920652
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1469817345
Short name T465
Test name
Test status
Simulation time 14452073 ps
CPU time 0.55 seconds
Started Jul 10 06:25:18 PM PDT 24
Finished Jul 10 06:25:22 PM PDT 24
Peak memory 182252 kb
Host smart-d410f7c2-1390-4225-9e4d-e84ff310bc87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469817345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1469817345
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2916586810
Short name T95
Test name
Test status
Simulation time 23127074 ps
CPU time 0.59 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:19 PM PDT 24
Peak memory 191176 kb
Host smart-3e537739-1557-4915-adf2-dcc046acb2cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916586810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2916586810
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.3518936509
Short name T524
Test name
Test status
Simulation time 38990978 ps
CPU time 1.15 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:19 PM PDT 24
Peak memory 196796 kb
Host smart-dfbb58ee-aa6f-4b98-a34d-41f51b2eddec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518936509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.3518936509
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1401928228
Short name T541
Test name
Test status
Simulation time 168147283 ps
CPU time 0.81 seconds
Started Jul 10 06:25:17 PM PDT 24
Finished Jul 10 06:25:20 PM PDT 24
Peak memory 193088 kb
Host smart-bc672665-90dd-4207-b219-740b3fb6e6c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401928228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1401928228
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2945490476
Short name T501
Test name
Test status
Simulation time 51684026 ps
CPU time 0.78 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:29 PM PDT 24
Peak memory 196188 kb
Host smart-faf194bc-e007-4bff-a2b1-b3406b5703bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945490476 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2945490476
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.3313635153
Short name T559
Test name
Test status
Simulation time 28332183 ps
CPU time 0.6 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:29 PM PDT 24
Peak memory 182276 kb
Host smart-74fef3b8-8081-442d-aaba-a0facb372f2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313635153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.3313635153
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1848629196
Short name T483
Test name
Test status
Simulation time 13639970 ps
CPU time 0.55 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:30 PM PDT 24
Peak memory 182200 kb
Host smart-4c468baa-b1f7-4e06-b5d8-b1450daf44c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848629196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1848629196
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.130154050
Short name T502
Test name
Test status
Simulation time 107436781 ps
CPU time 0.73 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:35 PM PDT 24
Peak memory 191296 kb
Host smart-bb32270e-121b-402c-a32e-786649c58415
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130154050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_ti
mer_same_csr_outstanding.130154050
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.731399722
Short name T456
Test name
Test status
Simulation time 40979362 ps
CPU time 1.06 seconds
Started Jul 10 06:25:23 PM PDT 24
Finished Jul 10 06:25:25 PM PDT 24
Peak memory 196716 kb
Host smart-1035623b-f801-4092-9ebe-45e48adf01ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731399722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.731399722
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1989237573
Short name T481
Test name
Test status
Simulation time 357634614 ps
CPU time 1.3 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:31 PM PDT 24
Peak memory 195084 kb
Host smart-92b4e49e-4e1e-4226-b4e4-2244b86ddbe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989237573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1989237573
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1171758113
Short name T482
Test name
Test status
Simulation time 45494462 ps
CPU time 1.09 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:36 PM PDT 24
Peak memory 196968 kb
Host smart-c5efe6b9-5849-410d-a0b0-4ba18c91cdaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171758113 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1171758113
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1447211054
Short name T484
Test name
Test status
Simulation time 56073663 ps
CPU time 0.57 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 182296 kb
Host smart-871ab1a5-64e8-4e84-8675-c0e687f79d99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447211054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1447211054
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1118132165
Short name T543
Test name
Test status
Simulation time 10486416 ps
CPU time 0.57 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:34 PM PDT 24
Peak memory 182164 kb
Host smart-bcf68ab4-e1c5-4ec4-bf7c-968cd92036fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118132165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1118132165
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3461406618
Short name T499
Test name
Test status
Simulation time 28294816 ps
CPU time 0.73 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:29 PM PDT 24
Peak memory 192920 kb
Host smart-253d5d9b-e1d3-455e-b583-2b245a8d0b89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461406618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3461406618
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.3395633399
Short name T462
Test name
Test status
Simulation time 27138431 ps
CPU time 1.21 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 197108 kb
Host smart-db2ee01a-bda2-456e-9147-f7d302b1f498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395633399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.3395633399
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2968884756
Short name T478
Test name
Test status
Simulation time 27734045 ps
CPU time 0.85 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:34 PM PDT 24
Peak memory 194748 kb
Host smart-cf69a039-8d44-4758-808f-0956752d7941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968884756 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2968884756
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2763556900
Short name T537
Test name
Test status
Simulation time 11918108 ps
CPU time 0.52 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:32 PM PDT 24
Peak memory 182084 kb
Host smart-a5a3e4a6-c8c6-4eda-bc86-ed632147265a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763556900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2763556900
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1623599971
Short name T487
Test name
Test status
Simulation time 42723505 ps
CPU time 0.52 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:26 PM PDT 24
Peak memory 181876 kb
Host smart-7a84de23-3a87-4572-8d5b-831e6f2f00d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623599971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1623599971
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2882168213
Short name T50
Test name
Test status
Simulation time 40054873 ps
CPU time 0.65 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:27 PM PDT 24
Peak memory 191136 kb
Host smart-5c89ae6c-1740-44bf-ae8f-006fb8d261c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882168213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2882168213
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2953906772
Short name T476
Test name
Test status
Simulation time 1010487533 ps
CPU time 2.85 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:29 PM PDT 24
Peak memory 197112 kb
Host smart-fc139a6c-5a91-44bb-ae8b-b17eef51b166
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953906772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2953906772
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4012428893
Short name T46
Test name
Test status
Simulation time 161849555 ps
CPU time 1.06 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:26 PM PDT 24
Peak memory 194680 kb
Host smart-3bf7263e-814b-4360-a97d-d331ed583a7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012428893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4012428893
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1162690040
Short name T542
Test name
Test status
Simulation time 69264712 ps
CPU time 1.03 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:36 PM PDT 24
Peak memory 196636 kb
Host smart-d642b45a-a9da-4f40-85d5-fa17b34db4aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162690040 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1162690040
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3198486159
Short name T85
Test name
Test status
Simulation time 29073274 ps
CPU time 0.53 seconds
Started Jul 10 06:25:32 PM PDT 24
Finished Jul 10 06:25:37 PM PDT 24
Peak memory 182320 kb
Host smart-ad475a30-c40f-46bb-8e11-a22a3d9ba6d6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198486159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3198486159
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2109148947
Short name T547
Test name
Test status
Simulation time 14301959 ps
CPU time 0.55 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:30 PM PDT 24
Peak memory 182196 kb
Host smart-4b35f082-fbda-444c-958c-73f287252e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109148947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2109148947
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1388235994
Short name T525
Test name
Test status
Simulation time 20934471 ps
CPU time 0.63 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:27 PM PDT 24
Peak memory 192616 kb
Host smart-0cb28436-13d6-4e4b-8634-07a109dbf7bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388235994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1388235994
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.3109227493
Short name T568
Test name
Test status
Simulation time 63859902 ps
CPU time 1.32 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:29 PM PDT 24
Peak memory 197136 kb
Host smart-a43546fd-a4a8-4090-9fab-3ab9332532b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109227493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.3109227493
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.4221279382
Short name T552
Test name
Test status
Simulation time 121250549 ps
CPU time 1.4 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:27 PM PDT 24
Peak memory 195136 kb
Host smart-a8633b03-4a30-467b-889f-19e0177fdf53
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221279382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.4221279382
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2030573342
Short name T539
Test name
Test status
Simulation time 27793770 ps
CPU time 0.77 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 195260 kb
Host smart-a3db1e90-427b-4ab4-bce4-9422a3b4f180
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030573342 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2030573342
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2359581303
Short name T88
Test name
Test status
Simulation time 32059355 ps
CPU time 0.6 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:28 PM PDT 24
Peak memory 182316 kb
Host smart-f6dba518-089b-4a8f-8767-f55d7dbbfff4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359581303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2359581303
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.537484205
Short name T540
Test name
Test status
Simulation time 156172792 ps
CPU time 0.56 seconds
Started Jul 10 06:25:23 PM PDT 24
Finished Jul 10 06:25:24 PM PDT 24
Peak memory 181684 kb
Host smart-285cf10b-bc08-48c6-aa5e-279a506c62c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537484205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.537484205
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2987286151
Short name T77
Test name
Test status
Simulation time 28826133 ps
CPU time 0.66 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:29 PM PDT 24
Peak memory 191828 kb
Host smart-afbfe266-ade4-4e62-b5b2-10dff0409105
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987286151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2987286151
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.595694560
Short name T549
Test name
Test status
Simulation time 158236672 ps
CPU time 2.8 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 197108 kb
Host smart-8c946f42-1360-49e3-a82c-d73f1d3dc98c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595694560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.595694560
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2479327673
Short name T576
Test name
Test status
Simulation time 458619753 ps
CPU time 1.35 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:30 PM PDT 24
Peak memory 194948 kb
Host smart-7bfc9aa4-b807-4432-81a9-9631a11f6b22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479327673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2479327673
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.4259181128
Short name T471
Test name
Test status
Simulation time 637063783 ps
CPU time 1.51 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:32 PM PDT 24
Peak memory 197084 kb
Host smart-fa25c0eb-7c28-4ecc-8158-b23dadd8ffbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259181128 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.4259181128
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2647375094
Short name T83
Test name
Test status
Simulation time 43243119 ps
CPU time 0.59 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:35 PM PDT 24
Peak memory 181928 kb
Host smart-0c4dfc91-b1ff-4052-b519-c5be90dac39e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647375094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2647375094
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.986446358
Short name T470
Test name
Test status
Simulation time 18116744 ps
CPU time 0.54 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:31 PM PDT 24
Peak memory 181876 kb
Host smart-431f3ac0-6454-403d-aae0-3416ac259a85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986446358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.986446358
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.592512923
Short name T514
Test name
Test status
Simulation time 26805086 ps
CPU time 0.72 seconds
Started Jul 10 06:25:23 PM PDT 24
Finished Jul 10 06:25:25 PM PDT 24
Peak memory 192604 kb
Host smart-0ea33c78-88c9-4d27-9ffc-7caf82e566c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592512923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.592512923
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1226651979
Short name T556
Test name
Test status
Simulation time 729137342 ps
CPU time 3.01 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:32 PM PDT 24
Peak memory 197112 kb
Host smart-42ef53e1-51cb-46df-ac87-ed3e4f3c216b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226651979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1226651979
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.150617846
Short name T97
Test name
Test status
Simulation time 354632131 ps
CPU time 1.1 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:26 PM PDT 24
Peak memory 194396 kb
Host smart-8dc442e7-1aa7-44ae-a3c7-ab53c3217a0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150617846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.150617846
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1184520553
Short name T550
Test name
Test status
Simulation time 28473355 ps
CPU time 0.83 seconds
Started Jul 10 06:25:31 PM PDT 24
Finished Jul 10 06:25:36 PM PDT 24
Peak memory 195408 kb
Host smart-7a238991-949e-4d16-b730-452c30bd87fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184520553 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1184520553
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2887673028
Short name T523
Test name
Test status
Simulation time 14426774 ps
CPU time 0.6 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:26 PM PDT 24
Peak memory 182340 kb
Host smart-8999da33-1df2-44d7-94f2-ca922e4cfad2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887673028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2887673028
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.107466697
Short name T490
Test name
Test status
Simulation time 13226611 ps
CPU time 0.59 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:26 PM PDT 24
Peak memory 182220 kb
Host smart-7a50b183-e3f3-473d-a79d-b3455c765942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107466697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.107466697
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3411897785
Short name T79
Test name
Test status
Simulation time 63323559 ps
CPU time 0.85 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:28 PM PDT 24
Peak memory 193080 kb
Host smart-ed82350a-372b-479b-9eaa-8cbfaa42969a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411897785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3411897785
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3314075283
Short name T516
Test name
Test status
Simulation time 797846455 ps
CPU time 1.82 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:34 PM PDT 24
Peak memory 197108 kb
Host smart-d463e5f7-840a-4d0a-9cdd-59386f9f2f60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314075283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3314075283
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1900645831
Short name T494
Test name
Test status
Simulation time 418084743 ps
CPU time 1.43 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:30 PM PDT 24
Peak memory 194672 kb
Host smart-fc6c50a3-1452-4848-bf07-8504f146985d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900645831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1900645831
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3779557029
Short name T32
Test name
Test status
Simulation time 63522596 ps
CPU time 0.6 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:29 PM PDT 24
Peak memory 192972 kb
Host smart-4af39a03-30aa-4b99-beb7-9ef09f5ee735
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779557029 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3779557029
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1601834745
Short name T84
Test name
Test status
Simulation time 11011763 ps
CPU time 0.59 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:30 PM PDT 24
Peak memory 182320 kb
Host smart-d356ddf0-b2e9-43b2-a939-d9d9c45aedd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601834745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1601834745
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.3840062858
Short name T466
Test name
Test status
Simulation time 18429952 ps
CPU time 0.58 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:35 PM PDT 24
Peak memory 182240 kb
Host smart-1bc089eb-3b82-41b6-8513-9e31165a7c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840062858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.3840062858
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4287672217
Short name T72
Test name
Test status
Simulation time 34268074 ps
CPU time 0.78 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 192948 kb
Host smart-1aa7d42e-47d7-4576-8f6d-55cd5c17048c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287672217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.4287672217
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.923487646
Short name T457
Test name
Test status
Simulation time 156424386 ps
CPU time 1.03 seconds
Started Jul 10 06:25:23 PM PDT 24
Finished Jul 10 06:25:25 PM PDT 24
Peak memory 195576 kb
Host smart-d25aa82c-2d1b-4241-9df0-021498055fa4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923487646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.923487646
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3054405803
Short name T49
Test name
Test status
Simulation time 445700060 ps
CPU time 1.45 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:29 PM PDT 24
Peak memory 194132 kb
Host smart-241584bb-d055-4f19-b760-2ac0ebf3467b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054405803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3054405803
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3905921561
Short name T44
Test name
Test status
Simulation time 39960114 ps
CPU time 0.84 seconds
Started Jul 10 06:25:12 PM PDT 24
Finished Jul 10 06:25:14 PM PDT 24
Peak memory 182292 kb
Host smart-0b57df66-4493-4454-91d1-286018ce156d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905921561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3905921561
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2541301986
Short name T508
Test name
Test status
Simulation time 320614997 ps
CPU time 2.48 seconds
Started Jul 10 06:25:10 PM PDT 24
Finished Jul 10 06:25:14 PM PDT 24
Peak memory 182468 kb
Host smart-3b13b69e-f298-4d8e-bfb2-5b66259b3da9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541301986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2541301986
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.13583665
Short name T89
Test name
Test status
Simulation time 14035826 ps
CPU time 0.56 seconds
Started Jul 10 06:25:09 PM PDT 24
Finished Jul 10 06:25:10 PM PDT 24
Peak memory 182324 kb
Host smart-5d1b9d7c-4699-4e41-a161-d3b5c62dbb74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13583665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_res
et.13583665
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3905868718
Short name T460
Test name
Test status
Simulation time 52258280 ps
CPU time 0.73 seconds
Started Jul 10 06:25:08 PM PDT 24
Finished Jul 10 06:25:10 PM PDT 24
Peak memory 195364 kb
Host smart-d3835a04-d6ef-4d85-9d5d-d151fa4b940b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905868718 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3905868718
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.606115417
Short name T81
Test name
Test status
Simulation time 35615017 ps
CPU time 0.56 seconds
Started Jul 10 06:25:09 PM PDT 24
Finished Jul 10 06:25:11 PM PDT 24
Peak memory 182292 kb
Host smart-48afc780-42a3-499c-b300-0cd217a39f5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606115417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.606115417
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.367563211
Short name T459
Test name
Test status
Simulation time 13205988 ps
CPU time 0.58 seconds
Started Jul 10 06:25:12 PM PDT 24
Finished Jul 10 06:25:14 PM PDT 24
Peak memory 181860 kb
Host smart-58f8341d-1b38-43da-9d3b-ec9439c73447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367563211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.367563211
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1783392662
Short name T515
Test name
Test status
Simulation time 63682032 ps
CPU time 0.62 seconds
Started Jul 10 06:25:08 PM PDT 24
Finished Jul 10 06:25:10 PM PDT 24
Peak memory 191536 kb
Host smart-12f5b6e3-694e-4549-9de4-a09eb6fca421
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783392662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1783392662
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.2644509358
Short name T512
Test name
Test status
Simulation time 138293421 ps
CPU time 1.93 seconds
Started Jul 10 06:25:11 PM PDT 24
Finished Jul 10 06:25:15 PM PDT 24
Peak memory 197068 kb
Host smart-8bbab664-b271-4c97-842d-2f43aff85ac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644509358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.2644509358
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1774826156
Short name T532
Test name
Test status
Simulation time 289649421 ps
CPU time 1.02 seconds
Started Jul 10 06:25:07 PM PDT 24
Finished Jul 10 06:25:09 PM PDT 24
Peak memory 194484 kb
Host smart-2d8ef529-3abe-4bb0-a732-4b70512f2653
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774826156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1774826156
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1245751738
Short name T548
Test name
Test status
Simulation time 27807062 ps
CPU time 0.58 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:35 PM PDT 24
Peak memory 182236 kb
Host smart-88eafd9d-9d16-4a87-9e58-d89929ffd4ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245751738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1245751738
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.704829776
Short name T529
Test name
Test status
Simulation time 37832009 ps
CPU time 0.55 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:29 PM PDT 24
Peak memory 182208 kb
Host smart-fe86600c-c0e7-4ccd-8ff2-83a0b04d186c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704829776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.704829776
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2990831832
Short name T472
Test name
Test status
Simulation time 17280185 ps
CPU time 0.6 seconds
Started Jul 10 06:25:30 PM PDT 24
Finished Jul 10 06:25:35 PM PDT 24
Peak memory 182240 kb
Host smart-4836cddc-8b0a-4569-b6e3-13f7739b2ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990831832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2990831832
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1944380485
Short name T468
Test name
Test status
Simulation time 12399403 ps
CPU time 0.57 seconds
Started Jul 10 06:25:28 PM PDT 24
Finished Jul 10 06:25:34 PM PDT 24
Peak memory 182228 kb
Host smart-779ff838-3a9a-4f27-a0c4-f209a7c31cf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944380485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1944380485
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2382786188
Short name T513
Test name
Test status
Simulation time 49214010 ps
CPU time 0.56 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:31 PM PDT 24
Peak memory 182224 kb
Host smart-ff7b8435-14eb-4b75-baaf-d2b965c7e080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382786188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2382786188
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.4098144765
Short name T522
Test name
Test status
Simulation time 14307189 ps
CPU time 0.55 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:32 PM PDT 24
Peak memory 181680 kb
Host smart-059ef987-0717-4af1-89d5-78a6e636f016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098144765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.4098144765
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.3218286182
Short name T574
Test name
Test status
Simulation time 37565125 ps
CPU time 0.54 seconds
Started Jul 10 06:25:21 PM PDT 24
Finished Jul 10 06:25:23 PM PDT 24
Peak memory 182224 kb
Host smart-54e36090-e48a-4c52-ab59-5a3a41c16a65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218286182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.3218286182
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1963819188
Short name T500
Test name
Test status
Simulation time 231611188 ps
CPU time 0.57 seconds
Started Jul 10 06:25:25 PM PDT 24
Finished Jul 10 06:25:28 PM PDT 24
Peak memory 182392 kb
Host smart-cd7c79f2-abd1-4338-b8a3-abd231169b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963819188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1963819188
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3708874551
Short name T557
Test name
Test status
Simulation time 21588405 ps
CPU time 0.53 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:31 PM PDT 24
Peak memory 181684 kb
Host smart-ea7a06f3-6590-49a9-a20a-bdac7c456aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708874551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3708874551
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.1030227584
Short name T545
Test name
Test status
Simulation time 11761454 ps
CPU time 0.55 seconds
Started Jul 10 06:25:30 PM PDT 24
Finished Jul 10 06:25:35 PM PDT 24
Peak memory 182192 kb
Host smart-7250201a-3790-4220-a63b-362ea3cd65c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030227584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.1030227584
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1617310239
Short name T82
Test name
Test status
Simulation time 131269829 ps
CPU time 0.8 seconds
Started Jul 10 06:25:09 PM PDT 24
Finished Jul 10 06:25:10 PM PDT 24
Peak memory 192392 kb
Host smart-b100ac50-a676-42c3-bcb1-ecbedbd20ffd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617310239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1617310239
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1866754687
Short name T80
Test name
Test status
Simulation time 241975876 ps
CPU time 2.34 seconds
Started Jul 10 06:25:07 PM PDT 24
Finished Jul 10 06:25:10 PM PDT 24
Peak memory 182488 kb
Host smart-921c57ce-8e43-4b10-8cb1-5a93c4ec8721
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866754687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1866754687
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.4035923389
Short name T61
Test name
Test status
Simulation time 44146111 ps
CPU time 0.54 seconds
Started Jul 10 06:25:08 PM PDT 24
Finished Jul 10 06:25:09 PM PDT 24
Peak memory 182380 kb
Host smart-9deebf7a-4ed5-4250-898d-adff631d45b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035923389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.4035923389
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.4103820643
Short name T45
Test name
Test status
Simulation time 26088659 ps
CPU time 0.67 seconds
Started Jul 10 06:25:09 PM PDT 24
Finished Jul 10 06:25:10 PM PDT 24
Peak memory 192568 kb
Host smart-cfffcc33-50cf-4b38-a954-c72bf9330f88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103820643 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.4103820643
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3402287830
Short name T520
Test name
Test status
Simulation time 38991585 ps
CPU time 0.66 seconds
Started Jul 10 06:25:11 PM PDT 24
Finished Jul 10 06:25:13 PM PDT 24
Peak memory 182316 kb
Host smart-68a4a383-5d80-418f-a0ed-dfdc16c5dbe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402287830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3402287830
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2754007569
Short name T505
Test name
Test status
Simulation time 52842040 ps
CPU time 0.57 seconds
Started Jul 10 06:25:07 PM PDT 24
Finished Jul 10 06:25:08 PM PDT 24
Peak memory 182228 kb
Host smart-64967d06-4133-4bc0-b526-6e0463293a8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754007569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2754007569
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1719123816
Short name T534
Test name
Test status
Simulation time 28832191 ps
CPU time 0.66 seconds
Started Jul 10 06:25:07 PM PDT 24
Finished Jul 10 06:25:08 PM PDT 24
Peak memory 191292 kb
Host smart-39d64055-84e5-4b0a-a97a-d2f7e4a69d1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719123816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1719123816
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3198891449
Short name T60
Test name
Test status
Simulation time 104869803 ps
CPU time 1.8 seconds
Started Jul 10 06:25:12 PM PDT 24
Finished Jul 10 06:25:15 PM PDT 24
Peak memory 197276 kb
Host smart-f0277b96-1241-41b8-9066-2b6eff358118
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198891449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3198891449
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.679306127
Short name T98
Test name
Test status
Simulation time 104586188 ps
CPU time 1.37 seconds
Started Jul 10 06:25:17 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 194800 kb
Host smart-32aac8c0-26b3-4934-b79f-f3030e253bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679306127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.679306127
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3491311481
Short name T503
Test name
Test status
Simulation time 11160607 ps
CPU time 0.54 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:27 PM PDT 24
Peak memory 181896 kb
Host smart-01a3fc8b-be35-47bf-aaec-d2bb01d5c848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491311481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3491311481
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4046071131
Short name T511
Test name
Test status
Simulation time 44436975 ps
CPU time 0.58 seconds
Started Jul 10 06:25:24 PM PDT 24
Finished Jul 10 06:25:26 PM PDT 24
Peak memory 182236 kb
Host smart-e8e2f65e-3a01-466c-8bfa-8d613ba88b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046071131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4046071131
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.785419873
Short name T535
Test name
Test status
Simulation time 26609003 ps
CPU time 0.56 seconds
Started Jul 10 06:25:22 PM PDT 24
Finished Jul 10 06:25:24 PM PDT 24
Peak memory 182140 kb
Host smart-cccd791c-f219-4124-bcb6-e3d683a4ebec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785419873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.785419873
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.1018561806
Short name T538
Test name
Test status
Simulation time 13523563 ps
CPU time 0.58 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:31 PM PDT 24
Peak memory 182204 kb
Host smart-d7bd8f99-919e-43cb-a0c1-1c338476a4be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018561806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.1018561806
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3352704766
Short name T510
Test name
Test status
Simulation time 16473367 ps
CPU time 0.56 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:32 PM PDT 24
Peak memory 182192 kb
Host smart-cd127353-804e-4a98-9c89-63f34dbf04e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352704766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3352704766
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2100059211
Short name T555
Test name
Test status
Simulation time 34736868 ps
CPU time 0.52 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:32 PM PDT 24
Peak memory 181672 kb
Host smart-de3e73a0-e3ce-4e0d-a462-052cf6eefab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100059211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2100059211
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2683849246
Short name T521
Test name
Test status
Simulation time 16716696 ps
CPU time 0.53 seconds
Started Jul 10 06:25:28 PM PDT 24
Finished Jul 10 06:25:34 PM PDT 24
Peak memory 182184 kb
Host smart-2b000078-e3a6-4dbe-afc9-3cc821541254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683849246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2683849246
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2889677557
Short name T492
Test name
Test status
Simulation time 13566678 ps
CPU time 0.53 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 182112 kb
Host smart-14914079-30a3-4eaa-859a-c09c162c3f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889677557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2889677557
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3653171508
Short name T480
Test name
Test status
Simulation time 38114086 ps
CPU time 0.53 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 182192 kb
Host smart-0caa8386-b4e2-4020-bb17-d39a2887acb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653171508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3653171508
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1188094102
Short name T495
Test name
Test status
Simulation time 16445541 ps
CPU time 0.58 seconds
Started Jul 10 06:25:28 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 182192 kb
Host smart-443abf74-b198-433f-93e3-542c8c019d3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188094102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1188094102
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.305890695
Short name T536
Test name
Test status
Simulation time 42701111 ps
CPU time 0.63 seconds
Started Jul 10 06:25:07 PM PDT 24
Finished Jul 10 06:25:09 PM PDT 24
Peak memory 182332 kb
Host smart-31b64f38-5c41-4318-bb3a-267c3c5af665
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305890695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.305890695
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2582432942
Short name T498
Test name
Test status
Simulation time 67845426 ps
CPU time 0.56 seconds
Started Jul 10 06:25:08 PM PDT 24
Finished Jul 10 06:25:10 PM PDT 24
Peak memory 181864 kb
Host smart-309ffadf-3eb1-4de7-901e-8b342d2ee9ae
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582432942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2582432942
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2793760475
Short name T474
Test name
Test status
Simulation time 21719403 ps
CPU time 0.89 seconds
Started Jul 10 06:25:12 PM PDT 24
Finished Jul 10 06:25:14 PM PDT 24
Peak memory 196992 kb
Host smart-75fcc47e-3540-45ba-8927-8a810568e2d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793760475 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2793760475
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.83050284
Short name T567
Test name
Test status
Simulation time 18467085 ps
CPU time 0.59 seconds
Started Jul 10 06:25:17 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 182256 kb
Host smart-7fc84816-df6e-49af-838a-808f49036b4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83050284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.83050284
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.536120510
Short name T473
Test name
Test status
Simulation time 14536743 ps
CPU time 0.58 seconds
Started Jul 10 06:25:12 PM PDT 24
Finished Jul 10 06:25:14 PM PDT 24
Peak memory 182216 kb
Host smart-d251e8ba-34ea-4d72-93ef-fa35d397f2e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536120510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.536120510
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2253423334
Short name T78
Test name
Test status
Simulation time 58497290 ps
CPU time 0.79 seconds
Started Jul 10 06:25:07 PM PDT 24
Finished Jul 10 06:25:09 PM PDT 24
Peak memory 192908 kb
Host smart-8602bbd6-fe61-41c1-a791-90afda971ef5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253423334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2253423334
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1319400432
Short name T526
Test name
Test status
Simulation time 80029229 ps
CPU time 1.52 seconds
Started Jul 10 06:25:17 PM PDT 24
Finished Jul 10 06:25:22 PM PDT 24
Peak memory 196912 kb
Host smart-1dd54581-a47f-41fb-9acd-3b794a2c21cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319400432 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1319400432
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3082296523
Short name T30
Test name
Test status
Simulation time 436268830 ps
CPU time 1.38 seconds
Started Jul 10 06:25:09 PM PDT 24
Finished Jul 10 06:25:11 PM PDT 24
Peak memory 194196 kb
Host smart-398e87a6-8315-455e-945b-f69bd5b63d93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082296523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3082296523
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3769342722
Short name T475
Test name
Test status
Simulation time 46256524 ps
CPU time 0.52 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:30 PM PDT 24
Peak memory 182084 kb
Host smart-f95ccf58-3552-4a6f-990f-954c1248ae43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769342722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3769342722
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.2620739917
Short name T507
Test name
Test status
Simulation time 51538152 ps
CPU time 0.57 seconds
Started Jul 10 06:25:28 PM PDT 24
Finished Jul 10 06:25:34 PM PDT 24
Peak memory 182232 kb
Host smart-dab26151-5743-47ad-ae87-db263fc62edc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620739917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.2620739917
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2375371312
Short name T479
Test name
Test status
Simulation time 15298211 ps
CPU time 0.53 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:35 PM PDT 24
Peak memory 181668 kb
Host smart-bbec51a2-8f64-408d-8933-48c70c4850e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375371312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2375371312
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.665768984
Short name T531
Test name
Test status
Simulation time 79336761 ps
CPU time 0.54 seconds
Started Jul 10 06:25:28 PM PDT 24
Finished Jul 10 06:25:34 PM PDT 24
Peak memory 182200 kb
Host smart-fadc2a60-c29a-4ece-b8a7-62f609d64298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665768984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.665768984
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2554394014
Short name T454
Test name
Test status
Simulation time 17663957 ps
CPU time 0.58 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:31 PM PDT 24
Peak memory 182228 kb
Host smart-811b74cd-7e24-4890-8c77-a6566fed4ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554394014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2554394014
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1829331851
Short name T546
Test name
Test status
Simulation time 144352175 ps
CPU time 0.54 seconds
Started Jul 10 06:25:27 PM PDT 24
Finished Jul 10 06:25:33 PM PDT 24
Peak memory 182216 kb
Host smart-10576667-b3ce-4c3b-9cfd-df40919e127e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829331851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1829331851
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.1834586820
Short name T569
Test name
Test status
Simulation time 14286895 ps
CPU time 0.57 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:35 PM PDT 24
Peak memory 181868 kb
Host smart-4b07c7ed-b7e7-4c1a-9339-429a17b227f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834586820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.1834586820
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2142327167
Short name T489
Test name
Test status
Simulation time 13261303 ps
CPU time 0.57 seconds
Started Jul 10 06:25:28 PM PDT 24
Finished Jul 10 06:25:34 PM PDT 24
Peak memory 182228 kb
Host smart-ab087d13-90ea-4847-8c41-36e9c7d8fe81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142327167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2142327167
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.452324440
Short name T554
Test name
Test status
Simulation time 60327301 ps
CPU time 0.55 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:35 PM PDT 24
Peak memory 181668 kb
Host smart-a0d70210-ea1c-4768-93cf-f7c1e1131351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452324440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.452324440
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.654866216
Short name T572
Test name
Test status
Simulation time 47280824 ps
CPU time 0.59 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:30 PM PDT 24
Peak memory 182244 kb
Host smart-dbf150fc-6340-4621-aff0-183fc5976624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654866216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.654866216
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1165590364
Short name T509
Test name
Test status
Simulation time 40774306 ps
CPU time 1.01 seconds
Started Jul 10 06:25:17 PM PDT 24
Finished Jul 10 06:25:20 PM PDT 24
Peak memory 196964 kb
Host smart-f8982d44-061d-48fd-a7f2-bc7eb17665f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165590364 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1165590364
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.134562272
Short name T565
Test name
Test status
Simulation time 13434977 ps
CPU time 0.55 seconds
Started Jul 10 06:25:10 PM PDT 24
Finished Jul 10 06:25:12 PM PDT 24
Peak memory 182288 kb
Host smart-d528c23b-d455-47eb-baa2-10b929751560
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134562272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.134562272
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4203014258
Short name T560
Test name
Test status
Simulation time 13256444 ps
CPU time 0.6 seconds
Started Jul 10 06:25:17 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 182048 kb
Host smart-24e0115c-d290-4387-b78d-ce3c10d4085f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203014258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4203014258
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1675924069
Short name T93
Test name
Test status
Simulation time 42125209 ps
CPU time 0.59 seconds
Started Jul 10 06:25:18 PM PDT 24
Finished Jul 10 06:25:22 PM PDT 24
Peak memory 191096 kb
Host smart-e4b902ae-7c02-45fe-8ee6-f31a79839138
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675924069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1675924069
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4063222362
Short name T506
Test name
Test status
Simulation time 62058266 ps
CPU time 1.59 seconds
Started Jul 10 06:25:11 PM PDT 24
Finished Jul 10 06:25:13 PM PDT 24
Peak memory 197112 kb
Host smart-90ac4232-dbf0-43cc-a6e0-da93cfc74109
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063222362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4063222362
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2638318682
Short name T28
Test name
Test status
Simulation time 67459438 ps
CPU time 1.09 seconds
Started Jul 10 06:25:17 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 182732 kb
Host smart-0accc2bc-525c-4bc7-8a1e-591672f62707
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638318682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2638318682
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.2672598991
Short name T570
Test name
Test status
Simulation time 29166353 ps
CPU time 0.63 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:19 PM PDT 24
Peak memory 193508 kb
Host smart-f35adfae-4409-46b3-b27c-a65141288494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672598991 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.2672598991
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.3157484141
Short name T527
Test name
Test status
Simulation time 52525624 ps
CPU time 0.55 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:20 PM PDT 24
Peak memory 182264 kb
Host smart-e73cc535-c927-40be-b503-d7e8e67b51c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157484141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.3157484141
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.4288895356
Short name T467
Test name
Test status
Simulation time 14308372 ps
CPU time 0.55 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:20 PM PDT 24
Peak memory 182068 kb
Host smart-1b57ad55-5237-4bc3-93d1-01e54c2751ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288895356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.4288895356
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3667896040
Short name T564
Test name
Test status
Simulation time 35422976 ps
CPU time 0.69 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:19 PM PDT 24
Peak memory 191716 kb
Host smart-4d6899f2-1f72-4840-b1ce-18c69746f934
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667896040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3667896040
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3116301758
Short name T455
Test name
Test status
Simulation time 153280525 ps
CPU time 2.77 seconds
Started Jul 10 06:25:21 PM PDT 24
Finished Jul 10 06:25:26 PM PDT 24
Peak memory 197136 kb
Host smart-5d4548bd-7aa9-44cf-aeec-287d1c8514fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116301758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3116301758
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1911577238
Short name T488
Test name
Test status
Simulation time 188724741 ps
CPU time 0.8 seconds
Started Jul 10 06:25:15 PM PDT 24
Finished Jul 10 06:25:17 PM PDT 24
Peak memory 193412 kb
Host smart-19f9131a-2823-481c-923b-6e35aa93fdcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911577238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1911577238
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3707578586
Short name T530
Test name
Test status
Simulation time 384003129 ps
CPU time 1.17 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 197116 kb
Host smart-e8d2756f-72a2-4662-8b01-48d8f0b83012
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707578586 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3707578586
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1137286633
Short name T463
Test name
Test status
Simulation time 11304952 ps
CPU time 0.57 seconds
Started Jul 10 06:25:15 PM PDT 24
Finished Jul 10 06:25:18 PM PDT 24
Peak memory 182092 kb
Host smart-5d7c9385-9dd4-455b-b205-7a2f1790407d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137286633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1137286633
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3729336726
Short name T504
Test name
Test status
Simulation time 40363319 ps
CPU time 0.51 seconds
Started Jul 10 06:25:17 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 181660 kb
Host smart-562a3d7f-5ad9-4487-b21e-886f2b3e0b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729336726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3729336726
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.240488318
Short name T74
Test name
Test status
Simulation time 77958712 ps
CPU time 0.77 seconds
Started Jul 10 06:25:18 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 192908 kb
Host smart-05ee0831-fb87-40d7-b00c-aa5b605b6982
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240488318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_tim
er_same_csr_outstanding.240488318
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3447880111
Short name T464
Test name
Test status
Simulation time 164230440 ps
CPU time 2.28 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 197068 kb
Host smart-768ee641-5710-408a-8c7d-5190d7f0bcd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447880111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3447880111
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1758323219
Short name T566
Test name
Test status
Simulation time 111296690 ps
CPU time 1.37 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:20 PM PDT 24
Peak memory 194924 kb
Host smart-81e8a72b-0958-4a87-bf73-8964061844fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758323219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1758323219
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3106597967
Short name T47
Test name
Test status
Simulation time 30261156 ps
CPU time 0.85 seconds
Started Jul 10 06:25:18 PM PDT 24
Finished Jul 10 06:25:22 PM PDT 24
Peak memory 194572 kb
Host smart-5b55e484-0af2-41a5-acd0-503e8b1a1d7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106597967 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3106597967
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3102529149
Short name T491
Test name
Test status
Simulation time 33810442 ps
CPU time 0.53 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:20 PM PDT 24
Peak memory 182016 kb
Host smart-6f093ca1-4872-4c77-85ac-7ec5b8c464bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102529149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3102529149
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2001431605
Short name T485
Test name
Test status
Simulation time 17630441 ps
CPU time 0.56 seconds
Started Jul 10 06:25:17 PM PDT 24
Finished Jul 10 06:25:20 PM PDT 24
Peak memory 182180 kb
Host smart-c8e098c2-a372-47dc-90cb-f1b3302b4be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001431605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2001431605
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2528063844
Short name T92
Test name
Test status
Simulation time 14867308 ps
CPU time 0.62 seconds
Started Jul 10 06:25:15 PM PDT 24
Finished Jul 10 06:25:17 PM PDT 24
Peak memory 191292 kb
Host smart-736dba08-0625-4b1c-8204-bfd770cf77a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528063844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2528063844
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1305390732
Short name T493
Test name
Test status
Simulation time 577586979 ps
CPU time 2.21 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 197072 kb
Host smart-c6c57c93-ddae-491c-bb05-dc101269e904
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305390732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1305390732
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2557830728
Short name T497
Test name
Test status
Simulation time 195034076 ps
CPU time 1.06 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:19 PM PDT 24
Peak memory 182812 kb
Host smart-53581128-03a8-40f1-9e6c-848fc020e5ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557830728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2557830728
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3149793919
Short name T496
Test name
Test status
Simulation time 45885358 ps
CPU time 0.62 seconds
Started Jul 10 06:25:18 PM PDT 24
Finished Jul 10 06:25:22 PM PDT 24
Peak memory 192752 kb
Host smart-e572093c-9400-4df1-a8ff-8e7b3faab9dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149793919 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3149793919
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.2179950673
Short name T461
Test name
Test status
Simulation time 23063492 ps
CPU time 0.53 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:19 PM PDT 24
Peak memory 182068 kb
Host smart-6638c1d6-93b3-411e-a09d-f8fb30972202
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179950673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.2179950673
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2875129689
Short name T477
Test name
Test status
Simulation time 12762179 ps
CPU time 0.55 seconds
Started Jul 10 06:25:15 PM PDT 24
Finished Jul 10 06:25:17 PM PDT 24
Peak memory 182192 kb
Host smart-4513bad7-7f98-4353-8a0a-78ee9135293f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875129689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2875129689
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.1117306254
Short name T94
Test name
Test status
Simulation time 30402893 ps
CPU time 0.57 seconds
Started Jul 10 06:25:15 PM PDT 24
Finished Jul 10 06:25:18 PM PDT 24
Peak memory 191028 kb
Host smart-7a2ac132-19e5-479d-b644-2735b70e9a86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117306254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.1117306254
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1601148126
Short name T518
Test name
Test status
Simulation time 46733015 ps
CPU time 2.29 seconds
Started Jul 10 06:25:16 PM PDT 24
Finished Jul 10 06:25:21 PM PDT 24
Peak memory 197120 kb
Host smart-e699adda-5ef9-4c8c-9c04-94c1125426d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601148126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1601148126
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.2356478266
Short name T528
Test name
Test status
Simulation time 123615463 ps
CPU time 1.3 seconds
Started Jul 10 06:25:19 PM PDT 24
Finished Jul 10 06:25:23 PM PDT 24
Peak memory 182788 kb
Host smart-93bd6fc8-1c2d-4418-9a63-d759d76ff94f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356478266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.2356478266
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.1987930715
Short name T228
Test name
Test status
Simulation time 5669445543 ps
CPU time 9.53 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:25:40 PM PDT 24
Peak memory 183136 kb
Host smart-6f91ac0d-ac9c-419b-aeb6-411c6b79a60e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987930715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.1987930715
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2716220370
Short name T424
Test name
Test status
Simulation time 252359006482 ps
CPU time 83.45 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:26:54 PM PDT 24
Peak memory 183136 kb
Host smart-4f7bbcf7-75ff-4004-a3ec-58d566a54ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716220370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2716220370
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2080406558
Short name T262
Test name
Test status
Simulation time 47640180131 ps
CPU time 64.58 seconds
Started Jul 10 06:25:31 PM PDT 24
Finished Jul 10 06:26:40 PM PDT 24
Peak memory 183132 kb
Host smart-ffd9ca83-7794-4075-86a3-33e2ec9bf75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080406558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2080406558
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1669004106
Short name T432
Test name
Test status
Simulation time 49381718 ps
CPU time 0.64 seconds
Started Jul 10 06:25:29 PM PDT 24
Finished Jul 10 06:25:35 PM PDT 24
Peak memory 182964 kb
Host smart-99e24750-fe98-4b55-947d-13f5ca3e9a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669004106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1669004106
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.852216454
Short name T376
Test name
Test status
Simulation time 239206502334 ps
CPU time 77.24 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:26:48 PM PDT 24
Peak memory 183340 kb
Host smart-6db8edb2-4bfb-4640-bb59-75202a2cf330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852216454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.852216454
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.1450163686
Short name T304
Test name
Test status
Simulation time 56600414645 ps
CPU time 62.95 seconds
Started Jul 10 06:25:31 PM PDT 24
Finished Jul 10 06:26:38 PM PDT 24
Peak memory 183140 kb
Host smart-8a1dcec9-7b52-4cfe-8c9a-3f5ed301f996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450163686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1450163686
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3793010510
Short name T236
Test name
Test status
Simulation time 123084470791 ps
CPU time 72.19 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:26:49 PM PDT 24
Peak memory 191364 kb
Host smart-1c92fe80-5218-4ba1-a249-e80c17d5ad27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793010510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3793010510
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.4131026786
Short name T15
Test name
Test status
Simulation time 63128385 ps
CPU time 0.84 seconds
Started Jul 10 06:25:28 PM PDT 24
Finished Jul 10 06:25:34 PM PDT 24
Peak memory 213440 kb
Host smart-9475a1f3-817e-403f-a9c1-f367317c7fed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131026786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.4131026786
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2866042314
Short name T354
Test name
Test status
Simulation time 8125484789 ps
CPU time 14.84 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:25:56 PM PDT 24
Peak memory 183132 kb
Host smart-0222c8ff-fe8b-4bfa-a6d3-92d2eb41c009
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866042314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2866042314
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.606364875
Short name T373
Test name
Test status
Simulation time 172854255327 ps
CPU time 277.73 seconds
Started Jul 10 06:25:43 PM PDT 24
Finished Jul 10 06:30:21 PM PDT 24
Peak memory 183156 kb
Host smart-f38bb295-f671-4217-8583-dd61ee99f37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606364875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.606364875
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1553760529
Short name T297
Test name
Test status
Simulation time 346038535351 ps
CPU time 138.14 seconds
Started Jul 10 06:25:41 PM PDT 24
Finished Jul 10 06:28:01 PM PDT 24
Peak memory 193716 kb
Host smart-31908a83-b540-46b3-a3f8-e41e9a4a5dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553760529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1553760529
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.3536456858
Short name T126
Test name
Test status
Simulation time 65678321952 ps
CPU time 99.43 seconds
Started Jul 10 06:26:31 PM PDT 24
Finished Jul 10 06:28:11 PM PDT 24
Peak memory 191320 kb
Host smart-5cbc0235-ec37-4bb7-a77f-ec219bf0c9f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536456858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3536456858
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.3324220350
Short name T186
Test name
Test status
Simulation time 147950162780 ps
CPU time 1058.45 seconds
Started Jul 10 06:26:32 PM PDT 24
Finished Jul 10 06:44:11 PM PDT 24
Peak memory 191380 kb
Host smart-b6eb8fb3-05a9-4194-bd6d-91707bf24e9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324220350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.3324220350
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1798003655
Short name T200
Test name
Test status
Simulation time 678664714149 ps
CPU time 357.8 seconds
Started Jul 10 06:26:36 PM PDT 24
Finished Jul 10 06:32:34 PM PDT 24
Peak memory 191320 kb
Host smart-aa6a3650-f119-48ff-b06d-a4ee0b65867e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798003655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1798003655
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1016211608
Short name T250
Test name
Test status
Simulation time 904524551372 ps
CPU time 708.63 seconds
Started Jul 10 06:26:29 PM PDT 24
Finished Jul 10 06:38:19 PM PDT 24
Peak memory 191324 kb
Host smart-c56cefd4-4735-4b30-89c5-b500ebfdc92a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016211608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1016211608
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2772193474
Short name T436
Test name
Test status
Simulation time 235889205676 ps
CPU time 718.22 seconds
Started Jul 10 06:26:32 PM PDT 24
Finished Jul 10 06:38:31 PM PDT 24
Peak memory 191336 kb
Host smart-f1c2d956-4c52-4459-b6e5-834ec12530ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772193474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2772193474
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1973228235
Short name T341
Test name
Test status
Simulation time 14368848641 ps
CPU time 25.98 seconds
Started Jul 10 06:25:38 PM PDT 24
Finished Jul 10 06:26:06 PM PDT 24
Peak memory 183132 kb
Host smart-9dc2c5ea-d86c-4133-b93e-583d1f7a5982
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973228235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1973228235
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3171154923
Short name T399
Test name
Test status
Simulation time 132905015630 ps
CPU time 196.94 seconds
Started Jul 10 06:25:38 PM PDT 24
Finished Jul 10 06:28:57 PM PDT 24
Peak memory 183136 kb
Host smart-29b31b1b-1cc2-4eb8-85e3-609799c548ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171154923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3171154923
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2799767930
Short name T299
Test name
Test status
Simulation time 302739063037 ps
CPU time 285.85 seconds
Started Jul 10 06:25:37 PM PDT 24
Finished Jul 10 06:30:25 PM PDT 24
Peak memory 191228 kb
Host smart-bdcea037-33db-4cdd-926b-08c69e32c81d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799767930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2799767930
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.4244785539
Short name T405
Test name
Test status
Simulation time 102630969 ps
CPU time 1.52 seconds
Started Jul 10 06:25:38 PM PDT 24
Finished Jul 10 06:25:41 PM PDT 24
Peak memory 183080 kb
Host smart-71a1cf44-e34e-4845-b7a9-2ae11e47a2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244785539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.4244785539
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.501145221
Short name T429
Test name
Test status
Simulation time 287100208033 ps
CPU time 119.35 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:27:41 PM PDT 24
Peak memory 183140 kb
Host smart-1136c71c-aaa2-4a58-bf6d-ef198f39e1c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501145221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
501145221
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/115.rv_timer_random.1790105366
Short name T5
Test name
Test status
Simulation time 242336526989 ps
CPU time 167.87 seconds
Started Jul 10 06:26:32 PM PDT 24
Finished Jul 10 06:29:20 PM PDT 24
Peak memory 191336 kb
Host smart-7b32796d-ecff-4707-9874-5562c9d621ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790105366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1790105366
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2844981172
Short name T295
Test name
Test status
Simulation time 516305259014 ps
CPU time 220.65 seconds
Started Jul 10 06:26:37 PM PDT 24
Finished Jul 10 06:30:18 PM PDT 24
Peak memory 191320 kb
Host smart-17d3fc30-3d8a-4cc2-a576-ee4bf1a99121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844981172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2844981172
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3084401981
Short name T150
Test name
Test status
Simulation time 230356477981 ps
CPU time 146.38 seconds
Started Jul 10 06:26:36 PM PDT 24
Finished Jul 10 06:29:03 PM PDT 24
Peak memory 191348 kb
Host smart-99158a98-1af4-4403-bdcf-90aafcf8aed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084401981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3084401981
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.869676919
Short name T280
Test name
Test status
Simulation time 151932704000 ps
CPU time 133.01 seconds
Started Jul 10 06:26:38 PM PDT 24
Finished Jul 10 06:28:52 PM PDT 24
Peak memory 191364 kb
Host smart-2ab963d0-2d7d-4f65-ba56-a5f552cf9666
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869676919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.869676919
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1722400880
Short name T246
Test name
Test status
Simulation time 30985633409 ps
CPU time 189.73 seconds
Started Jul 10 06:26:38 PM PDT 24
Finished Jul 10 06:29:48 PM PDT 24
Peak memory 191328 kb
Host smart-22117e06-cfc6-4675-9e3a-8bdf165244a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722400880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1722400880
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.83559390
Short name T251
Test name
Test status
Simulation time 670664994610 ps
CPU time 581.84 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:35:24 PM PDT 24
Peak memory 183088 kb
Host smart-5129c630-fa27-4041-a452-4767c4905cbd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83559390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.rv_timer_cfg_update_on_fly.83559390
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1777125639
Short name T3
Test name
Test status
Simulation time 8644285591 ps
CPU time 13.51 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:25:54 PM PDT 24
Peak memory 183152 kb
Host smart-597ffa6c-c55d-4abb-a1f7-5442161b9b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777125639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1777125639
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.283785132
Short name T57
Test name
Test status
Simulation time 43536926 ps
CPU time 0.55 seconds
Started Jul 10 06:25:41 PM PDT 24
Finished Jul 10 06:25:43 PM PDT 24
Peak memory 182956 kb
Host smart-dcf8ad2b-c353-46b6-b2fc-7d0ff293c3c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283785132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
283785132
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.618366916
Short name T270
Test name
Test status
Simulation time 38079067927 ps
CPU time 92.33 seconds
Started Jul 10 06:26:37 PM PDT 24
Finished Jul 10 06:28:10 PM PDT 24
Peak memory 191360 kb
Host smart-25ee13c6-6d3b-44d3-979b-626a905537ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618366916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.618366916
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.1513216348
Short name T357
Test name
Test status
Simulation time 81532854988 ps
CPU time 248.09 seconds
Started Jul 10 06:26:37 PM PDT 24
Finished Jul 10 06:30:46 PM PDT 24
Peak memory 191260 kb
Host smart-3b2655e6-dd32-4a1f-b2e6-09a65cb2c0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513216348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.1513216348
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.776072942
Short name T437
Test name
Test status
Simulation time 55606774150 ps
CPU time 99.04 seconds
Started Jul 10 06:26:42 PM PDT 24
Finished Jul 10 06:28:22 PM PDT 24
Peak memory 191336 kb
Host smart-4b294aad-2aca-4554-ba3c-6843141e47df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776072942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.776072942
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2443511353
Short name T277
Test name
Test status
Simulation time 324759167605 ps
CPU time 129.17 seconds
Started Jul 10 06:26:43 PM PDT 24
Finished Jul 10 06:28:53 PM PDT 24
Peak memory 191344 kb
Host smart-f2490f47-3831-46c8-aecd-db6c95c20db3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443511353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2443511353
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.3440797768
Short name T145
Test name
Test status
Simulation time 212134176593 ps
CPU time 1080.87 seconds
Started Jul 10 06:26:48 PM PDT 24
Finished Jul 10 06:44:50 PM PDT 24
Peak memory 193968 kb
Host smart-6e6e4441-29b5-4b18-9365-43469a4a01c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440797768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.3440797768
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3259088776
Short name T242
Test name
Test status
Simulation time 36631135611 ps
CPU time 23.7 seconds
Started Jul 10 06:26:48 PM PDT 24
Finished Jul 10 06:27:13 PM PDT 24
Peak memory 193544 kb
Host smart-32a6fa26-4c57-4b60-a23f-fa144f150a36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259088776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3259088776
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.170249814
Short name T319
Test name
Test status
Simulation time 40790782100 ps
CPU time 93.26 seconds
Started Jul 10 06:26:43 PM PDT 24
Finished Jul 10 06:28:17 PM PDT 24
Peak memory 183084 kb
Host smart-3f8d3f54-006b-4bb2-8df4-65f9fba49fd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170249814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.170249814
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1558846947
Short name T169
Test name
Test status
Simulation time 91026037624 ps
CPU time 153.77 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:28:15 PM PDT 24
Peak memory 183124 kb
Host smart-9cc482be-51d6-4a3c-9ff7-a859ed46659d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558846947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1558846947
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.2567565680
Short name T374
Test name
Test status
Simulation time 625923913326 ps
CPU time 250.97 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:29:53 PM PDT 24
Peak memory 183132 kb
Host smart-84964740-ed5a-4f6f-90fa-3b238da1bceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567565680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.2567565680
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.609021403
Short name T396
Test name
Test status
Simulation time 11600128127 ps
CPU time 6.25 seconds
Started Jul 10 06:25:44 PM PDT 24
Finished Jul 10 06:25:51 PM PDT 24
Peak memory 183136 kb
Host smart-09386190-947b-4c70-bb21-e29fb6eca032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609021403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.609021403
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.2136040589
Short name T12
Test name
Test status
Simulation time 51726825011 ps
CPU time 216.69 seconds
Started Jul 10 06:25:40 PM PDT 24
Finished Jul 10 06:29:19 PM PDT 24
Peak memory 206048 kb
Host smart-3f1229d4-d2e1-4217-aabe-7ac8148e198f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136040589 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.2136040589
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2317127185
Short name T271
Test name
Test status
Simulation time 154041250919 ps
CPU time 149.23 seconds
Started Jul 10 06:26:44 PM PDT 24
Finished Jul 10 06:29:14 PM PDT 24
Peak memory 183136 kb
Host smart-2c5a48e6-74ec-4348-acca-bb94b09cc1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317127185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2317127185
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1986883397
Short name T452
Test name
Test status
Simulation time 85663831683 ps
CPU time 71.04 seconds
Started Jul 10 06:26:44 PM PDT 24
Finished Jul 10 06:27:56 PM PDT 24
Peak memory 191328 kb
Host smart-84369330-656d-46b8-aab8-92bfa40a4d46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986883397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1986883397
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.1084916872
Short name T347
Test name
Test status
Simulation time 21483761335 ps
CPU time 18.33 seconds
Started Jul 10 06:26:44 PM PDT 24
Finished Jul 10 06:27:03 PM PDT 24
Peak memory 183136 kb
Host smart-dac828bb-40d1-41b4-a4b7-5e9babb56896
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084916872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1084916872
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.1470372560
Short name T384
Test name
Test status
Simulation time 63018163620 ps
CPU time 75.26 seconds
Started Jul 10 06:26:49 PM PDT 24
Finished Jul 10 06:28:05 PM PDT 24
Peak memory 183132 kb
Host smart-64410eaa-9254-430c-9872-eae8f5c9b4f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470372560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.1470372560
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2852474180
Short name T408
Test name
Test status
Simulation time 404594084361 ps
CPU time 768.6 seconds
Started Jul 10 06:26:48 PM PDT 24
Finished Jul 10 06:39:37 PM PDT 24
Peak memory 183112 kb
Host smart-86cf96d0-3b3b-44fe-a7d2-18d6ca34e41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852474180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2852474180
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.448412337
Short name T227
Test name
Test status
Simulation time 50030595281 ps
CPU time 290.43 seconds
Started Jul 10 06:26:54 PM PDT 24
Finished Jul 10 06:31:45 PM PDT 24
Peak memory 191340 kb
Host smart-bec2b348-33de-4ec7-99a3-3d13e17fc059
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448412337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.448412337
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2877569946
Short name T1
Test name
Test status
Simulation time 168181717514 ps
CPU time 588.48 seconds
Started Jul 10 06:26:56 PM PDT 24
Finished Jul 10 06:36:45 PM PDT 24
Peak memory 195180 kb
Host smart-b0ee715d-4ff6-4ee3-ae86-26d7fabb9fdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877569946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2877569946
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2432581418
Short name T175
Test name
Test status
Simulation time 289637028814 ps
CPU time 144.29 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:28:06 PM PDT 24
Peak memory 183108 kb
Host smart-c474a058-82e6-4e03-83d5-bd30957263d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432581418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2432581418
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.4216504328
Short name T434
Test name
Test status
Simulation time 141277592155 ps
CPU time 189.92 seconds
Started Jul 10 06:25:37 PM PDT 24
Finished Jul 10 06:28:49 PM PDT 24
Peak memory 183072 kb
Host smart-9f4b93d6-9743-4808-bb33-b3eb4f5f6580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216504328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4216504328
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/140.rv_timer_random.1006196651
Short name T239
Test name
Test status
Simulation time 128350512454 ps
CPU time 169.5 seconds
Started Jul 10 06:26:56 PM PDT 24
Finished Jul 10 06:29:46 PM PDT 24
Peak memory 183136 kb
Host smart-d41d97b5-03a5-4c7d-b843-bad92dd329e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006196651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1006196651
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.2178343136
Short name T413
Test name
Test status
Simulation time 95679181395 ps
CPU time 183.45 seconds
Started Jul 10 06:26:55 PM PDT 24
Finished Jul 10 06:29:59 PM PDT 24
Peak memory 191352 kb
Host smart-4dac58a9-8c5d-4857-8f57-95563ee8c86b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178343136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2178343136
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3042985887
Short name T194
Test name
Test status
Simulation time 209510736749 ps
CPU time 261.85 seconds
Started Jul 10 06:26:56 PM PDT 24
Finished Jul 10 06:31:18 PM PDT 24
Peak memory 191356 kb
Host smart-68de615f-3a1e-4008-a6d0-e98fb65b50a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042985887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3042985887
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.884690807
Short name T431
Test name
Test status
Simulation time 5886900553 ps
CPU time 8.44 seconds
Started Jul 10 06:26:54 PM PDT 24
Finished Jul 10 06:27:03 PM PDT 24
Peak memory 183036 kb
Host smart-39735f01-a0d5-4431-aeed-20474b37a57e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884690807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.884690807
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.761961230
Short name T287
Test name
Test status
Simulation time 54261110768 ps
CPU time 75.61 seconds
Started Jul 10 06:27:00 PM PDT 24
Finished Jul 10 06:28:16 PM PDT 24
Peak memory 191360 kb
Host smart-693e7fb1-bcc7-43d5-902d-78857095f2ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761961230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.761961230
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.2596088823
Short name T51
Test name
Test status
Simulation time 21675227626 ps
CPU time 34.21 seconds
Started Jul 10 06:27:04 PM PDT 24
Finished Jul 10 06:27:39 PM PDT 24
Peak memory 183036 kb
Host smart-cccff1a0-3587-4639-af58-d20cb98a4263
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596088823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.2596088823
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.2983208646
Short name T359
Test name
Test status
Simulation time 636970939141 ps
CPU time 225 seconds
Started Jul 10 06:25:40 PM PDT 24
Finished Jul 10 06:29:27 PM PDT 24
Peak memory 183144 kb
Host smart-d7b9fcf4-492d-48e9-8da7-b37017abae34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983208646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.2983208646
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1834038195
Short name T322
Test name
Test status
Simulation time 63424871570 ps
CPU time 176.68 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:28:43 PM PDT 24
Peak memory 183140 kb
Host smart-58a29b79-cc5b-482b-bc77-923a8d8ec4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834038195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1834038195
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1237707972
Short name T64
Test name
Test status
Simulation time 2728267106278 ps
CPU time 962.43 seconds
Started Jul 10 06:25:53 PM PDT 24
Finished Jul 10 06:41:56 PM PDT 24
Peak memory 190656 kb
Host smart-6e212798-0c11-404d-81bc-6ea2edab37ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237707972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1237707972
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.1237707100
Short name T164
Test name
Test status
Simulation time 631582746546 ps
CPU time 341.66 seconds
Started Jul 10 06:27:04 PM PDT 24
Finished Jul 10 06:32:46 PM PDT 24
Peak memory 191324 kb
Host smart-f1e42484-46fd-4c4c-96b3-e744c4ba6b99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237707100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1237707100
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.889286189
Short name T207
Test name
Test status
Simulation time 261791220922 ps
CPU time 926.89 seconds
Started Jul 10 06:27:05 PM PDT 24
Finished Jul 10 06:42:33 PM PDT 24
Peak memory 191340 kb
Host smart-e53ac8bb-593b-483b-ba5a-ac480d57839e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889286189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.889286189
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2082849426
Short name T244
Test name
Test status
Simulation time 419006993611 ps
CPU time 166.61 seconds
Started Jul 10 06:27:04 PM PDT 24
Finished Jul 10 06:29:52 PM PDT 24
Peak memory 191336 kb
Host smart-02641224-72ca-480f-8276-0b893b454b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082849426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2082849426
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3049434100
Short name T420
Test name
Test status
Simulation time 27695753748 ps
CPU time 45.81 seconds
Started Jul 10 06:27:04 PM PDT 24
Finished Jul 10 06:27:51 PM PDT 24
Peak memory 183140 kb
Host smart-3b4e0066-c5fa-4b92-aff1-9f1e8b1cef5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049434100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3049434100
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3624590983
Short name T117
Test name
Test status
Simulation time 628511207520 ps
CPU time 666.9 seconds
Started Jul 10 06:27:04 PM PDT 24
Finished Jul 10 06:38:12 PM PDT 24
Peak memory 191316 kb
Host smart-483eba74-f84c-4373-917a-3a0f68efb1c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624590983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3624590983
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1441299189
Short name T309
Test name
Test status
Simulation time 75792952661 ps
CPU time 38.54 seconds
Started Jul 10 06:27:05 PM PDT 24
Finished Jul 10 06:27:45 PM PDT 24
Peak memory 183140 kb
Host smart-44069949-ef44-4801-ba06-27b1135db0fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441299189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1441299189
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1802313837
Short name T7
Test name
Test status
Simulation time 326358359504 ps
CPU time 206.88 seconds
Started Jul 10 06:27:04 PM PDT 24
Finished Jul 10 06:30:33 PM PDT 24
Peak memory 194196 kb
Host smart-a6808b81-57d1-4d6a-a4d3-6b01661e0634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802313837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1802313837
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.46093764
Short name T303
Test name
Test status
Simulation time 51550591010 ps
CPU time 633.79 seconds
Started Jul 10 06:27:05 PM PDT 24
Finished Jul 10 06:37:40 PM PDT 24
Peak memory 191336 kb
Host smart-6e92375f-766c-4f79-b979-d5c2001afd51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46093764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.46093764
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3874417097
Short name T276
Test name
Test status
Simulation time 1560523039612 ps
CPU time 505.76 seconds
Started Jul 10 06:27:05 PM PDT 24
Finished Jul 10 06:35:32 PM PDT 24
Peak memory 191380 kb
Host smart-7c7c4ada-de5c-4c4e-b4ae-595d8b4bfe05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874417097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3874417097
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2225727552
Short name T272
Test name
Test status
Simulation time 29630078310 ps
CPU time 15.63 seconds
Started Jul 10 06:25:47 PM PDT 24
Finished Jul 10 06:26:04 PM PDT 24
Peak memory 183116 kb
Host smart-3cbbfb67-e5df-493a-a186-8568e5f746e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225727552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2225727552
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.365381435
Short name T428
Test name
Test status
Simulation time 552740793722 ps
CPU time 140.84 seconds
Started Jul 10 06:25:53 PM PDT 24
Finished Jul 10 06:28:14 PM PDT 24
Peak memory 182192 kb
Host smart-fd0220df-d556-4d27-8669-941ef853fbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365381435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.365381435
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2565650242
Short name T155
Test name
Test status
Simulation time 1835144855620 ps
CPU time 424.45 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:32:51 PM PDT 24
Peak memory 191340 kb
Host smart-51fcb897-994c-450e-9e9a-7576f9271e62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565650242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2565650242
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.354393327
Short name T442
Test name
Test status
Simulation time 40406117776 ps
CPU time 84.49 seconds
Started Jul 10 06:25:44 PM PDT 24
Finished Jul 10 06:27:09 PM PDT 24
Peak memory 194976 kb
Host smart-eb277182-1429-43fa-80a1-8fc9ee1fb57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354393327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.354393327
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.640847788
Short name T421
Test name
Test status
Simulation time 427470535166 ps
CPU time 139.3 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:28:06 PM PDT 24
Peak memory 183084 kb
Host smart-182202eb-4b73-466e-aad0-802853a70e78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640847788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
640847788
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.816559978
Short name T245
Test name
Test status
Simulation time 221747332108 ps
CPU time 798.97 seconds
Started Jul 10 06:27:04 PM PDT 24
Finished Jul 10 06:40:24 PM PDT 24
Peak memory 191340 kb
Host smart-8342552c-8871-47c9-b855-595461163f2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816559978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.816559978
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3361570627
Short name T325
Test name
Test status
Simulation time 22350761440 ps
CPU time 174.66 seconds
Started Jul 10 06:27:04 PM PDT 24
Finished Jul 10 06:30:00 PM PDT 24
Peak memory 183128 kb
Host smart-4d9d7034-fab8-47e1-9168-7513b280fa3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361570627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3361570627
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.4149664819
Short name T26
Test name
Test status
Simulation time 742250380864 ps
CPU time 1489.03 seconds
Started Jul 10 06:27:12 PM PDT 24
Finished Jul 10 06:52:02 PM PDT 24
Peak memory 191388 kb
Host smart-92a8b40f-1842-4929-9fe3-89fa3ab8bacc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149664819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.4149664819
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1738178795
Short name T440
Test name
Test status
Simulation time 50891676405 ps
CPU time 22.05 seconds
Started Jul 10 06:27:12 PM PDT 24
Finished Jul 10 06:27:36 PM PDT 24
Peak memory 183336 kb
Host smart-cc9c377b-012d-4386-b2f5-c81df3a4fe4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738178795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1738178795
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2886546147
Short name T159
Test name
Test status
Simulation time 35000758667 ps
CPU time 72.6 seconds
Started Jul 10 06:27:10 PM PDT 24
Finished Jul 10 06:28:24 PM PDT 24
Peak memory 191356 kb
Host smart-5f8bb8f8-3b1c-4652-852b-fa498fb6d3e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886546147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2886546147
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1397551446
Short name T217
Test name
Test status
Simulation time 39882850179 ps
CPU time 40.19 seconds
Started Jul 10 06:27:11 PM PDT 24
Finished Jul 10 06:27:53 PM PDT 24
Peak memory 183140 kb
Host smart-deb3b66f-8a5b-4710-b944-37b03ac83edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397551446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1397551446
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2957074332
Short name T144
Test name
Test status
Simulation time 919604654839 ps
CPU time 552.04 seconds
Started Jul 10 06:27:16 PM PDT 24
Finished Jul 10 06:36:29 PM PDT 24
Peak memory 191332 kb
Host smart-57a3c1e4-4a05-45a5-aa23-bddb003f8759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957074332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2957074332
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3874054614
Short name T323
Test name
Test status
Simulation time 28520659660 ps
CPU time 43.77 seconds
Started Jul 10 06:27:17 PM PDT 24
Finished Jul 10 06:28:01 PM PDT 24
Peak memory 183052 kb
Host smart-0cdd6194-c507-4469-ae68-49badc4317d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874054614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3874054614
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1298457461
Short name T349
Test name
Test status
Simulation time 60728838741 ps
CPU time 96.46 seconds
Started Jul 10 06:25:43 PM PDT 24
Finished Jul 10 06:27:20 PM PDT 24
Peak memory 183152 kb
Host smart-06b57320-f4d3-4e1a-8e1b-71a914b2bf73
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298457461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1298457461
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1284736174
Short name T390
Test name
Test status
Simulation time 60956135084 ps
CPU time 80.11 seconds
Started Jul 10 06:25:46 PM PDT 24
Finished Jul 10 06:27:08 PM PDT 24
Peak memory 183144 kb
Host smart-34bb582e-3689-4888-ad7a-539565e616be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284736174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1284736174
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3927668006
Short name T255
Test name
Test status
Simulation time 204673900527 ps
CPU time 142.98 seconds
Started Jul 10 06:25:47 PM PDT 24
Finished Jul 10 06:28:12 PM PDT 24
Peak memory 191316 kb
Host smart-5c5568d4-9ee2-4e54-819f-60ec761ccc22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927668006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3927668006
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1682121686
Short name T403
Test name
Test status
Simulation time 201624087 ps
CPU time 0.7 seconds
Started Jul 10 06:25:44 PM PDT 24
Finished Jul 10 06:25:46 PM PDT 24
Peak memory 183020 kb
Host smart-4be13e1c-ae78-4226-8d36-3b1e799d5f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682121686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1682121686
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.1292810790
Short name T419
Test name
Test status
Simulation time 52160089938 ps
CPU time 160.95 seconds
Started Jul 10 06:27:15 PM PDT 24
Finished Jul 10 06:29:57 PM PDT 24
Peak memory 191344 kb
Host smart-ecadf6a0-513e-475c-b5ce-319d56a42fe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292810790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1292810790
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3718284543
Short name T188
Test name
Test status
Simulation time 136559386265 ps
CPU time 406.14 seconds
Started Jul 10 06:27:16 PM PDT 24
Finished Jul 10 06:34:04 PM PDT 24
Peak memory 191328 kb
Host smart-22afa90c-b236-4228-b339-9ceca001502d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718284543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3718284543
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1386283350
Short name T136
Test name
Test status
Simulation time 44344400600 ps
CPU time 40.56 seconds
Started Jul 10 06:27:17 PM PDT 24
Finished Jul 10 06:27:59 PM PDT 24
Peak memory 183136 kb
Host smart-2025cddd-7dbd-4c3b-aaf5-37103ca1104a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386283350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1386283350
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.845660417
Short name T388
Test name
Test status
Simulation time 176393339152 ps
CPU time 110.88 seconds
Started Jul 10 06:27:17 PM PDT 24
Finished Jul 10 06:29:09 PM PDT 24
Peak memory 183036 kb
Host smart-b3859c36-fbb8-488a-9706-0008e0865dd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845660417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.845660417
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2330581979
Short name T210
Test name
Test status
Simulation time 186863810127 ps
CPU time 752.92 seconds
Started Jul 10 06:27:17 PM PDT 24
Finished Jul 10 06:39:51 PM PDT 24
Peak memory 191328 kb
Host smart-e33c797c-703e-4504-90ff-390a6d0810e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330581979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2330581979
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.1361914594
Short name T301
Test name
Test status
Simulation time 83010546949 ps
CPU time 1392.38 seconds
Started Jul 10 06:27:26 PM PDT 24
Finished Jul 10 06:50:40 PM PDT 24
Peak memory 191536 kb
Host smart-7e872be2-672d-4117-a00c-367c931d1a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361914594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.1361914594
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2044968069
Short name T326
Test name
Test status
Simulation time 115012018166 ps
CPU time 121.89 seconds
Started Jul 10 06:27:25 PM PDT 24
Finished Jul 10 06:29:28 PM PDT 24
Peak memory 191232 kb
Host smart-0a46ed21-1304-4bbe-ac2e-6db673118b90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044968069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2044968069
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1311131799
Short name T339
Test name
Test status
Simulation time 205701898640 ps
CPU time 749.5 seconds
Started Jul 10 06:27:23 PM PDT 24
Finished Jul 10 06:39:54 PM PDT 24
Peak memory 191308 kb
Host smart-e151a339-2be7-4d52-b3dc-a6c43d351100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311131799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1311131799
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1196911289
Short name T305
Test name
Test status
Simulation time 230448421128 ps
CPU time 384.94 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:32:12 PM PDT 24
Peak memory 183136 kb
Host smart-1ce940a8-84d4-43f6-8c8a-65caf3ab1bc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196911289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1196911289
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.4006620670
Short name T404
Test name
Test status
Simulation time 100142986315 ps
CPU time 53.64 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:26:40 PM PDT 24
Peak memory 183088 kb
Host smart-95863450-2826-43bb-83fe-2709b5db9480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006620670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.4006620670
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1750467981
Short name T336
Test name
Test status
Simulation time 48389142812 ps
CPU time 63.79 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:26:50 PM PDT 24
Peak memory 191336 kb
Host smart-4d07fdad-217d-4c4b-9b59-b78d0463b6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750467981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1750467981
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1390149735
Short name T379
Test name
Test status
Simulation time 785251575822 ps
CPU time 343.59 seconds
Started Jul 10 06:25:44 PM PDT 24
Finished Jul 10 06:31:28 PM PDT 24
Peak memory 191312 kb
Host smart-6ea15240-c050-40f2-8265-1cdc17df904c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390149735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1390149735
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all_with_rand_reset.204197780
Short name T34
Test name
Test status
Simulation time 12479306226 ps
CPU time 126.18 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:27:53 PM PDT 24
Peak memory 197820 kb
Host smart-1867900a-7da3-4aee-8ef0-7aa7bde6911a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204197780 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all_with_rand_reset.204197780
Directory /workspace/18.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.3212161547
Short name T445
Test name
Test status
Simulation time 294905959470 ps
CPU time 218.69 seconds
Started Jul 10 06:27:24 PM PDT 24
Finished Jul 10 06:31:04 PM PDT 24
Peak memory 191332 kb
Host smart-eade42e5-b8cc-4585-8954-d84168f967f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212161547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3212161547
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3985875802
Short name T265
Test name
Test status
Simulation time 227592214032 ps
CPU time 108.17 seconds
Started Jul 10 06:27:25 PM PDT 24
Finished Jul 10 06:29:14 PM PDT 24
Peak memory 191340 kb
Host smart-93c4484c-d030-4d55-844f-88b42235c735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985875802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3985875802
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.899858675
Short name T170
Test name
Test status
Simulation time 253745894974 ps
CPU time 1111.72 seconds
Started Jul 10 06:27:23 PM PDT 24
Finished Jul 10 06:45:56 PM PDT 24
Peak memory 191284 kb
Host smart-4843fc4a-98d2-4f0d-a694-1e523f16035c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899858675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.899858675
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1974058600
Short name T115
Test name
Test status
Simulation time 127543166189 ps
CPU time 481.06 seconds
Started Jul 10 06:27:29 PM PDT 24
Finished Jul 10 06:35:31 PM PDT 24
Peak memory 191368 kb
Host smart-d008ba37-28b7-42bc-8e38-32ee2596a632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974058600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1974058600
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2502189915
Short name T346
Test name
Test status
Simulation time 622201582226 ps
CPU time 351.95 seconds
Started Jul 10 06:27:31 PM PDT 24
Finished Jul 10 06:33:24 PM PDT 24
Peak memory 191348 kb
Host smart-89512a0b-c74d-42ec-bf80-97330f1fbabd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502189915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2502189915
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2398885903
Short name T104
Test name
Test status
Simulation time 82311972876 ps
CPU time 268.89 seconds
Started Jul 10 06:27:31 PM PDT 24
Finished Jul 10 06:32:01 PM PDT 24
Peak memory 191344 kb
Host smart-18f0209c-f499-42c0-b625-bf6aace9830e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398885903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2398885903
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.129377690
Short name T208
Test name
Test status
Simulation time 63811168430 ps
CPU time 260.17 seconds
Started Jul 10 06:27:30 PM PDT 24
Finished Jul 10 06:31:52 PM PDT 24
Peak memory 191332 kb
Host smart-2ccffb12-04ab-441a-ba5c-bbd0e4420abf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129377690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.129377690
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1330355050
Short name T58
Test name
Test status
Simulation time 531421492908 ps
CPU time 182.15 seconds
Started Jul 10 06:25:46 PM PDT 24
Finished Jul 10 06:28:50 PM PDT 24
Peak memory 183148 kb
Host smart-b3ee325c-f5e5-481d-9376-15c580353626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330355050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1330355050
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1317830171
Short name T356
Test name
Test status
Simulation time 75571471046 ps
CPU time 49.61 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:26:36 PM PDT 24
Peak memory 183152 kb
Host smart-71c140cb-a4d5-4991-8162-c7f87e0b6751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317830171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1317830171
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2758252904
Short name T368
Test name
Test status
Simulation time 16660447651 ps
CPU time 13.64 seconds
Started Jul 10 06:25:46 PM PDT 24
Finished Jul 10 06:26:01 PM PDT 24
Peak memory 183172 kb
Host smart-62e333e8-8a7c-4a85-a3b4-b81fba96dfdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758252904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2758252904
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.388158841
Short name T363
Test name
Test status
Simulation time 97603184319 ps
CPU time 123.91 seconds
Started Jul 10 06:25:46 PM PDT 24
Finished Jul 10 06:27:51 PM PDT 24
Peak memory 191336 kb
Host smart-2fbc5547-df03-47e2-bf8f-25a4ab7c1d76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388158841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
388158841
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all_with_rand_reset.3017852826
Short name T35
Test name
Test status
Simulation time 39933470417 ps
CPU time 350.61 seconds
Started Jul 10 06:25:46 PM PDT 24
Finished Jul 10 06:31:38 PM PDT 24
Peak memory 206028 kb
Host smart-470f5b38-5a30-4de8-ae1f-e0e66460f4b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017852826 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all_with_rand_reset.3017852826
Directory /workspace/19.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.3200146896
Short name T427
Test name
Test status
Simulation time 260696984255 ps
CPU time 116.41 seconds
Started Jul 10 06:27:30 PM PDT 24
Finished Jul 10 06:29:27 PM PDT 24
Peak memory 191328 kb
Host smart-e0462974-20a9-4b0d-af48-d6005af0bbcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200146896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3200146896
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2318186708
Short name T286
Test name
Test status
Simulation time 81502545524 ps
CPU time 127.77 seconds
Started Jul 10 06:27:29 PM PDT 24
Finished Jul 10 06:29:37 PM PDT 24
Peak memory 191312 kb
Host smart-ccc9cb79-9573-42a4-ad9f-e973bad41390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318186708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2318186708
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3995496339
Short name T185
Test name
Test status
Simulation time 323933301555 ps
CPU time 189.83 seconds
Started Jul 10 06:27:30 PM PDT 24
Finished Jul 10 06:30:41 PM PDT 24
Peak memory 191336 kb
Host smart-890030aa-7aae-48ea-ba87-84fe8b1cf41a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995496339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3995496339
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3189904617
Short name T237
Test name
Test status
Simulation time 934233049999 ps
CPU time 166.9 seconds
Started Jul 10 06:27:31 PM PDT 24
Finished Jul 10 06:30:19 PM PDT 24
Peak memory 191336 kb
Host smart-d1991774-9dc6-421a-b74c-af1ac348a390
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189904617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3189904617
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2700709244
Short name T9
Test name
Test status
Simulation time 359594870449 ps
CPU time 209.02 seconds
Started Jul 10 06:27:32 PM PDT 24
Finished Jul 10 06:31:02 PM PDT 24
Peak memory 191344 kb
Host smart-cbe96e39-d438-49ce-8657-a407ea75d6a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700709244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2700709244
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1404216709
Short name T165
Test name
Test status
Simulation time 419339948466 ps
CPU time 264.95 seconds
Started Jul 10 06:27:31 PM PDT 24
Finished Jul 10 06:31:57 PM PDT 24
Peak memory 191328 kb
Host smart-5a98af95-cc2b-4fbc-8b4c-6ace4c8b85ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404216709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1404216709
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.4107784681
Short name T283
Test name
Test status
Simulation time 170682978522 ps
CPU time 129.38 seconds
Started Jul 10 06:27:29 PM PDT 24
Finished Jul 10 06:29:40 PM PDT 24
Peak memory 191340 kb
Host smart-c74f7bf5-5b28-40f0-8904-b1d98af7b931
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107784681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.4107784681
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.963676109
Short name T230
Test name
Test status
Simulation time 85377141366 ps
CPU time 347.72 seconds
Started Jul 10 06:27:30 PM PDT 24
Finished Jul 10 06:33:19 PM PDT 24
Peak memory 193580 kb
Host smart-95f883ac-498a-430b-af9b-f01514e79d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963676109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.963676109
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1286359528
Short name T328
Test name
Test status
Simulation time 124232354122 ps
CPU time 129.54 seconds
Started Jul 10 06:27:29 PM PDT 24
Finished Jul 10 06:29:40 PM PDT 24
Peak memory 191324 kb
Host smart-8a6e03bd-0a27-479d-a2c6-3043929111cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286359528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1286359528
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.1426875718
Short name T402
Test name
Test status
Simulation time 404012133580 ps
CPU time 120.96 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:27:38 PM PDT 24
Peak memory 183084 kb
Host smart-f269ff8f-7027-4a3c-9c64-ff0e31e95086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426875718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.1426875718
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.3373001086
Short name T193
Test name
Test status
Simulation time 284770778254 ps
CPU time 149.9 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:28:08 PM PDT 24
Peak memory 191348 kb
Host smart-341abef8-ae50-4062-b635-18ebbaa5704f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373001086 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.3373001086
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1860663841
Short name T274
Test name
Test status
Simulation time 74282745481 ps
CPU time 243.9 seconds
Started Jul 10 06:25:33 PM PDT 24
Finished Jul 10 06:29:41 PM PDT 24
Peak memory 194292 kb
Host smart-fa699ecb-3728-4659-a8e1-9836b6583bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860663841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1860663841
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.177666578
Short name T14
Test name
Test status
Simulation time 174003528 ps
CPU time 0.95 seconds
Started Jul 10 06:25:35 PM PDT 24
Finished Jul 10 06:25:39 PM PDT 24
Peak memory 214592 kb
Host smart-d8be8396-c9d1-4ca3-b41f-d690152ec633
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177666578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.177666578
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.102463005
Short name T398
Test name
Test status
Simulation time 632983550173 ps
CPU time 496.53 seconds
Started Jul 10 06:25:35 PM PDT 24
Finished Jul 10 06:33:54 PM PDT 24
Peak memory 194780 kb
Host smart-0a018471-b8ca-444a-97d1-b41363bb0a1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102463005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.102463005
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2606030665
Short name T158
Test name
Test status
Simulation time 103925803304 ps
CPU time 59.68 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:26:46 PM PDT 24
Peak memory 183128 kb
Host smart-42f85d6b-cc4c-4e21-8ed2-3af9a5aeb6c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606030665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2606030665
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1944471333
Short name T416
Test name
Test status
Simulation time 402972943777 ps
CPU time 155.21 seconds
Started Jul 10 06:25:44 PM PDT 24
Finished Jul 10 06:28:21 PM PDT 24
Peak memory 183136 kb
Host smart-799dd6be-e810-4745-9a22-00b7fcae43a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944471333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1944471333
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1313014027
Short name T24
Test name
Test status
Simulation time 88249806147 ps
CPU time 567.67 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:35:15 PM PDT 24
Peak memory 191340 kb
Host smart-e0abe59a-74b4-4e4a-ad05-8664b17b2825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313014027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1313014027
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3106750014
Short name T367
Test name
Test status
Simulation time 13964168656 ps
CPU time 19.8 seconds
Started Jul 10 06:25:54 PM PDT 24
Finished Jul 10 06:26:14 PM PDT 24
Peak memory 183168 kb
Host smart-cfd504a2-4ce9-400b-a24e-397c32f560a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106750014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3106750014
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.735894284
Short name T229
Test name
Test status
Simulation time 502195106323 ps
CPU time 449.56 seconds
Started Jul 10 06:25:45 PM PDT 24
Finished Jul 10 06:33:17 PM PDT 24
Peak memory 191336 kb
Host smart-c825f8f1-0644-46af-abbb-290b156f6eb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735894284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.735894284
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.752977186
Short name T412
Test name
Test status
Simulation time 89541945 ps
CPU time 0.75 seconds
Started Jul 10 06:25:54 PM PDT 24
Finished Jul 10 06:25:56 PM PDT 24
Peak memory 183024 kb
Host smart-7df4d6f2-6410-41a4-ad30-38668ecd9582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752977186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.752977186
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1418972172
Short name T300
Test name
Test status
Simulation time 225424881241 ps
CPU time 123.91 seconds
Started Jul 10 06:25:55 PM PDT 24
Finished Jul 10 06:28:00 PM PDT 24
Peak memory 183180 kb
Host smart-55a93055-5c69-4e18-b6b0-6f40fe874f51
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418972172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1418972172
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.4180262257
Short name T422
Test name
Test status
Simulation time 49596334717 ps
CPU time 61.45 seconds
Started Jul 10 06:25:50 PM PDT 24
Finished Jul 10 06:26:53 PM PDT 24
Peak memory 183184 kb
Host smart-ef52c6c9-9096-45b5-b688-023e10213f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180262257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.4180262257
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1793122385
Short name T127
Test name
Test status
Simulation time 211477700568 ps
CPU time 137.48 seconds
Started Jul 10 06:26:01 PM PDT 24
Finished Jul 10 06:28:20 PM PDT 24
Peak memory 191332 kb
Host smart-a3291a69-d0a2-4fe3-b325-bfe5b902cf28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793122385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1793122385
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3272620297
Short name T387
Test name
Test status
Simulation time 9083885158 ps
CPU time 6.59 seconds
Started Jul 10 06:25:50 PM PDT 24
Finished Jul 10 06:25:58 PM PDT 24
Peak memory 183160 kb
Host smart-e62ea0b3-3788-430e-a53e-f8e26cd5f44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272620297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3272620297
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.4040103508
Short name T324
Test name
Test status
Simulation time 330404002064 ps
CPU time 478.56 seconds
Started Jul 10 06:25:53 PM PDT 24
Finished Jul 10 06:33:52 PM PDT 24
Peak memory 183148 kb
Host smart-abd5a6a4-a8b0-4dbb-93cc-a38d9e7ed282
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040103508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.4040103508
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2393351908
Short name T439
Test name
Test status
Simulation time 92444189225 ps
CPU time 143.34 seconds
Started Jul 10 06:25:53 PM PDT 24
Finished Jul 10 06:28:17 PM PDT 24
Peak memory 183168 kb
Host smart-bbf7e874-1543-4538-ac4a-59f3b1cd42f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393351908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2393351908
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1241270010
Short name T137
Test name
Test status
Simulation time 84843620272 ps
CPU time 118.41 seconds
Started Jul 10 06:25:54 PM PDT 24
Finished Jul 10 06:27:54 PM PDT 24
Peak memory 191260 kb
Host smart-ee286305-1713-4acc-a4d5-cc7cf96cbadc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241270010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1241270010
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1333267343
Short name T264
Test name
Test status
Simulation time 136833849171 ps
CPU time 140.12 seconds
Started Jul 10 06:25:53 PM PDT 24
Finished Jul 10 06:28:14 PM PDT 24
Peak memory 191308 kb
Host smart-4fee40e1-468b-432a-8a47-c51357b2c7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333267343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1333267343
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3272676841
Short name T294
Test name
Test status
Simulation time 507496631307 ps
CPU time 475.99 seconds
Started Jul 10 06:25:51 PM PDT 24
Finished Jul 10 06:33:48 PM PDT 24
Peak memory 183128 kb
Host smart-443d4d06-225e-46e7-863d-2097fbf37311
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272676841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3272676841
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_random.4063544255
Short name T204
Test name
Test status
Simulation time 551154217456 ps
CPU time 291.93 seconds
Started Jul 10 06:25:55 PM PDT 24
Finished Jul 10 06:30:48 PM PDT 24
Peak memory 183152 kb
Host smart-faf6ea2f-6bb5-4a71-a833-57dda78e6315
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063544255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.4063544255
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3069036076
Short name T27
Test name
Test status
Simulation time 1172525960013 ps
CPU time 189.72 seconds
Started Jul 10 06:25:49 PM PDT 24
Finished Jul 10 06:29:00 PM PDT 24
Peak memory 183120 kb
Host smart-5db3aba8-b930-4924-a51d-06a008e480f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069036076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3069036076
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all_with_rand_reset.917109006
Short name T37
Test name
Test status
Simulation time 39823357244 ps
CPU time 234.41 seconds
Started Jul 10 06:25:51 PM PDT 24
Finished Jul 10 06:29:46 PM PDT 24
Peak memory 197848 kb
Host smart-b44e92b8-0b6a-4d32-ae12-e9f28bb5b072
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917109006 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all_with_rand_reset.917109006
Directory /workspace/24.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.94724623
Short name T173
Test name
Test status
Simulation time 187108492351 ps
CPU time 188.58 seconds
Started Jul 10 06:25:54 PM PDT 24
Finished Jul 10 06:29:03 PM PDT 24
Peak memory 183132 kb
Host smart-fbdfe33a-f796-40a1-92bf-b30e37761c69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94724623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.rv_timer_cfg_update_on_fly.94724623
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2972730548
Short name T395
Test name
Test status
Simulation time 290284728690 ps
CPU time 166.81 seconds
Started Jul 10 06:25:52 PM PDT 24
Finished Jul 10 06:28:40 PM PDT 24
Peak memory 183120 kb
Host smart-aab5f092-d5fb-4e03-8d92-b83efa4d2ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972730548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2972730548
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3353499589
Short name T355
Test name
Test status
Simulation time 77701087799 ps
CPU time 125.06 seconds
Started Jul 10 06:25:54 PM PDT 24
Finished Jul 10 06:28:00 PM PDT 24
Peak memory 191340 kb
Host smart-224ba4f4-9639-433d-8d07-de1ee911c84a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353499589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3353499589
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2425180712
Short name T365
Test name
Test status
Simulation time 118714613 ps
CPU time 0.63 seconds
Started Jul 10 06:25:51 PM PDT 24
Finished Jul 10 06:25:52 PM PDT 24
Peak memory 182992 kb
Host smart-62a7d5cf-e815-4c29-9e7f-49df96cb1cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425180712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2425180712
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2649652195
Short name T113
Test name
Test status
Simulation time 1606116842658 ps
CPU time 806.22 seconds
Started Jul 10 06:25:48 PM PDT 24
Finished Jul 10 06:39:15 PM PDT 24
Peak memory 183028 kb
Host smart-3a6d9b96-25e2-4760-a727-7ae488f0da23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649652195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2649652195
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1513656137
Short name T409
Test name
Test status
Simulation time 13542063696 ps
CPU time 21.78 seconds
Started Jul 10 06:25:51 PM PDT 24
Finished Jul 10 06:26:14 PM PDT 24
Peak memory 183144 kb
Host smart-9ba5a829-00a0-4665-9d6d-b984dafdaa2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513656137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1513656137
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3729679405
Short name T138
Test name
Test status
Simulation time 64937952733 ps
CPU time 314.23 seconds
Started Jul 10 06:25:50 PM PDT 24
Finished Jul 10 06:31:06 PM PDT 24
Peak memory 195008 kb
Host smart-ba6d55fb-555f-4342-bb12-96d9abdfbe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729679405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3729679405
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2831398402
Short name T8
Test name
Test status
Simulation time 527023520887 ps
CPU time 1785.27 seconds
Started Jul 10 06:26:05 PM PDT 24
Finished Jul 10 06:55:53 PM PDT 24
Peak memory 191512 kb
Host smart-4d49bc06-f734-4c9f-806d-dd2b386d98e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831398402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2831398402
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2466300662
Short name T149
Test name
Test status
Simulation time 108452967648 ps
CPU time 155.8 seconds
Started Jul 10 06:25:59 PM PDT 24
Finished Jul 10 06:28:36 PM PDT 24
Peak memory 183112 kb
Host smart-7f16e611-feaa-4e1f-9847-427b0b1563c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466300662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2466300662
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2600228347
Short name T417
Test name
Test status
Simulation time 97196925109 ps
CPU time 121.56 seconds
Started Jul 10 06:25:55 PM PDT 24
Finished Jul 10 06:27:58 PM PDT 24
Peak memory 183164 kb
Host smart-e3b533b1-79b3-445c-9c1c-e22e3c04bc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600228347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2600228347
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2966638696
Short name T205
Test name
Test status
Simulation time 124857104152 ps
CPU time 217.54 seconds
Started Jul 10 06:25:58 PM PDT 24
Finished Jul 10 06:29:37 PM PDT 24
Peak memory 191340 kb
Host smart-0c588a31-c58d-4453-996f-08b0777e94fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966638696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2966638696
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3116243609
Short name T433
Test name
Test status
Simulation time 266287049 ps
CPU time 0.86 seconds
Started Jul 10 06:25:55 PM PDT 24
Finished Jul 10 06:25:57 PM PDT 24
Peak memory 183028 kb
Host smart-50ba380e-7ab6-49a5-88cb-3b2b4ef902f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116243609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3116243609
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.4282759832
Short name T401
Test name
Test status
Simulation time 17821926655 ps
CPU time 21.27 seconds
Started Jul 10 06:25:56 PM PDT 24
Finished Jul 10 06:26:18 PM PDT 24
Peak memory 183136 kb
Host smart-7d166b0a-1f1c-44c9-9894-c44f77ceafcc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282759832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.4282759832
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.466453227
Short name T451
Test name
Test status
Simulation time 283602778349 ps
CPU time 116.08 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:28:03 PM PDT 24
Peak memory 183152 kb
Host smart-461a9a70-1f2a-4a37-aa43-2b07751fc7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466453227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.466453227
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.595337080
Short name T21
Test name
Test status
Simulation time 336523525149 ps
CPU time 274.73 seconds
Started Jul 10 06:25:59 PM PDT 24
Finished Jul 10 06:30:35 PM PDT 24
Peak memory 193740 kb
Host smart-f623ee93-3234-4855-9e1e-3508affd0d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595337080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.595337080
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1129342439
Short name T261
Test name
Test status
Simulation time 70512400208 ps
CPU time 68.62 seconds
Started Jul 10 06:25:57 PM PDT 24
Finished Jul 10 06:27:07 PM PDT 24
Peak memory 183148 kb
Host smart-07a74a84-0f59-4acb-9195-916e89c05df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129342439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1129342439
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1572147202
Short name T259
Test name
Test status
Simulation time 113183984782 ps
CPU time 192.1 seconds
Started Jul 10 06:25:56 PM PDT 24
Finished Jul 10 06:29:09 PM PDT 24
Peak memory 183132 kb
Host smart-db9c03ed-1e31-4f55-b57e-d93bf962ed63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572147202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1572147202
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.1326666964
Short name T392
Test name
Test status
Simulation time 237119252486 ps
CPU time 92.2 seconds
Started Jul 10 06:25:59 PM PDT 24
Finished Jul 10 06:27:33 PM PDT 24
Peak memory 183132 kb
Host smart-22bbbf4c-0737-42bf-b07c-97f371cc2b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326666964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.1326666964
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.663553449
Short name T444
Test name
Test status
Simulation time 447915298862 ps
CPU time 308.5 seconds
Started Jul 10 06:26:05 PM PDT 24
Finished Jul 10 06:31:15 PM PDT 24
Peak memory 191520 kb
Host smart-77973585-5ae2-4791-9bc2-801ea1adb4d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663553449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.663553449
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2846608131
Short name T333
Test name
Test status
Simulation time 87625110419 ps
CPU time 439.71 seconds
Started Jul 10 06:26:05 PM PDT 24
Finished Jul 10 06:33:27 PM PDT 24
Peak memory 191524 kb
Host smart-b03f742a-ee63-4932-a5ff-e34d9d724deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846608131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2846608131
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.2383547574
Short name T389
Test name
Test status
Simulation time 295086963517 ps
CPU time 568.99 seconds
Started Jul 10 06:25:57 PM PDT 24
Finished Jul 10 06:35:27 PM PDT 24
Peak memory 191336 kb
Host smart-4403cda9-4e27-4b98-95c2-47043e7db57d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383547574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.2383547574
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.944791219
Short name T108
Test name
Test status
Simulation time 475868246609 ps
CPU time 420.95 seconds
Started Jul 10 06:25:32 PM PDT 24
Finished Jul 10 06:32:37 PM PDT 24
Peak memory 183108 kb
Host smart-11356349-6427-4c9d-aae4-af15bb94af65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944791219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.944791219
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2231363019
Short name T372
Test name
Test status
Simulation time 111974478218 ps
CPU time 162.22 seconds
Started Jul 10 06:25:26 PM PDT 24
Finished Jul 10 06:28:12 PM PDT 24
Peak memory 183152 kb
Host smart-3673c72e-72ed-4470-a764-f2573681ef56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231363019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2231363019
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3248262554
Short name T284
Test name
Test status
Simulation time 283376789036 ps
CPU time 1152.59 seconds
Started Jul 10 06:25:32 PM PDT 24
Finished Jul 10 06:44:49 PM PDT 24
Peak memory 191316 kb
Host smart-49986906-faee-40e7-b626-aca2e96d7f56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248262554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3248262554
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1593336389
Short name T199
Test name
Test status
Simulation time 508288064951 ps
CPU time 236.55 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:29:34 PM PDT 24
Peak memory 191364 kb
Host smart-642bd890-40ac-4433-94f1-cb47431df04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593336389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1593336389
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2321362316
Short name T17
Test name
Test status
Simulation time 76077942 ps
CPU time 0.73 seconds
Started Jul 10 06:25:31 PM PDT 24
Finished Jul 10 06:25:36 PM PDT 24
Peak memory 213380 kb
Host smart-72edaad4-2f45-4d23-a5e6-80df53442f57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321362316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2321362316
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2077541513
Short name T135
Test name
Test status
Simulation time 195985661828 ps
CPU time 97.56 seconds
Started Jul 10 06:26:01 PM PDT 24
Finished Jul 10 06:27:39 PM PDT 24
Peak memory 183132 kb
Host smart-add016fd-0446-42b8-a1bf-381a723b42f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077541513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2077541513
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1251420455
Short name T443
Test name
Test status
Simulation time 197974873279 ps
CPU time 76.07 seconds
Started Jul 10 06:25:56 PM PDT 24
Finished Jul 10 06:27:13 PM PDT 24
Peak memory 191540 kb
Host smart-a88dce63-9722-4908-afc3-dd3417d27550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251420455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1251420455
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1759649583
Short name T361
Test name
Test status
Simulation time 307134874753 ps
CPU time 233.3 seconds
Started Jul 10 06:26:00 PM PDT 24
Finished Jul 10 06:29:55 PM PDT 24
Peak memory 183136 kb
Host smart-db7c16e6-d2d1-4253-8350-eb5f4c317351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759649583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1759649583
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3476918003
Short name T140
Test name
Test status
Simulation time 25452427738 ps
CPU time 7.77 seconds
Started Jul 10 06:26:05 PM PDT 24
Finished Jul 10 06:26:15 PM PDT 24
Peak memory 183312 kb
Host smart-eaaca342-242d-4a02-9588-ed81d142cfe8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476918003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3476918003
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3689569893
Short name T377
Test name
Test status
Simulation time 362880395822 ps
CPU time 147.35 seconds
Started Jul 10 06:26:03 PM PDT 24
Finished Jul 10 06:28:32 PM PDT 24
Peak memory 183148 kb
Host smart-8fbba3e1-657a-4989-9024-43fea3b1ae9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689569893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3689569893
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3157376299
Short name T191
Test name
Test status
Simulation time 118046068635 ps
CPU time 179.44 seconds
Started Jul 10 06:25:59 PM PDT 24
Finished Jul 10 06:29:00 PM PDT 24
Peak memory 194768 kb
Host smart-57b8260d-f141-4bae-ac32-0f3e14f4abed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157376299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3157376299
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.722614783
Short name T203
Test name
Test status
Simulation time 49853375812 ps
CPU time 70.02 seconds
Started Jul 10 06:26:00 PM PDT 24
Finished Jul 10 06:27:11 PM PDT 24
Peak memory 191356 kb
Host smart-ab85a413-5841-4947-afeb-c611bc3ecf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722614783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.722614783
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.688643134
Short name T147
Test name
Test status
Simulation time 1981068156280 ps
CPU time 1690.99 seconds
Started Jul 10 06:25:54 PM PDT 24
Finished Jul 10 06:54:07 PM PDT 24
Peak memory 191228 kb
Host smart-bb1f3645-6392-4dcc-850f-3627a2c69ef2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688643134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
688643134
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2650783914
Short name T195
Test name
Test status
Simulation time 1805521266275 ps
CPU time 890.97 seconds
Started Jul 10 06:26:00 PM PDT 24
Finished Jul 10 06:40:52 PM PDT 24
Peak memory 183144 kb
Host smart-fd762ce9-84a5-47a5-ae95-cf920f78a5c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650783914 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2650783914
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.4286427011
Short name T369
Test name
Test status
Simulation time 364744205814 ps
CPU time 137.14 seconds
Started Jul 10 06:26:02 PM PDT 24
Finished Jul 10 06:28:21 PM PDT 24
Peak memory 183148 kb
Host smart-2947e929-0be5-4050-8541-fdb322aa12f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286427011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.4286427011
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.1715698587
Short name T296
Test name
Test status
Simulation time 257381083805 ps
CPU time 218.2 seconds
Started Jul 10 06:26:02 PM PDT 24
Finished Jul 10 06:29:42 PM PDT 24
Peak memory 193556 kb
Host smart-20bbe00d-2f1c-4990-859b-a323d4bc879f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715698587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1715698587
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.783146436
Short name T406
Test name
Test status
Simulation time 1120484344 ps
CPU time 2.27 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:26:09 PM PDT 24
Peak memory 183000 kb
Host smart-75868483-fa5d-43bf-a4a4-a49d33ed4d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783146436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.783146436
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3368543934
Short name T393
Test name
Test status
Simulation time 118654122 ps
CPU time 0.57 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:26:06 PM PDT 24
Peak memory 183004 kb
Host smart-1b9b9278-ee76-4366-9b66-aa88af5c0a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368543934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3368543934
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.528975000
Short name T400
Test name
Test status
Simulation time 119342968222 ps
CPU time 155.09 seconds
Started Jul 10 06:26:02 PM PDT 24
Finished Jul 10 06:28:38 PM PDT 24
Peak memory 183152 kb
Host smart-41366085-f9ae-4a53-8ee9-74d5d0b9db10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528975000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.528975000
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1820507739
Short name T279
Test name
Test status
Simulation time 170082195701 ps
CPU time 122.16 seconds
Started Jul 10 06:26:02 PM PDT 24
Finished Jul 10 06:28:06 PM PDT 24
Peak memory 191384 kb
Host smart-7bba7b15-b752-417a-95df-a7221a0b976d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820507739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1820507739
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2116650899
Short name T243
Test name
Test status
Simulation time 1861150457747 ps
CPU time 847.12 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:40:13 PM PDT 24
Peak memory 195052 kb
Host smart-17e42446-a31a-4a06-9879-adc8e54b60f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116650899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2116650899
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.917311038
Short name T334
Test name
Test status
Simulation time 137692998012 ps
CPU time 238.18 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:30:05 PM PDT 24
Peak memory 183112 kb
Host smart-97faf67b-f2d7-49d5-b073-c0dabb59b0ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917311038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.rv_timer_cfg_update_on_fly.917311038
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1436995187
Short name T415
Test name
Test status
Simulation time 105032516260 ps
CPU time 140.51 seconds
Started Jul 10 06:26:02 PM PDT 24
Finished Jul 10 06:28:24 PM PDT 24
Peak memory 183156 kb
Host smart-a2de0034-4202-4086-826c-82ce84be5760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436995187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1436995187
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3663500029
Short name T130
Test name
Test status
Simulation time 387077283170 ps
CPU time 109.51 seconds
Started Jul 10 06:26:03 PM PDT 24
Finished Jul 10 06:27:55 PM PDT 24
Peak memory 191332 kb
Host smart-6f0194da-0416-4c69-bf0e-376f4e02bb7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663500029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3663500029
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2558833267
Short name T453
Test name
Test status
Simulation time 372318053 ps
CPU time 0.69 seconds
Started Jul 10 06:26:02 PM PDT 24
Finished Jul 10 06:26:04 PM PDT 24
Peak memory 183020 kb
Host smart-7e142ecd-e445-4e2b-a637-f79d7c8d4469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558833267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2558833267
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.3940851330
Short name T131
Test name
Test status
Simulation time 47810628536 ps
CPU time 19.79 seconds
Started Jul 10 06:26:05 PM PDT 24
Finished Jul 10 06:26:27 PM PDT 24
Peak memory 183132 kb
Host smart-29ce272f-1397-4086-8015-874ee43d6cdf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940851330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.3940851330
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2946731094
Short name T435
Test name
Test status
Simulation time 272120795257 ps
CPU time 212.95 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:29:40 PM PDT 24
Peak memory 183176 kb
Host smart-3f8aa433-6405-4d04-9fc5-94301f200e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946731094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2946731094
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2023196443
Short name T222
Test name
Test status
Simulation time 205738358597 ps
CPU time 75.1 seconds
Started Jul 10 06:26:03 PM PDT 24
Finished Jul 10 06:27:21 PM PDT 24
Peak memory 191360 kb
Host smart-e5547d9f-dc8b-4edd-97ed-05a4c5755dce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023196443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2023196443
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.2095679527
Short name T340
Test name
Test status
Simulation time 102782609723 ps
CPU time 69.18 seconds
Started Jul 10 06:26:01 PM PDT 24
Finished Jul 10 06:27:12 PM PDT 24
Peak memory 191360 kb
Host smart-940303e4-d3c9-40fc-a3ac-7eb160efdbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095679527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.2095679527
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.490541610
Short name T33
Test name
Test status
Simulation time 10847298774 ps
CPU time 73.24 seconds
Started Jul 10 06:26:06 PM PDT 24
Finished Jul 10 06:27:21 PM PDT 24
Peak memory 198020 kb
Host smart-3689753f-415b-4894-8b36-48c77f71ff39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490541610 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.490541610
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1680646478
Short name T318
Test name
Test status
Simulation time 11117035100 ps
CPU time 17.55 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:26:23 PM PDT 24
Peak memory 183128 kb
Host smart-11a10111-b970-4e4d-bba4-c136dae3b494
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680646478 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1680646478
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.175412391
Short name T438
Test name
Test status
Simulation time 412943578758 ps
CPU time 110.26 seconds
Started Jul 10 06:26:03 PM PDT 24
Finished Jul 10 06:27:56 PM PDT 24
Peak memory 183144 kb
Host smart-961e5d97-7042-44b4-8ada-069822f6b9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175412391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.175412391
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.2793422419
Short name T331
Test name
Test status
Simulation time 63986360974 ps
CPU time 486.53 seconds
Started Jul 10 06:26:02 PM PDT 24
Finished Jul 10 06:34:11 PM PDT 24
Peak memory 193600 kb
Host smart-83f31943-1789-49b1-a1d5-5f598a3e5a26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793422419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2793422419
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2488914880
Short name T449
Test name
Test status
Simulation time 65930054481 ps
CPU time 104.89 seconds
Started Jul 10 06:26:03 PM PDT 24
Finished Jul 10 06:27:50 PM PDT 24
Peak memory 183104 kb
Host smart-25a57710-257a-446c-8d36-f2e771f67cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488914880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2488914880
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.949911321
Short name T176
Test name
Test status
Simulation time 137529651693 ps
CPU time 1677.96 seconds
Started Jul 10 06:26:03 PM PDT 24
Finished Jul 10 06:54:04 PM PDT 24
Peak memory 191336 kb
Host smart-a13b2be0-73fb-4e94-a394-ffa5735bddaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949911321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
949911321
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.2759017491
Short name T163
Test name
Test status
Simulation time 121164395808 ps
CPU time 67.16 seconds
Started Jul 10 06:26:05 PM PDT 24
Finished Jul 10 06:27:15 PM PDT 24
Peak memory 183132 kb
Host smart-afd01057-223e-4bc6-8c8f-837b7d13125c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759017491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.2759017491
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1091300750
Short name T383
Test name
Test status
Simulation time 191774614310 ps
CPU time 136.72 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:28:23 PM PDT 24
Peak memory 183152 kb
Host smart-f94cf5b7-8d7e-4e0f-8cd1-46f426004c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091300750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1091300750
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2878243016
Short name T196
Test name
Test status
Simulation time 75636245774 ps
CPU time 137.97 seconds
Started Jul 10 06:26:05 PM PDT 24
Finished Jul 10 06:28:25 PM PDT 24
Peak memory 191332 kb
Host smart-3c6d11be-25fb-41bf-810f-a5ffd5952c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878243016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2878243016
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3069626351
Short name T385
Test name
Test status
Simulation time 321983340 ps
CPU time 0.99 seconds
Started Jul 10 06:26:01 PM PDT 24
Finished Jul 10 06:26:03 PM PDT 24
Peak memory 183000 kb
Host smart-f5a82cb2-7c30-46bb-b0b0-218f6ae99c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069626351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3069626351
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.240873068
Short name T13
Test name
Test status
Simulation time 9053512246 ps
CPU time 89.13 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:27:36 PM PDT 24
Peak memory 197764 kb
Host smart-df615058-fd49-4410-8a7d-7f1edc81d4f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240873068 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.240873068
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3981338893
Short name T120
Test name
Test status
Simulation time 1599634187586 ps
CPU time 902.5 seconds
Started Jul 10 06:26:01 PM PDT 24
Finished Jul 10 06:41:05 PM PDT 24
Peak memory 183108 kb
Host smart-aa830480-e833-4d8c-9a8f-1f2435c96e02
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981338893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3981338893
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.3722156089
Short name T378
Test name
Test status
Simulation time 448247682298 ps
CPU time 164.61 seconds
Started Jul 10 06:26:03 PM PDT 24
Finished Jul 10 06:28:50 PM PDT 24
Peak memory 183140 kb
Host smart-c56df3ba-4063-45a1-9866-031ab402ced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722156089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.3722156089
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3162367859
Short name T329
Test name
Test status
Simulation time 17017601679 ps
CPU time 43.11 seconds
Started Jul 10 06:26:04 PM PDT 24
Finished Jul 10 06:26:49 PM PDT 24
Peak memory 191332 kb
Host smart-167ee1bf-bc58-4dcf-bc67-9e173929c44a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162367859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3162367859
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.823293258
Short name T330
Test name
Test status
Simulation time 164889446074 ps
CPU time 343.65 seconds
Started Jul 10 06:26:03 PM PDT 24
Finished Jul 10 06:31:49 PM PDT 24
Peak memory 191348 kb
Host smart-6798600f-ce81-4788-ac3e-4be8a243cce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823293258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.823293258
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.152815807
Short name T220
Test name
Test status
Simulation time 322295145359 ps
CPU time 383.81 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:32:36 PM PDT 24
Peak memory 191352 kb
Host smart-198934e3-8b0c-44eb-82b5-8f03b6c83841
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152815807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
152815807
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3784440713
Short name T448
Test name
Test status
Simulation time 360333375877 ps
CPU time 301.34 seconds
Started Jul 10 06:26:18 PM PDT 24
Finished Jul 10 06:31:23 PM PDT 24
Peak memory 183128 kb
Host smart-50b188e8-4ff8-4d5b-bd15-2730b36453cd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784440713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3784440713
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1512187930
Short name T364
Test name
Test status
Simulation time 118113101204 ps
CPU time 169.68 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:29:02 PM PDT 24
Peak memory 183164 kb
Host smart-48a3a016-c5f8-49a9-a301-b080b85d6c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512187930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1512187930
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.2611806990
Short name T269
Test name
Test status
Simulation time 175122121560 ps
CPU time 92.71 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:27:45 PM PDT 24
Peak memory 183152 kb
Host smart-7026d1b3-af9a-4389-b25e-d6f22e538277
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611806990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.2611806990
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2360070080
Short name T418
Test name
Test status
Simulation time 61024262 ps
CPU time 0.52 seconds
Started Jul 10 06:26:12 PM PDT 24
Finished Jul 10 06:26:16 PM PDT 24
Peak memory 183004 kb
Host smart-a88ce434-1987-4bea-bda3-c0fc6105483e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360070080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2360070080
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1869535094
Short name T67
Test name
Test status
Simulation time 831937135264 ps
CPU time 893.33 seconds
Started Jul 10 06:26:11 PM PDT 24
Finished Jul 10 06:41:08 PM PDT 24
Peak memory 191336 kb
Host smart-8e71513a-b2bc-40e4-a81d-c14263160598
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869535094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1869535094
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2497784844
Short name T215
Test name
Test status
Simulation time 2679289053 ps
CPU time 4.37 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:25:45 PM PDT 24
Peak memory 183140 kb
Host smart-1ce6ebc9-5f12-43f0-aab2-1e8c15f5115c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497784844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2497784844
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2282884490
Short name T375
Test name
Test status
Simulation time 41259147576 ps
CPU time 15.57 seconds
Started Jul 10 06:25:35 PM PDT 24
Finished Jul 10 06:25:53 PM PDT 24
Peak memory 183128 kb
Host smart-9eaca86b-7e06-45cf-ae4e-11d159d8b701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282884490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2282884490
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.441036391
Short name T19
Test name
Test status
Simulation time 364204049216 ps
CPU time 251.27 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:29:49 PM PDT 24
Peak memory 191288 kb
Host smart-1f142c1a-6f52-4fea-85cb-0978c8d8ee35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441036391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.441036391
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.3132391780
Short name T4
Test name
Test status
Simulation time 124172349 ps
CPU time 0.59 seconds
Started Jul 10 06:25:38 PM PDT 24
Finished Jul 10 06:25:41 PM PDT 24
Peak memory 183020 kb
Host smart-f69047f3-8043-4836-b85b-0935f60b33cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132391780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.3132391780
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.4267889733
Short name T16
Test name
Test status
Simulation time 229475842 ps
CPU time 0.82 seconds
Started Jul 10 06:25:40 PM PDT 24
Finished Jul 10 06:25:43 PM PDT 24
Peak memory 213596 kb
Host smart-e13b9376-394d-4b07-a3df-8e23f83db120
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267889733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.4267889733
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3997748771
Short name T65
Test name
Test status
Simulation time 40124095 ps
CPU time 0.64 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:25:38 PM PDT 24
Peak memory 183020 kb
Host smart-eda024fc-85c5-47f9-b996-a900b6c487bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997748771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3997748771
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.4016220923
Short name T179
Test name
Test status
Simulation time 192154243845 ps
CPU time 96.87 seconds
Started Jul 10 06:26:11 PM PDT 24
Finished Jul 10 06:27:52 PM PDT 24
Peak memory 183104 kb
Host smart-a707cfdb-ef82-4efd-8e40-4442cbc417fe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016220923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.4016220923
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2847968285
Short name T370
Test name
Test status
Simulation time 91732226271 ps
CPU time 131.41 seconds
Started Jul 10 06:26:11 PM PDT 24
Finished Jul 10 06:28:26 PM PDT 24
Peak memory 183176 kb
Host smart-398172c6-59a2-42de-92e8-30474cb81435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847968285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2847968285
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.268622412
Short name T20
Test name
Test status
Simulation time 28661362099 ps
CPU time 32.02 seconds
Started Jul 10 06:26:13 PM PDT 24
Finished Jul 10 06:26:48 PM PDT 24
Peak memory 183168 kb
Host smart-724fdcc4-eed3-488a-88eb-2338acd0d86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268622412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.268622412
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.1132882867
Short name T348
Test name
Test status
Simulation time 397876738977 ps
CPU time 625.93 seconds
Started Jul 10 06:26:09 PM PDT 24
Finished Jul 10 06:36:36 PM PDT 24
Peak memory 195208 kb
Host smart-6cd0039e-02c1-43e7-a584-06d7541bea8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132882867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.1132882867
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.3766241726
Short name T129
Test name
Test status
Simulation time 73863202744 ps
CPU time 110.32 seconds
Started Jul 10 06:26:13 PM PDT 24
Finished Jul 10 06:28:07 PM PDT 24
Peak memory 183132 kb
Host smart-8be8b030-e6b9-4ce4-b096-c81237a2fc6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766241726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.3766241726
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2034464988
Short name T391
Test name
Test status
Simulation time 56283885776 ps
CPU time 77.33 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:27:30 PM PDT 24
Peak memory 183164 kb
Host smart-23464001-8845-41ea-877d-edfe38473b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034464988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2034464988
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.1785097963
Short name T257
Test name
Test status
Simulation time 114741478645 ps
CPU time 1933.67 seconds
Started Jul 10 06:26:07 PM PDT 24
Finished Jul 10 06:58:23 PM PDT 24
Peak memory 191348 kb
Host smart-04e355c9-eaec-4939-823e-218bb308299e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785097963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.1785097963
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2546623681
Short name T362
Test name
Test status
Simulation time 2951641933 ps
CPU time 2.34 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:26:15 PM PDT 24
Peak memory 183160 kb
Host smart-5fb0a185-8cc0-4649-ba5c-3a7bb082072a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546623681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2546623681
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.971601554
Short name T235
Test name
Test status
Simulation time 1042132733167 ps
CPU time 529.58 seconds
Started Jul 10 06:26:06 PM PDT 24
Finished Jul 10 06:34:58 PM PDT 24
Peak memory 183116 kb
Host smart-60d7505c-f59e-4ee0-99c2-72ccbdec9ef2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971601554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.971601554
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.1005532903
Short name T366
Test name
Test status
Simulation time 44193314784 ps
CPU time 63.9 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:27:16 PM PDT 24
Peak memory 183152 kb
Host smart-6fe87003-742a-4e87-a7ba-483098eab5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005532903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.1005532903
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3721408560
Short name T282
Test name
Test status
Simulation time 114203751972 ps
CPU time 213.06 seconds
Started Jul 10 06:26:09 PM PDT 24
Finished Jul 10 06:29:44 PM PDT 24
Peak memory 191340 kb
Host smart-6b4bee9b-a036-42ff-9757-3b179fb3ff98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721408560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3721408560
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2136223545
Short name T327
Test name
Test status
Simulation time 61189570975 ps
CPU time 32.98 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:26:46 PM PDT 24
Peak memory 191364 kb
Host smart-a0bc4046-6910-40c8-b746-bbfd78fcaf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136223545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2136223545
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1559443932
Short name T430
Test name
Test status
Simulation time 72650143326 ps
CPU time 103.08 seconds
Started Jul 10 06:26:11 PM PDT 24
Finished Jul 10 06:27:57 PM PDT 24
Peak memory 183132 kb
Host smart-3171b403-2152-40f2-a0ee-be3034f94ebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559443932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1559443932
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.403550762
Short name T38
Test name
Test status
Simulation time 91674586345 ps
CPU time 736.92 seconds
Started Jul 10 06:26:11 PM PDT 24
Finished Jul 10 06:38:31 PM PDT 24
Peak memory 206048 kb
Host smart-c0a88757-3bf8-4084-954f-dcfd72eb0fc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403550762 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.403550762
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2054872374
Short name T40
Test name
Test status
Simulation time 177596204720 ps
CPU time 267.8 seconds
Started Jul 10 06:26:19 PM PDT 24
Finished Jul 10 06:30:49 PM PDT 24
Peak memory 183128 kb
Host smart-7659968f-93ff-41e3-b23b-27e4200d10f9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054872374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2054872374
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.1329085601
Short name T447
Test name
Test status
Simulation time 72754767465 ps
CPU time 13.63 seconds
Started Jul 10 06:26:08 PM PDT 24
Finished Jul 10 06:26:23 PM PDT 24
Peak memory 183048 kb
Host smart-872e6a85-15e0-4dfb-8345-c867e7dc1e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329085601 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.1329085601
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3863344692
Short name T285
Test name
Test status
Simulation time 62995054938 ps
CPU time 65.94 seconds
Started Jul 10 06:26:19 PM PDT 24
Finished Jul 10 06:27:28 PM PDT 24
Peak memory 191352 kb
Host smart-dcb5b4ac-87de-41f5-8c8d-27f6f05ba53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863344692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3863344692
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1257691927
Short name T342
Test name
Test status
Simulation time 340382063490 ps
CPU time 523.52 seconds
Started Jul 10 06:26:11 PM PDT 24
Finished Jul 10 06:34:58 PM PDT 24
Peak memory 183104 kb
Host smart-ae8da899-222c-4bac-953e-328bad5fcd81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257691927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1257691927
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.398918124
Short name T358
Test name
Test status
Simulation time 424449452086 ps
CPU time 72.77 seconds
Started Jul 10 06:26:13 PM PDT 24
Finished Jul 10 06:27:29 PM PDT 24
Peak memory 183152 kb
Host smart-d764ec70-326a-475d-85b2-6524d5f246d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398918124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.398918124
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1706333669
Short name T254
Test name
Test status
Simulation time 399631125510 ps
CPU time 201.8 seconds
Started Jul 10 06:26:11 PM PDT 24
Finished Jul 10 06:29:36 PM PDT 24
Peak memory 191352 kb
Host smart-30891afe-d901-4861-8d75-347baaa8df57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706333669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1706333669
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.1074110228
Short name T397
Test name
Test status
Simulation time 9594448211 ps
CPU time 17.87 seconds
Started Jul 10 06:26:09 PM PDT 24
Finished Jul 10 06:26:28 PM PDT 24
Peak memory 191372 kb
Host smart-864c6d85-5a2d-434e-bdd9-916549566f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074110228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.1074110228
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.1372527649
Short name T125
Test name
Test status
Simulation time 3788703181303 ps
CPU time 1727.63 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:55:00 PM PDT 24
Peak memory 191280 kb
Host smart-ca52a53a-a19a-481c-9187-746b7ca08757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372527649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1372527649
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.633146594
Short name T314
Test name
Test status
Simulation time 417278192289 ps
CPU time 682.7 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:37:36 PM PDT 24
Peak memory 183172 kb
Host smart-e0642803-cb36-4b34-8e3f-2b3a5c0d6c20
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633146594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.633146594
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1706212645
Short name T410
Test name
Test status
Simulation time 176034725304 ps
CPU time 266.38 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:30:40 PM PDT 24
Peak memory 183100 kb
Host smart-5846c455-5030-4f22-951d-f514f9c1fb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706212645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1706212645
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.3561141612
Short name T302
Test name
Test status
Simulation time 40753984807 ps
CPU time 19.4 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:26:31 PM PDT 24
Peak memory 183188 kb
Host smart-55cd2082-31f5-45f7-a807-636c1057603d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561141612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.3561141612
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2679067845
Short name T394
Test name
Test status
Simulation time 21189219 ps
CPU time 0.56 seconds
Started Jul 10 06:26:11 PM PDT 24
Finished Jul 10 06:26:15 PM PDT 24
Peak memory 182984 kb
Host smart-77fe57cb-51ee-4829-b629-56ab5ec44d7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679067845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2679067845
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3684482456
Short name T11
Test name
Test status
Simulation time 727384894002 ps
CPU time 335.99 seconds
Started Jul 10 06:26:13 PM PDT 24
Finished Jul 10 06:31:52 PM PDT 24
Peak memory 183156 kb
Host smart-9985928b-2c25-4f1c-bc4a-3d2c7221fe7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684482456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3684482456
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2208071215
Short name T52
Test name
Test status
Simulation time 611815128519 ps
CPU time 977.62 seconds
Started Jul 10 06:26:12 PM PDT 24
Finished Jul 10 06:42:33 PM PDT 24
Peak memory 191352 kb
Host smart-62f90b89-8b5d-4727-ab40-34b65ff94095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208071215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2208071215
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3530989597
Short name T156
Test name
Test status
Simulation time 408279004383 ps
CPU time 795.3 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:39:28 PM PDT 24
Peak memory 191356 kb
Host smart-a2d05dc0-f6b9-4ebb-9366-53ed3413107a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530989597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3530989597
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3728328251
Short name T178
Test name
Test status
Simulation time 44266649370 ps
CPU time 24.23 seconds
Started Jul 10 06:26:09 PM PDT 24
Finished Jul 10 06:26:35 PM PDT 24
Peak memory 183132 kb
Host smart-967235f4-9e5e-4741-8875-11efdc8638b3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728328251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3728328251
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.33856814
Short name T414
Test name
Test status
Simulation time 807865309371 ps
CPU time 179.98 seconds
Started Jul 10 06:26:08 PM PDT 24
Finished Jul 10 06:29:10 PM PDT 24
Peak memory 183136 kb
Host smart-bf4757bc-ada2-47e9-b75f-0c001354ece3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33856814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.33856814
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.4128296313
Short name T157
Test name
Test status
Simulation time 229115655022 ps
CPU time 1846.56 seconds
Started Jul 10 06:26:10 PM PDT 24
Finished Jul 10 06:56:58 PM PDT 24
Peak memory 191336 kb
Host smart-e39ff693-02c2-4399-84ad-a5c44e54f2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128296313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4128296313
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2112713867
Short name T142
Test name
Test status
Simulation time 66577568772 ps
CPU time 64.09 seconds
Started Jul 10 06:26:16 PM PDT 24
Finished Jul 10 06:27:24 PM PDT 24
Peak memory 191352 kb
Host smart-ec67ba1b-5663-4c8b-bc80-e5cdd57823cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112713867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2112713867
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.366692139
Short name T441
Test name
Test status
Simulation time 571642835089 ps
CPU time 235.86 seconds
Started Jul 10 06:26:15 PM PDT 24
Finished Jul 10 06:30:14 PM PDT 24
Peak memory 183136 kb
Host smart-f3ef8c83-0363-4fa0-b239-bd5575bb1514
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366692139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.366692139
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.565161270
Short name T382
Test name
Test status
Simulation time 53706913392 ps
CPU time 79.89 seconds
Started Jul 10 06:26:16 PM PDT 24
Finished Jul 10 06:27:39 PM PDT 24
Peak memory 183152 kb
Host smart-184153d4-dd27-4521-84b7-80bca9e1f3e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565161270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.565161270
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3931881553
Short name T407
Test name
Test status
Simulation time 6867809728 ps
CPU time 10.5 seconds
Started Jul 10 06:26:14 PM PDT 24
Finished Jul 10 06:26:28 PM PDT 24
Peak memory 191352 kb
Host smart-ba40c354-41ae-45f1-8bdf-b1000e09e98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931881553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3931881553
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.1005777932
Short name T139
Test name
Test status
Simulation time 34564674688 ps
CPU time 19.67 seconds
Started Jul 10 06:26:12 PM PDT 24
Finished Jul 10 06:26:36 PM PDT 24
Peak memory 183140 kb
Host smart-88bd73b8-3e9b-4869-bfa1-7e7338bcbfbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005777932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.1005777932
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.843531402
Short name T371
Test name
Test status
Simulation time 45592772503 ps
CPU time 50.32 seconds
Started Jul 10 06:26:12 PM PDT 24
Finished Jul 10 06:27:06 PM PDT 24
Peak memory 183124 kb
Host smart-be910bb1-3888-40ca-8a77-ceb380654128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843531402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.843531402
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2617450047
Short name T425
Test name
Test status
Simulation time 177075311046 ps
CPU time 84.71 seconds
Started Jul 10 06:26:12 PM PDT 24
Finished Jul 10 06:27:41 PM PDT 24
Peak memory 191388 kb
Host smart-6a25fbd3-f1fd-401d-86a1-7d0916d34ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617450047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2617450047
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3987856328
Short name T350
Test name
Test status
Simulation time 12702255513 ps
CPU time 18.61 seconds
Started Jul 10 06:26:17 PM PDT 24
Finished Jul 10 06:26:39 PM PDT 24
Peak memory 191360 kb
Host smart-78a09465-652f-4edf-9de2-fed3c4e18095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987856328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3987856328
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.598776429
Short name T22
Test name
Test status
Simulation time 1666467031231 ps
CPU time 904.54 seconds
Started Jul 10 06:25:32 PM PDT 24
Finished Jul 10 06:40:41 PM PDT 24
Peak memory 183120 kb
Host smart-7881615c-9780-4a93-90d0-7a69f382d5af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598776429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.rv_timer_cfg_update_on_fly.598776429
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3289633330
Short name T360
Test name
Test status
Simulation time 137239829995 ps
CPU time 177.79 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:28:40 PM PDT 24
Peak memory 183152 kb
Host smart-e267154d-d0af-4123-a7a9-792b541be37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289633330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3289633330
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.779512985
Short name T231
Test name
Test status
Simulation time 144107752627 ps
CPU time 76.16 seconds
Started Jul 10 06:25:35 PM PDT 24
Finished Jul 10 06:26:54 PM PDT 24
Peak memory 183140 kb
Host smart-ebf4185d-dcce-4b0c-9e30-61e6998c6b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779512985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.779512985
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2745243645
Short name T54
Test name
Test status
Simulation time 935932791 ps
CPU time 3.21 seconds
Started Jul 10 06:25:40 PM PDT 24
Finished Jul 10 06:25:45 PM PDT 24
Peak memory 191304 kb
Host smart-7fc7d9b1-16e4-4310-894c-a16fe61000b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745243645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2745243645
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.2472265088
Short name T39
Test name
Test status
Simulation time 173794418885 ps
CPU time 865.82 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:40:03 PM PDT 24
Peak memory 205980 kb
Host smart-d2165962-eef7-4c1f-b306-4ed049680f90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472265088 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.2472265088
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1513319362
Short name T180
Test name
Test status
Simulation time 693803518726 ps
CPU time 1827.37 seconds
Started Jul 10 06:26:13 PM PDT 24
Finished Jul 10 06:56:44 PM PDT 24
Peak memory 191360 kb
Host smart-25162098-6cb9-46d3-b003-927fca74cc6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513319362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1513319362
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3915178916
Short name T209
Test name
Test status
Simulation time 134837491456 ps
CPU time 207.85 seconds
Started Jul 10 06:26:16 PM PDT 24
Finished Jul 10 06:29:47 PM PDT 24
Peak memory 191340 kb
Host smart-6a3f67dd-076d-4e04-87a7-fdd3772db3e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915178916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3915178916
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.654132000
Short name T197
Test name
Test status
Simulation time 118559326658 ps
CPU time 519.12 seconds
Started Jul 10 06:26:14 PM PDT 24
Finished Jul 10 06:34:56 PM PDT 24
Peak memory 191328 kb
Host smart-f5b84021-7b8e-4046-8ed0-4631ba6622de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654132000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.654132000
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.185297900
Short name T450
Test name
Test status
Simulation time 374900776935 ps
CPU time 435.35 seconds
Started Jul 10 06:26:16 PM PDT 24
Finished Jul 10 06:33:34 PM PDT 24
Peak memory 191336 kb
Host smart-284fc2d1-eef4-4184-9593-8c38b8787db9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185297900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.185297900
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.3519190137
Short name T55
Test name
Test status
Simulation time 34179631179 ps
CPU time 248.44 seconds
Started Jul 10 06:26:18 PM PDT 24
Finished Jul 10 06:30:29 PM PDT 24
Peak memory 191336 kb
Host smart-01a04ca3-947f-4394-b751-534d7d213f2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519190137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.3519190137
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2359998716
Short name T110
Test name
Test status
Simulation time 91049716463 ps
CPU time 135.53 seconds
Started Jul 10 06:26:18 PM PDT 24
Finished Jul 10 06:28:37 PM PDT 24
Peak memory 191340 kb
Host smart-4fe0bbfd-9e46-42cc-b6c1-4dd218ed11ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359998716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2359998716
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.2905731944
Short name T353
Test name
Test status
Simulation time 32646888987 ps
CPU time 314.37 seconds
Started Jul 10 06:26:14 PM PDT 24
Finished Jul 10 06:31:32 PM PDT 24
Peak memory 183152 kb
Host smart-3968e2e9-6b83-41d5-8ed1-3e049a54e6df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905731944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.2905731944
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1315878622
Short name T190
Test name
Test status
Simulation time 200320692930 ps
CPU time 299.98 seconds
Started Jul 10 06:26:14 PM PDT 24
Finished Jul 10 06:31:17 PM PDT 24
Peak memory 191352 kb
Host smart-9022f585-83f1-4340-8419-fb06f670c49e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315878622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1315878622
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2803834188
Short name T192
Test name
Test status
Simulation time 649413287272 ps
CPU time 695.17 seconds
Started Jul 10 06:26:14 PM PDT 24
Finished Jul 10 06:37:52 PM PDT 24
Peak memory 191376 kb
Host smart-3993b6e0-7396-400a-94ca-3197074624b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803834188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2803834188
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.4194769745
Short name T105
Test name
Test status
Simulation time 287401527003 ps
CPU time 134.88 seconds
Started Jul 10 06:25:33 PM PDT 24
Finished Jul 10 06:27:52 PM PDT 24
Peak memory 183124 kb
Host smart-d7cd9ea5-19ff-4123-b4f7-e576cb1c27a2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194769745 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.4194769745
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.2656805261
Short name T381
Test name
Test status
Simulation time 27989535471 ps
CPU time 12.87 seconds
Started Jul 10 06:25:35 PM PDT 24
Finished Jul 10 06:25:51 PM PDT 24
Peak memory 195264 kb
Host smart-7aedee44-52ac-4f4c-9fc5-60d2d8268637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656805261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.2656805261
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2853329626
Short name T253
Test name
Test status
Simulation time 536873416749 ps
CPU time 1117.05 seconds
Started Jul 10 06:25:33 PM PDT 24
Finished Jul 10 06:44:14 PM PDT 24
Peak memory 191336 kb
Host smart-a3dbf5c1-72a8-46f1-8ca7-6352c9ae2d3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853329626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2853329626
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.3397323680
Short name T134
Test name
Test status
Simulation time 32482740352 ps
CPU time 97.51 seconds
Started Jul 10 06:26:14 PM PDT 24
Finished Jul 10 06:27:55 PM PDT 24
Peak memory 191324 kb
Host smart-3d678451-c210-4511-b15c-0b9eb3c8e75a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397323680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.3397323680
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.2785360105
Short name T161
Test name
Test status
Simulation time 155459055814 ps
CPU time 596.47 seconds
Started Jul 10 06:26:15 PM PDT 24
Finished Jul 10 06:36:15 PM PDT 24
Peak memory 191332 kb
Host smart-2cf759df-2c09-4d11-a1bb-6808297e9af1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785360105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.2785360105
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.451698888
Short name T123
Test name
Test status
Simulation time 58964173666 ps
CPU time 10.52 seconds
Started Jul 10 06:26:16 PM PDT 24
Finished Jul 10 06:26:29 PM PDT 24
Peak memory 191328 kb
Host smart-1821f5be-e1f9-40b9-84c5-32e299e819a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451698888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.451698888
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.235635485
Short name T174
Test name
Test status
Simulation time 77051289731 ps
CPU time 116.62 seconds
Started Jul 10 06:26:19 PM PDT 24
Finished Jul 10 06:28:18 PM PDT 24
Peak memory 191336 kb
Host smart-350f5446-d354-466a-bd99-c7e8adb06814
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235635485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.235635485
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1698263404
Short name T43
Test name
Test status
Simulation time 161063064692 ps
CPU time 177.74 seconds
Started Jul 10 06:26:16 PM PDT 24
Finished Jul 10 06:29:17 PM PDT 24
Peak memory 183152 kb
Host smart-1241e590-f36a-4bc0-a4c5-855697cbe23b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698263404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1698263404
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3406407344
Short name T386
Test name
Test status
Simulation time 91622458891 ps
CPU time 82.78 seconds
Started Jul 10 06:26:16 PM PDT 24
Finished Jul 10 06:27:42 PM PDT 24
Peak memory 191340 kb
Host smart-a34582e0-21a5-4357-8074-2dc03e2bf9ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406407344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3406407344
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3693461786
Short name T423
Test name
Test status
Simulation time 245028124578 ps
CPU time 195.18 seconds
Started Jul 10 06:25:40 PM PDT 24
Finished Jul 10 06:28:57 PM PDT 24
Peak memory 183172 kb
Host smart-520939f8-99cc-45a0-9680-1c6d23093199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693461786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3693461786
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3822227229
Short name T315
Test name
Test status
Simulation time 128104380561 ps
CPU time 141.22 seconds
Started Jul 10 06:25:32 PM PDT 24
Finished Jul 10 06:27:57 PM PDT 24
Peak memory 191328 kb
Host smart-0d195100-a05a-4b6b-9002-02f1c2159c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822227229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3822227229
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.3719711096
Short name T238
Test name
Test status
Simulation time 516556955304 ps
CPU time 237.99 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:29:36 PM PDT 24
Peak memory 191348 kb
Host smart-f99233f6-c04d-4b38-919f-bbc8e23dfc4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719711096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
3719711096
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.3416247000
Short name T132
Test name
Test status
Simulation time 475217040546 ps
CPU time 212.17 seconds
Started Jul 10 06:26:17 PM PDT 24
Finished Jul 10 06:29:52 PM PDT 24
Peak memory 191328 kb
Host smart-5f8059ad-5b87-4b71-a6be-bf6236395d0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416247000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3416247000
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.2369048416
Short name T148
Test name
Test status
Simulation time 108109526642 ps
CPU time 159.26 seconds
Started Jul 10 06:26:16 PM PDT 24
Finished Jul 10 06:28:58 PM PDT 24
Peak memory 191340 kb
Host smart-f6b72e9d-11ce-4d6d-a1ee-7f1e43445be5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369048416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.2369048416
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2288603602
Short name T119
Test name
Test status
Simulation time 121078255716 ps
CPU time 202.94 seconds
Started Jul 10 06:26:21 PM PDT 24
Finished Jul 10 06:29:45 PM PDT 24
Peak memory 191316 kb
Host smart-470cb032-17ed-4d6e-95e5-6cbe952fd7ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288603602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2288603602
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.101075014
Short name T101
Test name
Test status
Simulation time 723989483362 ps
CPU time 443.37 seconds
Started Jul 10 06:26:24 PM PDT 24
Finished Jul 10 06:33:48 PM PDT 24
Peak memory 191328 kb
Host smart-e889382f-7c06-4b8f-b291-35aa5c7cd304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101075014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.101075014
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2669765603
Short name T224
Test name
Test status
Simulation time 29313008767 ps
CPU time 40.31 seconds
Started Jul 10 06:26:19 PM PDT 24
Finished Jul 10 06:27:02 PM PDT 24
Peak memory 183052 kb
Host smart-995aee3b-f835-4636-9807-917dd0429322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669765603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2669765603
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2694772552
Short name T146
Test name
Test status
Simulation time 735363907774 ps
CPU time 168.2 seconds
Started Jul 10 06:26:20 PM PDT 24
Finished Jul 10 06:29:10 PM PDT 24
Peak memory 191344 kb
Host smart-5ee3e110-762f-402e-b921-4f69cb57a19c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694772552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2694772552
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3505209977
Short name T278
Test name
Test status
Simulation time 603470843895 ps
CPU time 298.94 seconds
Started Jul 10 06:26:21 PM PDT 24
Finished Jul 10 06:31:22 PM PDT 24
Peak memory 191332 kb
Host smart-5827ca07-80c1-4628-84e8-8db01f2f047a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505209977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3505209977
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1207824351
Short name T343
Test name
Test status
Simulation time 46915039687 ps
CPU time 71.46 seconds
Started Jul 10 06:26:22 PM PDT 24
Finished Jul 10 06:27:35 PM PDT 24
Peak memory 183144 kb
Host smart-08dd97bb-d376-48cc-9623-a819a154d698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207824351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1207824351
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3401101666
Short name T338
Test name
Test status
Simulation time 378509928794 ps
CPU time 852.86 seconds
Started Jul 10 06:26:20 PM PDT 24
Finished Jul 10 06:40:35 PM PDT 24
Peak memory 191356 kb
Host smart-2b5c34f0-1656-4ebc-bb3f-f597da8d223b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401101666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3401101666
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.164718079
Short name T166
Test name
Test status
Simulation time 419225861081 ps
CPU time 120.61 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:27:42 PM PDT 24
Peak memory 183148 kb
Host smart-7c8931d9-604d-46f1-9516-79111c3f6fc5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164718079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.164718079
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.938669315
Short name T411
Test name
Test status
Simulation time 192820407246 ps
CPU time 263.64 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 183144 kb
Host smart-a1ef3e34-6da2-46c4-8ae2-60f3fac6d12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938669315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.938669315
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1787461140
Short name T240
Test name
Test status
Simulation time 188125743821 ps
CPU time 169.93 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:28:31 PM PDT 24
Peak memory 191348 kb
Host smart-6d5d5b76-8f7e-40c6-a3b4-74dec4de0017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787461140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1787461140
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1003203327
Short name T109
Test name
Test status
Simulation time 87228040291 ps
CPU time 78.39 seconds
Started Jul 10 06:25:40 PM PDT 24
Finished Jul 10 06:27:01 PM PDT 24
Peak memory 190820 kb
Host smart-052c0c64-c9f0-4081-8e3e-e765fd9f2242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003203327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1003203327
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.3201781839
Short name T446
Test name
Test status
Simulation time 23803025453 ps
CPU time 31.37 seconds
Started Jul 10 06:26:22 PM PDT 24
Finished Jul 10 06:26:55 PM PDT 24
Peak memory 183044 kb
Host smart-459e6b59-35c0-4993-9c9f-53fa1aa61581
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201781839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3201781839
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1699850034
Short name T288
Test name
Test status
Simulation time 199579008829 ps
CPU time 635.81 seconds
Started Jul 10 06:26:21 PM PDT 24
Finished Jul 10 06:36:58 PM PDT 24
Peak memory 191340 kb
Host smart-97644e6c-c4ec-47e9-b06e-636dd388573a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699850034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1699850034
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.260812770
Short name T172
Test name
Test status
Simulation time 389630624137 ps
CPU time 417.27 seconds
Started Jul 10 06:26:24 PM PDT 24
Finished Jul 10 06:33:22 PM PDT 24
Peak memory 191320 kb
Host smart-e6d09168-d285-4a36-8725-58c025523149
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260812770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.260812770
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.469483201
Short name T306
Test name
Test status
Simulation time 10198180640 ps
CPU time 180.53 seconds
Started Jul 10 06:26:20 PM PDT 24
Finished Jul 10 06:29:23 PM PDT 24
Peak memory 183144 kb
Host smart-458da398-0c3e-4927-b30b-47107dd403b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469483201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.469483201
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.379417896
Short name T73
Test name
Test status
Simulation time 12874676761 ps
CPU time 21.65 seconds
Started Jul 10 06:26:21 PM PDT 24
Finished Jul 10 06:26:44 PM PDT 24
Peak memory 183192 kb
Host smart-e7f89a8c-63db-412c-a277-238b5814479a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379417896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.379417896
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.4090769923
Short name T214
Test name
Test status
Simulation time 400076955063 ps
CPU time 258.2 seconds
Started Jul 10 06:26:28 PM PDT 24
Finished Jul 10 06:30:47 PM PDT 24
Peak memory 191360 kb
Host smart-a3bd3055-b345-4c48-acf7-8d07603b025a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090769923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.4090769923
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1625216002
Short name T212
Test name
Test status
Simulation time 410833344576 ps
CPU time 191.31 seconds
Started Jul 10 06:26:26 PM PDT 24
Finished Jul 10 06:29:37 PM PDT 24
Peak memory 191332 kb
Host smart-739fa1df-3e91-4d8b-a8ab-2b5a2116ea48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625216002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1625216002
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.4188694647
Short name T332
Test name
Test status
Simulation time 28143904657 ps
CPU time 95.44 seconds
Started Jul 10 06:26:29 PM PDT 24
Finished Jul 10 06:28:05 PM PDT 24
Peak memory 183160 kb
Host smart-9d1c612f-c627-4a79-8e76-74b0bb7d4fab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188694647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.4188694647
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1481889041
Short name T268
Test name
Test status
Simulation time 129612776945 ps
CPU time 207.01 seconds
Started Jul 10 06:26:24 PM PDT 24
Finished Jul 10 06:29:51 PM PDT 24
Peak memory 191260 kb
Host smart-7a2f8a5c-04f5-4722-8a6d-389d45fd0c30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481889041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1481889041
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2732818204
Short name T189
Test name
Test status
Simulation time 523744964453 ps
CPU time 902.2 seconds
Started Jul 10 06:25:36 PM PDT 24
Finished Jul 10 06:40:41 PM PDT 24
Peak memory 183136 kb
Host smart-630e0b43-d70e-4130-8449-417966e584ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732818204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2732818204
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.1719772932
Short name T71
Test name
Test status
Simulation time 435338057795 ps
CPU time 108.46 seconds
Started Jul 10 06:25:37 PM PDT 24
Finished Jul 10 06:27:28 PM PDT 24
Peak memory 183184 kb
Host smart-bd534720-c7e7-4832-a050-8ec31ca5a42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719772932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.1719772932
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3618792358
Short name T181
Test name
Test status
Simulation time 395431635653 ps
CPU time 2211.99 seconds
Started Jul 10 06:25:34 PM PDT 24
Finished Jul 10 07:02:30 PM PDT 24
Peak memory 191344 kb
Host smart-587d63d9-ba54-4639-99df-3173505e16d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618792358 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3618792358
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3347349108
Short name T313
Test name
Test status
Simulation time 50793952833 ps
CPU time 68.05 seconds
Started Jul 10 06:25:36 PM PDT 24
Finished Jul 10 06:26:47 PM PDT 24
Peak memory 183168 kb
Host smart-d17d360d-2a96-4083-b7c1-505127e26b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347349108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3347349108
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1197931586
Short name T380
Test name
Test status
Simulation time 4950884264 ps
CPU time 7.87 seconds
Started Jul 10 06:25:39 PM PDT 24
Finished Jul 10 06:25:49 PM PDT 24
Peak memory 183044 kb
Host smart-9527e690-5b08-499c-b068-fd249cc95f93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197931586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1197931586
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/91.rv_timer_random.1415052726
Short name T316
Test name
Test status
Simulation time 128109307579 ps
CPU time 384.15 seconds
Started Jul 10 06:26:25 PM PDT 24
Finished Jul 10 06:32:50 PM PDT 24
Peak memory 191340 kb
Host smart-31fce4c9-ffde-4f7e-9689-7e59577b0256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415052726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1415052726
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.878847165
Short name T260
Test name
Test status
Simulation time 203907419784 ps
CPU time 92.84 seconds
Started Jul 10 06:26:26 PM PDT 24
Finished Jul 10 06:27:59 PM PDT 24
Peak memory 191336 kb
Host smart-71dff21a-ed94-491a-aaad-97279101d646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878847165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.878847165
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3241686895
Short name T351
Test name
Test status
Simulation time 183842797902 ps
CPU time 809.64 seconds
Started Jul 10 06:26:26 PM PDT 24
Finished Jul 10 06:39:56 PM PDT 24
Peak memory 191340 kb
Host smart-a67ee0a3-7e69-4f53-803f-39a56027da12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241686895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3241686895
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1775574977
Short name T317
Test name
Test status
Simulation time 24476270564 ps
CPU time 41.04 seconds
Started Jul 10 06:26:28 PM PDT 24
Finished Jul 10 06:27:10 PM PDT 24
Peak memory 183160 kb
Host smart-071aa7e7-48d2-498d-8d10-c2787a2c5f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775574977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1775574977
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2704674152
Short name T152
Test name
Test status
Simulation time 193668856189 ps
CPU time 282.5 seconds
Started Jul 10 06:26:24 PM PDT 24
Finished Jul 10 06:31:07 PM PDT 24
Peak memory 191352 kb
Host smart-62562843-98bd-41ad-b2cb-7885d39a073e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704674152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2704674152
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2813059159
Short name T121
Test name
Test status
Simulation time 43160199391 ps
CPU time 70.51 seconds
Started Jul 10 06:26:24 PM PDT 24
Finished Jul 10 06:27:35 PM PDT 24
Peak memory 183148 kb
Host smart-cda92571-1c58-4352-89a9-5150818537e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813059159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2813059159
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2284465781
Short name T218
Test name
Test status
Simulation time 486642206727 ps
CPU time 215.95 seconds
Started Jul 10 06:26:25 PM PDT 24
Finished Jul 10 06:30:01 PM PDT 24
Peak memory 194700 kb
Host smart-27bb93c1-4cf2-4a0f-b10f-205cefa7fe6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284465781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2284465781
Directory /workspace/99.rv_timer_random/latest
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