Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 578
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1276346694 Jul 11 05:26:19 PM PDT 24 Jul 11 05:26:23 PM PDT 24 16396389 ps
T509 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.568136707 Jul 11 05:26:26 PM PDT 24 Jul 11 05:26:31 PM PDT 24 21884950 ps
T510 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3364510181 Jul 11 05:26:23 PM PDT 24 Jul 11 05:26:28 PM PDT 24 23336246 ps
T511 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.660874711 Jul 11 05:26:52 PM PDT 24 Jul 11 05:26:54 PM PDT 24 47143832 ps
T512 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3117886394 Jul 11 05:26:41 PM PDT 24 Jul 11 05:26:44 PM PDT 24 156072255 ps
T513 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1051949036 Jul 11 05:26:45 PM PDT 24 Jul 11 05:26:48 PM PDT 24 91225772 ps
T514 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.380375597 Jul 11 05:26:51 PM PDT 24 Jul 11 05:26:53 PM PDT 24 67451830 ps
T515 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1537782645 Jul 11 05:26:38 PM PDT 24 Jul 11 05:26:43 PM PDT 24 156357163 ps
T516 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2971661355 Jul 11 05:26:48 PM PDT 24 Jul 11 05:26:50 PM PDT 24 24226309 ps
T517 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1716641804 Jul 11 05:26:56 PM PDT 24 Jul 11 05:26:58 PM PDT 24 41656649 ps
T518 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3795111475 Jul 11 05:26:32 PM PDT 24 Jul 11 05:26:37 PM PDT 24 15055248 ps
T519 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.93260196 Jul 11 05:26:50 PM PDT 24 Jul 11 05:26:52 PM PDT 24 28361734 ps
T520 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4153050685 Jul 11 05:26:39 PM PDT 24 Jul 11 05:26:44 PM PDT 24 849111114 ps
T521 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3651099518 Jul 11 05:26:23 PM PDT 24 Jul 11 05:26:29 PM PDT 24 38353469 ps
T522 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2334426958 Jul 11 05:26:48 PM PDT 24 Jul 11 05:26:51 PM PDT 24 287661725 ps
T523 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4293199851 Jul 11 05:26:52 PM PDT 24 Jul 11 05:26:54 PM PDT 24 16465680 ps
T524 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3592192276 Jul 11 05:26:20 PM PDT 24 Jul 11 05:26:24 PM PDT 24 25065790 ps
T525 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3996497343 Jul 11 05:26:58 PM PDT 24 Jul 11 05:27:00 PM PDT 24 32042199 ps
T526 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3961766341 Jul 11 05:26:22 PM PDT 24 Jul 11 05:26:27 PM PDT 24 114527766 ps
T527 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4149462941 Jul 11 05:26:43 PM PDT 24 Jul 11 05:26:46 PM PDT 24 19987478 ps
T528 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1602249672 Jul 11 05:26:53 PM PDT 24 Jul 11 05:26:55 PM PDT 24 64971222 ps
T529 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1410376049 Jul 11 05:26:22 PM PDT 24 Jul 11 05:26:26 PM PDT 24 66686374 ps
T530 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3583943900 Jul 11 05:26:38 PM PDT 24 Jul 11 05:26:42 PM PDT 24 15403247 ps
T531 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.602395746 Jul 11 05:26:26 PM PDT 24 Jul 11 05:26:31 PM PDT 24 28806127 ps
T532 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3518956887 Jul 11 05:26:55 PM PDT 24 Jul 11 05:26:56 PM PDT 24 23361158 ps
T533 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3082625859 Jul 11 05:26:22 PM PDT 24 Jul 11 05:26:27 PM PDT 24 14702314 ps
T534 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3826495332 Jul 11 05:26:50 PM PDT 24 Jul 11 05:26:53 PM PDT 24 17195860 ps
T535 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3998565921 Jul 11 05:26:38 PM PDT 24 Jul 11 05:26:42 PM PDT 24 217031607 ps
T536 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1405022091 Jul 11 05:26:22 PM PDT 24 Jul 11 05:26:27 PM PDT 24 23367503 ps
T537 /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.772291028 Jul 11 05:26:31 PM PDT 24 Jul 11 05:26:36 PM PDT 24 26086327 ps
T538 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2866219961 Jul 11 05:26:57 PM PDT 24 Jul 11 05:26:59 PM PDT 24 27980691 ps
T539 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2891371341 Jul 11 05:26:32 PM PDT 24 Jul 11 05:26:37 PM PDT 24 293257824 ps
T540 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4094904613 Jul 11 05:26:26 PM PDT 24 Jul 11 05:26:32 PM PDT 24 46413680 ps
T541 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.887048333 Jul 11 05:26:51 PM PDT 24 Jul 11 05:26:54 PM PDT 24 25035278 ps
T542 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.948087928 Jul 11 05:26:51 PM PDT 24 Jul 11 05:26:53 PM PDT 24 17603132 ps
T543 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1237164266 Jul 11 05:26:33 PM PDT 24 Jul 11 05:26:40 PM PDT 24 117703370 ps
T544 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.851076631 Jul 11 05:26:45 PM PDT 24 Jul 11 05:26:48 PM PDT 24 11204359 ps
T91 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.425911769 Jul 11 05:26:20 PM PDT 24 Jul 11 05:26:25 PM PDT 24 79116868 ps
T92 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.473332844 Jul 11 05:26:48 PM PDT 24 Jul 11 05:26:50 PM PDT 24 16249312 ps
T93 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.365470798 Jul 11 05:26:32 PM PDT 24 Jul 11 05:26:37 PM PDT 24 15000951 ps
T94 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.746205241 Jul 11 05:26:18 PM PDT 24 Jul 11 05:26:21 PM PDT 24 34168798 ps
T545 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3789517970 Jul 11 05:26:35 PM PDT 24 Jul 11 05:26:40 PM PDT 24 164687628 ps
T546 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2191710233 Jul 11 05:26:40 PM PDT 24 Jul 11 05:26:44 PM PDT 24 27440774 ps
T547 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1095094107 Jul 11 05:26:26 PM PDT 24 Jul 11 05:26:31 PM PDT 24 17541944 ps
T548 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1631183930 Jul 11 05:27:01 PM PDT 24 Jul 11 05:27:03 PM PDT 24 18171742 ps
T549 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.110943032 Jul 11 05:27:00 PM PDT 24 Jul 11 05:27:03 PM PDT 24 14144297 ps
T550 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4091296180 Jul 11 05:26:57 PM PDT 24 Jul 11 05:26:59 PM PDT 24 47226274 ps
T551 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2787192562 Jul 11 05:26:18 PM PDT 24 Jul 11 05:26:23 PM PDT 24 80267297 ps
T552 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.776391207 Jul 11 05:26:44 PM PDT 24 Jul 11 05:26:48 PM PDT 24 340316135 ps
T553 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.111637174 Jul 11 05:26:25 PM PDT 24 Jul 11 05:26:31 PM PDT 24 21646287 ps
T554 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3723462537 Jul 11 05:26:52 PM PDT 24 Jul 11 05:26:54 PM PDT 24 31117119 ps
T555 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1239391113 Jul 11 05:26:21 PM PDT 24 Jul 11 05:26:26 PM PDT 24 19983491 ps
T556 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.534687562 Jul 11 05:26:19 PM PDT 24 Jul 11 05:26:23 PM PDT 24 101924717 ps
T557 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3169894566 Jul 11 05:26:23 PM PDT 24 Jul 11 05:26:29 PM PDT 24 249821157 ps
T95 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1325289594 Jul 11 05:26:32 PM PDT 24 Jul 11 05:26:36 PM PDT 24 12336733 ps
T558 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.32801101 Jul 11 05:26:38 PM PDT 24 Jul 11 05:26:43 PM PDT 24 123192662 ps
T96 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1346093953 Jul 11 05:26:24 PM PDT 24 Jul 11 05:26:30 PM PDT 24 106743138 ps
T559 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.791739687 Jul 11 05:26:40 PM PDT 24 Jul 11 05:26:44 PM PDT 24 36646641 ps
T560 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3970294943 Jul 11 05:26:14 PM PDT 24 Jul 11 05:26:17 PM PDT 24 42101700 ps
T561 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3101728203 Jul 11 05:26:45 PM PDT 24 Jul 11 05:26:48 PM PDT 24 97495965 ps
T562 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3007769582 Jul 11 05:26:34 PM PDT 24 Jul 11 05:26:39 PM PDT 24 39877587 ps
T563 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3175387087 Jul 11 05:26:30 PM PDT 24 Jul 11 05:26:35 PM PDT 24 40638718 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.950182470 Jul 11 05:26:33 PM PDT 24 Jul 11 05:26:38 PM PDT 24 33552444 ps
T565 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2028390656 Jul 11 05:26:40 PM PDT 24 Jul 11 05:26:44 PM PDT 24 48238890 ps
T566 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.218090560 Jul 11 05:26:41 PM PDT 24 Jul 11 05:26:45 PM PDT 24 13130534 ps
T567 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.185238230 Jul 11 05:26:19 PM PDT 24 Jul 11 05:26:24 PM PDT 24 193478553 ps
T568 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3192694849 Jul 11 05:26:30 PM PDT 24 Jul 11 05:26:34 PM PDT 24 13590427 ps
T569 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4179098403 Jul 11 05:26:34 PM PDT 24 Jul 11 05:26:39 PM PDT 24 109784732 ps
T570 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1503140276 Jul 11 05:26:49 PM PDT 24 Jul 11 05:26:51 PM PDT 24 15301388 ps
T571 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3835807705 Jul 11 05:26:12 PM PDT 24 Jul 11 05:26:16 PM PDT 24 409333575 ps
T572 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2264596490 Jul 11 05:26:34 PM PDT 24 Jul 11 05:26:39 PM PDT 24 89205911 ps
T573 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3395123623 Jul 11 05:26:52 PM PDT 24 Jul 11 05:26:54 PM PDT 24 14761226 ps
T574 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1924271816 Jul 11 05:26:19 PM PDT 24 Jul 11 05:26:23 PM PDT 24 17784996 ps
T575 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1125533134 Jul 11 05:26:38 PM PDT 24 Jul 11 05:26:42 PM PDT 24 203985588 ps
T576 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1585881561 Jul 11 05:26:38 PM PDT 24 Jul 11 05:26:42 PM PDT 24 24668828 ps
T97 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.380215776 Jul 11 05:26:18 PM PDT 24 Jul 11 05:26:20 PM PDT 24 28430171 ps
T577 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3082488787 Jul 11 05:26:23 PM PDT 24 Jul 11 05:26:29 PM PDT 24 37519794 ps
T578 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1570600092 Jul 11 05:26:16 PM PDT 24 Jul 11 05:26:18 PM PDT 24 44480286 ps

Test location /workspace/coverage/default/44.rv_timer_stress_all.1177068200
Short name T6
Test name
Test status
Simulation time 944766498484 ps
CPU time 3845.47 seconds
Started Jul 11 05:27:58 PM PDT 24
Finished Jul 11 06:32:05 PM PDT 24
Peak memory 191300 kb
Host smart-434b6221-b860-4b87-9419-87230ee76789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177068200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.1177068200
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.3912919281
Short name T34
Test name
Test status
Simulation time 21884660265 ps
CPU time 164.65 seconds
Started Jul 11 05:27:42 PM PDT 24
Finished Jul 11 05:30:32 PM PDT 24
Peak memory 196904 kb
Host smart-054c3e4e-4f39-41c7-b314-693c94e6c30b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912919281 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.3912919281
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3141634918
Short name T109
Test name
Test status
Simulation time 1904617590987 ps
CPU time 4964.98 seconds
Started Jul 11 05:27:38 PM PDT 24
Finished Jul 11 06:50:29 PM PDT 24
Peak memory 191292 kb
Host smart-3d3abea0-e22f-4bda-be1b-ff496d85fe70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141634918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3141634918
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.4089175166
Short name T31
Test name
Test status
Simulation time 126257265 ps
CPU time 1.39 seconds
Started Jul 11 05:26:13 PM PDT 24
Finished Jul 11 05:26:17 PM PDT 24
Peak memory 194896 kb
Host smart-fa861eb0-b2ab-4181-8da6-a22fb4912ece
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089175166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.4089175166
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.767625338
Short name T117
Test name
Test status
Simulation time 3053871238400 ps
CPU time 2545.72 seconds
Started Jul 11 05:27:15 PM PDT 24
Finished Jul 11 06:09:44 PM PDT 24
Peak memory 195732 kb
Host smart-2356936c-af22-4a4d-bd92-00b7c1e1b38b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767625338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.767625338
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2802533578
Short name T281
Test name
Test status
Simulation time 1301378379287 ps
CPU time 1480.95 seconds
Started Jul 11 05:26:59 PM PDT 24
Finished Jul 11 05:51:41 PM PDT 24
Peak memory 191244 kb
Host smart-d77a84c9-0d28-4b9f-964d-247cd6ee2a25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802533578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2802533578
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3560788726
Short name T66
Test name
Test status
Simulation time 901275948675 ps
CPU time 1176.64 seconds
Started Jul 11 05:27:27 PM PDT 24
Finished Jul 11 05:47:08 PM PDT 24
Peak memory 191300 kb
Host smart-45a7392b-8151-442d-95c8-e68257892571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560788726 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3560788726
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.271123546
Short name T69
Test name
Test status
Simulation time 735792408919 ps
CPU time 1723.41 seconds
Started Jul 11 05:27:24 PM PDT 24
Finished Jul 11 05:56:11 PM PDT 24
Peak memory 191272 kb
Host smart-7739cbd4-37ed-4ea8-846b-b52bed45757e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271123546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
271123546
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.3934398202
Short name T70
Test name
Test status
Simulation time 1089157867140 ps
CPU time 1503.85 seconds
Started Jul 11 05:26:58 PM PDT 24
Finished Jul 11 05:52:04 PM PDT 24
Peak memory 191180 kb
Host smart-41435332-c2ed-4c4a-a78e-d6dcf2e40e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934398202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
3934398202
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.4004817
Short name T84
Test name
Test status
Simulation time 139473313 ps
CPU time 3.25 seconds
Started Jul 11 05:26:21 PM PDT 24
Finished Jul 11 05:26:27 PM PDT 24
Peak memory 193476 kb
Host smart-3c7dac1a-894b-4929-9f1f-198b969c7e11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_bas
h.4004817
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/183.rv_timer_random.2914377387
Short name T5
Test name
Test status
Simulation time 249118525776 ps
CPU time 595.25 seconds
Started Jul 11 05:29:03 PM PDT 24
Finished Jul 11 05:39:00 PM PDT 24
Peak memory 191296 kb
Host smart-8eb6d2af-170f-4ccf-b1f1-82f0ba59c065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914377387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2914377387
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1619053791
Short name T137
Test name
Test status
Simulation time 2196494790189 ps
CPU time 917.35 seconds
Started Jul 11 05:27:33 PM PDT 24
Finished Jul 11 05:42:55 PM PDT 24
Peak memory 191272 kb
Host smart-9430cc76-78ec-4a59-ab27-bed592375028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619053791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1619053791
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3187938094
Short name T153
Test name
Test status
Simulation time 462416189357 ps
CPU time 1224.37 seconds
Started Jul 11 05:27:30 PM PDT 24
Finished Jul 11 05:47:59 PM PDT 24
Peak memory 191208 kb
Host smart-a54c1cdb-79f3-4abf-a541-a7edc2f63514
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187938094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3187938094
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.2637600378
Short name T158
Test name
Test status
Simulation time 532663261269 ps
CPU time 3998.32 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 06:34:18 PM PDT 24
Peak memory 191260 kb
Host smart-7a758d44-dc93-4fa7-884f-ba792c21baea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637600378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.2637600378
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.676065411
Short name T16
Test name
Test status
Simulation time 40292634 ps
CPU time 0.81 seconds
Started Jul 11 05:27:02 PM PDT 24
Finished Jul 11 05:27:05 PM PDT 24
Peak memory 213392 kb
Host smart-b944fe95-5824-49b5-96e0-83896b8b5b0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676065411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.676065411
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3832362451
Short name T25
Test name
Test status
Simulation time 2233312048732 ps
CPU time 913.52 seconds
Started Jul 11 05:27:24 PM PDT 24
Finished Jul 11 05:42:40 PM PDT 24
Peak memory 191300 kb
Host smart-2bc4e083-905c-40fe-bfd7-6a9c0864b9ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832362451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3832362451
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.519810123
Short name T45
Test name
Test status
Simulation time 1770683074825 ps
CPU time 894.5 seconds
Started Jul 11 05:29:09 PM PDT 24
Finished Jul 11 05:44:05 PM PDT 24
Peak memory 191196 kb
Host smart-6758af5c-77d4-4e32-b1ae-5db625a5c9a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519810123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.519810123
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3338234256
Short name T340
Test name
Test status
Simulation time 7537054607547 ps
CPU time 2394.4 seconds
Started Jul 11 05:27:01 PM PDT 24
Finished Jul 11 06:06:58 PM PDT 24
Peak memory 195244 kb
Host smart-0f92eb4b-c1b8-456e-8383-8b792439749c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338234256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3338234256
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/178.rv_timer_random.2607968369
Short name T228
Test name
Test status
Simulation time 248293241836 ps
CPU time 508.73 seconds
Started Jul 11 05:28:58 PM PDT 24
Finished Jul 11 05:37:29 PM PDT 24
Peak memory 183052 kb
Host smart-886ce891-95ad-46da-b24f-4292f2cf1d9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607968369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2607968369
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.3754697842
Short name T251
Test name
Test status
Simulation time 635606486692 ps
CPU time 361.51 seconds
Started Jul 11 05:28:26 PM PDT 24
Finished Jul 11 05:34:29 PM PDT 24
Peak memory 191308 kb
Host smart-776769b2-218d-4208-b869-5d671b4fb6f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754697842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3754697842
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1748664025
Short name T166
Test name
Test status
Simulation time 655705313797 ps
CPU time 1597.24 seconds
Started Jul 11 05:27:23 PM PDT 24
Finished Jul 11 05:54:04 PM PDT 24
Peak memory 191236 kb
Host smart-b4b37c60-8b94-465d-ac12-2f981f07a068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748664025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1748664025
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2435774282
Short name T80
Test name
Test status
Simulation time 812677169536 ps
CPU time 933.82 seconds
Started Jul 11 05:28:13 PM PDT 24
Finished Jul 11 05:43:49 PM PDT 24
Peak memory 195852 kb
Host smart-a31af8c4-6f4c-4a37-9d3c-0f2314d3c6e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435774282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2435774282
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.4245970143
Short name T112
Test name
Test status
Simulation time 4240298103646 ps
CPU time 1188.29 seconds
Started Jul 11 05:28:13 PM PDT 24
Finished Jul 11 05:48:02 PM PDT 24
Peak memory 196156 kb
Host smart-3e6865b3-c1cb-4b3b-8d10-dbebb3fb2ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245970143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.4245970143
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/73.rv_timer_random.1826810050
Short name T282
Test name
Test status
Simulation time 278525688532 ps
CPU time 1434.59 seconds
Started Jul 11 05:28:17 PM PDT 24
Finished Jul 11 05:52:14 PM PDT 24
Peak memory 191212 kb
Host smart-2ee06d61-91cd-4286-9d99-1a301de1b89d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826810050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.1826810050
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3703419645
Short name T132
Test name
Test status
Simulation time 128754459121 ps
CPU time 446.64 seconds
Started Jul 11 05:29:11 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 191228 kb
Host smart-4d574b06-0cb3-41bc-af51-f282a0402619
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703419645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3703419645
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1656287015
Short name T189
Test name
Test status
Simulation time 518369872675 ps
CPU time 469.9 seconds
Started Jul 11 05:28:20 PM PDT 24
Finished Jul 11 05:36:12 PM PDT 24
Peak memory 191228 kb
Host smart-5e177711-dad4-4dbe-9759-239106d049c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656287015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1656287015
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.683481274
Short name T55
Test name
Test status
Simulation time 793159589232 ps
CPU time 355.23 seconds
Started Jul 11 05:28:22 PM PDT 24
Finished Jul 11 05:34:20 PM PDT 24
Peak memory 191268 kb
Host smart-0c12f78b-4f78-4004-8a46-1675c1df6289
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683481274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.683481274
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3056869909
Short name T301
Test name
Test status
Simulation time 125576188177 ps
CPU time 225.57 seconds
Started Jul 11 05:28:55 PM PDT 24
Finished Jul 11 05:32:41 PM PDT 24
Peak memory 190692 kb
Host smart-d22a4d6d-9e90-4c7c-a664-0f06659bc169
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056869909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3056869909
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.2389396582
Short name T279
Test name
Test status
Simulation time 726736677512 ps
CPU time 420.92 seconds
Started Jul 11 05:27:32 PM PDT 24
Finished Jul 11 05:34:38 PM PDT 24
Peak memory 191304 kb
Host smart-a43503f5-7a7e-4fee-b749-d07dbd8a99ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389396582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2389396582
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3435208249
Short name T185
Test name
Test status
Simulation time 209401710340 ps
CPU time 179.75 seconds
Started Jul 11 05:28:04 PM PDT 24
Finished Jul 11 05:31:06 PM PDT 24
Peak memory 191296 kb
Host smart-0ff5272c-18f5-432c-88aa-736628adfbae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435208249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3435208249
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1570975343
Short name T43
Test name
Test status
Simulation time 46717723666 ps
CPU time 137.52 seconds
Started Jul 11 05:28:23 PM PDT 24
Finished Jul 11 05:30:42 PM PDT 24
Peak memory 191308 kb
Host smart-143d3cd6-2c18-495a-9481-085695758287
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570975343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1570975343
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1081633645
Short name T118
Test name
Test status
Simulation time 609143255611 ps
CPU time 679.27 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:39:51 PM PDT 24
Peak memory 191236 kb
Host smart-80498d78-ecd5-42d2-9320-0d422693a7c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081633645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1081633645
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3995114390
Short name T124
Test name
Test status
Simulation time 501192211915 ps
CPU time 757.71 seconds
Started Jul 11 05:28:32 PM PDT 24
Finished Jul 11 05:41:11 PM PDT 24
Peak memory 191296 kb
Host smart-6ae09c67-5477-4087-b820-a6d764bfcda4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995114390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3995114390
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4205469442
Short name T161
Test name
Test status
Simulation time 1437562118315 ps
CPU time 910.48 seconds
Started Jul 11 05:28:36 PM PDT 24
Finished Jul 11 05:43:48 PM PDT 24
Peak memory 191308 kb
Host smart-93586233-d047-4a19-8f55-b9f24969d98e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205469442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4205469442
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.3628502298
Short name T206
Test name
Test status
Simulation time 1033283367103 ps
CPU time 208.47 seconds
Started Jul 11 05:28:58 PM PDT 24
Finished Jul 11 05:32:28 PM PDT 24
Peak memory 191196 kb
Host smart-8ef59710-1440-45b6-b8e0-fd7683f2ab99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628502298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.3628502298
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.3624974708
Short name T213
Test name
Test status
Simulation time 107306566390 ps
CPU time 348.08 seconds
Started Jul 11 05:27:20 PM PDT 24
Finished Jul 11 05:33:11 PM PDT 24
Peak memory 191308 kb
Host smart-ec4e2a8d-b55f-4350-9216-0d2f189650b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624974708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3624974708
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1025753089
Short name T234
Test name
Test status
Simulation time 222952611474 ps
CPU time 315.29 seconds
Started Jul 11 05:28:52 PM PDT 24
Finished Jul 11 05:34:09 PM PDT 24
Peak memory 191236 kb
Host smart-2b192078-ecd9-4ff2-a55a-00b8d2b5b0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025753089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1025753089
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3372515464
Short name T280
Test name
Test status
Simulation time 337688989748 ps
CPU time 779.16 seconds
Started Jul 11 05:27:33 PM PDT 24
Finished Jul 11 05:40:37 PM PDT 24
Peak memory 191312 kb
Host smart-77155228-66f7-472c-be99-9c9653a7bef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372515464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3372515464
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1563552424
Short name T221
Test name
Test status
Simulation time 223777341617 ps
CPU time 367.53 seconds
Started Jul 11 05:27:42 PM PDT 24
Finished Jul 11 05:33:55 PM PDT 24
Peak memory 183096 kb
Host smart-696730cd-23e6-483e-a9af-be0eb1cf7ac0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563552424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1563552424
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/139.rv_timer_random.3819112227
Short name T150
Test name
Test status
Simulation time 1652342130829 ps
CPU time 436.01 seconds
Started Jul 11 05:28:55 PM PDT 24
Finished Jul 11 05:36:12 PM PDT 24
Peak memory 191132 kb
Host smart-475cb470-71af-423c-a05b-e40b4362bcd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819112227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3819112227
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.705503648
Short name T304
Test name
Test status
Simulation time 358971914742 ps
CPU time 412.49 seconds
Started Jul 11 05:28:50 PM PDT 24
Finished Jul 11 05:35:45 PM PDT 24
Peak memory 191184 kb
Host smart-d27a98d8-1eb8-497c-b4d6-8e9944d2b393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705503648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.705503648
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.371621180
Short name T182
Test name
Test status
Simulation time 107941397201 ps
CPU time 155.79 seconds
Started Jul 11 05:29:14 PM PDT 24
Finished Jul 11 05:31:51 PM PDT 24
Peak memory 191212 kb
Host smart-6c0a716e-6ba4-4cb4-a2c1-92b616350b14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371621180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.371621180
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.2235770108
Short name T332
Test name
Test status
Simulation time 728083480751 ps
CPU time 298.41 seconds
Started Jul 11 05:27:26 PM PDT 24
Finished Jul 11 05:32:28 PM PDT 24
Peak memory 191272 kb
Host smart-aa0bef3d-a223-427e-b99f-b95719cf8a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235770108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.2235770108
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3949952291
Short name T311
Test name
Test status
Simulation time 270026593846 ps
CPU time 1073.87 seconds
Started Jul 11 05:27:35 PM PDT 24
Finished Jul 11 05:45:34 PM PDT 24
Peak memory 191196 kb
Host smart-5affccac-261e-4d93-8ea0-533758143a69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949952291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3949952291
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.1376508774
Short name T315
Test name
Test status
Simulation time 706284226361 ps
CPU time 327.1 seconds
Started Jul 11 05:28:32 PM PDT 24
Finished Jul 11 05:34:01 PM PDT 24
Peak memory 191224 kb
Host smart-fbcb53e1-50c8-4b8f-b23c-44dff8e4f181
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376508774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1376508774
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1996293575
Short name T26
Test name
Test status
Simulation time 176817536324 ps
CPU time 301.79 seconds
Started Jul 11 05:28:35 PM PDT 24
Finished Jul 11 05:33:38 PM PDT 24
Peak memory 194844 kb
Host smart-0748be3e-ac76-4bd0-97c7-f4cadd3306ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996293575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1996293575
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.3428005998
Short name T261
Test name
Test status
Simulation time 162821414096 ps
CPU time 273.23 seconds
Started Jul 11 05:28:23 PM PDT 24
Finished Jul 11 05:32:58 PM PDT 24
Peak memory 191220 kb
Host smart-70b08bfe-785a-4333-ba13-6fc988285eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428005998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.3428005998
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1142640129
Short name T119
Test name
Test status
Simulation time 165748674739 ps
CPU time 398.6 seconds
Started Jul 11 05:28:55 PM PDT 24
Finished Jul 11 05:35:34 PM PDT 24
Peak memory 191212 kb
Host smart-ab9a64f3-4cf7-49e8-b9a6-e7619d31eed1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142640129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1142640129
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.193842716
Short name T165
Test name
Test status
Simulation time 103555516110 ps
CPU time 390.2 seconds
Started Jul 11 05:27:29 PM PDT 24
Finished Jul 11 05:34:04 PM PDT 24
Peak memory 190308 kb
Host smart-c6e66046-2d4b-48a6-9c53-c1b9ae7002eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193842716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.193842716
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.471011092
Short name T23
Test name
Test status
Simulation time 73275515712 ps
CPU time 298.77 seconds
Started Jul 11 05:28:36 PM PDT 24
Finished Jul 11 05:33:36 PM PDT 24
Peak memory 191268 kb
Host smart-161b0d4c-467f-4add-bff0-cb4ad0cc1dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471011092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.471011092
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1157689724
Short name T276
Test name
Test status
Simulation time 1825189116647 ps
CPU time 993.57 seconds
Started Jul 11 05:27:24 PM PDT 24
Finished Jul 11 05:44:01 PM PDT 24
Peak memory 183080 kb
Host smart-fcaed95a-152c-4e4c-8804-6df1a94601bd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157689724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1157689724
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/196.rv_timer_random.2499601778
Short name T130
Test name
Test status
Simulation time 465886303787 ps
CPU time 501.21 seconds
Started Jul 11 05:29:10 PM PDT 24
Finished Jul 11 05:37:32 PM PDT 24
Peak memory 191296 kb
Host smart-95bacc0a-3d78-49c4-a7d8-2195265ab507
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499601778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2499601778
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2259062882
Short name T114
Test name
Test status
Simulation time 1060399745173 ps
CPU time 1334.98 seconds
Started Jul 11 05:27:30 PM PDT 24
Finished Jul 11 05:49:50 PM PDT 24
Peak memory 196356 kb
Host smart-8ab3d981-28ed-4ca5-999e-d4b2a62afbd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259062882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2259062882
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_random.2965061222
Short name T329
Test name
Test status
Simulation time 241567080918 ps
CPU time 191.58 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:30:50 PM PDT 24
Peak memory 193704 kb
Host smart-896e1df4-742a-4c84-8f77-005dff5e9f7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965061222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2965061222
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.4270648460
Short name T99
Test name
Test status
Simulation time 25904649 ps
CPU time 0.74 seconds
Started Jul 11 05:26:39 PM PDT 24
Finished Jul 11 05:26:43 PM PDT 24
Peak memory 191960 kb
Host smart-3d0737db-1fa4-4730-ae1d-8a950324faa2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270648460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.4270648460
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/109.rv_timer_random.2619909015
Short name T145
Test name
Test status
Simulation time 411070072546 ps
CPU time 247.6 seconds
Started Jul 11 05:28:36 PM PDT 24
Finished Jul 11 05:32:45 PM PDT 24
Peak memory 191224 kb
Host smart-e5b2863e-b86f-4907-b991-68476f7e930f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619909015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2619909015
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.726922458
Short name T113
Test name
Test status
Simulation time 77543102225 ps
CPU time 110.94 seconds
Started Jul 11 05:28:35 PM PDT 24
Finished Jul 11 05:30:28 PM PDT 24
Peak memory 195028 kb
Host smart-4a80506c-65c9-483a-acf4-9f2042459e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726922458 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.726922458
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.1208615474
Short name T240
Test name
Test status
Simulation time 1455569230795 ps
CPU time 676.72 seconds
Started Jul 11 05:27:29 PM PDT 24
Finished Jul 11 05:38:51 PM PDT 24
Peak memory 191092 kb
Host smart-b0b79da3-a39a-4de8-adef-7c2b345950e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208615474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.1208615474
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2487133314
Short name T229
Test name
Test status
Simulation time 560435308195 ps
CPU time 466.54 seconds
Started Jul 11 05:27:23 PM PDT 24
Finished Jul 11 05:35:12 PM PDT 24
Peak memory 182980 kb
Host smart-7e23fc09-3280-4c24-a339-d742d24754d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487133314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2487133314
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/146.rv_timer_random.614547229
Short name T241
Test name
Test status
Simulation time 354375400977 ps
CPU time 438.44 seconds
Started Jul 11 05:28:36 PM PDT 24
Finished Jul 11 05:35:57 PM PDT 24
Peak memory 195176 kb
Host smart-93e43ff2-3bc5-41c6-b390-f8d084a0caca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614547229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.614547229
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1437974379
Short name T191
Test name
Test status
Simulation time 83695382440 ps
CPU time 686.59 seconds
Started Jul 11 05:28:40 PM PDT 24
Finished Jul 11 05:40:10 PM PDT 24
Peak memory 191304 kb
Host smart-71a06677-3c01-4ba8-bcf8-e815f54bd2d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437974379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1437974379
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.1657569427
Short name T4
Test name
Test status
Simulation time 81254903688 ps
CPU time 122.7 seconds
Started Jul 11 05:27:26 PM PDT 24
Finished Jul 11 05:29:32 PM PDT 24
Peak memory 191304 kb
Host smart-1ac695b9-2fee-4e0a-a699-a98563419b35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657569427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1657569427
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1356869201
Short name T243
Test name
Test status
Simulation time 20110207825 ps
CPU time 19.34 seconds
Started Jul 11 05:27:28 PM PDT 24
Finished Jul 11 05:27:52 PM PDT 24
Peak memory 191204 kb
Host smart-3feb4bd4-367e-41f6-9473-41be4042d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356869201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1356869201
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/162.rv_timer_random.1031828846
Short name T226
Test name
Test status
Simulation time 154514243092 ps
CPU time 1081.64 seconds
Started Jul 11 05:28:53 PM PDT 24
Finished Jul 11 05:46:56 PM PDT 24
Peak memory 191300 kb
Host smart-151cead6-068d-409e-8d7c-6b3ddf83867e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031828846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1031828846
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.4005444020
Short name T116
Test name
Test status
Simulation time 368884759339 ps
CPU time 215.64 seconds
Started Jul 11 05:28:52 PM PDT 24
Finished Jul 11 05:32:29 PM PDT 24
Peak memory 191236 kb
Host smart-e9535b19-97bc-470a-8b54-afbe97b66743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005444020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.4005444020
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.3603849674
Short name T190
Test name
Test status
Simulation time 1657231623093 ps
CPU time 409.42 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:34:28 PM PDT 24
Peak memory 191300 kb
Host smart-bb44f235-e58f-4d11-b6eb-984f99ffadf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603849674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3603849674
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.33690953
Short name T347
Test name
Test status
Simulation time 460866748286 ps
CPU time 122.7 seconds
Started Jul 11 05:27:37 PM PDT 24
Finished Jul 11 05:29:45 PM PDT 24
Peak memory 183092 kb
Host smart-399d1796-a725-4f46-b1aa-d829b9a40a26
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33690953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.rv_timer_cfg_update_on_fly.33690953
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_random.3622301722
Short name T146
Test name
Test status
Simulation time 182255822699 ps
CPU time 791.18 seconds
Started Jul 11 05:27:33 PM PDT 24
Finished Jul 11 05:40:49 PM PDT 24
Peak memory 191296 kb
Host smart-c5df45a5-93c4-4294-9736-cc604143d978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622301722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3622301722
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2195749927
Short name T259
Test name
Test status
Simulation time 234336155870 ps
CPU time 122.07 seconds
Started Jul 11 05:27:41 PM PDT 24
Finished Jul 11 05:29:48 PM PDT 24
Peak memory 182976 kb
Host smart-49d752aa-5fca-43d2-b575-cbbeda625ed9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195749927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2195749927
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.797156189
Short name T175
Test name
Test status
Simulation time 74338125557 ps
CPU time 397.28 seconds
Started Jul 11 05:27:40 PM PDT 24
Finished Jul 11 05:34:22 PM PDT 24
Peak memory 183060 kb
Host smart-ff85d163-a406-41b9-87bd-85e77278ff9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797156189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.797156189
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2448734974
Short name T47
Test name
Test status
Simulation time 262372427864 ps
CPU time 217.8 seconds
Started Jul 11 05:28:17 PM PDT 24
Finished Jul 11 05:31:57 PM PDT 24
Peak memory 194976 kb
Host smart-c432eaf3-f30e-49f8-b391-5b687ebcfea1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448734974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2448734974
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.2691502122
Short name T287
Test name
Test status
Simulation time 234463814908 ps
CPU time 513.7 seconds
Started Jul 11 05:28:28 PM PDT 24
Finished Jul 11 05:37:04 PM PDT 24
Peak memory 192880 kb
Host smart-663c085a-eba3-4e01-b3a0-26bdaf14952f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691502122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.2691502122
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3961766341
Short name T526
Test name
Test status
Simulation time 114527766 ps
CPU time 0.82 seconds
Started Jul 11 05:26:22 PM PDT 24
Finished Jul 11 05:26:27 PM PDT 24
Peak memory 182784 kb
Host smart-b8476377-a7e4-44e2-8017-43a65a16f203
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961766341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3961766341
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/100.rv_timer_random.626883209
Short name T266
Test name
Test status
Simulation time 23365921103 ps
CPU time 40.78 seconds
Started Jul 11 05:28:25 PM PDT 24
Finished Jul 11 05:29:06 PM PDT 24
Peak memory 183108 kb
Host smart-aaac70f9-ae35-4c22-811e-4a4da5ba9d5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626883209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.626883209
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.4263135874
Short name T296
Test name
Test status
Simulation time 59561232468 ps
CPU time 97.7 seconds
Started Jul 11 05:28:25 PM PDT 24
Finished Jul 11 05:30:03 PM PDT 24
Peak memory 194868 kb
Host smart-f029f70c-8fdf-4d8d-9463-66f225ae64ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263135874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.4263135874
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.992260032
Short name T186
Test name
Test status
Simulation time 378603779582 ps
CPU time 221.55 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:32:13 PM PDT 24
Peak memory 191296 kb
Host smart-290da174-0a15-4b9d-81f0-a934395d407f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992260032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.992260032
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.4041385331
Short name T232
Test name
Test status
Simulation time 159666534177 ps
CPU time 208.83 seconds
Started Jul 11 05:28:32 PM PDT 24
Finished Jul 11 05:32:02 PM PDT 24
Peak memory 191200 kb
Host smart-642ea133-8d04-4bf5-b553-8419587c09f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041385331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.4041385331
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3513064796
Short name T195
Test name
Test status
Simulation time 200706536628 ps
CPU time 1041.25 seconds
Started Jul 11 05:28:30 PM PDT 24
Finished Jul 11 05:45:53 PM PDT 24
Peak memory 191236 kb
Host smart-9ce056f4-56ce-494f-9d1d-103e9bb36a61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513064796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3513064796
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.2156059095
Short name T223
Test name
Test status
Simulation time 1969965067859 ps
CPU time 650.59 seconds
Started Jul 11 05:28:52 PM PDT 24
Finished Jul 11 05:39:44 PM PDT 24
Peak memory 191212 kb
Host smart-f195601d-3700-4d82-acc9-a3378ece9ef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156059095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.2156059095
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4208298415
Short name T291
Test name
Test status
Simulation time 543154457575 ps
CPU time 299.36 seconds
Started Jul 11 05:27:22 PM PDT 24
Finished Jul 11 05:32:25 PM PDT 24
Peak memory 183044 kb
Host smart-de884d37-582f-4ab3-98d2-2fa1b48dc6e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208298415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.4208298415
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_random.3239684285
Short name T236
Test name
Test status
Simulation time 25733489610 ps
CPU time 47.18 seconds
Started Jul 11 05:27:24 PM PDT 24
Finished Jul 11 05:28:14 PM PDT 24
Peak memory 183088 kb
Host smart-5f3d1b64-4562-4cc0-93cd-8cfb7d3c96e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239684285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.3239684285
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.2547400572
Short name T135
Test name
Test status
Simulation time 102839846560 ps
CPU time 311.47 seconds
Started Jul 11 05:29:09 PM PDT 24
Finished Jul 11 05:34:21 PM PDT 24
Peak memory 191236 kb
Host smart-7c75bfbe-4c1f-41b0-9348-c093a7ad2e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547400572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.2547400572
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3707691442
Short name T298
Test name
Test status
Simulation time 154276710298 ps
CPU time 336.12 seconds
Started Jul 11 05:27:04 PM PDT 24
Finished Jul 11 05:32:42 PM PDT 24
Peak memory 191224 kb
Host smart-1553d9fc-c565-4450-8fb4-c8ba81c21503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707691442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3707691442
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_random.2388461813
Short name T337
Test name
Test status
Simulation time 107298292121 ps
CPU time 171.77 seconds
Started Jul 11 05:27:29 PM PDT 24
Finished Jul 11 05:30:26 PM PDT 24
Peak memory 194840 kb
Host smart-4dac9801-951e-4992-85cd-93045a87c656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388461813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2388461813
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.4282008187
Short name T263
Test name
Test status
Simulation time 197814631559 ps
CPU time 2768.55 seconds
Started Jul 11 05:27:58 PM PDT 24
Finished Jul 11 06:14:08 PM PDT 24
Peak memory 191304 kb
Host smart-1de4d6fe-c2dd-4c64-bf7e-3f0c26cc74e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282008187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.4282008187
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3102291193
Short name T168
Test name
Test status
Simulation time 235531806230 ps
CPU time 508.58 seconds
Started Jul 11 05:28:05 PM PDT 24
Finished Jul 11 05:36:36 PM PDT 24
Peak memory 194452 kb
Host smart-30848919-7738-46d0-91e4-3f8e68adae1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102291193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3102291193
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.850619026
Short name T345
Test name
Test status
Simulation time 314010801267 ps
CPU time 437.69 seconds
Started Jul 11 05:28:17 PM PDT 24
Finished Jul 11 05:35:37 PM PDT 24
Peak memory 191192 kb
Host smart-c44c2d12-d175-4b05-90f3-73ea090281b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850619026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.850619026
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1789557079
Short name T176
Test name
Test status
Simulation time 107141445771 ps
CPU time 178.55 seconds
Started Jul 11 05:28:19 PM PDT 24
Finished Jul 11 05:31:19 PM PDT 24
Peak memory 191236 kb
Host smart-2623a1d8-c4ea-417e-8f13-25b8404666b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789557079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1789557079
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3663800445
Short name T86
Test name
Test status
Simulation time 31074320 ps
CPU time 0.85 seconds
Started Jul 11 05:26:13 PM PDT 24
Finished Jul 11 05:26:16 PM PDT 24
Peak memory 191428 kb
Host smart-7ca0f945-8f50-4987-bcaa-0443e1d72e3d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663800445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3663800445
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3970294943
Short name T560
Test name
Test status
Simulation time 42101700 ps
CPU time 1.52 seconds
Started Jul 11 05:26:14 PM PDT 24
Finished Jul 11 05:26:17 PM PDT 24
Peak memory 192416 kb
Host smart-c7a63d68-ff23-42b8-a8f4-09a806a92124
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970294943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3970294943
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1682582607
Short name T90
Test name
Test status
Simulation time 18078290 ps
CPU time 0.6 seconds
Started Jul 11 05:26:19 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 182260 kb
Host smart-83ff1503-b143-4d27-811d-c0f94dddf44e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682582607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1682582607
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.594515765
Short name T490
Test name
Test status
Simulation time 72768065 ps
CPU time 0.71 seconds
Started Jul 11 05:26:15 PM PDT 24
Finished Jul 11 05:26:17 PM PDT 24
Peak memory 194660 kb
Host smart-7f5862cd-91c6-45bf-b881-2ed54eee8fcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594515765 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.594515765
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.27302374
Short name T466
Test name
Test status
Simulation time 18944449 ps
CPU time 0.57 seconds
Started Jul 11 05:26:14 PM PDT 24
Finished Jul 11 05:26:16 PM PDT 24
Peak memory 182200 kb
Host smart-bc019672-916c-4f63-8303-50bf0938523d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27302374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.27302374
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1276346694
Short name T508
Test name
Test status
Simulation time 16396389 ps
CPU time 0.56 seconds
Started Jul 11 05:26:19 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 182136 kb
Host smart-8e37dfa5-e770-4e51-88c3-08d60ddb5f87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276346694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1276346694
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.2581786414
Short name T494
Test name
Test status
Simulation time 48688788 ps
CPU time 0.76 seconds
Started Jul 11 05:26:10 PM PDT 24
Finished Jul 11 05:26:13 PM PDT 24
Peak memory 192740 kb
Host smart-f14cff88-33e1-43c9-bf0e-6b73fddf0924
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581786414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.2581786414
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3835807705
Short name T571
Test name
Test status
Simulation time 409333575 ps
CPU time 1.84 seconds
Started Jul 11 05:26:12 PM PDT 24
Finished Jul 11 05:26:16 PM PDT 24
Peak memory 197056 kb
Host smart-6ac04524-c1cf-47be-8cda-3eaec5b87594
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835807705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3835807705
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.425911769
Short name T91
Test name
Test status
Simulation time 79116868 ps
CPU time 0.87 seconds
Started Jul 11 05:26:20 PM PDT 24
Finished Jul 11 05:26:25 PM PDT 24
Peak memory 191980 kb
Host smart-97745e69-f611-4c35-aba5-ccf3d7876490
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425911769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.425911769
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.839465752
Short name T87
Test name
Test status
Simulation time 40859800 ps
CPU time 1.51 seconds
Started Jul 11 05:26:19 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 182396 kb
Host smart-755bf2b0-48dc-43b3-8f02-3c969cc681c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839465752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.839465752
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1123355434
Short name T82
Test name
Test status
Simulation time 64731155 ps
CPU time 0.56 seconds
Started Jul 11 05:26:19 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 182200 kb
Host smart-210026e7-f67f-4f8f-b7b5-0a3556e934b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123355434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1123355434
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.534687562
Short name T556
Test name
Test status
Simulation time 101924717 ps
CPU time 1.21 seconds
Started Jul 11 05:26:19 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 196964 kb
Host smart-8246034b-a4ad-45fa-bb48-5bf62352eb3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534687562 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.534687562
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3592192276
Short name T524
Test name
Test status
Simulation time 25065790 ps
CPU time 0.56 seconds
Started Jul 11 05:26:20 PM PDT 24
Finished Jul 11 05:26:24 PM PDT 24
Peak memory 181972 kb
Host smart-ea91f8f8-89a7-450d-aa6f-b69f5957f064
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592192276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3592192276
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1570600092
Short name T578
Test name
Test status
Simulation time 44480286 ps
CPU time 0.55 seconds
Started Jul 11 05:26:16 PM PDT 24
Finished Jul 11 05:26:18 PM PDT 24
Peak memory 181624 kb
Host smart-32ae453d-c4e9-4c40-8b32-ee5e18e62aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570600092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1570600092
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4231595065
Short name T506
Test name
Test status
Simulation time 107537675 ps
CPU time 0.75 seconds
Started Jul 11 05:26:24 PM PDT 24
Finished Jul 11 05:26:29 PM PDT 24
Peak memory 191172 kb
Host smart-e596e0ea-f9f2-4fe1-8e65-34544fb4b42a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231595065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4231595065
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1933618054
Short name T503
Test name
Test status
Simulation time 78926901 ps
CPU time 2.03 seconds
Started Jul 11 05:26:18 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 197028 kb
Host smart-75284a85-c6db-450b-b4b1-aa5f98d46c78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933618054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1933618054
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3524501930
Short name T51
Test name
Test status
Simulation time 23464329 ps
CPU time 0.73 seconds
Started Jul 11 05:26:33 PM PDT 24
Finished Jul 11 05:26:38 PM PDT 24
Peak memory 194132 kb
Host smart-a4157129-46d6-4a12-8174-30054d2e18d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524501930 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3524501930
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.365470798
Short name T93
Test name
Test status
Simulation time 15000951 ps
CPU time 0.62 seconds
Started Jul 11 05:26:32 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 182248 kb
Host smart-5a22b9c7-afcb-4bda-8530-8852f1f742e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365470798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.365470798
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.2364857901
Short name T495
Test name
Test status
Simulation time 12496839 ps
CPU time 0.54 seconds
Started Jul 11 05:26:34 PM PDT 24
Finished Jul 11 05:26:39 PM PDT 24
Peak memory 182000 kb
Host smart-7a213e77-e66e-4213-97cb-8acc17a28a51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364857901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.2364857901
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4179098403
Short name T569
Test name
Test status
Simulation time 109784732 ps
CPU time 0.82 seconds
Started Jul 11 05:26:34 PM PDT 24
Finished Jul 11 05:26:39 PM PDT 24
Peak memory 193004 kb
Host smart-38605f01-6789-4b6d-83a4-604abe36cf24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179098403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4179098403
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1793597347
Short name T459
Test name
Test status
Simulation time 38722051 ps
CPU time 1.03 seconds
Started Jul 11 05:26:32 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 196104 kb
Host smart-12ace2c2-5190-4451-acb8-d95a72b33942
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793597347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1793597347
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3300337164
Short name T104
Test name
Test status
Simulation time 183897545 ps
CPU time 1.3 seconds
Started Jul 11 05:26:31 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 194580 kb
Host smart-ebd075d2-cca6-4222-bf57-71ed3e53b880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300337164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3300337164
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.772291028
Short name T537
Test name
Test status
Simulation time 26086327 ps
CPU time 0.75 seconds
Started Jul 11 05:26:31 PM PDT 24
Finished Jul 11 05:26:36 PM PDT 24
Peak memory 194788 kb
Host smart-6d782332-cee2-445b-a09f-58916631afc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772291028 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.772291028
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3192694849
Short name T568
Test name
Test status
Simulation time 13590427 ps
CPU time 0.59 seconds
Started Jul 11 05:26:30 PM PDT 24
Finished Jul 11 05:26:34 PM PDT 24
Peak memory 182184 kb
Host smart-1118fe01-cf5e-4415-913d-4aa61005d552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192694849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3192694849
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3577777354
Short name T473
Test name
Test status
Simulation time 62580857 ps
CPU time 0.54 seconds
Started Jul 11 05:26:32 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 181608 kb
Host smart-385e3ad5-c4be-427d-a448-4840e69328c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577777354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3577777354
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2264596490
Short name T572
Test name
Test status
Simulation time 89205911 ps
CPU time 0.84 seconds
Started Jul 11 05:26:34 PM PDT 24
Finished Jul 11 05:26:39 PM PDT 24
Peak memory 193000 kb
Host smart-72150416-5728-478d-b9c9-045fa76f7734
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264596490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2264596490
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.374818575
Short name T499
Test name
Test status
Simulation time 233423254 ps
CPU time 2.31 seconds
Started Jul 11 05:26:32 PM PDT 24
Finished Jul 11 05:26:38 PM PDT 24
Peak memory 197036 kb
Host smart-e17bcfe7-becc-4f21-a921-b15ecbf7ea5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374818575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.374818575
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3007769582
Short name T562
Test name
Test status
Simulation time 39877587 ps
CPU time 0.82 seconds
Started Jul 11 05:26:34 PM PDT 24
Finished Jul 11 05:26:39 PM PDT 24
Peak memory 182748 kb
Host smart-ac675c16-e549-45d7-b087-b084e9bd6b04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007769582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3007769582
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3117886394
Short name T512
Test name
Test status
Simulation time 156072255 ps
CPU time 0.98 seconds
Started Jul 11 05:26:41 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 196652 kb
Host smart-05d01bee-af71-4b14-bdb6-69dafb1b156f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117886394 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3117886394
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1585881561
Short name T576
Test name
Test status
Simulation time 24668828 ps
CPU time 0.57 seconds
Started Jul 11 05:26:38 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 182256 kb
Host smart-12b54205-db54-4918-bfe5-823139283958
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585881561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1585881561
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.2191710233
Short name T546
Test name
Test status
Simulation time 27440774 ps
CPU time 0.56 seconds
Started Jul 11 05:26:40 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 182112 kb
Host smart-cd6cebf5-ac0a-4694-a26d-33aaca7b30b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191710233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.2191710233
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.32801101
Short name T558
Test name
Test status
Simulation time 123192662 ps
CPU time 0.91 seconds
Started Jul 11 05:26:38 PM PDT 24
Finished Jul 11 05:26:43 PM PDT 24
Peak memory 195708 kb
Host smart-2f834064-889b-4600-88ab-ca448a626c77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32801101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.32801101
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4153050685
Short name T520
Test name
Test status
Simulation time 849111114 ps
CPU time 1.25 seconds
Started Jul 11 05:26:39 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 182772 kb
Host smart-cfe0bb1c-a0dd-496b-bf1b-73e397cf11eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153050685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4153050685
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.1125533134
Short name T575
Test name
Test status
Simulation time 203985588 ps
CPU time 0.72 seconds
Started Jul 11 05:26:38 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 194276 kb
Host smart-f26772a1-9455-485c-bf6a-13ba21540b4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125533134 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.1125533134
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.2028390656
Short name T565
Test name
Test status
Simulation time 48238890 ps
CPU time 0.56 seconds
Started Jul 11 05:26:40 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 182264 kb
Host smart-2b322488-01e4-4a27-af4b-60b2a673ba53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028390656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.2028390656
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.218090560
Short name T566
Test name
Test status
Simulation time 13130534 ps
CPU time 0.61 seconds
Started Jul 11 05:26:41 PM PDT 24
Finished Jul 11 05:26:45 PM PDT 24
Peak memory 182188 kb
Host smart-b65590aa-b275-4aac-a1b1-ae0cad4e6793
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218090560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.218090560
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.3998565921
Short name T535
Test name
Test status
Simulation time 217031607 ps
CPU time 0.87 seconds
Started Jul 11 05:26:38 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 194032 kb
Host smart-43db9ed0-c82a-4ed1-92f5-8222c8718c05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998565921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.3998565921
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1537782645
Short name T515
Test name
Test status
Simulation time 156357163 ps
CPU time 1.62 seconds
Started Jul 11 05:26:38 PM PDT 24
Finished Jul 11 05:26:43 PM PDT 24
Peak memory 196992 kb
Host smart-227a25d9-a084-415b-b419-f3901de596c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537782645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1537782645
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.4268929424
Short name T107
Test name
Test status
Simulation time 309783987 ps
CPU time 1.45 seconds
Started Jul 11 05:26:37 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 194872 kb
Host smart-a2b2648e-bda0-4156-addb-8647b2b4b285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268929424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.4268929424
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3528442802
Short name T52
Test name
Test status
Simulation time 195312749 ps
CPU time 0.89 seconds
Started Jul 11 05:26:48 PM PDT 24
Finished Jul 11 05:26:50 PM PDT 24
Peak memory 196672 kb
Host smart-6281a3ab-16dd-4795-b4d6-7cf80c94c853
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528442802 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3528442802
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3583943900
Short name T530
Test name
Test status
Simulation time 15403247 ps
CPU time 0.6 seconds
Started Jul 11 05:26:38 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 182248 kb
Host smart-ebc981a9-9b9d-440b-8332-db7029e6affa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583943900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3583943900
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2971661355
Short name T516
Test name
Test status
Simulation time 24226309 ps
CPU time 0.54 seconds
Started Jul 11 05:26:48 PM PDT 24
Finished Jul 11 05:26:50 PM PDT 24
Peak memory 182152 kb
Host smart-40df29c3-63a8-4190-b438-fbf7395658a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971661355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2971661355
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.660874757
Short name T89
Test name
Test status
Simulation time 13463221 ps
CPU time 0.65 seconds
Started Jul 11 05:26:38 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 191080 kb
Host smart-6766332c-e405-4591-ab47-74ddd6bf2af6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660874757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.660874757
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2928873882
Short name T455
Test name
Test status
Simulation time 32589816 ps
CPU time 1.54 seconds
Started Jul 11 05:26:39 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 196972 kb
Host smart-cc0d4eb2-7f71-4cb5-b68c-2df6ff402fed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928873882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2928873882
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.4156666765
Short name T30
Test name
Test status
Simulation time 120421876 ps
CPU time 0.81 seconds
Started Jul 11 05:26:40 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 193016 kb
Host smart-b7c84a2e-3a5a-4e10-a286-2763d7ac353a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156666765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.4156666765
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.992974138
Short name T474
Test name
Test status
Simulation time 78089220 ps
CPU time 1.04 seconds
Started Jul 11 05:26:40 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 196840 kb
Host smart-d610bb39-e305-458f-9e44-d4457ddb917d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992974138 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.992974138
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.2926244790
Short name T98
Test name
Test status
Simulation time 35506281 ps
CPU time 0.57 seconds
Started Jul 11 05:26:40 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 182188 kb
Host smart-ef816888-4aca-48a8-aabf-eaabf4bd841c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926244790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.2926244790
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.791739687
Short name T559
Test name
Test status
Simulation time 36646641 ps
CPU time 0.54 seconds
Started Jul 11 05:26:40 PM PDT 24
Finished Jul 11 05:26:44 PM PDT 24
Peak memory 181832 kb
Host smart-b82951ff-0870-4693-b2d1-e54988e9af4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791739687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.791739687
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.1026291715
Short name T100
Test name
Test status
Simulation time 53646131 ps
CPU time 0.62 seconds
Started Jul 11 05:26:38 PM PDT 24
Finished Jul 11 05:26:42 PM PDT 24
Peak memory 191056 kb
Host smart-1dee648b-32b7-495b-ad53-d765393f66db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026291715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.1026291715
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2334426958
Short name T522
Test name
Test status
Simulation time 287661725 ps
CPU time 1.55 seconds
Started Jul 11 05:26:48 PM PDT 24
Finished Jul 11 05:26:51 PM PDT 24
Peak memory 197060 kb
Host smart-3c9dcbd1-d1b2-4133-83cd-47011f7fb914
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334426958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2334426958
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3210767634
Short name T463
Test name
Test status
Simulation time 455076394 ps
CPU time 0.8 seconds
Started Jul 11 05:26:39 PM PDT 24
Finished Jul 11 05:26:43 PM PDT 24
Peak memory 182652 kb
Host smart-0c0f6488-bba6-4feb-a1cb-e32fb513269d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210767634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3210767634
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3972076502
Short name T496
Test name
Test status
Simulation time 18524482 ps
CPU time 0.86 seconds
Started Jul 11 05:26:46 PM PDT 24
Finished Jul 11 05:26:49 PM PDT 24
Peak memory 196580 kb
Host smart-4d29ca3b-2af3-4954-a308-052072ebcaaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972076502 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3972076502
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.580431943
Short name T493
Test name
Test status
Simulation time 43734557 ps
CPU time 0.53 seconds
Started Jul 11 05:26:43 PM PDT 24
Finished Jul 11 05:26:46 PM PDT 24
Peak memory 182212 kb
Host smart-6ffffdf5-6dda-4d08-a8b3-2b9aa2212b92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580431943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.580431943
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.275731047
Short name T487
Test name
Test status
Simulation time 16027787 ps
CPU time 0.59 seconds
Started Jul 11 05:26:47 PM PDT 24
Finished Jul 11 05:26:49 PM PDT 24
Peak memory 182108 kb
Host smart-90a65279-c763-48d7-aa24-c724168eb895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275731047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.275731047
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.738376316
Short name T88
Test name
Test status
Simulation time 59140000 ps
CPU time 0.81 seconds
Started Jul 11 05:26:43 PM PDT 24
Finished Jul 11 05:26:46 PM PDT 24
Peak memory 192988 kb
Host smart-25370431-ec98-474e-98e5-f47ee25c94a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738376316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.738376316
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.3577832108
Short name T483
Test name
Test status
Simulation time 405021446 ps
CPU time 1.24 seconds
Started Jul 11 05:26:44 PM PDT 24
Finished Jul 11 05:26:48 PM PDT 24
Peak memory 196964 kb
Host smart-a7d2c090-58bb-4644-8fe0-4394b8c06043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577832108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.3577832108
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.776391207
Short name T552
Test name
Test status
Simulation time 340316135 ps
CPU time 1.33 seconds
Started Jul 11 05:26:44 PM PDT 24
Finished Jul 11 05:26:48 PM PDT 24
Peak memory 182896 kb
Host smart-fc124c9b-9a68-43e7-88fb-c81ea83156ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776391207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.776391207
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3720006094
Short name T460
Test name
Test status
Simulation time 98892044 ps
CPU time 0.63 seconds
Started Jul 11 05:26:44 PM PDT 24
Finished Jul 11 05:26:47 PM PDT 24
Peak memory 192668 kb
Host smart-28fd2476-6899-4e74-8775-34065f28c03d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720006094 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3720006094
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.4049240047
Short name T476
Test name
Test status
Simulation time 65262208 ps
CPU time 0.59 seconds
Started Jul 11 05:26:49 PM PDT 24
Finished Jul 11 05:26:51 PM PDT 24
Peak memory 182032 kb
Host smart-69081259-45a5-4389-b39f-8f92a5216413
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049240047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.4049240047
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.851076631
Short name T544
Test name
Test status
Simulation time 11204359 ps
CPU time 0.58 seconds
Started Jul 11 05:26:45 PM PDT 24
Finished Jul 11 05:26:48 PM PDT 24
Peak memory 181716 kb
Host smart-189811c9-b1e9-462d-97a7-15dec578287c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851076631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.851076631
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.913563120
Short name T83
Test name
Test status
Simulation time 39200403 ps
CPU time 0.9 seconds
Started Jul 11 05:26:45 PM PDT 24
Finished Jul 11 05:26:48 PM PDT 24
Peak memory 190400 kb
Host smart-afcdc00c-ab8b-488b-8f0b-8dc135884666
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913563120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.913563120
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2008893652
Short name T471
Test name
Test status
Simulation time 109439936 ps
CPU time 1.64 seconds
Started Jul 11 05:26:44 PM PDT 24
Finished Jul 11 05:26:48 PM PDT 24
Peak memory 197056 kb
Host smart-9a5c63ba-1a2d-4945-9870-d25af71c55af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008893652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2008893652
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3101728203
Short name T561
Test name
Test status
Simulation time 97495965 ps
CPU time 0.86 seconds
Started Jul 11 05:26:45 PM PDT 24
Finished Jul 11 05:26:48 PM PDT 24
Peak memory 193484 kb
Host smart-24143986-d995-4aa2-b6f1-1383289af55c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101728203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3101728203
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1051949036
Short name T513
Test name
Test status
Simulation time 91225772 ps
CPU time 0.72 seconds
Started Jul 11 05:26:45 PM PDT 24
Finished Jul 11 05:26:48 PM PDT 24
Peak memory 194416 kb
Host smart-c48aae2d-0fb6-4e0c-b867-6c0f3187515f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051949036 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1051949036
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.473332844
Short name T92
Test name
Test status
Simulation time 16249312 ps
CPU time 0.59 seconds
Started Jul 11 05:26:48 PM PDT 24
Finished Jul 11 05:26:50 PM PDT 24
Peak memory 182244 kb
Host smart-b2f7bffa-7d23-4931-94f0-3f006ded37f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473332844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.473332844
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1503140276
Short name T570
Test name
Test status
Simulation time 15301388 ps
CPU time 0.56 seconds
Started Jul 11 05:26:49 PM PDT 24
Finished Jul 11 05:26:51 PM PDT 24
Peak memory 182112 kb
Host smart-69e724d8-9493-49f6-b296-c3a3a0011a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503140276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1503140276
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.681708898
Short name T101
Test name
Test status
Simulation time 19897253 ps
CPU time 0.73 seconds
Started Jul 11 05:26:49 PM PDT 24
Finished Jul 11 05:26:51 PM PDT 24
Peak memory 191140 kb
Host smart-81a623d7-9ed0-485d-8a5b-9ebc72f7a739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681708898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.681708898
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3530811285
Short name T452
Test name
Test status
Simulation time 559965945 ps
CPU time 2.75 seconds
Started Jul 11 05:26:46 PM PDT 24
Finished Jul 11 05:26:51 PM PDT 24
Peak memory 196956 kb
Host smart-58d92c6b-0e4c-451f-9d80-b2cec8ce3e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530811285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3530811285
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1709284332
Short name T469
Test name
Test status
Simulation time 86906124 ps
CPU time 1.17 seconds
Started Jul 11 05:26:43 PM PDT 24
Finished Jul 11 05:26:47 PM PDT 24
Peak memory 194684 kb
Host smart-af85b50b-45fb-4b6d-86ed-1bf65044cced
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709284332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1709284332
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.887048333
Short name T541
Test name
Test status
Simulation time 25035278 ps
CPU time 1.04 seconds
Started Jul 11 05:26:51 PM PDT 24
Finished Jul 11 05:26:54 PM PDT 24
Peak memory 196804 kb
Host smart-2cd3930c-e639-46cd-82fe-f22eeca9ac5e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887048333 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.887048333
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.419453269
Short name T468
Test name
Test status
Simulation time 13528463 ps
CPU time 0.63 seconds
Started Jul 11 05:26:43 PM PDT 24
Finished Jul 11 05:26:46 PM PDT 24
Peak memory 182216 kb
Host smart-da12fef0-4997-40cc-830f-353a636f343b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419453269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.419453269
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4031782566
Short name T491
Test name
Test status
Simulation time 125394418 ps
CPU time 0.56 seconds
Started Jul 11 05:26:45 PM PDT 24
Finished Jul 11 05:26:48 PM PDT 24
Peak memory 182088 kb
Host smart-e17bc8c2-cddb-4063-92a5-43aa03174feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031782566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4031782566
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.4149462941
Short name T527
Test name
Test status
Simulation time 19987478 ps
CPU time 0.76 seconds
Started Jul 11 05:26:43 PM PDT 24
Finished Jul 11 05:26:46 PM PDT 24
Peak memory 191164 kb
Host smart-d7017967-e025-48ca-9e54-fce6507eccd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149462941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.4149462941
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1091377147
Short name T478
Test name
Test status
Simulation time 280179591 ps
CPU time 1.97 seconds
Started Jul 11 05:26:49 PM PDT 24
Finished Jul 11 05:26:52 PM PDT 24
Peak memory 196776 kb
Host smart-aac8fd78-adb4-4db4-93fb-482f463551e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091377147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1091377147
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3491665077
Short name T470
Test name
Test status
Simulation time 159119398 ps
CPU time 0.86 seconds
Started Jul 11 05:26:45 PM PDT 24
Finished Jul 11 05:26:48 PM PDT 24
Peak memory 193368 kb
Host smart-ce700689-b0cb-4bd9-a522-062c0cb21759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491665077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3491665077
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.746205241
Short name T94
Test name
Test status
Simulation time 34168798 ps
CPU time 0.66 seconds
Started Jul 11 05:26:18 PM PDT 24
Finished Jul 11 05:26:21 PM PDT 24
Peak memory 191484 kb
Host smart-922b9d88-0006-4cb8-b5b2-863ef3770801
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746205241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alias
ing.746205241
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3763090327
Short name T72
Test name
Test status
Simulation time 453763685 ps
CPU time 1.55 seconds
Started Jul 11 05:26:19 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 190660 kb
Host smart-ce0c5fdb-b70c-44d2-9680-803baa52b8d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763090327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3763090327
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.380215776
Short name T97
Test name
Test status
Simulation time 28430171 ps
CPU time 0.57 seconds
Started Jul 11 05:26:18 PM PDT 24
Finished Jul 11 05:26:20 PM PDT 24
Peak memory 182216 kb
Host smart-d517d3a7-9589-4f9a-8724-cdeb4106eecb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380215776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.380215776
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3082488787
Short name T577
Test name
Test status
Simulation time 37519794 ps
CPU time 0.61 seconds
Started Jul 11 05:26:23 PM PDT 24
Finished Jul 11 05:26:29 PM PDT 24
Peak memory 193132 kb
Host smart-5fe60982-c381-445c-bad9-170f22e4a76c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082488787 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3082488787
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3082625859
Short name T533
Test name
Test status
Simulation time 14702314 ps
CPU time 0.58 seconds
Started Jul 11 05:26:22 PM PDT 24
Finished Jul 11 05:26:27 PM PDT 24
Peak memory 182180 kb
Host smart-1eb72c4f-1bf6-4a48-9db6-72268e591dc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082625859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3082625859
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1239391113
Short name T555
Test name
Test status
Simulation time 19983491 ps
CPU time 0.58 seconds
Started Jul 11 05:26:21 PM PDT 24
Finished Jul 11 05:26:26 PM PDT 24
Peak memory 182408 kb
Host smart-9a7a1ec5-37ba-4034-ac7a-ba9f3388bf74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239391113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1239391113
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.1410376049
Short name T529
Test name
Test status
Simulation time 66686374 ps
CPU time 0.6 seconds
Started Jul 11 05:26:22 PM PDT 24
Finished Jul 11 05:26:26 PM PDT 24
Peak memory 191476 kb
Host smart-06018385-bfc2-4e50-ab93-e530318d59c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410376049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.1410376049
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1358791161
Short name T484
Test name
Test status
Simulation time 133112989 ps
CPU time 1.45 seconds
Started Jul 11 05:26:21 PM PDT 24
Finished Jul 11 05:26:26 PM PDT 24
Peak memory 197264 kb
Host smart-3b076045-9c62-437d-bd9b-cb06941e82be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358791161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1358791161
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.185238230
Short name T567
Test name
Test status
Simulation time 193478553 ps
CPU time 1.39 seconds
Started Jul 11 05:26:19 PM PDT 24
Finished Jul 11 05:26:24 PM PDT 24
Peak memory 194732 kb
Host smart-1568c979-fdb3-4551-9407-2fd2658d2ee0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185238230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.185238230
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1602249672
Short name T528
Test name
Test status
Simulation time 64971222 ps
CPU time 0.57 seconds
Started Jul 11 05:26:53 PM PDT 24
Finished Jul 11 05:26:55 PM PDT 24
Peak memory 182068 kb
Host smart-7daac8d2-ac76-4fbc-843c-8484f9e0d9a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602249672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1602249672
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2222268201
Short name T488
Test name
Test status
Simulation time 14361956 ps
CPU time 0.56 seconds
Started Jul 11 05:26:54 PM PDT 24
Finished Jul 11 05:26:56 PM PDT 24
Peak memory 182152 kb
Host smart-c61d6549-f9b3-45dd-a8be-ee3d8ef1eb45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222268201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2222268201
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3275195780
Short name T456
Test name
Test status
Simulation time 14299088 ps
CPU time 0.59 seconds
Started Jul 11 05:26:55 PM PDT 24
Finished Jul 11 05:26:57 PM PDT 24
Peak memory 182188 kb
Host smart-fb9b524f-54c2-4ce7-acde-6adfb82b0dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275195780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3275195780
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1848590703
Short name T451
Test name
Test status
Simulation time 11177348 ps
CPU time 0.59 seconds
Started Jul 11 05:26:58 PM PDT 24
Finished Jul 11 05:27:00 PM PDT 24
Peak memory 182164 kb
Host smart-05c3b8d0-e0fc-4625-ad00-c562a54ab400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848590703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1848590703
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.799583424
Short name T505
Test name
Test status
Simulation time 37029397 ps
CPU time 0.53 seconds
Started Jul 11 05:26:51 PM PDT 24
Finished Jul 11 05:26:53 PM PDT 24
Peak memory 182172 kb
Host smart-12e92cb2-e752-49ad-b451-121593d0852a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799583424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.799583424
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2765968196
Short name T479
Test name
Test status
Simulation time 38253565 ps
CPU time 0.6 seconds
Started Jul 11 05:26:52 PM PDT 24
Finished Jul 11 05:26:55 PM PDT 24
Peak memory 182016 kb
Host smart-4da696f0-9094-4ce5-9072-3c89573643da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765968196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2765968196
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.186747060
Short name T458
Test name
Test status
Simulation time 32331244 ps
CPU time 0.55 seconds
Started Jul 11 05:26:57 PM PDT 24
Finished Jul 11 05:26:58 PM PDT 24
Peak memory 181768 kb
Host smart-8cb87856-8bb9-43fd-81fc-c0e50cde1571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186747060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.186747060
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.93260196
Short name T519
Test name
Test status
Simulation time 28361734 ps
CPU time 0.6 seconds
Started Jul 11 05:26:50 PM PDT 24
Finished Jul 11 05:26:52 PM PDT 24
Peak memory 182176 kb
Host smart-6e06a0bb-2276-466d-bfef-37741ad825f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93260196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.93260196
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1076712588
Short name T489
Test name
Test status
Simulation time 37821137 ps
CPU time 0.6 seconds
Started Jul 11 05:26:51 PM PDT 24
Finished Jul 11 05:26:54 PM PDT 24
Peak memory 182104 kb
Host smart-c1155756-c238-49f0-bf87-7a1d05d4bdd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076712588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1076712588
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4252091221
Short name T482
Test name
Test status
Simulation time 44953029 ps
CPU time 0.52 seconds
Started Jul 11 05:26:51 PM PDT 24
Finished Jul 11 05:26:53 PM PDT 24
Peak memory 182064 kb
Host smart-08279bfb-886a-4e00-bcef-df0e3537f6cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252091221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4252091221
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3047978977
Short name T64
Test name
Test status
Simulation time 19417643 ps
CPU time 0.67 seconds
Started Jul 11 05:26:17 PM PDT 24
Finished Jul 11 05:26:18 PM PDT 24
Peak memory 182216 kb
Host smart-60623ed4-1791-4c21-b5c4-4db8d20e1757
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047978977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3047978977
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2651431530
Short name T497
Test name
Test status
Simulation time 188215871 ps
CPU time 2.41 seconds
Started Jul 11 05:26:23 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 190612 kb
Host smart-918bf04f-ce3b-4ad9-8107-184cb5b55e8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651431530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2651431530
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3544872605
Short name T33
Test name
Test status
Simulation time 52473559 ps
CPU time 0.55 seconds
Started Jul 11 05:26:23 PM PDT 24
Finished Jul 11 05:26:29 PM PDT 24
Peak memory 182244 kb
Host smart-b51de0f0-d41d-4c6b-8114-e233f4c3d64f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544872605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3544872605
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3581227579
Short name T457
Test name
Test status
Simulation time 16173502 ps
CPU time 0.67 seconds
Started Jul 11 05:26:21 PM PDT 24
Finished Jul 11 05:26:25 PM PDT 24
Peak memory 193628 kb
Host smart-9f252d1a-ae13-4c1a-a28c-3f960ad5b894
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581227579 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3581227579
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1405022091
Short name T536
Test name
Test status
Simulation time 23367503 ps
CPU time 0.54 seconds
Started Jul 11 05:26:22 PM PDT 24
Finished Jul 11 05:26:27 PM PDT 24
Peak memory 182248 kb
Host smart-eee2abc5-ade0-489a-86ec-4e4acc12ac2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405022091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1405022091
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.3847754261
Short name T467
Test name
Test status
Simulation time 25518459 ps
CPU time 0.56 seconds
Started Jul 11 05:26:22 PM PDT 24
Finished Jul 11 05:26:27 PM PDT 24
Peak memory 182020 kb
Host smart-46030978-a839-4729-b1e2-db347661453f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847754261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.3847754261
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1924271816
Short name T574
Test name
Test status
Simulation time 17784996 ps
CPU time 0.82 seconds
Started Jul 11 05:26:19 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 192856 kb
Host smart-f7c9dcdd-c0f7-40f7-b318-e795ed5534a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924271816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1924271816
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3364510181
Short name T510
Test name
Test status
Simulation time 23336246 ps
CPU time 1.07 seconds
Started Jul 11 05:26:23 PM PDT 24
Finished Jul 11 05:26:28 PM PDT 24
Peak memory 190604 kb
Host smart-1b3ad1eb-81e4-4e59-8ae4-34e89cd30902
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364510181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3364510181
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3795260775
Short name T461
Test name
Test status
Simulation time 177723367 ps
CPU time 1.11 seconds
Started Jul 11 05:26:23 PM PDT 24
Finished Jul 11 05:26:29 PM PDT 24
Peak memory 194712 kb
Host smart-e5b135a4-3f75-45e9-a8f9-6e82dae8fc28
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795260775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3795260775
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.948087928
Short name T542
Test name
Test status
Simulation time 17603132 ps
CPU time 0.58 seconds
Started Jul 11 05:26:51 PM PDT 24
Finished Jul 11 05:26:53 PM PDT 24
Peak memory 182044 kb
Host smart-e330ddad-17e3-473a-965b-d866045d7087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948087928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.948087928
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.1772084916
Short name T492
Test name
Test status
Simulation time 14289797 ps
CPU time 0.58 seconds
Started Jul 11 05:26:56 PM PDT 24
Finished Jul 11 05:26:58 PM PDT 24
Peak memory 182088 kb
Host smart-d7a1890f-fb14-4ab7-bb8b-67656dfa1daa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772084916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.1772084916
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.660874711
Short name T511
Test name
Test status
Simulation time 47143832 ps
CPU time 0.59 seconds
Started Jul 11 05:26:52 PM PDT 24
Finished Jul 11 05:26:54 PM PDT 24
Peak memory 182164 kb
Host smart-a4393dd7-fa90-4426-b460-21625f616238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660874711 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.660874711
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3395123623
Short name T573
Test name
Test status
Simulation time 14761226 ps
CPU time 0.55 seconds
Started Jul 11 05:26:52 PM PDT 24
Finished Jul 11 05:26:54 PM PDT 24
Peak memory 182180 kb
Host smart-03556d2d-a801-45f3-b360-8bf787d756fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395123623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3395123623
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3633906896
Short name T464
Test name
Test status
Simulation time 13679344 ps
CPU time 0.59 seconds
Started Jul 11 05:26:51 PM PDT 24
Finished Jul 11 05:26:54 PM PDT 24
Peak memory 182180 kb
Host smart-565b63eb-4196-48f8-a9f4-63ef7878f169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633906896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3633906896
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3723462537
Short name T554
Test name
Test status
Simulation time 31117119 ps
CPU time 0.52 seconds
Started Jul 11 05:26:52 PM PDT 24
Finished Jul 11 05:26:54 PM PDT 24
Peak memory 181572 kb
Host smart-f8ed4ce8-d891-48a5-aa9a-ee7ebaa45af1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723462537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3723462537
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1470340515
Short name T475
Test name
Test status
Simulation time 21818170 ps
CPU time 0.55 seconds
Started Jul 11 05:26:56 PM PDT 24
Finished Jul 11 05:26:58 PM PDT 24
Peak memory 181760 kb
Host smart-f617ea49-ba1c-4a3c-a14d-bcff1031441b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470340515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1470340515
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1716641804
Short name T517
Test name
Test status
Simulation time 41656649 ps
CPU time 0.57 seconds
Started Jul 11 05:26:56 PM PDT 24
Finished Jul 11 05:26:58 PM PDT 24
Peak memory 182052 kb
Host smart-70ea07e0-59bf-4148-be84-c2889b6d201e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716641804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1716641804
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.3518956887
Short name T532
Test name
Test status
Simulation time 23361158 ps
CPU time 0.57 seconds
Started Jul 11 05:26:55 PM PDT 24
Finished Jul 11 05:26:56 PM PDT 24
Peak memory 182188 kb
Host smart-83ce19bf-d744-4ce3-a602-7ddcfc025dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518956887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.3518956887
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.380375597
Short name T514
Test name
Test status
Simulation time 67451830 ps
CPU time 0.53 seconds
Started Jul 11 05:26:51 PM PDT 24
Finished Jul 11 05:26:53 PM PDT 24
Peak memory 182012 kb
Host smart-140faded-231a-4ea6-a1ac-7c0f048beba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380375597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.380375597
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3542706630
Short name T485
Test name
Test status
Simulation time 56682406 ps
CPU time 0.67 seconds
Started Jul 11 05:26:26 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 191488 kb
Host smart-b9ae267f-affc-4cb1-9ca1-0fba54881115
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542706630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3542706630
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1346093953
Short name T96
Test name
Test status
Simulation time 106743138 ps
CPU time 0.58 seconds
Started Jul 11 05:26:24 PM PDT 24
Finished Jul 11 05:26:30 PM PDT 24
Peak memory 182216 kb
Host smart-49214a3a-1159-466d-82c1-e17dfe40e8f5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346093953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1346093953
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.950182470
Short name T564
Test name
Test status
Simulation time 33552444 ps
CPU time 0.91 seconds
Started Jul 11 05:26:33 PM PDT 24
Finished Jul 11 05:26:38 PM PDT 24
Peak memory 196420 kb
Host smart-cb4f0c53-d527-4c68-93b6-b6e10a27f321
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950182470 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.950182470
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.3960547217
Short name T498
Test name
Test status
Simulation time 83150393 ps
CPU time 0.57 seconds
Started Jul 11 05:26:22 PM PDT 24
Finished Jul 11 05:26:27 PM PDT 24
Peak memory 182236 kb
Host smart-e4b81ae6-0a19-433d-98ca-29daa1addc13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960547217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.3960547217
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3651099518
Short name T521
Test name
Test status
Simulation time 38353469 ps
CPU time 0.54 seconds
Started Jul 11 05:26:23 PM PDT 24
Finished Jul 11 05:26:29 PM PDT 24
Peak memory 181772 kb
Host smart-174f50c2-d753-4c2e-93fa-e8961c717ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651099518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3651099518
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2776700584
Short name T103
Test name
Test status
Simulation time 78763402 ps
CPU time 0.87 seconds
Started Jul 11 05:26:24 PM PDT 24
Finished Jul 11 05:26:30 PM PDT 24
Peak memory 194260 kb
Host smart-8dcb0640-101d-4a9d-abf0-e8e3886758fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776700584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2776700584
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.2787192562
Short name T551
Test name
Test status
Simulation time 80267297 ps
CPU time 1.77 seconds
Started Jul 11 05:26:18 PM PDT 24
Finished Jul 11 05:26:23 PM PDT 24
Peak memory 197000 kb
Host smart-8cefee57-58e5-4699-ba41-889725c0a5e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787192562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.2787192562
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3169894566
Short name T557
Test name
Test status
Simulation time 249821157 ps
CPU time 0.87 seconds
Started Jul 11 05:26:23 PM PDT 24
Finished Jul 11 05:26:29 PM PDT 24
Peak memory 193312 kb
Host smart-213202ca-0c08-4afa-a3b9-4717a1b176df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169894566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3169894566
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.4293199851
Short name T523
Test name
Test status
Simulation time 16465680 ps
CPU time 0.59 seconds
Started Jul 11 05:26:52 PM PDT 24
Finished Jul 11 05:26:54 PM PDT 24
Peak memory 182108 kb
Host smart-e50f883e-f604-4162-86d3-761064bc92ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293199851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.4293199851
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3730300851
Short name T462
Test name
Test status
Simulation time 78488138 ps
CPU time 0.61 seconds
Started Jul 11 05:26:58 PM PDT 24
Finished Jul 11 05:27:00 PM PDT 24
Peak memory 182132 kb
Host smart-d744da5b-1e7d-44a8-9d03-dc41b229a86f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730300851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3730300851
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.1397782461
Short name T465
Test name
Test status
Simulation time 14936978 ps
CPU time 0.56 seconds
Started Jul 11 05:26:54 PM PDT 24
Finished Jul 11 05:26:56 PM PDT 24
Peak memory 181828 kb
Host smart-bc18d166-5df6-4c06-bd9c-588cffe69245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397782461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.1397782461
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3826495332
Short name T534
Test name
Test status
Simulation time 17195860 ps
CPU time 0.57 seconds
Started Jul 11 05:26:50 PM PDT 24
Finished Jul 11 05:26:53 PM PDT 24
Peak memory 182072 kb
Host smart-7fd01a03-739d-4a1b-b835-04d73ee35f23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826495332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3826495332
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.4091296180
Short name T550
Test name
Test status
Simulation time 47226274 ps
CPU time 0.62 seconds
Started Jul 11 05:26:57 PM PDT 24
Finished Jul 11 05:26:59 PM PDT 24
Peak memory 182116 kb
Host smart-26ff9f1f-79cc-4dc6-8cbd-ed1d15be3dbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091296180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.4091296180
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.1631183930
Short name T548
Test name
Test status
Simulation time 18171742 ps
CPU time 0.58 seconds
Started Jul 11 05:27:01 PM PDT 24
Finished Jul 11 05:27:03 PM PDT 24
Peak memory 182120 kb
Host smart-4bdffbbe-d63f-4346-9b23-8554dca5daca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631183930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.1631183930
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2866219961
Short name T538
Test name
Test status
Simulation time 27980691 ps
CPU time 0.54 seconds
Started Jul 11 05:26:57 PM PDT 24
Finished Jul 11 05:26:59 PM PDT 24
Peak memory 182124 kb
Host smart-4f0841a3-baf7-430b-8b65-51b0fa7b2208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866219961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2866219961
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2979458786
Short name T481
Test name
Test status
Simulation time 36987666 ps
CPU time 0.57 seconds
Started Jul 11 05:27:00 PM PDT 24
Finished Jul 11 05:27:02 PM PDT 24
Peak memory 182164 kb
Host smart-bf82d8f4-92f7-49ea-ab18-11dbbbe7bd41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979458786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2979458786
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3996497343
Short name T525
Test name
Test status
Simulation time 32042199 ps
CPU time 0.55 seconds
Started Jul 11 05:26:58 PM PDT 24
Finished Jul 11 05:27:00 PM PDT 24
Peak memory 182084 kb
Host smart-9246022e-d3cf-47bb-927a-fe1a3978057d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996497343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3996497343
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.110943032
Short name T549
Test name
Test status
Simulation time 14144297 ps
CPU time 0.59 seconds
Started Jul 11 05:27:00 PM PDT 24
Finished Jul 11 05:27:03 PM PDT 24
Peak memory 182136 kb
Host smart-c6323d9d-47a7-4266-a029-ebdd6c72488a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110943032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.110943032
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.111637174
Short name T553
Test name
Test status
Simulation time 21646287 ps
CPU time 1 seconds
Started Jul 11 05:26:25 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 196912 kb
Host smart-3dc11661-c6bf-4ef8-ba6e-ead61f248682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111637174 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.111637174
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.602395746
Short name T531
Test name
Test status
Simulation time 28806127 ps
CPU time 0.53 seconds
Started Jul 11 05:26:26 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 182020 kb
Host smart-3b0db71d-1fd1-49a7-a72f-8286a19be6c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602395746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.602395746
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4094904613
Short name T540
Test name
Test status
Simulation time 46413680 ps
CPU time 0.54 seconds
Started Jul 11 05:26:26 PM PDT 24
Finished Jul 11 05:26:32 PM PDT 24
Peak memory 182152 kb
Host smart-422a9cfa-69c1-434f-bd0b-52c2a8635d8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094904613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4094904613
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3483343871
Short name T501
Test name
Test status
Simulation time 67030527 ps
CPU time 0.6 seconds
Started Jul 11 05:26:25 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 190964 kb
Host smart-ce6ea249-7c7a-44a2-860e-d94c3edb7827
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483343871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3483343871
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2120154666
Short name T472
Test name
Test status
Simulation time 367420051 ps
CPU time 2.15 seconds
Started Jul 11 05:26:31 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 196572 kb
Host smart-b059c237-a732-4726-9a56-8361fdd143e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120154666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2120154666
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3760686752
Short name T105
Test name
Test status
Simulation time 88799954 ps
CPU time 0.82 seconds
Started Jul 11 05:26:26 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 182556 kb
Host smart-3d38c757-bdaa-4d7b-86fa-1ae9104825fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760686752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3760686752
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.568136707
Short name T509
Test name
Test status
Simulation time 21884950 ps
CPU time 0.95 seconds
Started Jul 11 05:26:26 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 196660 kb
Host smart-01be5e11-1c77-44f6-aed1-7630fc772031
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568136707 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.568136707
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2667055808
Short name T453
Test name
Test status
Simulation time 17186830 ps
CPU time 0.59 seconds
Started Jul 11 05:26:26 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 182268 kb
Host smart-46fe3b1c-3d4d-4688-acf3-12703acfeec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667055808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2667055808
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1095094107
Short name T547
Test name
Test status
Simulation time 17541944 ps
CPU time 0.6 seconds
Started Jul 11 05:26:26 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 182188 kb
Host smart-e35b8ef2-61cd-487d-97bc-a1dd0f0fab9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095094107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1095094107
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.658787667
Short name T500
Test name
Test status
Simulation time 21562981 ps
CPU time 0.64 seconds
Started Jul 11 05:26:25 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 191452 kb
Host smart-ecf3fcf6-ba30-4645-b1fe-6f47c584fa96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658787667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.658787667
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.1237164266
Short name T543
Test name
Test status
Simulation time 117703370 ps
CPU time 3.03 seconds
Started Jul 11 05:26:33 PM PDT 24
Finished Jul 11 05:26:40 PM PDT 24
Peak memory 197036 kb
Host smart-8661692f-5cd1-43fa-88c0-bb5605885aa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237164266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.1237164266
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2005522719
Short name T54
Test name
Test status
Simulation time 49722935 ps
CPU time 0.85 seconds
Started Jul 11 05:26:29 PM PDT 24
Finished Jul 11 05:26:33 PM PDT 24
Peak memory 193064 kb
Host smart-e30fa13c-414d-4238-924c-e7b0861f547e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005522719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2005522719
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1563564611
Short name T486
Test name
Test status
Simulation time 41917739 ps
CPU time 1.2 seconds
Started Jul 11 05:26:31 PM PDT 24
Finished Jul 11 05:26:36 PM PDT 24
Peak memory 196692 kb
Host smart-a36bb3ee-7ba3-44c7-902c-706d4488216f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563564611 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1563564611
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1151431994
Short name T454
Test name
Test status
Simulation time 166466236 ps
CPU time 0.57 seconds
Started Jul 11 05:26:24 PM PDT 24
Finished Jul 11 05:26:30 PM PDT 24
Peak memory 182180 kb
Host smart-e6637001-77ae-44b1-ae86-1463ddb7469b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151431994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1151431994
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3253963405
Short name T502
Test name
Test status
Simulation time 13527433 ps
CPU time 0.55 seconds
Started Jul 11 05:26:24 PM PDT 24
Finished Jul 11 05:26:30 PM PDT 24
Peak memory 182072 kb
Host smart-6f88adeb-ed88-4cd0-8b48-4be62fa272c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253963405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3253963405
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3163580739
Short name T102
Test name
Test status
Simulation time 31982902 ps
CPU time 0.8 seconds
Started Jul 11 05:26:25 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 192840 kb
Host smart-0ee3b0ba-624a-4de4-be1d-df24e64437e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163580739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3163580739
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1932483513
Short name T477
Test name
Test status
Simulation time 80714676 ps
CPU time 2.03 seconds
Started Jul 11 05:26:29 PM PDT 24
Finished Jul 11 05:26:34 PM PDT 24
Peak memory 190616 kb
Host smart-ce9be07b-f801-4abf-930b-267fc42f8f63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932483513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1932483513
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.600746382
Short name T32
Test name
Test status
Simulation time 50169224 ps
CPU time 0.79 seconds
Started Jul 11 05:26:25 PM PDT 24
Finished Jul 11 05:26:31 PM PDT 24
Peak memory 193016 kb
Host smart-a17cb86d-8886-4ab8-995a-617301cce762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600746382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_int
g_err.600746382
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2891371341
Short name T539
Test name
Test status
Simulation time 293257824 ps
CPU time 0.91 seconds
Started Jul 11 05:26:32 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 196440 kb
Host smart-ddccc2d3-7883-449b-ab00-57299a4455be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891371341 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2891371341
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1325289594
Short name T95
Test name
Test status
Simulation time 12336733 ps
CPU time 0.62 seconds
Started Jul 11 05:26:32 PM PDT 24
Finished Jul 11 05:26:36 PM PDT 24
Peak memory 182264 kb
Host smart-300c40da-6755-4b23-b2fd-75a37c0ac8bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325289594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1325289594
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.904586429
Short name T480
Test name
Test status
Simulation time 15440659 ps
CPU time 0.6 seconds
Started Jul 11 05:26:34 PM PDT 24
Finished Jul 11 05:26:38 PM PDT 24
Peak memory 182028 kb
Host smart-049afaa6-36e2-4773-9d10-067512e2ae79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904586429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.904586429
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1619150784
Short name T85
Test name
Test status
Simulation time 108785113 ps
CPU time 0.69 seconds
Started Jul 11 05:26:32 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 191776 kb
Host smart-485eb8f1-06d7-4df3-a715-6124aece2340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619150784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1619150784
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.2360069763
Short name T53
Test name
Test status
Simulation time 138315722 ps
CPU time 1.42 seconds
Started Jul 11 05:26:31 PM PDT 24
Finished Jul 11 05:26:36 PM PDT 24
Peak memory 196564 kb
Host smart-ed976bcf-a0ab-4f4f-a46d-22e68d024bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360069763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.2360069763
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3789517970
Short name T545
Test name
Test status
Simulation time 164687628 ps
CPU time 0.85 seconds
Started Jul 11 05:26:35 PM PDT 24
Finished Jul 11 05:26:40 PM PDT 24
Peak memory 182508 kb
Host smart-d2fb209e-0fb0-4366-8602-be1d6175362a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789517970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3789517970
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3795111475
Short name T518
Test name
Test status
Simulation time 15055248 ps
CPU time 0.7 seconds
Started Jul 11 05:26:32 PM PDT 24
Finished Jul 11 05:26:37 PM PDT 24
Peak memory 192572 kb
Host smart-004bb3ef-d101-49c0-b817-e1871141e541
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795111475 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3795111475
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3175387087
Short name T563
Test name
Test status
Simulation time 40638718 ps
CPU time 0.61 seconds
Started Jul 11 05:26:30 PM PDT 24
Finished Jul 11 05:26:35 PM PDT 24
Peak memory 191488 kb
Host smart-f5e82e45-cf1e-4bda-bc20-dcdb5d1b674c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175387087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3175387087
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.452857692
Short name T450
Test name
Test status
Simulation time 54290387 ps
CPU time 0.57 seconds
Started Jul 11 05:26:33 PM PDT 24
Finished Jul 11 05:26:38 PM PDT 24
Peak memory 182064 kb
Host smart-6a95b9f4-4568-468e-8212-b726170c178b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452857692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.452857692
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.722216670
Short name T507
Test name
Test status
Simulation time 47338487 ps
CPU time 0.63 seconds
Started Jul 11 05:26:31 PM PDT 24
Finished Jul 11 05:26:35 PM PDT 24
Peak memory 191620 kb
Host smart-3e9abfe8-661c-46b5-9fed-0fb86cc02921
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722216670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_tim
er_same_csr_outstanding.722216670
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.3045426162
Short name T504
Test name
Test status
Simulation time 86061249 ps
CPU time 1.06 seconds
Started Jul 11 05:26:33 PM PDT 24
Finished Jul 11 05:26:38 PM PDT 24
Peak memory 195264 kb
Host smart-83ff2915-c9eb-471b-b42b-bab691d989ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045426162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.3045426162
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.494308627
Short name T106
Test name
Test status
Simulation time 94891609 ps
CPU time 1.11 seconds
Started Jul 11 05:26:35 PM PDT 24
Finished Jul 11 05:26:40 PM PDT 24
Peak memory 182688 kb
Host smart-6214765f-3882-41f2-b5b3-5ac4fb8a3b92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494308627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.494308627
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.793240126
Short name T427
Test name
Test status
Simulation time 500157142305 ps
CPU time 793.92 seconds
Started Jul 11 05:27:04 PM PDT 24
Finished Jul 11 05:40:20 PM PDT 24
Peak memory 183088 kb
Host smart-b5dff68d-852b-4ca5-a696-f6b9389e8be3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793240126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.793240126
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.3465008939
Short name T368
Test name
Test status
Simulation time 44167300340 ps
CPU time 68.65 seconds
Started Jul 11 05:26:58 PM PDT 24
Finished Jul 11 05:28:07 PM PDT 24
Peak memory 183024 kb
Host smart-3392f141-3b6b-44d9-a437-80b07e38829e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465008939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.3465008939
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.188448260
Short name T288
Test name
Test status
Simulation time 444449740550 ps
CPU time 255.14 seconds
Started Jul 11 05:27:01 PM PDT 24
Finished Jul 11 05:31:18 PM PDT 24
Peak memory 191288 kb
Host smart-3e9d74f7-dc5d-4505-bb58-5a22fe54f947
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188448260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.188448260
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2208335450
Short name T436
Test name
Test status
Simulation time 806718559 ps
CPU time 0.91 seconds
Started Jul 11 05:26:57 PM PDT 24
Finished Jul 11 05:26:59 PM PDT 24
Peak memory 191584 kb
Host smart-06e697f4-da92-4f60-bd22-78edb89c69f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208335450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2208335450
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2358870325
Short name T274
Test name
Test status
Simulation time 353349249184 ps
CPU time 418.71 seconds
Started Jul 11 05:27:02 PM PDT 24
Finished Jul 11 05:34:03 PM PDT 24
Peak memory 182952 kb
Host smart-aaa0b24c-9c1a-4c4e-b4ca-0370fc39a0e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358870325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2358870325
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.4255692643
Short name T424
Test name
Test status
Simulation time 365398654036 ps
CPU time 148.28 seconds
Started Jul 11 05:27:04 PM PDT 24
Finished Jul 11 05:29:34 PM PDT 24
Peak memory 183048 kb
Host smart-5079e1b5-6f96-40f2-ae0c-dc9b5b46dca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255692643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.4255692643
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.885603252
Short name T224
Test name
Test status
Simulation time 111302379856 ps
CPU time 1501.51 seconds
Started Jul 11 05:27:03 PM PDT 24
Finished Jul 11 05:52:06 PM PDT 24
Peak memory 191280 kb
Host smart-0f6825de-429d-4efd-96ae-ca117a9afcc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885603252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.885603252
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.4219212033
Short name T406
Test name
Test status
Simulation time 22933290 ps
CPU time 0.56 seconds
Started Jul 11 05:27:01 PM PDT 24
Finished Jul 11 05:27:04 PM PDT 24
Peak memory 182936 kb
Host smart-be99b585-9999-4fdc-a4b2-64f5aa606d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219212033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.4219212033
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1872516934
Short name T19
Test name
Test status
Simulation time 62596475 ps
CPU time 0.8 seconds
Started Jul 11 05:26:59 PM PDT 24
Finished Jul 11 05:27:01 PM PDT 24
Peak memory 213428 kb
Host smart-ed68cdcf-0253-4cad-83ff-1f8fb75b8455
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872516934 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1872516934
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1291484990
Short name T299
Test name
Test status
Simulation time 49024433668 ps
CPU time 50.89 seconds
Started Jul 11 05:27:17 PM PDT 24
Finished Jul 11 05:28:11 PM PDT 24
Peak memory 183024 kb
Host smart-f5847c72-a4d4-4c5a-8723-4809b08bb858
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291484990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1291484990
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3701130605
Short name T352
Test name
Test status
Simulation time 22111269062 ps
CPU time 28.57 seconds
Started Jul 11 05:27:14 PM PDT 24
Finished Jul 11 05:27:45 PM PDT 24
Peak memory 183024 kb
Host smart-6379449d-31f0-4947-ae7a-304df12cd65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701130605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3701130605
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.2731322756
Short name T9
Test name
Test status
Simulation time 835896616871 ps
CPU time 2967.46 seconds
Started Jul 11 05:27:17 PM PDT 24
Finished Jul 11 06:16:48 PM PDT 24
Peak memory 191308 kb
Host smart-66ff792e-eb93-4bdf-a740-3ee2918b655b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731322756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2731322756
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3506220348
Short name T188
Test name
Test status
Simulation time 131857138422 ps
CPU time 76.66 seconds
Started Jul 11 05:27:14 PM PDT 24
Finished Jul 11 05:28:33 PM PDT 24
Peak memory 191248 kb
Host smart-5c5e99d8-344b-4fde-aed1-6dbecab8c0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506220348 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3506220348
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.483393918
Short name T324
Test name
Test status
Simulation time 141413615678 ps
CPU time 118.7 seconds
Started Jul 11 05:27:19 PM PDT 24
Finished Jul 11 05:29:21 PM PDT 24
Peak memory 195252 kb
Host smart-8fa360c8-8f86-4142-88c2-e1e4ce899555
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483393918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
483393918
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.2999911852
Short name T404
Test name
Test status
Simulation time 324957496711 ps
CPU time 193.46 seconds
Started Jul 11 05:28:25 PM PDT 24
Finished Jul 11 05:31:39 PM PDT 24
Peak memory 191308 kb
Host smart-396aa8bc-7904-4d8c-ad7b-4d82eb838cf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999911852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2999911852
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.806336164
Short name T421
Test name
Test status
Simulation time 104003833522 ps
CPU time 215.72 seconds
Started Jul 11 05:28:25 PM PDT 24
Finished Jul 11 05:32:02 PM PDT 24
Peak memory 191188 kb
Host smart-a72e8ba5-d459-49fd-ac49-174c4671967e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806336164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.806336164
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3953293456
Short name T305
Test name
Test status
Simulation time 336769861033 ps
CPU time 138.07 seconds
Started Jul 11 05:28:36 PM PDT 24
Finished Jul 11 05:30:56 PM PDT 24
Peak memory 191224 kb
Host smart-48c344a7-474f-4a2d-8ffc-883effb83126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953293456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3953293456
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1183538619
Short name T275
Test name
Test status
Simulation time 153058438871 ps
CPU time 67.09 seconds
Started Jul 11 05:28:24 PM PDT 24
Finished Jul 11 05:29:32 PM PDT 24
Peak memory 183112 kb
Host smart-94b08453-ef53-4757-8567-768b2479f19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183538619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1183538619
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.448669230
Short name T149
Test name
Test status
Simulation time 48280496034 ps
CPU time 205.79 seconds
Started Jul 11 05:28:25 PM PDT 24
Finished Jul 11 05:31:52 PM PDT 24
Peak memory 183012 kb
Host smart-dad376a2-22b8-4130-b8ba-0787b0d561a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448669230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.448669230
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.704807223
Short name T323
Test name
Test status
Simulation time 279305631039 ps
CPU time 160.71 seconds
Started Jul 11 05:27:21 PM PDT 24
Finished Jul 11 05:30:05 PM PDT 24
Peak memory 183104 kb
Host smart-b03df967-90f2-4f60-ae49-4b6697a20d38
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704807223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.704807223
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.1693262583
Short name T360
Test name
Test status
Simulation time 172572171081 ps
CPU time 142.6 seconds
Started Jul 11 05:27:22 PM PDT 24
Finished Jul 11 05:29:47 PM PDT 24
Peak memory 183108 kb
Host smart-ef1d1a25-fbcd-4a79-b0d0-ff20e7b2dc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693262583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.1693262583
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2919982022
Short name T439
Test name
Test status
Simulation time 60068129260 ps
CPU time 107.73 seconds
Started Jul 11 05:27:23 PM PDT 24
Finished Jul 11 05:29:14 PM PDT 24
Peak memory 191212 kb
Host smart-6692cf0d-3ada-4ce4-8090-8a5684027d57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919982022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2919982022
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.3152814090
Short name T394
Test name
Test status
Simulation time 969497034 ps
CPU time 1.41 seconds
Started Jul 11 05:27:21 PM PDT 24
Finished Jul 11 05:27:25 PM PDT 24
Peak memory 182908 kb
Host smart-2db0244b-c4e6-4876-b1e5-1b2f447427c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152814090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.3152814090
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.446766583
Short name T67
Test name
Test status
Simulation time 204179695920 ps
CPU time 271.17 seconds
Started Jul 11 05:27:32 PM PDT 24
Finished Jul 11 05:32:07 PM PDT 24
Peak memory 194836 kb
Host smart-229b5748-2967-42db-b22f-abd286d31d03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446766583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
446766583
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.3140780929
Short name T39
Test name
Test status
Simulation time 68556178663 ps
CPU time 410.8 seconds
Started Jul 11 05:27:24 PM PDT 24
Finished Jul 11 05:34:19 PM PDT 24
Peak memory 205980 kb
Host smart-8a44ba3c-a915-4840-a959-0aaa7e687b31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140780929 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.3140780929
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/112.rv_timer_random.1878633568
Short name T209
Test name
Test status
Simulation time 603383075062 ps
CPU time 457.98 seconds
Started Jul 11 05:28:27 PM PDT 24
Finished Jul 11 05:36:06 PM PDT 24
Peak memory 191308 kb
Host smart-7eab37cd-f692-4673-b23c-2443c3af5b10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878633568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1878633568
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.1658275999
Short name T212
Test name
Test status
Simulation time 344271311000 ps
CPU time 416.09 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:35:27 PM PDT 24
Peak memory 191212 kb
Host smart-92e38781-71ad-490d-ba75-ac12a6f460a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658275999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.1658275999
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1015680784
Short name T333
Test name
Test status
Simulation time 225848305337 ps
CPU time 870.77 seconds
Started Jul 11 05:28:32 PM PDT 24
Finished Jul 11 05:43:04 PM PDT 24
Peak memory 191300 kb
Host smart-827e968c-3b9d-4874-961a-9377f7b2f1ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015680784 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1015680784
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1532017599
Short name T430
Test name
Test status
Simulation time 117551041186 ps
CPU time 590.31 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:38:22 PM PDT 24
Peak memory 191184 kb
Host smart-c2442a21-8493-4093-9a23-9b119ae1ebd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532017599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1532017599
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.4005682334
Short name T218
Test name
Test status
Simulation time 114127230656 ps
CPU time 409.96 seconds
Started Jul 11 05:28:31 PM PDT 24
Finished Jul 11 05:35:23 PM PDT 24
Peak memory 191220 kb
Host smart-3a3fd4bc-4c71-435a-af14-0a2d7dce1735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005682334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.4005682334
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2036121075
Short name T312
Test name
Test status
Simulation time 292302444750 ps
CPU time 252.42 seconds
Started Jul 11 05:27:23 PM PDT 24
Finished Jul 11 05:31:39 PM PDT 24
Peak memory 183028 kb
Host smart-e937f4f2-0add-45a9-8ce2-c467afda11ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036121075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2036121075
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.712620417
Short name T363
Test name
Test status
Simulation time 154617015328 ps
CPU time 207.86 seconds
Started Jul 11 05:27:25 PM PDT 24
Finished Jul 11 05:30:57 PM PDT 24
Peak memory 183116 kb
Host smart-37539b16-72db-45e3-909f-a78dbb8bdb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712620417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.712620417
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.1642933886
Short name T392
Test name
Test status
Simulation time 525809233058 ps
CPU time 503.01 seconds
Started Jul 11 05:27:21 PM PDT 24
Finished Jul 11 05:35:47 PM PDT 24
Peak memory 183040 kb
Host smart-21560165-4a8d-45e0-a30d-2104a8ca246f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642933886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.1642933886
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1064805812
Short name T61
Test name
Test status
Simulation time 57983560721 ps
CPU time 136.48 seconds
Started Jul 11 05:27:25 PM PDT 24
Finished Jul 11 05:29:45 PM PDT 24
Peak memory 191320 kb
Host smart-95ebc7e2-324b-41ad-be0a-f8c52374478f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064805812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1064805812
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.2066591162
Short name T246
Test name
Test status
Simulation time 148313791574 ps
CPU time 225.16 seconds
Started Jul 11 05:28:55 PM PDT 24
Finished Jul 11 05:32:41 PM PDT 24
Peak memory 190652 kb
Host smart-dba5f7e3-8054-4434-baf7-441bed1c35c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066591162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.2066591162
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.257497176
Short name T220
Test name
Test status
Simulation time 200577475008 ps
CPU time 172.28 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:31:23 PM PDT 24
Peak memory 191288 kb
Host smart-9448ee01-1f38-4b94-8709-d506a495512a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257497176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.257497176
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.1834780482
Short name T74
Test name
Test status
Simulation time 203245114272 ps
CPU time 381.73 seconds
Started Jul 11 05:28:31 PM PDT 24
Finished Jul 11 05:34:54 PM PDT 24
Peak memory 183108 kb
Host smart-a337b964-d396-41f8-85ae-f2c6f4d702e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834780482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1834780482
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.2548068816
Short name T120
Test name
Test status
Simulation time 271571380085 ps
CPU time 564.53 seconds
Started Jul 11 05:28:30 PM PDT 24
Finished Jul 11 05:37:56 PM PDT 24
Peak memory 183088 kb
Host smart-dd85ff71-1712-44fc-a7ef-f337ec2cbf42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548068816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.2548068816
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1525377544
Short name T180
Test name
Test status
Simulation time 88840436141 ps
CPU time 369.97 seconds
Started Jul 11 05:28:30 PM PDT 24
Finished Jul 11 05:34:42 PM PDT 24
Peak memory 191212 kb
Host smart-6d4ac94e-9591-4335-a239-b4e2332ba9cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525377544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1525377544
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1112742988
Short name T142
Test name
Test status
Simulation time 218472340098 ps
CPU time 339.26 seconds
Started Jul 11 05:27:22 PM PDT 24
Finished Jul 11 05:33:04 PM PDT 24
Peak memory 183092 kb
Host smart-15f1c42e-ce25-41e6-b266-f2d618a888fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112742988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1112742988
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.3136267542
Short name T422
Test name
Test status
Simulation time 116803265577 ps
CPU time 164.91 seconds
Started Jul 11 05:27:26 PM PDT 24
Finished Jul 11 05:30:14 PM PDT 24
Peak memory 183120 kb
Host smart-02be1d99-fba5-417f-b161-975ed6b5f18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136267542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.3136267542
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.969486342
Short name T271
Test name
Test status
Simulation time 64317080672 ps
CPU time 98.32 seconds
Started Jul 11 05:27:26 PM PDT 24
Finished Jul 11 05:29:08 PM PDT 24
Peak memory 191200 kb
Host smart-45e44a3d-6f4a-4d74-a254-bbaea0838b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969486342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.969486342
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3137041238
Short name T314
Test name
Test status
Simulation time 722446471526 ps
CPU time 209.67 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:32:01 PM PDT 24
Peak memory 191300 kb
Host smart-060e7ee0-dcdb-460a-8b59-2c7512983585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137041238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3137041238
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.583793334
Short name T156
Test name
Test status
Simulation time 180673589832 ps
CPU time 176.71 seconds
Started Jul 11 05:28:31 PM PDT 24
Finished Jul 11 05:31:29 PM PDT 24
Peak memory 191156 kb
Host smart-4f5ef434-2997-4453-88d0-c47321561c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583793334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.583793334
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3359964684
Short name T253
Test name
Test status
Simulation time 181475544069 ps
CPU time 121.86 seconds
Started Jul 11 05:28:34 PM PDT 24
Finished Jul 11 05:30:37 PM PDT 24
Peak memory 191232 kb
Host smart-f9b51b25-89fc-49b0-943d-c36e6ffdf87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359964684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3359964684
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.19410883
Short name T252
Test name
Test status
Simulation time 608538021312 ps
CPU time 178.52 seconds
Started Jul 11 05:28:27 PM PDT 24
Finished Jul 11 05:31:27 PM PDT 24
Peak memory 191276 kb
Host smart-bf691878-9ac2-4b27-adc5-2abdadf5051b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19410883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.19410883
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.4135096499
Short name T339
Test name
Test status
Simulation time 469774598986 ps
CPU time 550.71 seconds
Started Jul 11 05:28:55 PM PDT 24
Finished Jul 11 05:38:07 PM PDT 24
Peak memory 191040 kb
Host smart-fde59b5d-17b4-4158-a2fb-17d52c8e158a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135096499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.4135096499
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1355990561
Short name T283
Test name
Test status
Simulation time 446930678220 ps
CPU time 1172.83 seconds
Started Jul 11 05:28:55 PM PDT 24
Finished Jul 11 05:48:29 PM PDT 24
Peak memory 191212 kb
Host smart-54dad021-f00b-4e9d-9e90-778730ce5971
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355990561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1355990561
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.2144370423
Short name T225
Test name
Test status
Simulation time 235999117593 ps
CPU time 420.41 seconds
Started Jul 11 05:28:36 PM PDT 24
Finished Jul 11 05:35:38 PM PDT 24
Peak memory 191280 kb
Host smart-089d1725-4bce-46e6-b210-cd56cea83848
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144370423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.2144370423
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1934875516
Short name T184
Test name
Test status
Simulation time 81602093416 ps
CPU time 481.38 seconds
Started Jul 11 05:28:55 PM PDT 24
Finished Jul 11 05:36:58 PM PDT 24
Peak memory 192060 kb
Host smart-d81d76c0-5e2a-4d9f-ab6c-99dc8545d121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934875516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1934875516
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.653267788
Short name T415
Test name
Test status
Simulation time 25472474560 ps
CPU time 35.22 seconds
Started Jul 11 05:27:21 PM PDT 24
Finished Jul 11 05:27:59 PM PDT 24
Peak memory 183100 kb
Host smart-f352b2e7-16e6-4fd3-a243-fa522c7e3f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653267788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.653267788
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.13493668
Short name T139
Test name
Test status
Simulation time 92969626212 ps
CPU time 82.1 seconds
Started Jul 11 05:27:24 PM PDT 24
Finished Jul 11 05:28:49 PM PDT 24
Peak memory 183084 kb
Host smart-3405062e-0ced-4677-a73c-a97e145809fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13493668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.13493668
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.4241240042
Short name T446
Test name
Test status
Simulation time 27564438541 ps
CPU time 25.74 seconds
Started Jul 11 05:27:24 PM PDT 24
Finished Jul 11 05:27:53 PM PDT 24
Peak memory 183128 kb
Host smart-09fdb67a-8e8c-49b7-84b7-4f62e9a50655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241240042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.4241240042
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.2385588887
Short name T162
Test name
Test status
Simulation time 301053329819 ps
CPU time 1673.32 seconds
Started Jul 11 05:28:34 PM PDT 24
Finished Jul 11 05:56:29 PM PDT 24
Peak memory 191320 kb
Host smart-d2e2ac15-e925-4d4f-b8e6-35e6a9b4844e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385588887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2385588887
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3164879617
Short name T133
Test name
Test status
Simulation time 24287629116 ps
CPU time 40.67 seconds
Started Jul 11 05:28:39 PM PDT 24
Finished Jul 11 05:29:23 PM PDT 24
Peak memory 183028 kb
Host smart-6820f5f3-1318-4af7-a11b-c457341d163c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164879617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3164879617
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.647398905
Short name T270
Test name
Test status
Simulation time 195508004656 ps
CPU time 878.3 seconds
Started Jul 11 05:28:35 PM PDT 24
Finished Jul 11 05:43:15 PM PDT 24
Peak memory 191236 kb
Host smart-d77cdd37-138d-4289-b208-45af9579d767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647398905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.647398905
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3394230943
Short name T257
Test name
Test status
Simulation time 215572375688 ps
CPU time 356.18 seconds
Started Jul 11 05:28:35 PM PDT 24
Finished Jul 11 05:34:32 PM PDT 24
Peak memory 191308 kb
Host smart-acbff578-ff24-495e-a158-0b8044927010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394230943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3394230943
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.78353560
Short name T230
Test name
Test status
Simulation time 365970412051 ps
CPU time 194.16 seconds
Started Jul 11 05:28:34 PM PDT 24
Finished Jul 11 05:31:49 PM PDT 24
Peak memory 191224 kb
Host smart-3934dc51-7523-4fd1-b1c2-43060f6d89f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78353560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.78353560
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1310163924
Short name T172
Test name
Test status
Simulation time 595645397561 ps
CPU time 346 seconds
Started Jul 11 05:28:42 PM PDT 24
Finished Jul 11 05:34:31 PM PDT 24
Peak memory 191304 kb
Host smart-ef17ee84-9dcc-403b-9cbc-6584a2a72ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310163924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1310163924
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1293866990
Short name T384
Test name
Test status
Simulation time 168708317279 ps
CPU time 245.24 seconds
Started Jul 11 05:27:29 PM PDT 24
Finished Jul 11 05:31:38 PM PDT 24
Peak memory 183024 kb
Host smart-9c643e90-630d-4c25-8d15-b433e3453302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293866990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1293866990
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3231161337
Short name T203
Test name
Test status
Simulation time 393122179239 ps
CPU time 670.83 seconds
Started Jul 11 05:27:21 PM PDT 24
Finished Jul 11 05:38:35 PM PDT 24
Peak memory 195220 kb
Host smart-35d3451a-39ac-467f-891e-e17aef474072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231161337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3231161337
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.4136644312
Short name T326
Test name
Test status
Simulation time 50062220255 ps
CPU time 67.8 seconds
Started Jul 11 05:28:44 PM PDT 24
Finished Jul 11 05:29:53 PM PDT 24
Peak memory 182956 kb
Host smart-429bf3dc-9fdb-4462-8c55-5c224df395ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136644312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.4136644312
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.2491028169
Short name T327
Test name
Test status
Simulation time 330862965458 ps
CPU time 67.68 seconds
Started Jul 11 05:28:40 PM PDT 24
Finished Jul 11 05:29:51 PM PDT 24
Peak memory 183108 kb
Host smart-3d432e1e-2441-4c1d-ade8-2dbf2cae7669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491028169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2491028169
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.794278013
Short name T138
Test name
Test status
Simulation time 295343500626 ps
CPU time 702.1 seconds
Started Jul 11 05:28:45 PM PDT 24
Finished Jul 11 05:40:29 PM PDT 24
Peak memory 194664 kb
Host smart-102180e1-9e81-4c85-885c-01cdb5a3c8d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794278013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.794278013
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.3857272316
Short name T447
Test name
Test status
Simulation time 52518778847 ps
CPU time 36.86 seconds
Started Jul 11 05:28:42 PM PDT 24
Finished Jul 11 05:29:22 PM PDT 24
Peak memory 183108 kb
Host smart-d6a41d13-7ab9-4a9e-b349-8316a1732916
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857272316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.3857272316
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.42284394
Short name T29
Test name
Test status
Simulation time 408842744524 ps
CPU time 981.01 seconds
Started Jul 11 05:28:41 PM PDT 24
Finished Jul 11 05:45:05 PM PDT 24
Peak memory 183036 kb
Host smart-4ee39994-8eb8-4367-b9ab-56b0001158a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42284394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.42284394
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3798785400
Short name T136
Test name
Test status
Simulation time 125647270901 ps
CPU time 551.85 seconds
Started Jul 11 05:28:42 PM PDT 24
Finished Jul 11 05:37:57 PM PDT 24
Peak memory 191308 kb
Host smart-24c6f77e-28f8-415b-bcd9-39494a1bf93f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798785400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3798785400
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1982964344
Short name T187
Test name
Test status
Simulation time 416162906310 ps
CPU time 517.22 seconds
Started Jul 11 05:28:40 PM PDT 24
Finished Jul 11 05:37:20 PM PDT 24
Peak memory 191296 kb
Host smart-85a516f6-e7c5-4443-a8d1-c2d540ea01a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982964344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1982964344
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1937564885
Short name T307
Test name
Test status
Simulation time 90950465528 ps
CPU time 42.3 seconds
Started Jul 11 05:28:43 PM PDT 24
Finished Jul 11 05:29:27 PM PDT 24
Peak memory 191204 kb
Host smart-c73dd329-bb6f-4631-8afd-dbc938dc2961
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937564885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1937564885
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.775930957
Short name T258
Test name
Test status
Simulation time 173008149613 ps
CPU time 110.53 seconds
Started Jul 11 05:28:54 PM PDT 24
Finished Jul 11 05:30:46 PM PDT 24
Peak memory 183108 kb
Host smart-547e4bde-db72-4ce8-8f86-0bbd6ad62c8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775930957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.775930957
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2807376181
Short name T432
Test name
Test status
Simulation time 216567913915 ps
CPU time 184.76 seconds
Started Jul 11 05:27:22 PM PDT 24
Finished Jul 11 05:30:30 PM PDT 24
Peak memory 183120 kb
Host smart-183f97c5-01b7-41a0-b30a-ed4e36317429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807376181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2807376181
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3884870673
Short name T8
Test name
Test status
Simulation time 25295277064 ps
CPU time 43.86 seconds
Started Jul 11 05:27:25 PM PDT 24
Finished Jul 11 05:28:13 PM PDT 24
Peak memory 191184 kb
Host smart-a45240e7-61ef-4f1c-a47e-10468f88d319
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884870673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3884870673
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.146016587
Short name T28
Test name
Test status
Simulation time 54511547477 ps
CPU time 80.35 seconds
Started Jul 11 05:27:26 PM PDT 24
Finished Jul 11 05:28:50 PM PDT 24
Peak memory 183088 kb
Host smart-83e05822-51cc-4ab7-8783-7c760c33a306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146016587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.146016587
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.2055999098
Short name T409
Test name
Test status
Simulation time 204165493683 ps
CPU time 92.81 seconds
Started Jul 11 05:28:50 PM PDT 24
Finished Jul 11 05:30:25 PM PDT 24
Peak memory 193424 kb
Host smart-1244cd1f-20da-4066-b1a3-1b807f622bdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055999098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.2055999098
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3593090160
Short name T325
Test name
Test status
Simulation time 140986137948 ps
CPU time 67.28 seconds
Started Jul 11 05:28:52 PM PDT 24
Finished Jul 11 05:30:01 PM PDT 24
Peak memory 183100 kb
Host smart-955af540-2c0d-44ee-a276-d2849068e6e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593090160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3593090160
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1234674908
Short name T431
Test name
Test status
Simulation time 160646677034 ps
CPU time 278.34 seconds
Started Jul 11 05:28:50 PM PDT 24
Finished Jul 11 05:33:30 PM PDT 24
Peak memory 191392 kb
Host smart-56e6526d-15b7-406d-9957-89518e199e3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234674908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1234674908
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.4187851567
Short name T318
Test name
Test status
Simulation time 115143231482 ps
CPU time 105.11 seconds
Started Jul 11 05:28:52 PM PDT 24
Finished Jul 11 05:30:39 PM PDT 24
Peak memory 191300 kb
Host smart-9f42a844-90eb-46e7-b3a3-174e0d703ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187851567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.4187851567
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2128085796
Short name T163
Test name
Test status
Simulation time 339851236489 ps
CPU time 1054.37 seconds
Started Jul 11 05:28:50 PM PDT 24
Finished Jul 11 05:46:27 PM PDT 24
Peak memory 191308 kb
Host smart-c01b98e6-1ffa-4946-8032-2eefaf6eb746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128085796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2128085796
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.3658093503
Short name T141
Test name
Test status
Simulation time 1034598765101 ps
CPU time 255.51 seconds
Started Jul 11 05:28:49 PM PDT 24
Finished Jul 11 05:33:06 PM PDT 24
Peak memory 191300 kb
Host smart-feba62a5-97ef-4082-8dcf-e15d710e7dad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658093503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.3658093503
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1181163448
Short name T250
Test name
Test status
Simulation time 350128214040 ps
CPU time 341.4 seconds
Started Jul 11 05:27:23 PM PDT 24
Finished Jul 11 05:33:07 PM PDT 24
Peak memory 183044 kb
Host smart-311cdee0-b7c1-42d9-8e4a-116bec07c171
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181163448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1181163448
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.1151110851
Short name T375
Test name
Test status
Simulation time 384740907862 ps
CPU time 127.27 seconds
Started Jul 11 05:27:19 PM PDT 24
Finished Jul 11 05:29:30 PM PDT 24
Peak memory 183116 kb
Host smart-6c1359fa-7fd2-4f09-8121-c2da83473628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151110851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.1151110851
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3054846380
Short name T198
Test name
Test status
Simulation time 597119134762 ps
CPU time 279.39 seconds
Started Jul 11 05:27:21 PM PDT 24
Finished Jul 11 05:32:04 PM PDT 24
Peak memory 191308 kb
Host smart-6886db04-1c85-47fd-8954-ac73004ddb60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054846380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3054846380
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.102678683
Short name T359
Test name
Test status
Simulation time 1127682671 ps
CPU time 1.63 seconds
Started Jul 11 05:27:20 PM PDT 24
Finished Jul 11 05:27:24 PM PDT 24
Peak memory 191884 kb
Host smart-3d42b54a-fc83-48cc-a3a8-048ecc6dc924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102678683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.102678683
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2742606900
Short name T343
Test name
Test status
Simulation time 461475232863 ps
CPU time 850.85 seconds
Started Jul 11 05:27:23 PM PDT 24
Finished Jul 11 05:41:37 PM PDT 24
Peak memory 191204 kb
Host smart-21cbce58-a8ca-4853-a7ea-8e61997529d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742606900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2742606900
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.1925112854
Short name T199
Test name
Test status
Simulation time 404174782141 ps
CPU time 209.36 seconds
Started Jul 11 05:28:52 PM PDT 24
Finished Jul 11 05:32:22 PM PDT 24
Peak memory 183028 kb
Host smart-19c03110-4984-4818-b9b6-7630fe80b9aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925112854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1925112854
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.978242090
Short name T76
Test name
Test status
Simulation time 22309373143 ps
CPU time 19.34 seconds
Started Jul 11 05:29:14 PM PDT 24
Finished Jul 11 05:29:35 PM PDT 24
Peak memory 183012 kb
Host smart-032cfc5f-0065-462a-bb0d-77e5a80feea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978242090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.978242090
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.1050584073
Short name T297
Test name
Test status
Simulation time 178507768839 ps
CPU time 140.19 seconds
Started Jul 11 05:28:58 PM PDT 24
Finished Jul 11 05:31:20 PM PDT 24
Peak memory 191236 kb
Host smart-45f76686-c750-44bc-8953-fdb98b7dfc19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050584073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.1050584073
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.121374110
Short name T308
Test name
Test status
Simulation time 297569926496 ps
CPU time 185.11 seconds
Started Jul 11 05:28:57 PM PDT 24
Finished Jul 11 05:32:03 PM PDT 24
Peak memory 191300 kb
Host smart-fc8e1a42-b2a5-4ded-98be-7e33b3d1950c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121374110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.121374110
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.767278764
Short name T222
Test name
Test status
Simulation time 80969956709 ps
CPU time 146.79 seconds
Started Jul 11 05:28:58 PM PDT 24
Finished Jul 11 05:31:26 PM PDT 24
Peak memory 193964 kb
Host smart-15d6b2f1-7809-47f0-8324-7a4b437de0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767278764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.767278764
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3919692538
Short name T442
Test name
Test status
Simulation time 88981126801 ps
CPU time 564.94 seconds
Started Jul 11 05:29:14 PM PDT 24
Finished Jul 11 05:38:41 PM PDT 24
Peak memory 183012 kb
Host smart-11de0395-b61b-4fcf-96aa-a72b5fa4f3dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919692538 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3919692538
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.680793049
Short name T397
Test name
Test status
Simulation time 49507142342 ps
CPU time 38.85 seconds
Started Jul 11 05:28:58 PM PDT 24
Finished Jul 11 05:29:38 PM PDT 24
Peak memory 183080 kb
Host smart-4e2a3196-d7f3-4e35-856a-da19296704a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680793049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.680793049
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.4099634853
Short name T148
Test name
Test status
Simulation time 47058455018 ps
CPU time 66.57 seconds
Started Jul 11 05:28:56 PM PDT 24
Finished Jul 11 05:30:03 PM PDT 24
Peak memory 191308 kb
Host smart-f7ec2785-27be-4f0f-9526-8645a4240628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099634853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.4099634853
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.839336381
Short name T316
Test name
Test status
Simulation time 424018424607 ps
CPU time 361.35 seconds
Started Jul 11 05:27:32 PM PDT 24
Finished Jul 11 05:33:38 PM PDT 24
Peak memory 183120 kb
Host smart-4f321a9f-23e2-4dbb-9233-71d71b11462a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839336381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.839336381
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2892760003
Short name T353
Test name
Test status
Simulation time 314783355336 ps
CPU time 132.97 seconds
Started Jul 11 05:27:24 PM PDT 24
Finished Jul 11 05:29:41 PM PDT 24
Peak memory 183092 kb
Host smart-3c04ccad-58a2-4caf-8787-e11889edd072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892760003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2892760003
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.776375959
Short name T63
Test name
Test status
Simulation time 25668036176 ps
CPU time 12.92 seconds
Started Jul 11 05:27:29 PM PDT 24
Finished Jul 11 05:27:47 PM PDT 24
Peak memory 193748 kb
Host smart-8c9b7dbb-d92a-4a57-95c3-1d9ea646a5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776375959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.776375959
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4266501127
Short name T160
Test name
Test status
Simulation time 381893672557 ps
CPU time 342.8 seconds
Started Jul 11 05:27:38 PM PDT 24
Finished Jul 11 05:33:26 PM PDT 24
Peak memory 191288 kb
Host smart-7653c3ac-2399-4176-88e6-291e083970bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266501127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4266501127
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.370483246
Short name T247
Test name
Test status
Simulation time 206453711663 ps
CPU time 652.61 seconds
Started Jul 11 05:28:57 PM PDT 24
Finished Jul 11 05:39:51 PM PDT 24
Peak memory 191300 kb
Host smart-7ae79190-6004-41af-a179-399205207a1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370483246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.370483246
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.475487995
Short name T3
Test name
Test status
Simulation time 343831827134 ps
CPU time 95.29 seconds
Started Jul 11 05:29:05 PM PDT 24
Finished Jul 11 05:30:43 PM PDT 24
Peak memory 183012 kb
Host smart-99600beb-1173-49b4-8070-4d58ccd5c0ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475487995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.475487995
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1238831474
Short name T217
Test name
Test status
Simulation time 154218895277 ps
CPU time 534.17 seconds
Started Jul 11 05:29:05 PM PDT 24
Finished Jul 11 05:38:02 PM PDT 24
Peak memory 191312 kb
Host smart-42172711-ebe7-4935-ae8b-f9c494d930c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238831474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1238831474
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3521889000
Short name T215
Test name
Test status
Simulation time 28526503487 ps
CPU time 44.17 seconds
Started Jul 11 05:29:02 PM PDT 24
Finished Jul 11 05:29:49 PM PDT 24
Peak memory 193516 kb
Host smart-ce219922-ed1e-450b-9030-ee346d195eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521889000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3521889000
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1225048556
Short name T197
Test name
Test status
Simulation time 136410749107 ps
CPU time 124.82 seconds
Started Jul 11 05:29:04 PM PDT 24
Finished Jul 11 05:31:11 PM PDT 24
Peak memory 191308 kb
Host smart-72063e52-958a-4352-890b-2efaa9a2693a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225048556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1225048556
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1476093311
Short name T214
Test name
Test status
Simulation time 248654140887 ps
CPU time 215.22 seconds
Started Jul 11 05:29:04 PM PDT 24
Finished Jul 11 05:32:42 PM PDT 24
Peak memory 191308 kb
Host smart-6c451df5-9e60-4fd7-a37f-5d2cc4e10398
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476093311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1476093311
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1317560120
Short name T10
Test name
Test status
Simulation time 16421768843 ps
CPU time 96.95 seconds
Started Jul 11 05:29:06 PM PDT 24
Finished Jul 11 05:30:45 PM PDT 24
Peak memory 183108 kb
Host smart-3f279eef-dc46-4423-a279-b18525731dc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317560120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1317560120
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1027480290
Short name T286
Test name
Test status
Simulation time 261238841918 ps
CPU time 116.24 seconds
Started Jul 11 05:29:15 PM PDT 24
Finished Jul 11 05:31:13 PM PDT 24
Peak memory 193584 kb
Host smart-b4b0095b-90db-4248-b885-2b49f95629df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027480290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1027480290
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.57467288
Short name T306
Test name
Test status
Simulation time 251605681963 ps
CPU time 364.43 seconds
Started Jul 11 05:27:26 PM PDT 24
Finished Jul 11 05:33:34 PM PDT 24
Peak memory 183068 kb
Host smart-0bda01e9-9b98-4bf9-a031-0b836eaf4a95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57467288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.rv_timer_cfg_update_on_fly.57467288
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2761751297
Short name T425
Test name
Test status
Simulation time 49493660662 ps
CPU time 78.2 seconds
Started Jul 11 05:27:25 PM PDT 24
Finished Jul 11 05:28:47 PM PDT 24
Peak memory 182088 kb
Host smart-a8b57f14-a034-4917-b1db-ea2d4b402012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761751297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2761751297
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.2655760572
Short name T351
Test name
Test status
Simulation time 379172831 ps
CPU time 0.6 seconds
Started Jul 11 05:27:25 PM PDT 24
Finished Jul 11 05:27:29 PM PDT 24
Peak memory 182896 kb
Host smart-8a06a57c-bdbc-4a76-99dc-dceddb40b797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655760572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.2655760572
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.4276968135
Short name T401
Test name
Test status
Simulation time 143480384544 ps
CPU time 185.39 seconds
Started Jul 11 05:27:25 PM PDT 24
Finished Jul 11 05:30:33 PM PDT 24
Peak memory 183032 kb
Host smart-1fb890ce-8d52-4c84-a416-1e3cf235edd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276968135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.4276968135
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.2765909693
Short name T235
Test name
Test status
Simulation time 1332469011217 ps
CPU time 533.48 seconds
Started Jul 11 05:29:12 PM PDT 24
Finished Jul 11 05:38:06 PM PDT 24
Peak memory 191288 kb
Host smart-94a2af57-9c83-4740-9841-c403aa0d3c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765909693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.2765909693
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.620357559
Short name T7
Test name
Test status
Simulation time 135354993153 ps
CPU time 38.5 seconds
Started Jul 11 05:29:09 PM PDT 24
Finished Jul 11 05:29:49 PM PDT 24
Peak memory 183020 kb
Host smart-372a15d3-35c6-4679-b3e2-64df8e28c1ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620357559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.620357559
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.140910176
Short name T111
Test name
Test status
Simulation time 215180171866 ps
CPU time 1890.27 seconds
Started Jul 11 05:29:10 PM PDT 24
Finished Jul 11 06:00:41 PM PDT 24
Peak memory 192468 kb
Host smart-f4fcde2a-abd5-43a8-b9d4-aa4558cc4f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140910176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.140910176
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.2566801716
Short name T256
Test name
Test status
Simulation time 209930489695 ps
CPU time 190.76 seconds
Started Jul 11 05:29:10 PM PDT 24
Finished Jul 11 05:32:22 PM PDT 24
Peak memory 191308 kb
Host smart-468bdb14-07a9-47da-9c40-57314c0bfad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566801716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.2566801716
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.4222606009
Short name T416
Test name
Test status
Simulation time 200610252706 ps
CPU time 97.92 seconds
Started Jul 11 05:29:14 PM PDT 24
Finished Jul 11 05:30:53 PM PDT 24
Peak memory 182992 kb
Host smart-6c0c570b-1424-4a07-bf54-7e26701808ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222606009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.4222606009
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.565536372
Short name T393
Test name
Test status
Simulation time 41045213832 ps
CPU time 55.29 seconds
Started Jul 11 05:29:15 PM PDT 24
Finished Jul 11 05:30:12 PM PDT 24
Peak memory 183036 kb
Host smart-7b06c469-285c-435d-b63d-fd5122d4b0b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565536372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.565536372
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2709933340
Short name T348
Test name
Test status
Simulation time 18544513770 ps
CPU time 9.61 seconds
Started Jul 11 05:27:00 PM PDT 24
Finished Jul 11 05:27:12 PM PDT 24
Peak memory 183028 kb
Host smart-e3da5a71-4a4b-4530-8edb-b07dbb137592
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709933340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2709933340
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2602154728
Short name T378
Test name
Test status
Simulation time 638915581372 ps
CPU time 245.45 seconds
Started Jul 11 05:27:02 PM PDT 24
Finished Jul 11 05:31:10 PM PDT 24
Peak memory 183092 kb
Host smart-8e67224a-e816-450b-b319-e1f41bb577c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602154728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2602154728
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1097006735
Short name T21
Test name
Test status
Simulation time 398095150220 ps
CPU time 172.33 seconds
Started Jul 11 05:27:00 PM PDT 24
Finished Jul 11 05:29:53 PM PDT 24
Peak memory 193332 kb
Host smart-8436480e-cbc5-47fd-8753-8c0ea8cf98c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097006735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1097006735
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.665634989
Short name T300
Test name
Test status
Simulation time 10076751536 ps
CPU time 5.77 seconds
Started Jul 11 05:27:04 PM PDT 24
Finished Jul 11 05:27:12 PM PDT 24
Peak memory 183116 kb
Host smart-d819f243-97e6-4ebe-b6e8-c9bb54aea577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665634989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.665634989
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3146592818
Short name T17
Test name
Test status
Simulation time 63549124 ps
CPU time 0.82 seconds
Started Jul 11 05:27:00 PM PDT 24
Finished Jul 11 05:27:02 PM PDT 24
Peak memory 214020 kb
Host smart-de5957f4-1231-4fb6-8753-57b1d5d49564
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146592818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3146592818
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1853407492
Short name T200
Test name
Test status
Simulation time 18912020064 ps
CPU time 30.27 seconds
Started Jul 11 05:27:25 PM PDT 24
Finished Jul 11 05:27:58 PM PDT 24
Peak memory 183012 kb
Host smart-ca8a5862-b542-468d-bf68-d97f4f82c735
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853407492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1853407492
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.1081800202
Short name T448
Test name
Test status
Simulation time 111203392749 ps
CPU time 68.92 seconds
Started Jul 11 05:27:25 PM PDT 24
Finished Jul 11 05:28:38 PM PDT 24
Peak memory 182160 kb
Host smart-58d9a7a6-4c2d-4133-91a1-273ef13cc826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081800202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.1081800202
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1852092404
Short name T121
Test name
Test status
Simulation time 199462122043 ps
CPU time 226.27 seconds
Started Jul 11 05:27:24 PM PDT 24
Finished Jul 11 05:31:13 PM PDT 24
Peak memory 191312 kb
Host smart-9b5cc3c2-4f8e-42b2-a7c7-a17ae1f4b39c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852092404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1852092404
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3583790260
Short name T320
Test name
Test status
Simulation time 329774873486 ps
CPU time 98.06 seconds
Started Jul 11 05:27:30 PM PDT 24
Finished Jul 11 05:29:13 PM PDT 24
Peak memory 183076 kb
Host smart-7aebffa1-9e93-45ac-94a3-7e0f1a33b7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583790260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3583790260
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2123666785
Short name T1
Test name
Test status
Simulation time 366431591656 ps
CPU time 557.97 seconds
Started Jul 11 05:27:27 PM PDT 24
Finished Jul 11 05:36:49 PM PDT 24
Peak memory 191232 kb
Host smart-8358e46a-b638-4b74-8e30-dbdb2b04c92b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123666785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2123666785
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.626814989
Short name T342
Test name
Test status
Simulation time 89059561069 ps
CPU time 148.99 seconds
Started Jul 11 05:27:32 PM PDT 24
Finished Jul 11 05:30:06 PM PDT 24
Peak memory 183012 kb
Host smart-863bc6f2-d6bd-4130-aac7-0aac2819b29c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626814989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.rv_timer_cfg_update_on_fly.626814989
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3811252333
Short name T400
Test name
Test status
Simulation time 195828822191 ps
CPU time 205 seconds
Started Jul 11 05:27:31 PM PDT 24
Finished Jul 11 05:31:00 PM PDT 24
Peak memory 182960 kb
Host smart-97212944-f838-4d11-a014-ffdd4467349c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811252333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3811252333
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.101927064
Short name T419
Test name
Test status
Simulation time 23780646396 ps
CPU time 8.24 seconds
Started Jul 11 05:27:38 PM PDT 24
Finished Jul 11 05:27:51 PM PDT 24
Peak memory 182820 kb
Host smart-cc9cf660-9bed-4fad-bf6e-bf95340abea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101927064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.101927064
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.818017561
Short name T328
Test name
Test status
Simulation time 86016302560 ps
CPU time 575.74 seconds
Started Jul 11 05:27:31 PM PDT 24
Finished Jul 11 05:37:12 PM PDT 24
Peak memory 191252 kb
Host smart-4f7eaa58-3c1e-4665-b873-9e3629494b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818017561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.818017561
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1334486417
Short name T412
Test name
Test status
Simulation time 1118902903946 ps
CPU time 326.14 seconds
Started Jul 11 05:27:32 PM PDT 24
Finished Jul 11 05:33:03 PM PDT 24
Peak memory 191208 kb
Host smart-a87fdc87-759e-42d3-9c4b-2ec660fd44cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334486417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1334486417
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3917441125
Short name T178
Test name
Test status
Simulation time 26536053486 ps
CPU time 40.54 seconds
Started Jul 11 05:27:38 PM PDT 24
Finished Jul 11 05:28:24 PM PDT 24
Peak memory 183088 kb
Host smart-252a70d5-fcb2-425b-b8ab-a1f22917b96d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917441125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3917441125
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.1021662990
Short name T358
Test name
Test status
Simulation time 153007849210 ps
CPU time 201.01 seconds
Started Jul 11 05:27:27 PM PDT 24
Finished Jul 11 05:30:53 PM PDT 24
Peak memory 183016 kb
Host smart-e7a69f4b-ae8c-493d-bdc2-92214be3e4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021662990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.1021662990
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1811663112
Short name T128
Test name
Test status
Simulation time 626879283827 ps
CPU time 554.74 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:36:54 PM PDT 24
Peak memory 191300 kb
Host smart-811c8cdf-b576-4e58-8df8-a10c4c2cf7a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811663112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1811663112
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.105260196
Short name T140
Test name
Test status
Simulation time 102293209070 ps
CPU time 874.86 seconds
Started Jul 11 05:27:36 PM PDT 24
Finished Jul 11 05:42:16 PM PDT 24
Peak memory 191320 kb
Host smart-4b3d2bcd-844d-4dea-9cfb-dab3a073df73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105260196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.105260196
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.757384792
Short name T14
Test name
Test status
Simulation time 124419757853 ps
CPU time 257.42 seconds
Started Jul 11 05:27:29 PM PDT 24
Finished Jul 11 05:31:51 PM PDT 24
Peak memory 206020 kb
Host smart-6a974794-18b6-4b52-9aac-dcbfd6bb6125
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757384792 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.757384792
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2130814457
Short name T403
Test name
Test status
Simulation time 186810643269 ps
CPU time 307.39 seconds
Started Jul 11 05:27:28 PM PDT 24
Finished Jul 11 05:32:40 PM PDT 24
Peak memory 183096 kb
Host smart-146e6d3d-24df-4b1b-b6c8-67d916bd51c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130814457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2130814457
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2806836640
Short name T411
Test name
Test status
Simulation time 97721336212 ps
CPU time 36.67 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:28:16 PM PDT 24
Peak memory 183112 kb
Host smart-2935ed83-d205-4346-ba7e-dfd2e88804ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806836640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2806836640
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.1321234409
Short name T254
Test name
Test status
Simulation time 23058915363 ps
CPU time 801.04 seconds
Started Jul 11 05:27:33 PM PDT 24
Finished Jul 11 05:40:59 PM PDT 24
Peak memory 183128 kb
Host smart-b507d003-deec-4272-bed2-9f228810975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321234409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.1321234409
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.107472688
Short name T155
Test name
Test status
Simulation time 1903413600527 ps
CPU time 851.66 seconds
Started Jul 11 05:27:37 PM PDT 24
Finished Jul 11 05:41:53 PM PDT 24
Peak memory 191296 kb
Host smart-3c12de54-6e06-407f-a268-0966a85a3f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107472688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
107472688
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.30519668
Short name T262
Test name
Test status
Simulation time 35150015417 ps
CPU time 10.75 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:27:49 PM PDT 24
Peak memory 183084 kb
Host smart-9fd91cc3-65cb-4c2e-b3fe-2e620ddcc03d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30519668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.rv_timer_cfg_update_on_fly.30519668
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3981644808
Short name T356
Test name
Test status
Simulation time 48023317562 ps
CPU time 72.14 seconds
Started Jul 11 05:27:31 PM PDT 24
Finished Jul 11 05:28:48 PM PDT 24
Peak memory 183120 kb
Host smart-3a61bdcb-9e09-4ca3-87ba-0c60ca45cd7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981644808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3981644808
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.784450195
Short name T278
Test name
Test status
Simulation time 220008772576 ps
CPU time 183.64 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:31:35 PM PDT 24
Peak memory 193276 kb
Host smart-d1feeed2-9244-4deb-8cad-55cfee20dc7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784450195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.784450195
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1595259925
Short name T196
Test name
Test status
Simulation time 20708109208 ps
CPU time 24.15 seconds
Started Jul 11 05:27:32 PM PDT 24
Finished Jul 11 05:28:01 PM PDT 24
Peak memory 194532 kb
Host smart-e9ad78b4-9962-4b62-9640-46852fc8344d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595259925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1595259925
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1877182829
Short name T24
Test name
Test status
Simulation time 209119631554 ps
CPU time 196.75 seconds
Started Jul 11 05:27:29 PM PDT 24
Finished Jul 11 05:30:50 PM PDT 24
Peak memory 183096 kb
Host smart-de74e4da-054b-4d45-a5e5-31cab0663d33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877182829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1877182829
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2471354326
Short name T371
Test name
Test status
Simulation time 914991392923 ps
CPU time 149.92 seconds
Started Jul 11 05:27:38 PM PDT 24
Finished Jul 11 05:30:13 PM PDT 24
Peak memory 182868 kb
Host smart-5f05de5f-0092-4bed-b25d-f8edd6b39847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471354326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2471354326
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.2941364362
Short name T134
Test name
Test status
Simulation time 20909337925 ps
CPU time 124.61 seconds
Started Jul 11 05:27:28 PM PDT 24
Finished Jul 11 05:29:38 PM PDT 24
Peak memory 183092 kb
Host smart-2361795c-a74d-440f-879d-84f2ed149785
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941364362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.2941364362
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2235574807
Short name T372
Test name
Test status
Simulation time 515323750 ps
CPU time 1.21 seconds
Started Jul 11 05:27:28 PM PDT 24
Finished Jul 11 05:27:33 PM PDT 24
Peak memory 183064 kb
Host smart-2bb1433d-4398-40da-9f66-1aac1e792607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235574807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2235574807
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.686786896
Short name T50
Test name
Test status
Simulation time 27571141305 ps
CPU time 209.84 seconds
Started Jul 11 05:27:28 PM PDT 24
Finished Jul 11 05:31:02 PM PDT 24
Peak memory 205916 kb
Host smart-dda60d45-46b4-4464-9f4c-868e96225c51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686786896 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.686786896
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.2468701185
Short name T313
Test name
Test status
Simulation time 159795500424 ps
CPU time 247.19 seconds
Started Jul 11 05:27:32 PM PDT 24
Finished Jul 11 05:31:44 PM PDT 24
Peak memory 182996 kb
Host smart-60ad5adf-4189-4eeb-9cbe-7ff4de210d18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468701185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.2468701185
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2534145973
Short name T41
Test name
Test status
Simulation time 216355335325 ps
CPU time 71.31 seconds
Started Jul 11 05:27:28 PM PDT 24
Finished Jul 11 05:28:44 PM PDT 24
Peak memory 183116 kb
Host smart-95d28f70-d5fa-44e6-87d4-499c6b2e1efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534145973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2534145973
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2357540382
Short name T336
Test name
Test status
Simulation time 685750894755 ps
CPU time 1370.4 seconds
Started Jul 11 05:27:31 PM PDT 24
Finished Jul 11 05:50:26 PM PDT 24
Peak memory 191248 kb
Host smart-84c13ebd-8368-4665-8032-bdad560b8274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357540382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2357540382
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3609182429
Short name T194
Test name
Test status
Simulation time 57230673905 ps
CPU time 93.05 seconds
Started Jul 11 05:27:33 PM PDT 24
Finished Jul 11 05:29:11 PM PDT 24
Peak memory 183104 kb
Host smart-5188ca41-0446-4712-8956-301cdbd3ef3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609182429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3609182429
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2220546295
Short name T354
Test name
Test status
Simulation time 616915690666 ps
CPU time 191.74 seconds
Started Jul 11 05:27:37 PM PDT 24
Finished Jul 11 05:30:55 PM PDT 24
Peak memory 183104 kb
Host smart-01132109-1ade-44e0-ab4c-9c4956519cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220546295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2220546295
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.1818536675
Short name T204
Test name
Test status
Simulation time 352052870631 ps
CPU time 216.92 seconds
Started Jul 11 05:28:17 PM PDT 24
Finished Jul 11 05:31:55 PM PDT 24
Peak memory 191212 kb
Host smart-3f52897d-9546-4791-91c3-d862c2095178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818536675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1818536675
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1907929658
Short name T444
Test name
Test status
Simulation time 169680219 ps
CPU time 1.52 seconds
Started Jul 11 05:27:28 PM PDT 24
Finished Jul 11 05:27:34 PM PDT 24
Peak memory 191268 kb
Host smart-1d9253b8-f004-4b4b-9431-dcdbcb604df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907929658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1907929658
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2739178073
Short name T216
Test name
Test status
Simulation time 3392097766907 ps
CPU time 2128.05 seconds
Started Jul 11 05:27:27 PM PDT 24
Finished Jul 11 06:02:59 PM PDT 24
Peak memory 195948 kb
Host smart-51fc34ff-c8d0-425f-b3b9-08774d4b8897
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739178073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2739178073
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_random.138380875
Short name T242
Test name
Test status
Simulation time 5613590653 ps
CPU time 66.11 seconds
Started Jul 11 05:27:29 PM PDT 24
Finished Jul 11 05:28:40 PM PDT 24
Peak memory 183024 kb
Host smart-d8602c4f-b2a2-4b50-8603-658737f106b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138380875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.138380875
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.2606030819
Short name T144
Test name
Test status
Simulation time 24933282824 ps
CPU time 13.45 seconds
Started Jul 11 05:27:31 PM PDT 24
Finished Jul 11 05:27:49 PM PDT 24
Peak memory 183024 kb
Host smart-595813ec-3be9-46e0-8a53-6199f7647643
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606030819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.2606030819
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.3621162493
Short name T398
Test name
Test status
Simulation time 136950581851 ps
CPU time 203.16 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:31:02 PM PDT 24
Peak memory 183040 kb
Host smart-284befef-e214-426b-8504-1674dbab4cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621162493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.3621162493
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1588466079
Short name T108
Test name
Test status
Simulation time 144996378713 ps
CPU time 376.9 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:33:56 PM PDT 24
Peak memory 194816 kb
Host smart-96ae5b2c-8c92-40ed-8090-4abe62a65b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588466079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1588466079
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.4190906724
Short name T405
Test name
Test status
Simulation time 4525192126 ps
CPU time 20.53 seconds
Started Jul 11 05:27:37 PM PDT 24
Finished Jul 11 05:28:03 PM PDT 24
Peak memory 183092 kb
Host smart-57a66949-3cc9-481a-8a59-365269194b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190906724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.4190906724
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2315948349
Short name T77
Test name
Test status
Simulation time 55304905607 ps
CPU time 31.03 seconds
Started Jul 11 05:26:59 PM PDT 24
Finished Jul 11 05:27:31 PM PDT 24
Peak memory 183084 kb
Host smart-27d4d647-afb9-4581-a088-d06e8272190f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315948349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2315948349
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3860128264
Short name T434
Test name
Test status
Simulation time 31247809332 ps
CPU time 41.55 seconds
Started Jul 11 05:26:59 PM PDT 24
Finished Jul 11 05:27:42 PM PDT 24
Peak memory 183060 kb
Host smart-32c076f1-f6b3-4155-9af4-98a92bcfc396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860128264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3860128264
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.2442218668
Short name T418
Test name
Test status
Simulation time 34063017477 ps
CPU time 59.58 seconds
Started Jul 11 05:27:03 PM PDT 24
Finished Jul 11 05:28:05 PM PDT 24
Peak memory 183108 kb
Host smart-157c13a5-9b2b-4767-a7a1-4d8a4caf5982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442218668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2442218668
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2783767260
Short name T239
Test name
Test status
Simulation time 851723449841 ps
CPU time 287.39 seconds
Started Jul 11 05:27:00 PM PDT 24
Finished Jul 11 05:31:49 PM PDT 24
Peak memory 195184 kb
Host smart-0fdaa692-4587-43cf-88fe-94d8a022bb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783767260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2783767260
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.2680371707
Short name T18
Test name
Test status
Simulation time 37250174 ps
CPU time 0.76 seconds
Started Jul 11 05:27:01 PM PDT 24
Finished Jul 11 05:27:04 PM PDT 24
Peak memory 213312 kb
Host smart-e0493441-8b2e-455c-8c3d-4382a80603a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680371707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.2680371707
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2581135845
Short name T181
Test name
Test status
Simulation time 74787727316 ps
CPU time 124.21 seconds
Started Jul 11 05:27:35 PM PDT 24
Finished Jul 11 05:29:45 PM PDT 24
Peak memory 183096 kb
Host smart-70b63c58-be56-4c48-9e0c-1b81c6a905fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581135845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2581135845
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1235455058
Short name T355
Test name
Test status
Simulation time 476516648806 ps
CPU time 146 seconds
Started Jul 11 05:27:33 PM PDT 24
Finished Jul 11 05:30:04 PM PDT 24
Peak memory 183132 kb
Host smart-d1488303-6923-40a2-8d14-c4ccd65ac0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235455058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1235455058
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3418834243
Short name T171
Test name
Test status
Simulation time 73923055818 ps
CPU time 129.51 seconds
Started Jul 11 05:27:41 PM PDT 24
Finished Jul 11 05:29:55 PM PDT 24
Peak memory 191192 kb
Host smart-bf4ddf6c-aff7-4e5d-b855-c198b4fe8da7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418834243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3418834243
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3468312632
Short name T379
Test name
Test status
Simulation time 826172184 ps
CPU time 1.16 seconds
Started Jul 11 05:27:33 PM PDT 24
Finished Jul 11 05:27:39 PM PDT 24
Peak memory 182864 kb
Host smart-9b75de70-87ff-4616-8f55-252b52bf1b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468312632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3468312632
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1567185793
Short name T293
Test name
Test status
Simulation time 220907804876 ps
CPU time 68.22 seconds
Started Jul 11 05:27:31 PM PDT 24
Finished Jul 11 05:28:44 PM PDT 24
Peak memory 183008 kb
Host smart-dd2de464-e57e-4bc4-a412-c592afed5614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567185793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1567185793
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.579445327
Short name T302
Test name
Test status
Simulation time 187899865848 ps
CPU time 312.88 seconds
Started Jul 11 05:27:47 PM PDT 24
Finished Jul 11 05:33:03 PM PDT 24
Peak memory 183036 kb
Host smart-925f6b85-3f67-4906-a597-608d24c02275
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579445327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.rv_timer_cfg_update_on_fly.579445327
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3965363998
Short name T413
Test name
Test status
Simulation time 6762580511 ps
CPU time 3.56 seconds
Started Jul 11 05:27:47 PM PDT 24
Finished Jul 11 05:27:53 PM PDT 24
Peak memory 183060 kb
Host smart-0a7295e8-e254-456e-b290-51bfdef1f6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965363998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3965363998
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1367529752
Short name T290
Test name
Test status
Simulation time 100872677060 ps
CPU time 173.87 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:30:33 PM PDT 24
Peak memory 194952 kb
Host smart-2489b475-f770-4770-8adc-0a21187fdb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367529752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1367529752
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1718757995
Short name T322
Test name
Test status
Simulation time 266982611939 ps
CPU time 345.43 seconds
Started Jul 11 05:27:33 PM PDT 24
Finished Jul 11 05:33:23 PM PDT 24
Peak memory 191300 kb
Host smart-b6c4393f-ece7-48c2-99dc-fb47e5eec784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718757995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1718757995
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.225076073
Short name T15
Test name
Test status
Simulation time 15461531092 ps
CPU time 147.23 seconds
Started Jul 11 05:27:33 PM PDT 24
Finished Jul 11 05:30:05 PM PDT 24
Peak memory 197808 kb
Host smart-80ab4942-f42e-471f-b8de-cb0f011b9f38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225076073 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.225076073
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.2573477589
Short name T152
Test name
Test status
Simulation time 218577598876 ps
CPU time 205.7 seconds
Started Jul 11 05:27:37 PM PDT 24
Finished Jul 11 05:31:08 PM PDT 24
Peak memory 183092 kb
Host smart-1c3dd141-3355-4e57-8dc1-a81a9575dede
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573477589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.2573477589
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2624665648
Short name T435
Test name
Test status
Simulation time 423501216491 ps
CPU time 322.35 seconds
Started Jul 11 05:27:47 PM PDT 24
Finished Jul 11 05:33:12 PM PDT 24
Peak memory 183060 kb
Host smart-5d83858a-2da5-4ceb-9bad-bc79bcdf2cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624665648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2624665648
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2000507020
Short name T167
Test name
Test status
Simulation time 916237170419 ps
CPU time 471.62 seconds
Started Jul 11 05:27:32 PM PDT 24
Finished Jul 11 05:35:28 PM PDT 24
Peak memory 191184 kb
Host smart-b423272a-5b1b-4da5-94c4-ea8d83212dd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000507020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2000507020
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.2344225946
Short name T383
Test name
Test status
Simulation time 577783908 ps
CPU time 1.78 seconds
Started Jul 11 05:27:35 PM PDT 24
Finished Jul 11 05:27:42 PM PDT 24
Peak memory 193676 kb
Host smart-0905f4dc-7342-44f4-8758-bd79fcd4205b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344225946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.2344225946
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.144423893
Short name T440
Test name
Test status
Simulation time 22202089010 ps
CPU time 224.07 seconds
Started Jul 11 05:27:36 PM PDT 24
Finished Jul 11 05:31:25 PM PDT 24
Peak memory 197808 kb
Host smart-f5d0d0de-4b32-4401-9ca8-82dcc0cf325a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144423893 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.144423893
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3115950654
Short name T341
Test name
Test status
Simulation time 3145118582 ps
CPU time 5.88 seconds
Started Jul 11 05:27:37 PM PDT 24
Finished Jul 11 05:27:48 PM PDT 24
Peak memory 182996 kb
Host smart-a0f7799f-5869-406c-890b-dc321509880a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115950654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3115950654
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_random.3811283857
Short name T309
Test name
Test status
Simulation time 576277090795 ps
CPU time 2574.01 seconds
Started Jul 11 05:27:37 PM PDT 24
Finished Jul 11 06:10:37 PM PDT 24
Peak memory 191280 kb
Host smart-bafe835d-cce6-4446-86c6-2e9366c3fb08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811283857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3811283857
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3985364405
Short name T346
Test name
Test status
Simulation time 174228059482 ps
CPU time 96.65 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:29:15 PM PDT 24
Peak memory 191328 kb
Host smart-79bc58c5-bc3a-47b2-9283-178d44f6aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985364405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3985364405
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3137252909
Short name T249
Test name
Test status
Simulation time 175862265162 ps
CPU time 287.93 seconds
Started Jul 11 05:27:35 PM PDT 24
Finished Jul 11 05:32:28 PM PDT 24
Peak memory 191300 kb
Host smart-30154919-88b0-4529-b27c-b7d6cef20d19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137252909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3137252909
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2488772446
Short name T420
Test name
Test status
Simulation time 238116788055 ps
CPU time 418.62 seconds
Started Jul 11 05:27:38 PM PDT 24
Finished Jul 11 05:34:42 PM PDT 24
Peak memory 183100 kb
Host smart-b5a7fc6b-81b0-4a0c-a09b-6aa0c06ea668
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488772446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2488772446
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1832007183
Short name T374
Test name
Test status
Simulation time 83160772334 ps
CPU time 115.65 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:29:34 PM PDT 24
Peak memory 183120 kb
Host smart-966a5f81-c200-4a49-baff-072befdab58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832007183 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1832007183
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.367023040
Short name T154
Test name
Test status
Simulation time 11343467695 ps
CPU time 21.62 seconds
Started Jul 11 05:27:32 PM PDT 24
Finished Jul 11 05:27:59 PM PDT 24
Peak memory 183104 kb
Host smart-b1d35628-08c7-43fb-848d-8b2a8ab95a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367023040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.367023040
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3732627287
Short name T71
Test name
Test status
Simulation time 354086482361 ps
CPU time 429.2 seconds
Started Jul 11 05:27:39 PM PDT 24
Finished Jul 11 05:34:54 PM PDT 24
Peak memory 195324 kb
Host smart-db63c71e-10a7-413d-aa5b-874219fe8bd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732627287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3732627287
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.1277684812
Short name T36
Test name
Test status
Simulation time 16166119586 ps
CPU time 94.57 seconds
Started Jul 11 05:27:46 PM PDT 24
Finished Jul 11 05:29:24 PM PDT 24
Peak memory 197748 kb
Host smart-4d38c365-07ee-4fec-a15f-3fbf988ebc48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277684812 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.1277684812
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3401914220
Short name T365
Test name
Test status
Simulation time 175573766791 ps
CPU time 124.56 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:29:43 PM PDT 24
Peak memory 183112 kb
Host smart-6b27e480-bac0-4300-ac3d-59596bacf8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401914220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3401914220
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.2502367006
Short name T387
Test name
Test status
Simulation time 34985172237 ps
CPU time 52.84 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:28:32 PM PDT 24
Peak memory 182924 kb
Host smart-7a9b471a-2223-49f7-bc50-1d5d9e17b749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502367006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.2502367006
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.503986539
Short name T78
Test name
Test status
Simulation time 3043171548 ps
CPU time 1.34 seconds
Started Jul 11 05:30:11 PM PDT 24
Finished Jul 11 05:30:14 PM PDT 24
Peak memory 192856 kb
Host smart-3d360496-ce29-4693-97c6-fe755177b70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503986539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.503986539
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3377032733
Short name T380
Test name
Test status
Simulation time 70596388 ps
CPU time 0.58 seconds
Started Jul 11 05:27:34 PM PDT 24
Finished Jul 11 05:27:39 PM PDT 24
Peak memory 182856 kb
Host smart-12982da9-210d-4b17-ae40-fe2d71a8b0e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377032733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3377032733
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1137240176
Short name T377
Test name
Test status
Simulation time 60298389731 ps
CPU time 91.98 seconds
Started Jul 11 05:27:38 PM PDT 24
Finished Jul 11 05:29:16 PM PDT 24
Peak memory 183096 kb
Host smart-d40ddabb-0ac1-44b3-8dbc-1ea273a05e5c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137240176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1137240176
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1267223968
Short name T56
Test name
Test status
Simulation time 172124069517 ps
CPU time 234.28 seconds
Started Jul 11 05:27:47 PM PDT 24
Finished Jul 11 05:31:44 PM PDT 24
Peak memory 183060 kb
Host smart-be8b8e1f-7a9d-4b97-bba8-ed81037eca84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267223968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1267223968
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1465143243
Short name T344
Test name
Test status
Simulation time 68209014960 ps
CPU time 31.54 seconds
Started Jul 11 05:27:41 PM PDT 24
Finished Jul 11 05:28:17 PM PDT 24
Peak memory 191216 kb
Host smart-cbfab3be-2acf-4714-ab98-7fe584da230e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465143243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1465143243
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2404412285
Short name T426
Test name
Test status
Simulation time 349764641670 ps
CPU time 283.7 seconds
Started Jul 11 05:27:39 PM PDT 24
Finished Jul 11 05:32:27 PM PDT 24
Peak memory 194596 kb
Host smart-efb1e154-7b88-447d-b317-0d1950e945c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404412285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2404412285
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.688441877
Short name T373
Test name
Test status
Simulation time 295547580485 ps
CPU time 200.67 seconds
Started Jul 11 05:27:52 PM PDT 24
Finished Jul 11 05:31:14 PM PDT 24
Peak memory 183048 kb
Host smart-75d81205-fe45-4207-b37e-d40dc8ced389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688441877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.688441877
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.2707838835
Short name T303
Test name
Test status
Simulation time 43867992026 ps
CPU time 78.57 seconds
Started Jul 11 05:27:40 PM PDT 24
Finished Jul 11 05:29:04 PM PDT 24
Peak memory 191276 kb
Host smart-46ec797c-dc5d-424e-bd27-e4507de42ed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707838835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.2707838835
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.624703722
Short name T267
Test name
Test status
Simulation time 108174725947 ps
CPU time 85.46 seconds
Started Jul 11 05:27:41 PM PDT 24
Finished Jul 11 05:29:12 PM PDT 24
Peak memory 194580 kb
Host smart-845fd562-1a31-4c05-a37d-deb907706290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624703722 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.624703722
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.313159144
Short name T201
Test name
Test status
Simulation time 374586274000 ps
CPU time 2302.5 seconds
Started Jul 11 05:27:40 PM PDT 24
Finished Jul 11 06:06:08 PM PDT 24
Peak memory 195152 kb
Host smart-40027ac0-ba25-4cc5-a66e-068d6a66aebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313159144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all.
313159144
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.2287687790
Short name T202
Test name
Test status
Simulation time 87223018102 ps
CPU time 152.8 seconds
Started Jul 11 05:27:52 PM PDT 24
Finished Jul 11 05:30:26 PM PDT 24
Peak memory 183024 kb
Host smart-d5733285-aed9-4b8b-a562-6fca77bda31b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287687790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.2287687790
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1055447895
Short name T42
Test name
Test status
Simulation time 376059728463 ps
CPU time 136.62 seconds
Started Jul 11 05:27:43 PM PDT 24
Finished Jul 11 05:30:04 PM PDT 24
Peak memory 183112 kb
Host smart-324af1fe-d895-4f8d-ab3c-4ce6821c5447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055447895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1055447895
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.2380358010
Short name T177
Test name
Test status
Simulation time 313470084129 ps
CPU time 311.64 seconds
Started Jul 11 05:27:48 PM PDT 24
Finished Jul 11 05:33:02 PM PDT 24
Peak memory 191320 kb
Host smart-4554e200-eed1-4368-88ce-78a8ccfef965
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380358010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2380358010
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1936530908
Short name T310
Test name
Test status
Simulation time 161844764173 ps
CPU time 531.37 seconds
Started Jul 11 05:27:41 PM PDT 24
Finished Jul 11 05:36:38 PM PDT 24
Peak memory 183032 kb
Host smart-d9ef8889-1601-475f-b908-102f39e5b49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936530908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1936530908
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.624383447
Short name T11
Test name
Test status
Simulation time 2022571083834 ps
CPU time 942.55 seconds
Started Jul 11 05:27:39 PM PDT 24
Finished Jul 11 05:43:27 PM PDT 24
Peak memory 195484 kb
Host smart-2fc01f50-b285-4129-babf-72fe461f863e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624383447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all.
624383447
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3434197638
Short name T268
Test name
Test status
Simulation time 90828259863 ps
CPU time 163.41 seconds
Started Jul 11 05:27:38 PM PDT 24
Finished Jul 11 05:30:27 PM PDT 24
Peak memory 183024 kb
Host smart-d23bb35a-cb8f-4780-a0d4-28130051927e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434197638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3434197638
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1298472862
Short name T449
Test name
Test status
Simulation time 84827878777 ps
CPU time 115.04 seconds
Started Jul 11 05:27:39 PM PDT 24
Finished Jul 11 05:29:39 PM PDT 24
Peak memory 183120 kb
Host smart-b9aa141b-ede9-408f-b448-7d9aa0a4528b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298472862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1298472862
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.3391979434
Short name T231
Test name
Test status
Simulation time 24533428136 ps
CPU time 16.08 seconds
Started Jul 11 05:27:52 PM PDT 24
Finished Jul 11 05:28:09 PM PDT 24
Peak memory 183028 kb
Host smart-5f4f517d-e0ab-451b-abb7-70ddacf1846c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391979434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3391979434
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.622032392
Short name T381
Test name
Test status
Simulation time 2943367321 ps
CPU time 5.14 seconds
Started Jul 11 05:27:38 PM PDT 24
Finished Jul 11 05:27:49 PM PDT 24
Peak memory 183000 kb
Host smart-85d89fc3-9a04-4280-928f-5b041d6ca5c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622032392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
622032392
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3927787900
Short name T131
Test name
Test status
Simulation time 273741546390 ps
CPU time 442.91 seconds
Started Jul 11 05:27:19 PM PDT 24
Finished Jul 11 05:34:45 PM PDT 24
Peak memory 183008 kb
Host smart-670b6756-43e1-45fe-8227-98a759a1c7ba
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927787900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3927787900
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.4184842683
Short name T369
Test name
Test status
Simulation time 867937870571 ps
CPU time 348.09 seconds
Started Jul 11 05:27:13 PM PDT 24
Finished Jul 11 05:33:03 PM PDT 24
Peak memory 183052 kb
Host smart-d8c10d37-62cf-47a1-bf50-13b7e17de1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184842683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.4184842683
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2214878699
Short name T62
Test name
Test status
Simulation time 119281962745 ps
CPU time 210.85 seconds
Started Jul 11 05:27:03 PM PDT 24
Finished Jul 11 05:30:36 PM PDT 24
Peak memory 191308 kb
Host smart-29a10792-d877-42dc-bb34-6834bc5d6432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214878699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2214878699
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.296045629
Short name T376
Test name
Test status
Simulation time 86548758 ps
CPU time 0.72 seconds
Started Jul 11 05:27:18 PM PDT 24
Finished Jul 11 05:27:22 PM PDT 24
Peak memory 182972 kb
Host smart-338d11ca-bef9-4e03-a9b0-8dc5d90321a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296045629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.296045629
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.3483025378
Short name T20
Test name
Test status
Simulation time 214804655 ps
CPU time 0.89 seconds
Started Jul 11 05:27:15 PM PDT 24
Finished Jul 11 05:27:19 PM PDT 24
Peak memory 213356 kb
Host smart-896c6f84-476b-4644-83e1-6ccbc5357d06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483025378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.3483025378
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.79648221
Short name T233
Test name
Test status
Simulation time 1399227282747 ps
CPU time 1104 seconds
Started Jul 11 05:27:16 PM PDT 24
Finished Jul 11 05:45:43 PM PDT 24
Peak memory 191300 kb
Host smart-8f92202f-77ae-4e32-ad4a-2acbdeba13aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79648221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.79648221
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1278080241
Short name T285
Test name
Test status
Simulation time 42725168184 ps
CPU time 21.01 seconds
Started Jul 11 05:27:53 PM PDT 24
Finished Jul 11 05:28:15 PM PDT 24
Peak memory 183024 kb
Host smart-a1943eec-c95c-4913-a0bc-230c24fa67b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278080241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1278080241
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.3380717788
Short name T361
Test name
Test status
Simulation time 314652560463 ps
CPU time 166.22 seconds
Started Jul 11 05:27:51 PM PDT 24
Finished Jul 11 05:30:38 PM PDT 24
Peak memory 183040 kb
Host smart-1aaabae6-5c83-4028-8487-688e08c47e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380717788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.3380717788
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.2119895822
Short name T265
Test name
Test status
Simulation time 1600863695043 ps
CPU time 780.95 seconds
Started Jul 11 05:27:42 PM PDT 24
Finished Jul 11 05:40:48 PM PDT 24
Peak memory 191212 kb
Host smart-ceebf1e2-a9d6-447c-927d-27dfd06d822b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119895822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.2119895822
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1785553039
Short name T173
Test name
Test status
Simulation time 93089522460 ps
CPU time 1057.06 seconds
Started Jul 11 05:27:39 PM PDT 24
Finished Jul 11 05:45:21 PM PDT 24
Peak memory 191536 kb
Host smart-e78ac166-e9e7-4a9c-a1c2-05fcb558ddb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785553039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1785553039
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.786018596
Short name T423
Test name
Test status
Simulation time 45467005462 ps
CPU time 66.53 seconds
Started Jul 11 05:27:52 PM PDT 24
Finished Jul 11 05:28:59 PM PDT 24
Peak memory 183036 kb
Host smart-77a10a05-894f-48a1-921e-bffc0ed59cf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786018596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all.
786018596
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.2521145791
Short name T38
Test name
Test status
Simulation time 15134062155 ps
CPU time 108.38 seconds
Started Jul 11 05:27:42 PM PDT 24
Finished Jul 11 05:29:36 PM PDT 24
Peak memory 196892 kb
Host smart-90bd788a-a659-43e2-98a6-605458f0ec1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521145791 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.2521145791
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1019545072
Short name T12
Test name
Test status
Simulation time 89702569172 ps
CPU time 146.39 seconds
Started Jul 11 05:27:42 PM PDT 24
Finished Jul 11 05:30:13 PM PDT 24
Peak memory 183092 kb
Host smart-ea63a08b-480d-48d7-8d3f-d40d58c01916
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019545072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1019545072
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2469653250
Short name T417
Test name
Test status
Simulation time 217496754564 ps
CPU time 81.37 seconds
Started Jul 11 05:27:41 PM PDT 24
Finished Jul 11 05:29:07 PM PDT 24
Peak memory 183024 kb
Host smart-ce811e4b-0c08-4499-bb64-0ad679b0a131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469653250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2469653250
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2983149262
Short name T48
Test name
Test status
Simulation time 49763736647 ps
CPU time 73.53 seconds
Started Jul 11 05:27:48 PM PDT 24
Finished Jul 11 05:29:03 PM PDT 24
Peak memory 191312 kb
Host smart-e32a064d-387c-4233-bd79-628a7d646055
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983149262 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2983149262
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3179575398
Short name T81
Test name
Test status
Simulation time 156585285905 ps
CPU time 584.65 seconds
Started Jul 11 05:27:40 PM PDT 24
Finished Jul 11 05:37:30 PM PDT 24
Peak memory 183096 kb
Host smart-2991e2fd-a8e6-4b89-9f12-d7b9d224a0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179575398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3179575398
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3448913067
Short name T68
Test name
Test status
Simulation time 1080837269626 ps
CPU time 530.66 seconds
Started Jul 11 05:27:53 PM PDT 24
Finished Jul 11 05:36:44 PM PDT 24
Peak memory 194656 kb
Host smart-87db0416-972e-4668-b90d-360fc0af581c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448913067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3448913067
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1862585604
Short name T125
Test name
Test status
Simulation time 2055274776107 ps
CPU time 1065.84 seconds
Started Jul 11 05:28:01 PM PDT 24
Finished Jul 11 05:45:48 PM PDT 24
Peak memory 183072 kb
Host smart-35e61bc6-d69b-407a-8115-39d3ad62bbb3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862585604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1862585604
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_random.4232299040
Short name T317
Test name
Test status
Simulation time 441661258629 ps
CPU time 205.87 seconds
Started Jul 11 05:27:47 PM PDT 24
Finished Jul 11 05:31:16 PM PDT 24
Peak memory 191184 kb
Host smart-4dfb0ec1-06c5-48f0-a711-7fe6017ce688
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232299040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4232299040
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.4121045557
Short name T388
Test name
Test status
Simulation time 8879183833 ps
CPU time 10.13 seconds
Started Jul 11 05:27:59 PM PDT 24
Finished Jul 11 05:28:10 PM PDT 24
Peak memory 194516 kb
Host smart-0c5c0e98-c63b-4660-a517-52b727d1eff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121045557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.4121045557
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.3646003126
Short name T386
Test name
Test status
Simulation time 312158120382 ps
CPU time 397.36 seconds
Started Jul 11 05:28:00 PM PDT 24
Finished Jul 11 05:34:39 PM PDT 24
Peak memory 191292 kb
Host smart-416578ca-8ec6-4ae2-a105-b1150d8e347c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646003126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.3646003126
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.3972573188
Short name T37
Test name
Test status
Simulation time 62033608460 ps
CPU time 485.2 seconds
Started Jul 11 05:28:00 PM PDT 24
Finished Jul 11 05:36:07 PM PDT 24
Peak memory 206544 kb
Host smart-4ca85284-b701-469b-9f32-3bc7548daf3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972573188 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.3972573188
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.392164519
Short name T126
Test name
Test status
Simulation time 1562848680993 ps
CPU time 797.6 seconds
Started Jul 11 05:28:00 PM PDT 24
Finished Jul 11 05:41:20 PM PDT 24
Peak memory 183100 kb
Host smart-3aa2b0dc-552a-4a8c-98c7-1c9540336a23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392164519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.rv_timer_cfg_update_on_fly.392164519
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.450933515
Short name T357
Test name
Test status
Simulation time 100355700537 ps
CPU time 129.5 seconds
Started Jul 11 05:28:00 PM PDT 24
Finished Jul 11 05:30:12 PM PDT 24
Peak memory 183120 kb
Host smart-58b3e165-dbe3-4975-9e60-2eb6b8191908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450933515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.450933515
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3372230558
Short name T396
Test name
Test status
Simulation time 45714795498 ps
CPU time 62.08 seconds
Started Jul 11 05:27:59 PM PDT 24
Finished Jul 11 05:29:02 PM PDT 24
Peak memory 194856 kb
Host smart-afd592fa-2b7c-4ed2-ac58-836ac938fd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372230558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3372230558
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.163027627
Short name T65
Test name
Test status
Simulation time 1235673314354 ps
CPU time 882 seconds
Started Jul 11 05:28:01 PM PDT 24
Finished Jul 11 05:42:45 PM PDT 24
Peak memory 191304 kb
Host smart-77b2417a-5b7b-4684-aaf1-35fffaf6fa1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163027627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.
163027627
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1070541965
Short name T115
Test name
Test status
Simulation time 132910349406 ps
CPU time 126.14 seconds
Started Jul 11 05:28:02 PM PDT 24
Finished Jul 11 05:30:09 PM PDT 24
Peak memory 183108 kb
Host smart-c1e63579-babf-49f9-9c70-e4bb87d5ec90
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070541965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1070541965
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.1058204448
Short name T370
Test name
Test status
Simulation time 656240317632 ps
CPU time 264.04 seconds
Started Jul 11 05:28:00 PM PDT 24
Finished Jul 11 05:32:26 PM PDT 24
Peak memory 183100 kb
Host smart-cc048995-8c46-4d9b-ba53-ebd9f03fc0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058204448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.1058204448
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1218824493
Short name T255
Test name
Test status
Simulation time 56390899972 ps
CPU time 48.76 seconds
Started Jul 11 05:28:01 PM PDT 24
Finished Jul 11 05:28:51 PM PDT 24
Peak memory 191204 kb
Host smart-e6d5a629-efe3-4b57-80de-25921f35c290
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218824493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1218824493
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.4022173116
Short name T49
Test name
Test status
Simulation time 288482034 ps
CPU time 1.89 seconds
Started Jul 11 05:27:58 PM PDT 24
Finished Jul 11 05:28:01 PM PDT 24
Peak memory 194028 kb
Host smart-6ae65fd9-d0cd-4e63-99fd-9abade3a503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022173116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.4022173116
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.4039881968
Short name T331
Test name
Test status
Simulation time 11599726020 ps
CPU time 9.44 seconds
Started Jul 11 05:30:14 PM PDT 24
Finished Jul 11 05:30:26 PM PDT 24
Peak memory 183088 kb
Host smart-03936ee8-7b85-43a7-815b-45986afdcd3c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039881968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.4039881968
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_random.376275989
Short name T129
Test name
Test status
Simulation time 1041739861375 ps
CPU time 428.48 seconds
Started Jul 11 05:28:03 PM PDT 24
Finished Jul 11 05:35:13 PM PDT 24
Peak memory 191192 kb
Host smart-fe6888a0-98f0-42f3-851a-ae61d368674e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376275989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.376275989
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.1873997763
Short name T27
Test name
Test status
Simulation time 38121246856 ps
CPU time 57.02 seconds
Started Jul 11 05:28:01 PM PDT 24
Finished Jul 11 05:29:00 PM PDT 24
Peak memory 183116 kb
Host smart-9a792722-4830-46b6-9768-9c1750fa6e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873997763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.1873997763
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.1622935582
Short name T73
Test name
Test status
Simulation time 592528195464 ps
CPU time 277.25 seconds
Started Jul 11 05:27:58 PM PDT 24
Finished Jul 11 05:32:36 PM PDT 24
Peak memory 183044 kb
Host smart-729bbaf5-4ae9-44c3-ab38-009989d9b266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622935582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.1622935582
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2137946776
Short name T408
Test name
Test status
Simulation time 36379889554 ps
CPU time 30.36 seconds
Started Jul 11 05:28:12 PM PDT 24
Finished Jul 11 05:28:43 PM PDT 24
Peak memory 183016 kb
Host smart-58faff52-70ed-4fef-a7ce-3067a41f30a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137946776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2137946776
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1013847583
Short name T395
Test name
Test status
Simulation time 844615605842 ps
CPU time 251.68 seconds
Started Jul 11 05:28:04 PM PDT 24
Finished Jul 11 05:32:18 PM PDT 24
Peak memory 183116 kb
Host smart-0655c69e-693e-45c8-8b19-7b93a491a66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013847583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1013847583
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.494234349
Short name T338
Test name
Test status
Simulation time 41974008315 ps
CPU time 61.98 seconds
Started Jul 11 05:28:09 PM PDT 24
Finished Jul 11 05:29:13 PM PDT 24
Peak memory 183116 kb
Host smart-24dbd409-7c89-4c7e-bf55-7a33567a2615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494234349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.494234349
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.795430719
Short name T46
Test name
Test status
Simulation time 17906396872 ps
CPU time 28.07 seconds
Started Jul 11 05:28:08 PM PDT 24
Finished Jul 11 05:28:37 PM PDT 24
Peak memory 183004 kb
Host smart-54092150-6adf-433b-8535-8c3567a6b793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795430719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.795430719
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2177368628
Short name T407
Test name
Test status
Simulation time 63560785 ps
CPU time 0.61 seconds
Started Jul 11 05:28:08 PM PDT 24
Finished Jul 11 05:28:11 PM PDT 24
Peak memory 182880 kb
Host smart-fe80b42c-7c92-4f13-8227-7d5c47404964
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177368628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2177368628
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2584287958
Short name T385
Test name
Test status
Simulation time 72781114782 ps
CPU time 60.69 seconds
Started Jul 11 05:28:12 PM PDT 24
Finished Jul 11 05:29:14 PM PDT 24
Peak memory 183016 kb
Host smart-699b9e5f-b450-4492-8564-ad0c79556e8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584287958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2584287958
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.2530289149
Short name T366
Test name
Test status
Simulation time 42079974999 ps
CPU time 59.91 seconds
Started Jul 11 05:28:04 PM PDT 24
Finished Jul 11 05:29:07 PM PDT 24
Peak memory 183120 kb
Host smart-eb09737f-8b89-4901-aa35-e556ec62d816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530289149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.2530289149
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.654771965
Short name T169
Test name
Test status
Simulation time 379499774677 ps
CPU time 587.88 seconds
Started Jul 11 05:28:07 PM PDT 24
Finished Jul 11 05:37:57 PM PDT 24
Peak memory 191296 kb
Host smart-97e37f9f-fa39-4003-80ae-1239abc148b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654771965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.654771965
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3529094275
Short name T211
Test name
Test status
Simulation time 79128623770 ps
CPU time 36.13 seconds
Started Jul 11 05:28:08 PM PDT 24
Finished Jul 11 05:28:46 PM PDT 24
Peak memory 183040 kb
Host smart-a19c3571-c91e-44a8-a0bd-23416bd0b658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529094275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3529094275
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.2713568198
Short name T207
Test name
Test status
Simulation time 314129274375 ps
CPU time 255.74 seconds
Started Jul 11 05:28:04 PM PDT 24
Finished Jul 11 05:32:21 PM PDT 24
Peak memory 183024 kb
Host smart-906f7cff-b155-4a89-b74c-50ea5a785f19
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713568198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.2713568198
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.421443292
Short name T443
Test name
Test status
Simulation time 133552306514 ps
CPU time 185.57 seconds
Started Jul 11 05:28:09 PM PDT 24
Finished Jul 11 05:31:16 PM PDT 24
Peak memory 183204 kb
Host smart-9157fd70-73d7-40c1-b90b-96c6cc2b38b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421443292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.421443292
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1453709986
Short name T445
Test name
Test status
Simulation time 46955358862 ps
CPU time 294.45 seconds
Started Jul 11 05:28:06 PM PDT 24
Finished Jul 11 05:33:03 PM PDT 24
Peak memory 191288 kb
Host smart-3da49b09-d621-4b4a-a39a-9036993ae9d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453709986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1453709986
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2397367887
Short name T147
Test name
Test status
Simulation time 75167923651 ps
CPU time 533.85 seconds
Started Jul 11 05:28:08 PM PDT 24
Finished Jul 11 05:37:04 PM PDT 24
Peak memory 191248 kb
Host smart-ff244981-7ebf-4009-a0a3-0dd098f1bdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397367887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2397367887
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1667967129
Short name T174
Test name
Test status
Simulation time 432655924139 ps
CPU time 673.7 seconds
Started Jul 11 05:28:05 PM PDT 24
Finished Jul 11 05:39:21 PM PDT 24
Peak memory 191228 kb
Host smart-dbfa74d3-e624-44ff-9e43-4b0552ea35cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667967129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1667967129
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.3780960125
Short name T2
Test name
Test status
Simulation time 41527231016 ps
CPU time 67.14 seconds
Started Jul 11 05:28:09 PM PDT 24
Finished Jul 11 05:29:18 PM PDT 24
Peak memory 183104 kb
Host smart-d8284ad1-5cf0-4c69-ad5b-fdb5b6ff98f3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780960125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.3780960125
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1654837148
Short name T367
Test name
Test status
Simulation time 620440183945 ps
CPU time 267.88 seconds
Started Jul 11 05:28:08 PM PDT 24
Finished Jul 11 05:32:38 PM PDT 24
Peak memory 183120 kb
Host smart-791cdabf-34c8-49a4-8165-190bbe3c760d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654837148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1654837148
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3128043200
Short name T237
Test name
Test status
Simulation time 672480469719 ps
CPU time 337.6 seconds
Started Jul 11 05:28:11 PM PDT 24
Finished Jul 11 05:33:50 PM PDT 24
Peak memory 191300 kb
Host smart-908f0e96-9c78-4af8-b3e9-91df1d18977e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128043200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3128043200
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1699960534
Short name T438
Test name
Test status
Simulation time 101545842 ps
CPU time 1.51 seconds
Started Jul 11 05:28:10 PM PDT 24
Finished Jul 11 05:28:13 PM PDT 24
Peak memory 183064 kb
Host smart-a228c8f0-b8b4-4681-8c3c-a14b20d9a93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699960534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1699960534
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.2943775852
Short name T260
Test name
Test status
Simulation time 528615513950 ps
CPU time 474.41 seconds
Started Jul 11 05:27:13 PM PDT 24
Finished Jul 11 05:35:09 PM PDT 24
Peak memory 183080 kb
Host smart-bbe350a8-dd51-49db-a279-3de199e26769
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943775852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.2943775852
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1689236294
Short name T402
Test name
Test status
Simulation time 370700131452 ps
CPU time 255.05 seconds
Started Jul 11 05:27:17 PM PDT 24
Finished Jul 11 05:31:36 PM PDT 24
Peak memory 183088 kb
Host smart-c848e18b-5a80-4f4c-b5c7-243c6b83f7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689236294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1689236294
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.551606038
Short name T399
Test name
Test status
Simulation time 89313317757 ps
CPU time 66.95 seconds
Started Jul 11 05:27:14 PM PDT 24
Finished Jul 11 05:28:22 PM PDT 24
Peak memory 191324 kb
Host smart-bab117c9-0303-41a0-a69b-61f7edf192c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551606038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.551606038
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.214658025
Short name T244
Test name
Test status
Simulation time 78086337221 ps
CPU time 123.77 seconds
Started Jul 11 05:27:14 PM PDT 24
Finished Jul 11 05:29:20 PM PDT 24
Peak memory 193560 kb
Host smart-01a40f7f-5f42-445a-8e3c-097fa7341119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214658025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.214658025
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all_with_rand_reset.1687670719
Short name T40
Test name
Test status
Simulation time 85217043989 ps
CPU time 1281.5 seconds
Started Jul 11 05:27:14 PM PDT 24
Finished Jul 11 05:48:38 PM PDT 24
Peak memory 206716 kb
Host smart-86506381-3638-423c-80aa-d15cea772e51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687670719 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all_with_rand_reset.1687670719
Directory /workspace/5.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.2549912998
Short name T428
Test name
Test status
Simulation time 44981069797 ps
CPU time 76.73 seconds
Started Jul 11 05:28:03 PM PDT 24
Finished Jul 11 05:29:21 PM PDT 24
Peak memory 183108 kb
Host smart-67cb1409-1ec4-47f8-810f-7dd7c65d0b79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549912998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.2549912998
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2858357307
Short name T193
Test name
Test status
Simulation time 363935901736 ps
CPU time 208.62 seconds
Started Jul 11 05:28:08 PM PDT 24
Finished Jul 11 05:31:39 PM PDT 24
Peak memory 191392 kb
Host smart-78a960eb-db0a-4238-a891-e9115ef32da0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858357307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2858357307
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1395992536
Short name T429
Test name
Test status
Simulation time 177240309897 ps
CPU time 492.62 seconds
Started Jul 11 05:28:07 PM PDT 24
Finished Jul 11 05:36:21 PM PDT 24
Peak memory 183088 kb
Host smart-8b09bc1b-4a7d-4f18-a209-57a8ead8be02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395992536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1395992536
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2335555117
Short name T57
Test name
Test status
Simulation time 119308174254 ps
CPU time 745.63 seconds
Started Jul 11 05:28:15 PM PDT 24
Finished Jul 11 05:40:43 PM PDT 24
Peak memory 183080 kb
Host smart-bb2fec6f-e554-4b23-bc9b-8991840b20e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335555117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2335555117
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.2982625656
Short name T44
Test name
Test status
Simulation time 63929834968 ps
CPU time 99.01 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:30:09 PM PDT 24
Peak memory 194920 kb
Host smart-b3993782-ad24-4960-a04e-51cea90a3a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982625656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.2982625656
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1248894312
Short name T433
Test name
Test status
Simulation time 65352726480 ps
CPU time 264.44 seconds
Started Jul 11 05:28:14 PM PDT 24
Finished Jul 11 05:32:40 PM PDT 24
Peak memory 191304 kb
Host smart-7db1966f-61b2-4baf-b147-9d3497eac733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248894312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1248894312
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.978754112
Short name T159
Test name
Test status
Simulation time 348799806438 ps
CPU time 399.64 seconds
Started Jul 11 05:28:14 PM PDT 24
Finished Jul 11 05:34:55 PM PDT 24
Peak memory 191304 kb
Host smart-b466c9e5-9621-4022-9b0f-7f56cf7f613c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978754112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.978754112
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2206705773
Short name T164
Test name
Test status
Simulation time 943531479997 ps
CPU time 365.2 seconds
Started Jul 11 05:28:22 PM PDT 24
Finished Jul 11 05:34:29 PM PDT 24
Peak memory 191216 kb
Host smart-da854657-2741-4fef-816f-83491bf11be8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206705773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2206705773
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.686322820
Short name T330
Test name
Test status
Simulation time 533668603826 ps
CPU time 462.76 seconds
Started Jul 11 05:27:15 PM PDT 24
Finished Jul 11 05:35:00 PM PDT 24
Peak memory 183048 kb
Host smart-258e70cd-7d19-4bfa-b126-1d0f43d07911
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686322820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.686322820
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3110945229
Short name T389
Test name
Test status
Simulation time 28703382815 ps
CPU time 43.87 seconds
Started Jul 11 05:27:15 PM PDT 24
Finished Jul 11 05:28:01 PM PDT 24
Peak memory 183196 kb
Host smart-7c9e9fcf-9e9b-4206-b1a5-d6d1386bee79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110945229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3110945229
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3242043706
Short name T192
Test name
Test status
Simulation time 53502951300 ps
CPU time 60.17 seconds
Started Jul 11 05:27:14 PM PDT 24
Finished Jul 11 05:28:16 PM PDT 24
Peak memory 183108 kb
Host smart-43d06320-237c-4ab7-92c5-895239ff5aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242043706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3242043706
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1098993600
Short name T362
Test name
Test status
Simulation time 1154331304 ps
CPU time 3.25 seconds
Started Jul 11 05:27:19 PM PDT 24
Finished Jul 11 05:27:26 PM PDT 24
Peak memory 183060 kb
Host smart-db63f29e-1b6a-428e-8538-a59a4095d226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098993600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1098993600
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.56162109
Short name T22
Test name
Test status
Simulation time 27567973403 ps
CPU time 43.48 seconds
Started Jul 11 05:27:28 PM PDT 24
Finished Jul 11 05:28:17 PM PDT 24
Peak memory 191304 kb
Host smart-535e48f4-cfb0-4ced-8476-d9134047ee4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56162109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.56162109
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2661420948
Short name T13
Test name
Test status
Simulation time 128093365639 ps
CPU time 525.16 seconds
Started Jul 11 05:27:14 PM PDT 24
Finished Jul 11 05:36:00 PM PDT 24
Peak memory 212116 kb
Host smart-e03d9c8f-4bcd-4ec9-ba35-003be6c33734
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661420948 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2661420948
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.1747202747
Short name T219
Test name
Test status
Simulation time 117889672044 ps
CPU time 223.5 seconds
Started Jul 11 05:28:17 PM PDT 24
Finished Jul 11 05:32:02 PM PDT 24
Peak memory 191220 kb
Host smart-e66fd6b8-bc47-4e5c-b38b-efffdcfc964d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747202747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1747202747
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.4034266253
Short name T205
Test name
Test status
Simulation time 45371699498 ps
CPU time 23.22 seconds
Started Jul 11 05:28:17 PM PDT 24
Finished Jul 11 05:28:42 PM PDT 24
Peak memory 183012 kb
Host smart-c65cde5c-2ece-46e0-a588-11fb5254ada3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034266253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.4034266253
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1844926591
Short name T210
Test name
Test status
Simulation time 390556564170 ps
CPU time 1797.82 seconds
Started Jul 11 05:28:16 PM PDT 24
Finished Jul 11 05:58:16 PM PDT 24
Peak memory 191220 kb
Host smart-1f6ef36b-735f-4979-ada8-612effbe3c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844926591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1844926591
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3723407909
Short name T248
Test name
Test status
Simulation time 283951395211 ps
CPU time 98.54 seconds
Started Jul 11 05:28:21 PM PDT 24
Finished Jul 11 05:30:02 PM PDT 24
Peak memory 191220 kb
Host smart-f15f3836-409c-4f85-aa25-ffcbad9cc7b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723407909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3723407909
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.97406903
Short name T292
Test name
Test status
Simulation time 637295106676 ps
CPU time 187.96 seconds
Started Jul 11 05:31:04 PM PDT 24
Finished Jul 11 05:34:13 PM PDT 24
Peak memory 191188 kb
Host smart-6682d84d-99cc-4a39-ad1e-3c40255c39ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97406903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.97406903
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.387782557
Short name T157
Test name
Test status
Simulation time 43074055604 ps
CPU time 185.58 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:31:36 PM PDT 24
Peak memory 191200 kb
Host smart-1e90c354-8392-4b1f-a29a-e55004e52e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387782557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.387782557
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.864439290
Short name T277
Test name
Test status
Simulation time 183775683396 ps
CPU time 108.84 seconds
Started Jul 11 05:28:22 PM PDT 24
Finished Jul 11 05:30:13 PM PDT 24
Peak memory 191188 kb
Host smart-9e2abaf3-cc7b-43b6-a02a-4abaa546a2ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864439290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.864439290
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.4290548734
Short name T127
Test name
Test status
Simulation time 712217772365 ps
CPU time 486.28 seconds
Started Jul 11 05:28:14 PM PDT 24
Finished Jul 11 05:36:22 PM PDT 24
Peak memory 193464 kb
Host smart-2f4e2119-d412-41c3-8a4b-d2cdfa489456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290548734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.4290548734
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2309747863
Short name T264
Test name
Test status
Simulation time 12930064886 ps
CPU time 15.35 seconds
Started Jul 11 05:28:15 PM PDT 24
Finished Jul 11 05:28:32 PM PDT 24
Peak memory 183088 kb
Host smart-e1c621e8-a68f-4897-aac5-e0b340a2acf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309747863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2309747863
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.321390773
Short name T59
Test name
Test status
Simulation time 251499292837 ps
CPU time 407.48 seconds
Started Jul 11 05:27:28 PM PDT 24
Finished Jul 11 05:34:20 PM PDT 24
Peak memory 183100 kb
Host smart-d480741c-c640-4d62-a1b0-44e2ed6ebc7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321390773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.rv_timer_cfg_update_on_fly.321390773
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.967796036
Short name T364
Test name
Test status
Simulation time 60560071061 ps
CPU time 42.63 seconds
Started Jul 11 05:27:24 PM PDT 24
Finished Jul 11 05:28:10 PM PDT 24
Peak memory 183120 kb
Host smart-560cd760-1dd2-4f8d-a6ae-6fcc8583c92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967796036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.967796036
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2712790718
Short name T294
Test name
Test status
Simulation time 60025349908 ps
CPU time 165.22 seconds
Started Jul 11 05:27:17 PM PDT 24
Finished Jul 11 05:30:05 PM PDT 24
Peak memory 191256 kb
Host smart-343cd6d5-9ee6-4613-b98e-4bdb06b43340
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712790718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2712790718
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.3293506344
Short name T410
Test name
Test status
Simulation time 219132832482 ps
CPU time 112.75 seconds
Started Jul 11 05:27:19 PM PDT 24
Finished Jul 11 05:29:15 PM PDT 24
Peak memory 194440 kb
Host smart-0c87ceb6-100c-4a41-bccd-9d9a51c3c41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293506344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.3293506344
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/71.rv_timer_random.3592747067
Short name T110
Test name
Test status
Simulation time 53796788947 ps
CPU time 215.88 seconds
Started Jul 11 05:28:14 PM PDT 24
Finished Jul 11 05:31:51 PM PDT 24
Peak memory 191312 kb
Host smart-dce8ff15-5d69-4688-b774-f58423675222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592747067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3592747067
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.766542349
Short name T60
Test name
Test status
Simulation time 45511048887 ps
CPU time 65.84 seconds
Started Jul 11 05:28:28 PM PDT 24
Finished Jul 11 05:29:36 PM PDT 24
Peak memory 183000 kb
Host smart-88ca61b6-4ee8-4b66-abd4-d3449494e1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766542349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.766542349
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.4093674946
Short name T238
Test name
Test status
Simulation time 21794603258 ps
CPU time 43.62 seconds
Started Jul 11 05:28:18 PM PDT 24
Finished Jul 11 05:29:04 PM PDT 24
Peak memory 191248 kb
Host smart-808c78cd-57fc-4cfb-b695-8791da913ccf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093674946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4093674946
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1181388685
Short name T295
Test name
Test status
Simulation time 76916536604 ps
CPU time 186.67 seconds
Started Jul 11 05:28:21 PM PDT 24
Finished Jul 11 05:31:30 PM PDT 24
Peak memory 191228 kb
Host smart-c6af0064-fce1-4ef3-8dc9-44f9d845a52e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181388685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1181388685
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.3769689875
Short name T123
Test name
Test status
Simulation time 294157335763 ps
CPU time 158.56 seconds
Started Jul 11 05:28:20 PM PDT 24
Finished Jul 11 05:31:01 PM PDT 24
Peak memory 191232 kb
Host smart-a2e766ea-6003-4f41-89f4-8dfe56e7a7d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769689875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.3769689875
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3523969377
Short name T179
Test name
Test status
Simulation time 398289286950 ps
CPU time 135.63 seconds
Started Jul 11 05:28:19 PM PDT 24
Finished Jul 11 05:30:37 PM PDT 24
Peak memory 191308 kb
Host smart-403c9f30-9f07-4e16-af1e-1f00fd7b1f99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523969377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3523969377
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.3922609992
Short name T122
Test name
Test status
Simulation time 344210543302 ps
CPU time 287.52 seconds
Started Jul 11 05:28:18 PM PDT 24
Finished Jul 11 05:33:08 PM PDT 24
Peak memory 191212 kb
Host smart-592bdc9a-c4a6-43e0-a129-cf0d2b17e822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922609992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.3922609992
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1810150257
Short name T227
Test name
Test status
Simulation time 104081820834 ps
CPU time 191.01 seconds
Started Jul 11 05:27:17 PM PDT 24
Finished Jul 11 05:30:31 PM PDT 24
Peak memory 183036 kb
Host smart-6b0f4186-0e28-4214-8e26-c21801ed9996
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810150257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1810150257
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2803027325
Short name T79
Test name
Test status
Simulation time 40327257039 ps
CPU time 62 seconds
Started Jul 11 05:27:14 PM PDT 24
Finished Jul 11 05:28:18 PM PDT 24
Peak memory 183064 kb
Host smart-6ed821d6-41e1-4e49-81aa-dccb9dfd7e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803027325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2803027325
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.1737562865
Short name T245
Test name
Test status
Simulation time 435136338139 ps
CPU time 383.07 seconds
Started Jul 11 05:27:15 PM PDT 24
Finished Jul 11 05:33:40 PM PDT 24
Peak memory 193432 kb
Host smart-b8f84b95-7298-4349-be0b-017ed31a004b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737562865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.1737562865
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.1621943486
Short name T414
Test name
Test status
Simulation time 236558848260 ps
CPU time 123.17 seconds
Started Jul 11 05:28:06 PM PDT 24
Finished Jul 11 05:30:11 PM PDT 24
Peak memory 183116 kb
Host smart-8d35af5b-b84e-490e-a627-ba6d30adb12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621943486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.1621943486
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all_with_rand_reset.3708729433
Short name T35
Test name
Test status
Simulation time 23190416134 ps
CPU time 166.3 seconds
Started Jul 11 05:27:18 PM PDT 24
Finished Jul 11 05:30:08 PM PDT 24
Peak memory 197660 kb
Host smart-34ab96f0-8467-42ce-bba4-409c29960f4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708729433 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all_with_rand_reset.3708729433
Directory /workspace/8.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.rv_timer_random.4079796671
Short name T391
Test name
Test status
Simulation time 10551568416 ps
CPU time 17.49 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:28:48 PM PDT 24
Peak memory 183004 kb
Host smart-37cc4c2e-86d5-42a7-a8d3-31adbb281644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079796671 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.4079796671
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.1520378830
Short name T437
Test name
Test status
Simulation time 2128508598941 ps
CPU time 1597.37 seconds
Started Jul 11 05:28:18 PM PDT 24
Finished Jul 11 05:54:58 PM PDT 24
Peak memory 191236 kb
Host smart-5dfe4a01-3e0d-490d-aee4-b088c4af04f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520378830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.1520378830
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3739360052
Short name T151
Test name
Test status
Simulation time 3215590281 ps
CPU time 1.97 seconds
Started Jul 11 05:28:19 PM PDT 24
Finished Jul 11 05:28:23 PM PDT 24
Peak memory 183108 kb
Host smart-3c633612-5156-4c02-99c7-7481c2c60ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739360052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3739360052
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1234256070
Short name T143
Test name
Test status
Simulation time 286003904976 ps
CPU time 245.57 seconds
Started Jul 11 05:28:21 PM PDT 24
Finished Jul 11 05:32:29 PM PDT 24
Peak memory 191192 kb
Host smart-6d82947a-7986-43a3-8153-bdab01f9246c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234256070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1234256070
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2426265071
Short name T170
Test name
Test status
Simulation time 211488006137 ps
CPU time 2013.44 seconds
Started Jul 11 05:28:28 PM PDT 24
Finished Jul 11 06:02:04 PM PDT 24
Peak memory 191204 kb
Host smart-bc76bfd3-5aa1-48b6-b32b-676303320a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426265071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2426265071
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.787572654
Short name T208
Test name
Test status
Simulation time 24168930407 ps
CPU time 151.83 seconds
Started Jul 11 05:28:20 PM PDT 24
Finished Jul 11 05:30:54 PM PDT 24
Peak memory 191236 kb
Host smart-b21b59b5-252e-4720-8f62-f1988cf48e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787572654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.787572654
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.143417362
Short name T334
Test name
Test status
Simulation time 320135498324 ps
CPU time 274.13 seconds
Started Jul 11 05:28:15 PM PDT 24
Finished Jul 11 05:32:52 PM PDT 24
Peak memory 191300 kb
Host smart-58479df3-a92c-4827-b2e9-3349ef1e717f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143417362 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.143417362
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2200618883
Short name T349
Test name
Test status
Simulation time 43284462415 ps
CPU time 37.36 seconds
Started Jul 11 05:27:16 PM PDT 24
Finished Jul 11 05:27:56 PM PDT 24
Peak memory 183104 kb
Host smart-c4c4c261-5781-4600-b855-9626fc1a8a32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200618883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2200618883
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.130266076
Short name T382
Test name
Test status
Simulation time 143510261434 ps
CPU time 57.74 seconds
Started Jul 11 05:27:15 PM PDT 24
Finished Jul 11 05:28:16 PM PDT 24
Peak memory 183048 kb
Host smart-64d3e49e-34f4-426a-b4d6-31d1944439ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130266076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.130266076
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.907822690
Short name T350
Test name
Test status
Simulation time 2940094566 ps
CPU time 102.98 seconds
Started Jul 11 05:27:16 PM PDT 24
Finished Jul 11 05:29:02 PM PDT 24
Peak memory 183104 kb
Host smart-9a7fa43a-5cba-4944-8384-bcdc0cbc03ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907822690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.907822690
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1769529442
Short name T441
Test name
Test status
Simulation time 397057847860 ps
CPU time 266.85 seconds
Started Jul 11 05:27:12 PM PDT 24
Finished Jul 11 05:31:40 PM PDT 24
Peak memory 191304 kb
Host smart-d033c813-7b61-4906-ae77-83d68e411801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769529442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1769529442
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.3090105114
Short name T390
Test name
Test status
Simulation time 347891437384 ps
CPU time 132.44 seconds
Started Jul 11 05:27:16 PM PDT 24
Finished Jul 11 05:29:31 PM PDT 24
Peak memory 194576 kb
Host smart-f454cfcc-2a89-4c9b-8f8c-23634a626650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090105114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
3090105114
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.497263413
Short name T75
Test name
Test status
Simulation time 99502784216 ps
CPU time 432.03 seconds
Started Jul 11 05:27:18 PM PDT 24
Finished Jul 11 05:34:33 PM PDT 24
Peak memory 205940 kb
Host smart-b1ebdfa2-ce94-4228-a7e5-8641b31361dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497263413 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.497263413
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2346254439
Short name T58
Test name
Test status
Simulation time 708244756052 ps
CPU time 2266.22 seconds
Started Jul 11 05:28:20 PM PDT 24
Finished Jul 11 06:06:09 PM PDT 24
Peak memory 191308 kb
Host smart-d80599d4-2b21-4af7-80d9-7f26b078f8b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346254439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2346254439
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.1464847354
Short name T273
Test name
Test status
Simulation time 20655338334 ps
CPU time 21.48 seconds
Started Jul 11 05:28:28 PM PDT 24
Finished Jul 11 05:28:52 PM PDT 24
Peak memory 190400 kb
Host smart-54a2c15a-1fd8-452a-ad0a-f50d0fc1b035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464847354 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.1464847354
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1080022435
Short name T321
Test name
Test status
Simulation time 44897885036 ps
CPU time 75.41 seconds
Started Jul 11 05:28:20 PM PDT 24
Finished Jul 11 05:29:37 PM PDT 24
Peak memory 191248 kb
Host smart-e5c68280-e438-4ca9-ba53-8b99ea896eb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080022435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1080022435
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.2978986516
Short name T284
Test name
Test status
Simulation time 3793143549291 ps
CPU time 890.48 seconds
Started Jul 11 05:28:35 PM PDT 24
Finished Jul 11 05:43:26 PM PDT 24
Peak memory 191224 kb
Host smart-96bded3d-eb3e-4a89-98f1-e5d935c1926d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978986516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2978986516
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1911629127
Short name T272
Test name
Test status
Simulation time 55352266087 ps
CPU time 277.98 seconds
Started Jul 11 05:28:21 PM PDT 24
Finished Jul 11 05:33:01 PM PDT 24
Peak memory 191304 kb
Host smart-9d73f364-55de-4977-bb3c-7042895c2eac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911629127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1911629127
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.4094018927
Short name T289
Test name
Test status
Simulation time 49891374099 ps
CPU time 510.51 seconds
Started Jul 11 05:28:35 PM PDT 24
Finished Jul 11 05:37:07 PM PDT 24
Peak memory 183024 kb
Host smart-08059deb-1291-4f76-ad1f-385080db7c0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094018927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.4094018927
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3553694345
Short name T183
Test name
Test status
Simulation time 511068221955 ps
CPU time 323.33 seconds
Started Jul 11 05:28:20 PM PDT 24
Finished Jul 11 05:33:46 PM PDT 24
Peak memory 191240 kb
Host smart-2fe271a4-a1ed-44a1-8db0-e09aeedf8a68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553694345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3553694345
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2799269776
Short name T269
Test name
Test status
Simulation time 299788479412 ps
CPU time 515.7 seconds
Started Jul 11 05:28:35 PM PDT 24
Finished Jul 11 05:37:11 PM PDT 24
Peak memory 191224 kb
Host smart-09e2a4a3-9c47-4618-9106-0f9ce9165b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799269776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2799269776
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1471906008
Short name T319
Test name
Test status
Simulation time 311355707743 ps
CPU time 175.62 seconds
Started Jul 11 05:28:29 PM PDT 24
Finished Jul 11 05:31:26 PM PDT 24
Peak memory 191196 kb
Host smart-7bbaa2da-268f-41b1-9904-dd705c3c0229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471906008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1471906008
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2191922451
Short name T335
Test name
Test status
Simulation time 153583213589 ps
CPU time 950.21 seconds
Started Jul 11 05:28:21 PM PDT 24
Finished Jul 11 05:44:13 PM PDT 24
Peak memory 191296 kb
Host smart-f4943b66-1fd8-4888-9da7-c2a88b1baef3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191922451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2191922451
Directory /workspace/99.rv_timer_random/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%