Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T508 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3445284313 Jul 12 05:39:19 PM PDT 24 Jul 12 05:39:21 PM PDT 24 36584781 ps
T509 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3544366620 Jul 12 05:39:11 PM PDT 24 Jul 12 05:39:12 PM PDT 24 40833787 ps
T69 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2045434322 Jul 12 05:39:33 PM PDT 24 Jul 12 05:39:37 PM PDT 24 18931568 ps
T95 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4002368429 Jul 12 05:39:23 PM PDT 24 Jul 12 05:39:25 PM PDT 24 332755017 ps
T70 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1003444144 Jul 12 05:39:11 PM PDT 24 Jul 12 05:39:12 PM PDT 24 18215041 ps
T510 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1353123816 Jul 12 05:39:23 PM PDT 24 Jul 12 05:39:25 PM PDT 24 99053981 ps
T511 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1191775080 Jul 12 05:39:09 PM PDT 24 Jul 12 05:39:10 PM PDT 24 44785627 ps
T512 /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.509503079 Jul 12 05:39:36 PM PDT 24 Jul 12 05:39:38 PM PDT 24 14295787 ps
T513 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1174004749 Jul 12 05:39:19 PM PDT 24 Jul 12 05:39:22 PM PDT 24 17790718 ps
T71 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.197372962 Jul 12 05:39:18 PM PDT 24 Jul 12 05:39:21 PM PDT 24 52295304 ps
T514 /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2649046405 Jul 12 05:39:29 PM PDT 24 Jul 12 05:39:33 PM PDT 24 308056514 ps
T515 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3310029051 Jul 12 05:39:17 PM PDT 24 Jul 12 05:39:20 PM PDT 24 295387177 ps
T516 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.795558911 Jul 12 05:39:02 PM PDT 24 Jul 12 05:39:03 PM PDT 24 45904038 ps
T517 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2741152026 Jul 12 05:39:31 PM PDT 24 Jul 12 05:39:34 PM PDT 24 14102439 ps
T518 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2257774783 Jul 12 05:39:32 PM PDT 24 Jul 12 05:39:36 PM PDT 24 64156721 ps
T519 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.210952689 Jul 12 05:39:09 PM PDT 24 Jul 12 05:39:10 PM PDT 24 13026299 ps
T520 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2593175078 Jul 12 05:39:18 PM PDT 24 Jul 12 05:39:20 PM PDT 24 44725283 ps
T521 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4024531586 Jul 12 05:39:18 PM PDT 24 Jul 12 05:39:22 PM PDT 24 271102496 ps
T522 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1465498168 Jul 12 05:39:20 PM PDT 24 Jul 12 05:39:22 PM PDT 24 11820162 ps
T72 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2687991171 Jul 12 05:39:32 PM PDT 24 Jul 12 05:39:36 PM PDT 24 15035091 ps
T523 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2823145324 Jul 12 05:39:33 PM PDT 24 Jul 12 05:39:37 PM PDT 24 66053446 ps
T524 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1046098107 Jul 12 05:39:17 PM PDT 24 Jul 12 05:39:18 PM PDT 24 26909752 ps
T525 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2493247238 Jul 12 05:39:26 PM PDT 24 Jul 12 05:39:28 PM PDT 24 159246099 ps
T526 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2018589148 Jul 12 05:39:32 PM PDT 24 Jul 12 05:39:36 PM PDT 24 75455043 ps
T527 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3270446336 Jul 12 05:39:09 PM PDT 24 Jul 12 05:39:13 PM PDT 24 292959072 ps
T528 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.221900033 Jul 12 05:39:27 PM PDT 24 Jul 12 05:39:29 PM PDT 24 169502236 ps
T529 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.841656970 Jul 12 05:39:24 PM PDT 24 Jul 12 05:39:26 PM PDT 24 31891415 ps
T530 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1144866973 Jul 12 05:39:39 PM PDT 24 Jul 12 05:39:41 PM PDT 24 23143224 ps
T531 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3270862627 Jul 12 05:39:36 PM PDT 24 Jul 12 05:39:38 PM PDT 24 43208387 ps
T532 /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3816928032 Jul 12 05:39:34 PM PDT 24 Jul 12 05:39:37 PM PDT 24 26492879 ps
T73 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3914383644 Jul 12 05:39:00 PM PDT 24 Jul 12 05:39:02 PM PDT 24 63703532 ps
T533 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3097200843 Jul 12 05:39:32 PM PDT 24 Jul 12 05:39:34 PM PDT 24 102531951 ps
T534 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1950413028 Jul 12 05:39:07 PM PDT 24 Jul 12 05:39:09 PM PDT 24 32096275 ps
T535 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1242782840 Jul 12 05:39:40 PM PDT 24 Jul 12 05:39:42 PM PDT 24 19513081 ps
T536 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1628250829 Jul 12 05:39:18 PM PDT 24 Jul 12 05:39:20 PM PDT 24 36219848 ps
T537 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3159908551 Jul 12 05:39:40 PM PDT 24 Jul 12 05:39:42 PM PDT 24 19275338 ps
T538 /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2382735319 Jul 12 05:39:32 PM PDT 24 Jul 12 05:39:36 PM PDT 24 149589302 ps
T539 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3263087612 Jul 12 05:39:32 PM PDT 24 Jul 12 05:39:36 PM PDT 24 29787662 ps
T540 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.281679747 Jul 12 05:39:35 PM PDT 24 Jul 12 05:39:38 PM PDT 24 81582861 ps
T541 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3704618636 Jul 12 05:39:23 PM PDT 24 Jul 12 05:39:24 PM PDT 24 30071963 ps
T542 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1440526170 Jul 12 05:39:25 PM PDT 24 Jul 12 05:39:27 PM PDT 24 19107073 ps
T543 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1733845759 Jul 12 05:39:17 PM PDT 24 Jul 12 05:39:19 PM PDT 24 48395241 ps
T544 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3449722614 Jul 12 05:39:38 PM PDT 24 Jul 12 05:39:39 PM PDT 24 49565257 ps
T545 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2035377225 Jul 12 05:39:36 PM PDT 24 Jul 12 05:39:38 PM PDT 24 28060195 ps
T546 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1447833021 Jul 12 05:39:34 PM PDT 24 Jul 12 05:39:38 PM PDT 24 1863237842 ps
T547 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4242973569 Jul 12 05:39:26 PM PDT 24 Jul 12 05:39:29 PM PDT 24 17070799 ps
T548 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.190071569 Jul 12 05:39:25 PM PDT 24 Jul 12 05:39:27 PM PDT 24 33978552 ps
T549 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3640400823 Jul 12 05:39:20 PM PDT 24 Jul 12 05:39:22 PM PDT 24 41278872 ps
T550 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3812047594 Jul 12 05:39:26 PM PDT 24 Jul 12 05:39:28 PM PDT 24 16301828 ps
T551 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.347096460 Jul 12 05:39:38 PM PDT 24 Jul 12 05:39:40 PM PDT 24 39885462 ps
T552 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1677489617 Jul 12 05:39:32 PM PDT 24 Jul 12 05:39:35 PM PDT 24 33310473 ps
T553 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3978261043 Jul 12 05:39:34 PM PDT 24 Jul 12 05:39:38 PM PDT 24 35082381 ps
T554 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3947300870 Jul 12 05:39:30 PM PDT 24 Jul 12 05:39:32 PM PDT 24 227691259 ps
T555 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2726089709 Jul 12 05:39:18 PM PDT 24 Jul 12 05:39:20 PM PDT 24 49706732 ps
T556 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.155151351 Jul 12 05:39:34 PM PDT 24 Jul 12 05:39:37 PM PDT 24 12073504 ps
T557 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2903879777 Jul 12 05:39:29 PM PDT 24 Jul 12 05:39:32 PM PDT 24 70961451 ps
T558 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.980476283 Jul 12 05:39:28 PM PDT 24 Jul 12 05:39:32 PM PDT 24 49346731 ps
T559 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.983359661 Jul 12 05:39:40 PM PDT 24 Jul 12 05:39:42 PM PDT 24 14152375 ps
T560 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3796550996 Jul 12 05:39:07 PM PDT 24 Jul 12 05:39:09 PM PDT 24 25829688 ps
T561 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2503037219 Jul 12 05:39:28 PM PDT 24 Jul 12 05:39:31 PM PDT 24 27995139 ps
T562 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3217910415 Jul 12 05:39:20 PM PDT 24 Jul 12 05:39:22 PM PDT 24 120824092 ps
T563 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3036366724 Jul 12 05:39:27 PM PDT 24 Jul 12 05:39:30 PM PDT 24 117555328 ps
T564 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2031757207 Jul 12 05:39:19 PM PDT 24 Jul 12 05:39:23 PM PDT 24 107351894 ps
T565 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2258327609 Jul 12 05:39:36 PM PDT 24 Jul 12 05:39:38 PM PDT 24 14380115 ps
T566 /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3685184615 Jul 12 05:39:28 PM PDT 24 Jul 12 05:39:31 PM PDT 24 160205318 ps
T567 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.4294572095 Jul 12 05:39:27 PM PDT 24 Jul 12 05:39:31 PM PDT 24 34012691 ps
T568 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1411520389 Jul 12 05:39:30 PM PDT 24 Jul 12 05:39:33 PM PDT 24 67706607 ps
T569 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4254917609 Jul 12 05:39:33 PM PDT 24 Jul 12 05:39:36 PM PDT 24 66294738 ps
T570 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1208730913 Jul 12 05:39:34 PM PDT 24 Jul 12 05:39:37 PM PDT 24 12224102 ps
T571 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2411859018 Jul 12 05:39:33 PM PDT 24 Jul 12 05:39:37 PM PDT 24 26060288 ps
T572 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3882839212 Jul 12 05:39:18 PM PDT 24 Jul 12 05:39:20 PM PDT 24 393467550 ps
T573 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1999674839 Jul 12 05:39:33 PM PDT 24 Jul 12 05:39:36 PM PDT 24 139212206 ps
T574 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2881536405 Jul 12 05:39:18 PM PDT 24 Jul 12 05:39:20 PM PDT 24 51996326 ps
T575 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.525681063 Jul 12 05:39:07 PM PDT 24 Jul 12 05:39:08 PM PDT 24 59295281 ps
T576 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4059366280 Jul 12 05:39:33 PM PDT 24 Jul 12 05:39:36 PM PDT 24 31170274 ps
T577 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4099680136 Jul 12 05:39:41 PM PDT 24 Jul 12 05:39:43 PM PDT 24 16839418 ps
T74 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1565166721 Jul 12 05:39:23 PM PDT 24 Jul 12 05:39:24 PM PDT 24 128915173 ps
T578 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2560642256 Jul 12 05:39:39 PM PDT 24 Jul 12 05:39:40 PM PDT 24 52839372 ps
T579 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2845506276 Jul 12 05:39:16 PM PDT 24 Jul 12 05:39:17 PM PDT 24 22995639 ps
T580 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2994924317 Jul 12 05:39:31 PM PDT 24 Jul 12 05:39:34 PM PDT 24 14051623 ps

Test location /workspace/coverage/default/5.rv_timer_stress_all.4055970924
Short name T5
Test name
Test status
Simulation time 533615589187 ps
CPU time 898.04 seconds
Started Jul 12 05:39:50 PM PDT 24
Finished Jul 12 05:54:49 PM PDT 24
Peak memory 191292 kb
Host smart-e7fdba42-7817-4339-b547-ee04cd7df7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055970924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
4055970924
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all_with_rand_reset.766917400
Short name T12
Test name
Test status
Simulation time 215455328743 ps
CPU time 448.48 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:47:49 PM PDT 24
Peak memory 206000 kb
Host smart-1003513c-02ff-4d8b-af59-2c2c16075717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766917400 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all_with_rand_reset.766917400
Directory /workspace/36.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.3875806462
Short name T29
Test name
Test status
Simulation time 101949159 ps
CPU time 1.35 seconds
Started Jul 12 05:39:30 PM PDT 24
Finished Jul 12 05:39:34 PM PDT 24
Peak memory 195008 kb
Host smart-eea74335-2502-4829-a80a-57a8e45438e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875806462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.3875806462
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3945183249
Short name T117
Test name
Test status
Simulation time 635520685706 ps
CPU time 1866.8 seconds
Started Jul 12 05:40:07 PM PDT 24
Finished Jul 12 06:11:16 PM PDT 24
Peak memory 196116 kb
Host smart-7d28999d-8aac-44ef-97e9-e7a32903b3ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945183249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3945183249
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2082824216
Short name T150
Test name
Test status
Simulation time 484584100784 ps
CPU time 800.07 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 05:53:55 PM PDT 24
Peak memory 194780 kb
Host smart-4086800b-43dc-4c50-b628-65fd76cf7cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082824216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2082824216
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.3075054985
Short name T35
Test name
Test status
Simulation time 1044392826735 ps
CPU time 1185.51 seconds
Started Jul 12 05:39:45 PM PDT 24
Finished Jul 12 05:59:32 PM PDT 24
Peak memory 195028 kb
Host smart-11584589-ba53-4c4f-b07f-8ed4844efbd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075054985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
3075054985
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.2977417586
Short name T184
Test name
Test status
Simulation time 3197036349332 ps
CPU time 2055.76 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 06:14:21 PM PDT 24
Peak memory 191260 kb
Host smart-c1dca34a-0713-489b-815f-e37c6a1d2750
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977417586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.2977417586
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.3038550156
Short name T48
Test name
Test status
Simulation time 2682267179782 ps
CPU time 1424.95 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 06:03:54 PM PDT 24
Peak memory 195828 kb
Host smart-5c25dd81-68eb-4af1-ae11-160ed021abe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038550156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.3038550156
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3822428984
Short name T169
Test name
Test status
Simulation time 3329774962605 ps
CPU time 1877.7 seconds
Started Jul 12 05:40:16 PM PDT 24
Finished Jul 12 06:11:35 PM PDT 24
Peak memory 191180 kb
Host smart-0670a2a2-84c6-413c-aa4d-445c3e657a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822428984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3822428984
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.91119702
Short name T182
Test name
Test status
Simulation time 695976190373 ps
CPU time 1025.95 seconds
Started Jul 12 05:39:58 PM PDT 24
Finished Jul 12 05:57:05 PM PDT 24
Peak memory 191292 kb
Host smart-89a250c3-c1a0-4129-9082-a9744c39fb27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91119702 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.91119702
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.3681282776
Short name T132
Test name
Test status
Simulation time 501965421951 ps
CPU time 336.34 seconds
Started Jul 12 05:41:11 PM PDT 24
Finished Jul 12 05:46:48 PM PDT 24
Peak memory 191300 kb
Host smart-d5d09b4d-628e-4d5d-a45c-24dded0702bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681282776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3681282776
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.908208945
Short name T34
Test name
Test status
Simulation time 14982096 ps
CPU time 0.59 seconds
Started Jul 12 05:39:09 PM PDT 24
Finished Jul 12 05:39:11 PM PDT 24
Peak memory 182212 kb
Host smart-162115c1-113f-4d75-bb0e-f71a92481f03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908208945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.908208945
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.759472530
Short name T163
Test name
Test status
Simulation time 2722784456687 ps
CPU time 1855.48 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 06:11:31 PM PDT 24
Peak memory 191288 kb
Host smart-be5a2957-7279-497b-b646-f48c9851fcdb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759472530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
759472530
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.142664405
Short name T154
Test name
Test status
Simulation time 1170480575571 ps
CPU time 1012.43 seconds
Started Jul 12 05:40:11 PM PDT 24
Finished Jul 12 05:57:05 PM PDT 24
Peak memory 191292 kb
Host smart-918b9fc0-da8c-443f-85b7-83c5387f3483
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142664405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
142664405
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.823378246
Short name T19
Test name
Test status
Simulation time 92103284 ps
CPU time 0.95 seconds
Started Jul 12 05:39:44 PM PDT 24
Finished Jul 12 05:39:46 PM PDT 24
Peak memory 214452 kb
Host smart-c9b04809-e31a-46e9-a065-56c0c50b2942
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823378246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.823378246
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/17.rv_timer_random.187915290
Short name T229
Test name
Test status
Simulation time 342701227867 ps
CPU time 204.13 seconds
Started Jul 12 05:40:02 PM PDT 24
Finished Jul 12 05:43:27 PM PDT 24
Peak memory 191308 kb
Host smart-7ea75f42-471b-4aeb-b257-f40da7bb4aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187915290 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.187915290
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.535065558
Short name T216
Test name
Test status
Simulation time 4515462721231 ps
CPU time 2559.5 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 06:22:46 PM PDT 24
Peak memory 191304 kb
Host smart-2d2a1fc7-a11d-43eb-bf11-aba6c3e7e2a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535065558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all.
535065558
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/126.rv_timer_random.4199093313
Short name T107
Test name
Test status
Simulation time 172817174201 ps
CPU time 1102.98 seconds
Started Jul 12 05:40:58 PM PDT 24
Finished Jul 12 05:59:21 PM PDT 24
Peak memory 191296 kb
Host smart-3c63e87c-895c-4f6f-bc09-81ea39e91d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199093313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.4199093313
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3134299526
Short name T43
Test name
Test status
Simulation time 2903987462139 ps
CPU time 1651.87 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 06:07:40 PM PDT 24
Peak memory 195596 kb
Host smart-613112d6-52d3-4ff2-b857-a88ff82329de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134299526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3134299526
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3994533565
Short name T222
Test name
Test status
Simulation time 532476175126 ps
CPU time 855.25 seconds
Started Jul 12 05:40:11 PM PDT 24
Finished Jul 12 05:54:28 PM PDT 24
Peak memory 191232 kb
Host smart-41af9424-78a9-4dfa-9eb9-4dc000bbf700
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994533565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3994533565
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_random.3487972042
Short name T25
Test name
Test status
Simulation time 189408278061 ps
CPU time 720.52 seconds
Started Jul 12 05:40:11 PM PDT 24
Finished Jul 12 05:52:13 PM PDT 24
Peak memory 191280 kb
Host smart-636f6f00-0a76-411e-8db4-ddac82923120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487972042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3487972042
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.672297393
Short name T257
Test name
Test status
Simulation time 390912111369 ps
CPU time 1244.93 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 06:01:07 PM PDT 24
Peak memory 191296 kb
Host smart-e923427e-c122-41db-8b38-ee24e16b93c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672297393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all.
672297393
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/111.rv_timer_random.2677857987
Short name T266
Test name
Test status
Simulation time 792478658841 ps
CPU time 1640.96 seconds
Started Jul 12 05:40:49 PM PDT 24
Finished Jul 12 06:08:11 PM PDT 24
Peak memory 191308 kb
Host smart-427ca674-8431-4629-a520-b334b97357d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677857987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2677857987
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/140.rv_timer_random.336647829
Short name T186
Test name
Test status
Simulation time 725154279003 ps
CPU time 639.83 seconds
Started Jul 12 05:41:04 PM PDT 24
Finished Jul 12 05:51:45 PM PDT 24
Peak memory 191296 kb
Host smart-41f6eb12-a527-4cc7-8079-07c622fa574b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336647829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.336647829
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3862296196
Short name T219
Test name
Test status
Simulation time 201612555770 ps
CPU time 2648.12 seconds
Started Jul 12 05:40:51 PM PDT 24
Finished Jul 12 06:24:59 PM PDT 24
Peak memory 191240 kb
Host smart-ce535c71-35a3-42a1-befa-e920a7b4e203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862296196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3862296196
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.3548953756
Short name T176
Test name
Test status
Simulation time 805156302924 ps
CPU time 3300.28 seconds
Started Jul 12 05:40:47 PM PDT 24
Finished Jul 12 06:35:48 PM PDT 24
Peak memory 191260 kb
Host smart-da9e403a-cc67-4768-8365-fac8f415decd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548953756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3548953756
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.354573898
Short name T299
Test name
Test status
Simulation time 608109285827 ps
CPU time 792.79 seconds
Started Jul 12 05:41:12 PM PDT 24
Finished Jul 12 05:54:26 PM PDT 24
Peak memory 191272 kb
Host smart-274d487b-8f3f-4ac1-a13d-6fb27a424d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354573898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.354573898
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.52922616
Short name T151
Test name
Test status
Simulation time 161959962821 ps
CPU time 1228.21 seconds
Started Jul 12 05:39:39 PM PDT 24
Finished Jul 12 06:00:09 PM PDT 24
Peak memory 191176 kb
Host smart-b42123bb-9792-4274-8c24-c772ad245111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52922616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.52922616
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random.798814906
Short name T114
Test name
Test status
Simulation time 247937801647 ps
CPU time 500.44 seconds
Started Jul 12 05:40:23 PM PDT 24
Finished Jul 12 05:48:46 PM PDT 24
Peak memory 191184 kb
Host smart-5bb75f6f-a122-45e5-807a-c6c401eb4a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798814906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.798814906
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.41863694
Short name T56
Test name
Test status
Simulation time 211605311771 ps
CPU time 408.86 seconds
Started Jul 12 05:39:55 PM PDT 24
Finished Jul 12 05:46:45 PM PDT 24
Peak memory 195232 kb
Host smart-5d489b26-a8d4-4049-900e-efb23c7b823f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41863694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.41863694
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/112.rv_timer_random.1247251964
Short name T143
Test name
Test status
Simulation time 270049200106 ps
CPU time 115.6 seconds
Started Jul 12 05:40:47 PM PDT 24
Finished Jul 12 05:42:43 PM PDT 24
Peak memory 191316 kb
Host smart-68f7f6bf-9cd7-428c-adcf-7cc4bcc669a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247251964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1247251964
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.4139505831
Short name T127
Test name
Test status
Simulation time 140057193485 ps
CPU time 282.93 seconds
Started Jul 12 05:41:27 PM PDT 24
Finished Jul 12 05:46:12 PM PDT 24
Peak memory 191292 kb
Host smart-c4eda1aa-158b-4333-9e4f-c78bcac4d6ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139505831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.4139505831
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random.2826479810
Short name T175
Test name
Test status
Simulation time 163233601087 ps
CPU time 1796.7 seconds
Started Jul 12 05:40:11 PM PDT 24
Finished Jul 12 06:10:09 PM PDT 24
Peak memory 191284 kb
Host smart-f1b5124e-c947-4082-8cb9-4485bf78c0ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826479810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2826479810
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1636445197
Short name T189
Test name
Test status
Simulation time 1885220708935 ps
CPU time 413.87 seconds
Started Jul 12 05:40:37 PM PDT 24
Finished Jul 12 05:47:32 PM PDT 24
Peak memory 191208 kb
Host smart-280abad6-346a-488a-8127-73b86ddb3bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636445197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1636445197
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.1448900736
Short name T21
Test name
Test status
Simulation time 199572118811 ps
CPU time 1707.76 seconds
Started Jul 12 05:40:42 PM PDT 24
Finished Jul 12 06:09:11 PM PDT 24
Peak memory 191316 kb
Host smart-af986d89-18b4-4bda-8245-3487d296a5a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448900736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.1448900736
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.481043134
Short name T152
Test name
Test status
Simulation time 1506874373944 ps
CPU time 2012.47 seconds
Started Jul 12 05:39:38 PM PDT 24
Finished Jul 12 06:13:12 PM PDT 24
Peak memory 191288 kb
Host smart-1c22fc74-250e-42b7-873d-c8987e4c5d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481043134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.481043134
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/105.rv_timer_random.4281470725
Short name T190
Test name
Test status
Simulation time 485780158812 ps
CPU time 301.44 seconds
Started Jul 12 05:40:49 PM PDT 24
Finished Jul 12 05:45:51 PM PDT 24
Peak memory 191288 kb
Host smart-c0459953-5d01-45b1-a77c-c7eb3bfa9028
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281470725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.4281470725
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.1984015411
Short name T218
Test name
Test status
Simulation time 148456015904 ps
CPU time 630.55 seconds
Started Jul 12 05:40:56 PM PDT 24
Finished Jul 12 05:51:27 PM PDT 24
Peak memory 191280 kb
Host smart-7b92eef5-1bcf-456f-a313-80966f952440
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984015411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1984015411
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.3114903614
Short name T214
Test name
Test status
Simulation time 360772170796 ps
CPU time 861.9 seconds
Started Jul 12 05:41:05 PM PDT 24
Finished Jul 12 05:55:27 PM PDT 24
Peak memory 191308 kb
Host smart-a7a454ef-6f2a-4561-8bd0-5f5d4f87af13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114903614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3114903614
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.805424589
Short name T109
Test name
Test status
Simulation time 102454156824 ps
CPU time 63.08 seconds
Started Jul 12 05:40:01 PM PDT 24
Finished Jul 12 05:41:04 PM PDT 24
Peak memory 183072 kb
Host smart-8cd7724f-9605-463f-ae40-29dfcb13cc63
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805424589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.rv_timer_cfg_update_on_fly.805424589
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_random.2565288714
Short name T269
Test name
Test status
Simulation time 534871884395 ps
CPU time 804.96 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 05:53:30 PM PDT 24
Peak memory 191276 kb
Host smart-63d7a0e4-8cec-4276-b463-7d5733695905
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565288714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.2565288714
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.998005491
Short name T248
Test name
Test status
Simulation time 440887737069 ps
CPU time 360.2 seconds
Started Jul 12 05:39:56 PM PDT 24
Finished Jul 12 05:45:57 PM PDT 24
Peak memory 193312 kb
Host smart-27e1baa7-f3d5-41d7-a2d7-b5436f8b8f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998005491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
998005491
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/150.rv_timer_random.4773304
Short name T262
Test name
Test status
Simulation time 55726098608 ps
CPU time 93.16 seconds
Started Jul 12 05:41:12 PM PDT 24
Finished Jul 12 05:42:46 PM PDT 24
Peak memory 191208 kb
Host smart-f7239326-0805-408e-bd5a-74bedc1eaddd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4773304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.4773304
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.3718673540
Short name T106
Test name
Test status
Simulation time 187412089194 ps
CPU time 676.88 seconds
Started Jul 12 05:41:27 PM PDT 24
Finished Jul 12 05:52:46 PM PDT 24
Peak memory 191280 kb
Host smart-f3c8a590-ef25-4eb7-94c4-eeb33f8150c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718673540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.3718673540
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3395441176
Short name T247
Test name
Test status
Simulation time 640795586194 ps
CPU time 1896.42 seconds
Started Jul 12 05:41:28 PM PDT 24
Finished Jul 12 06:13:06 PM PDT 24
Peak memory 191268 kb
Host smart-766a2d2a-1fab-4ba3-a76e-277163f7610b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395441176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3395441176
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.2865321496
Short name T180
Test name
Test status
Simulation time 140862156234 ps
CPU time 1923.36 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 06:11:46 PM PDT 24
Peak memory 191316 kb
Host smart-724718e5-1c14-49a4-beff-fbcf71b87cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865321496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2865321496
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3536287528
Short name T226
Test name
Test status
Simulation time 134314522120 ps
CPU time 215.93 seconds
Started Jul 12 05:40:16 PM PDT 24
Finished Jul 12 05:43:52 PM PDT 24
Peak memory 191180 kb
Host smart-4c03a7c8-8774-4291-829c-1f9dc700dcf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536287528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3536287528
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.715832886
Short name T97
Test name
Test status
Simulation time 563202565995 ps
CPU time 451.89 seconds
Started Jul 12 05:39:42 PM PDT 24
Finished Jul 12 05:47:16 PM PDT 24
Peak memory 183084 kb
Host smart-38e2c4ad-91c8-4801-add3-35524c7ef1af
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715832886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.715832886
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/101.rv_timer_random.3232728048
Short name T102
Test name
Test status
Simulation time 138387619775 ps
CPU time 244.75 seconds
Started Jul 12 05:40:50 PM PDT 24
Finished Jul 12 05:44:55 PM PDT 24
Peak memory 194596 kb
Host smart-8fdd6c47-5f16-43ff-84e9-5d64c034d985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232728048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3232728048
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1137954732
Short name T158
Test name
Test status
Simulation time 57092510652 ps
CPU time 397.72 seconds
Started Jul 12 05:40:51 PM PDT 24
Finished Jul 12 05:47:30 PM PDT 24
Peak memory 191284 kb
Host smart-2220c07f-32b5-451e-bce3-28107ca3850b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137954732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1137954732
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3602248315
Short name T58
Test name
Test status
Simulation time 865528810362 ps
CPU time 595.2 seconds
Started Jul 12 05:39:57 PM PDT 24
Finished Jul 12 05:49:53 PM PDT 24
Peak memory 191312 kb
Host smart-251cf6c9-a525-4aa7-b6c2-aff23b74d0ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602248315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3602248315
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/144.rv_timer_random.1818804794
Short name T144
Test name
Test status
Simulation time 101392444206 ps
CPU time 376.27 seconds
Started Jul 12 05:48:45 PM PDT 24
Finished Jul 12 05:55:02 PM PDT 24
Peak memory 193580 kb
Host smart-2d08efca-343e-4b6d-8508-af1bb21c214c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818804794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.1818804794
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.4202231594
Short name T240
Test name
Test status
Simulation time 267340085125 ps
CPU time 258.12 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 05:44:22 PM PDT 24
Peak memory 183068 kb
Host smart-8d78946d-d72e-4bdc-b20a-a305e91b45f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202231594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.4202231594
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2646024997
Short name T191
Test name
Test status
Simulation time 1063847298734 ps
CPU time 1046.3 seconds
Started Jul 12 05:41:27 PM PDT 24
Finished Jul 12 05:58:56 PM PDT 24
Peak memory 191308 kb
Host smart-49ee58be-a5a7-4ad9-ba2c-f9df4504351c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646024997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2646024997
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.2731779185
Short name T145
Test name
Test status
Simulation time 118976340363 ps
CPU time 1337.55 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 06:02:24 PM PDT 24
Peak memory 193484 kb
Host smart-fc0e8675-710f-4a1d-bac5-eb14ced2f908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731779185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2731779185
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4141184175
Short name T242
Test name
Test status
Simulation time 254842706268 ps
CPU time 367.37 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 05:46:13 PM PDT 24
Peak memory 191248 kb
Host smart-c1f2922e-1f26-49bd-88d9-b1e73c8761c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141184175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4141184175
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.4265295310
Short name T168
Test name
Test status
Simulation time 524689872102 ps
CPU time 752.12 seconds
Started Jul 12 05:40:18 PM PDT 24
Finished Jul 12 05:52:51 PM PDT 24
Peak memory 183064 kb
Host smart-41fb99cf-9608-472e-8e15-3e0cd982fb95
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265295310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.4265295310
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2219482971
Short name T156
Test name
Test status
Simulation time 1601157468515 ps
CPU time 750.81 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:52:54 PM PDT 24
Peak memory 191224 kb
Host smart-a0d24213-b2cf-4f1f-b3cd-d9ed497ea18a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219482971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2219482971
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/56.rv_timer_random.3277780168
Short name T185
Test name
Test status
Simulation time 1871141725716 ps
CPU time 1898.09 seconds
Started Jul 12 05:40:36 PM PDT 24
Finished Jul 12 06:12:15 PM PDT 24
Peak memory 191316 kb
Host smart-197afcf9-fe93-4b3e-8a93-7b27d159b318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277780168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3277780168
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.4241869864
Short name T85
Test name
Test status
Simulation time 445320836140 ps
CPU time 756.19 seconds
Started Jul 12 05:40:44 PM PDT 24
Finished Jul 12 05:53:21 PM PDT 24
Peak memory 191300 kb
Host smart-ca969cca-04ad-46b1-80f3-b0d3f8e97008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241869864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.4241869864
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3914383644
Short name T73
Test name
Test status
Simulation time 63703532 ps
CPU time 0.86 seconds
Started Jul 12 05:39:00 PM PDT 24
Finished Jul 12 05:39:02 PM PDT 24
Peak memory 182252 kb
Host smart-071af153-8c63-4330-824b-3ef52b98eecf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914383644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3914383644
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4187989382
Short name T76
Test name
Test status
Simulation time 144515768 ps
CPU time 0.72 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:39:09 PM PDT 24
Peak memory 191140 kb
Host smart-a390461a-6ddc-4ade-af86-6cc5c84094c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187989382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4187989382
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/124.rv_timer_random.1914055241
Short name T193
Test name
Test status
Simulation time 126783456169 ps
CPU time 253.26 seconds
Started Jul 12 05:40:57 PM PDT 24
Finished Jul 12 05:45:10 PM PDT 24
Peak memory 191284 kb
Host smart-15ab5549-0a94-46dc-ae57-011f8df8bacb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914055241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1914055241
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.566536689
Short name T130
Test name
Test status
Simulation time 356500292849 ps
CPU time 261.3 seconds
Started Jul 12 05:41:18 PM PDT 24
Finished Jul 12 05:45:40 PM PDT 24
Peak memory 191316 kb
Host smart-50ca9a71-e5f8-436f-8ec0-7b444a3a4b1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566536689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.566536689
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.444695549
Short name T113
Test name
Test status
Simulation time 1027100734277 ps
CPU time 1955.35 seconds
Started Jul 12 05:40:25 PM PDT 24
Finished Jul 12 06:13:02 PM PDT 24
Peak memory 195740 kb
Host smart-b055f0d8-47d1-4575-bffe-c449dd2ee892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444695549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
444695549
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_random.2112760522
Short name T115
Test name
Test status
Simulation time 417384571833 ps
CPU time 223.54 seconds
Started Jul 12 05:40:21 PM PDT 24
Finished Jul 12 05:44:07 PM PDT 24
Peak memory 191124 kb
Host smart-c797d6af-2537-4e98-ad39-8f620e42e776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112760522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.2112760522
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random.34114080
Short name T290
Test name
Test status
Simulation time 459058880856 ps
CPU time 384.71 seconds
Started Jul 12 05:40:27 PM PDT 24
Finished Jul 12 05:46:53 PM PDT 24
Peak memory 191284 kb
Host smart-879a391c-aa89-4f62-b2ab-d3a35754de67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34114080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.34114080
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.2731384510
Short name T82
Test name
Test status
Simulation time 1329139491151 ps
CPU time 1286.98 seconds
Started Jul 12 05:40:31 PM PDT 24
Finished Jul 12 06:01:59 PM PDT 24
Peak memory 190888 kb
Host smart-a0597872-0864-4ff2-b9e1-c77f9c4e2d3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731384510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.2731384510
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2117376125
Short name T207
Test name
Test status
Simulation time 148673665743 ps
CPU time 148.58 seconds
Started Jul 12 05:40:35 PM PDT 24
Finished Jul 12 05:43:04 PM PDT 24
Peak memory 191256 kb
Host smart-7e0e7e7c-7591-4fd2-812c-0b1fb1440061
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117376125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2117376125
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.469151235
Short name T165
Test name
Test status
Simulation time 477095451280 ps
CPU time 371.9 seconds
Started Jul 12 05:40:35 PM PDT 24
Finished Jul 12 05:46:47 PM PDT 24
Peak memory 193224 kb
Host smart-297eddd2-0c70-4c53-ae0c-5073bf752ecc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469151235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.469151235
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3233570315
Short name T317
Test name
Test status
Simulation time 150934003703 ps
CPU time 770.27 seconds
Started Jul 12 05:40:41 PM PDT 24
Finished Jul 12 05:53:32 PM PDT 24
Peak memory 191184 kb
Host smart-3899d982-d3e1-47dd-9177-a57a3f73893d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233570315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3233570315
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.221900033
Short name T528
Test name
Test status
Simulation time 169502236 ps
CPU time 0.85 seconds
Started Jul 12 05:39:27 PM PDT 24
Finished Jul 12 05:39:29 PM PDT 24
Peak memory 192988 kb
Host smart-8b26566d-61f3-40e7-b8ad-a743028eea07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221900033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.221900033
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_timer_random.3318311167
Short name T203
Test name
Test status
Simulation time 297867257447 ps
CPU time 950.93 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 05:55:34 PM PDT 24
Peak memory 193336 kb
Host smart-d0a63a15-4343-4d58-8de3-e4d861ab304b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318311167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3318311167
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2606523390
Short name T166
Test name
Test status
Simulation time 194792449811 ps
CPU time 1455.63 seconds
Started Jul 12 05:40:54 PM PDT 24
Finished Jul 12 06:05:10 PM PDT 24
Peak memory 183044 kb
Host smart-5720c927-f4b2-45db-9ad1-a738a19c816d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606523390 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2606523390
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1636146332
Short name T177
Test name
Test status
Simulation time 336948330056 ps
CPU time 150.54 seconds
Started Jul 12 05:40:48 PM PDT 24
Finished Jul 12 05:43:19 PM PDT 24
Peak memory 191224 kb
Host smart-8740e745-ccf7-4886-a231-cd00e36de622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636146332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1636146332
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.4028545899
Short name T201
Test name
Test status
Simulation time 488819810461 ps
CPU time 324.11 seconds
Started Jul 12 05:40:51 PM PDT 24
Finished Jul 12 05:46:15 PM PDT 24
Peak memory 191244 kb
Host smart-a3d0e0a1-bfe7-4423-a4fa-b03c9467042f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028545899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.4028545899
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.535282238
Short name T148
Test name
Test status
Simulation time 106953955066 ps
CPU time 185.64 seconds
Started Jul 12 05:40:50 PM PDT 24
Finished Jul 12 05:43:56 PM PDT 24
Peak memory 191308 kb
Host smart-b3cadcaa-d7db-432b-97ab-b261a7636735
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535282238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.535282238
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.342803652
Short name T227
Test name
Test status
Simulation time 105457604864 ps
CPU time 72.35 seconds
Started Jul 12 05:41:12 PM PDT 24
Finished Jul 12 05:42:25 PM PDT 24
Peak memory 193576 kb
Host smart-f1af640c-844b-429d-af6e-80a76a09d608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342803652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.342803652
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.3726352980
Short name T211
Test name
Test status
Simulation time 30647816006 ps
CPU time 55.96 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 05:41:00 PM PDT 24
Peak memory 183080 kb
Host smart-20b8f4c3-cfd5-42da-b8e8-340e7523f147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726352980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.3726352980
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/156.rv_timer_random.1621844026
Short name T20
Test name
Test status
Simulation time 596215640654 ps
CPU time 180.47 seconds
Started Jul 12 05:41:12 PM PDT 24
Finished Jul 12 05:44:13 PM PDT 24
Peak memory 191308 kb
Host smart-10dea0bb-67d5-482c-980e-13df0b2f9da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621844026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1621844026
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.821812617
Short name T313
Test name
Test status
Simulation time 145246006197 ps
CPU time 548.68 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:49:15 PM PDT 24
Peak memory 191224 kb
Host smart-dbefe36e-207f-4e44-bb47-6776c0199c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821812617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
821812617
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/19.rv_timer_random.1352552529
Short name T246
Test name
Test status
Simulation time 305617903196 ps
CPU time 176.09 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 05:43:05 PM PDT 24
Peak memory 191308 kb
Host smart-452b728e-8e12-49e2-af52-ccf5bef81cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352552529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1352552529
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.4117998048
Short name T225
Test name
Test status
Simulation time 949602003981 ps
CPU time 1209.34 seconds
Started Jul 12 05:41:28 PM PDT 24
Finished Jul 12 06:01:39 PM PDT 24
Peak memory 193048 kb
Host smart-28de31a7-fc6c-47f4-b1ac-8a065194464a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117998048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.4117998048
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.3222735708
Short name T140
Test name
Test status
Simulation time 590336515675 ps
CPU time 1304.3 seconds
Started Jul 12 05:41:28 PM PDT 24
Finished Jul 12 06:03:14 PM PDT 24
Peak memory 191204 kb
Host smart-c72cdeb9-6208-4e3e-bee0-3a4243e25efd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222735708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.3222735708
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2436558062
Short name T160
Test name
Test status
Simulation time 116783138535 ps
CPU time 444.4 seconds
Started Jul 12 05:41:35 PM PDT 24
Finished Jul 12 05:49:00 PM PDT 24
Peak memory 191312 kb
Host smart-fbb1cfe6-3bbd-485a-b3a8-9bd33dc1ee5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436558062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2436558062
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.881792426
Short name T283
Test name
Test status
Simulation time 343762090900 ps
CPU time 2612.87 seconds
Started Jul 12 05:41:34 PM PDT 24
Finished Jul 12 06:25:08 PM PDT 24
Peak memory 191296 kb
Host smart-ce788755-92d8-4810-828c-3399025e5a23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881792426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.881792426
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.1799188600
Short name T303
Test name
Test status
Simulation time 556388155681 ps
CPU time 1144.02 seconds
Started Jul 12 05:41:34 PM PDT 24
Finished Jul 12 06:00:39 PM PDT 24
Peak memory 191288 kb
Host smart-5d873c04-46ae-4853-ad15-179ebee913fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799188600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.1799188600
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.4204224967
Short name T298
Test name
Test status
Simulation time 50501400120 ps
CPU time 381.02 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 05:46:30 PM PDT 24
Peak memory 191324 kb
Host smart-f1d49aee-bb35-4fde-9bfb-5766a4924b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204224967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4204224967
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.3403222937
Short name T251
Test name
Test status
Simulation time 700662874933 ps
CPU time 1226.41 seconds
Started Jul 12 05:40:10 PM PDT 24
Finished Jul 12 06:00:37 PM PDT 24
Peak memory 183048 kb
Host smart-691eacbf-8439-4cf1-bcc0-94b63aeffe9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403222937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.3403222937
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2807610989
Short name T275
Test name
Test status
Simulation time 225373038923 ps
CPU time 377.11 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:46:30 PM PDT 24
Peak memory 182976 kb
Host smart-d4dc24f5-9b80-499a-ac5f-7aa689a0085e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807610989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2807610989
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3693863656
Short name T172
Test name
Test status
Simulation time 133554518830 ps
CPU time 61.96 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:41:16 PM PDT 24
Peak memory 183052 kb
Host smart-f7b0fd54-4a83-4e96-8c5b-bc1049a6228f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693863656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3693863656
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3611748407
Short name T139
Test name
Test status
Simulation time 205961180171 ps
CPU time 161.72 seconds
Started Jul 12 05:40:21 PM PDT 24
Finished Jul 12 05:43:06 PM PDT 24
Peak memory 191288 kb
Host smart-e55abb88-69a0-4f42-87d9-539e811fc087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611748407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3611748407
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.261984921
Short name T99
Test name
Test status
Simulation time 86635041679 ps
CPU time 138.23 seconds
Started Jul 12 05:40:22 PM PDT 24
Finished Jul 12 05:42:43 PM PDT 24
Peak memory 183092 kb
Host smart-cbc45d72-3baf-4a1b-90b7-4bf9b7d3b144
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261984921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.261984921
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.4080346254
Short name T306
Test name
Test status
Simulation time 48249559175 ps
CPU time 26.66 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:40:48 PM PDT 24
Peak memory 183036 kb
Host smart-60b60e6c-e741-4980-8c7b-eefb2a949d7a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080346254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.4080346254
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_random.3058340945
Short name T338
Test name
Test status
Simulation time 38222350336 ps
CPU time 21.89 seconds
Started Jul 12 05:40:33 PM PDT 24
Finished Jul 12 05:40:56 PM PDT 24
Peak memory 183008 kb
Host smart-64acd3db-edb5-4db8-abb0-1197c5815eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058340945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3058340945
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1247625729
Short name T146
Test name
Test status
Simulation time 168853855252 ps
CPU time 265.7 seconds
Started Jul 12 05:40:36 PM PDT 24
Finished Jul 12 05:45:03 PM PDT 24
Peak memory 191520 kb
Host smart-0d2ed927-4683-4aa7-8369-16b7ae30ff4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247625729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1247625729
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1764904399
Short name T46
Test name
Test status
Simulation time 120373116094 ps
CPU time 252.68 seconds
Started Jul 12 05:40:33 PM PDT 24
Finished Jul 12 05:44:47 PM PDT 24
Peak memory 191236 kb
Host smart-48b1df33-5fc1-4782-ae8b-32ac05327ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764904399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1764904399
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3334841728
Short name T339
Test name
Test status
Simulation time 194685995103 ps
CPU time 82.06 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 05:41:57 PM PDT 24
Peak memory 191304 kb
Host smart-055b5c08-50c7-47e1-8b24-19eeefef72ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334841728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3334841728
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.2113859707
Short name T155
Test name
Test status
Simulation time 111061268719 ps
CPU time 625.98 seconds
Started Jul 12 05:40:35 PM PDT 24
Finished Jul 12 05:51:02 PM PDT 24
Peak memory 191296 kb
Host smart-3ecb5855-3588-42ff-8fca-2dab89f92e7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113859707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.2113859707
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.123770095
Short name T270
Test name
Test status
Simulation time 60248462088 ps
CPU time 110.99 seconds
Started Jul 12 05:40:42 PM PDT 24
Finished Jul 12 05:42:34 PM PDT 24
Peak memory 191300 kb
Host smart-19320ea5-f03d-4bf5-8316-120ca5192ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123770095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.123770095
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3121519788
Short name T125
Test name
Test status
Simulation time 299569044642 ps
CPU time 553.74 seconds
Started Jul 12 05:40:48 PM PDT 24
Finished Jul 12 05:50:02 PM PDT 24
Peak memory 191276 kb
Host smart-0bff5e09-6e00-44a0-8d10-114ed74186f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121519788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3121519788
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.61976295
Short name T507
Test name
Test status
Simulation time 37611293 ps
CPU time 1.44 seconds
Started Jul 12 05:39:01 PM PDT 24
Finished Jul 12 05:39:04 PM PDT 24
Peak memory 190620 kb
Host smart-5fbd4817-5d6a-4491-83ea-dc1a50a438e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61976295 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_ba
sh.61976295
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.525681063
Short name T575
Test name
Test status
Simulation time 59295281 ps
CPU time 0.61 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:39:08 PM PDT 24
Peak memory 182252 kb
Host smart-c2e99844-da34-4731-ab66-f0d13d541902
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525681063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.525681063
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3796550996
Short name T560
Test name
Test status
Simulation time 25829688 ps
CPU time 1.27 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:39:09 PM PDT 24
Peak memory 197048 kb
Host smart-a1ebefd6-b914-4bbb-955a-fa3b95b22e0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796550996 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3796550996
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.858831628
Short name T486
Test name
Test status
Simulation time 23355960 ps
CPU time 0.58 seconds
Started Jul 12 05:39:00 PM PDT 24
Finished Jul 12 05:39:02 PM PDT 24
Peak memory 182132 kb
Host smart-a3cb7094-292c-473a-b15a-7921a3459abe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858831628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.858831628
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2627189854
Short name T465
Test name
Test status
Simulation time 16295486 ps
CPU time 0.59 seconds
Started Jul 12 05:38:59 PM PDT 24
Finished Jul 12 05:39:00 PM PDT 24
Peak memory 182060 kb
Host smart-8fba72a8-56a8-4f1c-8924-4d320c0b2f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627189854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2627189854
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.795558911
Short name T516
Test name
Test status
Simulation time 45904038 ps
CPU time 0.67 seconds
Started Jul 12 05:39:02 PM PDT 24
Finished Jul 12 05:39:03 PM PDT 24
Peak memory 191460 kb
Host smart-140997ce-c704-4080-80cd-be17f04f28bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795558911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.795558911
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.56788302
Short name T498
Test name
Test status
Simulation time 67353892 ps
CPU time 1.42 seconds
Started Jul 12 05:39:00 PM PDT 24
Finished Jul 12 05:39:03 PM PDT 24
Peak memory 196708 kb
Host smart-fe07652d-fdd6-47be-9de9-a28a1769cdc1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56788302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.56788302
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2382017563
Short name T475
Test name
Test status
Simulation time 356092395 ps
CPU time 0.85 seconds
Started Jul 12 05:39:02 PM PDT 24
Finished Jul 12 05:39:03 PM PDT 24
Peak memory 193380 kb
Host smart-74b1b6c4-d4d2-4508-84c5-ea7ed3da0348
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382017563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2382017563
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1003444144
Short name T70
Test name
Test status
Simulation time 18215041 ps
CPU time 0.73 seconds
Started Jul 12 05:39:11 PM PDT 24
Finished Jul 12 05:39:12 PM PDT 24
Peak memory 191556 kb
Host smart-0ccfae0a-0b00-46d2-8984-fb54785d83f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003444144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1003444144
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.2874396150
Short name T462
Test name
Test status
Simulation time 266080421 ps
CPU time 2.47 seconds
Started Jul 12 05:39:10 PM PDT 24
Finished Jul 12 05:39:13 PM PDT 24
Peak memory 182392 kb
Host smart-59aced1e-2b8e-4325-82b3-5f5c357a05cf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874396150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.2874396150
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1191775080
Short name T511
Test name
Test status
Simulation time 44785627 ps
CPU time 0.72 seconds
Started Jul 12 05:39:09 PM PDT 24
Finished Jul 12 05:39:10 PM PDT 24
Peak memory 195008 kb
Host smart-7d2c6067-df29-43aa-926d-9935648a251a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191775080 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.1191775080
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.210952689
Short name T519
Test name
Test status
Simulation time 13026299 ps
CPU time 0.54 seconds
Started Jul 12 05:39:09 PM PDT 24
Finished Jul 12 05:39:10 PM PDT 24
Peak memory 182060 kb
Host smart-3172c2eb-2690-4228-bf2c-65f0e3856080
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210952689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.210952689
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.283201233
Short name T471
Test name
Test status
Simulation time 30835457 ps
CPU time 0.54 seconds
Started Jul 12 05:39:09 PM PDT 24
Finished Jul 12 05:39:10 PM PDT 24
Peak memory 182100 kb
Host smart-8134920a-cfb8-4b4c-9694-3f619bfaab84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283201233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.283201233
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.504388653
Short name T477
Test name
Test status
Simulation time 97760732 ps
CPU time 1.57 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:39:09 PM PDT 24
Peak memory 197048 kb
Host smart-2265c627-ee74-4cb8-a664-98b6427da200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504388653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.504388653
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.2594296513
Short name T484
Test name
Test status
Simulation time 169406010 ps
CPU time 1.36 seconds
Started Jul 12 05:39:00 PM PDT 24
Finished Jul 12 05:39:02 PM PDT 24
Peak memory 182884 kb
Host smart-0e4c3ff0-eccd-41de-b187-af246e8b4bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594296513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.2594296513
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.744498730
Short name T502
Test name
Test status
Simulation time 23146442 ps
CPU time 0.74 seconds
Started Jul 12 05:39:25 PM PDT 24
Finished Jul 12 05:39:27 PM PDT 24
Peak memory 194532 kb
Host smart-bb865e2b-c30a-4db1-adcc-fa44d74c1cb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744498730 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.744498730
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1537689514
Short name T89
Test name
Test status
Simulation time 15170855 ps
CPU time 0.58 seconds
Started Jul 12 05:39:29 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 182216 kb
Host smart-0ae68b1d-f949-4baf-8c02-b7d3ec3d78c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537689514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1537689514
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.50967818
Short name T467
Test name
Test status
Simulation time 90237167 ps
CPU time 0.55 seconds
Started Jul 12 05:39:26 PM PDT 24
Finished Jul 12 05:39:28 PM PDT 24
Peak memory 182152 kb
Host smart-9842f164-2dab-46ef-9b63-d6accd8d619b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50967818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.50967818
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2903879777
Short name T557
Test name
Test status
Simulation time 70961451 ps
CPU time 0.62 seconds
Started Jul 12 05:39:29 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 191052 kb
Host smart-11af2cca-c3ed-4605-b303-e896e4587065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903879777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2903879777
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1122888517
Short name T474
Test name
Test status
Simulation time 127371870 ps
CPU time 3.72 seconds
Started Jul 12 05:39:26 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 196736 kb
Host smart-4bf10ccb-d36d-445f-b531-020f5f28e7c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122888517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1122888517
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3299146156
Short name T53
Test name
Test status
Simulation time 39573992 ps
CPU time 0.92 seconds
Started Jul 12 05:39:25 PM PDT 24
Finished Jul 12 05:39:27 PM PDT 24
Peak memory 196344 kb
Host smart-bc15b6b8-a077-44d3-a4a6-d95d1a92a8d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299146156 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3299146156
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.1418914181
Short name T500
Test name
Test status
Simulation time 29172359 ps
CPU time 0.61 seconds
Started Jul 12 05:39:25 PM PDT 24
Finished Jul 12 05:39:27 PM PDT 24
Peak memory 182196 kb
Host smart-c6869e93-ff6a-48fc-bee9-afc532d2cdf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418914181 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.1418914181
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.2503037219
Short name T561
Test name
Test status
Simulation time 27995139 ps
CPU time 0.58 seconds
Started Jul 12 05:39:28 PM PDT 24
Finished Jul 12 05:39:31 PM PDT 24
Peak memory 182076 kb
Host smart-f7c6548d-2990-4792-88f4-57419768e4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503037219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.2503037219
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.502706291
Short name T32
Test name
Test status
Simulation time 142859726 ps
CPU time 0.76 seconds
Started Jul 12 05:39:27 PM PDT 24
Finished Jul 12 05:39:30 PM PDT 24
Peak memory 191196 kb
Host smart-a7d56b25-2bc3-4528-b5af-ce06e05d6f6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502706291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.502706291
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.980476283
Short name T558
Test name
Test status
Simulation time 49346731 ps
CPU time 1.03 seconds
Started Jul 12 05:39:28 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 195808 kb
Host smart-0d246ab2-8def-4f89-b318-ce8347c7e8dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980476283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.980476283
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.660877842
Short name T480
Test name
Test status
Simulation time 75202038 ps
CPU time 0.9 seconds
Started Jul 12 05:39:31 PM PDT 24
Finished Jul 12 05:39:34 PM PDT 24
Peak memory 196240 kb
Host smart-c965a7ad-7e74-42c9-85d4-791d0cc46d67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660877842 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.660877842
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.2440625329
Short name T63
Test name
Test status
Simulation time 31217178 ps
CPU time 0.63 seconds
Started Jul 12 05:39:26 PM PDT 24
Finished Jul 12 05:39:28 PM PDT 24
Peak memory 182264 kb
Host smart-013a2a5f-d996-464e-a18e-6a7a94eeb939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440625329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.2440625329
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.353660613
Short name T494
Test name
Test status
Simulation time 13425382 ps
CPU time 0.51 seconds
Started Jul 12 05:39:29 PM PDT 24
Finished Jul 12 05:39:31 PM PDT 24
Peak memory 181544 kb
Host smart-0a1336e7-e30c-413d-82bd-6b6b058b2062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353660613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.353660613
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1092882347
Short name T67
Test name
Test status
Simulation time 14045895 ps
CPU time 0.63 seconds
Started Jul 12 05:39:29 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 191164 kb
Host smart-59e514bd-b27a-4847-995c-8b62fb11cf16
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092882347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1092882347
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.4146793259
Short name T481
Test name
Test status
Simulation time 497259067 ps
CPU time 1 seconds
Started Jul 12 05:39:26 PM PDT 24
Finished Jul 12 05:39:29 PM PDT 24
Peak memory 196824 kb
Host smart-ad23c6ac-a225-4b04-a2c7-ad5baf01fe68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146793259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.4146793259
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3284603816
Short name T92
Test name
Test status
Simulation time 81836254 ps
CPU time 1.06 seconds
Started Jul 12 05:39:28 PM PDT 24
Finished Jul 12 05:39:31 PM PDT 24
Peak memory 194528 kb
Host smart-cf84c837-c8e2-4b70-b5d9-485d92cf2a0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284603816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3284603816
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3107704569
Short name T55
Test name
Test status
Simulation time 19945550 ps
CPU time 0.67 seconds
Started Jul 12 05:39:31 PM PDT 24
Finished Jul 12 05:39:34 PM PDT 24
Peak memory 193740 kb
Host smart-d810b2b4-ca9d-44df-8498-bad5581d483c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107704569 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3107704569
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3704618636
Short name T541
Test name
Test status
Simulation time 30071963 ps
CPU time 0.54 seconds
Started Jul 12 05:39:23 PM PDT 24
Finished Jul 12 05:39:24 PM PDT 24
Peak memory 182192 kb
Host smart-10a44e0a-52f8-42a5-b679-d0edda431196
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704618636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3704618636
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2333951332
Short name T491
Test name
Test status
Simulation time 45119642 ps
CPU time 0.57 seconds
Started Jul 12 05:39:25 PM PDT 24
Finished Jul 12 05:39:28 PM PDT 24
Peak memory 181740 kb
Host smart-fc157862-bc30-41ca-b6a8-38afa32a2285
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333951332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2333951332
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2493247238
Short name T525
Test name
Test status
Simulation time 159246099 ps
CPU time 0.6 seconds
Started Jul 12 05:39:26 PM PDT 24
Finished Jul 12 05:39:28 PM PDT 24
Peak memory 191436 kb
Host smart-68dc5c40-f1c9-4bc2-a2ef-d7e12dfc3065
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493247238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2493247238
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2257774783
Short name T518
Test name
Test status
Simulation time 64156721 ps
CPU time 1.81 seconds
Started Jul 12 05:39:32 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 196908 kb
Host smart-61d15e89-3c07-41d5-b24e-6fdb98a4a72d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257774783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2257774783
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.4218621477
Short name T54
Test name
Test status
Simulation time 151489876 ps
CPU time 0.85 seconds
Started Jul 12 05:39:25 PM PDT 24
Finished Jul 12 05:39:28 PM PDT 24
Peak memory 193352 kb
Host smart-260c1ea9-2fab-4465-a018-5b226c7c9334
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218621477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.4218621477
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1669238868
Short name T461
Test name
Test status
Simulation time 26445845 ps
CPU time 1.2 seconds
Started Jul 12 05:39:31 PM PDT 24
Finished Jul 12 05:39:34 PM PDT 24
Peak memory 197044 kb
Host smart-1528470d-2928-421b-bf73-cffbbcedd526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669238868 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1669238868
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1440526170
Short name T542
Test name
Test status
Simulation time 19107073 ps
CPU time 0.59 seconds
Started Jul 12 05:39:25 PM PDT 24
Finished Jul 12 05:39:27 PM PDT 24
Peak memory 182260 kb
Host smart-3cb3badc-7d76-4002-bd30-180fd269b753
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440526170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1440526170
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1411520389
Short name T568
Test name
Test status
Simulation time 67706607 ps
CPU time 0.52 seconds
Started Jul 12 05:39:30 PM PDT 24
Finished Jul 12 05:39:33 PM PDT 24
Peak memory 181584 kb
Host smart-80f60183-f908-4ba0-bcdd-a84d95b912f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411520389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1411520389
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.841842727
Short name T75
Test name
Test status
Simulation time 48880767 ps
CPU time 0.71 seconds
Started Jul 12 05:39:29 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 192556 kb
Host smart-f7a33c1a-0c03-471c-91ff-ff77273b88c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841842727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.841842727
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.964413417
Short name T488
Test name
Test status
Simulation time 116554530 ps
CPU time 2.28 seconds
Started Jul 12 05:39:31 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 197048 kb
Host smart-56ac1f51-ff91-407b-b791-f38d3a0b0458
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964413417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.964413417
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3007249983
Short name T487
Test name
Test status
Simulation time 116241705 ps
CPU time 1.3 seconds
Started Jul 12 05:39:28 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 194956 kb
Host smart-64b17869-3ea0-4952-aadd-55ffe97f3d78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007249983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3007249983
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.4294572095
Short name T567
Test name
Test status
Simulation time 34012691 ps
CPU time 1.37 seconds
Started Jul 12 05:39:27 PM PDT 24
Finished Jul 12 05:39:31 PM PDT 24
Peak memory 197032 kb
Host smart-5bc6ee5e-cb13-4fb6-a3e0-fa8ddeca65b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294572095 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.4294572095
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.190071569
Short name T548
Test name
Test status
Simulation time 33978552 ps
CPU time 0.6 seconds
Started Jul 12 05:39:25 PM PDT 24
Finished Jul 12 05:39:27 PM PDT 24
Peak memory 182140 kb
Host smart-ba841ba1-4788-439a-8ecc-5489c2e9e90e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190071569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.190071569
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.4242973569
Short name T547
Test name
Test status
Simulation time 17070799 ps
CPU time 0.54 seconds
Started Jul 12 05:39:26 PM PDT 24
Finished Jul 12 05:39:29 PM PDT 24
Peak memory 182128 kb
Host smart-b74d8f13-70c0-4b8a-ba68-7d0f83dd3b6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242973569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.4242973569
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3036366724
Short name T563
Test name
Test status
Simulation time 117555328 ps
CPU time 0.81 seconds
Started Jul 12 05:39:27 PM PDT 24
Finished Jul 12 05:39:30 PM PDT 24
Peak memory 192708 kb
Host smart-2dd833ef-55b5-49f7-bb88-85b5f57a3816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036366724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3036366724
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.2018589148
Short name T526
Test name
Test status
Simulation time 75455043 ps
CPU time 1.06 seconds
Started Jul 12 05:39:32 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 196780 kb
Host smart-52721231-1f25-48e1-aec4-c0297c09666c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018589148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.2018589148
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3891217723
Short name T30
Test name
Test status
Simulation time 166148512 ps
CPU time 0.86 seconds
Started Jul 12 05:39:26 PM PDT 24
Finished Jul 12 05:39:28 PM PDT 24
Peak memory 193052 kb
Host smart-2ea569e2-2108-490f-90a5-135e73761daf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891217723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3891217723
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2780750561
Short name T460
Test name
Test status
Simulation time 19276175 ps
CPU time 0.78 seconds
Started Jul 12 05:39:28 PM PDT 24
Finished Jul 12 05:39:31 PM PDT 24
Peak memory 196812 kb
Host smart-594e75f1-7441-4036-8940-80aa239f8df6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780750561 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2780750561
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.450538518
Short name T482
Test name
Test status
Simulation time 117933844 ps
CPU time 0.56 seconds
Started Jul 12 05:39:30 PM PDT 24
Finished Jul 12 05:39:33 PM PDT 24
Peak memory 182208 kb
Host smart-61dd713b-df11-4494-80ad-c9683aad8605
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450538518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.450538518
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3812047594
Short name T550
Test name
Test status
Simulation time 16301828 ps
CPU time 0.57 seconds
Started Jul 12 05:39:26 PM PDT 24
Finished Jul 12 05:39:28 PM PDT 24
Peak memory 182152 kb
Host smart-8fb56033-51b4-4000-b686-5b5b8fcf433a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812047594 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3812047594
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.3947300870
Short name T554
Test name
Test status
Simulation time 227691259 ps
CPU time 0.83 seconds
Started Jul 12 05:39:30 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 191188 kb
Host smart-e85bbbd8-da1c-4e0a-8035-305638969fb6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947300870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.3947300870
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2649046405
Short name T514
Test name
Test status
Simulation time 308056514 ps
CPU time 1.79 seconds
Started Jul 12 05:39:29 PM PDT 24
Finished Jul 12 05:39:33 PM PDT 24
Peak memory 197004 kb
Host smart-a7bfad63-299c-43e2-a704-e3b01e5c9d90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649046405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2649046405
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.629869650
Short name T93
Test name
Test status
Simulation time 358002380 ps
CPU time 1.41 seconds
Started Jul 12 05:39:27 PM PDT 24
Finished Jul 12 05:39:30 PM PDT 24
Peak memory 182972 kb
Host smart-0c8a278f-1530-4501-becd-cfa032bb6fd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629869650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.629869650
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2490688086
Short name T463
Test name
Test status
Simulation time 163645020 ps
CPU time 1.13 seconds
Started Jul 12 05:39:34 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 196852 kb
Host smart-cdd7ea01-f06a-4614-bbfa-4b93abf14763
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490688086 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2490688086
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2045434322
Short name T69
Test name
Test status
Simulation time 18931568 ps
CPU time 0.61 seconds
Started Jul 12 05:39:33 PM PDT 24
Finished Jul 12 05:39:37 PM PDT 24
Peak memory 182260 kb
Host smart-88569b42-160c-49d6-aa78-624064d03e88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045434322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2045434322
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.594615906
Short name T454
Test name
Test status
Simulation time 11706323 ps
CPU time 0.53 seconds
Started Jul 12 05:39:37 PM PDT 24
Finished Jul 12 05:39:39 PM PDT 24
Peak memory 181812 kb
Host smart-a23cf4bf-d8e8-4f2d-ad60-4ce9fc284678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594615906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.594615906
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.1836221429
Short name T66
Test name
Test status
Simulation time 18235681 ps
CPU time 0.69 seconds
Started Jul 12 05:39:33 PM PDT 24
Finished Jul 12 05:39:37 PM PDT 24
Peak memory 192612 kb
Host smart-28c0f4e6-3d49-4747-bf7d-4b804e439936
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836221429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.1836221429
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.2883619979
Short name T503
Test name
Test status
Simulation time 49289424 ps
CPU time 2.49 seconds
Started Jul 12 05:39:27 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 197048 kb
Host smart-7e2ca586-23d9-4cc5-bf93-3334b542a89d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883619979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.2883619979
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.281679747
Short name T540
Test name
Test status
Simulation time 81582861 ps
CPU time 0.86 seconds
Started Jul 12 05:39:35 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 193040 kb
Host smart-dd0495ff-069f-4d20-8325-3fe9669d3c6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281679747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_in
tg_err.281679747
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3978261043
Short name T553
Test name
Test status
Simulation time 35082381 ps
CPU time 1.67 seconds
Started Jul 12 05:39:34 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 197072 kb
Host smart-156f3b17-e516-4eb7-8df2-cad0697fcbe0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978261043 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3978261043
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.4254917609
Short name T569
Test name
Test status
Simulation time 66294738 ps
CPU time 0.57 seconds
Started Jul 12 05:39:33 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 182264 kb
Host smart-254d1476-9997-42b6-87ac-ce4fd7b54408
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254917609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.4254917609
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.4059366280
Short name T576
Test name
Test status
Simulation time 31170274 ps
CPU time 0.58 seconds
Started Jul 12 05:39:33 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 182136 kb
Host smart-e685c6aa-c3c6-48e8-ba56-a26cc8e80bcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059366280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.4059366280
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.509503079
Short name T512
Test name
Test status
Simulation time 14295787 ps
CPU time 0.67 seconds
Started Jul 12 05:39:36 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 191432 kb
Host smart-839686b6-ba08-4f02-9e3e-fa16e1629e2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509503079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.509503079
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.457501811
Short name T493
Test name
Test status
Simulation time 51068577 ps
CPU time 2.41 seconds
Started Jul 12 05:39:33 PM PDT 24
Finished Jul 12 05:39:39 PM PDT 24
Peak memory 197028 kb
Host smart-603d9c9a-35d5-44f4-9844-ebb257fb9aae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457501811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.457501811
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.1447833021
Short name T546
Test name
Test status
Simulation time 1863237842 ps
CPU time 1.48 seconds
Started Jul 12 05:39:34 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 194988 kb
Host smart-c155bc40-dd7f-4819-895e-6b97a0d110de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447833021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.1447833021
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.3263087612
Short name T539
Test name
Test status
Simulation time 29787662 ps
CPU time 0.81 seconds
Started Jul 12 05:39:32 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 194828 kb
Host smart-f22acab2-c742-4056-93cd-beefdfef1291
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263087612 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.3263087612
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2687991171
Short name T72
Test name
Test status
Simulation time 15035091 ps
CPU time 0.56 seconds
Started Jul 12 05:39:32 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 182248 kb
Host smart-74f9dede-332d-4fe2-be73-eec2fe0d2949
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687991171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2687991171
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.2580528927
Short name T455
Test name
Test status
Simulation time 51976578 ps
CPU time 0.57 seconds
Started Jul 12 05:39:32 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 182184 kb
Host smart-9218eac0-d23e-4d29-bf11-6de3e04eae79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580528927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.2580528927
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1677489617
Short name T552
Test name
Test status
Simulation time 33310473 ps
CPU time 0.8 seconds
Started Jul 12 05:39:32 PM PDT 24
Finished Jul 12 05:39:35 PM PDT 24
Peak memory 192916 kb
Host smart-8d2e21c5-4b24-4a03-a216-4cc00e3f311c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677489617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1677489617
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1884569919
Short name T459
Test name
Test status
Simulation time 57122373 ps
CPU time 1.47 seconds
Started Jul 12 05:39:37 PM PDT 24
Finished Jul 12 05:39:39 PM PDT 24
Peak memory 196860 kb
Host smart-c7fb95b4-1c10-4c33-874b-f3cf9988d844
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884569919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1884569919
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.2510337233
Short name T31
Test name
Test status
Simulation time 43513412 ps
CPU time 0.82 seconds
Started Jul 12 05:39:37 PM PDT 24
Finished Jul 12 05:39:39 PM PDT 24
Peak memory 193020 kb
Host smart-06f5d89c-8a97-4e09-acaa-869f299e9ac1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510337233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.2510337233
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3082216588
Short name T68
Test name
Test status
Simulation time 19919187 ps
CPU time 0.8 seconds
Started Jul 12 05:39:10 PM PDT 24
Finished Jul 12 05:39:11 PM PDT 24
Peak memory 192028 kb
Host smart-159cdb16-7186-4b36-a135-417fb55495c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082216588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3082216588
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3637356986
Short name T60
Test name
Test status
Simulation time 548965449 ps
CPU time 2.44 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:39:11 PM PDT 24
Peak memory 182400 kb
Host smart-24127281-2461-446f-bdcb-6d910cc8460c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637356986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3637356986
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3544366620
Short name T509
Test name
Test status
Simulation time 40833787 ps
CPU time 0.56 seconds
Started Jul 12 05:39:11 PM PDT 24
Finished Jul 12 05:39:12 PM PDT 24
Peak memory 182256 kb
Host smart-7cfdd050-768b-4b09-b862-6222dc75c4af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544366620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3544366620
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1950413028
Short name T534
Test name
Test status
Simulation time 32096275 ps
CPU time 0.83 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:39:09 PM PDT 24
Peak memory 196540 kb
Host smart-3722282c-0aab-4288-a79c-ec5cb27eea0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950413028 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1950413028
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3720986657
Short name T88
Test name
Test status
Simulation time 13792335 ps
CPU time 0.58 seconds
Started Jul 12 05:39:09 PM PDT 24
Finished Jul 12 05:39:10 PM PDT 24
Peak memory 182120 kb
Host smart-9c1c93fc-6752-4c34-a8b0-b59cf02280c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720986657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3720986657
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2762871570
Short name T457
Test name
Test status
Simulation time 35726245 ps
CPU time 0.59 seconds
Started Jul 12 05:39:07 PM PDT 24
Finished Jul 12 05:39:09 PM PDT 24
Peak memory 182164 kb
Host smart-e6927ecd-c605-4b6b-b68c-7f78edf0c7f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762871570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2762871570
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.35153241
Short name T77
Test name
Test status
Simulation time 34822078 ps
CPU time 0.92 seconds
Started Jul 12 05:39:12 PM PDT 24
Finished Jul 12 05:39:14 PM PDT 24
Peak memory 193060 kb
Host smart-325ee5c1-dba1-42d6-8f09-c3c9d6d70e8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35153241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_time
r_same_csr_outstanding.35153241
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.926781467
Short name T452
Test name
Test status
Simulation time 56169315 ps
CPU time 1.45 seconds
Started Jul 12 05:39:09 PM PDT 24
Finished Jul 12 05:39:11 PM PDT 24
Peak memory 196944 kb
Host smart-e57a0551-aaa8-41dc-ac7b-717204677a2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926781467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.926781467
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.932113689
Short name T470
Test name
Test status
Simulation time 300402970 ps
CPU time 1.18 seconds
Started Jul 12 05:39:08 PM PDT 24
Finished Jul 12 05:39:10 PM PDT 24
Peak memory 194352 kb
Host smart-6131bfa5-a1c8-4a43-a951-365f1afd71e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932113689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.932113689
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2994924317
Short name T580
Test name
Test status
Simulation time 14051623 ps
CPU time 0.57 seconds
Started Jul 12 05:39:31 PM PDT 24
Finished Jul 12 05:39:34 PM PDT 24
Peak memory 181836 kb
Host smart-fa1b95bd-d450-4c68-bc2d-ee755aadb953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994924317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2994924317
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.2741152026
Short name T517
Test name
Test status
Simulation time 14102439 ps
CPU time 0.54 seconds
Started Jul 12 05:39:31 PM PDT 24
Finished Jul 12 05:39:34 PM PDT 24
Peak memory 181568 kb
Host smart-7f4a08ef-7619-4db8-8d74-cb98f9bda14f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741152026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.2741152026
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3816928032
Short name T532
Test name
Test status
Simulation time 26492879 ps
CPU time 0.61 seconds
Started Jul 12 05:39:34 PM PDT 24
Finished Jul 12 05:39:37 PM PDT 24
Peak memory 182152 kb
Host smart-26a10e68-8006-43c1-8339-f9d934d31f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816928032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3816928032
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.1999674839
Short name T573
Test name
Test status
Simulation time 139212206 ps
CPU time 0.52 seconds
Started Jul 12 05:39:33 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 181560 kb
Host smart-1cb55966-dd1c-4dc9-b66e-de54bdb810bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999674839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.1999674839
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2411859018
Short name T571
Test name
Test status
Simulation time 26060288 ps
CPU time 0.56 seconds
Started Jul 12 05:39:33 PM PDT 24
Finished Jul 12 05:39:37 PM PDT 24
Peak memory 181792 kb
Host smart-f9d6d1b2-c373-412d-b3e0-b5373070b98e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411859018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2411859018
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2258327609
Short name T565
Test name
Test status
Simulation time 14380115 ps
CPU time 0.52 seconds
Started Jul 12 05:39:36 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 181616 kb
Host smart-10de4ecd-3fa9-4e3e-b03c-93aaf0b75d2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258327609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2258327609
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1183898310
Short name T489
Test name
Test status
Simulation time 50638232 ps
CPU time 0.57 seconds
Started Jul 12 05:39:32 PM PDT 24
Finished Jul 12 05:39:35 PM PDT 24
Peak memory 182176 kb
Host smart-78cc974d-5180-44f9-8b88-5daeb7972a26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183898310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1183898310
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.605505575
Short name T490
Test name
Test status
Simulation time 15353170 ps
CPU time 0.55 seconds
Started Jul 12 05:39:35 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 182156 kb
Host smart-d1f022a6-ffd4-4207-98f8-3759297de40d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605505575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.605505575
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2823145324
Short name T523
Test name
Test status
Simulation time 66053446 ps
CPU time 0.58 seconds
Started Jul 12 05:39:33 PM PDT 24
Finished Jul 12 05:39:37 PM PDT 24
Peak memory 182124 kb
Host smart-ca800055-d8b2-4106-bfcb-f75aeb952ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823145324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2823145324
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3097200843
Short name T533
Test name
Test status
Simulation time 102531951 ps
CPU time 0.59 seconds
Started Jul 12 05:39:32 PM PDT 24
Finished Jul 12 05:39:34 PM PDT 24
Peak memory 182172 kb
Host smart-3ab6fbd1-0b28-4a7b-9f48-29fe0922e461
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097200843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3097200843
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1046098107
Short name T524
Test name
Test status
Simulation time 26909752 ps
CPU time 0.66 seconds
Started Jul 12 05:39:17 PM PDT 24
Finished Jul 12 05:39:18 PM PDT 24
Peak memory 182256 kb
Host smart-80572739-5089-4827-b4fb-9f4d71a8ed38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046098107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1046098107
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3882839212
Short name T572
Test name
Test status
Simulation time 393467550 ps
CPU time 1.59 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 192344 kb
Host smart-fb49eb61-0f31-4ee9-a900-25efae304a41
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882839212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3882839212
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3057531189
Short name T90
Test name
Test status
Simulation time 26511393 ps
CPU time 0.56 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:21 PM PDT 24
Peak memory 181908 kb
Host smart-8ea54a8c-f099-466d-90aa-4ed29dad37a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057531189 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3057531189
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3279504247
Short name T52
Test name
Test status
Simulation time 39049079 ps
CPU time 0.93 seconds
Started Jul 12 05:39:17 PM PDT 24
Finished Jul 12 05:39:19 PM PDT 24
Peak memory 196404 kb
Host smart-b52738aa-089e-4358-913a-fd8d1b9eaf55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279504247 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3279504247
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3640400823
Short name T549
Test name
Test status
Simulation time 41278872 ps
CPU time 0.58 seconds
Started Jul 12 05:39:20 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 182208 kb
Host smart-81cff3f8-2eec-4d6d-bfb3-bc961e2cdae0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640400823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3640400823
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.2067267767
Short name T479
Test name
Test status
Simulation time 14824405 ps
CPU time 0.55 seconds
Started Jul 12 05:39:09 PM PDT 24
Finished Jul 12 05:39:10 PM PDT 24
Peak memory 181660 kb
Host smart-4a9dd5be-e986-4d44-949a-913775ec179c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067267767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.2067267767
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2845506276
Short name T579
Test name
Test status
Simulation time 22995639 ps
CPU time 0.83 seconds
Started Jul 12 05:39:16 PM PDT 24
Finished Jul 12 05:39:17 PM PDT 24
Peak memory 192928 kb
Host smart-628cb854-4f03-41be-ae89-08a2f4f30e85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845506276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.2845506276
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3270446336
Short name T527
Test name
Test status
Simulation time 292959072 ps
CPU time 2.63 seconds
Started Jul 12 05:39:09 PM PDT 24
Finished Jul 12 05:39:13 PM PDT 24
Peak memory 197012 kb
Host smart-d6499098-b8fd-4980-840b-be26a4a309ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270446336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3270446336
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.4128175475
Short name T94
Test name
Test status
Simulation time 99186433 ps
CPU time 1.13 seconds
Started Jul 12 05:39:08 PM PDT 24
Finished Jul 12 05:39:10 PM PDT 24
Peak memory 194816 kb
Host smart-760672d1-ab33-4234-b8ac-80720cd71e5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128175475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.4128175475
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1208730913
Short name T570
Test name
Test status
Simulation time 12224102 ps
CPU time 0.59 seconds
Started Jul 12 05:39:34 PM PDT 24
Finished Jul 12 05:39:37 PM PDT 24
Peak memory 182088 kb
Host smart-5543668a-bea4-4428-9f14-3abff241ce5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208730913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1208730913
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.589688404
Short name T453
Test name
Test status
Simulation time 87188425 ps
CPU time 0.58 seconds
Started Jul 12 05:39:36 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 182024 kb
Host smart-37374748-9d80-4004-b1cc-fa44385198f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589688404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.589688404
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2035377225
Short name T545
Test name
Test status
Simulation time 28060195 ps
CPU time 0.54 seconds
Started Jul 12 05:39:36 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 182076 kb
Host smart-63a8cc0d-15ee-4d6c-af0d-a921966f3503
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035377225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2035377225
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3598295795
Short name T472
Test name
Test status
Simulation time 52340448 ps
CPU time 0.57 seconds
Started Jul 12 05:39:36 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 182044 kb
Host smart-a779e521-c12c-4be5-a5f8-a1f661c165b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598295795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3598295795
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.155151351
Short name T556
Test name
Test status
Simulation time 12073504 ps
CPU time 0.56 seconds
Started Jul 12 05:39:34 PM PDT 24
Finished Jul 12 05:39:37 PM PDT 24
Peak memory 181796 kb
Host smart-3abc9897-0dff-42b6-9473-44fad6b07c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155151351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.155151351
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3270862627
Short name T531
Test name
Test status
Simulation time 43208387 ps
CPU time 0.59 seconds
Started Jul 12 05:39:36 PM PDT 24
Finished Jul 12 05:39:38 PM PDT 24
Peak memory 182052 kb
Host smart-c99d90fb-e70f-48a1-983d-af6e50502540
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270862627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3270862627
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1144866973
Short name T530
Test name
Test status
Simulation time 23143224 ps
CPU time 0.54 seconds
Started Jul 12 05:39:39 PM PDT 24
Finished Jul 12 05:39:41 PM PDT 24
Peak memory 181600 kb
Host smart-67c00943-dea5-4807-a556-78b78922d9de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144866973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1144866973
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.468864244
Short name T458
Test name
Test status
Simulation time 11377051 ps
CPU time 0.58 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 05:39:44 PM PDT 24
Peak memory 182100 kb
Host smart-af7c5f92-2452-43f1-870e-6034e26c733b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468864244 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.468864244
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.983359661
Short name T559
Test name
Test status
Simulation time 14152375 ps
CPU time 0.56 seconds
Started Jul 12 05:39:40 PM PDT 24
Finished Jul 12 05:39:42 PM PDT 24
Peak memory 182168 kb
Host smart-fc4785dc-358d-4344-ba53-d162ac5fbefd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983359661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.983359661
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.2322824418
Short name T495
Test name
Test status
Simulation time 13408606 ps
CPU time 0.51 seconds
Started Jul 12 05:39:43 PM PDT 24
Finished Jul 12 05:39:45 PM PDT 24
Peak memory 181552 kb
Host smart-ec46e914-ea13-4e9f-9f8f-db247ae32263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322824418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.2322824418
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1565166721
Short name T74
Test name
Test status
Simulation time 128915173 ps
CPU time 0.85 seconds
Started Jul 12 05:39:23 PM PDT 24
Finished Jul 12 05:39:24 PM PDT 24
Peak memory 192312 kb
Host smart-923be0be-688c-4a43-92c3-2b3fc18223de
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565166721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1565166721
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.255543765
Short name T33
Test name
Test status
Simulation time 146649165 ps
CPU time 1.55 seconds
Started Jul 12 05:39:19 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 190556 kb
Host smart-8875c8cd-9549-4719-94a2-749ffc2b80c1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255543765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.255543765
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1594615162
Short name T497
Test name
Test status
Simulation time 15885542 ps
CPU time 0.61 seconds
Started Jul 12 05:39:20 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 191248 kb
Host smart-a8826197-8b4b-44e2-9580-c0d570564fd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594615162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1594615162
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1109550834
Short name T468
Test name
Test status
Simulation time 49789080 ps
CPU time 1.24 seconds
Started Jul 12 05:39:19 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 197060 kb
Host smart-f46bc358-6acd-404f-931d-01b55f0c7713
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109550834 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1109550834
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.147301663
Short name T504
Test name
Test status
Simulation time 80992708 ps
CPU time 0.61 seconds
Started Jul 12 05:39:22 PM PDT 24
Finished Jul 12 05:39:23 PM PDT 24
Peak memory 182416 kb
Host smart-cdbfe0c9-542d-4c5a-99a5-5edb4f9cd8b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147301663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.147301663
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1733845759
Short name T543
Test name
Test status
Simulation time 48395241 ps
CPU time 0.56 seconds
Started Jul 12 05:39:17 PM PDT 24
Finished Jul 12 05:39:19 PM PDT 24
Peak memory 182088 kb
Host smart-b2f9d41d-2686-474a-a7a9-d8fda48edf50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733845759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1733845759
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3640499250
Short name T62
Test name
Test status
Simulation time 31798379 ps
CPU time 0.82 seconds
Started Jul 12 05:39:20 PM PDT 24
Finished Jul 12 05:39:23 PM PDT 24
Peak memory 191212 kb
Host smart-60316b6d-a53e-413e-8a94-000faedd6177
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640499250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3640499250
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4024531586
Short name T521
Test name
Test status
Simulation time 271102496 ps
CPU time 2.55 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 197300 kb
Host smart-3c38aee6-8c2b-4c20-9c10-ea3a5fc7f879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024531586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.4024531586
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2593175078
Short name T520
Test name
Test status
Simulation time 44725283 ps
CPU time 0.83 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 182748 kb
Host smart-fdc93286-784b-4ec5-9048-b4b3a32da24d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593175078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2593175078
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1441651664
Short name T505
Test name
Test status
Simulation time 21734764 ps
CPU time 0.6 seconds
Started Jul 12 05:39:40 PM PDT 24
Finished Jul 12 05:39:42 PM PDT 24
Peak memory 182160 kb
Host smart-aca54abc-6121-4af9-8924-5c8dcd5c2bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441651664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1441651664
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.3405389788
Short name T496
Test name
Test status
Simulation time 49463476 ps
CPU time 0.6 seconds
Started Jul 12 05:39:39 PM PDT 24
Finished Jul 12 05:39:41 PM PDT 24
Peak memory 182148 kb
Host smart-980a9c77-af4e-49ac-9367-3cd6d2cc876a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405389788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.3405389788
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.3449722614
Short name T544
Test name
Test status
Simulation time 49565257 ps
CPU time 0.54 seconds
Started Jul 12 05:39:38 PM PDT 24
Finished Jul 12 05:39:39 PM PDT 24
Peak memory 182116 kb
Host smart-4a698033-5c74-40c7-ac24-8fadf756335e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449722614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.3449722614
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2413066324
Short name T492
Test name
Test status
Simulation time 45800679 ps
CPU time 0.55 seconds
Started Jul 12 05:39:40 PM PDT 24
Finished Jul 12 05:39:42 PM PDT 24
Peak memory 181624 kb
Host smart-8c1e6bc5-4017-4a8f-866f-8578b4a7d5a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413066324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2413066324
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.347096460
Short name T551
Test name
Test status
Simulation time 39885462 ps
CPU time 0.53 seconds
Started Jul 12 05:39:38 PM PDT 24
Finished Jul 12 05:39:40 PM PDT 24
Peak memory 181600 kb
Host smart-f83e87f4-6e45-4358-b1e1-1b17cc87d280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347096460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.347096460
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.4099680136
Short name T577
Test name
Test status
Simulation time 16839418 ps
CPU time 0.54 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 05:39:43 PM PDT 24
Peak memory 181624 kb
Host smart-9c62d6a2-8b1b-435b-8b10-d35f3a08f5a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099680136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.4099680136
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.3159908551
Short name T537
Test name
Test status
Simulation time 19275338 ps
CPU time 0.58 seconds
Started Jul 12 05:39:40 PM PDT 24
Finished Jul 12 05:39:42 PM PDT 24
Peak memory 181988 kb
Host smart-c0cc6a03-b19a-42a8-b17d-9dda9328616f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159908551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.3159908551
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.1242782840
Short name T535
Test name
Test status
Simulation time 19513081 ps
CPU time 0.58 seconds
Started Jul 12 05:39:40 PM PDT 24
Finished Jul 12 05:39:42 PM PDT 24
Peak memory 182144 kb
Host smart-baf2f0e7-96d4-4a47-9426-3c24623b203f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242782840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.1242782840
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.524237923
Short name T473
Test name
Test status
Simulation time 11493683 ps
CPU time 0.56 seconds
Started Jul 12 05:39:42 PM PDT 24
Finished Jul 12 05:39:44 PM PDT 24
Peak memory 181592 kb
Host smart-42229069-dbf6-46d0-90e1-28dba34a1bb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524237923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.524237923
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.2560642256
Short name T578
Test name
Test status
Simulation time 52839372 ps
CPU time 0.55 seconds
Started Jul 12 05:39:39 PM PDT 24
Finished Jul 12 05:39:40 PM PDT 24
Peak memory 182120 kb
Host smart-1164c172-14ac-4808-97cf-e8f1ab3c57d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560642256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.2560642256
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2881536405
Short name T574
Test name
Test status
Simulation time 51996326 ps
CPU time 1.16 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 196936 kb
Host smart-c401de3e-cb2b-4ba7-a8c8-db2328f5aa5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881536405 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2881536405
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.3445284313
Short name T508
Test name
Test status
Simulation time 36584781 ps
CPU time 0.56 seconds
Started Jul 12 05:39:19 PM PDT 24
Finished Jul 12 05:39:21 PM PDT 24
Peak memory 182200 kb
Host smart-186a7d33-890b-47db-8d30-e9f6b3642e8d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445284313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.3445284313
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1897742100
Short name T506
Test name
Test status
Simulation time 40371229 ps
CPU time 0.59 seconds
Started Jul 12 05:39:17 PM PDT 24
Finished Jul 12 05:39:19 PM PDT 24
Peak memory 182384 kb
Host smart-6a635477-2c28-485b-b0ab-7ff5ed669293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897742100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1897742100
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2880868812
Short name T61
Test name
Test status
Simulation time 26760043 ps
CPU time 0.72 seconds
Started Jul 12 05:39:19 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 191164 kb
Host smart-f95c5c19-e03f-4e8d-bcd1-32f0e167df30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880868812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2880868812
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.59826964
Short name T499
Test name
Test status
Simulation time 264575356 ps
CPU time 2.82 seconds
Started Jul 12 05:39:19 PM PDT 24
Finished Jul 12 05:39:24 PM PDT 24
Peak memory 197048 kb
Host smart-a80bd2f4-43f3-4d3e-af60-fd0bcfa23be1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59826964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.59826964
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1353123816
Short name T510
Test name
Test status
Simulation time 99053981 ps
CPU time 1.34 seconds
Started Jul 12 05:39:23 PM PDT 24
Finished Jul 12 05:39:25 PM PDT 24
Peak memory 194944 kb
Host smart-6f493828-3f8d-4cc0-a5c2-b9d97d92e249
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353123816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1353123816
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.4241254054
Short name T485
Test name
Test status
Simulation time 38467538 ps
CPU time 1.61 seconds
Started Jul 12 05:39:21 PM PDT 24
Finished Jul 12 05:39:24 PM PDT 24
Peak memory 197068 kb
Host smart-53066d15-b232-49c4-8147-a4f01c556762
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241254054 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.4241254054
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2726089709
Short name T555
Test name
Test status
Simulation time 49706732 ps
CPU time 0.59 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 182188 kb
Host smart-1d3a3f9a-ce57-48e2-94ce-20c35c6f1715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726089709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2726089709
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.1174004749
Short name T513
Test name
Test status
Simulation time 17790718 ps
CPU time 0.59 seconds
Started Jul 12 05:39:19 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 182088 kb
Host smart-26a29971-4251-40cf-89cd-53e15a603796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174004749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.1174004749
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.3336598364
Short name T65
Test name
Test status
Simulation time 293955449 ps
CPU time 0.88 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 191188 kb
Host smart-e225e559-aabc-47ee-8084-50546172fb2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336598364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.3336598364
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.2031757207
Short name T564
Test name
Test status
Simulation time 107351894 ps
CPU time 1.92 seconds
Started Jul 12 05:39:19 PM PDT 24
Finished Jul 12 05:39:23 PM PDT 24
Peak memory 197028 kb
Host smart-442054fb-0785-47e0-bf93-44b338505c18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031757207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.2031757207
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.4002368429
Short name T95
Test name
Test status
Simulation time 332755017 ps
CPU time 1.06 seconds
Started Jul 12 05:39:23 PM PDT 24
Finished Jul 12 05:39:25 PM PDT 24
Peak memory 194688 kb
Host smart-b8e0740b-6d8b-4a1c-ba5e-6b1a79934b1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002368429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.4002368429
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.841656970
Short name T529
Test name
Test status
Simulation time 31891415 ps
CPU time 0.89 seconds
Started Jul 12 05:39:24 PM PDT 24
Finished Jul 12 05:39:26 PM PDT 24
Peak memory 196704 kb
Host smart-74c39baf-354f-4d59-9a36-da3b583cd0d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841656970 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.841656970
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1465498168
Short name T522
Test name
Test status
Simulation time 11820162 ps
CPU time 0.56 seconds
Started Jul 12 05:39:20 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 181984 kb
Host smart-bc13c880-e446-4d96-87e6-26beacd662e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465498168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1465498168
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.987104545
Short name T456
Test name
Test status
Simulation time 16019331 ps
CPU time 0.57 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:19 PM PDT 24
Peak memory 182056 kb
Host smart-8740093e-6ab5-4d14-a03a-8f845777f880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987104545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.987104545
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1302844127
Short name T64
Test name
Test status
Simulation time 19534783 ps
CPU time 0.64 seconds
Started Jul 12 05:39:19 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 191476 kb
Host smart-63994411-bbc6-449e-b575-db84445b821b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302844127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1302844127
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.3217910415
Short name T562
Test name
Test status
Simulation time 120824092 ps
CPU time 0.94 seconds
Started Jul 12 05:39:20 PM PDT 24
Finished Jul 12 05:39:22 PM PDT 24
Peak memory 195984 kb
Host smart-c211d7f9-d959-4a27-b491-f438a78541f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217910415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.3217910415
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3310029051
Short name T515
Test name
Test status
Simulation time 295387177 ps
CPU time 1.1 seconds
Started Jul 12 05:39:17 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 194460 kb
Host smart-2aa85457-f99c-4580-bdeb-09f41808878b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310029051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3310029051
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1627701520
Short name T469
Test name
Test status
Simulation time 94802720 ps
CPU time 1.39 seconds
Started Jul 12 05:39:17 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 197052 kb
Host smart-37c154cb-4556-4a31-a7c0-f5c3fe8dec8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627701520 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1627701520
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.197372962
Short name T71
Test name
Test status
Simulation time 52295304 ps
CPU time 0.6 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:21 PM PDT 24
Peak memory 182268 kb
Host smart-a1ea1852-75b1-440f-9816-82652f57dd98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197372962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.197372962
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.3903505307
Short name T478
Test name
Test status
Simulation time 15102155 ps
CPU time 0.57 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 182176 kb
Host smart-9078cdca-9ab4-4469-927f-b12dd9e28d13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903505307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.3903505307
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1628250829
Short name T536
Test name
Test status
Simulation time 36219848 ps
CPU time 0.64 seconds
Started Jul 12 05:39:18 PM PDT 24
Finished Jul 12 05:39:20 PM PDT 24
Peak memory 191456 kb
Host smart-b8bfef08-e00b-49f4-9b6e-70adec8fa8d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628250829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1628250829
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.1376152120
Short name T466
Test name
Test status
Simulation time 201245454 ps
CPU time 2.28 seconds
Started Jul 12 05:39:19 PM PDT 24
Finished Jul 12 05:39:24 PM PDT 24
Peak memory 197000 kb
Host smart-538597b3-b901-4271-895d-e6b58e7ef7ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376152120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.1376152120
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3050164589
Short name T501
Test name
Test status
Simulation time 78262150 ps
CPU time 1.11 seconds
Started Jul 12 05:39:16 PM PDT 24
Finished Jul 12 05:39:19 PM PDT 24
Peak memory 194552 kb
Host smart-e6205998-1196-491d-a962-c89a320601ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050164589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3050164589
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.2382735319
Short name T538
Test name
Test status
Simulation time 149589302 ps
CPU time 0.9 seconds
Started Jul 12 05:39:32 PM PDT 24
Finished Jul 12 05:39:36 PM PDT 24
Peak memory 196064 kb
Host smart-a231076e-8f56-4778-a3ff-89b910a8194d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382735319 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.2382735319
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.3280533229
Short name T483
Test name
Test status
Simulation time 23258510 ps
CPU time 0.61 seconds
Started Jul 12 05:39:29 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 191464 kb
Host smart-f0fa984c-2b38-498f-a49b-62b7c3aa5d6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280533229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.3280533229
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2779787160
Short name T464
Test name
Test status
Simulation time 25737069 ps
CPU time 0.56 seconds
Started Jul 12 05:39:29 PM PDT 24
Finished Jul 12 05:39:32 PM PDT 24
Peak memory 182116 kb
Host smart-f4017a73-692f-44ad-acaf-73ca4807261a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779787160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2779787160
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.3685184615
Short name T566
Test name
Test status
Simulation time 160205318 ps
CPU time 0.85 seconds
Started Jul 12 05:39:28 PM PDT 24
Finished Jul 12 05:39:31 PM PDT 24
Peak memory 191216 kb
Host smart-96a627b3-3f07-473e-b045-078930e1911c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685184615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.3685184615
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1697735428
Short name T476
Test name
Test status
Simulation time 572461786 ps
CPU time 2.77 seconds
Started Jul 12 05:39:24 PM PDT 24
Finished Jul 12 05:39:28 PM PDT 24
Peak memory 197056 kb
Host smart-71822f83-ea59-43f4-9a7d-d49e5076a8a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697735428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1697735428
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.616961238
Short name T91
Test name
Test status
Simulation time 348647469 ps
CPU time 1.4 seconds
Started Jul 12 05:39:24 PM PDT 24
Finished Jul 12 05:39:27 PM PDT 24
Peak memory 195000 kb
Host smart-2a043cee-a198-4eb4-b1e2-54c0e0fcfbd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616961238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.616961238
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3047686938
Short name T443
Test name
Test status
Simulation time 206551848117 ps
CPU time 244.74 seconds
Started Jul 12 05:39:42 PM PDT 24
Finished Jul 12 05:43:49 PM PDT 24
Peak memory 183064 kb
Host smart-8ee0f05d-512e-4a1c-9542-c7bf4ce15de4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047686938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3047686938
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2662817433
Short name T427
Test name
Test status
Simulation time 570805768708 ps
CPU time 225.32 seconds
Started Jul 12 05:39:39 PM PDT 24
Finished Jul 12 05:43:26 PM PDT 24
Peak memory 182996 kb
Host smart-72584fbd-bae1-4347-ad89-11a80545430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662817433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2662817433
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.2437911227
Short name T412
Test name
Test status
Simulation time 1314016856832 ps
CPU time 380.97 seconds
Started Jul 12 05:39:42 PM PDT 24
Finished Jul 12 05:46:05 PM PDT 24
Peak memory 191292 kb
Host smart-1d1ef510-e1b9-4568-a860-ad0e2d293336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437911227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2437911227
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.3270521161
Short name T80
Test name
Test status
Simulation time 29077150390 ps
CPU time 51.8 seconds
Started Jul 12 05:39:39 PM PDT 24
Finished Jul 12 05:40:33 PM PDT 24
Peak memory 191288 kb
Host smart-fca417d9-09da-43a2-aa49-3a83edc92027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270521161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.3270521161
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.612922625
Short name T448
Test name
Test status
Simulation time 126874120266 ps
CPU time 189.67 seconds
Started Jul 12 05:39:40 PM PDT 24
Finished Jul 12 05:42:51 PM PDT 24
Peak memory 183060 kb
Host smart-e56b18a1-283d-419b-bcba-e9008f6023b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612922625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.612922625
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3617048416
Short name T321
Test name
Test status
Simulation time 71422508526 ps
CPU time 26.15 seconds
Started Jul 12 05:39:40 PM PDT 24
Finished Jul 12 05:40:07 PM PDT 24
Peak memory 195228 kb
Host smart-f9947df4-e8fa-4d4d-a49e-469faf401a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617048416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3617048416
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2728284997
Short name T17
Test name
Test status
Simulation time 110140923 ps
CPU time 0.84 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 05:39:45 PM PDT 24
Peak memory 213524 kb
Host smart-5bf0e223-715e-4ce8-94a5-59713a216743
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728284997 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2728284997
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.1064666317
Short name T391
Test name
Test status
Simulation time 616246844081 ps
CPU time 507.6 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 05:48:11 PM PDT 24
Peak memory 191260 kb
Host smart-abb22d7f-1778-4d57-a39c-0481b29b24fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064666317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
1064666317
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.1842985350
Short name T42
Test name
Test status
Simulation time 127407211741 ps
CPU time 691.04 seconds
Started Jul 12 05:39:44 PM PDT 24
Finished Jul 12 05:51:16 PM PDT 24
Peak memory 200380 kb
Host smart-ac181e07-c68f-4991-87eb-229cd1914b06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842985350 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.1842985350
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3008965252
Short name T126
Test name
Test status
Simulation time 86152391587 ps
CPU time 136.47 seconds
Started Jul 12 05:39:55 PM PDT 24
Finished Jul 12 05:42:12 PM PDT 24
Peak memory 183076 kb
Host smart-8667ac05-cc19-4187-908b-d69aef468f0a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008965252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3008965252
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.203790985
Short name T366
Test name
Test status
Simulation time 43731709287 ps
CPU time 64.37 seconds
Started Jul 12 05:39:55 PM PDT 24
Finished Jul 12 05:41:00 PM PDT 24
Peak memory 183104 kb
Host smart-8a19239d-2030-4741-b316-00ac2e1eb89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203790985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.203790985
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3011617963
Short name T326
Test name
Test status
Simulation time 597156224862 ps
CPU time 1317.55 seconds
Started Jul 12 05:39:56 PM PDT 24
Finished Jul 12 06:01:54 PM PDT 24
Peak memory 191292 kb
Host smart-5071bcb5-7d71-4f63-aba1-22c95b856a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011617963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3011617963
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2112721858
Short name T315
Test name
Test status
Simulation time 41761620957 ps
CPU time 22.19 seconds
Started Jul 12 05:39:55 PM PDT 24
Finished Jul 12 05:40:18 PM PDT 24
Peak memory 191316 kb
Host smart-d6c54ec0-7036-48d6-a16a-0a11ce2f542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112721858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2112721858
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/100.rv_timer_random.3489173077
Short name T129
Test name
Test status
Simulation time 769915386963 ps
CPU time 138.17 seconds
Started Jul 12 05:40:48 PM PDT 24
Finished Jul 12 05:43:07 PM PDT 24
Peak memory 191220 kb
Host smart-825fffe8-5933-4691-b96c-76c4421d5b11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489173077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3489173077
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2432616251
Short name T301
Test name
Test status
Simulation time 43191476300 ps
CPU time 70.91 seconds
Started Jul 12 05:40:49 PM PDT 24
Finished Jul 12 05:42:01 PM PDT 24
Peak memory 182920 kb
Host smart-9aebfe90-9739-4806-ac94-5789e1c86aea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432616251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2432616251
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2417593109
Short name T161
Test name
Test status
Simulation time 289867689681 ps
CPU time 241.8 seconds
Started Jul 12 05:40:49 PM PDT 24
Finished Jul 12 05:44:52 PM PDT 24
Peak memory 191280 kb
Host smart-ef014188-4b76-415b-83b7-a49309f3ebcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417593109 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2417593109
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2479958492
Short name T110
Test name
Test status
Simulation time 387555033383 ps
CPU time 538.87 seconds
Started Jul 12 05:40:49 PM PDT 24
Finished Jul 12 05:49:49 PM PDT 24
Peak memory 191252 kb
Host smart-cf7f763e-572c-4a17-84f8-bbc5fbd1093c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479958492 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2479958492
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2814595364
Short name T276
Test name
Test status
Simulation time 1688828989214 ps
CPU time 892.21 seconds
Started Jul 12 05:39:55 PM PDT 24
Finished Jul 12 05:54:48 PM PDT 24
Peak memory 183084 kb
Host smart-1e2bd21a-10c6-4476-88ea-269101abbab4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814595364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2814595364
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.4199240004
Short name T359
Test name
Test status
Simulation time 29755407427 ps
CPU time 45.09 seconds
Started Jul 12 05:39:56 PM PDT 24
Finished Jul 12 05:40:42 PM PDT 24
Peak memory 183128 kb
Host smart-bb092566-7294-4aa0-9295-31282d9ebea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199240004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.4199240004
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2684041951
Short name T377
Test name
Test status
Simulation time 137236930551 ps
CPU time 60.37 seconds
Started Jul 12 05:39:55 PM PDT 24
Finished Jul 12 05:40:56 PM PDT 24
Peak memory 183096 kb
Host smart-cdb51cd7-c47b-44c4-a125-1520f11d2326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684041951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2684041951
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2717368311
Short name T384
Test name
Test status
Simulation time 1411303292 ps
CPU time 1.17 seconds
Started Jul 12 05:39:56 PM PDT 24
Finished Jul 12 05:39:58 PM PDT 24
Peak memory 182968 kb
Host smart-2b8465a6-1e3f-4063-8abd-648f4571410f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717368311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2717368311
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/114.rv_timer_random.3000632764
Short name T236
Test name
Test status
Simulation time 46936597595 ps
CPU time 50.26 seconds
Started Jul 12 05:40:50 PM PDT 24
Finished Jul 12 05:41:41 PM PDT 24
Peak memory 193604 kb
Host smart-1f1f367e-f1b7-4a36-a022-8a6b7009b0e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000632764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.3000632764
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3979043485
Short name T213
Test name
Test status
Simulation time 420765526662 ps
CPU time 385.92 seconds
Started Jul 12 05:40:48 PM PDT 24
Finished Jul 12 05:47:15 PM PDT 24
Peak memory 194704 kb
Host smart-d5b8c037-62c4-469c-868a-ba712cb8b963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979043485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3979043485
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.4036013566
Short name T279
Test name
Test status
Simulation time 1102196603866 ps
CPU time 527.84 seconds
Started Jul 12 05:40:55 PM PDT 24
Finished Jul 12 05:49:43 PM PDT 24
Peak memory 191172 kb
Host smart-20963813-825a-46f8-aa5f-4a1f17aab22f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036013566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.4036013566
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3071195494
Short name T334
Test name
Test status
Simulation time 118108873735 ps
CPU time 1401.22 seconds
Started Jul 12 05:41:35 PM PDT 24
Finished Jul 12 06:04:57 PM PDT 24
Peak memory 192320 kb
Host smart-241b150c-f633-42d4-9765-a3088e1ef610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071195494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3071195494
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.4174684284
Short name T319
Test name
Test status
Simulation time 310511548854 ps
CPU time 383.31 seconds
Started Jul 12 05:40:59 PM PDT 24
Finished Jul 12 05:47:23 PM PDT 24
Peak memory 191292 kb
Host smart-84c4e41e-38f6-4ae2-aaee-89b6e5f263d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174684284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.4174684284
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2063929444
Short name T399
Test name
Test status
Simulation time 52843757889 ps
CPU time 59.11 seconds
Started Jul 12 05:40:56 PM PDT 24
Finished Jul 12 05:41:55 PM PDT 24
Peak memory 183084 kb
Host smart-d27f86a6-b73f-4a24-9f65-cb750fd0d8f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063929444 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2063929444
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.701840096
Short name T434
Test name
Test status
Simulation time 36852047524 ps
CPU time 20.58 seconds
Started Jul 12 05:39:57 PM PDT 24
Finished Jul 12 05:40:18 PM PDT 24
Peak memory 182972 kb
Host smart-725db0ec-d0d0-4b08-9b7a-034b534274be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701840096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.701840096
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.3700179985
Short name T347
Test name
Test status
Simulation time 88057076591 ps
CPU time 122.24 seconds
Started Jul 12 05:39:54 PM PDT 24
Finished Jul 12 05:41:58 PM PDT 24
Peak memory 183068 kb
Host smart-775d0874-6464-4ac5-b266-f9deb1892e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700179985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.3700179985
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.4037561124
Short name T295
Test name
Test status
Simulation time 334441274162 ps
CPU time 239.72 seconds
Started Jul 12 05:39:54 PM PDT 24
Finished Jul 12 05:43:55 PM PDT 24
Peak memory 191216 kb
Host smart-8fc6e88d-3093-4bf1-b0cc-9d363ca1727f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037561124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4037561124
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.633146991
Short name T393
Test name
Test status
Simulation time 137372594 ps
CPU time 2.56 seconds
Started Jul 12 05:39:57 PM PDT 24
Finished Jul 12 05:40:01 PM PDT 24
Peak memory 183068 kb
Host smart-3fd7fc63-bdc5-4c1d-827f-7d8b8edc10e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633146991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.633146991
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/121.rv_timer_random.3410898903
Short name T413
Test name
Test status
Simulation time 129760986976 ps
CPU time 77.33 seconds
Started Jul 12 05:40:56 PM PDT 24
Finished Jul 12 05:42:14 PM PDT 24
Peak memory 183084 kb
Host smart-31258617-f686-485d-8d08-956ae18e6888
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410898903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3410898903
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.3783155764
Short name T135
Test name
Test status
Simulation time 927332367025 ps
CPU time 306.06 seconds
Started Jul 12 05:40:57 PM PDT 24
Finished Jul 12 05:46:04 PM PDT 24
Peak memory 191240 kb
Host smart-edc3a94f-7722-4f55-b978-9516975d0308
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783155764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.3783155764
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2202191411
Short name T323
Test name
Test status
Simulation time 307861741546 ps
CPU time 685.61 seconds
Started Jul 12 05:40:56 PM PDT 24
Finished Jul 12 05:52:22 PM PDT 24
Peak memory 191304 kb
Host smart-b8135c43-5b07-4cd1-852d-6ae615a53dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202191411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2202191411
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.2520020579
Short name T10
Test name
Test status
Simulation time 678892386069 ps
CPU time 1101.98 seconds
Started Jul 12 05:41:00 PM PDT 24
Finished Jul 12 05:59:23 PM PDT 24
Peak memory 191244 kb
Host smart-a1858cae-ff51-4145-aff3-7ac1e0c41a58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520020579 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.2520020579
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.2723436786
Short name T274
Test name
Test status
Simulation time 334895875696 ps
CPU time 176.21 seconds
Started Jul 12 05:41:04 PM PDT 24
Finished Jul 12 05:44:01 PM PDT 24
Peak memory 191280 kb
Host smart-37e99ec9-b3c5-47af-8a77-7f393132fb43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723436786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.2723436786
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3536292767
Short name T277
Test name
Test status
Simulation time 358231119024 ps
CPU time 288.81 seconds
Started Jul 12 05:41:02 PM PDT 24
Finished Jul 12 05:45:51 PM PDT 24
Peak memory 191300 kb
Host smart-e86a41e1-0b8e-4704-ae39-0eee24c35a3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536292767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3536292767
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3625008411
Short name T101
Test name
Test status
Simulation time 79578293880 ps
CPU time 476.67 seconds
Started Jul 12 05:41:05 PM PDT 24
Finished Jul 12 05:49:02 PM PDT 24
Peak memory 191264 kb
Host smart-8f6cf46e-340f-4139-b904-b5257deed3a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625008411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3625008411
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2435695985
Short name T383
Test name
Test status
Simulation time 1237002715 ps
CPU time 2.73 seconds
Started Jul 12 05:39:54 PM PDT 24
Finished Jul 12 05:39:57 PM PDT 24
Peak memory 182932 kb
Host smart-e128db56-259f-447e-a841-47c58aab2b71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435695985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2435695985
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.177912309
Short name T362
Test name
Test status
Simulation time 132327758556 ps
CPU time 154.94 seconds
Started Jul 12 05:39:56 PM PDT 24
Finished Jul 12 05:42:32 PM PDT 24
Peak memory 182944 kb
Host smart-1948b3db-4793-40aa-96e8-ce5f2583c135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177912309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.177912309
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.2999333951
Short name T296
Test name
Test status
Simulation time 55934929041 ps
CPU time 77.38 seconds
Started Jul 12 05:39:53 PM PDT 24
Finished Jul 12 05:41:11 PM PDT 24
Peak memory 191304 kb
Host smart-f66351ea-8a88-4657-9a71-b2ece72b8cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999333951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.2999333951
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2762762968
Short name T256
Test name
Test status
Simulation time 23008138614 ps
CPU time 36.04 seconds
Started Jul 12 05:39:56 PM PDT 24
Finished Jul 12 05:40:33 PM PDT 24
Peak memory 191304 kb
Host smart-45329d59-1f11-4011-b42f-3d10445dbdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762762968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2762762968
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2201549827
Short name T316
Test name
Test status
Simulation time 125082775905 ps
CPU time 177.57 seconds
Started Jul 12 05:41:04 PM PDT 24
Finished Jul 12 05:44:02 PM PDT 24
Peak memory 183316 kb
Host smart-dc3e561b-ee92-4830-95e8-fd5d16596ba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201549827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2201549827
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3494614491
Short name T124
Test name
Test status
Simulation time 25604880367 ps
CPU time 33.53 seconds
Started Jul 12 05:41:06 PM PDT 24
Finished Jul 12 05:41:40 PM PDT 24
Peak memory 183088 kb
Host smart-82727874-5955-41d6-8889-74fe611a1ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494614491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3494614491
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.3912844503
Short name T337
Test name
Test status
Simulation time 263306195682 ps
CPU time 354.25 seconds
Started Jul 12 05:41:04 PM PDT 24
Finished Jul 12 05:46:59 PM PDT 24
Peak memory 191172 kb
Host smart-29a96cba-6a8e-4654-a66d-286e2e929753
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912844503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.3912844503
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.421210558
Short name T291
Test name
Test status
Simulation time 379707214925 ps
CPU time 198.42 seconds
Started Jul 12 05:41:06 PM PDT 24
Finished Jul 12 05:44:25 PM PDT 24
Peak memory 191244 kb
Host smart-d72c0a28-2cf5-4a1f-9d6e-7772e836d518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421210558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.421210558
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.499340446
Short name T238
Test name
Test status
Simulation time 327323191190 ps
CPU time 172.12 seconds
Started Jul 12 05:41:06 PM PDT 24
Finished Jul 12 05:43:58 PM PDT 24
Peak memory 191308 kb
Host smart-199ac2b0-7c30-4638-9ac4-7aedded0c59c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499340446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.499340446
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.567434961
Short name T192
Test name
Test status
Simulation time 847863233405 ps
CPU time 1839.57 seconds
Started Jul 12 05:41:05 PM PDT 24
Finished Jul 12 06:11:46 PM PDT 24
Peak memory 191292 kb
Host smart-938d6078-b4f3-403a-a881-d461be0765aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567434961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.567434961
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3140826952
Short name T204
Test name
Test status
Simulation time 274323217739 ps
CPU time 479.35 seconds
Started Jul 12 05:41:03 PM PDT 24
Finished Jul 12 05:49:03 PM PDT 24
Peak memory 191288 kb
Host smart-e0e5fe3f-fb57-4bed-8493-4818f49f5adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140826952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3140826952
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.3396348347
Short name T250
Test name
Test status
Simulation time 74475857948 ps
CPU time 63.97 seconds
Started Jul 12 05:41:04 PM PDT 24
Finished Jul 12 05:42:08 PM PDT 24
Peak memory 194740 kb
Host smart-870e3509-6914-4518-824c-9ccec7618d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396348347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.3396348347
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.430002036
Short name T329
Test name
Test status
Simulation time 18874871693 ps
CPU time 73.7 seconds
Started Jul 12 05:41:03 PM PDT 24
Finished Jul 12 05:42:17 PM PDT 24
Peak memory 191188 kb
Host smart-e739f28a-4520-42ec-ab92-05b2f0d788c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430002036 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.430002036
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3837837887
Short name T249
Test name
Test status
Simulation time 1033879841079 ps
CPU time 398.16 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 05:46:47 PM PDT 24
Peak memory 183084 kb
Host smart-17fba797-1d42-46b8-8083-2ba79f7e77a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837837887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3837837887
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2628660892
Short name T47
Test name
Test status
Simulation time 84900821333 ps
CPU time 122.82 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 05:42:07 PM PDT 24
Peak memory 183328 kb
Host smart-865e3494-92d3-49f6-b179-716713ab11d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628660892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2628660892
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.940806359
Short name T4
Test name
Test status
Simulation time 216006059016 ps
CPU time 123.58 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:42:10 PM PDT 24
Peak memory 191284 kb
Host smart-eb76ec1b-dcb3-4140-87cf-abd33af4928f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940806359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.940806359
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1390675372
Short name T363
Test name
Test status
Simulation time 197088339116 ps
CPU time 50.05 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 05:40:59 PM PDT 24
Peak memory 193772 kb
Host smart-5d8aec01-4ba2-4f2c-910a-377891bdfcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390675372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1390675372
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.2217568537
Short name T401
Test name
Test status
Simulation time 34251967087 ps
CPU time 348.95 seconds
Started Jul 12 05:40:02 PM PDT 24
Finished Jul 12 05:45:52 PM PDT 24
Peak memory 206008 kb
Host smart-9003c008-9826-474b-89e9-9e738aa7ff0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217568537 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.2217568537
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/141.rv_timer_random.2190842864
Short name T254
Test name
Test status
Simulation time 172072485921 ps
CPU time 139.61 seconds
Started Jul 12 05:41:05 PM PDT 24
Finished Jul 12 05:43:25 PM PDT 24
Peak memory 193732 kb
Host smart-84ccb566-a47e-4e6f-a966-272782817dfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190842864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.2190842864
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3482195191
Short name T217
Test name
Test status
Simulation time 790556101864 ps
CPU time 84.13 seconds
Started Jul 12 05:41:03 PM PDT 24
Finished Jul 12 05:42:27 PM PDT 24
Peak memory 191180 kb
Host smart-e3e873b6-e374-4a88-adcf-11104230f779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482195191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3482195191
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1164127999
Short name T286
Test name
Test status
Simulation time 5895106681 ps
CPU time 5.98 seconds
Started Jul 12 05:41:05 PM PDT 24
Finished Jul 12 05:41:11 PM PDT 24
Peak memory 183080 kb
Host smart-08997152-5ded-4858-9008-51a7daadc4b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164127999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1164127999
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3986584376
Short name T197
Test name
Test status
Simulation time 63525919163 ps
CPU time 66.84 seconds
Started Jul 12 05:41:12 PM PDT 24
Finished Jul 12 05:42:19 PM PDT 24
Peak memory 183100 kb
Host smart-d596ec7a-b158-4a83-bb06-fedc57ca8fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986584376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3986584376
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.2510701636
Short name T136
Test name
Test status
Simulation time 527881277898 ps
CPU time 307.07 seconds
Started Jul 12 05:41:11 PM PDT 24
Finished Jul 12 05:46:19 PM PDT 24
Peak memory 191288 kb
Host smart-64132cf1-f6b8-44a1-9bb3-ca1abb065f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510701636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.2510701636
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.919280094
Short name T51
Test name
Test status
Simulation time 1730646521788 ps
CPU time 549.36 seconds
Started Jul 12 05:41:11 PM PDT 24
Finished Jul 12 05:50:20 PM PDT 24
Peak memory 192304 kb
Host smart-23fcee5b-e8c4-46a9-852f-5f51434fc23a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919280094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.919280094
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.112683206
Short name T410
Test name
Test status
Simulation time 157457761308 ps
CPU time 154.88 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:42:43 PM PDT 24
Peak memory 182972 kb
Host smart-dcb8480b-451f-4e35-927e-4229b76805c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112683206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.112683206
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.437237062
Short name T380
Test name
Test status
Simulation time 159848413261 ps
CPU time 223.24 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 05:43:52 PM PDT 24
Peak memory 183104 kb
Host smart-dc1e8b31-7820-4eef-9f41-9e5e8b8076d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437237062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.437237062
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/152.rv_timer_random.322363630
Short name T255
Test name
Test status
Simulation time 223452342910 ps
CPU time 205.18 seconds
Started Jul 12 05:48:51 PM PDT 24
Finished Jul 12 05:52:18 PM PDT 24
Peak memory 192352 kb
Host smart-531d6eb0-aca2-4d9b-a163-871d292277b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322363630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.322363630
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.110604568
Short name T273
Test name
Test status
Simulation time 42062238746 ps
CPU time 63.82 seconds
Started Jul 12 05:41:11 PM PDT 24
Finished Jul 12 05:42:15 PM PDT 24
Peak memory 183104 kb
Host smart-e9132130-84f5-42cd-b7c1-37011d528f5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110604568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.110604568
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3205509231
Short name T280
Test name
Test status
Simulation time 40378756030 ps
CPU time 18.19 seconds
Started Jul 12 05:41:12 PM PDT 24
Finished Jul 12 05:41:31 PM PDT 24
Peak memory 191260 kb
Host smart-9b332d66-c568-4b64-b9e1-f750d1265295
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205509231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3205509231
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.1102312275
Short name T444
Test name
Test status
Simulation time 699127928174 ps
CPU time 123.26 seconds
Started Jul 12 05:41:11 PM PDT 24
Finished Jul 12 05:43:14 PM PDT 24
Peak memory 183092 kb
Host smart-94ff225c-fd39-407b-a17a-86d232303fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102312275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.1102312275
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2369588134
Short name T405
Test name
Test status
Simulation time 105035005073 ps
CPU time 177.91 seconds
Started Jul 12 05:41:11 PM PDT 24
Finished Jul 12 05:44:10 PM PDT 24
Peak memory 191216 kb
Host smart-adfa37fc-612c-41cc-a289-5892cee77db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369588134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2369588134
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.545367585
Short name T450
Test name
Test status
Simulation time 252811461697 ps
CPU time 270.52 seconds
Started Jul 12 05:41:13 PM PDT 24
Finished Jul 12 05:45:44 PM PDT 24
Peak memory 191304 kb
Host smart-773b0c43-e282-4041-b52e-00e7fdbc98e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545367585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.545367585
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.257979531
Short name T309
Test name
Test status
Simulation time 270711307432 ps
CPU time 709.78 seconds
Started Jul 12 05:41:10 PM PDT 24
Finished Jul 12 05:53:00 PM PDT 24
Peak memory 191292 kb
Host smart-87b31dad-e281-45e1-b458-6e6a11648255
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257979531 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.257979531
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.2453602764
Short name T287
Test name
Test status
Simulation time 227667322192 ps
CPU time 198.65 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 05:43:23 PM PDT 24
Peak memory 183100 kb
Host smart-19dec003-71e0-4336-8ec2-b91a902343de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453602764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.2453602764
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2240100051
Short name T365
Test name
Test status
Simulation time 185460289931 ps
CPU time 110.86 seconds
Started Jul 12 05:40:02 PM PDT 24
Finished Jul 12 05:41:53 PM PDT 24
Peak memory 183076 kb
Host smart-bc095214-9768-4533-9367-d582bb0e6f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240100051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2240100051
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2125763323
Short name T133
Test name
Test status
Simulation time 519228495097 ps
CPU time 363.68 seconds
Started Jul 12 05:40:04 PM PDT 24
Finished Jul 12 05:46:10 PM PDT 24
Peak memory 191296 kb
Host smart-0ed5de42-589a-440d-962e-97c7fef707de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125763323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2125763323
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.2612671300
Short name T406
Test name
Test status
Simulation time 505552859 ps
CPU time 1.15 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:40:08 PM PDT 24
Peak memory 182896 kb
Host smart-e822b932-8e6d-4d3c-bedb-66cdd20f9d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612671300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.2612671300
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.3939227970
Short name T108
Test name
Test status
Simulation time 564712114992 ps
CPU time 154.47 seconds
Started Jul 12 05:41:13 PM PDT 24
Finished Jul 12 05:43:48 PM PDT 24
Peak memory 191300 kb
Host smart-c8b86f9d-fee3-42c8-bd13-22850ecd6b93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939227970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3939227970
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.4272856395
Short name T164
Test name
Test status
Simulation time 162909586769 ps
CPU time 127.69 seconds
Started Jul 12 05:41:19 PM PDT 24
Finished Jul 12 05:43:28 PM PDT 24
Peak memory 191220 kb
Host smart-d0c2c86b-5953-4b9f-8c96-b863dfec29c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272856395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4272856395
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1246084972
Short name T431
Test name
Test status
Simulation time 35424984055 ps
CPU time 255.64 seconds
Started Jul 12 05:48:25 PM PDT 24
Finished Jul 12 05:52:42 PM PDT 24
Peak memory 191304 kb
Host smart-45ed2e2e-6046-4291-a635-3f9269da9164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246084972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1246084972
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.1559259277
Short name T426
Test name
Test status
Simulation time 51579706148 ps
CPU time 54.81 seconds
Started Jul 12 05:41:20 PM PDT 24
Finished Jul 12 05:42:15 PM PDT 24
Peak memory 183088 kb
Host smart-a8084a65-bab6-4a4f-81ad-19d56a54e3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559259277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.1559259277
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.2454228865
Short name T153
Test name
Test status
Simulation time 1291314381906 ps
CPU time 1139.2 seconds
Started Jul 12 05:41:19 PM PDT 24
Finished Jul 12 06:00:20 PM PDT 24
Peak memory 191128 kb
Host smart-20ccc5e5-ee18-4c2c-9598-538efcade6d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454228865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.2454228865
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.352715402
Short name T331
Test name
Test status
Simulation time 393380677453 ps
CPU time 214.09 seconds
Started Jul 12 05:41:18 PM PDT 24
Finished Jul 12 05:44:53 PM PDT 24
Peak memory 191296 kb
Host smart-6fcf53cb-fc83-4065-9bc0-755702c4437b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352715402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.352715402
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1362379656
Short name T271
Test name
Test status
Simulation time 174734220520 ps
CPU time 97.88 seconds
Started Jul 12 05:41:17 PM PDT 24
Finished Jul 12 05:42:56 PM PDT 24
Peak memory 191272 kb
Host smart-79f46380-f54f-4c60-b42a-d512744af19c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362379656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1362379656
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.340228436
Short name T404
Test name
Test status
Simulation time 88423727566 ps
CPU time 147.46 seconds
Started Jul 12 05:41:20 PM PDT 24
Finished Jul 12 05:43:49 PM PDT 24
Peak memory 191124 kb
Host smart-90372718-96c1-4deb-a79c-dd714c636877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340228436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.340228436
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.932310685
Short name T187
Test name
Test status
Simulation time 997888689924 ps
CPU time 511.62 seconds
Started Jul 12 05:41:19 PM PDT 24
Finished Jul 12 05:49:51 PM PDT 24
Peak memory 191276 kb
Host smart-c16bf9f3-2b59-4264-bc2d-4b0540ea6d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932310685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.932310685
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3788452033
Short name T268
Test name
Test status
Simulation time 1383281516 ps
CPU time 2.67 seconds
Started Jul 12 05:40:02 PM PDT 24
Finished Jul 12 05:40:06 PM PDT 24
Peak memory 182860 kb
Host smart-114349d1-b4f5-4da8-b66c-c8ba3198f371
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788452033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3788452033
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.3233941246
Short name T374
Test name
Test status
Simulation time 27367852258 ps
CPU time 33.35 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 05:40:39 PM PDT 24
Peak memory 183048 kb
Host smart-0517db63-e119-475f-b3ec-a2c16f7bcf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233941246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.3233941246
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.265291055
Short name T350
Test name
Test status
Simulation time 34748804 ps
CPU time 0.56 seconds
Started Jul 12 05:40:02 PM PDT 24
Finished Jul 12 05:40:04 PM PDT 24
Peak memory 182932 kb
Host smart-df23253a-20cc-4f01-899e-9543b763e774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265291055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.265291055
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.46572893
Short name T112
Test name
Test status
Simulation time 148127581185 ps
CPU time 3285.1 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 06:34:54 PM PDT 24
Peak memory 191168 kb
Host smart-d5009369-ea54-4f9b-821b-eeffebbe7b88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46572893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.46572893
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.2968139940
Short name T233
Test name
Test status
Simulation time 38609004603 ps
CPU time 58.14 seconds
Started Jul 12 05:41:18 PM PDT 24
Finished Jul 12 05:42:17 PM PDT 24
Peak memory 183028 kb
Host smart-b834434b-9e05-4957-9996-94efef7cc19e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968139940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2968139940
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.2371412972
Short name T241
Test name
Test status
Simulation time 1608153749558 ps
CPU time 1381.5 seconds
Started Jul 12 05:41:21 PM PDT 24
Finished Jul 12 06:04:23 PM PDT 24
Peak memory 191272 kb
Host smart-5607c67a-6d23-4c46-aebe-f5d72e2e80d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371412972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2371412972
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.343760504
Short name T212
Test name
Test status
Simulation time 82195183459 ps
CPU time 96.2 seconds
Started Jul 12 05:41:20 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 191320 kb
Host smart-eb95b1ff-98c4-42a2-ae22-3610b80f09a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343760504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.343760504
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.2262056401
Short name T7
Test name
Test status
Simulation time 2208256686 ps
CPU time 4.68 seconds
Started Jul 12 05:41:19 PM PDT 24
Finished Jul 12 05:41:25 PM PDT 24
Peak memory 183088 kb
Host smart-6f87d767-8c85-49d6-823a-be7e4bcadc7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262056401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.2262056401
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.4270606450
Short name T419
Test name
Test status
Simulation time 50533748537 ps
CPU time 445.54 seconds
Started Jul 12 05:41:19 PM PDT 24
Finished Jul 12 05:48:45 PM PDT 24
Peak memory 191412 kb
Host smart-b5ea609a-8415-4527-b4c0-ad00ddd3c24a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270606450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.4270606450
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.1343002422
Short name T258
Test name
Test status
Simulation time 680078901533 ps
CPU time 1078.08 seconds
Started Jul 12 05:41:18 PM PDT 24
Finished Jul 12 05:59:17 PM PDT 24
Peak memory 191204 kb
Host smart-bdd3f2a3-c57c-44c3-bd73-f8c465779c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343002422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.1343002422
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2075516489
Short name T442
Test name
Test status
Simulation time 177014585137 ps
CPU time 393.84 seconds
Started Jul 12 05:41:21 PM PDT 24
Finished Jul 12 05:47:56 PM PDT 24
Peak memory 191272 kb
Host smart-93200a5d-1c25-4145-995e-8950d3bb3366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075516489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2075516489
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.2732107064
Short name T188
Test name
Test status
Simulation time 122728055369 ps
CPU time 73.25 seconds
Started Jul 12 05:41:27 PM PDT 24
Finished Jul 12 05:42:42 PM PDT 24
Peak memory 191292 kb
Host smart-acef4c0e-b33e-4a0d-984a-d9241a1d40ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732107064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.2732107064
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.2468521815
Short name T235
Test name
Test status
Simulation time 69659116164 ps
CPU time 22.7 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 05:40:28 PM PDT 24
Peak memory 183080 kb
Host smart-e1e75f61-d35d-4f76-b970-a7dad67db4e2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468521815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.2468521815
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3250697743
Short name T403
Test name
Test status
Simulation time 162789288442 ps
CPU time 117.92 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:42:04 PM PDT 24
Peak memory 183044 kb
Host smart-36d863b5-f3bf-4da6-954b-ded686e6d70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250697743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3250697743
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.995420152
Short name T208
Test name
Test status
Simulation time 77555487180 ps
CPU time 86.9 seconds
Started Jul 12 05:40:01 PM PDT 24
Finished Jul 12 05:41:28 PM PDT 24
Peak memory 191304 kb
Host smart-9cc50d0d-13e5-4614-91f2-b250e03f2a1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995420152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.995420152
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1929938973
Short name T260
Test name
Test status
Simulation time 18861928205 ps
CPU time 29.82 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 05:40:38 PM PDT 24
Peak memory 191320 kb
Host smart-68cccfab-a9d9-4a33-a77f-59345550df37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929938973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1929938973
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2000222634
Short name T300
Test name
Test status
Simulation time 275232937800 ps
CPU time 524.32 seconds
Started Jul 12 05:40:07 PM PDT 24
Finished Jul 12 05:48:53 PM PDT 24
Peak memory 183084 kb
Host smart-1e533b32-8829-4f43-b20a-40e6581b8534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000222634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2000222634
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.1669628154
Short name T223
Test name
Test status
Simulation time 246587520242 ps
CPU time 247.81 seconds
Started Jul 12 05:41:27 PM PDT 24
Finished Jul 12 05:45:37 PM PDT 24
Peak memory 191312 kb
Host smart-e508c667-a3e9-4749-a41e-e7a27fa1c3b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669628154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1669628154
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.3137956005
Short name T142
Test name
Test status
Simulation time 653453254213 ps
CPU time 541.55 seconds
Started Jul 12 05:41:27 PM PDT 24
Finished Jul 12 05:50:30 PM PDT 24
Peak memory 191296 kb
Host smart-877220ec-f334-4b0e-abc8-596680306b91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137956005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.3137956005
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.2520123835
Short name T435
Test name
Test status
Simulation time 112030467299 ps
CPU time 118.76 seconds
Started Jul 12 05:41:31 PM PDT 24
Finished Jul 12 05:43:30 PM PDT 24
Peak memory 191312 kb
Host smart-0b0d1a69-1b14-4a3a-b3cd-7400169a2357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520123835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.2520123835
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.1340907396
Short name T259
Test name
Test status
Simulation time 66063057859 ps
CPU time 406.91 seconds
Started Jul 12 05:41:27 PM PDT 24
Finished Jul 12 05:48:15 PM PDT 24
Peak memory 191280 kb
Host smart-6485d070-e192-4cc0-851b-4b6d8d95f626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340907396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1340907396
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1234079136
Short name T364
Test name
Test status
Simulation time 46819910291 ps
CPU time 88.09 seconds
Started Jul 12 05:41:27 PM PDT 24
Finished Jul 12 05:42:57 PM PDT 24
Peak memory 183064 kb
Host smart-d91cb3ad-f1b6-41db-b35a-134b9ae9f60f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234079136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1234079136
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3698220029
Short name T206
Test name
Test status
Simulation time 143993589692 ps
CPU time 205.77 seconds
Started Jul 12 05:41:27 PM PDT 24
Finished Jul 12 05:44:54 PM PDT 24
Peak memory 191300 kb
Host smart-8796bddb-6d90-498a-83c1-43541fd8c05d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698220029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3698220029
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.862126705
Short name T322
Test name
Test status
Simulation time 93791408207 ps
CPU time 153.3 seconds
Started Jul 12 05:41:28 PM PDT 24
Finished Jul 12 05:44:03 PM PDT 24
Peak memory 191196 kb
Host smart-4e8a72fd-6e0c-4d30-b06e-b027091c3b87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862126705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.862126705
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.1412919335
Short name T432
Test name
Test status
Simulation time 222838784596 ps
CPU time 140.74 seconds
Started Jul 12 05:41:28 PM PDT 24
Finished Jul 12 05:43:50 PM PDT 24
Peak memory 191232 kb
Host smart-11ef9bf3-7175-48e2-a41b-5bbe7fef1712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412919335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.1412919335
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3723783336
Short name T343
Test name
Test status
Simulation time 15064178969 ps
CPU time 21.64 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 05:40:30 PM PDT 24
Peak memory 183000 kb
Host smart-4138c536-4866-4be6-bc45-e3f8f1677df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723783336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3723783336
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.1547728134
Short name T292
Test name
Test status
Simulation time 21133811495 ps
CPU time 40.86 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 05:40:46 PM PDT 24
Peak memory 191296 kb
Host smart-a0f3e14b-7b0f-4732-b4eb-7c09abef5954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547728134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.1547728134
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/193.rv_timer_random.1170077932
Short name T278
Test name
Test status
Simulation time 168351510063 ps
CPU time 592.94 seconds
Started Jul 12 05:41:33 PM PDT 24
Finished Jul 12 05:51:27 PM PDT 24
Peak memory 191180 kb
Host smart-9cb3dde5-ba4e-492e-b93d-fc1c76123f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170077932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1170077932
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1843698447
Short name T200
Test name
Test status
Simulation time 36318356298 ps
CPU time 102.06 seconds
Started Jul 12 05:41:33 PM PDT 24
Finished Jul 12 05:43:16 PM PDT 24
Peak memory 193188 kb
Host smart-ab5b735c-4f02-45fa-b94d-d15c2b8f4586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843698447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1843698447
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.3190689457
Short name T297
Test name
Test status
Simulation time 325138544442 ps
CPU time 100.7 seconds
Started Jul 12 05:41:34 PM PDT 24
Finished Jul 12 05:43:16 PM PDT 24
Peak memory 191292 kb
Host smart-1b74bdd8-00c2-4585-9068-ca227a3a05f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190689457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.3190689457
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3432069396
Short name T6
Test name
Test status
Simulation time 414633568471 ps
CPU time 323.85 seconds
Started Jul 12 05:41:34 PM PDT 24
Finished Jul 12 05:46:58 PM PDT 24
Peak memory 191208 kb
Host smart-cbddfce2-7f72-440a-a1f0-8095a200a5a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432069396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3432069396
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.315887078
Short name T98
Test name
Test status
Simulation time 3198076597012 ps
CPU time 2978.34 seconds
Started Jul 12 05:41:34 PM PDT 24
Finished Jul 12 06:31:13 PM PDT 24
Peak memory 191292 kb
Host smart-dab6930d-48ad-4f9a-b2a4-52e2392c3557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315887078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.315887078
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2335236529
Short name T104
Test name
Test status
Simulation time 227935548829 ps
CPU time 400.92 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 05:46:24 PM PDT 24
Peak memory 183088 kb
Host smart-f56e83f2-01b5-4e1c-971b-ecc80d488af4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335236529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2335236529
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3455064772
Short name T395
Test name
Test status
Simulation time 224956639804 ps
CPU time 212.66 seconds
Started Jul 12 05:39:39 PM PDT 24
Finished Jul 12 05:43:13 PM PDT 24
Peak memory 183028 kb
Host smart-de3e76a2-b20d-4cc8-b38e-73e7d7133499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455064772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3455064772
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.1410973301
Short name T44
Test name
Test status
Simulation time 39402318931 ps
CPU time 65.62 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 05:40:49 PM PDT 24
Peak memory 191240 kb
Host smart-a14f92f2-ab8e-4bef-b7d2-537052f05dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410973301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.1410973301
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.1451634863
Short name T15
Test name
Test status
Simulation time 116689252 ps
CPU time 0.76 seconds
Started Jul 12 05:39:42 PM PDT 24
Finished Jul 12 05:39:44 PM PDT 24
Peak memory 213468 kb
Host smart-2d49f916-c39b-48c0-9b9d-a889d2c8f6f7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451634863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.1451634863
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1782269948
Short name T436
Test name
Test status
Simulation time 790885096978 ps
CPU time 525.81 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 05:48:28 PM PDT 24
Peak memory 195636 kb
Host smart-3e7a711d-774f-4688-9507-6af34ad57219
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782269948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1782269948
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2000301331
Short name T134
Test name
Test status
Simulation time 1335849102650 ps
CPU time 724.7 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 05:52:12 PM PDT 24
Peak memory 183092 kb
Host smart-209972fc-d24f-4192-98e1-8337dee77ffd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000301331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2000301331
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.4217058776
Short name T400
Test name
Test status
Simulation time 220309566347 ps
CPU time 106.5 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:41:53 PM PDT 24
Peak memory 183088 kb
Host smart-83afa3bc-f114-473d-b341-0e905b0bd207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217058776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.4217058776
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all_with_rand_reset.3530645225
Short name T14
Test name
Test status
Simulation time 43224179646 ps
CPU time 344.13 seconds
Started Jul 12 05:40:04 PM PDT 24
Finished Jul 12 05:45:50 PM PDT 24
Peak memory 206860 kb
Host smart-a1696702-9d6c-4591-ada2-78eb723be3dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530645225 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all_with_rand_reset.3530645225
Directory /workspace/20.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.2791598032
Short name T123
Test name
Test status
Simulation time 3593600237023 ps
CPU time 929.75 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:55:37 PM PDT 24
Peak memory 182976 kb
Host smart-c9204b58-232a-4ddf-8f12-c2428d084115
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791598032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.2791598032
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3037259367
Short name T429
Test name
Test status
Simulation time 406190335553 ps
CPU time 283.29 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 05:44:52 PM PDT 24
Peak memory 182976 kb
Host smart-3efd90db-0dba-4395-b35d-843b00266805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037259367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3037259367
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.2370453463
Short name T402
Test name
Test status
Simulation time 316085901 ps
CPU time 0.73 seconds
Started Jul 12 05:40:07 PM PDT 24
Finished Jul 12 05:40:10 PM PDT 24
Peak memory 182960 kb
Host smart-2f057c0e-0bca-457d-b07c-7a380b005a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370453463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.2370453463
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.464018993
Short name T397
Test name
Test status
Simulation time 791575980315 ps
CPU time 328.3 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 195864 kb
Host smart-d3866427-37ef-4356-a572-4528935582f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464018993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all.
464018993
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.2191806145
Short name T157
Test name
Test status
Simulation time 396986689064 ps
CPU time 644.85 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:50:51 PM PDT 24
Peak memory 183100 kb
Host smart-2fc33f4c-0b7d-4f2a-9803-dda3a7a94e40
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191806145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.2191806145
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.1879278741
Short name T224
Test name
Test status
Simulation time 563601300857 ps
CPU time 287.81 seconds
Started Jul 12 05:40:07 PM PDT 24
Finished Jul 12 05:44:57 PM PDT 24
Peak memory 195028 kb
Host smart-4a11c120-bc0a-4e31-a9ae-a5634244864a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879278741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1879278741
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2566509496
Short name T332
Test name
Test status
Simulation time 199662776719 ps
CPU time 124.06 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:42:11 PM PDT 24
Peak memory 191256 kb
Host smart-0fe44e9d-1b77-4425-8fe4-74ed6dfdd024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566509496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2566509496
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.2670355809
Short name T105
Test name
Test status
Simulation time 172408625142 ps
CPU time 243.5 seconds
Started Jul 12 05:40:05 PM PDT 24
Finished Jul 12 05:44:10 PM PDT 24
Peak memory 183088 kb
Host smart-1e06dbb6-2f87-4d02-9457-9462df58ddd7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670355809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.2670355809
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.1450876023
Short name T451
Test name
Test status
Simulation time 425563695540 ps
CPU time 167.87 seconds
Started Jul 12 05:40:03 PM PDT 24
Finished Jul 12 05:42:52 PM PDT 24
Peak memory 183104 kb
Host smart-0c40aed0-0713-4c31-b4af-4ddf9442d125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450876023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.1450876023
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2667634399
Short name T302
Test name
Test status
Simulation time 83587474318 ps
CPU time 241.63 seconds
Started Jul 12 05:40:06 PM PDT 24
Finished Jul 12 05:44:09 PM PDT 24
Peak memory 191520 kb
Host smart-c82674c1-f8fe-4e80-a637-48581744094d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667634399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2667634399
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2851322868
Short name T57
Test name
Test status
Simulation time 187165903121 ps
CPU time 268.12 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:44:41 PM PDT 24
Peak memory 194920 kb
Host smart-0a499882-5c9e-4b2d-9183-ce055ae95717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851322868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2851322868
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3958390786
Short name T198
Test name
Test status
Simulation time 510163388782 ps
CPU time 214.1 seconds
Started Jul 12 05:40:13 PM PDT 24
Finished Jul 12 05:43:49 PM PDT 24
Peak memory 183112 kb
Host smart-3dff9397-333b-47c9-85cb-82904ea1d265
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958390786 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3958390786
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.2187279115
Short name T358
Test name
Test status
Simulation time 358109071953 ps
CPU time 117.04 seconds
Started Jul 12 05:40:10 PM PDT 24
Finished Jul 12 05:42:08 PM PDT 24
Peak memory 183116 kb
Host smart-b01e4dad-d6ad-45ac-8a79-2feba0d0a617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187279115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.2187279115
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2740301730
Short name T263
Test name
Test status
Simulation time 468231619281 ps
CPU time 591.56 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:50:05 PM PDT 24
Peak memory 191184 kb
Host smart-61abac52-f48d-4721-a680-3b39cd2ab649
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740301730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2740301730
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1129590160
Short name T392
Test name
Test status
Simulation time 47138919 ps
CPU time 0.53 seconds
Started Jul 12 05:40:13 PM PDT 24
Finished Jul 12 05:40:16 PM PDT 24
Peak memory 182960 kb
Host smart-ee534e43-e4d5-4485-978c-ef6f25926d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129590160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1129590160
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.1594003462
Short name T324
Test name
Test status
Simulation time 136882009720 ps
CPU time 173.48 seconds
Started Jul 12 05:40:09 PM PDT 24
Finished Jul 12 05:43:04 PM PDT 24
Peak memory 183080 kb
Host smart-f7c88f1b-102a-4b30-873c-5912fe8116e5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594003462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.1594003462
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.822130121
Short name T83
Test name
Test status
Simulation time 69535389522 ps
CPU time 28.77 seconds
Started Jul 12 05:40:14 PM PDT 24
Finished Jul 12 05:40:44 PM PDT 24
Peak memory 183104 kb
Host smart-df3a3a6a-a6e2-4da5-867f-3c1925c7c16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822130121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.822130121
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.1195019540
Short name T1
Test name
Test status
Simulation time 967961893182 ps
CPU time 572.42 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:49:47 PM PDT 24
Peak memory 193332 kb
Host smart-9a879118-3711-4a22-bd96-731a4d44204a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195019540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1195019540
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3588961394
Short name T411
Test name
Test status
Simulation time 141671779 ps
CPU time 0.74 seconds
Started Jul 12 05:40:10 PM PDT 24
Finished Jul 12 05:40:11 PM PDT 24
Peak memory 182964 kb
Host smart-b2b2a21f-668b-4d41-bfd3-a779effbe9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588961394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3588961394
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.4183421604
Short name T333
Test name
Test status
Simulation time 120439562109 ps
CPU time 105.78 seconds
Started Jul 12 05:40:13 PM PDT 24
Finished Jul 12 05:42:01 PM PDT 24
Peak memory 183108 kb
Host smart-b111ed10-010b-411c-8f08-f455749c2180
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183421604 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.4183421604
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.2306882631
Short name T349
Test name
Test status
Simulation time 39138831343 ps
CPU time 57.72 seconds
Started Jul 12 05:40:15 PM PDT 24
Finished Jul 12 05:41:14 PM PDT 24
Peak memory 183016 kb
Host smart-cbb85ed2-ecec-45c9-9606-aa857abfd2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306882631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.2306882631
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3090190894
Short name T209
Test name
Test status
Simulation time 19430264009 ps
CPU time 27.19 seconds
Started Jul 12 05:40:15 PM PDT 24
Finished Jul 12 05:40:43 PM PDT 24
Peak memory 183104 kb
Host smart-67f6fa50-7eab-4f2b-b673-0b6fba7f996d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090190894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3090190894
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all_with_rand_reset.3062706726
Short name T38
Test name
Test status
Simulation time 40788720387 ps
CPU time 157.28 seconds
Started Jul 12 05:40:13 PM PDT 24
Finished Jul 12 05:42:52 PM PDT 24
Peak memory 197792 kb
Host smart-f34e7555-a1e6-43de-9c41-19c902a7ee68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062706726 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all_with_rand_reset.3062706726
Directory /workspace/26.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3592963822
Short name T272
Test name
Test status
Simulation time 573685731286 ps
CPU time 219.9 seconds
Started Jul 12 05:40:11 PM PDT 24
Finished Jul 12 05:43:52 PM PDT 24
Peak memory 183092 kb
Host smart-263d87b9-1454-487e-846a-46513f3fc5be
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592963822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3592963822
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.1794450731
Short name T375
Test name
Test status
Simulation time 61609419502 ps
CPU time 30.79 seconds
Started Jul 12 05:40:10 PM PDT 24
Finished Jul 12 05:40:41 PM PDT 24
Peak memory 183028 kb
Host smart-59538753-8add-4421-b807-4ff3c091c48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794450731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.1794450731
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2439087075
Short name T181
Test name
Test status
Simulation time 1311730994539 ps
CPU time 814.09 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:53:48 PM PDT 24
Peak memory 191236 kb
Host smart-dbcc441d-8678-460e-a599-49358bdd98c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439087075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2439087075
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.511491806
Short name T355
Test name
Test status
Simulation time 8462531854 ps
CPU time 30.77 seconds
Started Jul 12 05:40:17 PM PDT 24
Finished Jul 12 05:40:48 PM PDT 24
Peak memory 191296 kb
Host smart-236aeffd-5054-4764-92a9-c6aab60bf07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511491806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.511491806
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3790765703
Short name T388
Test name
Test status
Simulation time 224406404577 ps
CPU time 302.25 seconds
Started Jul 12 05:40:10 PM PDT 24
Finished Jul 12 05:45:13 PM PDT 24
Peak memory 191516 kb
Host smart-be2d9394-9b4c-4098-84cc-7876381619e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790765703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3790765703
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1787244127
Short name T244
Test name
Test status
Simulation time 228144262549 ps
CPU time 360.99 seconds
Started Jul 12 05:40:10 PM PDT 24
Finished Jul 12 05:46:13 PM PDT 24
Peak memory 182924 kb
Host smart-f75260cb-f45e-40ad-a9e5-b2305db4cb47
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787244127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1787244127
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.390320302
Short name T385
Test name
Test status
Simulation time 928566649791 ps
CPU time 107.58 seconds
Started Jul 12 05:40:15 PM PDT 24
Finished Jul 12 05:42:04 PM PDT 24
Peak memory 183112 kb
Host smart-b09357d7-ab48-4870-a6d4-7e5a8cbcc050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390320302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.390320302
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2743105087
Short name T119
Test name
Test status
Simulation time 116618745576 ps
CPU time 107.38 seconds
Started Jul 12 05:40:11 PM PDT 24
Finished Jul 12 05:42:00 PM PDT 24
Peak memory 191264 kb
Host smart-9d93e31e-aac9-443f-8923-8d64fa970351
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743105087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2743105087
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.744928766
Short name T194
Test name
Test status
Simulation time 277665564030 ps
CPU time 196.97 seconds
Started Jul 12 05:40:13 PM PDT 24
Finished Jul 12 05:43:32 PM PDT 24
Peak memory 194652 kb
Host smart-56c9dc9c-32d6-4cde-a936-558b2844308d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744928766 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.744928766
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.4073646504
Short name T220
Test name
Test status
Simulation time 799274128142 ps
CPU time 1006.86 seconds
Started Jul 12 05:40:15 PM PDT 24
Finished Jul 12 05:57:03 PM PDT 24
Peak memory 191276 kb
Host smart-99d05dea-0d3f-4e5d-abc3-0f6706f5539d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073646504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.4073646504
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2197746570
Short name T447
Test name
Test status
Simulation time 70238944871 ps
CPU time 45.59 seconds
Started Jul 12 05:40:11 PM PDT 24
Finished Jul 12 05:40:59 PM PDT 24
Peak memory 183056 kb
Host smart-4c49bfd7-d4cd-4258-8c58-3616cabfe86e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197746570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2197746570
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.4069542566
Short name T281
Test name
Test status
Simulation time 200088220503 ps
CPU time 142.85 seconds
Started Jul 12 05:40:10 PM PDT 24
Finished Jul 12 05:42:34 PM PDT 24
Peak memory 191264 kb
Host smart-68aed56d-3236-4cc9-9914-bb04d14b9656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069542566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.4069542566
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.748357793
Short name T170
Test name
Test status
Simulation time 29982571282 ps
CPU time 53.44 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:41:07 PM PDT 24
Peak memory 183112 kb
Host smart-ae0b8111-34f7-473b-a324-215380b4cc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748357793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.748357793
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.1085839703
Short name T327
Test name
Test status
Simulation time 227848157430 ps
CPU time 112.58 seconds
Started Jul 12 05:39:39 PM PDT 24
Finished Jul 12 05:41:33 PM PDT 24
Peak memory 183032 kb
Host smart-06a8f224-28e3-4fd1-a2db-cbb43991d5fb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085839703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.1085839703
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2651943006
Short name T449
Test name
Test status
Simulation time 71179187712 ps
CPU time 96.14 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 05:41:19 PM PDT 24
Peak memory 183084 kb
Host smart-8332fd1a-4a2a-447f-b624-4711d5a8d1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651943006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2651943006
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.537254804
Short name T389
Test name
Test status
Simulation time 7595075093 ps
CPU time 12.1 seconds
Started Jul 12 05:39:42 PM PDT 24
Finished Jul 12 05:39:56 PM PDT 24
Peak memory 183028 kb
Host smart-6eafd8bc-1a1d-49fa-80dc-e7192815bff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537254804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.537254804
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.1505394525
Short name T16
Test name
Test status
Simulation time 33263066 ps
CPU time 0.72 seconds
Started Jul 12 05:39:46 PM PDT 24
Finished Jul 12 05:39:48 PM PDT 24
Peak memory 213344 kb
Host smart-568c799f-6399-4663-838f-ed52bf5d7541
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505394525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.1505394525
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3979434456
Short name T430
Test name
Test status
Simulation time 1113741045479 ps
CPU time 358.29 seconds
Started Jul 12 05:39:47 PM PDT 24
Finished Jul 12 05:45:47 PM PDT 24
Peak memory 183084 kb
Host smart-bbbe74ba-e2f9-46c7-b6c5-214b10edac4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979434456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3979434456
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.1398409077
Short name T420
Test name
Test status
Simulation time 20151457043 ps
CPU time 227.45 seconds
Started Jul 12 05:39:41 PM PDT 24
Finished Jul 12 05:43:31 PM PDT 24
Peak memory 198016 kb
Host smart-1575ef9a-66f9-4b75-96d9-c5ec467fb90c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398409077 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.1398409077
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2916371009
Short name T414
Test name
Test status
Simulation time 592298044167 ps
CPU time 88.64 seconds
Started Jul 12 05:40:13 PM PDT 24
Finished Jul 12 05:41:43 PM PDT 24
Peak memory 183104 kb
Host smart-4b7044fc-8e4c-418b-b23f-24453b47a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916371009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2916371009
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.3849127966
Short name T438
Test name
Test status
Simulation time 76952985101 ps
CPU time 78.22 seconds
Started Jul 12 05:40:13 PM PDT 24
Finished Jul 12 05:41:33 PM PDT 24
Peak memory 183088 kb
Host smart-5568bcf1-a844-413c-bce6-ef059ebcd996
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849127966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3849127966
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.2429978219
Short name T320
Test name
Test status
Simulation time 78738533739 ps
CPU time 232.12 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:44:06 PM PDT 24
Peak memory 191296 kb
Host smart-5dbc0e7d-52c6-489b-9d52-ba7a5dd51c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429978219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.2429978219
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.1482626091
Short name T305
Test name
Test status
Simulation time 293727050756 ps
CPU time 501.29 seconds
Started Jul 12 05:40:11 PM PDT 24
Finished Jul 12 05:48:34 PM PDT 24
Peak memory 191300 kb
Host smart-3ff000f2-9e40-4638-b838-e3e6d816d5b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482626091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.1482626091
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.1895395751
Short name T237
Test name
Test status
Simulation time 1785514840096 ps
CPU time 928.12 seconds
Started Jul 12 05:40:13 PM PDT 24
Finished Jul 12 05:55:43 PM PDT 24
Peak memory 183080 kb
Host smart-1328bfd3-ebe1-4b1d-aa36-a3c4f19f7af0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895395751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.1895395751
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.1752691122
Short name T348
Test name
Test status
Simulation time 807070543463 ps
CPU time 193.63 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:43:28 PM PDT 24
Peak memory 183100 kb
Host smart-8b279972-d756-4229-bb61-e70a1d4db2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752691122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.1752691122
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2474887737
Short name T446
Test name
Test status
Simulation time 240021157926 ps
CPU time 155.42 seconds
Started Jul 12 05:40:17 PM PDT 24
Finished Jul 12 05:42:53 PM PDT 24
Peak memory 191184 kb
Host smart-29d897f0-6446-45d0-b699-252db16ab326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474887737 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2474887737
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.4290066576
Short name T340
Test name
Test status
Simulation time 16956950306 ps
CPU time 15.43 seconds
Started Jul 12 05:40:13 PM PDT 24
Finished Jul 12 05:40:30 PM PDT 24
Peak memory 183104 kb
Host smart-84628abc-b8c4-4458-a6b4-55272d146327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290066576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.4290066576
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.2774925373
Short name T357
Test name
Test status
Simulation time 98847625 ps
CPU time 0.64 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:40:14 PM PDT 24
Peak memory 182920 kb
Host smart-5bc5d1fb-5ad9-48d3-bc1e-94cf092d08e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774925373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.2774925373
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.353082606
Short name T360
Test name
Test status
Simulation time 76751074722 ps
CPU time 121.03 seconds
Started Jul 12 05:40:10 PM PDT 24
Finished Jul 12 05:42:11 PM PDT 24
Peak memory 182996 kb
Host smart-3fc1fc06-400d-4390-841d-93b4d1d0b390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353082606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.353082606
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.2769162057
Short name T422
Test name
Test status
Simulation time 499008881039 ps
CPU time 1785.38 seconds
Started Jul 12 05:40:13 PM PDT 24
Finished Jul 12 06:10:00 PM PDT 24
Peak memory 191296 kb
Host smart-3184958a-3ff4-4eb4-9371-0356efdd25e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769162057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.2769162057
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3600013060
Short name T122
Test name
Test status
Simulation time 8749697834 ps
CPU time 68.72 seconds
Started Jul 12 05:40:12 PM PDT 24
Finished Jul 12 05:41:23 PM PDT 24
Peak memory 183096 kb
Host smart-5d077d86-2e39-4bdd-a450-e7590f8dd639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600013060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3600013060
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1621208653
Short name T344
Test name
Test status
Simulation time 495451828328 ps
CPU time 188.66 seconds
Started Jul 12 05:40:11 PM PDT 24
Finished Jul 12 05:43:22 PM PDT 24
Peak memory 183068 kb
Host smart-46dbb458-79d7-49d8-851b-48f17cbddba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621208653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1621208653
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.1396640186
Short name T120
Test name
Test status
Simulation time 283463047723 ps
CPU time 318.08 seconds
Started Jul 12 05:40:17 PM PDT 24
Finished Jul 12 05:45:35 PM PDT 24
Peak memory 182972 kb
Host smart-253cddf0-e17c-4d9a-b18e-1c90aa69fbf1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396640186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.1396640186
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2400504754
Short name T418
Test name
Test status
Simulation time 122143927281 ps
CPU time 111.37 seconds
Started Jul 12 05:40:15 PM PDT 24
Finished Jul 12 05:42:07 PM PDT 24
Peak memory 183088 kb
Host smart-a9411aec-da2d-48c0-adda-3a62513dfd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400504754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2400504754
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.121624964
Short name T345
Test name
Test status
Simulation time 690863386 ps
CPU time 0.64 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:40:21 PM PDT 24
Peak memory 182940 kb
Host smart-87ee96e5-fec4-4c0f-b614-068857afe2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121624964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.121624964
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.2521767807
Short name T440
Test name
Test status
Simulation time 139288045 ps
CPU time 0.69 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:40:22 PM PDT 24
Peak memory 182916 kb
Host smart-27e86f33-7220-48fd-bf22-1bf0748263cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521767807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.2521767807
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.537874252
Short name T36
Test name
Test status
Simulation time 57039392628 ps
CPU time 493.65 seconds
Started Jul 12 05:40:18 PM PDT 24
Finished Jul 12 05:48:33 PM PDT 24
Peak memory 205892 kb
Host smart-b1e04c9e-0840-4ad7-8474-5bde3d4ec324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537874252 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.537874252
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2257783670
Short name T310
Test name
Test status
Simulation time 201578991415 ps
CPU time 298.62 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:45:20 PM PDT 24
Peak memory 183068 kb
Host smart-d3eace37-f6df-459f-b19c-5925b271b014
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257783670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2257783670
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.1844488026
Short name T28
Test name
Test status
Simulation time 84510248821 ps
CPU time 128.69 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:42:32 PM PDT 24
Peak memory 183072 kb
Host smart-f5e64cab-879a-47fe-baeb-65a92ada27a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844488026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.1844488026
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.251724578
Short name T439
Test name
Test status
Simulation time 132660102314 ps
CPU time 335.58 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:45:59 PM PDT 24
Peak memory 191280 kb
Host smart-e38c66ef-0235-4fce-8c0c-85ea2e2a4f8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251724578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.251724578
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.2569392960
Short name T149
Test name
Test status
Simulation time 79378221495 ps
CPU time 473.07 seconds
Started Jul 12 05:40:22 PM PDT 24
Finished Jul 12 05:48:18 PM PDT 24
Peak memory 193392 kb
Host smart-6fa65bee-0534-46da-8236-85846639ec79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569392960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.2569392960
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.891919533
Short name T87
Test name
Test status
Simulation time 92355594222 ps
CPU time 876.11 seconds
Started Jul 12 05:40:21 PM PDT 24
Finished Jul 12 05:55:00 PM PDT 24
Peak memory 205948 kb
Host smart-a7179600-f81a-4da2-980b-3b2277474fec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891919533 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.891919533
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1536426013
Short name T131
Test name
Test status
Simulation time 105899844419 ps
CPU time 77.99 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:41:39 PM PDT 24
Peak memory 182964 kb
Host smart-d74a3266-94f5-4857-b49f-fd4aa61cc47a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536426013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1536426013
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1562505665
Short name T9
Test name
Test status
Simulation time 149744718494 ps
CPU time 226.78 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:44:10 PM PDT 24
Peak memory 183116 kb
Host smart-78d3940f-b5b9-4407-bdf4-e54e8b481754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562505665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1562505665
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.3567927411
Short name T312
Test name
Test status
Simulation time 76373555842 ps
CPU time 126.18 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:42:29 PM PDT 24
Peak memory 194992 kb
Host smart-f89aea87-0ed6-4425-b623-a4caeed3f694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567927411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.3567927411
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4121472161
Short name T369
Test name
Test status
Simulation time 114713687 ps
CPU time 0.94 seconds
Started Jul 12 05:40:22 PM PDT 24
Finished Jul 12 05:40:26 PM PDT 24
Peak memory 183040 kb
Host smart-961e7c53-94d9-438f-9137-1b970140f9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121472161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4121472161
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.2088873835
Short name T253
Test name
Test status
Simulation time 336599752465 ps
CPU time 428.59 seconds
Started Jul 12 05:40:19 PM PDT 24
Finished Jul 12 05:47:29 PM PDT 24
Peak memory 195732 kb
Host smart-718ea436-ac03-4ec4-8529-902195c220a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088873835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.2088873835
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.549581808
Short name T86
Test name
Test status
Simulation time 98182725710 ps
CPU time 953.69 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:56:16 PM PDT 24
Peak memory 211960 kb
Host smart-54ddc114-ac45-4614-b637-f2c53d9ad47d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549581808 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.549581808
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1601831179
Short name T314
Test name
Test status
Simulation time 625408460855 ps
CPU time 235.97 seconds
Started Jul 12 05:40:18 PM PDT 24
Finished Jul 12 05:44:14 PM PDT 24
Peak memory 183056 kb
Host smart-370bca66-89e0-41aa-a631-a984a6a85609
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601831179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1601831179
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.1751844597
Short name T373
Test name
Test status
Simulation time 110452905752 ps
CPU time 141.45 seconds
Started Jul 12 05:40:19 PM PDT 24
Finished Jul 12 05:42:41 PM PDT 24
Peak memory 183036 kb
Host smart-bb6e69aa-c068-40a8-b45b-8179a22a6985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751844597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.1751844597
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1344055474
Short name T174
Test name
Test status
Simulation time 546355618426 ps
CPU time 593.79 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:50:16 PM PDT 24
Peak memory 191184 kb
Host smart-1aac924d-4e51-40a2-b6f4-15879c940460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344055474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1344055474
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.83745906
Short name T228
Test name
Test status
Simulation time 41892272711 ps
CPU time 34.65 seconds
Started Jul 12 05:40:19 PM PDT 24
Finished Jul 12 05:40:54 PM PDT 24
Peak memory 183104 kb
Host smart-d03a5074-f4a8-4878-b8fc-efca8acb0d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83745906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.83745906
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1782017160
Short name T304
Test name
Test status
Simulation time 366388008017 ps
CPU time 660.31 seconds
Started Jul 12 05:40:21 PM PDT 24
Finished Jul 12 05:51:24 PM PDT 24
Peak memory 183112 kb
Host smart-f8725a06-32b8-4a25-8378-79b666ca5659
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782017160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1782017160
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3956472499
Short name T437
Test name
Test status
Simulation time 229017279217 ps
CPU time 45.5 seconds
Started Jul 12 05:40:18 PM PDT 24
Finished Jul 12 05:41:04 PM PDT 24
Peak memory 182988 kb
Host smart-d9298fd5-9f52-4e61-a3dc-7d6771ce6ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956472499 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3956472499
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.680910696
Short name T81
Test name
Test status
Simulation time 156473192690 ps
CPU time 316.93 seconds
Started Jul 12 05:40:21 PM PDT 24
Finished Jul 12 05:45:40 PM PDT 24
Peak memory 191272 kb
Host smart-c240ffb3-a791-4641-b1ee-b28fe0142b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680910696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.680910696
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2276921704
Short name T100
Test name
Test status
Simulation time 5792474825 ps
CPU time 8.53 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:40:30 PM PDT 24
Peak memory 183084 kb
Host smart-f125511d-b422-4cc3-8ed5-1c8afb4ad239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276921704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2276921704
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.4207396218
Short name T26
Test name
Test status
Simulation time 376345892858 ps
CPU time 663.76 seconds
Started Jul 12 05:40:18 PM PDT 24
Finished Jul 12 05:51:22 PM PDT 24
Peak memory 191296 kb
Host smart-27e5035b-f458-4902-b27b-a428befddf23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207396218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.4207396218
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2978717617
Short name T423
Test name
Test status
Simulation time 369552342104 ps
CPU time 149.93 seconds
Started Jul 12 05:40:19 PM PDT 24
Finished Jul 12 05:42:49 PM PDT 24
Peak memory 183108 kb
Host smart-15f1f207-2d86-401b-9c48-f9a631539b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978717617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2978717617
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1130754567
Short name T202
Test name
Test status
Simulation time 429594919846 ps
CPU time 443.51 seconds
Started Jul 12 05:40:18 PM PDT 24
Finished Jul 12 05:47:42 PM PDT 24
Peak memory 191296 kb
Host smart-dcae14f3-76de-429f-9bf5-9b32f0c7c732
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130754567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1130754567
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2300977251
Short name T361
Test name
Test status
Simulation time 150679172 ps
CPU time 0.69 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:40:24 PM PDT 24
Peak memory 182976 kb
Host smart-b19f64e5-e1bb-484e-a93b-7f64669de316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300977251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2300977251
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3978571210
Short name T116
Test name
Test status
Simulation time 3153608125278 ps
CPU time 3219.23 seconds
Started Jul 12 05:40:21 PM PDT 24
Finished Jul 12 06:34:03 PM PDT 24
Peak memory 194920 kb
Host smart-303de960-d902-4afc-9486-8ff6657a036f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978571210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3978571210
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.508742044
Short name T37
Test name
Test status
Simulation time 90541193512 ps
CPU time 388.53 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:46:52 PM PDT 24
Peak memory 205992 kb
Host smart-6c2ac554-3677-417a-8746-20f02a5e1fae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508742044 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.508742044
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_random.1541654519
Short name T294
Test name
Test status
Simulation time 13226988151 ps
CPU time 79.75 seconds
Started Jul 12 05:40:21 PM PDT 24
Finished Jul 12 05:41:44 PM PDT 24
Peak memory 183072 kb
Host smart-dfba908e-dc7d-4049-9c83-f3e235a0532e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541654519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.1541654519
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.3915746324
Short name T408
Test name
Test status
Simulation time 194942886 ps
CPU time 1.03 seconds
Started Jul 12 05:40:21 PM PDT 24
Finished Jul 12 05:40:25 PM PDT 24
Peak memory 182956 kb
Host smart-864c3851-fd70-4682-829f-8302b1140d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915746324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.3915746324
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.431854659
Short name T11
Test name
Test status
Simulation time 1886456994491 ps
CPU time 1584.6 seconds
Started Jul 12 05:40:22 PM PDT 24
Finished Jul 12 06:06:50 PM PDT 24
Peak memory 191304 kb
Host smart-de56333f-69f4-470e-9a46-251c21791a2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431854659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
431854659
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2761746977
Short name T162
Test name
Test status
Simulation time 336746032995 ps
CPU time 555.44 seconds
Started Jul 12 05:39:50 PM PDT 24
Finished Jul 12 05:49:06 PM PDT 24
Peak memory 183072 kb
Host smart-df4509a6-84b1-4785-a4e4-3350abcbb938
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761746977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2761746977
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1082635787
Short name T425
Test name
Test status
Simulation time 282032640633 ps
CPU time 81.6 seconds
Started Jul 12 05:39:47 PM PDT 24
Finished Jul 12 05:41:09 PM PDT 24
Peak memory 183100 kb
Host smart-9f9df5b8-10d2-4600-a56d-1bb3f235def4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082635787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1082635787
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3226808787
Short name T284
Test name
Test status
Simulation time 147169440593 ps
CPU time 69.53 seconds
Started Jul 12 05:39:46 PM PDT 24
Finished Jul 12 05:40:56 PM PDT 24
Peak memory 183092 kb
Host smart-c2f11bc1-97a0-414b-8280-c126e2a17bd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226808787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3226808787
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.4265647223
Short name T421
Test name
Test status
Simulation time 641622391 ps
CPU time 0.9 seconds
Started Jul 12 05:39:48 PM PDT 24
Finished Jul 12 05:39:50 PM PDT 24
Peak memory 191812 kb
Host smart-46262b20-e62b-468c-96a5-3ec92893b4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265647223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.4265647223
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2614559829
Short name T18
Test name
Test status
Simulation time 53354883 ps
CPU time 0.83 seconds
Started Jul 12 05:39:52 PM PDT 24
Finished Jul 12 05:39:54 PM PDT 24
Peak memory 213340 kb
Host smart-d0436452-79e9-409e-97a9-2268d94775e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614559829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2614559829
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2843060005
Short name T396
Test name
Test status
Simulation time 344177344672 ps
CPU time 169.9 seconds
Started Jul 12 05:40:19 PM PDT 24
Finished Jul 12 05:43:11 PM PDT 24
Peak memory 183116 kb
Host smart-1d7c13e5-a788-4333-95a7-878e5c22c604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843060005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2843060005
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1613564785
Short name T22
Test name
Test status
Simulation time 206204541004 ps
CPU time 93.21 seconds
Started Jul 12 05:40:21 PM PDT 24
Finished Jul 12 05:41:57 PM PDT 24
Peak memory 191320 kb
Host smart-e2084eff-0447-4635-95b3-2196bae1c2eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613564785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1613564785
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2692708357
Short name T336
Test name
Test status
Simulation time 339902582254 ps
CPU time 115.63 seconds
Started Jul 12 05:40:22 PM PDT 24
Finished Jul 12 05:42:20 PM PDT 24
Peak memory 193564 kb
Host smart-e52b8b4e-d070-46f2-9747-7a5e182a0e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692708357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2692708357
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2785161767
Short name T173
Test name
Test status
Simulation time 262285307850 ps
CPU time 601.68 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:50:24 PM PDT 24
Peak memory 195136 kb
Host smart-e5e37eef-8e97-40b2-8061-35658e877366
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785161767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2785161767
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.701742214
Short name T245
Test name
Test status
Simulation time 179077065922 ps
CPU time 317.86 seconds
Started Jul 12 05:40:21 PM PDT 24
Finished Jul 12 05:45:42 PM PDT 24
Peak memory 183064 kb
Host smart-01b65991-965a-4382-bf51-cfb430243e3e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701742214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.701742214
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_random.733810180
Short name T215
Test name
Test status
Simulation time 16455810419 ps
CPU time 26.07 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:40:47 PM PDT 24
Peak memory 183104 kb
Host smart-7fa2453b-d419-467c-aa43-f7b612972ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733810180 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.733810180
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3893003882
Short name T78
Test name
Test status
Simulation time 69667045283 ps
CPU time 73.74 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:41:37 PM PDT 24
Peak memory 191312 kb
Host smart-12662f70-662d-4f15-992b-0c9c53ba201c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893003882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3893003882
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.1010936819
Short name T308
Test name
Test status
Simulation time 28814388683 ps
CPU time 27.15 seconds
Started Jul 12 05:40:24 PM PDT 24
Finished Jul 12 05:40:53 PM PDT 24
Peak memory 183084 kb
Host smart-8e1d5fe4-14b9-4b89-81ca-fa73e562bb3d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010936819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.1010936819
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3006181033
Short name T376
Test name
Test status
Simulation time 272937782789 ps
CPU time 154.25 seconds
Started Jul 12 05:40:23 PM PDT 24
Finished Jul 12 05:43:00 PM PDT 24
Peak memory 183000 kb
Host smart-b60b557c-2f37-4cb0-a6df-9d1d507c6153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006181033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3006181033
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.4283286977
Short name T341
Test name
Test status
Simulation time 351598562913 ps
CPU time 79.15 seconds
Started Jul 12 05:40:23 PM PDT 24
Finished Jul 12 05:41:45 PM PDT 24
Peak memory 183104 kb
Host smart-4c641169-82ab-45d8-9ed6-72cc8273bd59
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283286977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.4283286977
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.4167671061
Short name T307
Test name
Test status
Simulation time 110032127454 ps
CPU time 75.39 seconds
Started Jul 12 05:40:24 PM PDT 24
Finished Jul 12 05:41:41 PM PDT 24
Peak memory 191216 kb
Host smart-b082bce6-e60c-43f1-bc87-dcc4b61a294a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167671061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.4167671061
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.3823421451
Short name T40
Test name
Test status
Simulation time 65860206290 ps
CPU time 495.65 seconds
Started Jul 12 05:40:22 PM PDT 24
Finished Jul 12 05:48:40 PM PDT 24
Peak memory 206220 kb
Host smart-2434dc35-34fb-4926-aa77-505ebbe01843
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823421451 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.3823421451
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2633851216
Short name T264
Test name
Test status
Simulation time 325250583885 ps
CPU time 557.94 seconds
Started Jul 12 05:40:20 PM PDT 24
Finished Jul 12 05:49:41 PM PDT 24
Peak memory 183092 kb
Host smart-11ff04e1-a4e1-4442-ad69-519886a53ad4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633851216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2633851216
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2267600340
Short name T368
Test name
Test status
Simulation time 293450002012 ps
CPU time 48.66 seconds
Started Jul 12 05:40:22 PM PDT 24
Finished Jul 12 05:41:13 PM PDT 24
Peak memory 183308 kb
Host smart-d6a8d211-cce9-4bb7-baa2-ac1e98f34bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267600340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2267600340
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.786936502
Short name T381
Test name
Test status
Simulation time 275712276505 ps
CPU time 102.29 seconds
Started Jul 12 05:40:24 PM PDT 24
Finished Jul 12 05:42:08 PM PDT 24
Peak memory 194924 kb
Host smart-fff3d1d4-6111-4672-81b6-31461d7002c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786936502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.786936502
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3513024624
Short name T386
Test name
Test status
Simulation time 671989271561 ps
CPU time 276.09 seconds
Started Jul 12 05:40:23 PM PDT 24
Finished Jul 12 05:45:02 PM PDT 24
Peak memory 183068 kb
Host smart-b7881efe-5b1a-4fbb-8c02-de4a26f0623d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513024624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3513024624
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1350262666
Short name T199
Test name
Test status
Simulation time 380230645795 ps
CPU time 179.96 seconds
Started Jul 12 05:40:24 PM PDT 24
Finished Jul 12 05:43:26 PM PDT 24
Peak memory 182912 kb
Host smart-458cd94e-1a01-4321-ae51-9fc2104e4938
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350262666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1350262666
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.938879773
Short name T370
Test name
Test status
Simulation time 304428637152 ps
CPU time 98.7 seconds
Started Jul 12 05:40:24 PM PDT 24
Finished Jul 12 05:42:04 PM PDT 24
Peak memory 183072 kb
Host smart-980d551e-7d5b-40c0-8aab-5d235cb6d2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938879773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.938879773
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3587327652
Short name T267
Test name
Test status
Simulation time 26093789813 ps
CPU time 62.88 seconds
Started Jul 12 05:40:24 PM PDT 24
Finished Jul 12 05:41:29 PM PDT 24
Peak memory 194572 kb
Host smart-06e3220c-9f46-45e2-bd97-b3adedee3c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587327652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3587327652
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.118819644
Short name T178
Test name
Test status
Simulation time 1456621776866 ps
CPU time 3965.59 seconds
Started Jul 12 05:40:28 PM PDT 24
Finished Jul 12 06:46:34 PM PDT 24
Peak memory 197340 kb
Host smart-ddf7b5f1-bf2c-4290-aaa8-3cdfd181fca0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118819644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
118819644
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3300016551
Short name T230
Test name
Test status
Simulation time 206637606980 ps
CPU time 337.4 seconds
Started Jul 12 05:40:33 PM PDT 24
Finished Jul 12 05:46:11 PM PDT 24
Peak memory 183088 kb
Host smart-81fc2c9d-3688-4404-85ba-bbb067416d06
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300016551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3300016551
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.399179748
Short name T353
Test name
Test status
Simulation time 642596818455 ps
CPU time 261.27 seconds
Started Jul 12 05:40:27 PM PDT 24
Finished Jul 12 05:44:49 PM PDT 24
Peak memory 183108 kb
Host smart-8ed03aa2-ae31-4187-b24f-29ad500ea880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399179748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.399179748
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1041693264
Short name T8
Test name
Test status
Simulation time 129369897570 ps
CPU time 86.64 seconds
Started Jul 12 05:40:36 PM PDT 24
Finished Jul 12 05:42:03 PM PDT 24
Peak memory 183104 kb
Host smart-706555a5-8589-4f5c-abda-233a179b8c80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041693264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1041693264
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.714507272
Short name T328
Test name
Test status
Simulation time 66027890371 ps
CPU time 96.45 seconds
Started Jul 12 05:40:35 PM PDT 24
Finished Jul 12 05:42:13 PM PDT 24
Peak memory 191228 kb
Host smart-55e6fe11-3ce8-40f3-a3da-fabc3a1a2f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714507272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.714507272
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1796308526
Short name T167
Test name
Test status
Simulation time 23513317384 ps
CPU time 18.8 seconds
Started Jul 12 05:40:26 PM PDT 24
Finished Jul 12 05:40:46 PM PDT 24
Peak memory 183056 kb
Host smart-b28ea43b-524c-4bc9-938f-ac6f1ab0bc9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796308526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1796308526
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3199058896
Short name T346
Test name
Test status
Simulation time 93665173375 ps
CPU time 125.08 seconds
Started Jul 12 05:40:27 PM PDT 24
Finished Jul 12 05:42:32 PM PDT 24
Peak memory 183096 kb
Host smart-d577eca1-6756-496c-a6eb-546dbe9933d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199058896 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3199058896
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.1957279350
Short name T371
Test name
Test status
Simulation time 61815685 ps
CPU time 0.52 seconds
Started Jul 12 05:40:29 PM PDT 24
Finished Jul 12 05:40:30 PM PDT 24
Peak memory 182860 kb
Host smart-91dd9d0a-a560-425d-8629-6d079fa48c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957279350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.1957279350
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2609080900
Short name T118
Test name
Test status
Simulation time 366974953022 ps
CPU time 749.8 seconds
Started Jul 12 05:40:26 PM PDT 24
Finished Jul 12 05:52:57 PM PDT 24
Peak memory 195784 kb
Host smart-7234df55-e019-4ef0-adec-9cce2a83a222
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609080900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2609080900
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2315507795
Short name T23
Test name
Test status
Simulation time 302795896476 ps
CPU time 95.54 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 05:42:10 PM PDT 24
Peak memory 183084 kb
Host smart-415a9823-c527-4a67-aff9-f92404e60e2b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315507795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2315507795
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1558326389
Short name T416
Test name
Test status
Simulation time 90254657955 ps
CPU time 129.77 seconds
Started Jul 12 05:40:32 PM PDT 24
Finished Jul 12 05:42:42 PM PDT 24
Peak memory 183012 kb
Host smart-b7932e07-c582-428c-a0ac-a011eb6befdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558326389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1558326389
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1514412700
Short name T179
Test name
Test status
Simulation time 49040605508 ps
CPU time 111.32 seconds
Started Jul 12 05:40:32 PM PDT 24
Finished Jul 12 05:42:24 PM PDT 24
Peak memory 191176 kb
Host smart-85cf6750-12b6-4641-a57b-5d99adc2ba74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514412700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1514412700
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2414485919
Short name T390
Test name
Test status
Simulation time 44359815536 ps
CPU time 373.45 seconds
Started Jul 12 05:40:31 PM PDT 24
Finished Jul 12 05:46:45 PM PDT 24
Peak memory 182724 kb
Host smart-18de71bb-2b9d-4f04-a300-acf5e6963506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414485919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2414485919
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1077378672
Short name T387
Test name
Test status
Simulation time 131323674397 ps
CPU time 211 seconds
Started Jul 12 05:40:31 PM PDT 24
Finished Jul 12 05:44:02 PM PDT 24
Peak memory 182968 kb
Host smart-6c20a304-c087-481a-a343-1ec6c267bf35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077378672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1077378672
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1982522728
Short name T356
Test name
Test status
Simulation time 101100252909 ps
CPU time 134.13 seconds
Started Jul 12 05:40:33 PM PDT 24
Finished Jul 12 05:42:48 PM PDT 24
Peak memory 183020 kb
Host smart-ac3f48c5-be5b-4df2-b6cd-e1f5ec5762fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982522728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1982522728
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.2162379026
Short name T335
Test name
Test status
Simulation time 102422619742 ps
CPU time 91.69 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 05:42:06 PM PDT 24
Peak memory 183112 kb
Host smart-d013ff3f-d534-4a53-bf6d-d6bcd4bb1d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162379026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.2162379026
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1397545172
Short name T424
Test name
Test status
Simulation time 1454485709 ps
CPU time 0.87 seconds
Started Jul 12 05:40:33 PM PDT 24
Finished Jul 12 05:40:34 PM PDT 24
Peak memory 182872 kb
Host smart-88342d31-3c5a-44d8-b747-2f921f8334cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397545172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1397545172
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3644926199
Short name T293
Test name
Test status
Simulation time 270710703356 ps
CPU time 1229.19 seconds
Started Jul 12 05:40:26 PM PDT 24
Finished Jul 12 06:00:56 PM PDT 24
Peak memory 195224 kb
Host smart-16d2f0b6-6ee2-471f-b196-cce8d39a579c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644926199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3644926199
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.568604616
Short name T261
Test name
Test status
Simulation time 3492573995151 ps
CPU time 1952.97 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 06:13:08 PM PDT 24
Peak memory 183044 kb
Host smart-4729f7da-a562-43a9-8ad4-4f22143d75b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568604616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.568604616
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.3901508052
Short name T342
Test name
Test status
Simulation time 84780711766 ps
CPU time 121.92 seconds
Started Jul 12 05:40:28 PM PDT 24
Finished Jul 12 05:42:30 PM PDT 24
Peak memory 183328 kb
Host smart-cc276b06-d2ff-4c00-a6e0-6967a4231e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901508052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.3901508052
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1575227022
Short name T318
Test name
Test status
Simulation time 97319563836 ps
CPU time 112.72 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 05:42:28 PM PDT 24
Peak memory 191320 kb
Host smart-3f2d2480-65a8-4cef-9f77-e3ea5456ce79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575227022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1575227022
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.914012690
Short name T59
Test name
Test status
Simulation time 439278722061 ps
CPU time 162.84 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 05:43:18 PM PDT 24
Peak memory 191272 kb
Host smart-03ac2a15-82fb-4025-92f4-8436c57be33e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914012690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
914012690
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.491689084
Short name T39
Test name
Test status
Simulation time 112354193452 ps
CPU time 1187.69 seconds
Started Jul 12 05:40:33 PM PDT 24
Finished Jul 12 06:00:21 PM PDT 24
Peak memory 213680 kb
Host smart-56161361-aae6-4ce1-870b-ab2e3ea8e598
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491689084 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.491689084
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4113074674
Short name T96
Test name
Test status
Simulation time 141974289572 ps
CPU time 220.45 seconds
Started Jul 12 05:39:48 PM PDT 24
Finished Jul 12 05:43:29 PM PDT 24
Peak memory 183036 kb
Host smart-d6559891-d82c-4a8a-b394-241a567dcfa9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113074674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.4113074674
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.4223929778
Short name T407
Test name
Test status
Simulation time 182581028301 ps
CPU time 62.59 seconds
Started Jul 12 05:39:48 PM PDT 24
Finished Jul 12 05:40:52 PM PDT 24
Peak memory 183132 kb
Host smart-eb8091ec-7753-4e09-93c1-ad0a425f2008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223929778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.4223929778
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.2454164695
Short name T239
Test name
Test status
Simulation time 37234877158 ps
CPU time 150.34 seconds
Started Jul 12 05:39:45 PM PDT 24
Finished Jul 12 05:42:17 PM PDT 24
Peak memory 182984 kb
Host smart-eb8e06d5-ca78-4c73-b716-d6ed9dbf4f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454164695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.2454164695
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.3113693462
Short name T137
Test name
Test status
Simulation time 61968123363 ps
CPU time 197.33 seconds
Started Jul 12 05:39:47 PM PDT 24
Finished Jul 12 05:43:06 PM PDT 24
Peak memory 191320 kb
Host smart-33b7a0e7-d390-44f9-bcb7-f55ba943b9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113693462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.3113693462
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1091009202
Short name T45
Test name
Test status
Simulation time 290121381994 ps
CPU time 189.06 seconds
Started Jul 12 05:40:33 PM PDT 24
Finished Jul 12 05:43:43 PM PDT 24
Peak memory 191296 kb
Host smart-15b5ae36-bd26-43bb-b0e5-479a8b142053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091009202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1091009202
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1650690385
Short name T231
Test name
Test status
Simulation time 680107103703 ps
CPU time 624.71 seconds
Started Jul 12 05:40:27 PM PDT 24
Finished Jul 12 05:50:53 PM PDT 24
Peak memory 191236 kb
Host smart-3d3a634a-b5d0-4711-8f52-db211cc8515a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650690385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1650690385
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.3617937218
Short name T24
Test name
Test status
Simulation time 43882730941 ps
CPU time 67 seconds
Started Jul 12 05:40:37 PM PDT 24
Finished Jul 12 05:41:45 PM PDT 24
Peak memory 183316 kb
Host smart-319355f1-1fcf-48ab-8791-53982b2a78d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617937218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.3617937218
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1866735451
Short name T394
Test name
Test status
Simulation time 122044538166 ps
CPU time 524.93 seconds
Started Jul 12 05:40:36 PM PDT 24
Finished Jul 12 05:49:22 PM PDT 24
Peak memory 183100 kb
Host smart-1cfecabc-484b-44c6-9f92-0ccde28d4da1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866735451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1866735451
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.3721789501
Short name T330
Test name
Test status
Simulation time 916541850100 ps
CPU time 877.8 seconds
Started Jul 12 05:40:36 PM PDT 24
Finished Jul 12 05:55:15 PM PDT 24
Peak memory 193372 kb
Host smart-c2cf334a-28ec-4a36-b7af-9e5210900b32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721789501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.3721789501
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.117975113
Short name T382
Test name
Test status
Simulation time 105518886794 ps
CPU time 185.37 seconds
Started Jul 12 05:39:46 PM PDT 24
Finished Jul 12 05:42:52 PM PDT 24
Peak memory 183080 kb
Host smart-3b81bd96-a056-45b8-813f-a83d9a63752c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117975113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.rv_timer_cfg_update_on_fly.117975113
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_random.2542757963
Short name T103
Test name
Test status
Simulation time 468687218562 ps
CPU time 246.59 seconds
Started Jul 12 05:39:51 PM PDT 24
Finished Jul 12 05:43:58 PM PDT 24
Peak memory 191168 kb
Host smart-45941e58-ed34-4028-957a-3a1479b47126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542757963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2542757963
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.125078493
Short name T351
Test name
Test status
Simulation time 291296872 ps
CPU time 0.68 seconds
Started Jul 12 05:39:51 PM PDT 24
Finished Jul 12 05:39:52 PM PDT 24
Peak memory 182960 kb
Host smart-c7cc5e96-83e6-44da-bd37-8ad37d5590f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125078493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.125078493
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2468373508
Short name T428
Test name
Test status
Simulation time 1067348553345 ps
CPU time 1054.64 seconds
Started Jul 12 05:39:46 PM PDT 24
Finished Jul 12 05:57:22 PM PDT 24
Peak memory 196028 kb
Host smart-ccd4db30-05dc-4dad-b039-e17f1e06bc0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468373508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2468373508
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/61.rv_timer_random.2110737466
Short name T289
Test name
Test status
Simulation time 63860580645 ps
CPU time 43.36 seconds
Started Jul 12 05:40:36 PM PDT 24
Finished Jul 12 05:41:20 PM PDT 24
Peak memory 182964 kb
Host smart-8a3bfd88-478c-4a38-bbf6-0e5a0cb712de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110737466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2110737466
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.30221649
Short name T252
Test name
Test status
Simulation time 444400322999 ps
CPU time 2537.75 seconds
Started Jul 12 05:40:36 PM PDT 24
Finished Jul 12 06:22:55 PM PDT 24
Peak memory 191296 kb
Host smart-e03d9fb7-6f52-497a-96d7-6fbec8b6a521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30221649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.30221649
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.3428690264
Short name T49
Test name
Test status
Simulation time 299773981667 ps
CPU time 354.72 seconds
Started Jul 12 05:40:36 PM PDT 24
Finished Jul 12 05:46:32 PM PDT 24
Peak memory 191308 kb
Host smart-50734f03-b6dc-439c-9475-a761f26631ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428690264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.3428690264
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1467180227
Short name T282
Test name
Test status
Simulation time 218561867762 ps
CPU time 100.67 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 05:42:16 PM PDT 24
Peak memory 191132 kb
Host smart-8e3e8620-8bc1-4756-ad94-028453f0fd6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467180227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1467180227
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.4204247340
Short name T441
Test name
Test status
Simulation time 246366900890 ps
CPU time 750.52 seconds
Started Jul 12 05:40:33 PM PDT 24
Finished Jul 12 05:53:05 PM PDT 24
Peak memory 191292 kb
Host smart-e5279535-b200-4289-a6fa-f1c0c9f8c5b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204247340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.4204247340
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2730541853
Short name T183
Test name
Test status
Simulation time 519116352593 ps
CPU time 397.96 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 05:47:13 PM PDT 24
Peak memory 191284 kb
Host smart-6a1085ec-45ab-4b04-a2f5-6dfd2afde672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730541853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2730541853
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2885303372
Short name T288
Test name
Test status
Simulation time 3108505750150 ps
CPU time 1726.97 seconds
Started Jul 12 05:39:50 PM PDT 24
Finished Jul 12 06:08:38 PM PDT 24
Peak memory 183008 kb
Host smart-cfec6efe-7df7-4d33-8c24-4413b2a2e870
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885303372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2885303372
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.616179780
Short name T352
Test name
Test status
Simulation time 465872754950 ps
CPU time 185.77 seconds
Started Jul 12 05:39:47 PM PDT 24
Finished Jul 12 05:42:54 PM PDT 24
Peak memory 183088 kb
Host smart-dabe7639-557e-4fee-ac91-ed3ff8f2f6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616179780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.616179780
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3646217802
Short name T79
Test name
Test status
Simulation time 41796995567 ps
CPU time 44.56 seconds
Started Jul 12 05:39:51 PM PDT 24
Finished Jul 12 05:40:36 PM PDT 24
Peak memory 183104 kb
Host smart-78406f44-77e1-4b58-a474-f816bc39197a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646217802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3646217802
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2935728846
Short name T378
Test name
Test status
Simulation time 63394258 ps
CPU time 0.6 seconds
Started Jul 12 05:39:51 PM PDT 24
Finished Jul 12 05:39:52 PM PDT 24
Peak memory 182960 kb
Host smart-ba64a7d0-f8e1-451f-aee6-f2f47077dbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935728846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2935728846
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2998754507
Short name T3
Test name
Test status
Simulation time 899725123458 ps
CPU time 565.73 seconds
Started Jul 12 05:39:47 PM PDT 24
Finished Jul 12 05:49:14 PM PDT 24
Peak memory 191400 kb
Host smart-2568d23e-dcb9-4458-82b6-84e840535651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998754507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2998754507
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2129982814
Short name T13
Test name
Test status
Simulation time 40509020029 ps
CPU time 353.88 seconds
Started Jul 12 05:39:49 PM PDT 24
Finished Jul 12 05:45:44 PM PDT 24
Peak memory 207004 kb
Host smart-1e332538-4543-4ec1-a0eb-d5a27d0fb1fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129982814 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.2129982814
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2782923055
Short name T234
Test name
Test status
Simulation time 280390350950 ps
CPU time 225.85 seconds
Started Jul 12 05:40:34 PM PDT 24
Finished Jul 12 05:44:21 PM PDT 24
Peak memory 191304 kb
Host smart-3e389a78-d3b1-4755-8303-ce15e26d8046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782923055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2782923055
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.29359490
Short name T195
Test name
Test status
Simulation time 103005316826 ps
CPU time 154.94 seconds
Started Jul 12 05:40:36 PM PDT 24
Finished Jul 12 05:43:12 PM PDT 24
Peak memory 191516 kb
Host smart-e2a6f7e1-939f-4b38-a82c-3dd9d59ef016
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29359490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.29359490
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2533878242
Short name T128
Test name
Test status
Simulation time 159372898463 ps
CPU time 334.18 seconds
Started Jul 12 05:40:33 PM PDT 24
Finished Jul 12 05:46:08 PM PDT 24
Peak memory 194144 kb
Host smart-b4fc07f9-dbf3-4271-8250-4bcd71210a63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533878242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2533878242
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.3642764049
Short name T27
Test name
Test status
Simulation time 80789371024 ps
CPU time 116.35 seconds
Started Jul 12 05:40:42 PM PDT 24
Finished Jul 12 05:42:39 PM PDT 24
Peak memory 191196 kb
Host smart-f435fce0-85ae-4a3c-8bbf-c551e1008067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642764049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.3642764049
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3209797436
Short name T50
Test name
Test status
Simulation time 201462178852 ps
CPU time 88.25 seconds
Started Jul 12 05:40:43 PM PDT 24
Finished Jul 12 05:42:12 PM PDT 24
Peak memory 183316 kb
Host smart-d42eaee4-58e2-4ced-a7ae-fe42aa94efdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209797436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3209797436
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.3128340688
Short name T159
Test name
Test status
Simulation time 920536618722 ps
CPU time 369.99 seconds
Started Jul 12 05:40:43 PM PDT 24
Finished Jul 12 05:46:54 PM PDT 24
Peak memory 191304 kb
Host smart-00474d89-9790-4fff-9236-f95fc2775ba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128340688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.3128340688
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.2056422635
Short name T205
Test name
Test status
Simulation time 276591954615 ps
CPU time 668.92 seconds
Started Jul 12 05:40:43 PM PDT 24
Finished Jul 12 05:51:52 PM PDT 24
Peak memory 191292 kb
Host smart-4b9ae0d9-8f6e-4134-aa32-12d1b079846e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056422635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.2056422635
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3407701541
Short name T232
Test name
Test status
Simulation time 235387245090 ps
CPU time 279.65 seconds
Started Jul 12 05:40:43 PM PDT 24
Finished Jul 12 05:45:23 PM PDT 24
Peak memory 191304 kb
Host smart-875b1d8b-836a-42ce-981b-605212b54037
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407701541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3407701541
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.747159991
Short name T433
Test name
Test status
Simulation time 139441476942 ps
CPU time 1443.34 seconds
Started Jul 12 05:40:41 PM PDT 24
Finished Jul 12 06:04:45 PM PDT 24
Peak memory 191160 kb
Host smart-e2760487-05fc-4607-b2e8-617e97fab90e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747159991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.747159991
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.505168778
Short name T121
Test name
Test status
Simulation time 73770347187 ps
CPU time 97.78 seconds
Started Jul 12 05:40:49 PM PDT 24
Finished Jul 12 05:42:28 PM PDT 24
Peak memory 191236 kb
Host smart-40e962b6-7f16-442e-b045-2b71e118edc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505168778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.505168778
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.236815565
Short name T2
Test name
Test status
Simulation time 270229182090 ps
CPU time 326.06 seconds
Started Jul 12 05:39:48 PM PDT 24
Finished Jul 12 05:45:16 PM PDT 24
Peak memory 183056 kb
Host smart-b9ebd0ed-70aa-46ee-99e9-5f4f1dddf566
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236815565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.rv_timer_cfg_update_on_fly.236815565
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2066014618
Short name T354
Test name
Test status
Simulation time 69730581724 ps
CPU time 111.47 seconds
Started Jul 12 05:39:51 PM PDT 24
Finished Jul 12 05:41:43 PM PDT 24
Peak memory 182988 kb
Host smart-69cb2cb5-e61e-4c2a-84ae-30c24ba1c847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066014618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2066014618
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2290351249
Short name T111
Test name
Test status
Simulation time 229112916479 ps
CPU time 351.77 seconds
Started Jul 12 05:39:46 PM PDT 24
Finished Jul 12 05:45:39 PM PDT 24
Peak memory 191308 kb
Host smart-7e0f6bb3-f9ed-4d06-9817-f801fd539a31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290351249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2290351249
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.465739463
Short name T367
Test name
Test status
Simulation time 477625599 ps
CPU time 0.72 seconds
Started Jul 12 05:39:47 PM PDT 24
Finished Jul 12 05:39:50 PM PDT 24
Peak memory 191544 kb
Host smart-cd429b63-65c7-4052-90a8-1bd7a8d2a507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465739463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.465739463
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3886855062
Short name T171
Test name
Test status
Simulation time 271649719581 ps
CPU time 435.19 seconds
Started Jul 12 05:39:46 PM PDT 24
Finished Jul 12 05:47:02 PM PDT 24
Peak memory 191292 kb
Host smart-39092eff-2064-42d9-ab76-0e022a449205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886855062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3886855062
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.3651769761
Short name T84
Test name
Test status
Simulation time 179245576524 ps
CPU time 165.42 seconds
Started Jul 12 05:40:41 PM PDT 24
Finished Jul 12 05:43:27 PM PDT 24
Peak memory 183092 kb
Host smart-9758c4c9-76af-4299-bb68-9fd6b6c423b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651769761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.3651769761
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1560628853
Short name T265
Test name
Test status
Simulation time 206877632294 ps
CPU time 210.02 seconds
Started Jul 12 05:40:42 PM PDT 24
Finished Jul 12 05:44:12 PM PDT 24
Peak memory 191304 kb
Host smart-e9c6c0ca-ad92-4c56-8ea5-0aba570b1b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560628853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1560628853
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.2522668212
Short name T138
Test name
Test status
Simulation time 104430754456 ps
CPU time 754.24 seconds
Started Jul 12 05:40:41 PM PDT 24
Finished Jul 12 05:53:16 PM PDT 24
Peak memory 191296 kb
Host smart-61832cf3-2c7a-4567-9efc-160529f30cdf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522668212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2522668212
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3775795263
Short name T196
Test name
Test status
Simulation time 100834599855 ps
CPU time 608.8 seconds
Started Jul 12 05:40:42 PM PDT 24
Finished Jul 12 05:50:51 PM PDT 24
Peak memory 191284 kb
Host smart-5026ce72-ec4c-4c63-b065-2665a1d9a1af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775795263 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3775795263
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.832959559
Short name T210
Test name
Test status
Simulation time 1420639639651 ps
CPU time 324.93 seconds
Started Jul 12 05:40:49 PM PDT 24
Finished Jul 12 05:46:14 PM PDT 24
Peak memory 191244 kb
Host smart-6f4f72c6-c15e-4eb0-ad5c-b2d777f7f05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832959559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.832959559
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.1873103609
Short name T311
Test name
Test status
Simulation time 333998585031 ps
CPU time 173.86 seconds
Started Jul 12 05:40:41 PM PDT 24
Finished Jul 12 05:43:35 PM PDT 24
Peak memory 191412 kb
Host smart-2685a0b9-d487-4a3c-bfd4-cf4f51cc225c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873103609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.1873103609
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.1013421644
Short name T285
Test name
Test status
Simulation time 1103766560787 ps
CPU time 521.87 seconds
Started Jul 12 05:40:42 PM PDT 24
Finished Jul 12 05:49:25 PM PDT 24
Peak memory 191168 kb
Host smart-b5354e91-8256-4148-8671-72450c4049d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013421644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.1013421644
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2593215027
Short name T243
Test name
Test status
Simulation time 31933916280 ps
CPU time 47.96 seconds
Started Jul 12 05:40:48 PM PDT 24
Finished Jul 12 05:41:37 PM PDT 24
Peak memory 191248 kb
Host smart-eef11d6f-fdda-4f8d-8ebc-05990e11427d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593215027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2593215027
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1452295144
Short name T325
Test name
Test status
Simulation time 6906375199 ps
CPU time 6.59 seconds
Started Jul 12 05:39:52 PM PDT 24
Finished Jul 12 05:39:59 PM PDT 24
Peak memory 182968 kb
Host smart-905ccf57-fd35-46a0-a0cf-b1e16f7d9136
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452295144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1452295144
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.4169448831
Short name T372
Test name
Test status
Simulation time 688672225205 ps
CPU time 282.89 seconds
Started Jul 12 05:39:46 PM PDT 24
Finished Jul 12 05:44:30 PM PDT 24
Peak memory 183120 kb
Host smart-19daf3d0-49d3-4590-9ce7-c4ebc4e00e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169448831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4169448831
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2979637235
Short name T221
Test name
Test status
Simulation time 489023223269 ps
CPU time 581.12 seconds
Started Jul 12 05:39:47 PM PDT 24
Finished Jul 12 05:49:29 PM PDT 24
Peak memory 191272 kb
Host smart-1e2a2249-bd0d-4fb4-a505-6ad55d7de8b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979637235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2979637235
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1342758846
Short name T398
Test name
Test status
Simulation time 256495479 ps
CPU time 0.63 seconds
Started Jul 12 05:39:46 PM PDT 24
Finished Jul 12 05:39:47 PM PDT 24
Peak memory 182976 kb
Host smart-87c3c545-a669-48e1-84c3-a692ad7ef275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342758846 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1342758846
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.2560498835
Short name T409
Test name
Test status
Simulation time 357799233490 ps
CPU time 169.1 seconds
Started Jul 12 05:39:59 PM PDT 24
Finished Jul 12 05:42:49 PM PDT 24
Peak memory 194196 kb
Host smart-52e43d90-be79-481e-8eef-6c64e77cb982
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560498835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
2560498835
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.2023460107
Short name T41
Test name
Test status
Simulation time 90700148100 ps
CPU time 668.2 seconds
Started Jul 12 05:39:56 PM PDT 24
Finished Jul 12 05:51:05 PM PDT 24
Peak memory 214180 kb
Host smart-66258f07-2117-4957-af27-9ca818515a3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023460107 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.2023460107
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.159504907
Short name T415
Test name
Test status
Simulation time 358676461178 ps
CPU time 229.06 seconds
Started Jul 12 05:40:42 PM PDT 24
Finished Jul 12 05:44:31 PM PDT 24
Peak memory 191288 kb
Host smart-a7df7efc-8948-4412-abac-ad921a05d69f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159504907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.159504907
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.538766674
Short name T141
Test name
Test status
Simulation time 41021528065 ps
CPU time 61.35 seconds
Started Jul 12 05:40:42 PM PDT 24
Finished Jul 12 05:41:44 PM PDT 24
Peak memory 191288 kb
Host smart-4d4c8f66-7a14-4c6e-b65e-b8f3525f2804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538766674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.538766674
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.69265533
Short name T445
Test name
Test status
Simulation time 31286149534 ps
CPU time 11.12 seconds
Started Jul 12 05:40:44 PM PDT 24
Finished Jul 12 05:40:55 PM PDT 24
Peak memory 183008 kb
Host smart-d514c714-f7f2-40ac-a7f1-f729c37b87d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69265533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.69265533
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.845315473
Short name T379
Test name
Test status
Simulation time 28762401274 ps
CPU time 46.35 seconds
Started Jul 12 05:40:48 PM PDT 24
Finished Jul 12 05:41:35 PM PDT 24
Peak memory 191180 kb
Host smart-22ff66f3-eb44-4f02-b589-ebb6b0aae316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845315473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.845315473
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.4294703900
Short name T417
Test name
Test status
Simulation time 7593439445 ps
CPU time 6.95 seconds
Started Jul 12 05:40:50 PM PDT 24
Finished Jul 12 05:40:57 PM PDT 24
Peak memory 183088 kb
Host smart-ae58774a-73bb-41f1-81e8-1214c9326313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294703900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.4294703900
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.3617944234
Short name T147
Test name
Test status
Simulation time 178149341205 ps
CPU time 513.73 seconds
Started Jul 12 05:40:48 PM PDT 24
Finished Jul 12 05:49:22 PM PDT 24
Peak memory 191508 kb
Host smart-81f9ebc6-be30-4b81-a9ef-fcfb81bba5ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617944234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.3617944234
Directory /workspace/99.rv_timer_random/latest
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