Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.36 98.73 100.00 100.00 100.00 99.89


Total test records in report: 570
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T102 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1507798082 Jul 13 04:39:34 PM PDT 24 Jul 13 04:39:36 PM PDT 24 80700471 ps
T509 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2450459379 Jul 13 04:39:16 PM PDT 24 Jul 13 04:39:20 PM PDT 24 94761448 ps
T510 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3092408346 Jul 13 04:39:04 PM PDT 24 Jul 13 04:39:06 PM PDT 24 14976243 ps
T511 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1038888139 Jul 13 04:38:53 PM PDT 24 Jul 13 04:38:56 PM PDT 24 30539367 ps
T512 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1080963149 Jul 13 04:38:54 PM PDT 24 Jul 13 04:38:57 PM PDT 24 39500402 ps
T513 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1102107698 Jul 13 04:39:10 PM PDT 24 Jul 13 04:39:13 PM PDT 24 981830683 ps
T514 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2674280680 Jul 13 04:39:35 PM PDT 24 Jul 13 04:39:37 PM PDT 24 42105033 ps
T515 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1261248475 Jul 13 04:39:15 PM PDT 24 Jul 13 04:39:19 PM PDT 24 31913737 ps
T88 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.318409376 Jul 13 04:39:09 PM PDT 24 Jul 13 04:39:10 PM PDT 24 11240669 ps
T516 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3740164844 Jul 13 04:39:02 PM PDT 24 Jul 13 04:39:04 PM PDT 24 210153099 ps
T517 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1308621887 Jul 13 04:39:32 PM PDT 24 Jul 13 04:39:34 PM PDT 24 18035278 ps
T518 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2369043056 Jul 13 04:39:23 PM PDT 24 Jul 13 04:39:25 PM PDT 24 140458089 ps
T519 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3854315955 Jul 13 04:39:12 PM PDT 24 Jul 13 04:39:13 PM PDT 24 123515650 ps
T520 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3955030434 Jul 13 04:39:05 PM PDT 24 Jul 13 04:39:07 PM PDT 24 16079817 ps
T521 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3103415775 Jul 13 04:39:27 PM PDT 24 Jul 13 04:39:32 PM PDT 24 13095925 ps
T522 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.431230304 Jul 13 04:38:56 PM PDT 24 Jul 13 04:38:58 PM PDT 24 13654652 ps
T89 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.488232866 Jul 13 04:39:31 PM PDT 24 Jul 13 04:39:34 PM PDT 24 30526408 ps
T90 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3104754591 Jul 13 04:39:12 PM PDT 24 Jul 13 04:39:13 PM PDT 24 17333356 ps
T523 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3493505135 Jul 13 04:39:36 PM PDT 24 Jul 13 04:39:38 PM PDT 24 131236464 ps
T91 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3905071063 Jul 13 04:39:15 PM PDT 24 Jul 13 04:39:19 PM PDT 24 53500101 ps
T524 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.834453683 Jul 13 04:38:55 PM PDT 24 Jul 13 04:38:58 PM PDT 24 35083554 ps
T525 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3383530919 Jul 13 04:38:53 PM PDT 24 Jul 13 04:38:55 PM PDT 24 50575578 ps
T526 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1078326087 Jul 13 04:39:15 PM PDT 24 Jul 13 04:39:19 PM PDT 24 50503506 ps
T93 /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1040178947 Jul 13 04:39:18 PM PDT 24 Jul 13 04:39:32 PM PDT 24 12310100 ps
T527 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1680168411 Jul 13 04:39:34 PM PDT 24 Jul 13 04:39:38 PM PDT 24 1838019940 ps
T528 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.4287355324 Jul 13 04:39:14 PM PDT 24 Jul 13 04:39:17 PM PDT 24 13118331 ps
T529 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.952953193 Jul 13 04:39:20 PM PDT 24 Jul 13 04:39:22 PM PDT 24 16655760 ps
T530 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3211708881 Jul 13 04:39:07 PM PDT 24 Jul 13 04:39:09 PM PDT 24 107606623 ps
T531 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3585791493 Jul 13 04:39:13 PM PDT 24 Jul 13 04:39:16 PM PDT 24 25290412 ps
T532 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2820325481 Jul 13 04:39:12 PM PDT 24 Jul 13 04:39:14 PM PDT 24 39659417 ps
T533 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2704666873 Jul 13 04:39:38 PM PDT 24 Jul 13 04:39:40 PM PDT 24 88206763 ps
T94 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2918751176 Jul 13 04:39:12 PM PDT 24 Jul 13 04:39:14 PM PDT 24 58026398 ps
T534 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2043550091 Jul 13 04:39:11 PM PDT 24 Jul 13 04:39:12 PM PDT 24 86298912 ps
T535 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1837431829 Jul 13 04:39:14 PM PDT 24 Jul 13 04:39:16 PM PDT 24 68872437 ps
T536 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3632766697 Jul 13 04:39:06 PM PDT 24 Jul 13 04:39:07 PM PDT 24 19689938 ps
T537 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2073670973 Jul 13 04:39:09 PM PDT 24 Jul 13 04:39:11 PM PDT 24 429538973 ps
T538 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2947272068 Jul 13 04:39:03 PM PDT 24 Jul 13 04:39:05 PM PDT 24 195392596 ps
T539 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4057339541 Jul 13 04:39:15 PM PDT 24 Jul 13 04:39:18 PM PDT 24 27736706 ps
T540 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2633118084 Jul 13 04:39:23 PM PDT 24 Jul 13 04:39:25 PM PDT 24 76901815 ps
T541 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3999941693 Jul 13 04:39:30 PM PDT 24 Jul 13 04:39:35 PM PDT 24 424560404 ps
T542 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2199698876 Jul 13 04:39:21 PM PDT 24 Jul 13 04:39:23 PM PDT 24 11969158 ps
T543 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1155442162 Jul 13 04:39:03 PM PDT 24 Jul 13 04:39:05 PM PDT 24 50789384 ps
T544 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.867263872 Jul 13 04:39:19 PM PDT 24 Jul 13 04:39:22 PM PDT 24 135703150 ps
T545 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.767573839 Jul 13 04:39:15 PM PDT 24 Jul 13 04:39:19 PM PDT 24 629146449 ps
T546 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.506672909 Jul 13 04:39:32 PM PDT 24 Jul 13 04:39:34 PM PDT 24 17226703 ps
T95 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1853179351 Jul 13 04:39:10 PM PDT 24 Jul 13 04:39:11 PM PDT 24 28307986 ps
T547 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3205427232 Jul 13 04:39:25 PM PDT 24 Jul 13 04:39:28 PM PDT 24 16757439 ps
T548 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.713399753 Jul 13 04:39:21 PM PDT 24 Jul 13 04:39:23 PM PDT 24 36282720 ps
T549 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3611421724 Jul 13 04:38:56 PM PDT 24 Jul 13 04:39:04 PM PDT 24 229632691 ps
T550 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3127473679 Jul 13 04:38:58 PM PDT 24 Jul 13 04:39:00 PM PDT 24 33712702 ps
T551 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3662406649 Jul 13 04:38:58 PM PDT 24 Jul 13 04:39:00 PM PDT 24 28863672 ps
T552 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1113116999 Jul 13 04:39:19 PM PDT 24 Jul 13 04:39:22 PM PDT 24 41637133 ps
T553 /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3712095185 Jul 13 04:39:14 PM PDT 24 Jul 13 04:39:17 PM PDT 24 16782977 ps
T554 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3977497186 Jul 13 04:39:00 PM PDT 24 Jul 13 04:39:01 PM PDT 24 15786755 ps
T555 /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.150462164 Jul 13 04:39:25 PM PDT 24 Jul 13 04:39:27 PM PDT 24 16123758 ps
T556 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1532934421 Jul 13 04:38:52 PM PDT 24 Jul 13 04:38:54 PM PDT 24 12391644 ps
T557 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1163550853 Jul 13 04:39:13 PM PDT 24 Jul 13 04:39:15 PM PDT 24 20659864 ps
T558 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.333652067 Jul 13 04:39:13 PM PDT 24 Jul 13 04:39:15 PM PDT 24 39469615 ps
T559 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.928381271 Jul 13 04:39:13 PM PDT 24 Jul 13 04:39:15 PM PDT 24 40374395 ps
T560 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2584598882 Jul 13 04:39:18 PM PDT 24 Jul 13 04:39:21 PM PDT 24 14164011 ps
T561 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.656613892 Jul 13 04:39:13 PM PDT 24 Jul 13 04:39:15 PM PDT 24 15248289 ps
T562 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2959726479 Jul 13 04:39:04 PM PDT 24 Jul 13 04:39:06 PM PDT 24 12457454 ps
T563 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.165098602 Jul 13 04:39:13 PM PDT 24 Jul 13 04:39:17 PM PDT 24 120679271 ps
T564 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1425209676 Jul 13 04:39:14 PM PDT 24 Jul 13 04:39:17 PM PDT 24 88445307 ps
T565 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.68949867 Jul 13 04:39:15 PM PDT 24 Jul 13 04:39:17 PM PDT 24 12854912 ps
T566 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3826914994 Jul 13 04:39:15 PM PDT 24 Jul 13 04:39:22 PM PDT 24 41540135 ps
T567 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2120671636 Jul 13 04:39:16 PM PDT 24 Jul 13 04:39:20 PM PDT 24 20348449 ps
T568 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2734442274 Jul 13 04:39:03 PM PDT 24 Jul 13 04:39:06 PM PDT 24 956668447 ps
T569 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.519334439 Jul 13 04:39:33 PM PDT 24 Jul 13 04:39:35 PM PDT 24 13921976 ps
T570 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1549078084 Jul 13 04:39:14 PM PDT 24 Jul 13 04:39:16 PM PDT 24 14309190 ps

Test location /workspace/coverage/default/20.rv_timer_random.3912755421
Short name T4
Test name
Test status
Simulation time 137113735959 ps
CPU time 309.57 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:58:17 PM PDT 24
Peak memory 194584 kb
Host smart-1fa46a29-1a66-424d-a5c8-f75489493a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912755421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.3912755421
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.2953974077
Short name T34
Test name
Test status
Simulation time 1937035437622 ps
CPU time 920.87 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 06:08:46 PM PDT 24
Peak memory 191316 kb
Host smart-9b5f254d-e7cb-4963-a009-796a8b55d291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953974077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.2953974077
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.4045214203
Short name T35
Test name
Test status
Simulation time 99062264977 ps
CPU time 762.2 seconds
Started Jul 13 05:53:18 PM PDT 24
Finished Jul 13 06:06:01 PM PDT 24
Peak memory 208180 kb
Host smart-6de10c49-208d-4d7c-bbca-55c21dc1dd12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045214203 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.4045214203
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1599902037
Short name T135
Test name
Test status
Simulation time 1974152034766 ps
CPU time 1729.93 seconds
Started Jul 13 05:52:46 PM PDT 24
Finished Jul 13 06:21:37 PM PDT 24
Peak memory 191320 kb
Host smart-b25c95f6-cc1c-4080-aba9-15929477f83a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599902037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1599902037
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.1034022866
Short name T170
Test name
Test status
Simulation time 911070393679 ps
CPU time 2297.22 seconds
Started Jul 13 05:53:11 PM PDT 24
Finished Jul 13 06:31:29 PM PDT 24
Peak memory 191188 kb
Host smart-7d98aacc-3781-433c-a192-f6eb16095cc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034022866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.1034022866
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3259461637
Short name T14
Test name
Test status
Simulation time 294162339 ps
CPU time 0.77 seconds
Started Jul 13 05:52:39 PM PDT 24
Finished Jul 13 05:52:41 PM PDT 24
Peak memory 213380 kb
Host smart-6bc554a8-24e2-4f23-8c79-8c7f5ade0d64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259461637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3259461637
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3578032512
Short name T42
Test name
Test status
Simulation time 2588031719506 ps
CPU time 2017.48 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 06:26:56 PM PDT 24
Peak memory 196824 kb
Host smart-674b006a-40fe-4249-9955-400ba5d8bdd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578032512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3578032512
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.142388009
Short name T71
Test name
Test status
Simulation time 9322646447924 ps
CPU time 2566.58 seconds
Started Jul 13 05:52:53 PM PDT 24
Finished Jul 13 06:35:41 PM PDT 24
Peak memory 191300 kb
Host smart-35d80469-3b11-46ff-a235-8ea3a40aa5e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142388009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.142388009
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1513722689
Short name T220
Test name
Test status
Simulation time 2362018200248 ps
CPU time 2105.11 seconds
Started Jul 13 05:53:08 PM PDT 24
Finished Jul 13 06:28:14 PM PDT 24
Peak memory 191560 kb
Host smart-bb4b373c-464c-40d3-bb30-faf477edf3a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513722689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1513722689
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1083227609
Short name T50
Test name
Test status
Simulation time 179902934 ps
CPU time 0.6 seconds
Started Jul 13 04:39:10 PM PDT 24
Finished Jul 13 04:39:11 PM PDT 24
Peak memory 191684 kb
Host smart-74b98cd5-5351-4c56-a683-790473fbf23d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083227609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1083227609
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.934250963
Short name T72
Test name
Test status
Simulation time 9073488832018 ps
CPU time 2023.56 seconds
Started Jul 13 05:53:27 PM PDT 24
Finished Jul 13 06:27:11 PM PDT 24
Peak memory 191336 kb
Host smart-7f8a92f1-41fe-4119-8bef-eacb3ecf6fb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934250963 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all.
934250963
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.598627623
Short name T46
Test name
Test status
Simulation time 9874643736095 ps
CPU time 1794.88 seconds
Started Jul 13 05:53:12 PM PDT 24
Finished Jul 13 06:23:08 PM PDT 24
Peak memory 191324 kb
Host smart-bffcec87-9b94-4c2d-b151-dfc49c440a78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598627623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all.
598627623
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.2718724891
Short name T212
Test name
Test status
Simulation time 2567499298099 ps
CPU time 1660.87 seconds
Started Jul 13 05:53:13 PM PDT 24
Finished Jul 13 06:20:55 PM PDT 24
Peak memory 194608 kb
Host smart-8e350287-e8fa-4e93-9e59-afe972210e07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718724891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.2718724891
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2148476520
Short name T208
Test name
Test status
Simulation time 438134054386 ps
CPU time 1025.12 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 06:10:10 PM PDT 24
Peak memory 191212 kb
Host smart-8ff9123a-2d8d-4e25-828f-da90b79fef08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148476520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2148476520
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3034691823
Short name T29
Test name
Test status
Simulation time 287045515 ps
CPU time 1.33 seconds
Started Jul 13 04:39:01 PM PDT 24
Finished Jul 13 04:39:04 PM PDT 24
Peak memory 194708 kb
Host smart-3b9a2bb9-3103-4c7a-bed7-edd3af2fe83f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034691823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3034691823
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.979001788
Short name T175
Test name
Test status
Simulation time 626645229709 ps
CPU time 3567 seconds
Started Jul 13 05:52:55 PM PDT 24
Finished Jul 13 06:52:23 PM PDT 24
Peak memory 191304 kb
Host smart-2d03d211-e038-4f37-885a-f315ec3e1ea4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979001788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.979001788
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3304158563
Short name T113
Test name
Test status
Simulation time 1164719967893 ps
CPU time 2422.06 seconds
Started Jul 13 05:52:53 PM PDT 24
Finished Jul 13 06:33:17 PM PDT 24
Peak memory 191236 kb
Host smart-01ca292f-36b5-479c-9a29-1f2c6024e86c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304158563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3304158563
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/65.rv_timer_random.2700053935
Short name T128
Test name
Test status
Simulation time 167949261406 ps
CPU time 1557.99 seconds
Started Jul 13 05:53:37 PM PDT 24
Finished Jul 13 06:19:36 PM PDT 24
Peak memory 191300 kb
Host smart-2bee68d6-93ec-472e-a1ea-9584bb9318e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700053935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.2700053935
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.1992469052
Short name T161
Test name
Test status
Simulation time 1211599411698 ps
CPU time 531.18 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 06:01:57 PM PDT 24
Peak memory 196860 kb
Host smart-56615932-5ee6-4866-8ed9-10a912f619fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992469052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.1992469052
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3742521132
Short name T70
Test name
Test status
Simulation time 760013792307 ps
CPU time 1194.84 seconds
Started Jul 13 05:53:16 PM PDT 24
Finished Jul 13 06:13:11 PM PDT 24
Peak memory 191292 kb
Host smart-e2ea445e-c97e-4ce9-868c-a47ec9fff09d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742521132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3742521132
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1425674275
Short name T153
Test name
Test status
Simulation time 1521063280499 ps
CPU time 596.86 seconds
Started Jul 13 05:53:31 PM PDT 24
Finished Jul 13 06:03:28 PM PDT 24
Peak memory 191524 kb
Host smart-88ba64ea-ae35-4319-bc3f-24399e020ff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425674275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1425674275
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.3893424937
Short name T288
Test name
Test status
Simulation time 342308956656 ps
CPU time 842.28 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 06:07:25 PM PDT 24
Peak memory 191212 kb
Host smart-24d295ef-c7ec-4720-9129-769da570e9d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893424937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.3893424937
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.1874674580
Short name T155
Test name
Test status
Simulation time 2502412407174 ps
CPU time 1667.4 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 06:21:13 PM PDT 24
Peak memory 191212 kb
Host smart-93039081-4c1e-49ba-8052-853a23b4eb6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874674580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.1874674580
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/137.rv_timer_random.1190038147
Short name T243
Test name
Test status
Simulation time 151117897164 ps
CPU time 981.04 seconds
Started Jul 13 05:54:07 PM PDT 24
Finished Jul 13 06:10:29 PM PDT 24
Peak memory 191240 kb
Host smart-206bfd0e-d4c0-4731-91b5-bf670245dde7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190038147 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1190038147
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3804009093
Short name T227
Test name
Test status
Simulation time 277196339467 ps
CPU time 458.66 seconds
Started Jul 13 05:53:21 PM PDT 24
Finished Jul 13 06:01:00 PM PDT 24
Peak memory 191296 kb
Host smart-6f029e0d-78e7-46bf-aef7-adbec2ad5101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804009093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3804009093
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_random.707550992
Short name T263
Test name
Test status
Simulation time 287111145363 ps
CPU time 1194.7 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 06:13:20 PM PDT 24
Peak memory 191296 kb
Host smart-36ea98af-33e6-42a0-86ed-a56d37d54569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707550992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.707550992
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2942017836
Short name T240
Test name
Test status
Simulation time 1135745214562 ps
CPU time 2316.4 seconds
Started Jul 13 05:53:39 PM PDT 24
Finished Jul 13 06:32:18 PM PDT 24
Peak memory 191276 kb
Host smart-cc6f61a6-75b2-42f0-8542-b41c9f1c293d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942017836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2942017836
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.4102299600
Short name T166
Test name
Test status
Simulation time 211293461021 ps
CPU time 648.63 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 06:03:54 PM PDT 24
Peak memory 191264 kb
Host smart-f5258265-3647-41d7-a53b-f0f6ab52cf87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102299600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.4102299600
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3427197466
Short name T436
Test name
Test status
Simulation time 215262164496 ps
CPU time 1205.74 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:13:45 PM PDT 24
Peak memory 195604 kb
Host smart-92b3b26d-8d2d-4ab6-93c9-92f9bbe12aca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427197466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3427197466
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/69.rv_timer_random.2271657758
Short name T79
Test name
Test status
Simulation time 121234261562 ps
CPU time 566.25 seconds
Started Jul 13 05:53:40 PM PDT 24
Finished Jul 13 06:03:07 PM PDT 24
Peak memory 191528 kb
Host smart-2e4f3608-11ff-4442-9718-0817f6855bf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271657758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2271657758
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.2103528338
Short name T184
Test name
Test status
Simulation time 3763354493105 ps
CPU time 1185.76 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 06:12:52 PM PDT 24
Peak memory 190920 kb
Host smart-29bd8019-3419-49c1-a548-248d7ac14395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103528338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.2103528338
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/169.rv_timer_random.1771019260
Short name T225
Test name
Test status
Simulation time 209750682503 ps
CPU time 918.24 seconds
Started Jul 13 05:54:21 PM PDT 24
Finished Jul 13 06:09:39 PM PDT 24
Peak memory 191304 kb
Host smart-0274e1ea-b033-43b8-9f37-e1295aebffd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771019260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1771019260
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.2378294267
Short name T176
Test name
Test status
Simulation time 574349404053 ps
CPU time 274.61 seconds
Started Jul 13 05:54:20 PM PDT 24
Finished Jul 13 05:58:56 PM PDT 24
Peak memory 191340 kb
Host smart-beef7ab5-3c2f-4284-bb8e-f47ce0424376
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378294267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2378294267
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2823766611
Short name T274
Test name
Test status
Simulation time 280870373052 ps
CPU time 411.74 seconds
Started Jul 13 05:53:24 PM PDT 24
Finished Jul 13 06:00:17 PM PDT 24
Peak memory 191216 kb
Host smart-8a802a4f-c004-49cc-bf41-9e17482486c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823766611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2823766611
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_random.1440954654
Short name T247
Test name
Test status
Simulation time 277240553588 ps
CPU time 340.18 seconds
Started Jul 13 05:52:56 PM PDT 24
Finished Jul 13 05:58:37 PM PDT 24
Peak memory 191292 kb
Host smart-d9afdc15-1051-49cf-9507-e9effc435690
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440954654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1440954654
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3602681639
Short name T203
Test name
Test status
Simulation time 150177107040 ps
CPU time 206.08 seconds
Started Jul 13 05:53:39 PM PDT 24
Finished Jul 13 05:57:07 PM PDT 24
Peak memory 191300 kb
Host smart-6f4faaeb-0d16-4a55-a4b8-13766526c504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602681639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3602681639
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3587017135
Short name T253
Test name
Test status
Simulation time 118415859126 ps
CPU time 101.49 seconds
Started Jul 13 05:53:46 PM PDT 24
Finished Jul 13 05:55:28 PM PDT 24
Peak memory 191332 kb
Host smart-8de73d76-f604-425b-b680-d9db0f920d5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587017135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3587017135
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.879968437
Short name T10
Test name
Test status
Simulation time 78185303924 ps
CPU time 40.75 seconds
Started Jul 13 05:53:15 PM PDT 24
Finished Jul 13 05:53:57 PM PDT 24
Peak memory 191220 kb
Host smart-a5ef09e6-b173-40cd-8ec0-e177d63643dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879968437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.879968437
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2787700507
Short name T44
Test name
Test status
Simulation time 310102204146 ps
CPU time 285.94 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 05:58:45 PM PDT 24
Peak memory 191256 kb
Host smart-da32317f-f5fc-4369-aa73-1a3317bfadff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787700507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2787700507
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1906765613
Short name T199
Test name
Test status
Simulation time 282492831158 ps
CPU time 808.93 seconds
Started Jul 13 05:54:14 PM PDT 24
Finished Jul 13 06:07:43 PM PDT 24
Peak memory 191324 kb
Host smart-6202eeeb-f699-4195-a4b8-60a7c56aabd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906765613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1906765613
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.573839431
Short name T143
Test name
Test status
Simulation time 1374827163363 ps
CPU time 1558.94 seconds
Started Jul 13 05:54:48 PM PDT 24
Finished Jul 13 06:20:48 PM PDT 24
Peak memory 191332 kb
Host smart-fe78cbcf-71b4-400b-b022-480695b280fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573839431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.573839431
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.4198624288
Short name T116
Test name
Test status
Simulation time 758428309529 ps
CPU time 671.59 seconds
Started Jul 13 05:54:43 PM PDT 24
Finished Jul 13 06:05:55 PM PDT 24
Peak memory 191320 kb
Host smart-a91831ac-4c3c-4cee-b192-764a61eb1f7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198624288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.4198624288
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2266455394
Short name T215
Test name
Test status
Simulation time 271162162897 ps
CPU time 2571.76 seconds
Started Jul 13 05:53:11 PM PDT 24
Finished Jul 13 06:36:03 PM PDT 24
Peak memory 195744 kb
Host smart-9eb2ca71-b0a6-47dc-9d8d-14172cc474d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266455394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2266455394
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/51.rv_timer_random.845800133
Short name T159
Test name
Test status
Simulation time 156087516749 ps
CPU time 1840.05 seconds
Started Jul 13 05:53:31 PM PDT 24
Finished Jul 13 06:24:12 PM PDT 24
Peak memory 191268 kb
Host smart-6f6b000b-fe18-482c-b6ec-84e9db19faa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845800133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.845800133
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.998183400
Short name T110
Test name
Test status
Simulation time 1017341001866 ps
CPU time 198.01 seconds
Started Jul 13 05:53:37 PM PDT 24
Finished Jul 13 05:56:57 PM PDT 24
Peak memory 191296 kb
Host smart-b1d5b735-ad80-4c3d-9c93-b4ea906fb198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998183400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.998183400
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.1929743724
Short name T185
Test name
Test status
Simulation time 485397407787 ps
CPU time 280.77 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 05:57:45 PM PDT 24
Peak memory 191220 kb
Host smart-8b937247-3709-4f79-a661-2e60b14c7cd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929743724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1929743724
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2653130025
Short name T191
Test name
Test status
Simulation time 242203750634 ps
CPU time 210.72 seconds
Started Jul 13 05:53:53 PM PDT 24
Finished Jul 13 05:57:24 PM PDT 24
Peak memory 191220 kb
Host smart-7cc55787-6d39-4b9a-aca7-49de3bd949bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653130025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2653130025
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.3742816064
Short name T316
Test name
Test status
Simulation time 539561989478 ps
CPU time 254.53 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 05:58:14 PM PDT 24
Peak memory 191256 kb
Host smart-1db78666-2ef9-4c7d-8da8-baf2a9530383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742816064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.3742816064
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.2143830436
Short name T279
Test name
Test status
Simulation time 171324070510 ps
CPU time 278.56 seconds
Started Jul 13 05:54:22 PM PDT 24
Finished Jul 13 05:59:01 PM PDT 24
Peak memory 191328 kb
Host smart-22f305bd-6ece-4a68-9ea2-6670f3d1cbb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143830436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.2143830436
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.3694160524
Short name T312
Test name
Test status
Simulation time 1079928821880 ps
CPU time 340.55 seconds
Started Jul 13 05:53:12 PM PDT 24
Finished Jul 13 05:58:53 PM PDT 24
Peak memory 191324 kb
Host smart-925abf3c-1290-4da2-bd6e-68590761185a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694160524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3694160524
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.498733858
Short name T163
Test name
Test status
Simulation time 192562791915 ps
CPU time 553.68 seconds
Started Jul 13 05:53:37 PM PDT 24
Finished Jul 13 06:02:52 PM PDT 24
Peak memory 191288 kb
Host smart-ebf928e4-3941-4806-9419-6036587c2aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498733858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.498733858
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3316799948
Short name T134
Test name
Test status
Simulation time 102585448658 ps
CPU time 172.66 seconds
Started Jul 13 05:52:53 PM PDT 24
Finished Jul 13 05:55:47 PM PDT 24
Peak memory 183012 kb
Host smart-c7d38702-82d9-4772-be45-b9438a1c7c08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316799948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3316799948
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3862811738
Short name T100
Test name
Test status
Simulation time 93287510 ps
CPU time 0.74 seconds
Started Jul 13 04:39:02 PM PDT 24
Finished Jul 13 04:39:04 PM PDT 24
Peak memory 191544 kb
Host smart-5fab26bc-fc50-424d-b80a-586f27548a1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862811738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.3862811738
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.3654101959
Short name T236
Test name
Test status
Simulation time 272037221990 ps
CPU time 360.76 seconds
Started Jul 13 05:52:43 PM PDT 24
Finished Jul 13 05:58:44 PM PDT 24
Peak memory 195412 kb
Host smart-c40f98a0-14e1-487f-ba29-ee191c177516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654101959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
3654101959
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/102.rv_timer_random.715896790
Short name T260
Test name
Test status
Simulation time 198157920807 ps
CPU time 743.99 seconds
Started Jul 13 05:53:45 PM PDT 24
Finished Jul 13 06:06:09 PM PDT 24
Peak memory 191300 kb
Host smart-7c78d999-005c-4e0e-89a1-5bf1085e3617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715896790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.715896790
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.3092335137
Short name T20
Test name
Test status
Simulation time 368361624078 ps
CPU time 900.3 seconds
Started Jul 13 05:53:47 PM PDT 24
Finished Jul 13 06:08:48 PM PDT 24
Peak memory 191220 kb
Host smart-e07434bf-4607-4dfe-bc41-3bde345ef691
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092335137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.3092335137
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.4111961606
Short name T303
Test name
Test status
Simulation time 507116649144 ps
CPU time 2452.66 seconds
Started Jul 13 05:53:51 PM PDT 24
Finished Jul 13 06:34:44 PM PDT 24
Peak memory 191300 kb
Host smart-f22c53ae-0e03-4175-ba01-2fc93313fe85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111961606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.4111961606
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.2888087800
Short name T226
Test name
Test status
Simulation time 594419812773 ps
CPU time 291.16 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 05:58:51 PM PDT 24
Peak memory 191256 kb
Host smart-e20524eb-c8d9-444a-8e1c-98059470dc20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888087800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2888087800
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2484673823
Short name T280
Test name
Test status
Simulation time 452810726678 ps
CPU time 279.36 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 05:58:39 PM PDT 24
Peak memory 191324 kb
Host smart-e9fafca7-1ace-4b9a-b400-9c2dfed2a4e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484673823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2484673823
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.3926123034
Short name T73
Test name
Test status
Simulation time 205831293866 ps
CPU time 326.71 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 05:58:32 PM PDT 24
Peak memory 191216 kb
Host smart-8eafb572-718f-4585-90bc-0ee19aa23f08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926123034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.3926123034
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_random.1740173165
Short name T287
Test name
Test status
Simulation time 98788380873 ps
CPU time 103.45 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 05:54:50 PM PDT 24
Peak memory 191212 kb
Host smart-30441c0c-76f4-4d16-aa8b-c41454049fe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740173165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1740173165
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.977365977
Short name T242
Test name
Test status
Simulation time 97701155629 ps
CPU time 35.71 seconds
Started Jul 13 05:53:16 PM PDT 24
Finished Jul 13 05:53:53 PM PDT 24
Peak memory 193536 kb
Host smart-61f2b9d1-7474-4c6b-82b0-993c75de1e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977365977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.977365977
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.3180412023
Short name T177
Test name
Test status
Simulation time 866878087321 ps
CPU time 404.88 seconds
Started Jul 13 05:52:45 PM PDT 24
Finished Jul 13 05:59:31 PM PDT 24
Peak memory 191252 kb
Host smart-e7a6b6f8-1483-4175-bbe9-427e0e845df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180412023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
3180412023
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.2709177361
Short name T107
Test name
Test status
Simulation time 181506221670 ps
CPU time 2360.51 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:33:01 PM PDT 24
Peak memory 191088 kb
Host smart-e95c09c2-8585-4900-ba9f-7170290c6fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709177361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.2709177361
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/82.rv_timer_random.2656037540
Short name T169
Test name
Test status
Simulation time 267888315132 ps
CPU time 251.74 seconds
Started Jul 13 05:53:37 PM PDT 24
Finished Jul 13 05:57:50 PM PDT 24
Peak memory 191300 kb
Host smart-c0e53c0c-ff3a-45a4-b0a6-5cfada00c9fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656037540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.2656037540
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.2088066900
Short name T103
Test name
Test status
Simulation time 322834622 ps
CPU time 1.08 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:20 PM PDT 24
Peak memory 194672 kb
Host smart-d0c8d380-bbf2-415a-bb50-8a801567cc56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088066900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.2088066900
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2707959629
Short name T195
Test name
Test status
Simulation time 1116501782728 ps
CPU time 765.71 seconds
Started Jul 13 05:52:37 PM PDT 24
Finished Jul 13 06:05:23 PM PDT 24
Peak memory 191308 kb
Host smart-6ad877cc-bf47-48d5-87d5-0070cd997f90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707959629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2707959629
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2844303339
Short name T222
Test name
Test status
Simulation time 47713018551 ps
CPU time 24.42 seconds
Started Jul 13 05:52:44 PM PDT 24
Finished Jul 13 05:53:09 PM PDT 24
Peak memory 183092 kb
Host smart-449a67a8-3d70-4449-9da3-a393b5657d3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844303339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2844303339
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3880879888
Short name T65
Test name
Test status
Simulation time 35078435567 ps
CPU time 49.62 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 05:53:55 PM PDT 24
Peak memory 183076 kb
Host smart-8abaa409-8816-4bd1-afa1-e43f7429172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880879888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3880879888
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/103.rv_timer_random.1493995843
Short name T117
Test name
Test status
Simulation time 705997058463 ps
CPU time 407.19 seconds
Started Jul 13 05:53:45 PM PDT 24
Finished Jul 13 06:00:33 PM PDT 24
Peak memory 191236 kb
Host smart-a8018d0b-ccc8-473e-8284-76609d8ea889
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493995843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1493995843
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.2653159612
Short name T295
Test name
Test status
Simulation time 37014885738 ps
CPU time 241.25 seconds
Started Jul 13 05:53:47 PM PDT 24
Finished Jul 13 05:57:49 PM PDT 24
Peak memory 191220 kb
Host smart-b847e786-2f36-44b5-b8ca-fdf0d1cf3793
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653159612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.2653159612
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.387782172
Short name T286
Test name
Test status
Simulation time 125334935135 ps
CPU time 200.91 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:56:28 PM PDT 24
Peak memory 191328 kb
Host smart-dd0fa533-be9b-4f81-90a2-c4254ca8f0e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387782172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.387782172
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.856462642
Short name T187
Test name
Test status
Simulation time 107436827609 ps
CPU time 401.68 seconds
Started Jul 13 05:53:51 PM PDT 24
Finished Jul 13 06:00:34 PM PDT 24
Peak memory 183132 kb
Host smart-a17c1a7d-de60-4e78-94b7-20f09e2e04c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856462642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.856462642
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.807437090
Short name T237
Test name
Test status
Simulation time 568588966122 ps
CPU time 157.3 seconds
Started Jul 13 05:53:52 PM PDT 24
Finished Jul 13 05:56:30 PM PDT 24
Peak memory 194036 kb
Host smart-c204d76d-d442-4691-9d9c-d88a56f08e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807437090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.807437090
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3353436209
Short name T216
Test name
Test status
Simulation time 51985449730 ps
CPU time 485.92 seconds
Started Jul 13 05:54:01 PM PDT 24
Finished Jul 13 06:02:07 PM PDT 24
Peak memory 191320 kb
Host smart-4b34d6e7-33fe-48ab-8471-86010f3202bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353436209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3353436209
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.1844909793
Short name T182
Test name
Test status
Simulation time 652836429818 ps
CPU time 368.38 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 06:00:08 PM PDT 24
Peak memory 191324 kb
Host smart-0a91e72c-cebc-45a8-94fb-ca4c8233e3ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844909793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.1844909793
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3344105372
Short name T317
Test name
Test status
Simulation time 47264101927 ps
CPU time 62.25 seconds
Started Jul 13 05:54:06 PM PDT 24
Finished Jul 13 05:55:08 PM PDT 24
Peak memory 191220 kb
Host smart-9479100c-22b6-4d38-bd09-d52b95f2c4de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344105372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3344105372
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random.3535629802
Short name T121
Test name
Test status
Simulation time 138005806847 ps
CPU time 233.6 seconds
Started Jul 13 05:53:03 PM PDT 24
Finished Jul 13 05:56:57 PM PDT 24
Peak memory 191252 kb
Host smart-0b5d9849-b389-47f5-9cca-b1da1da7de67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535629802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3535629802
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.4138726051
Short name T238
Test name
Test status
Simulation time 224447989560 ps
CPU time 423.06 seconds
Started Jul 13 05:54:21 PM PDT 24
Finished Jul 13 06:01:25 PM PDT 24
Peak memory 191316 kb
Host smart-4ee5acf2-4d0e-410e-b401-dcf8054f4594
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138726051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.4138726051
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3095268940
Short name T241
Test name
Test status
Simulation time 2413427304763 ps
CPU time 901.14 seconds
Started Jul 13 05:53:06 PM PDT 24
Finished Jul 13 06:08:09 PM PDT 24
Peak memory 183064 kb
Host smart-4f7f6160-2635-4b95-a67d-a37340dcc3a0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095268940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3095268940
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/175.rv_timer_random.4095138070
Short name T351
Test name
Test status
Simulation time 49208306511 ps
CPU time 114.29 seconds
Started Jul 13 05:54:28 PM PDT 24
Finished Jul 13 05:56:22 PM PDT 24
Peak memory 191220 kb
Host smart-02af8718-c0ea-41f9-8ccb-93022de73356
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095138070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.4095138070
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.1594429250
Short name T304
Test name
Test status
Simulation time 265579857921 ps
CPU time 257.08 seconds
Started Jul 13 05:54:36 PM PDT 24
Finished Jul 13 05:58:54 PM PDT 24
Peak memory 191300 kb
Host smart-9f3a413b-9bbc-44fc-9017-5727fa7bf64d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594429250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.1594429250
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2435383833
Short name T302
Test name
Test status
Simulation time 126900035279 ps
CPU time 173.95 seconds
Started Jul 13 05:53:07 PM PDT 24
Finished Jul 13 05:56:02 PM PDT 24
Peak memory 183088 kb
Host smart-9bfda2dc-e72f-472e-ba66-e529fcad508e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435383833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2435383833
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2330687187
Short name T74
Test name
Test status
Simulation time 1311327706977 ps
CPU time 1226.22 seconds
Started Jul 13 05:53:07 PM PDT 24
Finished Jul 13 06:13:35 PM PDT 24
Peak memory 195060 kb
Host smart-62d20af9-3171-4d6e-88a3-4a7764bd7d86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330687187 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2330687187
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_random.3865349046
Short name T156
Test name
Test status
Simulation time 240952471608 ps
CPU time 367.84 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 05:59:14 PM PDT 24
Peak memory 191324 kb
Host smart-9d4e08cc-e90d-4d06-8d62-d8e203a87b4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865349046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3865349046
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random.4155998156
Short name T338
Test name
Test status
Simulation time 101554754606 ps
CPU time 127.82 seconds
Started Jul 13 05:53:15 PM PDT 24
Finished Jul 13 05:55:23 PM PDT 24
Peak memory 183132 kb
Host smart-0d3de876-a50e-4773-a0d0-3c20d380a5cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155998156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.4155998156
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.1889342274
Short name T214
Test name
Test status
Simulation time 363423301063 ps
CPU time 550.82 seconds
Started Jul 13 05:53:15 PM PDT 24
Finished Jul 13 06:02:27 PM PDT 24
Peak memory 191228 kb
Host smart-5da5e10d-d26e-4324-bb5d-fe89112ac5d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889342274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.1889342274
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random.1448283610
Short name T245
Test name
Test status
Simulation time 120580920475 ps
CPU time 589.18 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 06:03:08 PM PDT 24
Peak memory 191324 kb
Host smart-34667b1b-55db-4296-b3ee-35d86cbc4641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448283610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.1448283610
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random.3611792560
Short name T273
Test name
Test status
Simulation time 127448672210 ps
CPU time 536.56 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 06:02:21 PM PDT 24
Peak memory 191324 kb
Host smart-ac4b0ffd-a5bd-4dcb-a12b-217e041a9eab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611792560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3611792560
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random.4194747047
Short name T165
Test name
Test status
Simulation time 544304696970 ps
CPU time 652.02 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:04:32 PM PDT 24
Peak memory 191248 kb
Host smart-3d90a0f1-5a19-4db3-8832-488555a147ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194747047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.4194747047
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.98066022
Short name T7
Test name
Test status
Simulation time 139780983372 ps
CPU time 228.54 seconds
Started Jul 13 05:52:53 PM PDT 24
Finished Jul 13 05:56:42 PM PDT 24
Peak memory 194672 kb
Host smart-de0e7c82-b7aa-4e80-bccd-eb5c44d56f16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98066022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.98066022
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4230133178
Short name T86
Test name
Test status
Simulation time 121324314 ps
CPU time 0.84 seconds
Started Jul 13 04:39:29 PM PDT 24
Finished Jul 13 04:39:33 PM PDT 24
Peak memory 192148 kb
Host smart-491543fa-0df7-429b-8fe6-fe3b80bb009d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230133178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4230133178
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.917610039
Short name T84
Test name
Test status
Simulation time 63228814 ps
CPU time 2.34 seconds
Started Jul 13 04:39:11 PM PDT 24
Finished Jul 13 04:39:14 PM PDT 24
Peak memory 193272 kb
Host smart-92f8980e-7fd3-4e0c-a082-12915c0a5555
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917610039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.917610039
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2693749292
Short name T495
Test name
Test status
Simulation time 81347265 ps
CPU time 0.55 seconds
Started Jul 13 04:39:20 PM PDT 24
Finished Jul 13 04:39:22 PM PDT 24
Peak memory 181684 kb
Host smart-cc36fa65-184e-4b4f-b68f-cce4aac23268
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693749292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2693749292
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.3127473679
Short name T550
Test name
Test status
Simulation time 33712702 ps
CPU time 0.84 seconds
Started Jul 13 04:38:58 PM PDT 24
Finished Jul 13 04:39:00 PM PDT 24
Peak memory 195896 kb
Host smart-cb8a982e-4d2f-4393-85ee-77e1885c4ccd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127473679 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.3127473679
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.347314250
Short name T53
Test name
Test status
Simulation time 147707980 ps
CPU time 0.56 seconds
Started Jul 13 04:38:58 PM PDT 24
Finished Jul 13 04:39:00 PM PDT 24
Peak memory 181996 kb
Host smart-f6a779a0-e5f8-458c-8f0e-59a5389a5fb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347314250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.347314250
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.1080963149
Short name T512
Test name
Test status
Simulation time 39500402 ps
CPU time 0.56 seconds
Started Jul 13 04:38:54 PM PDT 24
Finished Jul 13 04:38:57 PM PDT 24
Peak memory 182064 kb
Host smart-412af57f-2c2f-4657-b9c0-cbb661be9b06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080963149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.1080963149
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.834453683
Short name T524
Test name
Test status
Simulation time 35083554 ps
CPU time 0.63 seconds
Started Jul 13 04:38:55 PM PDT 24
Finished Jul 13 04:38:58 PM PDT 24
Peak memory 190980 kb
Host smart-60966302-cc72-430d-b183-e67cd71e9eb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834453683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.834453683
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2947272068
Short name T538
Test name
Test status
Simulation time 195392596 ps
CPU time 1.28 seconds
Started Jul 13 04:39:03 PM PDT 24
Finished Jul 13 04:39:05 PM PDT 24
Peak memory 197000 kb
Host smart-82ee12fb-4142-44df-bb38-a294e23bbdcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947272068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2947272068
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1572250890
Short name T489
Test name
Test status
Simulation time 193836504 ps
CPU time 0.81 seconds
Started Jul 13 04:39:20 PM PDT 24
Finished Jul 13 04:39:23 PM PDT 24
Peak memory 193176 kb
Host smart-8cefa876-1504-4424-b6b7-c7d86561eae7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572250890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1572250890
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.1607453544
Short name T83
Test name
Test status
Simulation time 125759056 ps
CPU time 0.61 seconds
Started Jul 13 04:39:00 PM PDT 24
Finished Jul 13 04:39:01 PM PDT 24
Peak memory 191332 kb
Host smart-312fe7ed-d7d7-4878-9764-a7d4f3b4e149
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607453544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.1607453544
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3730695541
Short name T92
Test name
Test status
Simulation time 1132631274 ps
CPU time 3.63 seconds
Started Jul 13 04:39:01 PM PDT 24
Finished Jul 13 04:39:06 PM PDT 24
Peak memory 191752 kb
Host smart-c090fabc-c6a1-41fe-b30c-96cbae96434f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730695541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3730695541
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.1853179351
Short name T95
Test name
Test status
Simulation time 28307986 ps
CPU time 0.57 seconds
Started Jul 13 04:39:10 PM PDT 24
Finished Jul 13 04:39:11 PM PDT 24
Peak memory 182156 kb
Host smart-aa3d0026-3942-4897-a8a2-9816555e100e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853179351 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.1853179351
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3632766697
Short name T536
Test name
Test status
Simulation time 19689938 ps
CPU time 0.81 seconds
Started Jul 13 04:39:06 PM PDT 24
Finished Jul 13 04:39:07 PM PDT 24
Peak memory 196348 kb
Host smart-32453ca8-0ae8-47ce-aa29-13d9d3e3f3cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632766697 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3632766697
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.1018993767
Short name T478
Test name
Test status
Simulation time 15439746 ps
CPU time 0.59 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:17 PM PDT 24
Peak memory 182168 kb
Host smart-07cdf470-fde2-4e7b-9b94-cb512383c293
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018993767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.1018993767
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.1919382621
Short name T490
Test name
Test status
Simulation time 10746256 ps
CPU time 0.62 seconds
Started Jul 13 04:39:21 PM PDT 24
Finished Jul 13 04:39:23 PM PDT 24
Peak memory 181728 kb
Host smart-233b44dc-d8c8-423b-b04e-6e0c86db0571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919382621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.1919382621
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3415808897
Short name T38
Test name
Test status
Simulation time 325079951 ps
CPU time 3.12 seconds
Started Jul 13 04:39:18 PM PDT 24
Finished Jul 13 04:39:23 PM PDT 24
Peak memory 197356 kb
Host smart-8a70e9e3-11bf-4d6c-801b-b668f4cfcb6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415808897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3415808897
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3530249495
Short name T505
Test name
Test status
Simulation time 21247203 ps
CPU time 0.69 seconds
Started Jul 13 04:38:54 PM PDT 24
Finished Jul 13 04:38:57 PM PDT 24
Peak memory 194120 kb
Host smart-68c9e58a-9aec-4540-98c8-d43111352dd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530249495 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3530249495
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3905071063
Short name T91
Test name
Test status
Simulation time 53500101 ps
CPU time 0.56 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:19 PM PDT 24
Peak memory 181968 kb
Host smart-d5e0c79f-756d-41b3-9491-a3438a439d15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905071063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3905071063
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.1364253253
Short name T498
Test name
Test status
Simulation time 14932904 ps
CPU time 0.54 seconds
Started Jul 13 04:39:16 PM PDT 24
Finished Jul 13 04:39:20 PM PDT 24
Peak memory 182044 kb
Host smart-28ed4b16-ed6c-4eb2-9682-8f6c9cadbb94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364253253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.1364253253
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3955030434
Short name T520
Test name
Test status
Simulation time 16079817 ps
CPU time 0.7 seconds
Started Jul 13 04:39:05 PM PDT 24
Finished Jul 13 04:39:07 PM PDT 24
Peak memory 191112 kb
Host smart-6836d56e-268b-4c84-84db-9679c1a3aa59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955030434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3955030434
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3011522374
Short name T55
Test name
Test status
Simulation time 804164683 ps
CPU time 1.82 seconds
Started Jul 13 04:38:57 PM PDT 24
Finished Jul 13 04:39:00 PM PDT 24
Peak memory 196952 kb
Host smart-d2f239f7-6659-45ba-b038-91a5ce80e77d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011522374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3011522374
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.1425209676
Short name T564
Test name
Test status
Simulation time 88445307 ps
CPU time 0.83 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:17 PM PDT 24
Peak memory 193276 kb
Host smart-c240d4fc-ce7c-4845-88cd-b6d6d9f8dd80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425209676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.1425209676
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2525055241
Short name T66
Test name
Test status
Simulation time 35060311 ps
CPU time 0.78 seconds
Started Jul 13 04:39:12 PM PDT 24
Finished Jul 13 04:39:14 PM PDT 24
Peak memory 194728 kb
Host smart-88cd6cd8-536f-42bd-894c-20936d767da0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525055241 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2525055241
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2120671636
Short name T567
Test name
Test status
Simulation time 20348449 ps
CPU time 0.59 seconds
Started Jul 13 04:39:16 PM PDT 24
Finished Jul 13 04:39:20 PM PDT 24
Peak memory 182172 kb
Host smart-ad1bed59-8c1c-4715-bfbb-4433a8412c72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120671636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2120671636
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.68949867
Short name T565
Test name
Test status
Simulation time 12854912 ps
CPU time 0.53 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:17 PM PDT 24
Peak memory 182080 kb
Host smart-b473c314-55cf-40b0-9880-27abf2548e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68949867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.68949867
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.669419146
Short name T96
Test name
Test status
Simulation time 27650465 ps
CPU time 0.72 seconds
Started Jul 13 04:39:16 PM PDT 24
Finished Jul 13 04:39:19 PM PDT 24
Peak memory 192676 kb
Host smart-c1e3def4-f4e9-4615-81f5-d1fa294233db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669419146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.669419146
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1876632587
Short name T484
Test name
Test status
Simulation time 653926634 ps
CPU time 2.94 seconds
Started Jul 13 04:38:58 PM PDT 24
Finished Jul 13 04:39:02 PM PDT 24
Peak memory 196932 kb
Host smart-0eff5acd-1d84-4ba0-9c67-3a5d09cefc52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876632587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1876632587
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.2048653867
Short name T470
Test name
Test status
Simulation time 31656177 ps
CPU time 1.2 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:22 PM PDT 24
Peak memory 196956 kb
Host smart-9da144f0-f702-458c-adee-c8a592cefc99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048653867 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.2048653867
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3092408346
Short name T510
Test name
Test status
Simulation time 14976243 ps
CPU time 0.6 seconds
Started Jul 13 04:39:04 PM PDT 24
Finished Jul 13 04:39:06 PM PDT 24
Peak memory 182084 kb
Host smart-85665229-4595-4c2b-93a8-4d6c1b6c3049
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092408346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3092408346
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2419316419
Short name T506
Test name
Test status
Simulation time 201653688 ps
CPU time 0.63 seconds
Started Jul 13 04:38:59 PM PDT 24
Finished Jul 13 04:39:00 PM PDT 24
Peak memory 190972 kb
Host smart-c10657d8-8130-4a78-9967-f9646634f28a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419316419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2419316419
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1267623185
Short name T479
Test name
Test status
Simulation time 800350579 ps
CPU time 2.79 seconds
Started Jul 13 04:38:54 PM PDT 24
Finished Jul 13 04:38:59 PM PDT 24
Peak memory 196972 kb
Host smart-221d37d9-fa4d-4828-ba12-df6fc4c95b8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267623185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1267623185
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.3237413378
Short name T30
Test name
Test status
Simulation time 450269863 ps
CPU time 1.33 seconds
Started Jul 13 04:39:09 PM PDT 24
Finished Jul 13 04:39:11 PM PDT 24
Peak memory 194820 kb
Host smart-e1f88904-3a22-4d9a-8a0e-26f4262403c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237413378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.3237413378
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3740164844
Short name T516
Test name
Test status
Simulation time 210153099 ps
CPU time 0.86 seconds
Started Jul 13 04:39:02 PM PDT 24
Finished Jul 13 04:39:04 PM PDT 24
Peak memory 195800 kb
Host smart-25324fdb-d044-42f5-ab1b-f9c23c8d60dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740164844 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3740164844
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.1040178947
Short name T93
Test name
Test status
Simulation time 12310100 ps
CPU time 0.56 seconds
Started Jul 13 04:39:18 PM PDT 24
Finished Jul 13 04:39:32 PM PDT 24
Peak memory 182188 kb
Host smart-8e5ff793-fa1c-45ed-9738-e305f0d82482
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040178947 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.1040178947
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2762428704
Short name T469
Test name
Test status
Simulation time 41032955 ps
CPU time 0.55 seconds
Started Jul 13 04:39:16 PM PDT 24
Finished Jul 13 04:39:19 PM PDT 24
Peak memory 182024 kb
Host smart-b8c65897-fe72-47fd-8814-219c9ea6dd08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762428704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2762428704
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.333652067
Short name T558
Test name
Test status
Simulation time 39469615 ps
CPU time 0.69 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:15 PM PDT 24
Peak memory 192548 kb
Host smart-e5e7f878-fb38-4bf7-ac05-8063ec726468
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333652067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_ti
mer_same_csr_outstanding.333652067
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1113116999
Short name T552
Test name
Test status
Simulation time 41637133 ps
CPU time 0.97 seconds
Started Jul 13 04:39:19 PM PDT 24
Finished Jul 13 04:39:22 PM PDT 24
Peak memory 196548 kb
Host smart-b4f641d8-227a-424c-96a6-49611a2307d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113116999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1113116999
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.517952854
Short name T464
Test name
Test status
Simulation time 84986515 ps
CPU time 1.21 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:18 PM PDT 24
Peak memory 194612 kb
Host smart-3c84c5c0-0325-451e-90e2-8aaf56ca5d94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517952854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_in
tg_err.517952854
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.4039224120
Short name T467
Test name
Test status
Simulation time 72346355 ps
CPU time 0.69 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:15 PM PDT 24
Peak memory 194376 kb
Host smart-9580a468-f9b6-4da0-ba88-63d28f0da00b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039224120 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.4039224120
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.2584598882
Short name T560
Test name
Test status
Simulation time 14164011 ps
CPU time 0.57 seconds
Started Jul 13 04:39:18 PM PDT 24
Finished Jul 13 04:39:21 PM PDT 24
Peak memory 182468 kb
Host smart-a9254609-b201-4bd7-bb42-ee8314f62d3e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584598882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.2584598882
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.1078326087
Short name T526
Test name
Test status
Simulation time 50503506 ps
CPU time 0.63 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:19 PM PDT 24
Peak memory 182024 kb
Host smart-bc94f71e-3d4b-4101-accf-4f3d6d5b3350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078326087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.1078326087
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.504783799
Short name T477
Test name
Test status
Simulation time 25656942 ps
CPU time 0.61 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:17 PM PDT 24
Peak memory 190900 kb
Host smart-7ab85476-ae0b-445e-914b-3e35fa53a382
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504783799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_ti
mer_same_csr_outstanding.504783799
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1654638133
Short name T508
Test name
Test status
Simulation time 487326286 ps
CPU time 2.11 seconds
Started Jul 13 04:39:10 PM PDT 24
Finished Jul 13 04:39:12 PM PDT 24
Peak memory 196988 kb
Host smart-b7f5d8a7-7599-4084-b0d2-dc90e79ba65b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654638133 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1654638133
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2733570165
Short name T28
Test name
Test status
Simulation time 68534677 ps
CPU time 1.12 seconds
Started Jul 13 04:39:10 PM PDT 24
Finished Jul 13 04:39:12 PM PDT 24
Peak memory 194696 kb
Host smart-37354dee-1f60-4728-bd90-689b8165ace8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733570165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2733570165
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.3211708881
Short name T530
Test name
Test status
Simulation time 107606623 ps
CPU time 0.79 seconds
Started Jul 13 04:39:07 PM PDT 24
Finished Jul 13 04:39:09 PM PDT 24
Peak memory 194980 kb
Host smart-f5248eeb-14a2-43d4-8b3f-5f7964c283e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211708881 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.3211708881
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3104754591
Short name T90
Test name
Test status
Simulation time 17333356 ps
CPU time 0.58 seconds
Started Jul 13 04:39:12 PM PDT 24
Finished Jul 13 04:39:13 PM PDT 24
Peak memory 182180 kb
Host smart-99b24004-7484-438d-958e-8245178143d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104754591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3104754591
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.2313130307
Short name T481
Test name
Test status
Simulation time 113693104 ps
CPU time 0.56 seconds
Started Jul 13 04:39:16 PM PDT 24
Finished Jul 13 04:39:20 PM PDT 24
Peak memory 182024 kb
Host smart-a935b987-93f8-4b8b-9192-fc573aa2969f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313130307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.2313130307
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3921026968
Short name T87
Test name
Test status
Simulation time 16004357 ps
CPU time 0.72 seconds
Started Jul 13 04:39:21 PM PDT 24
Finished Jul 13 04:39:24 PM PDT 24
Peak memory 191108 kb
Host smart-6ab3d552-4d7e-4bdf-b1d3-3a256d622492
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921026968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3921026968
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.867263872
Short name T544
Test name
Test status
Simulation time 135703150 ps
CPU time 1.52 seconds
Started Jul 13 04:39:19 PM PDT 24
Finished Jul 13 04:39:22 PM PDT 24
Peak memory 196960 kb
Host smart-d9066df1-3963-46da-bddd-e46fc8630c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867263872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.867263872
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.2073670973
Short name T537
Test name
Test status
Simulation time 429538973 ps
CPU time 1.38 seconds
Started Jul 13 04:39:09 PM PDT 24
Finished Jul 13 04:39:11 PM PDT 24
Peak memory 193908 kb
Host smart-ad6bb671-c1f8-4df9-b8a9-9a2e3acebb5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073670973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.2073670973
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.1935469961
Short name T488
Test name
Test status
Simulation time 643051716 ps
CPU time 0.99 seconds
Started Jul 13 04:39:12 PM PDT 24
Finished Jul 13 04:39:15 PM PDT 24
Peak memory 196144 kb
Host smart-c4130e22-526c-491e-b223-d689cfdbca52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935469961 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.1935469961
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.3446012472
Short name T449
Test name
Test status
Simulation time 15675810 ps
CPU time 0.57 seconds
Started Jul 13 04:39:08 PM PDT 24
Finished Jul 13 04:39:09 PM PDT 24
Peak memory 181900 kb
Host smart-dd1d28ba-99b2-419d-ba91-0096f8674886
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446012472 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.3446012472
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2959726479
Short name T562
Test name
Test status
Simulation time 12457454 ps
CPU time 0.58 seconds
Started Jul 13 04:39:04 PM PDT 24
Finished Jul 13 04:39:06 PM PDT 24
Peak memory 182048 kb
Host smart-cac5e3f8-b266-4fd1-85f6-a0b95d08d738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959726479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2959726479
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1482072734
Short name T85
Test name
Test status
Simulation time 52522066 ps
CPU time 0.71 seconds
Started Jul 13 04:39:11 PM PDT 24
Finished Jul 13 04:39:13 PM PDT 24
Peak memory 191132 kb
Host smart-1f5efd01-484d-42e4-847d-5cd16bea132e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482072734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1482072734
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4051777559
Short name T452
Test name
Test status
Simulation time 32506061 ps
CPU time 1.61 seconds
Started Jul 13 04:39:07 PM PDT 24
Finished Jul 13 04:39:09 PM PDT 24
Peak memory 196900 kb
Host smart-856807ba-378f-466d-9c63-27bef9f27adf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051777559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4051777559
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2704666873
Short name T533
Test name
Test status
Simulation time 88206763 ps
CPU time 1.11 seconds
Started Jul 13 04:39:38 PM PDT 24
Finished Jul 13 04:39:40 PM PDT 24
Peak memory 194708 kb
Host smart-94d72957-0881-4997-acf3-9858a80e87ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704666873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2704666873
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3493505135
Short name T523
Test name
Test status
Simulation time 131236464 ps
CPU time 0.85 seconds
Started Jul 13 04:39:36 PM PDT 24
Finished Jul 13 04:39:38 PM PDT 24
Peak memory 196292 kb
Host smart-a2887b11-ff5e-46c8-90a9-fc713993decd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493505135 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3493505135
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.488232866
Short name T89
Test name
Test status
Simulation time 30526408 ps
CPU time 0.55 seconds
Started Jul 13 04:39:31 PM PDT 24
Finished Jul 13 04:39:34 PM PDT 24
Peak memory 181856 kb
Host smart-c450ad18-5c8f-472c-b47e-afa170a16a7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488232866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.488232866
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1894684879
Short name T475
Test name
Test status
Simulation time 66454274 ps
CPU time 0.55 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:39:31 PM PDT 24
Peak memory 182012 kb
Host smart-b2b15b88-a3ab-4b7e-b68e-9bf9303443e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894684879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1894684879
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.2633118084
Short name T540
Test name
Test status
Simulation time 76901815 ps
CPU time 0.7 seconds
Started Jul 13 04:39:23 PM PDT 24
Finished Jul 13 04:39:25 PM PDT 24
Peak memory 191536 kb
Host smart-9955964b-ec0e-4bcd-a63a-40c604002cb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633118084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.2633118084
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3079116416
Short name T40
Test name
Test status
Simulation time 157175092 ps
CPU time 3.12 seconds
Started Jul 13 04:38:55 PM PDT 24
Finished Jul 13 04:39:00 PM PDT 24
Peak memory 196904 kb
Host smart-860f539c-ae4f-4f03-9bff-9438334e541d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079116416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3079116416
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3854315955
Short name T519
Test name
Test status
Simulation time 123515650 ps
CPU time 0.78 seconds
Started Jul 13 04:39:12 PM PDT 24
Finished Jul 13 04:39:13 PM PDT 24
Peak memory 192120 kb
Host smart-dfdb70c6-2cb5-4d11-8488-bf17a997b453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854315955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3854315955
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3668249104
Short name T39
Test name
Test status
Simulation time 81012092 ps
CPU time 0.74 seconds
Started Jul 13 04:39:20 PM PDT 24
Finished Jul 13 04:39:23 PM PDT 24
Peak memory 195568 kb
Host smart-e327841c-a2f4-41c1-ae7e-a9549b1288e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668249104 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3668249104
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3499939951
Short name T461
Test name
Test status
Simulation time 43985115 ps
CPU time 0.56 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:27 PM PDT 24
Peak memory 182104 kb
Host smart-57a433c2-6382-413c-b0b9-61fa4db3ba4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499939951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3499939951
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3205427232
Short name T547
Test name
Test status
Simulation time 16757439 ps
CPU time 0.53 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:28 PM PDT 24
Peak memory 182032 kb
Host smart-e0ea8c83-049b-43e4-950c-48b22a8956d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205427232 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3205427232
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.1906073597
Short name T54
Test name
Test status
Simulation time 38571187 ps
CPU time 0.79 seconds
Started Jul 13 04:39:28 PM PDT 24
Finished Jul 13 04:39:32 PM PDT 24
Peak memory 192776 kb
Host smart-41fd40d2-9538-4376-a2bb-65bd70c6cb29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906073597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.1906073597
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1347060892
Short name T462
Test name
Test status
Simulation time 63095934 ps
CPU time 1.72 seconds
Started Jul 13 04:39:32 PM PDT 24
Finished Jul 13 04:39:40 PM PDT 24
Peak memory 196964 kb
Host smart-b1a8bc39-ce94-4953-b0f7-bd352cba7a04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347060892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1347060892
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.145212029
Short name T67
Test name
Test status
Simulation time 220594161 ps
CPU time 1.31 seconds
Started Jul 13 04:39:18 PM PDT 24
Finished Jul 13 04:39:21 PM PDT 24
Peak memory 194916 kb
Host smart-8295e078-9260-43e0-b1ed-71126a963347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145212029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_in
tg_err.145212029
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1308621887
Short name T517
Test name
Test status
Simulation time 18035278 ps
CPU time 0.62 seconds
Started Jul 13 04:39:32 PM PDT 24
Finished Jul 13 04:39:34 PM PDT 24
Peak memory 192960 kb
Host smart-cf73df1c-a7d8-4ca5-8d2f-a91737cf52da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308621887 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1308621887
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1604202094
Short name T31
Test name
Test status
Simulation time 23878632 ps
CPU time 0.57 seconds
Started Jul 13 04:39:32 PM PDT 24
Finished Jul 13 04:39:34 PM PDT 24
Peak memory 182168 kb
Host smart-14b4dbc6-7edd-4dad-8b78-c8e30b1bf710
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604202094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1604202094
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.1278149769
Short name T492
Test name
Test status
Simulation time 15704361 ps
CPU time 0.57 seconds
Started Jul 13 04:39:16 PM PDT 24
Finished Jul 13 04:39:20 PM PDT 24
Peak memory 182108 kb
Host smart-f61fb681-4bfc-4f7a-869e-f5d516af56b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278149769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.1278149769
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.3948112753
Short name T97
Test name
Test status
Simulation time 43861359 ps
CPU time 0.79 seconds
Started Jul 13 04:39:39 PM PDT 24
Finished Jul 13 04:39:42 PM PDT 24
Peak memory 192784 kb
Host smart-99daad7b-fdeb-40f3-9c2a-0e5a0dd9d034
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948112753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.3948112753
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.1362797023
Short name T457
Test name
Test status
Simulation time 205604736 ps
CPU time 2.8 seconds
Started Jul 13 04:39:22 PM PDT 24
Finished Jul 13 04:39:26 PM PDT 24
Peak memory 196940 kb
Host smart-82ea3390-6b01-408c-b92a-7d2dbde4b3c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362797023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.1362797023
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1507798082
Short name T102
Test name
Test status
Simulation time 80700471 ps
CPU time 1.05 seconds
Started Jul 13 04:39:34 PM PDT 24
Finished Jul 13 04:39:36 PM PDT 24
Peak memory 194428 kb
Host smart-089d4310-ac99-40f1-9110-e1d7dde1343d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507798082 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.1507798082
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3847624683
Short name T33
Test name
Test status
Simulation time 56709862 ps
CPU time 0.73 seconds
Started Jul 13 04:39:11 PM PDT 24
Finished Jul 13 04:39:12 PM PDT 24
Peak memory 192008 kb
Host smart-0ce0ab3a-1d09-48bc-a262-58527e4186bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847624683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3847624683
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2734442274
Short name T568
Test name
Test status
Simulation time 956668447 ps
CPU time 2.42 seconds
Started Jul 13 04:39:03 PM PDT 24
Finished Jul 13 04:39:06 PM PDT 24
Peak memory 192140 kb
Host smart-b5f4db4e-c301-4c8c-979b-8ebce4e866f9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734442274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2734442274
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.656613892
Short name T561
Test name
Test status
Simulation time 15248289 ps
CPU time 0.62 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:15 PM PDT 24
Peak memory 182192 kb
Host smart-453e0b42-602f-47ac-b7fa-7b12011b391f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656613892 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_re
set.656613892
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.458541217
Short name T56
Test name
Test status
Simulation time 27815281 ps
CPU time 0.76 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:17 PM PDT 24
Peak memory 195696 kb
Host smart-a1ab2d59-2e48-46b2-a7c9-5f6eb652e70b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458541217 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.458541217
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1532934421
Short name T556
Test name
Test status
Simulation time 12391644 ps
CPU time 0.54 seconds
Started Jul 13 04:38:52 PM PDT 24
Finished Jul 13 04:38:54 PM PDT 24
Peak memory 182084 kb
Host smart-04261c36-2001-4e42-ab72-091f7cdc97c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532934421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1532934421
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.431230304
Short name T522
Test name
Test status
Simulation time 13654652 ps
CPU time 0.54 seconds
Started Jul 13 04:38:56 PM PDT 24
Finished Jul 13 04:38:58 PM PDT 24
Peak memory 182128 kb
Host smart-ae32b344-6d74-4ef1-bfa6-17ae30f2a8c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431230304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.431230304
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2956805247
Short name T98
Test name
Test status
Simulation time 22025523 ps
CPU time 0.66 seconds
Started Jul 13 04:39:03 PM PDT 24
Finished Jul 13 04:39:05 PM PDT 24
Peak memory 191456 kb
Host smart-b84287e5-a18a-4ba8-8d99-f83f2e288d51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956805247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2956805247
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.3662406649
Short name T551
Test name
Test status
Simulation time 28863672 ps
CPU time 1.43 seconds
Started Jul 13 04:38:58 PM PDT 24
Finished Jul 13 04:39:00 PM PDT 24
Peak memory 196864 kb
Host smart-6d172573-162a-49b0-9a3f-9edf1c668eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662406649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.3662406649
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.3611421724
Short name T549
Test name
Test status
Simulation time 229632691 ps
CPU time 1.36 seconds
Started Jul 13 04:38:56 PM PDT 24
Finished Jul 13 04:39:04 PM PDT 24
Peak memory 182720 kb
Host smart-9b0c7e0f-5c44-40b8-a514-f99682cccf55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611421724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.3611421724
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.194679173
Short name T485
Test name
Test status
Simulation time 27135541 ps
CPU time 0.57 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:39:30 PM PDT 24
Peak memory 182084 kb
Host smart-45d21900-48f2-4cd3-a08b-48edb894ef24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194679173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.194679173
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.693920978
Short name T487
Test name
Test status
Simulation time 23032835 ps
CPU time 0.57 seconds
Started Jul 13 04:39:18 PM PDT 24
Finished Jul 13 04:39:21 PM PDT 24
Peak memory 182096 kb
Host smart-1dbe7872-c665-4777-9fab-021a825a2618
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693920978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.693920978
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.3701161935
Short name T448
Test name
Test status
Simulation time 24378259 ps
CPU time 0.57 seconds
Started Jul 13 04:39:34 PM PDT 24
Finished Jul 13 04:39:35 PM PDT 24
Peak memory 182080 kb
Host smart-8696f667-e9fc-4da8-9cc7-34ec74e0706c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701161935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.3701161935
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2369043056
Short name T518
Test name
Test status
Simulation time 140458089 ps
CPU time 0.52 seconds
Started Jul 13 04:39:23 PM PDT 24
Finished Jul 13 04:39:25 PM PDT 24
Peak memory 181500 kb
Host smart-2f0ee212-7764-4bfc-83b0-5d6d60cf76d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369043056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2369043056
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.1254782416
Short name T463
Test name
Test status
Simulation time 13901480 ps
CPU time 0.57 seconds
Started Jul 13 04:39:22 PM PDT 24
Finished Jul 13 04:39:24 PM PDT 24
Peak memory 182060 kb
Host smart-2d427210-94cf-4e48-9d0d-8c95cb070dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254782416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.1254782416
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1134661426
Short name T482
Test name
Test status
Simulation time 10787728 ps
CPU time 0.53 seconds
Started Jul 13 04:39:29 PM PDT 24
Finished Jul 13 04:39:33 PM PDT 24
Peak memory 182020 kb
Host smart-e12bf7f0-cb49-4864-8cc1-4cdc204018e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134661426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1134661426
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1906064882
Short name T473
Test name
Test status
Simulation time 48541744 ps
CPU time 0.56 seconds
Started Jul 13 04:39:26 PM PDT 24
Finished Jul 13 04:39:30 PM PDT 24
Peak memory 182008 kb
Host smart-804bd19d-e6cb-479f-bf5f-22afa18c0ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906064882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1906064882
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.4287355324
Short name T528
Test name
Test status
Simulation time 13118331 ps
CPU time 0.56 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:17 PM PDT 24
Peak memory 182088 kb
Host smart-5f3d7381-c5f9-4896-9895-2ea62977dbce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287355324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.4287355324
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.3462085468
Short name T456
Test name
Test status
Simulation time 12053428 ps
CPU time 0.55 seconds
Started Jul 13 04:39:24 PM PDT 24
Finished Jul 13 04:39:26 PM PDT 24
Peak memory 182036 kb
Host smart-fa4bfd01-b7ed-4353-9540-ac7945e9a8f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462085468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.3462085468
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2674280680
Short name T514
Test name
Test status
Simulation time 42105033 ps
CPU time 0.59 seconds
Started Jul 13 04:39:35 PM PDT 24
Finished Jul 13 04:39:37 PM PDT 24
Peak memory 182072 kb
Host smart-986633aa-3422-4f11-bdce-ba70133cdb29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674280680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2674280680
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.2043550091
Short name T534
Test name
Test status
Simulation time 86298912 ps
CPU time 0.73 seconds
Started Jul 13 04:39:11 PM PDT 24
Finished Jul 13 04:39:12 PM PDT 24
Peak memory 191880 kb
Host smart-dd8bb879-1d91-435e-8cd2-33aaa613413f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043550091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.2043550091
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.165098602
Short name T563
Test name
Test status
Simulation time 120679271 ps
CPU time 2.39 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:17 PM PDT 24
Peak memory 190504 kb
Host smart-51c0743e-0644-442c-ae52-1c843e7db81a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165098602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_b
ash.165098602
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.1155442162
Short name T543
Test name
Test status
Simulation time 50789384 ps
CPU time 0.56 seconds
Started Jul 13 04:39:03 PM PDT 24
Finished Jul 13 04:39:05 PM PDT 24
Peak memory 182184 kb
Host smart-786a26f0-a707-4e63-a838-7e18af5d5b9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155442162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.1155442162
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.1038888139
Short name T511
Test name
Test status
Simulation time 30539367 ps
CPU time 0.65 seconds
Started Jul 13 04:38:53 PM PDT 24
Finished Jul 13 04:38:56 PM PDT 24
Peak memory 193856 kb
Host smart-32aa54e2-6a9e-4d08-b971-e954c369a2f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038888139 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.1038888139
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.2820325481
Short name T532
Test name
Test status
Simulation time 39659417 ps
CPU time 0.56 seconds
Started Jul 13 04:39:12 PM PDT 24
Finished Jul 13 04:39:14 PM PDT 24
Peak memory 182116 kb
Host smart-3ad9ecdd-6c54-42a4-8cd7-34d9fec39af8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820325481 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.2820325481
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.547536388
Short name T447
Test name
Test status
Simulation time 53218200 ps
CPU time 0.53 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:19 PM PDT 24
Peak memory 181716 kb
Host smart-40088492-18eb-4b56-a954-c2f8c83f3327
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547536388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.547536388
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1496676037
Short name T502
Test name
Test status
Simulation time 14514536 ps
CPU time 0.61 seconds
Started Jul 13 04:39:00 PM PDT 24
Finished Jul 13 04:39:01 PM PDT 24
Peak memory 191396 kb
Host smart-bac7b487-d66c-4ab6-aae2-5be987ed658d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496676037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1496676037
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3999941693
Short name T541
Test name
Test status
Simulation time 424560404 ps
CPU time 1.94 seconds
Started Jul 13 04:39:30 PM PDT 24
Finished Jul 13 04:39:35 PM PDT 24
Peak memory 196956 kb
Host smart-7b140be8-1370-430f-83d5-c419e48c27b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999941693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3999941693
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.412126882
Short name T472
Test name
Test status
Simulation time 160221608 ps
CPU time 1.12 seconds
Started Jul 13 04:38:53 PM PDT 24
Finished Jul 13 04:38:56 PM PDT 24
Peak memory 194252 kb
Host smart-1ddf46cd-9e27-4a4b-85ce-97861a543a06
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412126882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_int
g_err.412126882
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3100667001
Short name T494
Test name
Test status
Simulation time 13450607 ps
CPU time 0.52 seconds
Started Jul 13 04:39:23 PM PDT 24
Finished Jul 13 04:39:24 PM PDT 24
Peak memory 181484 kb
Host smart-221e2855-f5c8-449e-80b3-ff3389b8d9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100667001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3100667001
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.4127239759
Short name T500
Test name
Test status
Simulation time 45082016 ps
CPU time 0.55 seconds
Started Jul 13 04:39:16 PM PDT 24
Finished Jul 13 04:39:20 PM PDT 24
Peak memory 182088 kb
Host smart-5fb7deee-85d6-44da-a84c-27f18dc65061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127239759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.4127239759
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.1039749816
Short name T450
Test name
Test status
Simulation time 50641004 ps
CPU time 0.59 seconds
Started Jul 13 04:39:23 PM PDT 24
Finished Jul 13 04:39:25 PM PDT 24
Peak memory 182028 kb
Host smart-00b12198-1540-48ab-ab2f-852eb2a6ec61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039749816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.1039749816
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2199698876
Short name T542
Test name
Test status
Simulation time 11969158 ps
CPU time 0.56 seconds
Started Jul 13 04:39:21 PM PDT 24
Finished Jul 13 04:39:23 PM PDT 24
Peak memory 182004 kb
Host smart-5d4a5fb9-7f5f-4651-b7a7-4ccc1829caf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199698876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2199698876
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.1540283274
Short name T504
Test name
Test status
Simulation time 30522284 ps
CPU time 0.53 seconds
Started Jul 13 04:39:39 PM PDT 24
Finished Jul 13 04:39:40 PM PDT 24
Peak memory 181728 kb
Host smart-54f128a9-d295-4110-8f86-5283b30d1e84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540283274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.1540283274
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.952953193
Short name T529
Test name
Test status
Simulation time 16655760 ps
CPU time 0.6 seconds
Started Jul 13 04:39:20 PM PDT 24
Finished Jul 13 04:39:22 PM PDT 24
Peak memory 182088 kb
Host smart-11886bd7-68da-4b26-8fcc-b3cf95b1ef2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952953193 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.952953193
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.1308015774
Short name T499
Test name
Test status
Simulation time 27421091 ps
CPU time 0.57 seconds
Started Jul 13 04:39:31 PM PDT 24
Finished Jul 13 04:39:34 PM PDT 24
Peak memory 182080 kb
Host smart-16605d5e-c3d2-4f88-9c33-0a3fe633506f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308015774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.1308015774
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1113978373
Short name T468
Test name
Test status
Simulation time 17709772 ps
CPU time 0.54 seconds
Started Jul 13 04:39:17 PM PDT 24
Finished Jul 13 04:39:20 PM PDT 24
Peak memory 181972 kb
Host smart-39f1a0a3-0776-4a29-baef-67ffa0e400de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113978373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1113978373
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.4057339541
Short name T539
Test name
Test status
Simulation time 27736706 ps
CPU time 0.56 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:18 PM PDT 24
Peak memory 182092 kb
Host smart-64648e6f-1467-4388-bf1e-388a14d1aaf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057339541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.4057339541
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.506672909
Short name T546
Test name
Test status
Simulation time 17226703 ps
CPU time 0.59 seconds
Started Jul 13 04:39:32 PM PDT 24
Finished Jul 13 04:39:34 PM PDT 24
Peak memory 182020 kb
Host smart-07a728d1-6915-48b6-8cbc-595b0d6b0029
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506672909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.506672909
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1163550853
Short name T557
Test name
Test status
Simulation time 20659864 ps
CPU time 0.62 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:15 PM PDT 24
Peak memory 182200 kb
Host smart-c9351935-a9f2-4c6e-8d51-83bf0ddd3a96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163550853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1163550853
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.1680168411
Short name T527
Test name
Test status
Simulation time 1838019940 ps
CPU time 3.3 seconds
Started Jul 13 04:39:34 PM PDT 24
Finished Jul 13 04:39:38 PM PDT 24
Peak memory 191760 kb
Host smart-cfc534a6-aa16-48b9-96b6-70cf4b44c1d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680168411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.1680168411
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2918751176
Short name T94
Test name
Test status
Simulation time 58026398 ps
CPU time 0.58 seconds
Started Jul 13 04:39:12 PM PDT 24
Finished Jul 13 04:39:14 PM PDT 24
Peak memory 191392 kb
Host smart-35eeddbb-2630-45e1-9ad0-6f1f7e2b81ef
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918751176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2918751176
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3586861988
Short name T496
Test name
Test status
Simulation time 36641198 ps
CPU time 0.88 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:39:31 PM PDT 24
Peak memory 195884 kb
Host smart-51afe469-4439-4d7d-8e4b-bfb2e0845ac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586861988 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3586861988
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2545794009
Short name T82
Test name
Test status
Simulation time 17563475 ps
CPU time 0.54 seconds
Started Jul 13 04:38:54 PM PDT 24
Finished Jul 13 04:38:57 PM PDT 24
Peak memory 182124 kb
Host smart-e61d54dc-67b0-49bc-b792-2bfbb3d635b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545794009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2545794009
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.142593341
Short name T486
Test name
Test status
Simulation time 14372934 ps
CPU time 0.59 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:29 PM PDT 24
Peak memory 182456 kb
Host smart-d7cadede-a040-4b01-96e5-9562485643d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142593341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.142593341
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.490247199
Short name T99
Test name
Test status
Simulation time 64090232 ps
CPU time 0.63 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:15 PM PDT 24
Peak memory 190892 kb
Host smart-3d34146f-4ecc-4727-981f-78fe313b1304
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490247199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.490247199
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1102107698
Short name T513
Test name
Test status
Simulation time 981830683 ps
CPU time 2.34 seconds
Started Jul 13 04:39:10 PM PDT 24
Finished Jul 13 04:39:13 PM PDT 24
Peak memory 196864 kb
Host smart-d13af928-a8f2-485b-96dd-2149c56c3a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102107698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1102107698
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.643190865
Short name T466
Test name
Test status
Simulation time 226075486 ps
CPU time 0.9 seconds
Started Jul 13 04:38:52 PM PDT 24
Finished Jul 13 04:38:55 PM PDT 24
Peak memory 193008 kb
Host smart-19318eb2-091a-4e1e-8d79-c5b8094328de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643190865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_int
g_err.643190865
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3103415775
Short name T521
Test name
Test status
Simulation time 13095925 ps
CPU time 0.61 seconds
Started Jul 13 04:39:27 PM PDT 24
Finished Jul 13 04:39:32 PM PDT 24
Peak memory 182040 kb
Host smart-9b25b867-167f-4478-b432-4da636a357c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103415775 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3103415775
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.121455901
Short name T465
Test name
Test status
Simulation time 18601038 ps
CPU time 0.54 seconds
Started Jul 13 04:39:23 PM PDT 24
Finished Jul 13 04:39:25 PM PDT 24
Peak memory 182080 kb
Host smart-ad1b8a00-69b9-4797-92dc-af702fddbdd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121455901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.121455901
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.713399753
Short name T548
Test name
Test status
Simulation time 36282720 ps
CPU time 0.53 seconds
Started Jul 13 04:39:21 PM PDT 24
Finished Jul 13 04:39:23 PM PDT 24
Peak memory 182056 kb
Host smart-c57897f4-0919-4858-9b59-2045f2fe9bef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713399753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.713399753
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.3826914994
Short name T566
Test name
Test status
Simulation time 41540135 ps
CPU time 0.55 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:22 PM PDT 24
Peak memory 182040 kb
Host smart-e3799887-25e7-403b-935f-30a84655e190
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826914994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.3826914994
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.519334439
Short name T569
Test name
Test status
Simulation time 13921976 ps
CPU time 0.6 seconds
Started Jul 13 04:39:33 PM PDT 24
Finished Jul 13 04:39:35 PM PDT 24
Peak memory 182052 kb
Host smart-1173d328-daf0-4b50-a17c-a17d68569c81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519334439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.519334439
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3114509400
Short name T458
Test name
Test status
Simulation time 13176630 ps
CPU time 0.54 seconds
Started Jul 13 04:39:19 PM PDT 24
Finished Jul 13 04:39:22 PM PDT 24
Peak memory 181676 kb
Host smart-ec9e7550-629d-4e4d-9444-0ae26a6a9c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114509400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3114509400
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.150462164
Short name T555
Test name
Test status
Simulation time 16123758 ps
CPU time 0.56 seconds
Started Jul 13 04:39:25 PM PDT 24
Finished Jul 13 04:39:27 PM PDT 24
Peak memory 182084 kb
Host smart-7a5f122a-c3ee-4c5e-9570-2241317f8fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150462164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.150462164
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2056826939
Short name T491
Test name
Test status
Simulation time 23962306 ps
CPU time 0.57 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:15 PM PDT 24
Peak memory 181528 kb
Host smart-2ed9e085-b1f4-4696-b332-efce77604bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056826939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2056826939
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3712095185
Short name T553
Test name
Test status
Simulation time 16782977 ps
CPU time 0.53 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:17 PM PDT 24
Peak memory 181516 kb
Host smart-0456f84a-6f76-42f2-bc5e-d70b41d9e817
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712095185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3712095185
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1443854008
Short name T459
Test name
Test status
Simulation time 182530402 ps
CPU time 0.54 seconds
Started Jul 13 04:39:40 PM PDT 24
Finished Jul 13 04:39:43 PM PDT 24
Peak memory 182004 kb
Host smart-72f3df59-bc86-4481-9e77-135ec319adaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443854008 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1443854008
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4234697114
Short name T471
Test name
Test status
Simulation time 34719901 ps
CPU time 0.77 seconds
Started Jul 13 04:39:11 PM PDT 24
Finished Jul 13 04:39:13 PM PDT 24
Peak memory 195316 kb
Host smart-1f392dca-21b5-4fc7-9597-1ef03ff3c1ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234697114 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.4234697114
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2755571005
Short name T51
Test name
Test status
Simulation time 15905242 ps
CPU time 0.56 seconds
Started Jul 13 04:38:57 PM PDT 24
Finished Jul 13 04:38:59 PM PDT 24
Peak memory 182160 kb
Host smart-d08740b8-6cdd-45c8-81af-06d3a6acca07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755571005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2755571005
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.3580895712
Short name T455
Test name
Test status
Simulation time 69982106 ps
CPU time 0.54 seconds
Started Jul 13 04:38:58 PM PDT 24
Finished Jul 13 04:38:59 PM PDT 24
Peak memory 182028 kb
Host smart-f8b41229-e383-4fe6-89bc-43a5fea126e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580895712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.3580895712
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.1003484305
Short name T474
Test name
Test status
Simulation time 78405723 ps
CPU time 0.8 seconds
Started Jul 13 04:39:07 PM PDT 24
Finished Jul 13 04:39:08 PM PDT 24
Peak memory 192900 kb
Host smart-6b48436c-e863-416f-a0a3-346aef22537a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003484305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.1003484305
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.2450459379
Short name T509
Test name
Test status
Simulation time 94761448 ps
CPU time 1.25 seconds
Started Jul 13 04:39:16 PM PDT 24
Finished Jul 13 04:39:20 PM PDT 24
Peak memory 195472 kb
Host smart-528d7162-f263-4f01-961b-b10ff9b57098
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450459379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.2450459379
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.1996265755
Short name T57
Test name
Test status
Simulation time 1647817920 ps
CPU time 1.4 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:17 PM PDT 24
Peak memory 194984 kb
Host smart-ebfcf164-c26e-4a15-bdd1-3301e170e8fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996265755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.1996265755
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3355789671
Short name T454
Test name
Test status
Simulation time 41723292 ps
CPU time 0.71 seconds
Started Jul 13 04:39:02 PM PDT 24
Finished Jul 13 04:39:03 PM PDT 24
Peak memory 194432 kb
Host smart-48d644fd-58a3-4a2d-ba64-29fc5cfacb82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355789671 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3355789671
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.928381271
Short name T559
Test name
Test status
Simulation time 40374395 ps
CPU time 0.65 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:15 PM PDT 24
Peak memory 182172 kb
Host smart-53ccdac9-6f87-4691-97a4-aed21f158e2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928381271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.928381271
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3383530919
Short name T525
Test name
Test status
Simulation time 50575578 ps
CPU time 0.55 seconds
Started Jul 13 04:38:53 PM PDT 24
Finished Jul 13 04:38:55 PM PDT 24
Peak memory 182084 kb
Host smart-f71ca575-c40f-4d2f-a332-03f9e64c798f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383530919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3383530919
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.2358250114
Short name T32
Test name
Test status
Simulation time 68038953 ps
CPU time 0.8 seconds
Started Jul 13 04:39:08 PM PDT 24
Finished Jul 13 04:39:10 PM PDT 24
Peak memory 192892 kb
Host smart-a344ad67-c9bd-4deb-852a-bb45c5ab408e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358250114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.2358250114
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.723079257
Short name T453
Test name
Test status
Simulation time 39015352 ps
CPU time 1.9 seconds
Started Jul 13 04:39:11 PM PDT 24
Finished Jul 13 04:39:13 PM PDT 24
Peak memory 196920 kb
Host smart-3db35bd6-6d26-42fc-9989-f1d948d29ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723079257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.723079257
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1837431829
Short name T535
Test name
Test status
Simulation time 68872437 ps
CPU time 0.88 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:16 PM PDT 24
Peak memory 193008 kb
Host smart-1caf964e-c0f0-4ae9-8191-5f3e22325577
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837431829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1837431829
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.750041844
Short name T460
Test name
Test status
Simulation time 36162264 ps
CPU time 1.67 seconds
Started Jul 13 04:39:06 PM PDT 24
Finished Jul 13 04:39:09 PM PDT 24
Peak memory 196968 kb
Host smart-596388c8-3a7a-4d74-aaee-3dbbaec21773
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750041844 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.750041844
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3977497186
Short name T554
Test name
Test status
Simulation time 15786755 ps
CPU time 0.55 seconds
Started Jul 13 04:39:00 PM PDT 24
Finished Jul 13 04:39:01 PM PDT 24
Peak memory 182120 kb
Host smart-0073758d-16c4-4838-9649-2eb5ed787701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977497186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3977497186
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2405788454
Short name T451
Test name
Test status
Simulation time 13779701 ps
CPU time 0.53 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:19 PM PDT 24
Peak memory 181328 kb
Host smart-e2b5e07c-ebc8-41d4-8237-8804aa29936f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405788454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2405788454
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.4027483123
Short name T507
Test name
Test status
Simulation time 26251329 ps
CPU time 0.71 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:16 PM PDT 24
Peak memory 191064 kb
Host smart-c47d5ad6-21e5-44fd-8803-08f332c6f56b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027483123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.4027483123
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.4064535411
Short name T476
Test name
Test status
Simulation time 114194074 ps
CPU time 1.68 seconds
Started Jul 13 04:38:57 PM PDT 24
Finished Jul 13 04:39:00 PM PDT 24
Peak memory 196892 kb
Host smart-5ebabcd1-6a5b-41e3-98ea-0a11982c14c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064535411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.4064535411
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1273922167
Short name T101
Test name
Test status
Simulation time 189886917 ps
CPU time 1.35 seconds
Started Jul 13 04:38:52 PM PDT 24
Finished Jul 13 04:38:56 PM PDT 24
Peak memory 182728 kb
Host smart-4f385c35-a977-47fb-94e9-974b6fa0a1c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273922167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1273922167
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3585791493
Short name T531
Test name
Test status
Simulation time 25290412 ps
CPU time 0.99 seconds
Started Jul 13 04:39:13 PM PDT 24
Finished Jul 13 04:39:16 PM PDT 24
Peak memory 196820 kb
Host smart-1120736e-de83-4177-a156-9ed0b2b9eedd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585791493 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3585791493
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1261248475
Short name T515
Test name
Test status
Simulation time 31913737 ps
CPU time 0.6 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:19 PM PDT 24
Peak memory 182172 kb
Host smart-08d08cc6-7e2d-49e6-ae89-e7a21cc29a5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261248475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1261248475
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1549078084
Short name T570
Test name
Test status
Simulation time 14309190 ps
CPU time 0.54 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:16 PM PDT 24
Peak memory 182072 kb
Host smart-cda3090b-11d6-49a8-8de6-b615d073dcf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549078084 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1549078084
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3450478989
Short name T503
Test name
Test status
Simulation time 71913337 ps
CPU time 0.78 seconds
Started Jul 13 04:39:12 PM PDT 24
Finished Jul 13 04:39:14 PM PDT 24
Peak memory 191112 kb
Host smart-870e847b-3493-480c-bfae-8926a24421cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450478989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3450478989
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3794241532
Short name T497
Test name
Test status
Simulation time 496543952 ps
CPU time 2.54 seconds
Started Jul 13 04:38:54 PM PDT 24
Finished Jul 13 04:38:58 PM PDT 24
Peak memory 196956 kb
Host smart-c9326efb-2a9e-48bb-8f85-a2166cdfc0e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794241532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3794241532
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.357895408
Short name T480
Test name
Test status
Simulation time 66768957 ps
CPU time 0.81 seconds
Started Jul 13 04:39:02 PM PDT 24
Finished Jul 13 04:39:04 PM PDT 24
Peak memory 182516 kb
Host smart-4ec9693d-011e-44b3-929e-3571fb299ab4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357895408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_int
g_err.357895408
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.871277322
Short name T501
Test name
Test status
Simulation time 36223675 ps
CPU time 0.87 seconds
Started Jul 13 04:39:35 PM PDT 24
Finished Jul 13 04:39:37 PM PDT 24
Peak memory 196456 kb
Host smart-bec53218-6591-4569-9899-e63f18f72868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871277322 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.871277322
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.318409376
Short name T88
Test name
Test status
Simulation time 11240669 ps
CPU time 0.59 seconds
Started Jul 13 04:39:09 PM PDT 24
Finished Jul 13 04:39:10 PM PDT 24
Peak memory 182168 kb
Host smart-2ebc8fe7-4b43-4619-b49e-fe4c18f99849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318409376 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.318409376
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4131495053
Short name T493
Test name
Test status
Simulation time 14637255 ps
CPU time 0.58 seconds
Started Jul 13 04:39:16 PM PDT 24
Finished Jul 13 04:39:20 PM PDT 24
Peak memory 182076 kb
Host smart-b15045b1-20a0-4572-a0f3-8d85d1e06d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131495053 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4131495053
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2743625261
Short name T52
Test name
Test status
Simulation time 27685532 ps
CPU time 0.71 seconds
Started Jul 13 04:39:14 PM PDT 24
Finished Jul 13 04:39:16 PM PDT 24
Peak memory 190908 kb
Host smart-907b5560-a65e-4310-a91e-d676c428fc69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743625261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2743625261
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.23122453
Short name T483
Test name
Test status
Simulation time 407177149 ps
CPU time 1.42 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:20 PM PDT 24
Peak memory 196612 kb
Host smart-fe17721f-a425-4719-80d6-692c0bd61c2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23122453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.23122453
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.767573839
Short name T545
Test name
Test status
Simulation time 629146449 ps
CPU time 1.07 seconds
Started Jul 13 04:39:15 PM PDT 24
Finished Jul 13 04:39:19 PM PDT 24
Peak memory 193584 kb
Host smart-6104a7e7-2073-4526-a754-d1d91554d412
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767573839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.767573839
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3187762660
Short name T259
Test name
Test status
Simulation time 138898340779 ps
CPU time 205.01 seconds
Started Jul 13 05:52:39 PM PDT 24
Finished Jul 13 05:56:05 PM PDT 24
Peak memory 183052 kb
Host smart-7efc98b8-099d-40fe-b350-d843bbb5b542
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187762660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3187762660
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2841818203
Short name T48
Test name
Test status
Simulation time 66961882268 ps
CPU time 104.7 seconds
Started Jul 13 05:52:38 PM PDT 24
Finished Jul 13 05:54:23 PM PDT 24
Peak memory 183136 kb
Host smart-2c7dbea3-8893-4663-9c4d-3d786a1d723a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841818203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2841818203
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.3531898446
Short name T147
Test name
Test status
Simulation time 686460404859 ps
CPU time 724.63 seconds
Started Jul 13 05:52:37 PM PDT 24
Finished Jul 13 06:04:42 PM PDT 24
Peak memory 191220 kb
Host smart-d961b407-83c8-4836-a87e-73f9ace9dc0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531898446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.3531898446
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2539080610
Short name T205
Test name
Test status
Simulation time 88568697961 ps
CPU time 905.75 seconds
Started Jul 13 05:52:38 PM PDT 24
Finished Jul 13 06:07:45 PM PDT 24
Peak memory 191304 kb
Host smart-adf370f9-1ee2-4601-8624-fc856b32fd26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539080610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2539080610
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.716171528
Short name T366
Test name
Test status
Simulation time 201999181341 ps
CPU time 259.69 seconds
Started Jul 13 05:52:43 PM PDT 24
Finished Jul 13 05:57:03 PM PDT 24
Peak memory 183112 kb
Host smart-8775492b-867e-4e82-9267-959b284afab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716171528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.716171528
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.173701613
Short name T235
Test name
Test status
Simulation time 106072693160 ps
CPU time 255.81 seconds
Started Jul 13 05:52:38 PM PDT 24
Finished Jul 13 05:56:54 PM PDT 24
Peak memory 191256 kb
Host smart-54dee74a-b9a4-4248-8d4f-35a20a060983
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173701613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.173701613
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.1837880347
Short name T232
Test name
Test status
Simulation time 103027598435 ps
CPU time 51.57 seconds
Started Jul 13 05:52:38 PM PDT 24
Finished Jul 13 05:53:30 PM PDT 24
Peak memory 183044 kb
Host smart-8b4d3e26-6b1f-42cf-9964-3fec137cda12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837880347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.1837880347
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1907171385
Short name T17
Test name
Test status
Simulation time 60756586 ps
CPU time 0.86 seconds
Started Jul 13 05:52:37 PM PDT 24
Finished Jul 13 05:52:38 PM PDT 24
Peak memory 213400 kb
Host smart-201b8bc7-cd23-41ff-ba61-0d975ceca324
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907171385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1907171385
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.1400504916
Short name T11
Test name
Test status
Simulation time 17497633789 ps
CPU time 121.43 seconds
Started Jul 13 05:52:40 PM PDT 24
Finished Jul 13 05:54:42 PM PDT 24
Peak memory 197800 kb
Host smart-2c4bdfc7-6dfa-4cde-8449-13e6eacea37f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400504916 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.1400504916
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.1929253365
Short name T248
Test name
Test status
Simulation time 902966990443 ps
CPU time 385.23 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:59:32 PM PDT 24
Peak memory 183032 kb
Host smart-9c48928a-d868-46c9-92bd-964234f757de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929253365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.1929253365
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3205572497
Short name T365
Test name
Test status
Simulation time 852736100473 ps
CPU time 194.32 seconds
Started Jul 13 05:53:03 PM PDT 24
Finished Jul 13 05:56:18 PM PDT 24
Peak memory 183032 kb
Host smart-a6281f4b-99fe-4ff5-8d0c-c50cc0b6f03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205572497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3205572497
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/100.rv_timer_random.1151636955
Short name T426
Test name
Test status
Simulation time 98423547867 ps
CPU time 91.17 seconds
Started Jul 13 05:53:45 PM PDT 24
Finished Jul 13 05:55:16 PM PDT 24
Peak memory 191248 kb
Host smart-ad591058-8b6f-446e-acad-3d908f7edafa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151636955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1151636955
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.2525777552
Short name T130
Test name
Test status
Simulation time 75640532822 ps
CPU time 125.33 seconds
Started Jul 13 05:53:45 PM PDT 24
Finished Jul 13 05:55:51 PM PDT 24
Peak memory 191332 kb
Host smart-1544de66-4fb5-4810-b194-bc85c8533b58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525777552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.2525777552
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1614915397
Short name T58
Test name
Test status
Simulation time 119318597581 ps
CPU time 201.43 seconds
Started Jul 13 05:53:56 PM PDT 24
Finished Jul 13 05:57:18 PM PDT 24
Peak memory 190852 kb
Host smart-73da10e9-e82a-4de2-a442-1d613e3b08b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614915397 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1614915397
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3475387986
Short name T157
Test name
Test status
Simulation time 406844399058 ps
CPU time 893.95 seconds
Started Jul 13 05:53:45 PM PDT 24
Finished Jul 13 06:08:40 PM PDT 24
Peak memory 191260 kb
Host smart-0c9b6d3f-d444-4f9c-a9bb-88721380fe4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475387986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3475387986
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.283907728
Short name T210
Test name
Test status
Simulation time 267041151938 ps
CPU time 228.32 seconds
Started Jul 13 05:53:44 PM PDT 24
Finished Jul 13 05:57:33 PM PDT 24
Peak memory 191324 kb
Host smart-d50fbc28-9524-4d7b-982f-4c310dfd51ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283907728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.283907728
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.1315721239
Short name T206
Test name
Test status
Simulation time 33862650930 ps
CPU time 17.64 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:53:25 PM PDT 24
Peak memory 183096 kb
Host smart-be0aa0c5-8e78-4a88-9d01-d04df2db5f5d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315721239 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.1315721239
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3131513704
Short name T368
Test name
Test status
Simulation time 461621856610 ps
CPU time 195.87 seconds
Started Jul 13 05:53:07 PM PDT 24
Finished Jul 13 05:56:24 PM PDT 24
Peak memory 183104 kb
Host smart-5013a2c9-cebe-4a5d-8286-8102352bd29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131513704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3131513704
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2080633280
Short name T306
Test name
Test status
Simulation time 102160595778 ps
CPU time 90.88 seconds
Started Jul 13 05:53:03 PM PDT 24
Finished Jul 13 05:54:35 PM PDT 24
Peak memory 195068 kb
Host smart-b24b3845-3bdb-435a-b2b3-c2134af94e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080633280 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2080633280
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all_with_rand_reset.29118539
Short name T12
Test name
Test status
Simulation time 63885514019 ps
CPU time 667.49 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 06:04:15 PM PDT 24
Peak memory 213356 kb
Host smart-cf7f4140-9860-495f-a93d-8d08a7ecc385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29118539 -assert nopos
tproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all_with_rand_reset.29118539
Directory /workspace/11.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.3693730272
Short name T327
Test name
Test status
Simulation time 2039955264 ps
CPU time 24.76 seconds
Started Jul 13 05:53:52 PM PDT 24
Finished Jul 13 05:54:17 PM PDT 24
Peak memory 182976 kb
Host smart-406f05ac-c027-46b5-8b70-cf8c565b560f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693730272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.3693730272
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.800116651
Short name T408
Test name
Test status
Simulation time 10636502231 ps
CPU time 7.9 seconds
Started Jul 13 05:53:51 PM PDT 24
Finished Jul 13 05:54:00 PM PDT 24
Peak memory 183124 kb
Host smart-e4732146-f564-459b-a9f4-bdd1826b319b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800116651 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.800116651
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.1717979588
Short name T202
Test name
Test status
Simulation time 85814880715 ps
CPU time 131.77 seconds
Started Jul 13 05:53:52 PM PDT 24
Finished Jul 13 05:56:04 PM PDT 24
Peak memory 183132 kb
Host smart-b946f61b-60f5-4bc5-8a5b-762244c7b35f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717979588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.1717979588
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.2074540195
Short name T290
Test name
Test status
Simulation time 157362419056 ps
CPU time 117.59 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 05:55:57 PM PDT 24
Peak memory 191256 kb
Host smart-c1300c02-e386-4ed9-8049-21fbab8a912f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074540195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.2074540195
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.410475443
Short name T393
Test name
Test status
Simulation time 96053739688 ps
CPU time 1720.16 seconds
Started Jul 13 05:53:53 PM PDT 24
Finished Jul 13 06:22:33 PM PDT 24
Peak memory 191300 kb
Host smart-47fc1b60-1162-4ab8-a942-0f931353051c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410475443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.410475443
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.2909145626
Short name T407
Test name
Test status
Simulation time 8377323220 ps
CPU time 14.23 seconds
Started Jul 13 05:53:02 PM PDT 24
Finished Jul 13 05:53:17 PM PDT 24
Peak memory 183048 kb
Host smart-976aa592-1264-49e0-86e7-a8d763def1d4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909145626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.2909145626
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2298804182
Short name T81
Test name
Test status
Simulation time 46099496175 ps
CPU time 19.71 seconds
Started Jul 13 05:53:03 PM PDT 24
Finished Jul 13 05:53:24 PM PDT 24
Peak memory 183324 kb
Host smart-4528854d-95c8-4f9e-b151-87995a619e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298804182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2298804182
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.4250813641
Short name T194
Test name
Test status
Simulation time 229110630933 ps
CPU time 1206.17 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 06:13:13 PM PDT 24
Peak memory 193392 kb
Host smart-c991a84c-6991-46ad-ab28-93d4dfd31a71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250813641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.4250813641
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.1731416126
Short name T21
Test name
Test status
Simulation time 24094506903 ps
CPU time 41.09 seconds
Started Jul 13 05:53:02 PM PDT 24
Finished Jul 13 05:53:44 PM PDT 24
Peak memory 183140 kb
Host smart-97647060-07a0-4169-9861-5000560015f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731416126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.1731416126
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.781116015
Short name T76
Test name
Test status
Simulation time 603233469095 ps
CPU time 2465.19 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 06:34:12 PM PDT 24
Peak memory 191164 kb
Host smart-e37767f0-f05b-46ba-bccd-6adf3a589bd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781116015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all.
781116015
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/120.rv_timer_random.3619820870
Short name T431
Test name
Test status
Simulation time 8638267101 ps
CPU time 15.66 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 05:54:16 PM PDT 24
Peak memory 183056 kb
Host smart-5b182d4a-4192-4f4f-9ad7-ea4299eee82c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619820870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3619820870
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.1326273691
Short name T19
Test name
Test status
Simulation time 24097997327 ps
CPU time 37.8 seconds
Started Jul 13 05:53:52 PM PDT 24
Finished Jul 13 05:54:31 PM PDT 24
Peak memory 183124 kb
Host smart-e9e275b2-c9ed-43c7-a8df-3e2176ba966f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326273691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.1326273691
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.4154937616
Short name T140
Test name
Test status
Simulation time 61813173335 ps
CPU time 91.77 seconds
Started Jul 13 05:53:58 PM PDT 24
Finished Jul 13 05:55:31 PM PDT 24
Peak memory 191220 kb
Host smart-03f97bfe-c296-4479-980c-b3bfba9366d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154937616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.4154937616
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.757664885
Short name T294
Test name
Test status
Simulation time 165408792020 ps
CPU time 1670.01 seconds
Started Jul 13 05:53:58 PM PDT 24
Finished Jul 13 06:21:48 PM PDT 24
Peak memory 191332 kb
Host smart-ba2fd04d-e92d-44a7-832c-35864acd7f9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757664885 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.757664885
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1251796026
Short name T133
Test name
Test status
Simulation time 443019030824 ps
CPU time 476.52 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 06:01:57 PM PDT 24
Peak memory 191300 kb
Host smart-7e3c112c-55f8-4471-a1ef-7d48d1867479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251796026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1251796026
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.869479107
Short name T200
Test name
Test status
Simulation time 992071322267 ps
CPU time 1514.43 seconds
Started Jul 13 05:53:58 PM PDT 24
Finished Jul 13 06:19:14 PM PDT 24
Peak memory 191332 kb
Host smart-c039c89e-4534-4bfc-a545-789507f39df4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869479107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.869479107
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.2219046199
Short name T405
Test name
Test status
Simulation time 69944604736 ps
CPU time 72.81 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 05:55:13 PM PDT 24
Peak memory 183060 kb
Host smart-0dc56b0f-b48d-4600-8c6c-64744900320e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219046199 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.2219046199
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2737352519
Short name T348
Test name
Test status
Simulation time 541695329267 ps
CPU time 245.02 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:57:12 PM PDT 24
Peak memory 183084 kb
Host smart-9cca5598-13f2-4cb2-9e01-a819dc23cf94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737352519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2737352519
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.608857883
Short name T49
Test name
Test status
Simulation time 342306461774 ps
CPU time 256.38 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:57:23 PM PDT 24
Peak memory 183112 kb
Host smart-e909014f-3e34-465a-8ab8-1ce8e3ffb375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608857883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.608857883
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.4175068580
Short name T164
Test name
Test status
Simulation time 134081002186 ps
CPU time 274.41 seconds
Started Jul 13 05:53:06 PM PDT 24
Finished Jul 13 05:57:42 PM PDT 24
Peak memory 190768 kb
Host smart-55f5395d-2d7d-45f4-baec-0209be3abc2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175068580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.4175068580
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.653532125
Short name T394
Test name
Test status
Simulation time 109191552792 ps
CPU time 46.88 seconds
Started Jul 13 05:53:03 PM PDT 24
Finished Jul 13 05:53:51 PM PDT 24
Peak memory 191304 kb
Host smart-e4017a6d-8851-455b-9aeb-c4795d056194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653532125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.653532125
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.3254304152
Short name T337
Test name
Test status
Simulation time 18248785572 ps
CPU time 72.38 seconds
Started Jul 13 05:54:00 PM PDT 24
Finished Jul 13 05:55:13 PM PDT 24
Peak memory 183128 kb
Host smart-9f11763e-c0d4-48d2-87c7-57755c79e7ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254304152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.3254304152
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1097700071
Short name T127
Test name
Test status
Simulation time 17774697182 ps
CPU time 404.89 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 06:00:45 PM PDT 24
Peak memory 193944 kb
Host smart-b14e4be0-b067-4d09-9a87-b2e40005f064
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097700071 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1097700071
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.590718533
Short name T331
Test name
Test status
Simulation time 1068402595413 ps
CPU time 2008.47 seconds
Started Jul 13 05:54:01 PM PDT 24
Finished Jul 13 06:27:30 PM PDT 24
Peak memory 191276 kb
Host smart-5a8cde6a-e060-4ac0-a6f7-9db328332578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590718533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.590718533
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.950579729
Short name T285
Test name
Test status
Simulation time 236841344534 ps
CPU time 830.17 seconds
Started Jul 13 05:53:58 PM PDT 24
Finished Jul 13 06:07:48 PM PDT 24
Peak memory 191324 kb
Host smart-48385a1d-4577-4cc0-b570-cdea3305ef2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950579729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.950579729
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.2383049507
Short name T104
Test name
Test status
Simulation time 37595539592 ps
CPU time 288.54 seconds
Started Jul 13 05:53:59 PM PDT 24
Finished Jul 13 05:58:49 PM PDT 24
Peak memory 183124 kb
Host smart-46fb4851-42d6-4851-bfb1-7b79d94f7474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383049507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.2383049507
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3113994038
Short name T440
Test name
Test status
Simulation time 334336514099 ps
CPU time 1457.14 seconds
Started Jul 13 05:53:58 PM PDT 24
Finished Jul 13 06:18:16 PM PDT 24
Peak memory 191324 kb
Host smart-5d50248b-c319-4167-ba69-e58e09b479ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113994038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3113994038
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1427116768
Short name T168
Test name
Test status
Simulation time 2003053964773 ps
CPU time 1363.51 seconds
Started Jul 13 05:54:06 PM PDT 24
Finished Jul 13 06:16:50 PM PDT 24
Peak memory 191328 kb
Host smart-3d12cc49-786b-4486-a4e4-805abed5c715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427116768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1427116768
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2271972010
Short name T418
Test name
Test status
Simulation time 35784530277 ps
CPU time 210.76 seconds
Started Jul 13 05:54:06 PM PDT 24
Finished Jul 13 05:57:37 PM PDT 24
Peak memory 183124 kb
Host smart-5b1b2d7b-1777-49df-a895-b277a9f7264a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271972010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2271972010
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2878694213
Short name T174
Test name
Test status
Simulation time 88441730135 ps
CPU time 87.81 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:54:35 PM PDT 24
Peak memory 183056 kb
Host smart-f75ff7fb-afe1-47ae-bf87-a2fc613aaa33
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878694213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2878694213
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2350525815
Short name T375
Test name
Test status
Simulation time 197135604812 ps
CPU time 305.93 seconds
Started Jul 13 05:53:02 PM PDT 24
Finished Jul 13 05:58:09 PM PDT 24
Peak memory 183132 kb
Host smart-df8a645f-6f98-46ab-abf3-f26e09dfeacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350525815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2350525815
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.4074359816
Short name T146
Test name
Test status
Simulation time 328587133535 ps
CPU time 773.66 seconds
Started Jul 13 05:53:03 PM PDT 24
Finished Jul 13 06:05:57 PM PDT 24
Peak memory 194024 kb
Host smart-6c53d72c-ad80-41f1-85bf-d5a4ce650a2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074359816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.4074359816
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3237422332
Short name T5
Test name
Test status
Simulation time 61730995 ps
CPU time 0.63 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:53:08 PM PDT 24
Peak memory 182940 kb
Host smart-61480c0e-21a1-4f86-b44f-d69b3f4d784e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237422332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3237422332
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.443103383
Short name T75
Test name
Test status
Simulation time 192386227781 ps
CPU time 569.92 seconds
Started Jul 13 05:53:02 PM PDT 24
Finished Jul 13 06:02:32 PM PDT 24
Peak memory 194880 kb
Host smart-5cb309aa-6101-4be1-8b86-b45b9ac7a2ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443103383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
443103383
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/140.rv_timer_random.746193791
Short name T266
Test name
Test status
Simulation time 93569509367 ps
CPU time 174.75 seconds
Started Jul 13 05:54:07 PM PDT 24
Finished Jul 13 05:57:03 PM PDT 24
Peak memory 191300 kb
Host smart-5c3e11b9-d6a6-4c36-beff-585d4e533dbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746193791 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.746193791
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.73155034
Short name T336
Test name
Test status
Simulation time 415104717956 ps
CPU time 540.59 seconds
Started Jul 13 05:54:07 PM PDT 24
Finished Jul 13 06:03:08 PM PDT 24
Peak memory 191312 kb
Host smart-78afe050-5ee8-4374-bb12-b1ffec39caf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73155034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.73155034
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3017239894
Short name T213
Test name
Test status
Simulation time 140192927252 ps
CPU time 774.78 seconds
Started Jul 13 05:54:07 PM PDT 24
Finished Jul 13 06:07:02 PM PDT 24
Peak memory 192352 kb
Host smart-fad72874-b873-403c-80da-7ae455efdcfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017239894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3017239894
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.190502176
Short name T179
Test name
Test status
Simulation time 107482245199 ps
CPU time 474.24 seconds
Started Jul 13 05:54:05 PM PDT 24
Finished Jul 13 06:02:00 PM PDT 24
Peak memory 191220 kb
Host smart-3b96f258-2473-4602-99c9-6d76ea7123c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190502176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.190502176
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.4118665788
Short name T373
Test name
Test status
Simulation time 42702551710 ps
CPU time 74 seconds
Started Jul 13 05:54:07 PM PDT 24
Finished Jul 13 05:55:22 PM PDT 24
Peak memory 183100 kb
Host smart-ff5ae3f9-5bd8-4b8a-875d-371da2adc12b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118665788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.4118665788
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.4131116756
Short name T332
Test name
Test status
Simulation time 59958875615 ps
CPU time 54.52 seconds
Started Jul 13 05:54:09 PM PDT 24
Finished Jul 13 05:55:03 PM PDT 24
Peak memory 191300 kb
Host smart-2bdbf0f9-8bd7-4dc2-b4ed-7a65cc8b2041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131116756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.4131116756
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3664269334
Short name T217
Test name
Test status
Simulation time 302158736429 ps
CPU time 178.26 seconds
Started Jul 13 05:54:08 PM PDT 24
Finished Jul 13 05:57:06 PM PDT 24
Peak memory 191300 kb
Host smart-6311f868-e7cf-40a2-905b-0a87e84cd7c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664269334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3664269334
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.4102235556
Short name T118
Test name
Test status
Simulation time 151998053680 ps
CPU time 71.86 seconds
Started Jul 13 05:54:12 PM PDT 24
Finished Jul 13 05:55:24 PM PDT 24
Peak memory 183048 kb
Host smart-1c460383-c094-4386-a1d8-3cd7105b89a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102235556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.4102235556
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1543969273
Short name T239
Test name
Test status
Simulation time 474200807060 ps
CPU time 668.26 seconds
Started Jul 13 05:54:14 PM PDT 24
Finished Jul 13 06:05:23 PM PDT 24
Peak memory 191260 kb
Host smart-d7ebc19d-a091-4cf8-86c0-0d85e51a5bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543969273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1543969273
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.500316359
Short name T201
Test name
Test status
Simulation time 61112866295 ps
CPU time 109.21 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:54:57 PM PDT 24
Peak memory 183096 kb
Host smart-15dd307c-f4bb-4ed8-ac4b-f87efc269797
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500316359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.rv_timer_cfg_update_on_fly.500316359
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.450595894
Short name T441
Test name
Test status
Simulation time 34497366091 ps
CPU time 48.89 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 05:53:54 PM PDT 24
Peak memory 183068 kb
Host smart-f950452c-faee-438f-bfcf-b39f6fc4fc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450595894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.450595894
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.2599495861
Short name T26
Test name
Test status
Simulation time 54270966941 ps
CPU time 74.16 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:54:21 PM PDT 24
Peak memory 191332 kb
Host smart-82e15d2d-9e6c-4a82-8084-db8f699d9fd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599495861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.2599495861
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.689575196
Short name T183
Test name
Test status
Simulation time 157930940392 ps
CPU time 654.11 seconds
Started Jul 13 05:53:01 PM PDT 24
Finished Jul 13 06:03:56 PM PDT 24
Peak memory 191316 kb
Host smart-e21014a9-bd0f-4c5d-8de1-5a577ccf4cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689575196 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.689575196
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.440607530
Short name T296
Test name
Test status
Simulation time 86070967923 ps
CPU time 167.46 seconds
Started Jul 13 05:54:18 PM PDT 24
Finished Jul 13 05:57:06 PM PDT 24
Peak memory 191332 kb
Host smart-70f0b0fa-d6fa-455d-8e73-ce936504aa6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440607530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.440607530
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3549864790
Short name T321
Test name
Test status
Simulation time 54202286585 ps
CPU time 51.12 seconds
Started Jul 13 05:54:15 PM PDT 24
Finished Jul 13 05:55:06 PM PDT 24
Peak memory 191320 kb
Host smart-daa8fba6-8624-4ac5-9625-e1e35d5c31af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549864790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3549864790
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2546739268
Short name T145
Test name
Test status
Simulation time 221954349683 ps
CPU time 117.3 seconds
Started Jul 13 05:54:17 PM PDT 24
Finished Jul 13 05:56:15 PM PDT 24
Peak memory 191340 kb
Host smart-f8067db0-db3a-4dc7-a054-252adc542ddb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546739268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2546739268
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1655346692
Short name T254
Test name
Test status
Simulation time 195875899347 ps
CPU time 653.65 seconds
Started Jul 13 05:54:17 PM PDT 24
Finished Jul 13 06:05:11 PM PDT 24
Peak memory 194328 kb
Host smart-793a73b3-ffd3-4fc9-ba27-dc2060bbb857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655346692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1655346692
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3594906534
Short name T391
Test name
Test status
Simulation time 146747905 ps
CPU time 0.91 seconds
Started Jul 13 05:54:16 PM PDT 24
Finished Jul 13 05:54:17 PM PDT 24
Peak memory 183176 kb
Host smart-92b8d327-5fed-4cb1-b8f7-266c047779c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594906534 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3594906534
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.28768560
Short name T188
Test name
Test status
Simulation time 376928337802 ps
CPU time 42.19 seconds
Started Jul 13 05:54:13 PM PDT 24
Finished Jul 13 05:54:55 PM PDT 24
Peak memory 183036 kb
Host smart-254f4753-b07a-46a5-8977-82ee8c09b191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28768560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.28768560
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.1669408527
Short name T272
Test name
Test status
Simulation time 167188159443 ps
CPU time 189.13 seconds
Started Jul 13 05:54:13 PM PDT 24
Finished Jul 13 05:57:23 PM PDT 24
Peak memory 191300 kb
Host smart-584868d7-d125-4999-a250-9b776c50027b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669408527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.1669408527
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3337887705
Short name T109
Test name
Test status
Simulation time 568660794742 ps
CPU time 696.84 seconds
Started Jul 13 05:54:18 PM PDT 24
Finished Jul 13 06:05:56 PM PDT 24
Peak memory 191340 kb
Host smart-e17aece6-8251-4171-8889-0290e8461101
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337887705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3337887705
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3849328724
Short name T270
Test name
Test status
Simulation time 29946012386 ps
CPU time 53.15 seconds
Started Jul 13 05:54:15 PM PDT 24
Finished Jul 13 05:55:08 PM PDT 24
Peak memory 183104 kb
Host smart-caed31d8-f35e-482b-a01b-dd56e0a343fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849328724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3849328724
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1003634315
Short name T271
Test name
Test status
Simulation time 112448863992 ps
CPU time 177.3 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:56:04 PM PDT 24
Peak memory 182932 kb
Host smart-52f57f5d-9354-4446-ad2f-093aeb584d08
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003634315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1003634315
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.626359425
Short name T417
Test name
Test status
Simulation time 46891612809 ps
CPU time 58.04 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:54:04 PM PDT 24
Peak memory 183108 kb
Host smart-ce56e669-c6ec-424a-bb34-eb50378ff27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626359425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.626359425
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1328015471
Short name T291
Test name
Test status
Simulation time 302219962661 ps
CPU time 102.08 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 05:54:48 PM PDT 24
Peak memory 193804 kb
Host smart-6660c461-0901-49eb-a81b-de85c5357ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328015471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1328015471
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.1745045986
Short name T420
Test name
Test status
Simulation time 142025072817 ps
CPU time 59.01 seconds
Started Jul 13 05:54:20 PM PDT 24
Finished Jul 13 05:55:20 PM PDT 24
Peak memory 183092 kb
Host smart-3ad05949-8bfa-42d4-908b-c56f5cf1c79b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745045986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1745045986
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1941785388
Short name T172
Test name
Test status
Simulation time 139853419722 ps
CPU time 384.09 seconds
Started Jul 13 05:54:21 PM PDT 24
Finished Jul 13 06:00:46 PM PDT 24
Peak memory 191300 kb
Host smart-a4fe8937-edbf-443c-ab43-516eacbcc7c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941785388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1941785388
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2905018150
Short name T167
Test name
Test status
Simulation time 279713100401 ps
CPU time 592.09 seconds
Started Jul 13 05:54:22 PM PDT 24
Finished Jul 13 06:04:15 PM PDT 24
Peak memory 191320 kb
Host smart-e3cc7cd7-90ab-4906-b05b-46fe9c51d2c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905018150 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2905018150
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.386163906
Short name T267
Test name
Test status
Simulation time 76752726203 ps
CPU time 285.45 seconds
Started Jul 13 05:54:20 PM PDT 24
Finished Jul 13 05:59:06 PM PDT 24
Peak memory 183132 kb
Host smart-4ee9f128-5931-44ee-b5cc-f83d50bde46d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386163906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.386163906
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2659096177
Short name T171
Test name
Test status
Simulation time 67998340946 ps
CPU time 50.49 seconds
Started Jul 13 05:54:20 PM PDT 24
Finished Jul 13 05:55:11 PM PDT 24
Peak memory 182888 kb
Host smart-e225a0ed-eb71-41d7-83b2-c76b555609dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659096177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2659096177
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.2127208118
Short name T310
Test name
Test status
Simulation time 12114249642 ps
CPU time 17.79 seconds
Started Jul 13 05:54:20 PM PDT 24
Finished Jul 13 05:54:38 PM PDT 24
Peak memory 183120 kb
Host smart-cd0c29a4-4081-4c6b-a268-3624e5af2622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127208118 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.2127208118
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2790306307
Short name T180
Test name
Test status
Simulation time 1520857611622 ps
CPU time 1582.15 seconds
Started Jul 13 05:54:21 PM PDT 24
Finished Jul 13 06:20:44 PM PDT 24
Peak memory 193372 kb
Host smart-e64f43a2-4f52-47f3-8e1f-79057cdf46ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790306307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2790306307
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2464892043
Short name T423
Test name
Test status
Simulation time 609679638424 ps
CPU time 84.05 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:54:31 PM PDT 24
Peak memory 183108 kb
Host smart-b1cfd1a7-50d8-4020-a5be-ebbc260fec01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464892043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2464892043
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.841778061
Short name T136
Test name
Test status
Simulation time 137136859714 ps
CPU time 84.48 seconds
Started Jul 13 05:53:03 PM PDT 24
Finished Jul 13 05:54:29 PM PDT 24
Peak memory 191324 kb
Host smart-381b889f-e37e-4261-abea-21d71067289b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841778061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.841778061
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/171.rv_timer_random.2577678330
Short name T442
Test name
Test status
Simulation time 30370363873 ps
CPU time 23.81 seconds
Started Jul 13 05:54:27 PM PDT 24
Finished Jul 13 05:54:51 PM PDT 24
Peak memory 183092 kb
Host smart-4e66bae2-2eb6-490e-8fb6-11fe1b54cd94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577678330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.2577678330
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.134884076
Short name T221
Test name
Test status
Simulation time 91639715731 ps
CPU time 67.22 seconds
Started Jul 13 05:54:26 PM PDT 24
Finished Jul 13 05:55:33 PM PDT 24
Peak memory 182988 kb
Host smart-22006737-aeea-4bad-b5d5-49f06d9e5988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134884076 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.134884076
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.4062099198
Short name T344
Test name
Test status
Simulation time 41365322838 ps
CPU time 62.82 seconds
Started Jul 13 05:54:29 PM PDT 24
Finished Jul 13 05:55:32 PM PDT 24
Peak memory 183132 kb
Host smart-05425c8c-91c7-48d8-9195-9a7d849d54a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062099198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.4062099198
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.1606064055
Short name T129
Test name
Test status
Simulation time 787482305532 ps
CPU time 1381.42 seconds
Started Jul 13 05:54:28 PM PDT 24
Finished Jul 13 06:17:30 PM PDT 24
Peak memory 191332 kb
Host smart-c347c004-557f-4ef3-a6dc-6a1b63dd0711
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606064055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.1606064055
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3758850352
Short name T269
Test name
Test status
Simulation time 46192852059 ps
CPU time 95.23 seconds
Started Jul 13 05:54:29 PM PDT 24
Finished Jul 13 05:56:04 PM PDT 24
Peak memory 183020 kb
Host smart-8693214e-295e-47d4-bc4e-21cb1387cfc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758850352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3758850352
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2613806306
Short name T425
Test name
Test status
Simulation time 146727404782 ps
CPU time 144.68 seconds
Started Jul 13 05:54:27 PM PDT 24
Finished Jul 13 05:56:52 PM PDT 24
Peak memory 183132 kb
Host smart-32a225c8-0fe5-4050-9c3f-6b87f8a8cdb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613806306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2613806306
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3871251912
Short name T299
Test name
Test status
Simulation time 95452010892 ps
CPU time 134.44 seconds
Started Jul 13 05:54:26 PM PDT 24
Finished Jul 13 05:56:41 PM PDT 24
Peak memory 194720 kb
Host smart-c068d8e9-ab96-416c-a773-f8881259a053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871251912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3871251912
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.217940170
Short name T439
Test name
Test status
Simulation time 1091349989339 ps
CPU time 658.45 seconds
Started Jul 13 05:54:26 PM PDT 24
Finished Jul 13 06:05:25 PM PDT 24
Peak memory 191300 kb
Host smart-7e2538b9-b7d0-491f-8510-3c52dc9dfcf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217940170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.217940170
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.445252316
Short name T150
Test name
Test status
Simulation time 704926713866 ps
CPU time 635.04 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 06:03:41 PM PDT 24
Peak memory 183096 kb
Host smart-57b3c187-81f9-4bec-b5c8-79f2b3ecd9c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445252316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.rv_timer_cfg_update_on_fly.445252316
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.383947436
Short name T384
Test name
Test status
Simulation time 52186364066 ps
CPU time 20.52 seconds
Started Jul 13 05:53:06 PM PDT 24
Finished Jul 13 05:53:28 PM PDT 24
Peak memory 183104 kb
Host smart-6ab13986-01d6-4a25-afb8-248583cda756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383947436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.383947436
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.1468757522
Short name T318
Test name
Test status
Simulation time 129272210339 ps
CPU time 74.03 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:54:22 PM PDT 24
Peak memory 191324 kb
Host smart-f10df6f6-9aa4-43a0-8771-687a9d275e71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468757522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.1468757522
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3247843245
Short name T347
Test name
Test status
Simulation time 33449948022 ps
CPU time 50.61 seconds
Started Jul 13 05:53:07 PM PDT 24
Finished Jul 13 05:53:59 PM PDT 24
Peak memory 191548 kb
Host smart-51cfd77f-18a8-4ab2-a8f6-d939b38c6f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247843245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3247843245
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/180.rv_timer_random.1343636918
Short name T307
Test name
Test status
Simulation time 493162223150 ps
CPU time 439.55 seconds
Started Jul 13 05:54:27 PM PDT 24
Finished Jul 13 06:01:47 PM PDT 24
Peak memory 191308 kb
Host smart-0f36de91-d1f2-4818-9246-9d58d5db704a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343636918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1343636918
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1479563780
Short name T345
Test name
Test status
Simulation time 43135947333 ps
CPU time 59.17 seconds
Started Jul 13 05:54:28 PM PDT 24
Finished Jul 13 05:55:27 PM PDT 24
Peak memory 183052 kb
Host smart-2fe8ef70-4980-43d5-9adc-76cff56de79f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479563780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1479563780
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1118790610
Short name T325
Test name
Test status
Simulation time 121950727088 ps
CPU time 143.37 seconds
Started Jul 13 05:54:37 PM PDT 24
Finished Jul 13 05:57:00 PM PDT 24
Peak memory 191296 kb
Host smart-c8083a37-bd1e-4710-823f-77948032770a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118790610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1118790610
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.3806678379
Short name T433
Test name
Test status
Simulation time 82728068633 ps
CPU time 172.19 seconds
Started Jul 13 05:54:36 PM PDT 24
Finished Jul 13 05:57:28 PM PDT 24
Peak memory 191292 kb
Host smart-f6cf3036-7340-4f18-94b3-79e39cbd0fb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806678379 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3806678379
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1993057614
Short name T308
Test name
Test status
Simulation time 71937804860 ps
CPU time 320.92 seconds
Started Jul 13 05:54:36 PM PDT 24
Finished Jul 13 05:59:57 PM PDT 24
Peak memory 191320 kb
Host smart-0fecdaff-18e7-4a3c-b6be-965efab5f04f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993057614 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1993057614
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.2456750454
Short name T434
Test name
Test status
Simulation time 335642539926 ps
CPU time 145.71 seconds
Started Jul 13 05:54:35 PM PDT 24
Finished Jul 13 05:57:01 PM PDT 24
Peak memory 191224 kb
Host smart-70222891-0fca-4372-afdf-4ed975e4b7ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456750454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.2456750454
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.66692439
Short name T284
Test name
Test status
Simulation time 315546517770 ps
CPU time 485.81 seconds
Started Jul 13 05:54:36 PM PDT 24
Finished Jul 13 06:02:43 PM PDT 24
Peak memory 191240 kb
Host smart-11a4e63d-29c8-4716-9137-ce5e81a7235d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66692439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.66692439
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.269317578
Short name T144
Test name
Test status
Simulation time 245862387879 ps
CPU time 590.49 seconds
Started Jul 13 05:54:36 PM PDT 24
Finished Jul 13 06:04:26 PM PDT 24
Peak memory 191324 kb
Host smart-588662eb-134f-4d2f-88c7-f87eaeb4a825
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269317578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.269317578
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3341023713
Short name T197
Test name
Test status
Simulation time 371747365619 ps
CPU time 271.71 seconds
Started Jul 13 05:54:47 PM PDT 24
Finished Jul 13 05:59:19 PM PDT 24
Peak memory 191332 kb
Host smart-68316825-e0d7-4468-890f-4172394bfb43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341023713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3341023713
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.3566997310
Short name T80
Test name
Test status
Simulation time 57019358266 ps
CPU time 44.89 seconds
Started Jul 13 05:53:08 PM PDT 24
Finished Jul 13 05:53:54 PM PDT 24
Peak memory 183368 kb
Host smart-c9579a09-c6e1-4df3-8162-38bbd55ee9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566997310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.3566997310
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1576503179
Short name T292
Test name
Test status
Simulation time 1026607251877 ps
CPU time 606.78 seconds
Started Jul 13 05:53:08 PM PDT 24
Finished Jul 13 06:03:16 PM PDT 24
Peak memory 191512 kb
Host smart-6384ac46-0616-40b8-8276-1c758cd4fe47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576503179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1576503179
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3966564562
Short name T378
Test name
Test status
Simulation time 711781895 ps
CPU time 1.37 seconds
Started Jul 13 05:53:05 PM PDT 24
Finished Jul 13 05:53:08 PM PDT 24
Peak memory 191256 kb
Host smart-21dd7acb-869b-4de4-912c-a4957397cd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966564562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3966564562
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1394849686
Short name T255
Test name
Test status
Simulation time 823257840549 ps
CPU time 442.67 seconds
Started Jul 13 05:53:07 PM PDT 24
Finished Jul 13 06:00:31 PM PDT 24
Peak memory 194672 kb
Host smart-212858bb-3ff0-4fe3-a957-623e2529bf6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394849686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1394849686
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.2383546782
Short name T233
Test name
Test status
Simulation time 109912567561 ps
CPU time 192.57 seconds
Started Jul 13 05:54:43 PM PDT 24
Finished Jul 13 05:57:56 PM PDT 24
Peak memory 191300 kb
Host smart-75d00b91-d547-47cc-80cc-d9d78b97e455
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383546782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2383546782
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.3748451525
Short name T47
Test name
Test status
Simulation time 122381775744 ps
CPU time 190.14 seconds
Started Jul 13 05:54:43 PM PDT 24
Finished Jul 13 05:57:54 PM PDT 24
Peak memory 191296 kb
Host smart-add1d637-3ffb-43e7-9aa8-820483b0f705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748451525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.3748451525
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.1199337599
Short name T154
Test name
Test status
Simulation time 133529046395 ps
CPU time 63.51 seconds
Started Jul 13 05:54:43 PM PDT 24
Finished Jul 13 05:55:46 PM PDT 24
Peak memory 183128 kb
Host smart-4cc0e6cb-8f95-47d1-ae0c-1b4411cf6d91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199337599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.1199337599
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.326442789
Short name T114
Test name
Test status
Simulation time 1560909237311 ps
CPU time 775.55 seconds
Started Jul 13 05:54:48 PM PDT 24
Finished Jul 13 06:07:44 PM PDT 24
Peak memory 193384 kb
Host smart-242c966e-daed-48ee-879c-637b5d47b572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326442789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.326442789
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.2174838644
Short name T314
Test name
Test status
Simulation time 58457361328 ps
CPU time 119.25 seconds
Started Jul 13 05:54:42 PM PDT 24
Finished Jul 13 05:56:42 PM PDT 24
Peak memory 191092 kb
Host smart-7d88a897-cc7e-4b76-b7a5-e2082ebf97fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174838644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.2174838644
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3252682555
Short name T297
Test name
Test status
Simulation time 91791065023 ps
CPU time 279.56 seconds
Started Jul 13 05:54:41 PM PDT 24
Finished Jul 13 05:59:21 PM PDT 24
Peak memory 191300 kb
Host smart-c7cb1f04-bcf1-44df-bcdc-64c2613de464
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252682555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3252682555
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1781806626
Short name T339
Test name
Test status
Simulation time 412344164373 ps
CPU time 172.43 seconds
Started Jul 13 05:54:49 PM PDT 24
Finished Jul 13 05:57:41 PM PDT 24
Peak memory 191332 kb
Host smart-96d79c49-88dc-4a46-bcb6-187f2ac5e877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781806626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1781806626
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.2024675104
Short name T223
Test name
Test status
Simulation time 138219807607 ps
CPU time 135.77 seconds
Started Jul 13 05:54:43 PM PDT 24
Finished Jul 13 05:56:59 PM PDT 24
Peak memory 191292 kb
Host smart-c1174541-e69e-4695-9972-ce9c58af523e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024675104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.2024675104
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.645506191
Short name T322
Test name
Test status
Simulation time 245816819394 ps
CPU time 435.7 seconds
Started Jul 13 05:52:45 PM PDT 24
Finished Jul 13 06:00:01 PM PDT 24
Peak memory 183092 kb
Host smart-b88fd2c1-bc29-4f21-bce4-df2d43dead67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645506191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.rv_timer_cfg_update_on_fly.645506191
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.4089940077
Short name T406
Test name
Test status
Simulation time 201039737535 ps
CPU time 150.7 seconds
Started Jul 13 05:52:53 PM PDT 24
Finished Jul 13 05:55:25 PM PDT 24
Peak memory 183008 kb
Host smart-d006dad1-8c14-45f8-9833-59584c471c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089940077 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.4089940077
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.987019845
Short name T424
Test name
Test status
Simulation time 140405601117 ps
CPU time 513.86 seconds
Started Jul 13 05:52:46 PM PDT 24
Finished Jul 13 06:01:20 PM PDT 24
Peak memory 194748 kb
Host smart-e1356c2b-e622-4503-b92e-d08856d17d55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987019845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.987019845
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2420651942
Short name T389
Test name
Test status
Simulation time 83395223 ps
CPU time 0.65 seconds
Started Jul 13 05:52:47 PM PDT 24
Finished Jul 13 05:52:48 PM PDT 24
Peak memory 182880 kb
Host smart-4dd7e79b-b4d3-4ae9-a2cf-b01af64a4e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420651942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2420651942
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.3855474971
Short name T16
Test name
Test status
Simulation time 647111451 ps
CPU time 0.92 seconds
Started Jul 13 05:52:50 PM PDT 24
Finished Jul 13 05:52:52 PM PDT 24
Peak memory 214420 kb
Host smart-ff395247-a83c-474e-84db-da6c53755ac9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855474971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.3855474971
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.895031865
Short name T386
Test name
Test status
Simulation time 167663532632 ps
CPU time 225.02 seconds
Started Jul 13 05:52:47 PM PDT 24
Finished Jul 13 05:56:32 PM PDT 24
Peak memory 194608 kb
Host smart-bc34c8aa-a467-41fe-be76-de91b134caa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895031865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.895031865
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.728491234
Short name T106
Test name
Test status
Simulation time 29808177043 ps
CPU time 25.49 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 05:53:32 PM PDT 24
Peak memory 183100 kb
Host smart-ecc3efbc-5f52-403b-9b3f-e6cfd0a2a13c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728491234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.rv_timer_cfg_update_on_fly.728491234
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.754904958
Short name T445
Test name
Test status
Simulation time 209543622613 ps
CPU time 159.82 seconds
Started Jul 13 05:53:06 PM PDT 24
Finished Jul 13 05:55:48 PM PDT 24
Peak memory 182620 kb
Host smart-a381bef9-7092-45b3-bdf7-8c88d18bf2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754904958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.754904958
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4118781209
Short name T410
Test name
Test status
Simulation time 86005162265 ps
CPU time 126.19 seconds
Started Jul 13 05:53:06 PM PDT 24
Finished Jul 13 05:55:14 PM PDT 24
Peak memory 183108 kb
Host smart-c761851f-c0bd-4740-a3cd-e73782c9f080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118781209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4118781209
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1845130836
Short name T346
Test name
Test status
Simulation time 1605724789072 ps
CPU time 868.84 seconds
Started Jul 13 05:53:12 PM PDT 24
Finished Jul 13 06:07:42 PM PDT 24
Peak memory 183060 kb
Host smart-20d6170a-107a-412d-ba2f-b55b9ae8f724
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845130836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1845130836
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.1395492015
Short name T362
Test name
Test status
Simulation time 52547149359 ps
CPU time 59.68 seconds
Started Jul 13 05:53:14 PM PDT 24
Finished Jul 13 05:54:15 PM PDT 24
Peak memory 183112 kb
Host smart-4fe4deaa-0104-4a7a-b209-54f8e52a2a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395492015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.1395492015
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1408352210
Short name T301
Test name
Test status
Simulation time 42316948337 ps
CPU time 63.46 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 05:54:26 PM PDT 24
Peak memory 191296 kb
Host smart-5ee0b5a2-db40-4a6d-9212-0e1aa8693f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408352210 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1408352210
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.3691163618
Short name T343
Test name
Test status
Simulation time 1179203854162 ps
CPU time 592.32 seconds
Started Jul 13 05:53:16 PM PDT 24
Finished Jul 13 06:03:10 PM PDT 24
Peak memory 182716 kb
Host smart-68876095-7d93-43c6-8091-06fc7fc6e2ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691163618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.3691163618
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.4000632219
Short name T367
Test name
Test status
Simulation time 412223015489 ps
CPU time 158.14 seconds
Started Jul 13 05:53:13 PM PDT 24
Finished Jul 13 05:55:52 PM PDT 24
Peak memory 183108 kb
Host smart-d6164ee9-83d7-42e1-ad07-c8fa3e28cb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000632219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.4000632219
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.267351235
Short name T125
Test name
Test status
Simulation time 69753836527 ps
CPU time 308.6 seconds
Started Jul 13 05:53:15 PM PDT 24
Finished Jul 13 05:58:25 PM PDT 24
Peak memory 191232 kb
Host smart-1e71322b-6af1-4ad1-b7bb-c9a0f2943b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267351235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.267351235
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.490631433
Short name T415
Test name
Test status
Simulation time 319407334373 ps
CPU time 163.29 seconds
Started Jul 13 05:53:18 PM PDT 24
Finished Jul 13 05:56:02 PM PDT 24
Peak memory 183316 kb
Host smart-36d6fbb8-024a-4283-8927-937bfbdd768b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490631433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.490631433
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2083712486
Short name T403
Test name
Test status
Simulation time 92119595597 ps
CPU time 70.74 seconds
Started Jul 13 05:53:13 PM PDT 24
Finished Jul 13 05:54:24 PM PDT 24
Peak memory 183132 kb
Host smart-65442c65-2be2-4903-aa97-3a03878c14e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083712486 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2083712486
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.3665358696
Short name T282
Test name
Test status
Simulation time 5901358633 ps
CPU time 10.28 seconds
Started Jul 13 05:53:11 PM PDT 24
Finished Jul 13 05:53:22 PM PDT 24
Peak memory 183012 kb
Host smart-eda23d98-3baa-48da-992f-9d6b755a10c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665358696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.3665358696
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2368049385
Short name T22
Test name
Test status
Simulation time 48310104078 ps
CPU time 239.02 seconds
Started Jul 13 05:53:13 PM PDT 24
Finished Jul 13 05:57:13 PM PDT 24
Peak memory 183132 kb
Host smart-17c4887a-d6b4-4a61-a056-e14991ef4ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368049385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2368049385
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2875145964
Short name T249
Test name
Test status
Simulation time 6346418630123 ps
CPU time 1741.37 seconds
Started Jul 13 05:53:18 PM PDT 24
Finished Jul 13 06:22:21 PM PDT 24
Peak memory 191296 kb
Host smart-1aafbeaf-9986-4355-84c2-2c6958be76c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875145964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2875145964
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.2743094836
Short name T24
Test name
Test status
Simulation time 25222534110 ps
CPU time 15.1 seconds
Started Jul 13 05:53:16 PM PDT 24
Finished Jul 13 05:53:32 PM PDT 24
Peak memory 183092 kb
Host smart-0d19eddf-6973-4ae1-af13-0f623960c123
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743094836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.2743094836
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.3968658945
Short name T387
Test name
Test status
Simulation time 102435922877 ps
CPU time 128.61 seconds
Started Jul 13 05:53:14 PM PDT 24
Finished Jul 13 05:55:23 PM PDT 24
Peak memory 183120 kb
Host smart-a4052946-5875-48de-b83d-62945392e1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968658945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.3968658945
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.2042872308
Short name T333
Test name
Test status
Simulation time 17087732791 ps
CPU time 36.48 seconds
Started Jul 13 05:53:13 PM PDT 24
Finished Jul 13 05:53:51 PM PDT 24
Peak memory 191248 kb
Host smart-a573006e-6a3f-4e0d-9364-f6027d21fe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042872308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.2042872308
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.2838850612
Short name T380
Test name
Test status
Simulation time 597975131672 ps
CPU time 232.9 seconds
Started Jul 13 05:53:13 PM PDT 24
Finished Jul 13 05:57:07 PM PDT 24
Peak memory 183124 kb
Host smart-2ef6dced-5b40-4ed6-b025-fa4841f5ee7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838850612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.2838850612
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2940115344
Short name T59
Test name
Test status
Simulation time 349926910643 ps
CPU time 299 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 05:58:22 PM PDT 24
Peak memory 183008 kb
Host smart-13e35be0-1ac8-416d-a26a-6bdc9555746c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940115344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2940115344
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.1934791602
Short name T78
Test name
Test status
Simulation time 570442686486 ps
CPU time 217.75 seconds
Started Jul 13 05:53:16 PM PDT 24
Finished Jul 13 05:56:55 PM PDT 24
Peak memory 183104 kb
Host smart-369e8c49-37dc-4a9d-abbd-af01769a25b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934791602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.1934791602
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.620301040
Short name T112
Test name
Test status
Simulation time 352106672980 ps
CPU time 560.27 seconds
Started Jul 13 05:53:14 PM PDT 24
Finished Jul 13 06:02:36 PM PDT 24
Peak memory 183104 kb
Host smart-fdff3dd4-6208-43cc-a817-5c41afaaf4a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620301040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.rv_timer_cfg_update_on_fly.620301040
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.3570356234
Short name T416
Test name
Test status
Simulation time 83960155316 ps
CPU time 110.18 seconds
Started Jul 13 05:53:14 PM PDT 24
Finished Jul 13 05:55:05 PM PDT 24
Peak memory 183124 kb
Host smart-6e46faee-f2dd-4f3c-a71d-826a1573d2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570356234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.3570356234
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.2586716057
Short name T160
Test name
Test status
Simulation time 56438254235 ps
CPU time 649.41 seconds
Started Jul 13 05:53:15 PM PDT 24
Finished Jul 13 06:04:06 PM PDT 24
Peak memory 191568 kb
Host smart-4421f274-a7ff-4515-ad37-68666266bf43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586716057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2586716057
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.1460817235
Short name T186
Test name
Test status
Simulation time 2448359316 ps
CPU time 4.43 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 05:53:27 PM PDT 24
Peak memory 183004 kb
Host smart-e7c407fb-fbf6-4e05-8668-6d97e4f2f9ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460817235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.1460817235
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.436378739
Short name T404
Test name
Test status
Simulation time 187727071325 ps
CPU time 80.66 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 05:54:39 PM PDT 24
Peak memory 183108 kb
Host smart-d3dab908-7de9-49c2-86f5-71900ac55f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436378739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.436378739
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.3923593727
Short name T293
Test name
Test status
Simulation time 38618606325 ps
CPU time 58.46 seconds
Started Jul 13 05:53:13 PM PDT 24
Finished Jul 13 05:54:13 PM PDT 24
Peak memory 183036 kb
Host smart-f4f71a7b-5022-455e-99df-624062c1df7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923593727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.3923593727
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2081896876
Short name T244
Test name
Test status
Simulation time 1684750628513 ps
CPU time 917.86 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 06:08:40 PM PDT 24
Peak memory 183004 kb
Host smart-7a8ff564-7031-47e4-b35f-0cc4e48570e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081896876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2081896876
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.2597338707
Short name T383
Test name
Test status
Simulation time 951589297621 ps
CPU time 173.72 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 05:56:12 PM PDT 24
Peak memory 183104 kb
Host smart-048f758a-a704-40cf-9caf-f145f60d6936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597338707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.2597338707
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.4131996821
Short name T119
Test name
Test status
Simulation time 33254859444 ps
CPU time 52.11 seconds
Started Jul 13 05:53:14 PM PDT 24
Finished Jul 13 05:54:07 PM PDT 24
Peak memory 191332 kb
Host smart-fdf457bf-453d-4eca-99db-35fcee2a672e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131996821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.4131996821
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1489618009
Short name T444
Test name
Test status
Simulation time 88543866903 ps
CPU time 450.15 seconds
Started Jul 13 05:53:15 PM PDT 24
Finished Jul 13 06:00:47 PM PDT 24
Peak memory 191244 kb
Host smart-5a897963-5096-4b54-8fe1-8953ad17a654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489618009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1489618009
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.885764484
Short name T43
Test name
Test status
Simulation time 45819201324 ps
CPU time 26.27 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 05:53:45 PM PDT 24
Peak memory 183096 kb
Host smart-03d6555f-655a-4764-9560-ed79f315fb2a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885764484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.rv_timer_cfg_update_on_fly.885764484
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2402943732
Short name T25
Test name
Test status
Simulation time 73767719550 ps
CPU time 107.06 seconds
Started Jul 13 05:53:12 PM PDT 24
Finished Jul 13 05:55:00 PM PDT 24
Peak memory 183116 kb
Host smart-9876099b-db0f-41bd-9665-4cdc2278606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402943732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2402943732
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.113916277
Short name T281
Test name
Test status
Simulation time 1161224283653 ps
CPU time 650.6 seconds
Started Jul 13 05:53:13 PM PDT 24
Finished Jul 13 06:04:05 PM PDT 24
Peak memory 191288 kb
Host smart-4e3cb1cd-45ae-49d4-8f09-f7d654cde33a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113916277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.113916277
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3025228832
Short name T111
Test name
Test status
Simulation time 46082853730 ps
CPU time 150.99 seconds
Started Jul 13 05:53:16 PM PDT 24
Finished Jul 13 05:55:47 PM PDT 24
Peak memory 191328 kb
Host smart-a25a3cc8-7b0b-433f-a6de-69c94b6eb081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025228832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3025228832
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1497395922
Short name T390
Test name
Test status
Simulation time 228548247597 ps
CPU time 332.5 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 05:58:51 PM PDT 24
Peak memory 191300 kb
Host smart-9d24ee13-d29b-4462-a584-82775d8daf9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497395922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1497395922
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.456835065
Short name T77
Test name
Test status
Simulation time 53001316277 ps
CPU time 23.89 seconds
Started Jul 13 05:52:46 PM PDT 24
Finished Jul 13 05:53:11 PM PDT 24
Peak memory 183120 kb
Host smart-b80037ba-2cd5-4aa9-924b-a0c7ef44b210
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456835065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.456835065
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.267704946
Short name T422
Test name
Test status
Simulation time 118129693224 ps
CPU time 92.53 seconds
Started Jul 13 05:52:45 PM PDT 24
Finished Jul 13 05:54:18 PM PDT 24
Peak memory 183120 kb
Host smart-d4a63f06-28bb-4194-acdf-9fb9503e2b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267704946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.267704946
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.3285342641
Short name T388
Test name
Test status
Simulation time 623100438341 ps
CPU time 182.09 seconds
Started Jul 13 05:52:46 PM PDT 24
Finished Jul 13 05:55:49 PM PDT 24
Peak memory 183112 kb
Host smart-76e10194-77db-4273-8bb6-18cdfe96dff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285342641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3285342641
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2216738072
Short name T120
Test name
Test status
Simulation time 30661256979 ps
CPU time 12.58 seconds
Started Jul 13 05:52:46 PM PDT 24
Finished Jul 13 05:53:00 PM PDT 24
Peak memory 183236 kb
Host smart-d74fded3-126e-483a-8a97-64f9132aa51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216738072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2216738072
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.242364879
Short name T15
Test name
Test status
Simulation time 543799170 ps
CPU time 0.74 seconds
Started Jul 13 05:52:50 PM PDT 24
Finished Jul 13 05:52:51 PM PDT 24
Peak memory 213308 kb
Host smart-597e91db-96ca-49b3-9c94-a5f2e9a2648f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242364879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.242364879
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2364033882
Short name T139
Test name
Test status
Simulation time 1310373273729 ps
CPU time 400.02 seconds
Started Jul 13 05:53:12 PM PDT 24
Finished Jul 13 05:59:53 PM PDT 24
Peak memory 183004 kb
Host smart-12cbfab7-0103-4b6c-874c-ac10e0731947
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364033882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2364033882
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.1383546115
Short name T371
Test name
Test status
Simulation time 30303547560 ps
CPU time 37.66 seconds
Started Jul 13 05:53:15 PM PDT 24
Finished Jul 13 05:53:54 PM PDT 24
Peak memory 183132 kb
Host smart-bfee739d-4db3-4229-a4ac-b9188043a184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383546115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.1383546115
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1250815566
Short name T364
Test name
Test status
Simulation time 1090938295 ps
CPU time 2.22 seconds
Started Jul 13 05:53:18 PM PDT 24
Finished Jul 13 05:53:21 PM PDT 24
Peak memory 182968 kb
Host smart-96bbb55f-8bca-42a5-902e-5c2d2d712cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250815566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1250815566
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.582853396
Short name T315
Test name
Test status
Simulation time 281233144457 ps
CPU time 640.87 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 06:04:00 PM PDT 24
Peak memory 194548 kb
Host smart-ded4b518-00c8-4199-a275-b526b638c52f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582853396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
582853396
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3052426968
Short name T413
Test name
Test status
Simulation time 1292386369800 ps
CPU time 548.4 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 06:02:26 PM PDT 24
Peak memory 183016 kb
Host smart-1fb1300e-c963-4411-b3af-ac9352bf4b6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052426968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3052426968
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.121700168
Short name T432
Test name
Test status
Simulation time 32852396305 ps
CPU time 49.43 seconds
Started Jul 13 05:53:14 PM PDT 24
Finished Jul 13 05:54:04 PM PDT 24
Peak memory 183108 kb
Host smart-6360f40b-cb9f-4874-ab7d-d30cb9d096fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121700168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.121700168
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.1745331517
Short name T211
Test name
Test status
Simulation time 380479283618 ps
CPU time 378.87 seconds
Started Jul 13 05:53:16 PM PDT 24
Finished Jul 13 05:59:35 PM PDT 24
Peak memory 191224 kb
Host smart-6af2517d-3bee-4c86-be99-090efaab1a49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745331517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.1745331517
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1036607573
Short name T446
Test name
Test status
Simulation time 499460255771 ps
CPU time 127.61 seconds
Started Jul 13 05:53:15 PM PDT 24
Finished Jul 13 05:55:24 PM PDT 24
Peak memory 183116 kb
Host smart-660522be-eb53-48e1-9c37-64a22878f29e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036607573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1036607573
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3459051014
Short name T276
Test name
Test status
Simulation time 352644124913 ps
CPU time 523.19 seconds
Started Jul 13 05:53:14 PM PDT 24
Finished Jul 13 06:01:58 PM PDT 24
Peak memory 183008 kb
Host smart-2294cf97-fbd5-49fc-a908-cf8ba018817d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459051014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3459051014
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1108122132
Short name T357
Test name
Test status
Simulation time 31446397181 ps
CPU time 45.13 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 05:54:04 PM PDT 24
Peak memory 182904 kb
Host smart-7cf4be73-969f-4773-899e-e463624466b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108122132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1108122132
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.3852524893
Short name T354
Test name
Test status
Simulation time 7958179294 ps
CPU time 16.09 seconds
Started Jul 13 05:53:13 PM PDT 24
Finished Jul 13 05:53:30 PM PDT 24
Peak memory 183108 kb
Host smart-7b035bb6-a13f-4008-ba84-154e484b7281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852524893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.3852524893
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3614786985
Short name T313
Test name
Test status
Simulation time 397576649244 ps
CPU time 1204.61 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 06:13:27 PM PDT 24
Peak memory 195696 kb
Host smart-87e0d60c-9528-4c24-8ba8-da83632c77ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614786985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3614786985
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.3983785671
Short name T13
Test name
Test status
Simulation time 135438270879 ps
CPU time 390.81 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 05:59:50 PM PDT 24
Peak memory 205984 kb
Host smart-6f960304-07fe-4472-84d4-6c1fafea4636
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983785671 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.3983785671
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2208805129
Short name T300
Test name
Test status
Simulation time 19663148504 ps
CPU time 34.71 seconds
Started Jul 13 05:53:14 PM PDT 24
Finished Jul 13 05:53:49 PM PDT 24
Peak memory 183060 kb
Host smart-61b54d61-d855-4913-aab4-02906b1cb07e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208805129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2208805129
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.3683003844
Short name T419
Test name
Test status
Simulation time 149645351484 ps
CPU time 62.81 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 05:54:21 PM PDT 24
Peak memory 183108 kb
Host smart-5e61eca5-c931-4831-bfcf-342b6dce2098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683003844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.3683003844
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.934335105
Short name T323
Test name
Test status
Simulation time 182819029539 ps
CPU time 94.4 seconds
Started Jul 13 05:53:13 PM PDT 24
Finished Jul 13 05:54:49 PM PDT 24
Peak memory 191248 kb
Host smart-110046e8-b398-4530-9f17-6305de2dedf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934335105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.934335105
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.439656217
Short name T309
Test name
Test status
Simulation time 1926455297 ps
CPU time 1.56 seconds
Started Jul 13 05:53:17 PM PDT 24
Finished Jul 13 05:53:20 PM PDT 24
Peak memory 194148 kb
Host smart-4b5c6917-7a17-4725-a973-d64cf0e33dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439656217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.439656217
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3791992863
Short name T142
Test name
Test status
Simulation time 24066030080 ps
CPU time 24.86 seconds
Started Jul 13 05:53:28 PM PDT 24
Finished Jul 13 05:53:53 PM PDT 24
Peak memory 183316 kb
Host smart-5b3b349d-5449-41a1-bc0c-727cad46607e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791992863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3791992863
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.195968041
Short name T392
Test name
Test status
Simulation time 58144838456 ps
CPU time 54.87 seconds
Started Jul 13 05:53:24 PM PDT 24
Finished Jul 13 05:54:21 PM PDT 24
Peak memory 183060 kb
Host smart-33902cc8-8e5f-44e6-b23f-7bf811db398e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195968041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.195968041
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2413819320
Short name T198
Test name
Test status
Simulation time 56849189519 ps
CPU time 102.89 seconds
Started Jul 13 05:53:26 PM PDT 24
Finished Jul 13 05:55:10 PM PDT 24
Peak memory 191260 kb
Host smart-e5ea0e14-ad95-4693-9b5b-9dcdc600f5b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413819320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2413819320
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.3792817956
Short name T289
Test name
Test status
Simulation time 177581795423 ps
CPU time 373.02 seconds
Started Jul 13 05:53:31 PM PDT 24
Finished Jul 13 05:59:45 PM PDT 24
Peak memory 191316 kb
Host smart-1c334f18-f10c-4364-bc03-9cc7d014cbe4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792817956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.3792817956
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1079761442
Short name T105
Test name
Test status
Simulation time 23903345581 ps
CPU time 13.65 seconds
Started Jul 13 05:53:32 PM PDT 24
Finished Jul 13 05:53:46 PM PDT 24
Peak memory 183088 kb
Host smart-54498ac4-cfcf-45e2-8a69-81a1514da90f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079761442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1079761442
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2569728188
Short name T8
Test name
Test status
Simulation time 39578738089 ps
CPU time 58.17 seconds
Started Jul 13 05:53:25 PM PDT 24
Finished Jul 13 05:54:24 PM PDT 24
Peak memory 183104 kb
Host smart-d17e1e11-a79f-480b-8178-fc38ff091196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569728188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2569728188
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1382832719
Short name T350
Test name
Test status
Simulation time 95418620386 ps
CPU time 68.71 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 05:54:32 PM PDT 24
Peak memory 195064 kb
Host smart-5d5fe007-e919-49f2-8911-a4096103329f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382832719 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1382832719
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1328020774
Short name T430
Test name
Test status
Simulation time 719051437 ps
CPU time 1.04 seconds
Started Jul 13 05:53:25 PM PDT 24
Finished Jul 13 05:53:27 PM PDT 24
Peak memory 191212 kb
Host smart-05bc8e84-6ebd-4c91-9429-28bd4507959e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328020774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1328020774
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.821727507
Short name T3
Test name
Test status
Simulation time 67512546 ps
CPU time 0.58 seconds
Started Jul 13 05:53:25 PM PDT 24
Finished Jul 13 05:53:27 PM PDT 24
Peak memory 182944 kb
Host smart-f10d3ef2-4d6a-410c-ae83-381e05780636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821727507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
821727507
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.534392990
Short name T36
Test name
Test status
Simulation time 47448278698 ps
CPU time 274.7 seconds
Started Jul 13 05:53:24 PM PDT 24
Finished Jul 13 05:58:01 PM PDT 24
Peak memory 205952 kb
Host smart-e709146c-3c55-4099-8f0d-2b28a13b5282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534392990 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.534392990
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.373689883
Short name T443
Test name
Test status
Simulation time 293707327261 ps
CPU time 170.18 seconds
Started Jul 13 05:53:25 PM PDT 24
Finished Jul 13 05:56:16 PM PDT 24
Peak memory 183048 kb
Host smart-f983bf1e-2772-4dc2-8049-3ada496ae65c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373689883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.373689883
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3049593075
Short name T437
Test name
Test status
Simulation time 116944315624 ps
CPU time 87.17 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 05:54:51 PM PDT 24
Peak memory 183036 kb
Host smart-e86ebb4f-dc02-469e-869c-9c8a49eb9226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049593075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3049593075
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.299705989
Short name T334
Test name
Test status
Simulation time 108595309660 ps
CPU time 99.38 seconds
Started Jul 13 05:53:32 PM PDT 24
Finished Jul 13 05:55:12 PM PDT 24
Peak memory 191320 kb
Host smart-8d7f6f3d-3425-4629-8677-1d3b7f941ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299705989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.299705989
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2724600869
Short name T123
Test name
Test status
Simulation time 40983035022 ps
CPU time 62.44 seconds
Started Jul 13 05:53:25 PM PDT 24
Finished Jul 13 05:54:29 PM PDT 24
Peak memory 194808 kb
Host smart-f09a9b78-9520-41b2-b440-49a605840038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724600869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2724600869
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.659607703
Short name T219
Test name
Test status
Simulation time 1174079682048 ps
CPU time 514.23 seconds
Started Jul 13 05:53:24 PM PDT 24
Finished Jul 13 06:02:00 PM PDT 24
Peak memory 183100 kb
Host smart-62f4f28b-4fea-4433-8ef4-aae6e1de45cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659607703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.659607703
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3799205816
Short name T382
Test name
Test status
Simulation time 432377222060 ps
CPU time 165.53 seconds
Started Jul 13 05:53:24 PM PDT 24
Finished Jul 13 05:56:11 PM PDT 24
Peak memory 183076 kb
Host smart-8e3fa699-aa63-4109-92a8-fc29ab47e1fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799205816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3799205816
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1899740264
Short name T193
Test name
Test status
Simulation time 397327114501 ps
CPU time 388.58 seconds
Started Jul 13 05:53:24 PM PDT 24
Finished Jul 13 05:59:54 PM PDT 24
Peak memory 191324 kb
Host smart-43468644-57b8-49e8-b59d-373daae7bb92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899740264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1899740264
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1146480401
Short name T376
Test name
Test status
Simulation time 661869981 ps
CPU time 0.74 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 05:53:25 PM PDT 24
Peak memory 182976 kb
Host smart-7fea2e94-9116-4eec-8d09-c9fbcce8050c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146480401 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1146480401
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1775979676
Short name T353
Test name
Test status
Simulation time 1049327450298 ps
CPU time 418.48 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 06:00:23 PM PDT 24
Peak memory 191212 kb
Host smart-41033fcc-0952-4fbe-b220-923c0c9d0075
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775979676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1775979676
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3290617733
Short name T181
Test name
Test status
Simulation time 376095195665 ps
CPU time 300.74 seconds
Started Jul 13 05:53:24 PM PDT 24
Finished Jul 13 05:58:26 PM PDT 24
Peak memory 183112 kb
Host smart-fba85b0d-d57c-46a2-b164-273572dc91ad
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290617733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3290617733
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.981737116
Short name T361
Test name
Test status
Simulation time 199215675147 ps
CPU time 146.37 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 05:55:50 PM PDT 24
Peak memory 183036 kb
Host smart-828b230f-9e9b-49d9-8ad0-5abf17b1849a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981737116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.981737116
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3333983872
Short name T108
Test name
Test status
Simulation time 310641089529 ps
CPU time 372.27 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 05:59:37 PM PDT 24
Peak memory 191320 kb
Host smart-24d7dc5f-2eaf-435d-9387-ed09c8f4b5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333983872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3333983872
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1913734606
Short name T411
Test name
Test status
Simulation time 2167726924734 ps
CPU time 709.23 seconds
Started Jul 13 05:53:29 PM PDT 24
Finished Jul 13 06:05:18 PM PDT 24
Peak memory 182944 kb
Host smart-baf2cd20-2c0c-47c9-9bc5-01e2c3f19d89
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913734606 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1913734606
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2957638022
Short name T385
Test name
Test status
Simulation time 192131534072 ps
CPU time 255.52 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 05:57:41 PM PDT 24
Peak memory 183132 kb
Host smart-eca602fc-8e00-454b-b6c5-18c5d00f2290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957638022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2957638022
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.4144755078
Short name T340
Test name
Test status
Simulation time 113311261925 ps
CPU time 1362.41 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 06:16:07 PM PDT 24
Peak memory 191260 kb
Host smart-5dd2c2af-c902-46b6-b47a-53351e39a948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144755078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.4144755078
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1202044590
Short name T377
Test name
Test status
Simulation time 143474223 ps
CPU time 0.73 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 05:53:24 PM PDT 24
Peak memory 182968 kb
Host smart-c2841573-c16e-4ba1-8dec-d9669b43138f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202044590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1202044590
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.3444294469
Short name T335
Test name
Test status
Simulation time 372788270671 ps
CPU time 336.01 seconds
Started Jul 13 05:53:26 PM PDT 24
Finished Jul 13 05:59:03 PM PDT 24
Peak memory 190980 kb
Host smart-a3aa6c21-3748-4cfb-8720-369a58d842ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444294469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.3444294469
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.712227729
Short name T122
Test name
Test status
Simulation time 93657489492 ps
CPU time 101.81 seconds
Started Jul 13 05:52:46 PM PDT 24
Finished Jul 13 05:54:28 PM PDT 24
Peak memory 183100 kb
Host smart-91809308-aae0-4bb0-b714-6e54f3e3e550
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712227729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.rv_timer_cfg_update_on_fly.712227729
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2175160081
Short name T381
Test name
Test status
Simulation time 81250548644 ps
CPU time 118.45 seconds
Started Jul 13 05:52:46 PM PDT 24
Finished Jul 13 05:54:46 PM PDT 24
Peak memory 183032 kb
Host smart-d2f10577-27e9-49a3-8f30-b27b4805d844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175160081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2175160081
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.3086004581
Short name T421
Test name
Test status
Simulation time 62676362060 ps
CPU time 80.46 seconds
Started Jul 13 05:52:44 PM PDT 24
Finished Jul 13 05:54:05 PM PDT 24
Peak memory 193696 kb
Host smart-8f3287d6-8669-46ce-8731-909f1bb3c759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086004581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3086004581
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1273200995
Short name T126
Test name
Test status
Simulation time 33027768024 ps
CPU time 42.17 seconds
Started Jul 13 05:52:53 PM PDT 24
Finished Jul 13 05:53:36 PM PDT 24
Peak memory 182924 kb
Host smart-4b8652a7-abaa-4ff7-9993-69d2bc016adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273200995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1273200995
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.78573903
Short name T18
Test name
Test status
Simulation time 66000789 ps
CPU time 0.87 seconds
Started Jul 13 05:52:47 PM PDT 24
Finished Jul 13 05:52:48 PM PDT 24
Peak memory 213384 kb
Host smart-ffbe0a39-ccb0-4723-961a-c59881979413
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78573903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.78573903
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all_with_rand_reset.3100138775
Short name T37
Test name
Test status
Simulation time 53765399338 ps
CPU time 230.06 seconds
Started Jul 13 05:52:50 PM PDT 24
Finished Jul 13 05:56:41 PM PDT 24
Peak memory 197700 kb
Host smart-eb07c7b1-a4a8-48fc-9f3e-fa21452e40fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100138775 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all_with_rand_reset.3100138775
Directory /workspace/4.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3006511249
Short name T379
Test name
Test status
Simulation time 20096781970 ps
CPU time 19.23 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 05:53:44 PM PDT 24
Peak memory 183084 kb
Host smart-4adf860c-fb41-4a7d-bb1e-0425a13807c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006511249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3006511249
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1458488822
Short name T399
Test name
Test status
Simulation time 108119804962 ps
CPU time 39.99 seconds
Started Jul 13 05:53:24 PM PDT 24
Finished Jul 13 05:54:06 PM PDT 24
Peak memory 183116 kb
Host smart-5a30b55d-a296-4d49-8501-9ebfadb69737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458488822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1458488822
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.552179923
Short name T278
Test name
Test status
Simulation time 19456011385 ps
CPU time 15.44 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 05:53:39 PM PDT 24
Peak memory 183016 kb
Host smart-acd77eba-be4b-43d8-b26b-234aec564e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552179923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.552179923
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.3212777346
Short name T427
Test name
Test status
Simulation time 12746351094 ps
CPU time 20.58 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 05:53:46 PM PDT 24
Peak memory 191320 kb
Host smart-a6f54e73-ec0c-4ed3-b5b9-129492f82195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212777346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.3212777346
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2171477224
Short name T124
Test name
Test status
Simulation time 201031156164 ps
CPU time 361.53 seconds
Started Jul 13 05:53:27 PM PDT 24
Finished Jul 13 05:59:29 PM PDT 24
Peak memory 191252 kb
Host smart-45d8d469-e887-4e9d-a0d3-a38c66eed8ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171477224 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2171477224
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.991924608
Short name T162
Test name
Test status
Simulation time 32288652551 ps
CPU time 47.63 seconds
Started Jul 13 05:53:27 PM PDT 24
Finished Jul 13 05:54:15 PM PDT 24
Peak memory 183052 kb
Host smart-1fc7059a-d278-4e67-8dca-9ee31a8d9b32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991924608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.991924608
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3975092856
Short name T358
Test name
Test status
Simulation time 65590611565 ps
CPU time 105.57 seconds
Started Jul 13 05:53:25 PM PDT 24
Finished Jul 13 05:55:12 PM PDT 24
Peak memory 183040 kb
Host smart-e2e68bae-83c5-4440-b474-8ae47c1599ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975092856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3975092856
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.68317439
Short name T173
Test name
Test status
Simulation time 282997816032 ps
CPU time 139.51 seconds
Started Jul 13 05:53:27 PM PDT 24
Finished Jul 13 05:55:47 PM PDT 24
Peak memory 191320 kb
Host smart-d30acab5-7e8b-484b-93e0-1521aa8fed62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68317439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.68317439
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.920758679
Short name T370
Test name
Test status
Simulation time 22194802091 ps
CPU time 18.79 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 05:53:41 PM PDT 24
Peak memory 191320 kb
Host smart-6197829b-1c6c-49c9-9d3a-bcb6347c8287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920758679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.920758679
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.4167710188
Short name T68
Test name
Test status
Simulation time 251127250649 ps
CPU time 249.03 seconds
Started Jul 13 05:53:24 PM PDT 24
Finished Jul 13 05:57:34 PM PDT 24
Peak memory 195392 kb
Host smart-dfcce862-45ae-49c8-81b5-c2d7c8337ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167710188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.4167710188
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2705265827
Short name T6
Test name
Test status
Simulation time 23442540533 ps
CPU time 11.6 seconds
Started Jul 13 05:53:25 PM PDT 24
Finished Jul 13 05:53:38 PM PDT 24
Peak memory 183032 kb
Host smart-91c7ca6c-0c2e-403c-be58-6450ba98c33e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705265827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2705265827
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3112501554
Short name T369
Test name
Test status
Simulation time 170752632440 ps
CPU time 123.89 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 05:55:28 PM PDT 24
Peak memory 183128 kb
Host smart-15429bff-abb4-4e68-bb49-82009477859f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112501554 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3112501554
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.1072638665
Short name T148
Test name
Test status
Simulation time 100784690577 ps
CPU time 171.67 seconds
Started Jul 13 05:53:22 PM PDT 24
Finished Jul 13 05:56:15 PM PDT 24
Peak memory 191240 kb
Host smart-85d34665-9a63-4d12-8dee-4ec157c0d5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072638665 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.1072638665
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3343626985
Short name T189
Test name
Test status
Simulation time 1452196307719 ps
CPU time 770.32 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 06:06:16 PM PDT 24
Peak memory 183084 kb
Host smart-60dd2207-41d3-4e55-b269-dd56d1cf0bbf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343626985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3343626985
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3739601221
Short name T397
Test name
Test status
Simulation time 99207781823 ps
CPU time 152 seconds
Started Jul 13 05:53:23 PM PDT 24
Finished Jul 13 05:55:57 PM PDT 24
Peak memory 183116 kb
Host smart-1322f59b-fa7b-4e89-a88c-3b3171ad316b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739601221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3739601221
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3543106081
Short name T229
Test name
Test status
Simulation time 125730001316 ps
CPU time 187.49 seconds
Started Jul 13 05:53:25 PM PDT 24
Finished Jul 13 05:56:34 PM PDT 24
Peak memory 191256 kb
Host smart-75bff33d-8425-405d-970b-f56817802678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543106081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3543106081
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3589426592
Short name T435
Test name
Test status
Simulation time 88466807232 ps
CPU time 176.92 seconds
Started Jul 13 05:53:24 PM PDT 24
Finished Jul 13 05:56:23 PM PDT 24
Peak memory 183112 kb
Host smart-684a4a65-ccde-465c-b365-fce8cf932e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589426592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3589426592
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.2760037445
Short name T209
Test name
Test status
Simulation time 19328740895 ps
CPU time 35.81 seconds
Started Jul 13 05:53:30 PM PDT 24
Finished Jul 13 05:54:07 PM PDT 24
Peak memory 183088 kb
Host smart-f066489e-d6cf-4d83-921f-e8039bf19f17
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760037445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.2760037445
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_random.228445462
Short name T326
Test name
Test status
Simulation time 115270656049 ps
CPU time 591.17 seconds
Started Jul 13 05:53:32 PM PDT 24
Finished Jul 13 06:03:24 PM PDT 24
Peak memory 191328 kb
Host smart-a9a129d9-69cd-4c6e-ada8-7cb647bb9f0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228445462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.228445462
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.938280371
Short name T41
Test name
Test status
Simulation time 67507589453 ps
CPU time 313.33 seconds
Started Jul 13 05:53:31 PM PDT 24
Finished Jul 13 05:58:46 PM PDT 24
Peak memory 191292 kb
Host smart-6edafa1e-4060-48ec-a4d5-1dc34ff4ad8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938280371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.938280371
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.932933940
Short name T251
Test name
Test status
Simulation time 890724725355 ps
CPU time 416.5 seconds
Started Jul 13 05:53:37 PM PDT 24
Finished Jul 13 06:00:35 PM PDT 24
Peak memory 183056 kb
Host smart-1194d08a-001a-4454-bd38-241d95ef6300
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932933940 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.932933940
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1319647559
Short name T372
Test name
Test status
Simulation time 322524406990 ps
CPU time 123.91 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:55:44 PM PDT 24
Peak memory 183088 kb
Host smart-7cf4583c-50a9-41f7-84a3-cc412e3016e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319647559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1319647559
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.263018495
Short name T178
Test name
Test status
Simulation time 438993364127 ps
CPU time 1561.27 seconds
Started Jul 13 05:53:40 PM PDT 24
Finished Jul 13 06:19:43 PM PDT 24
Peak memory 194804 kb
Host smart-3bfab9be-5ca6-41a4-ab0b-32cd2239df06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263018495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.263018495
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3351348461
Short name T69
Test name
Test status
Simulation time 416665646861 ps
CPU time 624.82 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:04:05 PM PDT 24
Peak memory 191268 kb
Host smart-b3eec2da-b9f6-495b-b0e6-ef8bc3f3e976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351348461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3351348461
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2543094254
Short name T258
Test name
Test status
Simulation time 1419217410855 ps
CPU time 694.46 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:05:14 PM PDT 24
Peak memory 183088 kb
Host smart-0ad8cdaa-3eb6-4102-8b65-142ada90135c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543094254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2543094254
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3729899900
Short name T360
Test name
Test status
Simulation time 357517600760 ps
CPU time 248.58 seconds
Started Jul 13 05:53:32 PM PDT 24
Finished Jul 13 05:57:41 PM PDT 24
Peak memory 183060 kb
Host smart-27ff13fa-fdf8-4208-a5e7-eea738b58ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729899900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3729899900
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3548742856
Short name T320
Test name
Test status
Simulation time 82143536145 ps
CPU time 69.62 seconds
Started Jul 13 05:53:30 PM PDT 24
Finished Jul 13 05:54:40 PM PDT 24
Peak memory 191328 kb
Host smart-6e17d4ce-b111-469f-90f4-7c32ea711b06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548742856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3548742856
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2152537369
Short name T363
Test name
Test status
Simulation time 5878604533 ps
CPU time 21.94 seconds
Started Jul 13 05:53:29 PM PDT 24
Finished Jul 13 05:53:51 PM PDT 24
Peak memory 183076 kb
Host smart-bbee2026-89f7-414c-bd6e-369affd03ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152537369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2152537369
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.3899937852
Short name T149
Test name
Test status
Simulation time 895365778465 ps
CPU time 490.08 seconds
Started Jul 13 05:53:39 PM PDT 24
Finished Jul 13 06:01:51 PM PDT 24
Peak memory 182880 kb
Host smart-15dadd36-b4d3-459a-b7c5-d67a69970c18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899937852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.3899937852
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.3594580470
Short name T356
Test name
Test status
Simulation time 14019837681 ps
CPU time 7.57 seconds
Started Jul 13 05:53:30 PM PDT 24
Finished Jul 13 05:53:38 PM PDT 24
Peak memory 183116 kb
Host smart-67c2ff5e-87f2-407d-aff7-3df5a4f68c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594580470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.3594580470
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.2612380381
Short name T256
Test name
Test status
Simulation time 1361144544076 ps
CPU time 383.89 seconds
Started Jul 13 05:53:29 PM PDT 24
Finished Jul 13 05:59:53 PM PDT 24
Peak memory 191332 kb
Host smart-cd28b6f0-1daa-4c7e-a449-48405c5f213b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612380381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.2612380381
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2432449130
Short name T402
Test name
Test status
Simulation time 196736368 ps
CPU time 1.18 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:53:41 PM PDT 24
Peak memory 191048 kb
Host smart-4c6440ce-0cf7-4a7c-aa3a-03c4ef5fc7b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432449130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2432449130
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.4009708173
Short name T395
Test name
Test status
Simulation time 56560481 ps
CPU time 0.54 seconds
Started Jul 13 05:53:39 PM PDT 24
Finished Jul 13 05:53:41 PM PDT 24
Peak memory 182972 kb
Host smart-a979fac9-8cb1-4ba6-9320-36a2d7beb7ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009708173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.4009708173
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.4172368836
Short name T224
Test name
Test status
Simulation time 1003498546920 ps
CPU time 1675.53 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:21:35 PM PDT 24
Peak memory 183116 kb
Host smart-7fcce16f-e226-4bf7-93fc-571e9399fd69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172368836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.4172368836
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.3192050254
Short name T401
Test name
Test status
Simulation time 425894969260 ps
CPU time 100.62 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:55:21 PM PDT 24
Peak memory 182904 kb
Host smart-5efea4ba-30f3-4b31-b7e8-47a12657e1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192050254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.3192050254
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.3650640724
Short name T207
Test name
Test status
Simulation time 151849004326 ps
CPU time 112.92 seconds
Started Jul 13 05:53:29 PM PDT 24
Finished Jul 13 05:55:22 PM PDT 24
Peak memory 191220 kb
Host smart-0b8c9a21-15ce-451b-889c-d5a8af517b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650640724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.3650640724
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.3380027380
Short name T330
Test name
Test status
Simulation time 23884854428 ps
CPU time 40.71 seconds
Started Jul 13 05:53:40 PM PDT 24
Finished Jul 13 05:54:22 PM PDT 24
Peak memory 191308 kb
Host smart-f7f33099-7b32-49e2-9f4c-b666b28306c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380027380 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.3380027380
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.497991731
Short name T349
Test name
Test status
Simulation time 21809933504 ps
CPU time 12.04 seconds
Started Jul 13 05:53:31 PM PDT 24
Finished Jul 13 05:53:44 PM PDT 24
Peak memory 183052 kb
Host smart-8a4b708e-7915-4e06-946a-5a9ccd05ba0b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497991731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.497991731
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1018202436
Short name T398
Test name
Test status
Simulation time 154498728240 ps
CPU time 227.43 seconds
Started Jul 13 05:53:37 PM PDT 24
Finished Jul 13 05:57:25 PM PDT 24
Peak memory 183116 kb
Host smart-37400e07-7ad9-4ad8-a7e1-46c421b8f46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018202436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1018202436
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.3522944810
Short name T1
Test name
Test status
Simulation time 120445649081 ps
CPU time 665.82 seconds
Started Jul 13 05:53:39 PM PDT 24
Finished Jul 13 06:04:47 PM PDT 24
Peak memory 191332 kb
Host smart-bf8f66d9-fa02-40d7-af11-19556f9c7b8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522944810 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3522944810
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.3654609619
Short name T374
Test name
Test status
Simulation time 267832592 ps
CPU time 1.19 seconds
Started Jul 13 05:53:30 PM PDT 24
Finished Jul 13 05:53:32 PM PDT 24
Peak memory 182976 kb
Host smart-4ae4437d-5073-4eda-bba9-d9c7e8f5b8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654609619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.3654609619
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3600548097
Short name T204
Test name
Test status
Simulation time 713809611298 ps
CPU time 678.7 seconds
Started Jul 13 05:52:53 PM PDT 24
Finished Jul 13 06:04:13 PM PDT 24
Peak memory 183052 kb
Host smart-4770ba4e-5756-4ae7-b13a-6f6e306d9d0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600548097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3600548097
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.2342265060
Short name T62
Test name
Test status
Simulation time 160433865752 ps
CPU time 120.07 seconds
Started Jul 13 05:52:54 PM PDT 24
Finished Jul 13 05:54:55 PM PDT 24
Peak memory 183072 kb
Host smart-797cde71-c9fd-4841-abdf-b12ef35547da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342265060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.2342265060
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.410948108
Short name T63
Test name
Test status
Simulation time 24387801141 ps
CPU time 39.75 seconds
Started Jul 13 05:52:54 PM PDT 24
Finished Jul 13 05:53:35 PM PDT 24
Peak memory 183100 kb
Host smart-1b56516a-4342-4a3d-92f3-5bdda206a161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410948108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.410948108
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.1268187081
Short name T234
Test name
Test status
Simulation time 373665061613 ps
CPU time 490.51 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:01:50 PM PDT 24
Peak memory 191324 kb
Host smart-c58ce26b-9738-4a7e-ab36-3972f7cb5e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268187081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.1268187081
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.3758162842
Short name T246
Test name
Test status
Simulation time 175126308983 ps
CPU time 726.22 seconds
Started Jul 13 05:53:32 PM PDT 24
Finished Jul 13 06:05:39 PM PDT 24
Peak memory 194360 kb
Host smart-f6e09da9-e0d3-44a1-951f-088134259652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758162842 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3758162842
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.1985023682
Short name T329
Test name
Test status
Simulation time 119473032487 ps
CPU time 220.4 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:57:20 PM PDT 24
Peak memory 191092 kb
Host smart-5ed02e3e-e703-4f31-bf5f-3243f95bb4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985023682 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.1985023682
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.1886957894
Short name T305
Test name
Test status
Simulation time 897695783592 ps
CPU time 1418.46 seconds
Started Jul 13 05:53:31 PM PDT 24
Finished Jul 13 06:17:11 PM PDT 24
Peak memory 191300 kb
Host smart-c27fca67-af5b-40b1-8a6a-3304a99154d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886957894 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.1886957894
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3183441201
Short name T2
Test name
Test status
Simulation time 698967349589 ps
CPU time 614.53 seconds
Started Jul 13 05:53:39 PM PDT 24
Finished Jul 13 06:03:55 PM PDT 24
Peak memory 191276 kb
Host smart-d3a67050-7af7-496c-bda3-318d96c3b0ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183441201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3183441201
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1557650585
Short name T190
Test name
Test status
Simulation time 154858139213 ps
CPU time 717.56 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:05:37 PM PDT 24
Peak memory 193136 kb
Host smart-2bf213c5-10ca-400c-879b-e58aa6d63f52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557650585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1557650585
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.29009110
Short name T319
Test name
Test status
Simulation time 240603736664 ps
CPU time 226.44 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:57:26 PM PDT 24
Peak memory 191264 kb
Host smart-85efbd5b-3d24-4206-895d-be65bf925d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29009110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.29009110
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2816135
Short name T311
Test name
Test status
Simulation time 822208985116 ps
CPU time 439.98 seconds
Started Jul 13 05:53:39 PM PDT 24
Finished Jul 13 06:01:01 PM PDT 24
Peak memory 191312 kb
Host smart-4be959de-49ef-4f78-80ef-852fd236e3a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816135 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2816135
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.4289457277
Short name T428
Test name
Test status
Simulation time 11398472686 ps
CPU time 6.36 seconds
Started Jul 13 05:52:51 PM PDT 24
Finished Jul 13 05:52:58 PM PDT 24
Peak memory 183096 kb
Host smart-1b5b02f8-fa5a-4124-a429-90aca1758de6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289457277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.4289457277
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.3870972861
Short name T400
Test name
Test status
Simulation time 436922771000 ps
CPU time 304.22 seconds
Started Jul 13 05:52:54 PM PDT 24
Finished Jul 13 05:58:00 PM PDT 24
Peak memory 183032 kb
Host smart-fea8dd65-63d1-494a-b0aa-1fb9b175c48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870972861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.3870972861
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2600056322
Short name T115
Test name
Test status
Simulation time 78928475599 ps
CPU time 160.42 seconds
Started Jul 13 05:52:53 PM PDT 24
Finished Jul 13 05:55:34 PM PDT 24
Peak memory 191292 kb
Host smart-1c0287f4-1497-44a7-9fd3-b221b6271bfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600056322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2600056322
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3819340332
Short name T252
Test name
Test status
Simulation time 8989476558 ps
CPU time 15.15 seconds
Started Jul 13 05:52:56 PM PDT 24
Finished Jul 13 05:53:12 PM PDT 24
Peak memory 183108 kb
Host smart-45caaebe-3f01-42ee-9d42-14c498f8722a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819340332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3819340332
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.3198514393
Short name T27
Test name
Test status
Simulation time 517335389810 ps
CPU time 711.22 seconds
Started Jul 13 05:53:32 PM PDT 24
Finished Jul 13 06:05:24 PM PDT 24
Peak memory 191248 kb
Host smart-a10830ad-7c91-4f07-aece-56f476f58c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198514393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.3198514393
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.2876348148
Short name T23
Test name
Test status
Simulation time 136413151306 ps
CPU time 222.11 seconds
Started Jul 13 05:53:39 PM PDT 24
Finished Jul 13 05:57:23 PM PDT 24
Peak memory 191312 kb
Host smart-988d3510-e0a7-4348-9f34-61e883dcf0b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876348148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2876348148
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1816124930
Short name T45
Test name
Test status
Simulation time 62501845 ps
CPU time 0.61 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:53:41 PM PDT 24
Peak memory 182912 kb
Host smart-0d8d5b05-a1c7-402a-9f4c-314cf5adae40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816124930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1816124930
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.1328775924
Short name T262
Test name
Test status
Simulation time 170227051134 ps
CPU time 178.9 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:56:38 PM PDT 24
Peak memory 191332 kb
Host smart-27b5c661-2c16-4187-aeff-89113fd1cb81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328775924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.1328775924
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1643299274
Short name T409
Test name
Test status
Simulation time 111713308519 ps
CPU time 153.59 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:56:14 PM PDT 24
Peak memory 194752 kb
Host smart-d6b144ab-ebb4-4e43-ad93-641ead98aafc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643299274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1643299274
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.3298723021
Short name T138
Test name
Test status
Simulation time 395706787929 ps
CPU time 517.94 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:02:18 PM PDT 24
Peak memory 191296 kb
Host smart-a8325948-d58b-40c4-8169-39fc941b6f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298723021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.3298723021
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1806605930
Short name T342
Test name
Test status
Simulation time 175387429186 ps
CPU time 43.98 seconds
Started Jul 13 05:53:42 PM PDT 24
Finished Jul 13 05:54:26 PM PDT 24
Peak memory 182892 kb
Host smart-b1507139-806d-452e-a859-5bfbeb357111
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806605930 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1806605930
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.787135944
Short name T228
Test name
Test status
Simulation time 127896813427 ps
CPU time 1937.12 seconds
Started Jul 13 05:53:37 PM PDT 24
Finished Jul 13 06:25:55 PM PDT 24
Peak memory 191216 kb
Host smart-296672aa-56de-407e-964b-91d98e0d58b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787135944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.787135944
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.3837448936
Short name T277
Test name
Test status
Simulation time 671946095130 ps
CPU time 614.82 seconds
Started Jul 13 05:52:53 PM PDT 24
Finished Jul 13 06:03:10 PM PDT 24
Peak memory 183116 kb
Host smart-0f8ff767-65e9-402d-a309-43286cb8e697
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837448936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.3837448936
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3773500306
Short name T355
Test name
Test status
Simulation time 26834755553 ps
CPU time 40.82 seconds
Started Jul 13 05:52:54 PM PDT 24
Finished Jul 13 05:53:36 PM PDT 24
Peak memory 183024 kb
Host smart-953b3b6d-d0c2-4903-98bf-6d75b59e23e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773500306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3773500306
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.121846177
Short name T324
Test name
Test status
Simulation time 34030098394 ps
CPU time 447.35 seconds
Started Jul 13 05:52:54 PM PDT 24
Finished Jul 13 06:00:22 PM PDT 24
Peak memory 191312 kb
Host smart-5acc0bdd-f230-4b25-b089-ea3763d5d2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121846177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.121846177
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.679250130
Short name T359
Test name
Test status
Simulation time 1267965499 ps
CPU time 1.92 seconds
Started Jul 13 05:52:52 PM PDT 24
Finished Jul 13 05:52:55 PM PDT 24
Peak memory 193284 kb
Host smart-cb688270-28cf-4cc7-bf52-6aba0437e9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679250130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.679250130
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.758697899
Short name T158
Test name
Test status
Simulation time 230961939332 ps
CPU time 106.73 seconds
Started Jul 13 05:53:37 PM PDT 24
Finished Jul 13 05:55:25 PM PDT 24
Peak memory 191328 kb
Host smart-14303f90-3fce-40c8-917e-43eda5e39752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758697899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.758697899
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.340836080
Short name T152
Test name
Test status
Simulation time 240751510770 ps
CPU time 338.26 seconds
Started Jul 13 05:53:40 PM PDT 24
Finished Jul 13 05:59:20 PM PDT 24
Peak memory 194832 kb
Host smart-01744413-c161-4613-83cb-325c58c77a70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340836080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.340836080
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2719742342
Short name T61
Test name
Test status
Simulation time 56079195145 ps
CPU time 46.81 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:54:27 PM PDT 24
Peak memory 183124 kb
Host smart-8e59bda0-f3cf-493c-b6e8-d761c841e6f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719742342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2719742342
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3873429314
Short name T412
Test name
Test status
Simulation time 17467032744 ps
CPU time 8.87 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:53:49 PM PDT 24
Peak memory 183132 kb
Host smart-8a09f354-6c6f-4b6a-a94a-04cc5ab3c92a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873429314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3873429314
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1284145749
Short name T257
Test name
Test status
Simulation time 136659140286 ps
CPU time 338.63 seconds
Started Jul 13 05:53:37 PM PDT 24
Finished Jul 13 05:59:16 PM PDT 24
Peak memory 191220 kb
Host smart-32da4572-bfd3-439f-ab32-59e313b7f6f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284145749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1284145749
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.754271336
Short name T261
Test name
Test status
Simulation time 128399114710 ps
CPU time 621.71 seconds
Started Jul 13 05:53:36 PM PDT 24
Finished Jul 13 06:03:58 PM PDT 24
Peak memory 191240 kb
Host smart-d8644307-6df7-494b-8e12-b1bf3cd92f81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754271336 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.754271336
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.638863943
Short name T137
Test name
Test status
Simulation time 395879938032 ps
CPU time 706.27 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:05:27 PM PDT 24
Peak memory 191264 kb
Host smart-e73d0aa5-af3d-496b-843a-7d9b30cb3118
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638863943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.638863943
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.3761593510
Short name T141
Test name
Test status
Simulation time 372531558197 ps
CPU time 284.53 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 05:58:24 PM PDT 24
Peak memory 191324 kb
Host smart-e8bd1e43-0bf3-41d7-8d50-7572cf0cae51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761593510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.3761593510
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2058455462
Short name T9
Test name
Test status
Simulation time 141049260031 ps
CPU time 181.99 seconds
Started Jul 13 05:52:55 PM PDT 24
Finished Jul 13 05:55:57 PM PDT 24
Peak memory 183108 kb
Host smart-a6251b33-a4ac-468b-8e29-e730c4d96721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058455462 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2058455462
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3669389659
Short name T275
Test name
Test status
Simulation time 71199505149 ps
CPU time 1279.97 seconds
Started Jul 13 05:52:55 PM PDT 24
Finished Jul 13 06:14:16 PM PDT 24
Peak memory 183132 kb
Host smart-fdb59d50-1012-4107-98ec-eca395fc286d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669389659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3669389659
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3987594675
Short name T64
Test name
Test status
Simulation time 175433391538 ps
CPU time 81.71 seconds
Started Jul 13 05:52:54 PM PDT 24
Finished Jul 13 05:54:17 PM PDT 24
Peak memory 183124 kb
Host smart-343dd5d1-3032-4d34-bcbc-430614662b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987594675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3987594675
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.1701489945
Short name T131
Test name
Test status
Simulation time 72976688377 ps
CPU time 100.23 seconds
Started Jul 13 05:53:37 PM PDT 24
Finished Jul 13 05:55:18 PM PDT 24
Peak memory 193472 kb
Host smart-3be9c4fb-edaa-4b66-9e68-ae76968d7f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701489945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.1701489945
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.1937470778
Short name T352
Test name
Test status
Simulation time 33133582397 ps
CPU time 24 seconds
Started Jul 13 05:53:39 PM PDT 24
Finished Jul 13 05:54:05 PM PDT 24
Peak memory 183044 kb
Host smart-38e1b129-2f47-4f46-9f01-36f911254505
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937470778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1937470778
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.3260390555
Short name T396
Test name
Test status
Simulation time 430527595705 ps
CPU time 401.94 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:00:22 PM PDT 24
Peak memory 191324 kb
Host smart-9baad821-5fec-4169-8f90-31213492debd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260390555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.3260390555
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3685961565
Short name T192
Test name
Test status
Simulation time 527858548841 ps
CPU time 812.99 seconds
Started Jul 13 05:53:38 PM PDT 24
Finished Jul 13 06:07:13 PM PDT 24
Peak memory 194560 kb
Host smart-449470e0-0bc3-4593-b662-53d18a5b2cf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685961565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3685961565
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2176443974
Short name T298
Test name
Test status
Simulation time 139721555806 ps
CPU time 389.64 seconds
Started Jul 13 05:53:36 PM PDT 24
Finished Jul 13 06:00:06 PM PDT 24
Peak memory 191300 kb
Host smart-f7d4a131-fcc1-4d3f-bddd-b15f7da00f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176443974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2176443974
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2671343503
Short name T218
Test name
Test status
Simulation time 105133315109 ps
CPU time 245.37 seconds
Started Jul 13 05:53:46 PM PDT 24
Finished Jul 13 05:57:52 PM PDT 24
Peak memory 193360 kb
Host smart-300a3955-acdf-449f-903a-83a6aa240f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671343503 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2671343503
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3278318493
Short name T265
Test name
Test status
Simulation time 281800484637 ps
CPU time 111.15 seconds
Started Jul 13 05:53:46 PM PDT 24
Finished Jul 13 05:55:37 PM PDT 24
Peak memory 193440 kb
Host smart-15de769a-0535-4a92-a749-a60358a8ef85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278318493 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3278318493
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3044445701
Short name T230
Test name
Test status
Simulation time 838426998606 ps
CPU time 334.67 seconds
Started Jul 13 05:53:49 PM PDT 24
Finished Jul 13 05:59:24 PM PDT 24
Peak memory 191092 kb
Host smart-f731898d-1df4-4912-a56e-a21216fd61a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044445701 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3044445701
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.313318824
Short name T429
Test name
Test status
Simulation time 1053881163239 ps
CPU time 501.61 seconds
Started Jul 13 05:53:10 PM PDT 24
Finished Jul 13 06:01:33 PM PDT 24
Peak memory 182984 kb
Host smart-97578b81-2ea3-40ae-a841-e132c667e05a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313318824 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.313318824
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.4071403307
Short name T414
Test name
Test status
Simulation time 519469607912 ps
CPU time 123.88 seconds
Started Jul 13 05:52:54 PM PDT 24
Finished Jul 13 05:54:59 PM PDT 24
Peak memory 183124 kb
Host smart-9c29a29d-a681-4e2d-a6c4-65dfff6551c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071403307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.4071403307
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.1691790288
Short name T438
Test name
Test status
Simulation time 66660712586 ps
CPU time 106.43 seconds
Started Jul 13 05:52:53 PM PDT 24
Finished Jul 13 05:54:40 PM PDT 24
Peak memory 191272 kb
Host smart-af2bcc94-1224-452d-b8fd-b4ecb9bb7d11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691790288 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.1691790288
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.2888620095
Short name T283
Test name
Test status
Simulation time 11374226109 ps
CPU time 19.79 seconds
Started Jul 13 05:53:04 PM PDT 24
Finished Jul 13 05:53:25 PM PDT 24
Peak memory 191324 kb
Host smart-c71f4069-3c9a-4e1a-8047-3fbf05cf4f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888620095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.2888620095
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.740667226
Short name T250
Test name
Test status
Simulation time 789261537647 ps
CPU time 1721.2 seconds
Started Jul 13 05:53:06 PM PDT 24
Finished Jul 13 06:21:49 PM PDT 24
Peak memory 183100 kb
Host smart-46633c1a-6f06-4de4-ad82-4ccbf19ca4ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740667226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.740667226
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.1448921477
Short name T151
Test name
Test status
Simulation time 83845718525 ps
CPU time 116.79 seconds
Started Jul 13 05:53:44 PM PDT 24
Finished Jul 13 05:55:42 PM PDT 24
Peak memory 191316 kb
Host smart-0da09ad6-39ca-438a-a1d8-cbea9fdb2dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448921477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1448921477
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3663734057
Short name T264
Test name
Test status
Simulation time 141884569477 ps
CPU time 267.84 seconds
Started Jul 13 05:53:44 PM PDT 24
Finished Jul 13 05:58:13 PM PDT 24
Peak memory 191292 kb
Host smart-28a4fec4-e1f4-4a5e-932a-831b240c90bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663734057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3663734057
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.604114968
Short name T328
Test name
Test status
Simulation time 58763963509 ps
CPU time 89.63 seconds
Started Jul 13 05:53:57 PM PDT 24
Finished Jul 13 05:55:27 PM PDT 24
Peak memory 191252 kb
Host smart-77151f4a-6408-4d9d-9afe-a735142b868d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604114968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.604114968
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3040822819
Short name T196
Test name
Test status
Simulation time 173900388682 ps
CPU time 171.48 seconds
Started Jul 13 05:53:45 PM PDT 24
Finished Jul 13 05:56:37 PM PDT 24
Peak memory 191248 kb
Host smart-ce45b763-7c52-48e5-896b-dd97a536804f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040822819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3040822819
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.1944812686
Short name T341
Test name
Test status
Simulation time 240240227093 ps
CPU time 142.01 seconds
Started Jul 13 05:53:44 PM PDT 24
Finished Jul 13 05:56:06 PM PDT 24
Peak memory 191300 kb
Host smart-c703cd53-a25c-438b-bc7b-a2425b3805fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944812686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.1944812686
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2130146346
Short name T132
Test name
Test status
Simulation time 213819061223 ps
CPU time 88.06 seconds
Started Jul 13 05:53:46 PM PDT 24
Finished Jul 13 05:55:14 PM PDT 24
Peak memory 191300 kb
Host smart-22948325-fb34-4a63-b55d-22d40ae9f692
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130146346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2130146346
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.2696590662
Short name T231
Test name
Test status
Simulation time 107017277270 ps
CPU time 390.55 seconds
Started Jul 13 05:53:56 PM PDT 24
Finished Jul 13 06:00:27 PM PDT 24
Peak memory 190836 kb
Host smart-92cd0676-adda-4dcf-9cdd-ce254dac381b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696590662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.2696590662
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1601203952
Short name T60
Test name
Test status
Simulation time 784572528602 ps
CPU time 339.79 seconds
Started Jul 13 05:53:44 PM PDT 24
Finished Jul 13 05:59:24 PM PDT 24
Peak memory 191300 kb
Host smart-345a6920-61e7-40db-9b65-06fa16bcbfe2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601203952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1601203952
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.749838033
Short name T268
Test name
Test status
Simulation time 153894409837 ps
CPU time 436.58 seconds
Started Jul 13 05:53:45 PM PDT 24
Finished Jul 13 06:01:02 PM PDT 24
Peak memory 191296 kb
Host smart-b649527b-9d69-454c-8255-ebe3506aef2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749838033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.749838033
Directory /workspace/99.rv_timer_random/latest
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