Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 579
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T507 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4078022804 Jul 14 04:23:05 PM PDT 24 Jul 14 04:23:07 PM PDT 24 24047258 ps
T508 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.419999743 Jul 14 04:17:09 PM PDT 24 Jul 14 04:17:11 PM PDT 24 34474988 ps
T71 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3731506221 Jul 14 04:17:11 PM PDT 24 Jul 14 04:17:15 PM PDT 24 32425384 ps
T509 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3892177959 Jul 14 04:22:01 PM PDT 24 Jul 14 04:22:03 PM PDT 24 23415484 ps
T510 /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3070401415 Jul 14 04:22:30 PM PDT 24 Jul 14 04:22:35 PM PDT 24 35717441 ps
T511 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3752337405 Jul 14 04:22:37 PM PDT 24 Jul 14 04:22:39 PM PDT 24 31118872 ps
T512 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3207016096 Jul 14 04:22:27 PM PDT 24 Jul 14 04:22:31 PM PDT 24 14333696 ps
T513 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3301457814 Jul 14 04:22:30 PM PDT 24 Jul 14 04:22:34 PM PDT 24 69928928 ps
T514 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3055283858 Jul 14 04:19:29 PM PDT 24 Jul 14 04:19:30 PM PDT 24 57469071 ps
T515 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3206925817 Jul 14 04:23:07 PM PDT 24 Jul 14 04:23:09 PM PDT 24 352695002 ps
T516 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3260134957 Jul 14 04:18:07 PM PDT 24 Jul 14 04:18:08 PM PDT 24 164313620 ps
T517 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3609131122 Jul 14 04:23:07 PM PDT 24 Jul 14 04:23:09 PM PDT 24 141554547 ps
T518 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1197792546 Jul 14 04:17:20 PM PDT 24 Jul 14 04:17:22 PM PDT 24 30667018 ps
T519 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2015533241 Jul 14 04:20:53 PM PDT 24 Jul 14 04:20:54 PM PDT 24 13457631 ps
T520 /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4038921681 Jul 14 04:17:11 PM PDT 24 Jul 14 04:17:15 PM PDT 24 112013488 ps
T72 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3980535201 Jul 14 04:17:11 PM PDT 24 Jul 14 04:17:14 PM PDT 24 24181409 ps
T521 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1332845582 Jul 14 04:18:53 PM PDT 24 Jul 14 04:18:55 PM PDT 24 402577373 ps
T522 /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1024789956 Jul 14 04:21:19 PM PDT 24 Jul 14 04:21:21 PM PDT 24 111446852 ps
T523 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4134502335 Jul 14 04:22:02 PM PDT 24 Jul 14 04:22:04 PM PDT 24 38340012 ps
T524 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3061072378 Jul 14 04:20:30 PM PDT 24 Jul 14 04:20:31 PM PDT 24 11338553 ps
T525 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2654369772 Jul 14 04:21:47 PM PDT 24 Jul 14 04:21:49 PM PDT 24 29681715 ps
T73 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3044402115 Jul 14 04:17:09 PM PDT 24 Jul 14 04:17:12 PM PDT 24 27020667 ps
T526 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3425438830 Jul 14 04:22:23 PM PDT 24 Jul 14 04:22:25 PM PDT 24 1862857821 ps
T527 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.820764790 Jul 14 04:20:42 PM PDT 24 Jul 14 04:20:43 PM PDT 24 14379634 ps
T528 /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2951124341 Jul 14 04:17:17 PM PDT 24 Jul 14 04:17:19 PM PDT 24 25979019 ps
T529 /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1201734009 Jul 14 04:17:02 PM PDT 24 Jul 14 04:17:03 PM PDT 24 64483245 ps
T530 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.784641090 Jul 14 04:17:12 PM PDT 24 Jul 14 04:17:15 PM PDT 24 80449167 ps
T531 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.980599276 Jul 14 04:22:31 PM PDT 24 Jul 14 04:22:34 PM PDT 24 1989004692 ps
T532 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2740032813 Jul 14 04:17:50 PM PDT 24 Jul 14 04:17:52 PM PDT 24 29516438 ps
T533 /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1075806726 Jul 14 04:17:12 PM PDT 24 Jul 14 04:17:15 PM PDT 24 91304906 ps
T534 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2966440293 Jul 14 04:17:17 PM PDT 24 Jul 14 04:17:18 PM PDT 24 45636113 ps
T535 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2068240456 Jul 14 04:22:07 PM PDT 24 Jul 14 04:22:09 PM PDT 24 21489999 ps
T536 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2517148425 Jul 14 04:20:43 PM PDT 24 Jul 14 04:20:45 PM PDT 24 428375332 ps
T537 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.886884756 Jul 14 04:22:18 PM PDT 24 Jul 14 04:22:19 PM PDT 24 86073949 ps
T538 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2892267843 Jul 14 04:17:09 PM PDT 24 Jul 14 04:17:11 PM PDT 24 44774432 ps
T539 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.422050033 Jul 14 04:22:37 PM PDT 24 Jul 14 04:22:38 PM PDT 24 33550056 ps
T540 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1491652879 Jul 14 04:22:27 PM PDT 24 Jul 14 04:22:31 PM PDT 24 12554289 ps
T541 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1225780575 Jul 14 04:17:09 PM PDT 24 Jul 14 04:17:12 PM PDT 24 83942777 ps
T542 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3327413729 Jul 14 04:23:30 PM PDT 24 Jul 14 04:23:34 PM PDT 24 38912670 ps
T543 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1346635117 Jul 14 04:21:49 PM PDT 24 Jul 14 04:21:52 PM PDT 24 53494945 ps
T544 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3398183226 Jul 14 04:17:09 PM PDT 24 Jul 14 04:17:12 PM PDT 24 113450745 ps
T74 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.945831338 Jul 14 04:18:04 PM PDT 24 Jul 14 04:18:05 PM PDT 24 55723853 ps
T545 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1829424750 Jul 14 04:21:49 PM PDT 24 Jul 14 04:21:51 PM PDT 24 53928808 ps
T546 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1210649676 Jul 14 04:17:21 PM PDT 24 Jul 14 04:17:22 PM PDT 24 28912297 ps
T547 /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3630901851 Jul 14 04:23:02 PM PDT 24 Jul 14 04:23:04 PM PDT 24 105116022 ps
T548 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.145045869 Jul 14 04:17:46 PM PDT 24 Jul 14 04:17:47 PM PDT 24 53998371 ps
T549 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.83502770 Jul 14 04:22:00 PM PDT 24 Jul 14 04:22:02 PM PDT 24 13549044 ps
T550 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3601091080 Jul 14 04:17:18 PM PDT 24 Jul 14 04:17:20 PM PDT 24 104088658 ps
T551 /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3525346850 Jul 14 04:22:33 PM PDT 24 Jul 14 04:22:36 PM PDT 24 85152787 ps
T552 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1221456937 Jul 14 04:17:28 PM PDT 24 Jul 14 04:17:29 PM PDT 24 40824241 ps
T553 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.72308886 Jul 14 04:17:31 PM PDT 24 Jul 14 04:17:32 PM PDT 24 21845798 ps
T75 /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.449771320 Jul 14 04:23:42 PM PDT 24 Jul 14 04:23:44 PM PDT 24 11942916 ps
T76 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1568673825 Jul 14 04:17:08 PM PDT 24 Jul 14 04:17:09 PM PDT 24 12087957 ps
T554 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3946773897 Jul 14 04:21:57 PM PDT 24 Jul 14 04:22:01 PM PDT 24 116791572 ps
T555 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3973471301 Jul 14 04:23:01 PM PDT 24 Jul 14 04:23:03 PM PDT 24 55936678 ps
T556 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.855728568 Jul 14 04:22:09 PM PDT 24 Jul 14 04:22:10 PM PDT 24 25251127 ps
T557 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2279459038 Jul 14 04:22:02 PM PDT 24 Jul 14 04:22:04 PM PDT 24 24900576 ps
T558 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2997653736 Jul 14 04:17:16 PM PDT 24 Jul 14 04:17:18 PM PDT 24 18002114 ps
T559 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2713538548 Jul 14 04:22:33 PM PDT 24 Jul 14 04:22:36 PM PDT 24 23272488 ps
T560 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1098059727 Jul 14 04:22:30 PM PDT 24 Jul 14 04:22:33 PM PDT 24 46447078 ps
T561 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2150159721 Jul 14 04:23:07 PM PDT 24 Jul 14 04:23:10 PM PDT 24 86061843 ps
T562 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1159353893 Jul 14 04:22:22 PM PDT 24 Jul 14 04:22:23 PM PDT 24 42967795 ps
T563 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.375640110 Jul 14 04:21:04 PM PDT 24 Jul 14 04:21:05 PM PDT 24 12522954 ps
T564 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2318272472 Jul 14 04:21:44 PM PDT 24 Jul 14 04:21:45 PM PDT 24 70761266 ps
T565 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3096419944 Jul 14 04:19:31 PM PDT 24 Jul 14 04:19:32 PM PDT 24 49252201 ps
T566 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2473778863 Jul 14 04:23:04 PM PDT 24 Jul 14 04:23:08 PM PDT 24 14222422 ps
T567 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.4271114590 Jul 14 04:22:28 PM PDT 24 Jul 14 04:22:31 PM PDT 24 16199448 ps
T568 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3428783134 Jul 14 04:17:45 PM PDT 24 Jul 14 04:17:47 PM PDT 24 521457376 ps
T569 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.532854641 Jul 14 04:18:07 PM PDT 24 Jul 14 04:18:08 PM PDT 24 19031937 ps
T570 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4144800041 Jul 14 04:17:22 PM PDT 24 Jul 14 04:17:23 PM PDT 24 418951062 ps
T571 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.663165030 Jul 14 04:22:18 PM PDT 24 Jul 14 04:22:20 PM PDT 24 44749864 ps
T572 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2553048310 Jul 14 04:22:30 PM PDT 24 Jul 14 04:22:33 PM PDT 24 19276994 ps
T573 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1798543482 Jul 14 04:18:03 PM PDT 24 Jul 14 04:18:06 PM PDT 24 49381446 ps
T574 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3517785616 Jul 14 04:22:42 PM PDT 24 Jul 14 04:22:46 PM PDT 24 28203496 ps
T575 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2278096121 Jul 14 04:17:10 PM PDT 24 Jul 14 04:17:15 PM PDT 24 158150086 ps
T576 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1157350899 Jul 14 04:17:20 PM PDT 24 Jul 14 04:17:22 PM PDT 24 138094206 ps
T577 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2947806759 Jul 14 04:21:04 PM PDT 24 Jul 14 04:21:06 PM PDT 24 53308636 ps
T578 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.4051323215 Jul 14 04:17:36 PM PDT 24 Jul 14 04:17:37 PM PDT 24 51020759 ps
T579 /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.523194498 Jul 14 04:22:23 PM PDT 24 Jul 14 04:22:24 PM PDT 24 49053539 ps

Test location /workspace/coverage/default/133.rv_timer_random.1628627825
Short name T3
Test name
Test status
Simulation time 1172943071957 ps
CPU time 3531.28 seconds
Started Jul 14 04:22:35 PM PDT 24
Finished Jul 14 05:21:27 PM PDT 24
Peak memory 191056 kb
Host smart-756c38c3-016c-4126-b66e-d0a92f92433e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628627825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.1628627825
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all_with_rand_reset.2590818845
Short name T12
Test name
Test status
Simulation time 62240674646 ps
CPU time 343.07 seconds
Started Jul 14 04:23:19 PM PDT 24
Finished Jul 14 04:29:03 PM PDT 24
Peak memory 197600 kb
Host smart-30f06a70-52bf-454b-84d3-f1d8eafa2670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590818845 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all_with_rand_reset.2590818845
Directory /workspace/49.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3630949519
Short name T11
Test name
Test status
Simulation time 4033240959866 ps
CPU time 6230.12 seconds
Started Jul 14 04:23:03 PM PDT 24
Finished Jul 14 06:06:56 PM PDT 24
Peak memory 188832 kb
Host smart-ae542ac9-8082-4af6-842f-451c9d3fe2b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630949519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3630949519
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.1034509173
Short name T94
Test name
Test status
Simulation time 258384151 ps
CPU time 1.34 seconds
Started Jul 14 04:22:37 PM PDT 24
Finished Jul 14 04:22:39 PM PDT 24
Peak memory 192536 kb
Host smart-5cf27fbf-d927-4a00-ae48-094b94f29c68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034509173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.1034509173
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.2575687312
Short name T53
Test name
Test status
Simulation time 2235824245836 ps
CPU time 1552.74 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:48:36 PM PDT 24
Peak memory 191112 kb
Host smart-fa9437da-16d1-4aa8-a555-54c2388b4dcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575687312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.2575687312
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.3773162105
Short name T101
Test name
Test status
Simulation time 527436205621 ps
CPU time 3662.29 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 05:23:34 PM PDT 24
Peak memory 190768 kb
Host smart-da463db4-9d55-4f53-bf4f-1dce3a4aba29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773162105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
3773162105
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.4058768252
Short name T110
Test name
Test status
Simulation time 6237498989961 ps
CPU time 2160.35 seconds
Started Jul 14 04:23:17 PM PDT 24
Finished Jul 14 04:59:19 PM PDT 24
Peak memory 190836 kb
Host smart-cf6c75e4-2b7f-42a6-bb15-e7602855a5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058768252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.4058768252
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.2556783437
Short name T108
Test name
Test status
Simulation time 9052200455800 ps
CPU time 2058.44 seconds
Started Jul 14 04:19:21 PM PDT 24
Finished Jul 14 04:53:39 PM PDT 24
Peak memory 195948 kb
Host smart-b5af6ef6-01a4-4818-880a-488d29cd6531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556783437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.2556783437
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.1056115883
Short name T41
Test name
Test status
Simulation time 395472033680 ps
CPU time 495.54 seconds
Started Jul 14 04:19:43 PM PDT 24
Finished Jul 14 04:28:00 PM PDT 24
Peak memory 189444 kb
Host smart-a9041c3b-a82a-4fd4-ab8c-69a47344ae19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056115883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.1056115883
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.2950865752
Short name T61
Test name
Test status
Simulation time 12313180 ps
CPU time 0.58 seconds
Started Jul 14 04:17:18 PM PDT 24
Finished Jul 14 04:17:19 PM PDT 24
Peak memory 181936 kb
Host smart-8f27e40f-b348-4ea7-8574-7ab6aec3c7a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950865752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.2950865752
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.3210504758
Short name T216
Test name
Test status
Simulation time 1787259719533 ps
CPU time 1512.75 seconds
Started Jul 14 04:21:18 PM PDT 24
Finished Jul 14 04:46:32 PM PDT 24
Peak memory 191152 kb
Host smart-e151b9b0-1322-476a-9078-30332b1c0ae1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210504758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.3210504758
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.888902983
Short name T162
Test name
Test status
Simulation time 971909348755 ps
CPU time 1312.6 seconds
Started Jul 14 04:23:18 PM PDT 24
Finished Jul 14 04:45:12 PM PDT 24
Peak memory 194676 kb
Host smart-d97e297d-1fd1-49f4-99fa-65d0864b3b3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888902983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all.
888902983
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.578622075
Short name T148
Test name
Test status
Simulation time 1312978086980 ps
CPU time 3718.04 seconds
Started Jul 14 04:18:32 PM PDT 24
Finished Jul 14 05:20:31 PM PDT 24
Peak memory 191244 kb
Host smart-79337473-0e27-4cc0-a997-d3c3d4d65b2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578622075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
578622075
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.2117311557
Short name T16
Test name
Test status
Simulation time 764805533 ps
CPU time 0.82 seconds
Started Jul 14 04:17:07 PM PDT 24
Finished Jul 14 04:17:09 PM PDT 24
Peak memory 212608 kb
Host smart-5fe5c625-f81e-4442-a749-16fd0c6421dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117311557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.2117311557
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.447567284
Short name T100
Test name
Test status
Simulation time 510084768164 ps
CPU time 1095.8 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:41:50 PM PDT 24
Peak memory 190988 kb
Host smart-fcc80d2a-e160-4c7d-a457-e4df22b7870a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447567284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
447567284
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.473336179
Short name T43
Test name
Test status
Simulation time 2652513328264 ps
CPU time 2269.59 seconds
Started Jul 14 04:19:50 PM PDT 24
Finished Jul 14 04:57:41 PM PDT 24
Peak memory 191256 kb
Host smart-087a2277-3a28-4e6c-9270-414daaf0cdc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473336179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
473336179
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.2202658114
Short name T235
Test name
Test status
Simulation time 435562747859 ps
CPU time 954.53 seconds
Started Jul 14 04:19:13 PM PDT 24
Finished Jul 14 04:35:08 PM PDT 24
Peak memory 191100 kb
Host smart-58e4b220-df43-401e-815b-b12580b393a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202658114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.2202658114
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3968168125
Short name T287
Test name
Test status
Simulation time 1820486888218 ps
CPU time 998.69 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:38:40 PM PDT 24
Peak memory 190908 kb
Host smart-e612d80f-7bdd-455d-8b63-a206c826c1b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968168125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3968168125
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/181.rv_timer_random.2637180040
Short name T10
Test name
Test status
Simulation time 569331483163 ps
CPU time 422.81 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:29:46 PM PDT 24
Peak memory 191152 kb
Host smart-d191b135-d09d-4a94-840c-11ba7d85417c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637180040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2637180040
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.1600190272
Short name T44
Test name
Test status
Simulation time 367344316281 ps
CPU time 829.12 seconds
Started Jul 14 04:19:54 PM PDT 24
Finished Jul 14 04:33:44 PM PDT 24
Peak memory 194240 kb
Host smart-64e8d07c-34d6-48ca-aa07-3be9f74e8cc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600190272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.1600190272
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.2751725903
Short name T55
Test name
Test status
Simulation time 535121114536 ps
CPU time 1361.21 seconds
Started Jul 14 04:18:45 PM PDT 24
Finished Jul 14 04:41:27 PM PDT 24
Peak memory 195888 kb
Host smart-fdeea5f3-8a55-4374-830b-15c06bfe5307
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751725903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
2751725903
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/102.rv_timer_random.3118272629
Short name T116
Test name
Test status
Simulation time 239538064621 ps
CPU time 391.59 seconds
Started Jul 14 04:23:18 PM PDT 24
Finished Jul 14 04:29:51 PM PDT 24
Peak memory 191084 kb
Host smart-4e2ac557-076c-47a3-aeb8-1f15c85158fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118272629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3118272629
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.3389623327
Short name T154
Test name
Test status
Simulation time 964507387564 ps
CPU time 1412.3 seconds
Started Jul 14 04:19:43 PM PDT 24
Finished Jul 14 04:43:17 PM PDT 24
Peak memory 189740 kb
Host smart-7ef16829-823d-49d8-aaac-fb8257309eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389623327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.3389623327
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/97.rv_timer_random.1499586753
Short name T156
Test name
Test status
Simulation time 128715426773 ps
CPU time 194.65 seconds
Started Jul 14 04:21:42 PM PDT 24
Finished Jul 14 04:24:57 PM PDT 24
Peak memory 191524 kb
Host smart-3862cdb7-4eb2-4a44-9d44-0433ef327e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499586753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1499586753
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.1308612066
Short name T133
Test name
Test status
Simulation time 594939353329 ps
CPU time 1033.86 seconds
Started Jul 14 04:22:44 PM PDT 24
Finished Jul 14 04:40:01 PM PDT 24
Peak memory 193504 kb
Host smart-b7371f39-322f-4462-9bc0-283104a219fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308612066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.1308612066
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.60824789
Short name T292
Test name
Test status
Simulation time 276130131312 ps
CPU time 1031.44 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:40:47 PM PDT 24
Peak memory 190988 kb
Host smart-d978352a-201f-41a9-8c2e-b5536a88427b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60824789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.60824789
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.4231605567
Short name T251
Test name
Test status
Simulation time 362806615073 ps
CPU time 1637.28 seconds
Started Jul 14 04:22:32 PM PDT 24
Finished Jul 14 04:49:52 PM PDT 24
Peak memory 189476 kb
Host smart-1e940e93-4612-4bb4-993a-8bc3d7b2d7ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231605567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4231605567
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.4169821544
Short name T172
Test name
Test status
Simulation time 194020572972 ps
CPU time 104.62 seconds
Started Jul 14 04:23:02 PM PDT 24
Finished Jul 14 04:24:48 PM PDT 24
Peak memory 190456 kb
Host smart-c897b0ea-7324-4b4f-b6bf-9242c8bcd1dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169821544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4169821544
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1321043345
Short name T48
Test name
Test status
Simulation time 610840048846 ps
CPU time 270.95 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:27:33 PM PDT 24
Peak memory 189236 kb
Host smart-948bbc21-166a-4e13-8e7b-a80c47e4d264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321043345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1321043345
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.736621124
Short name T136
Test name
Test status
Simulation time 629463537758 ps
CPU time 635.33 seconds
Started Jul 14 04:22:39 PM PDT 24
Finished Jul 14 04:33:15 PM PDT 24
Peak memory 191104 kb
Host smart-78d1c562-55c5-49c3-b251-b2bf6b89a9cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736621124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.736621124
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.4125261235
Short name T145
Test name
Test status
Simulation time 383502947985 ps
CPU time 635.23 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:33:18 PM PDT 24
Peak memory 191108 kb
Host smart-7c16aed3-0170-4ea0-8257-b3c03da502ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125261235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.4125261235
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.3541543713
Short name T169
Test name
Test status
Simulation time 272397628947 ps
CPU time 644.03 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:33:30 PM PDT 24
Peak memory 191068 kb
Host smart-8fb4490d-8269-4cb8-86fc-47af89f3f1ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541543713 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3541543713
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.3727146129
Short name T144
Test name
Test status
Simulation time 786733187267 ps
CPU time 287.85 seconds
Started Jul 14 04:18:44 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 191092 kb
Host smart-4ccf9c14-b959-430d-99a9-3d87a52d2511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727146129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3727146129
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3715059495
Short name T208
Test name
Test status
Simulation time 78948683386 ps
CPU time 206.21 seconds
Started Jul 14 04:22:14 PM PDT 24
Finished Jul 14 04:25:41 PM PDT 24
Peak memory 191236 kb
Host smart-9a801384-3e91-4bd0-97e8-d309df909003
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715059495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3715059495
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1638239186
Short name T180
Test name
Test status
Simulation time 78396922605 ps
CPU time 161.08 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:25:26 PM PDT 24
Peak memory 191108 kb
Host smart-406c5f6c-69d2-4538-a16f-a59fd9744fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638239186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1638239186
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.3552567454
Short name T152
Test name
Test status
Simulation time 146321025210 ps
CPU time 668.79 seconds
Started Jul 14 04:22:54 PM PDT 24
Finished Jul 14 04:34:03 PM PDT 24
Peak memory 191064 kb
Host smart-29803568-6248-4670-81f0-36c0427cc313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552567454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.3552567454
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3615328542
Short name T209
Test name
Test status
Simulation time 468465256057 ps
CPU time 255.61 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:26:59 PM PDT 24
Peak memory 191148 kb
Host smart-64c78edf-56c6-4e05-8c75-5581a899c9d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615328542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3615328542
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2073566042
Short name T220
Test name
Test status
Simulation time 5900664174724 ps
CPU time 1988.21 seconds
Started Jul 14 04:20:06 PM PDT 24
Finished Jul 14 04:53:14 PM PDT 24
Peak memory 191256 kb
Host smart-38bef7ec-3ecd-4fea-b06c-4a8b00a08ebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073566042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2073566042
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/89.rv_timer_random.2531683435
Short name T263
Test name
Test status
Simulation time 1531040501794 ps
CPU time 405.84 seconds
Started Jul 14 04:22:52 PM PDT 24
Finished Jul 14 04:29:38 PM PDT 24
Peak memory 191044 kb
Host smart-339b6f4a-9827-4ec4-9685-143f3f529f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531683435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.2531683435
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2939344128
Short name T129
Test name
Test status
Simulation time 1036533401849 ps
CPU time 1163.32 seconds
Started Jul 14 04:19:33 PM PDT 24
Finished Jul 14 04:38:57 PM PDT 24
Peak memory 195276 kb
Host smart-c6fbc53d-7de2-4136-888c-0f0b99e9dd28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939344128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2939344128
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.1003072650
Short name T255
Test name
Test status
Simulation time 227710414271 ps
CPU time 191.51 seconds
Started Jul 14 04:22:32 PM PDT 24
Finished Jul 14 04:25:46 PM PDT 24
Peak memory 181096 kb
Host smart-c9a9180f-e5f9-49b2-8586-bb28b6869525
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003072650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.1003072650
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/130.rv_timer_random.1632635406
Short name T47
Test name
Test status
Simulation time 106730819078 ps
CPU time 1037 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:39:45 PM PDT 24
Peak memory 191148 kb
Host smart-b8b2a8e9-9f48-4f5d-a6c6-da6bb15b9ee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632635406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.1632635406
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.4224050547
Short name T122
Test name
Test status
Simulation time 3782440419180 ps
CPU time 1414.85 seconds
Started Jul 14 04:23:17 PM PDT 24
Finished Jul 14 04:46:53 PM PDT 24
Peak memory 182632 kb
Host smart-b43216b3-eae0-4e3f-916b-f4f01af17e67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224050547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.4224050547
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_random.1401117468
Short name T20
Test name
Test status
Simulation time 800375080073 ps
CPU time 1406.87 seconds
Started Jul 14 04:23:05 PM PDT 24
Finished Jul 14 04:46:34 PM PDT 24
Peak memory 189228 kb
Host smart-15850feb-2b4f-4767-abd3-4d29306e25f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401117468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1401117468
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random.2649929555
Short name T113
Test name
Test status
Simulation time 131241452325 ps
CPU time 135.16 seconds
Started Jul 14 04:22:44 PM PDT 24
Finished Jul 14 04:25:03 PM PDT 24
Peak memory 189472 kb
Host smart-cebd029c-f734-4b5f-8444-59616334623b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649929555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.2649929555
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random.2626201983
Short name T232
Test name
Test status
Simulation time 131854610302 ps
CPU time 472.42 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:30:00 PM PDT 24
Peak memory 191092 kb
Host smart-4487090d-8a9a-4f2c-a864-e62111ce9265
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626201983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2626201983
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2985771363
Short name T6
Test name
Test status
Simulation time 269545167835 ps
CPU time 138.88 seconds
Started Jul 14 04:23:14 PM PDT 24
Finished Jul 14 04:25:34 PM PDT 24
Peak memory 190984 kb
Host smart-cf8048d5-5702-4696-84cc-92d1a8411253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985771363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2985771363
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.333923874
Short name T109
Test name
Test status
Simulation time 410752769621 ps
CPU time 458.49 seconds
Started Jul 14 04:21:56 PM PDT 24
Finished Jul 14 04:29:36 PM PDT 24
Peak memory 191116 kb
Host smart-65944fff-8950-497a-9201-eeccff6ac600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333923874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.333923874
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.1552071415
Short name T192
Test name
Test status
Simulation time 135394664186 ps
CPU time 1033.81 seconds
Started Jul 14 04:23:04 PM PDT 24
Finished Jul 14 04:40:20 PM PDT 24
Peak memory 190408 kb
Host smart-806dcd1a-c07c-4770-adf0-29bf1ef16f01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552071415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.1552071415
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3546104332
Short name T115
Test name
Test status
Simulation time 594538102762 ps
CPU time 1008.88 seconds
Started Jul 14 04:22:20 PM PDT 24
Finished Jul 14 04:39:10 PM PDT 24
Peak memory 191244 kb
Host smart-81228ff2-aaf4-48a8-9a34-97b8bb009d24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546104332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3546104332
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.3211525863
Short name T140
Test name
Test status
Simulation time 553727074073 ps
CPU time 343.17 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:28:11 PM PDT 24
Peak memory 191148 kb
Host smart-6c11b16e-4f6e-42ad-b439-82d5de6dce29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211525863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.3211525863
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1508361884
Short name T434
Test name
Test status
Simulation time 765093758093 ps
CPU time 871.55 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:37:13 PM PDT 24
Peak memory 191104 kb
Host smart-f7bdeb4e-64ac-4aa3-80e9-951e0bdda65b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508361884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1508361884
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3590655144
Short name T338
Test name
Test status
Simulation time 77751594550 ps
CPU time 106.49 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:25:31 PM PDT 24
Peak memory 194152 kb
Host smart-ce4cd345-869f-413b-b672-e44a23b0945b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590655144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3590655144
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.84052072
Short name T294
Test name
Test status
Simulation time 123129975113 ps
CPU time 1356.51 seconds
Started Jul 14 04:22:50 PM PDT 24
Finished Jul 14 04:45:27 PM PDT 24
Peak memory 191280 kb
Host smart-2a93ec9e-d481-4366-afa4-b8b768f02071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84052072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.84052072
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.4019609555
Short name T82
Test name
Test status
Simulation time 698441826176 ps
CPU time 317.63 seconds
Started Jul 14 04:17:57 PM PDT 24
Finished Jul 14 04:23:15 PM PDT 24
Peak memory 182856 kb
Host smart-42a82235-da9e-48d6-92ec-578569f14673
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019609555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.4019609555
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1292585620
Short name T207
Test name
Test status
Simulation time 2470752649628 ps
CPU time 530.31 seconds
Started Jul 14 04:19:43 PM PDT 24
Finished Jul 14 04:28:35 PM PDT 24
Peak memory 181756 kb
Host smart-3852f3b0-680a-4e44-916c-39321547663e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292585620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1292585620
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.870535736
Short name T194
Test name
Test status
Simulation time 176049768224 ps
CPU time 242.27 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:25:59 PM PDT 24
Peak memory 181472 kb
Host smart-012cb0fb-630f-40cf-9abe-536507ba9ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870535736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.870535736
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/78.rv_timer_random.1364190065
Short name T250
Test name
Test status
Simulation time 64841833998 ps
CPU time 130.72 seconds
Started Jul 14 04:22:38 PM PDT 24
Finished Jul 14 04:24:50 PM PDT 24
Peak memory 191120 kb
Host smart-f34dda11-9b1a-467a-9891-c7282fc03612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364190065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1364190065
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2210564361
Short name T119
Test name
Test status
Simulation time 95818934053 ps
CPU time 152.46 seconds
Started Jul 14 04:17:08 PM PDT 24
Finished Jul 14 04:19:41 PM PDT 24
Peak memory 182652 kb
Host smart-036f4bff-2458-475c-b8a6-abb8caf7877c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210564361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2210564361
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/100.rv_timer_random.1875613561
Short name T314
Test name
Test status
Simulation time 177231135812 ps
CPU time 186.57 seconds
Started Jul 14 04:21:37 PM PDT 24
Finished Jul 14 04:24:44 PM PDT 24
Peak memory 193800 kb
Host smart-49ece8ea-40a5-4856-816f-d3c727cf74ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875613561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.1875613561
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3156213605
Short name T269
Test name
Test status
Simulation time 41515908217 ps
CPU time 35.23 seconds
Started Jul 14 04:23:14 PM PDT 24
Finished Jul 14 04:23:51 PM PDT 24
Peak memory 191044 kb
Host smart-31d9d3cb-90be-42dc-8b43-227299888580
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156213605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3156213605
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.4088232494
Short name T327
Test name
Test status
Simulation time 104639253008 ps
CPU time 199.74 seconds
Started Jul 14 04:23:23 PM PDT 24
Finished Jul 14 04:26:44 PM PDT 24
Peak memory 190392 kb
Host smart-8124ee7b-d00d-4e9a-999d-a5d9e815d773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088232494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.4088232494
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2381209278
Short name T205
Test name
Test status
Simulation time 454672034094 ps
CPU time 261.37 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:28:05 PM PDT 24
Peak memory 190928 kb
Host smart-ec6f6388-3008-4eed-a60a-07f1734ed36c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381209278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2381209278
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.3794122306
Short name T99
Test name
Test status
Simulation time 134812460766 ps
CPU time 225.64 seconds
Started Jul 14 04:22:01 PM PDT 24
Finished Jul 14 04:25:48 PM PDT 24
Peak memory 182888 kb
Host smart-239d0b7b-0d5f-4c9d-abd1-917d48f4d930
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794122306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.3794122306
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/185.rv_timer_random.2818131852
Short name T270
Test name
Test status
Simulation time 131754633932 ps
CPU time 711.12 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:34:37 PM PDT 24
Peak memory 191100 kb
Host smart-e8c986d8-b881-4949-9d4c-fffb5ec29733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818131852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.2818131852
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random.907586985
Short name T117
Test name
Test status
Simulation time 323275026295 ps
CPU time 354.96 seconds
Started Jul 14 04:22:33 PM PDT 24
Finished Jul 14 04:28:30 PM PDT 24
Peak memory 191100 kb
Host smart-0ef088bc-e6a6-482e-af9f-ca1f76393cfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907586985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.907586985
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random.1732634419
Short name T202
Test name
Test status
Simulation time 599864058325 ps
CPU time 360.16 seconds
Started Jul 14 04:17:43 PM PDT 24
Finished Jul 14 04:23:44 PM PDT 24
Peak memory 191092 kb
Host smart-96f2f52b-5022-4dbe-9324-20101e4989ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732634419 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1732634419
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.1496137344
Short name T211
Test name
Test status
Simulation time 6117201074055 ps
CPU time 1488.39 seconds
Started Jul 14 04:18:04 PM PDT 24
Finished Jul 14 04:42:53 PM PDT 24
Peak memory 182920 kb
Host smart-3342a924-9e55-4c02-9f9d-b94cf93678b6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496137344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.1496137344
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_random.4026887388
Short name T111
Test name
Test status
Simulation time 208181337122 ps
CPU time 689.84 seconds
Started Jul 14 04:21:57 PM PDT 24
Finished Jul 14 04:33:29 PM PDT 24
Peak memory 190788 kb
Host smart-270e3d19-ffc1-4765-b24b-134afa77e4fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026887388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.4026887388
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3959091941
Short name T280
Test name
Test status
Simulation time 1187913611 ps
CPU time 2.23 seconds
Started Jul 14 04:18:53 PM PDT 24
Finished Jul 14 04:18:56 PM PDT 24
Peak memory 182728 kb
Host smart-b8c4d820-3451-4546-8bc9-7df813308a30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959091941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3959091941
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.294021070
Short name T57
Test name
Test status
Simulation time 4334349636751 ps
CPU time 1219.32 seconds
Started Jul 14 04:21:57 PM PDT 24
Finished Jul 14 04:42:18 PM PDT 24
Peak memory 195580 kb
Host smart-5032f912-c58e-4875-ae70-e97f78bd1ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294021070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.294021070
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_random.1885886305
Short name T221
Test name
Test status
Simulation time 191584797241 ps
CPU time 588.94 seconds
Started Jul 14 04:22:19 PM PDT 24
Finished Jul 14 04:32:09 PM PDT 24
Peak memory 190388 kb
Host smart-be089856-91e1-4101-a05d-530d4cf239e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885886305 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1885886305
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.2846526858
Short name T243
Test name
Test status
Simulation time 859182371883 ps
CPU time 296.24 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:26:51 PM PDT 24
Peak memory 193504 kb
Host smart-00863aee-a47e-40bb-88bb-ae477aaa53a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846526858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2846526858
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.2984704334
Short name T471
Test name
Test status
Simulation time 177312459 ps
CPU time 0.79 seconds
Started Jul 14 04:17:11 PM PDT 24
Finished Jul 14 04:17:14 PM PDT 24
Peak memory 181732 kb
Host smart-1ca43b5e-7239-475d-ab7a-1f0148405a22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984704334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.2984704334
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.648249515
Short name T321
Test name
Test status
Simulation time 9821779431 ps
CPU time 5.72 seconds
Started Jul 14 04:17:11 PM PDT 24
Finished Jul 14 04:17:20 PM PDT 24
Peak memory 190932 kb
Host smart-c1e34b65-e93f-46c7-9f23-623a5dea32d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648249515 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.648249515
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_random.2533410949
Short name T230
Test name
Test status
Simulation time 487649344698 ps
CPU time 386.53 seconds
Started Jul 14 04:17:41 PM PDT 24
Finished Jul 14 04:24:08 PM PDT 24
Peak memory 191092 kb
Host smart-3166e3c5-8a79-43e8-9ecb-3dc79c6de88c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533410949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2533410949
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2640059563
Short name T142
Test name
Test status
Simulation time 719955844096 ps
CPU time 382.58 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:29:25 PM PDT 24
Peak memory 190136 kb
Host smart-5fbdcc7f-e246-40ff-89ba-b2f6d2bb0427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640059563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2640059563
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.4201924888
Short name T282
Test name
Test status
Simulation time 106077880252 ps
CPU time 180.07 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:24:55 PM PDT 24
Peak memory 182704 kb
Host smart-739b2e0e-9996-41a1-9c9b-86a28234da5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201924888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.4201924888
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/116.rv_timer_random.1786270863
Short name T409
Test name
Test status
Simulation time 125358095751 ps
CPU time 589.5 seconds
Started Jul 14 04:21:56 PM PDT 24
Finished Jul 14 04:31:48 PM PDT 24
Peak memory 191116 kb
Host smart-f0cce1ee-1696-4f0f-ac46-563daa8413d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786270863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1786270863
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1908875667
Short name T277
Test name
Test status
Simulation time 528590572501 ps
CPU time 429.95 seconds
Started Jul 14 04:17:55 PM PDT 24
Finished Jul 14 04:25:06 PM PDT 24
Peak memory 183036 kb
Host smart-d7480d70-54c5-478e-8b0b-5fbeeddfd7d7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908875667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1908875667
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_random.3818881718
Short name T46
Test name
Test status
Simulation time 119741390249 ps
CPU time 98.47 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 191120 kb
Host smart-d8860fbf-6043-4a2d-923f-70b075a110d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818881718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3818881718
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3887571416
Short name T256
Test name
Test status
Simulation time 116191225801 ps
CPU time 167.43 seconds
Started Jul 14 04:22:29 PM PDT 24
Finished Jul 14 04:25:18 PM PDT 24
Peak memory 182180 kb
Host smart-226a4faa-0bf3-4305-91c8-ab6452610a04
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887571416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3887571416
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/140.rv_timer_random.3270551289
Short name T257
Test name
Test status
Simulation time 95293579539 ps
CPU time 141.02 seconds
Started Jul 14 04:23:33 PM PDT 24
Finished Jul 14 04:25:58 PM PDT 24
Peak memory 189916 kb
Host smart-256da98c-9562-4547-bd3f-e8446c464c3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270551289 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3270551289
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.810027110
Short name T305
Test name
Test status
Simulation time 65838792351 ps
CPU time 1220.79 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:43:05 PM PDT 24
Peak memory 191052 kb
Host smart-886e0bdd-c81d-48f0-b523-f4627c2efd5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810027110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.810027110
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1382442984
Short name T186
Test name
Test status
Simulation time 110849226724 ps
CPU time 66.55 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:23:48 PM PDT 24
Peak memory 191104 kb
Host smart-3be5ae94-e772-4417-a7e3-c8b50c3801a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382442984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1382442984
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.2738611139
Short name T212
Test name
Test status
Simulation time 723310243046 ps
CPU time 1025.01 seconds
Started Jul 14 04:22:54 PM PDT 24
Finished Jul 14 04:39:59 PM PDT 24
Peak memory 191064 kb
Host smart-023f0a93-8d4b-49f0-b49c-88027ba68457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738611139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.2738611139
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3496000284
Short name T141
Test name
Test status
Simulation time 82142732305 ps
CPU time 230.56 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:26:34 PM PDT 24
Peak memory 191104 kb
Host smart-6a129ef7-4557-48a0-b8a2-dec2cd4cc292
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496000284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3496000284
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.3108277773
Short name T8
Test name
Test status
Simulation time 361508725892 ps
CPU time 284.43 seconds
Started Jul 14 04:22:33 PM PDT 24
Finished Jul 14 04:27:19 PM PDT 24
Peak memory 182884 kb
Host smart-59b272ec-f956-4929-ae4e-876c137732c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108277773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.3108277773
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/191.rv_timer_random.850400752
Short name T223
Test name
Test status
Simulation time 43011704906 ps
CPU time 70.19 seconds
Started Jul 14 04:22:48 PM PDT 24
Finished Jul 14 04:23:59 PM PDT 24
Peak memory 191088 kb
Host smart-f1b7ef80-9899-43ac-9643-b07eb51e25d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850400752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.850400752
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.807782279
Short name T204
Test name
Test status
Simulation time 110128573468 ps
CPU time 369.57 seconds
Started Jul 14 04:18:03 PM PDT 24
Finished Jul 14 04:24:13 PM PDT 24
Peak memory 191120 kb
Host smart-de8d658f-650e-46f8-ab07-348b80d18a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807782279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.807782279
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random.3459672897
Short name T299
Test name
Test status
Simulation time 395909090458 ps
CPU time 114.06 seconds
Started Jul 14 04:17:08 PM PDT 24
Finished Jul 14 04:19:03 PM PDT 24
Peak memory 191072 kb
Host smart-780e803e-6017-4436-a829-09160e0134fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459672897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.3459672897
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.2183683832
Short name T298
Test name
Test status
Simulation time 1151707999513 ps
CPU time 804.47 seconds
Started Jul 14 04:18:53 PM PDT 24
Finished Jul 14 04:32:18 PM PDT 24
Peak memory 191056 kb
Host smart-44887582-5946-4a26-a85e-cedcedb88837
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183683832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.2183683832
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random.1256681730
Short name T181
Test name
Test status
Simulation time 163604256924 ps
CPU time 1439.23 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:45:53 PM PDT 24
Peak memory 189928 kb
Host smart-b2dcf6ed-218b-4dd0-ab60-d13576c03291
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256681730 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.1256681730
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.2015207603
Short name T23
Test name
Test status
Simulation time 251007820264 ps
CPU time 119.32 seconds
Started Jul 14 04:22:27 PM PDT 24
Finished Jul 14 04:24:28 PM PDT 24
Peak memory 182208 kb
Host smart-6a8de019-652f-43fd-bcad-4017ae31a43e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015207603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.2015207603
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.2523189757
Short name T26
Test name
Test status
Simulation time 1262180962983 ps
CPU time 562.24 seconds
Started Jul 14 04:22:09 PM PDT 24
Finished Jul 14 04:31:33 PM PDT 24
Peak memory 190576 kb
Host smart-d20f2c02-79ef-4f74-bc25-64170312c6bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523189757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.2523189757
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.8124083
Short name T228
Test name
Test status
Simulation time 37133522902 ps
CPU time 54.56 seconds
Started Jul 14 04:21:57 PM PDT 24
Finished Jul 14 04:22:53 PM PDT 24
Peak memory 182656 kb
Host smart-44748495-c3ab-4bb1-be59-1df2823df96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8124083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.8124083
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.1677092261
Short name T118
Test name
Test status
Simulation time 523000558458 ps
CPU time 157.95 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:24:33 PM PDT 24
Peak memory 182252 kb
Host smart-ad864f31-f0c5-4fef-8e31-0f42016e9113
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677092261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.1677092261
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/88.rv_timer_random.2349631004
Short name T2
Test name
Test status
Simulation time 149190853401 ps
CPU time 375.98 seconds
Started Jul 14 04:23:03 PM PDT 24
Finished Jul 14 04:29:20 PM PDT 24
Peak memory 190764 kb
Host smart-bbf9cac2-19d5-4b64-8290-1655ba0dfa08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349631004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.2349631004
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.1225780575
Short name T541
Test name
Test status
Simulation time 83942777 ps
CPU time 0.82 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:12 PM PDT 24
Peak memory 180752 kb
Host smart-57776010-253a-475e-bae3-887508d5dbbc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225780575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.1225780575
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.749101332
Short name T467
Test name
Test status
Simulation time 277438308 ps
CPU time 2.68 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:14 PM PDT 24
Peak memory 190508 kb
Host smart-85b7608c-9d9c-40e0-8ef8-489dae85a6c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749101332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_b
ash.749101332
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.1210649676
Short name T546
Test name
Test status
Simulation time 28912297 ps
CPU time 0.58 seconds
Started Jul 14 04:17:21 PM PDT 24
Finished Jul 14 04:17:22 PM PDT 24
Peak memory 182156 kb
Host smart-4202bfe9-fd8d-4637-8e3b-0655cb981caa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210649676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.1210649676
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.784641090
Short name T530
Test name
Test status
Simulation time 80449167 ps
CPU time 0.92 seconds
Started Jul 14 04:17:12 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 196556 kb
Host smart-15cc746c-f1fb-4ba0-b96a-28e80d08ec3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784641090 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.784641090
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1568673825
Short name T76
Test name
Test status
Simulation time 12087957 ps
CPU time 0.52 seconds
Started Jul 14 04:17:08 PM PDT 24
Finished Jul 14 04:17:09 PM PDT 24
Peak memory 181356 kb
Host smart-452e9be1-7047-41a8-9462-1a85129df8b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568673825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1568673825
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.2279459038
Short name T557
Test name
Test status
Simulation time 24900576 ps
CPU time 0.54 seconds
Started Jul 14 04:22:02 PM PDT 24
Finished Jul 14 04:22:04 PM PDT 24
Peak memory 181980 kb
Host smart-65ba8bbc-3c0d-4cf1-b1fe-8e013413286c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279459038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.2279459038
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.521792634
Short name T77
Test name
Test status
Simulation time 79958957 ps
CPU time 0.64 seconds
Started Jul 14 04:17:14 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 191800 kb
Host smart-d44097e0-344f-416f-a25a-6e1f37ff2b6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521792634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.521792634
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.1346635117
Short name T543
Test name
Test status
Simulation time 53494945 ps
CPU time 2.45 seconds
Started Jul 14 04:21:49 PM PDT 24
Finished Jul 14 04:21:52 PM PDT 24
Peak memory 195796 kb
Host smart-d9d0926e-96a4-448a-96fc-f736583718ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346635117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.1346635117
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3731506221
Short name T71
Test name
Test status
Simulation time 32425384 ps
CPU time 0.74 seconds
Started Jul 14 04:17:11 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 191088 kb
Host smart-40a544a4-2ef1-40ee-8b50-04d068dac083
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731506221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3731506221
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.808641006
Short name T504
Test name
Test status
Simulation time 557079702 ps
CPU time 1.64 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:13 PM PDT 24
Peak memory 188968 kb
Host smart-637b365f-8475-4814-bec4-0efbc35a9c57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808641006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_b
ash.808641006
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.2892267843
Short name T538
Test name
Test status
Simulation time 44774432 ps
CPU time 0.63 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:11 PM PDT 24
Peak memory 180668 kb
Host smart-1b841056-4836-46cb-8ccb-82b848bf7d0e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892267843 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.2892267843
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4038921681
Short name T520
Test name
Test status
Simulation time 112013488 ps
CPU time 0.77 seconds
Started Jul 14 04:17:11 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 194904 kb
Host smart-e1c60300-894d-4d03-aed4-d2a570fe3ee5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038921681 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4038921681
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.714640015
Short name T65
Test name
Test status
Simulation time 18117069 ps
CPU time 0.66 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:12 PM PDT 24
Peak memory 180608 kb
Host smart-82f88c67-3014-40cd-89e8-22695bdd17a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714640015 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.714640015
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3652996145
Short name T456
Test name
Test status
Simulation time 14765828 ps
CPU time 0.66 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:11 PM PDT 24
Peak memory 179872 kb
Host smart-5a7f2293-a482-4e3d-9eea-16bf4a9371d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652996145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3652996145
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.4052327575
Short name T81
Test name
Test status
Simulation time 18447793 ps
CPU time 0.67 seconds
Started Jul 14 04:17:12 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 191200 kb
Host smart-f2f50ab9-e35e-4c9d-a081-0925ce378348
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052327575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.4052327575
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.1829424750
Short name T545
Test name
Test status
Simulation time 53928808 ps
CPU time 1.13 seconds
Started Jul 14 04:21:49 PM PDT 24
Finished Jul 14 04:21:51 PM PDT 24
Peak memory 196568 kb
Host smart-91f1e3c9-0b6d-4b78-92be-91607f90ef23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829424750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.1829424750
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1332845582
Short name T521
Test name
Test status
Simulation time 402577373 ps
CPU time 1.31 seconds
Started Jul 14 04:18:53 PM PDT 24
Finished Jul 14 04:18:55 PM PDT 24
Peak memory 182856 kb
Host smart-9acae4c5-757c-4d0b-b87f-9a93d998c6cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332845582 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1332845582
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.835557327
Short name T490
Test name
Test status
Simulation time 118370918 ps
CPU time 1.18 seconds
Started Jul 14 04:23:03 PM PDT 24
Finished Jul 14 04:23:06 PM PDT 24
Peak memory 195784 kb
Host smart-676b4f96-e6ec-4a54-bd3f-fc018e71da15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835557327 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.835557327
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.4233142178
Short name T486
Test name
Test status
Simulation time 13873846 ps
CPU time 0.55 seconds
Started Jul 14 04:18:07 PM PDT 24
Finished Jul 14 04:18:08 PM PDT 24
Peak memory 181836 kb
Host smart-66685761-5874-43bd-a251-c43bf5ffc4da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233142178 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.4233142178
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.683683925
Short name T453
Test name
Test status
Simulation time 13948870 ps
CPU time 0.59 seconds
Started Jul 14 04:18:11 PM PDT 24
Finished Jul 14 04:18:12 PM PDT 24
Peak memory 181448 kb
Host smart-40c51fb2-9678-44e7-8782-3d86e83c9ad9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683683925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.683683925
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.3609131122
Short name T517
Test name
Test status
Simulation time 141554547 ps
CPU time 0.55 seconds
Started Jul 14 04:23:07 PM PDT 24
Finished Jul 14 04:23:09 PM PDT 24
Peak memory 190364 kb
Host smart-a3d256d0-d9df-476b-afb8-3d5bf4bb898d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609131122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.3609131122
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.358726859
Short name T461
Test name
Test status
Simulation time 205798736 ps
CPU time 2.96 seconds
Started Jul 14 04:23:07 PM PDT 24
Finished Jul 14 04:23:11 PM PDT 24
Peak memory 194928 kb
Host smart-edfa4efd-9d79-4387-82ea-34a29a9d5cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358726859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.358726859
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2791683868
Short name T30
Test name
Test status
Simulation time 506717439 ps
CPU time 1.29 seconds
Started Jul 14 04:18:03 PM PDT 24
Finished Jul 14 04:18:05 PM PDT 24
Peak memory 194528 kb
Host smart-8876edf3-9c12-4826-af04-654cb2e504c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791683868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2791683868
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.1113054931
Short name T483
Test name
Test status
Simulation time 66773546 ps
CPU time 0.62 seconds
Started Jul 14 04:18:06 PM PDT 24
Finished Jul 14 04:18:07 PM PDT 24
Peak memory 192648 kb
Host smart-3663a9a9-4b20-4ed3-ba48-1492b0f8dc2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113054931 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.1113054931
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.449771320
Short name T75
Test name
Test status
Simulation time 11942916 ps
CPU time 0.53 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:23:44 PM PDT 24
Peak memory 181820 kb
Host smart-3d2b3b7e-1ee8-4a93-a3e9-b7a3ddb7e689
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449771320 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.449771320
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4078022804
Short name T507
Test name
Test status
Simulation time 24047258 ps
CPU time 0.52 seconds
Started Jul 14 04:23:05 PM PDT 24
Finished Jul 14 04:23:07 PM PDT 24
Peak memory 181764 kb
Host smart-fd10cd2d-ee7d-4852-84ef-c1f273c556c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078022804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4078022804
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2740032813
Short name T532
Test name
Test status
Simulation time 29516438 ps
CPU time 0.71 seconds
Started Jul 14 04:17:50 PM PDT 24
Finished Jul 14 04:17:52 PM PDT 24
Peak memory 192384 kb
Host smart-dae9fc01-01c7-498b-9c55-5ce7fa5f89ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740032813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2740032813
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.1798543482
Short name T573
Test name
Test status
Simulation time 49381446 ps
CPU time 2.25 seconds
Started Jul 14 04:18:03 PM PDT 24
Finished Jul 14 04:18:06 PM PDT 24
Peak memory 196900 kb
Host smart-86fe9caf-39c4-4b37-a58c-70fe41248d79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798543482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.1798543482
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.4144800041
Short name T570
Test name
Test status
Simulation time 418951062 ps
CPU time 1.42 seconds
Started Jul 14 04:17:22 PM PDT 24
Finished Jul 14 04:17:23 PM PDT 24
Peak memory 194748 kb
Host smart-5fb770d1-d51b-42cd-bf20-9cfb82f60ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144800041 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.4144800041
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.3517785616
Short name T574
Test name
Test status
Simulation time 28203496 ps
CPU time 1.29 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:46 PM PDT 24
Peak memory 196820 kb
Host smart-bc382bea-d1b2-4e34-ae40-9706427f2ab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517785616 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.3517785616
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.1098059727
Short name T560
Test name
Test status
Simulation time 46447078 ps
CPU time 0.51 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:22:33 PM PDT 24
Peak memory 181300 kb
Host smart-dbcdb6f0-8154-48b1-ada4-c6b939a80177
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098059727 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.1098059727
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1940454487
Short name T455
Test name
Test status
Simulation time 54977108 ps
CPU time 0.54 seconds
Started Jul 14 04:22:09 PM PDT 24
Finished Jul 14 04:22:11 PM PDT 24
Peak memory 181648 kb
Host smart-46701fed-6312-45a1-a489-0968a58a4aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940454487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1940454487
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3752337405
Short name T511
Test name
Test status
Simulation time 31118872 ps
CPU time 0.65 seconds
Started Jul 14 04:22:37 PM PDT 24
Finished Jul 14 04:22:39 PM PDT 24
Peak memory 191088 kb
Host smart-56ff7baf-40c4-483f-b4f0-865c39b648a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752337405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3752337405
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.261173657
Short name T479
Test name
Test status
Simulation time 312377761 ps
CPU time 1.59 seconds
Started Jul 14 04:21:30 PM PDT 24
Finished Jul 14 04:21:32 PM PDT 24
Peak memory 197036 kb
Host smart-bd5aff62-d3b0-48bd-a736-8c89f4ebc4e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261173657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.261173657
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2486128360
Short name T470
Test name
Test status
Simulation time 852998943 ps
CPU time 1.02 seconds
Started Jul 14 04:22:23 PM PDT 24
Finished Jul 14 04:22:25 PM PDT 24
Peak memory 182520 kb
Host smart-88dd59e9-dd0f-4f06-a89e-57928fa311a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486128360 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2486128360
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2344136397
Short name T473
Test name
Test status
Simulation time 53267507 ps
CPU time 1.11 seconds
Started Jul 14 04:23:02 PM PDT 24
Finished Jul 14 04:23:05 PM PDT 24
Peak memory 196552 kb
Host smart-6859658b-9652-47f4-bf66-0ea373a027fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344136397 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2344136397
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3886597709
Short name T502
Test name
Test status
Simulation time 43699934 ps
CPU time 0.55 seconds
Started Jul 14 04:23:15 PM PDT 24
Finished Jul 14 04:23:17 PM PDT 24
Peak memory 182024 kb
Host smart-f21b4e2b-a0eb-4638-9835-0861396deb4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886597709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3886597709
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.886884756
Short name T537
Test name
Test status
Simulation time 86073949 ps
CPU time 0.53 seconds
Started Jul 14 04:22:18 PM PDT 24
Finished Jul 14 04:22:19 PM PDT 24
Peak memory 181588 kb
Host smart-4205555e-f946-46c5-8afc-403c6d7a5a42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886884756 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.886884756
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.2947806759
Short name T577
Test name
Test status
Simulation time 53308636 ps
CPU time 0.8 seconds
Started Jul 14 04:21:04 PM PDT 24
Finished Jul 14 04:21:06 PM PDT 24
Peak memory 191140 kb
Host smart-23bd894d-f546-4098-9218-43510730d8d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947806759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.2947806759
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1077755350
Short name T472
Test name
Test status
Simulation time 562207297 ps
CPU time 2.33 seconds
Started Jul 14 04:22:31 PM PDT 24
Finished Jul 14 04:22:35 PM PDT 24
Peak memory 196540 kb
Host smart-4b0b9f05-15dd-4618-bf3c-51911340c025
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077755350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1077755350
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.2047401203
Short name T96
Test name
Test status
Simulation time 69376148 ps
CPU time 1.07 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:46 PM PDT 24
Peak memory 194500 kb
Host smart-e189b684-d54f-4ca7-82ec-6871db94b4c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047401203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.2047401203
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.3781182035
Short name T50
Test name
Test status
Simulation time 67863328 ps
CPU time 0.71 seconds
Started Jul 14 04:22:31 PM PDT 24
Finished Jul 14 04:22:34 PM PDT 24
Peak memory 194208 kb
Host smart-21654a56-8378-4bd4-9524-37103b0244fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781182035 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.3781182035
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.572953688
Short name T80
Test name
Test status
Simulation time 14337798 ps
CPU time 0.56 seconds
Started Jul 14 04:22:38 PM PDT 24
Finished Jul 14 04:22:39 PM PDT 24
Peak memory 181844 kb
Host smart-653d5cf1-322a-4735-a64c-e7995d45bc9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572953688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.572953688
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2500569735
Short name T477
Test name
Test status
Simulation time 18846064 ps
CPU time 0.52 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:44 PM PDT 24
Peak memory 181928 kb
Host smart-1c7a0358-eee7-42ba-8a24-7018bef1cd3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500569735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2500569735
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1817572213
Short name T79
Test name
Test status
Simulation time 53690291 ps
CPU time 0.6 seconds
Started Jul 14 04:21:04 PM PDT 24
Finished Jul 14 04:21:05 PM PDT 24
Peak memory 191492 kb
Host smart-25903867-8beb-4fae-95d3-e6e515c2ce97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817572213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1817572213
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.3876583128
Short name T487
Test name
Test status
Simulation time 97350447 ps
CPU time 1.38 seconds
Started Jul 14 04:22:32 PM PDT 24
Finished Jul 14 04:22:35 PM PDT 24
Peak memory 196644 kb
Host smart-7c2f0850-da34-4e82-bc94-7341eaaf7e82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876583128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.3876583128
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.346494285
Short name T489
Test name
Test status
Simulation time 141069541 ps
CPU time 0.93 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:46 PM PDT 24
Peak memory 196752 kb
Host smart-36c75189-c263-4299-b504-127ed91cd657
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346494285 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.346494285
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1976815459
Short name T488
Test name
Test status
Simulation time 16275311 ps
CPU time 0.57 seconds
Started Jul 14 04:18:52 PM PDT 24
Finished Jul 14 04:18:53 PM PDT 24
Peak memory 182080 kb
Host smart-6864288b-90ec-4647-aefe-e81fb45208f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976815459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1976815459
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.855728568
Short name T556
Test name
Test status
Simulation time 25251127 ps
CPU time 0.5 seconds
Started Jul 14 04:22:09 PM PDT 24
Finished Jul 14 04:22:10 PM PDT 24
Peak memory 181600 kb
Host smart-40d13fbb-2940-44b5-be8c-f0574213181a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855728568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.855728568
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3040492194
Short name T498
Test name
Test status
Simulation time 30989184 ps
CPU time 0.67 seconds
Started Jul 14 04:22:31 PM PDT 24
Finished Jul 14 04:22:34 PM PDT 24
Peak memory 190816 kb
Host smart-54069ac5-5ae9-4a92-97a4-2d4623873991
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040492194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3040492194
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1679638696
Short name T465
Test name
Test status
Simulation time 399386594 ps
CPU time 1.99 seconds
Started Jul 14 04:17:49 PM PDT 24
Finished Jul 14 04:17:51 PM PDT 24
Peak memory 197292 kb
Host smart-be10599b-aa04-4aee-9cfd-cd7ba4a9be08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679638696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1679638696
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3946773897
Short name T554
Test name
Test status
Simulation time 116791572 ps
CPU time 1.3 seconds
Started Jul 14 04:21:57 PM PDT 24
Finished Jul 14 04:22:01 PM PDT 24
Peak memory 194540 kb
Host smart-78233557-3dbb-41fc-aecc-c7acbe094a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946773897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.3946773897
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.374658474
Short name T491
Test name
Test status
Simulation time 85354038 ps
CPU time 1.42 seconds
Started Jul 14 04:22:37 PM PDT 24
Finished Jul 14 04:22:39 PM PDT 24
Peak memory 195436 kb
Host smart-0b3c58c4-b68e-4ff9-b260-379db5d42aa0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374658474 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.374658474
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2553048310
Short name T572
Test name
Test status
Simulation time 19276994 ps
CPU time 0.59 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:22:33 PM PDT 24
Peak memory 180580 kb
Host smart-26eabce6-0939-4aba-b17e-e17abc63ca0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553048310 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2553048310
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.3061072378
Short name T524
Test name
Test status
Simulation time 11338553 ps
CPU time 0.52 seconds
Started Jul 14 04:20:30 PM PDT 24
Finished Jul 14 04:20:31 PM PDT 24
Peak memory 181460 kb
Host smart-bb9c15e8-1dbb-499e-92ff-4103b659248d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061072378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.3061072378
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.422050033
Short name T539
Test name
Test status
Simulation time 33550056 ps
CPU time 0.7 seconds
Started Jul 14 04:22:37 PM PDT 24
Finished Jul 14 04:22:38 PM PDT 24
Peak memory 190296 kb
Host smart-62343342-c5a5-45ba-9cb4-fa43f05cef43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422050033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_ti
mer_same_csr_outstanding.422050033
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.1611471718
Short name T458
Test name
Test status
Simulation time 118995323 ps
CPU time 1.43 seconds
Started Jul 14 04:20:43 PM PDT 24
Finished Jul 14 04:20:45 PM PDT 24
Peak memory 196880 kb
Host smart-9f4369aa-81e2-4186-ac15-71e5b0cce926
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611471718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.1611471718
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.980599276
Short name T531
Test name
Test status
Simulation time 1989004692 ps
CPU time 1.21 seconds
Started Jul 14 04:22:31 PM PDT 24
Finished Jul 14 04:22:34 PM PDT 24
Peak memory 194364 kb
Host smart-bbc26e33-ab1c-4a6c-aab8-8fffc032a42e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980599276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.980599276
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3056444238
Short name T466
Test name
Test status
Simulation time 57039256 ps
CPU time 0.89 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:22:34 PM PDT 24
Peak memory 195312 kb
Host smart-0b871f26-26ef-4d32-8e3d-336c7969b029
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056444238 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3056444238
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1922589170
Short name T66
Test name
Test status
Simulation time 55950416 ps
CPU time 0.54 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:45 PM PDT 24
Peak memory 182112 kb
Host smart-70843321-5d5b-4ebe-8ba7-db9f6e277648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922589170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1922589170
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2704411406
Short name T449
Test name
Test status
Simulation time 19739447 ps
CPU time 0.53 seconds
Started Jul 14 04:22:09 PM PDT 24
Finished Jul 14 04:22:10 PM PDT 24
Peak memory 181916 kb
Host smart-43ff6cd7-8f74-4010-9d89-542d3454f457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704411406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2704411406
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.4046687241
Short name T68
Test name
Test status
Simulation time 48554879 ps
CPU time 0.64 seconds
Started Jul 14 04:21:56 PM PDT 24
Finished Jul 14 04:21:59 PM PDT 24
Peak memory 190228 kb
Host smart-6806eded-2c3c-46c6-b4bc-4d01f921fac2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046687241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.4046687241
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.4176946039
Short name T49
Test name
Test status
Simulation time 70258189 ps
CPU time 1.24 seconds
Started Jul 14 04:23:15 PM PDT 24
Finished Jul 14 04:23:18 PM PDT 24
Peak memory 196808 kb
Host smart-95ea11a4-8a85-4002-b345-d08e57fcfa07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176946039 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.4176946039
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3525346850
Short name T551
Test name
Test status
Simulation time 85152787 ps
CPU time 1.08 seconds
Started Jul 14 04:22:33 PM PDT 24
Finished Jul 14 04:22:36 PM PDT 24
Peak memory 193628 kb
Host smart-602c567a-84bd-4f87-8abf-e8b1022d8d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525346850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3525346850
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.2318272472
Short name T564
Test name
Test status
Simulation time 70761266 ps
CPU time 0.96 seconds
Started Jul 14 04:21:44 PM PDT 24
Finished Jul 14 04:21:45 PM PDT 24
Peak memory 196720 kb
Host smart-6d902267-988e-4337-8097-3f2442ab50a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318272472 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.2318272472
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2356686409
Short name T475
Test name
Test status
Simulation time 48285024 ps
CPU time 0.54 seconds
Started Jul 14 04:23:15 PM PDT 24
Finished Jul 14 04:23:17 PM PDT 24
Peak memory 182024 kb
Host smart-de7d9cea-702e-47a4-942f-5d8188cc073c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356686409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2356686409
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.3630901851
Short name T547
Test name
Test status
Simulation time 105116022 ps
CPU time 0.53 seconds
Started Jul 14 04:23:02 PM PDT 24
Finished Jul 14 04:23:04 PM PDT 24
Peak memory 181356 kb
Host smart-c9f6d660-f54c-4787-af14-f1728075391e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630901851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.3630901851
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.4226859464
Short name T505
Test name
Test status
Simulation time 22594930 ps
CPU time 0.64 seconds
Started Jul 14 04:23:15 PM PDT 24
Finished Jul 14 04:23:17 PM PDT 24
Peak memory 191452 kb
Host smart-1aa5cfad-a937-4f86-9fa1-b67088bf33d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226859464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.4226859464
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.3070401415
Short name T510
Test name
Test status
Simulation time 35717441 ps
CPU time 1.63 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:22:35 PM PDT 24
Peak memory 195568 kb
Host smart-f54e541d-e779-42c4-862e-79b6ca1e8680
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070401415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.3070401415
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3301457814
Short name T513
Test name
Test status
Simulation time 69928928 ps
CPU time 0.82 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:22:34 PM PDT 24
Peak memory 191300 kb
Host smart-cb858cbe-c8b7-42fc-9391-4b8433ad23d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301457814 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3301457814
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.1665001741
Short name T485
Test name
Test status
Simulation time 110735256 ps
CPU time 0.87 seconds
Started Jul 14 04:23:02 PM PDT 24
Finished Jul 14 04:23:04 PM PDT 24
Peak memory 193144 kb
Host smart-e792c593-1b1b-4d9a-bdfe-ee190b6cf1fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665001741 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.1665001741
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2137719056
Short name T494
Test name
Test status
Simulation time 14562105 ps
CPU time 0.54 seconds
Started Jul 14 04:20:41 PM PDT 24
Finished Jul 14 04:20:42 PM PDT 24
Peak memory 182120 kb
Host smart-0fed53fc-7cd4-4a85-b38d-25f657ab06da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137719056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2137719056
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.820764790
Short name T527
Test name
Test status
Simulation time 14379634 ps
CPU time 0.54 seconds
Started Jul 14 04:20:42 PM PDT 24
Finished Jul 14 04:20:43 PM PDT 24
Peak memory 182004 kb
Host smart-0dac224a-073b-4104-82d3-4c9f15fa91e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820764790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.820764790
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.671575304
Short name T52
Test name
Test status
Simulation time 79690780 ps
CPU time 0.6 seconds
Started Jul 14 04:20:44 PM PDT 24
Finished Jul 14 04:20:45 PM PDT 24
Peak memory 191376 kb
Host smart-101b1c77-ca5f-4673-8859-8f9435afaad2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671575304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_ti
mer_same_csr_outstanding.671575304
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.196983862
Short name T474
Test name
Test status
Simulation time 198093238 ps
CPU time 1.82 seconds
Started Jul 14 04:17:56 PM PDT 24
Finished Jul 14 04:17:59 PM PDT 24
Peak memory 196888 kb
Host smart-886b0035-b0ee-422f-81a0-0cc5a6d0697a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196983862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.196983862
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3190489062
Short name T29
Test name
Test status
Simulation time 134738092 ps
CPU time 1.31 seconds
Started Jul 14 04:23:15 PM PDT 24
Finished Jul 14 04:23:18 PM PDT 24
Peak memory 182444 kb
Host smart-9a6f987f-1625-4941-87a9-a39268873dbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190489062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3190489062
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.3044402115
Short name T73
Test name
Test status
Simulation time 27020667 ps
CPU time 0.7 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:12 PM PDT 24
Peak memory 191444 kb
Host smart-6cbdd238-f54b-48ce-a97e-2886e54a4fd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044402115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.3044402115
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.2517148425
Short name T536
Test name
Test status
Simulation time 428375332 ps
CPU time 1.49 seconds
Started Jul 14 04:20:43 PM PDT 24
Finished Jul 14 04:20:45 PM PDT 24
Peak memory 190436 kb
Host smart-a4cfcff3-337d-4b0d-b88c-bdc33fe06b35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517148425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.2517148425
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.3980535201
Short name T72
Test name
Test status
Simulation time 24181409 ps
CPU time 0.54 seconds
Started Jul 14 04:17:11 PM PDT 24
Finished Jul 14 04:17:14 PM PDT 24
Peak memory 181488 kb
Host smart-e5383e54-020c-43cb-8eed-72c9d395f161
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980535201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.3980535201
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.1075806726
Short name T533
Test name
Test status
Simulation time 91304906 ps
CPU time 1.26 seconds
Started Jul 14 04:17:12 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 196708 kb
Host smart-66b3c8c1-fce6-4e03-a873-bca7609d0dca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075806726 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.1075806726
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.1069684517
Short name T70
Test name
Test status
Simulation time 31029325 ps
CPU time 0.69 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:12 PM PDT 24
Peak memory 180740 kb
Host smart-dc15d55f-231e-4716-b7fe-e0cbfa41140b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069684517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.1069684517
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1627267079
Short name T484
Test name
Test status
Simulation time 14927296 ps
CPU time 0.54 seconds
Started Jul 14 04:22:02 PM PDT 24
Finished Jul 14 04:22:04 PM PDT 24
Peak memory 182020 kb
Host smart-138bbcbb-4c59-4604-a74c-ce7655142c57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627267079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1627267079
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3398183226
Short name T544
Test name
Test status
Simulation time 113450745 ps
CPU time 0.85 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:12 PM PDT 24
Peak memory 189636 kb
Host smart-e1527e26-ecec-46cf-bf4c-95d2af3f0f26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398183226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3398183226
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.4219863346
Short name T460
Test name
Test status
Simulation time 24035506 ps
CPU time 1.17 seconds
Started Jul 14 04:22:02 PM PDT 24
Finished Jul 14 04:22:04 PM PDT 24
Peak memory 196888 kb
Host smart-c8084e78-13c0-4278-bbc0-45916155b502
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219863346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.4219863346
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1880668687
Short name T493
Test name
Test status
Simulation time 164777594 ps
CPU time 0.89 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:12 PM PDT 24
Peak memory 190588 kb
Host smart-c7afe6b3-1599-4c68-9031-0fb7ead4cdf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880668687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1880668687
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.2015533241
Short name T519
Test name
Test status
Simulation time 13457631 ps
CPU time 0.52 seconds
Started Jul 14 04:20:53 PM PDT 24
Finished Jul 14 04:20:54 PM PDT 24
Peak memory 181620 kb
Host smart-d2234b67-7489-413a-93b8-04a37ea440b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015533241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.2015533241
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.375640110
Short name T563
Test name
Test status
Simulation time 12522954 ps
CPU time 0.56 seconds
Started Jul 14 04:21:04 PM PDT 24
Finished Jul 14 04:21:05 PM PDT 24
Peak memory 182392 kb
Host smart-2c7e07cf-b964-4f58-b8d9-c12ba135ccac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375640110 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.375640110
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.1870411272
Short name T459
Test name
Test status
Simulation time 18918052 ps
CPU time 0.55 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:22:45 PM PDT 24
Peak memory 181968 kb
Host smart-8a0801b8-f222-4cca-93e2-d9dc84de5d00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870411272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.1870411272
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.663165030
Short name T571
Test name
Test status
Simulation time 44749864 ps
CPU time 0.59 seconds
Started Jul 14 04:22:18 PM PDT 24
Finished Jul 14 04:22:20 PM PDT 24
Peak memory 181104 kb
Host smart-3eb0dfa6-70e9-429e-94df-2dcdb407a980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663165030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.663165030
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2423338697
Short name T464
Test name
Test status
Simulation time 13627536 ps
CPU time 0.66 seconds
Started Jul 14 04:22:27 PM PDT 24
Finished Jul 14 04:22:31 PM PDT 24
Peak memory 179876 kb
Host smart-a4672194-aafc-468b-9133-01a6c61d97b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423338697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2423338697
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.3207016096
Short name T512
Test name
Test status
Simulation time 14333696 ps
CPU time 0.65 seconds
Started Jul 14 04:22:27 PM PDT 24
Finished Jul 14 04:22:31 PM PDT 24
Peak memory 180024 kb
Host smart-1556292f-45a5-463c-a896-a45b9b68fff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207016096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.3207016096
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1491652879
Short name T540
Test name
Test status
Simulation time 12554289 ps
CPU time 0.55 seconds
Started Jul 14 04:22:27 PM PDT 24
Finished Jul 14 04:22:31 PM PDT 24
Peak memory 180948 kb
Host smart-791f0b60-bc9e-4a29-8207-ae9e0be7d8bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491652879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1491652879
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.2713538548
Short name T559
Test name
Test status
Simulation time 23272488 ps
CPU time 0.53 seconds
Started Jul 14 04:22:33 PM PDT 24
Finished Jul 14 04:22:36 PM PDT 24
Peak memory 181980 kb
Host smart-efa01ed7-05ab-4199-b365-74ba28e13169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713538548 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.2713538548
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.4271114590
Short name T567
Test name
Test status
Simulation time 16199448 ps
CPU time 0.54 seconds
Started Jul 14 04:22:28 PM PDT 24
Finished Jul 14 04:22:31 PM PDT 24
Peak memory 181072 kb
Host smart-0ab20808-d7d6-4c98-81f5-a2416a37f8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271114590 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.4271114590
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3704959418
Short name T448
Test name
Test status
Simulation time 13006014 ps
CPU time 0.52 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:22:46 PM PDT 24
Peak memory 181616 kb
Host smart-040012e5-46d6-425b-bc03-44242138f352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704959418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3704959418
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.916424272
Short name T500
Test name
Test status
Simulation time 21938850 ps
CPU time 0.61 seconds
Started Jul 14 04:17:12 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 181904 kb
Host smart-41c1bec6-bc59-4503-89e4-9a8093eaf2fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916424272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alias
ing.916424272
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.2836046079
Short name T67
Test name
Test status
Simulation time 120395942 ps
CPU time 2.32 seconds
Started Jul 14 04:17:11 PM PDT 24
Finished Jul 14 04:17:16 PM PDT 24
Peak memory 190256 kb
Host smart-c2dcd906-9bab-4bc2-8ba5-c6ad45b16a3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836046079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.2836046079
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.171611258
Short name T63
Test name
Test status
Simulation time 54919787 ps
CPU time 0.58 seconds
Started Jul 14 04:21:47 PM PDT 24
Finished Jul 14 04:21:49 PM PDT 24
Peak memory 180840 kb
Host smart-aa81f356-9f56-46de-869b-cc11fa8561c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171611258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.171611258
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3327413729
Short name T542
Test name
Test status
Simulation time 38912670 ps
CPU time 1.36 seconds
Started Jul 14 04:23:30 PM PDT 24
Finished Jul 14 04:23:34 PM PDT 24
Peak memory 196684 kb
Host smart-28a38e88-2cf1-4d6d-b8f6-b221c5afb26e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327413729 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.3327413729
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.1157350899
Short name T576
Test name
Test status
Simulation time 138094206 ps
CPU time 0.6 seconds
Started Jul 14 04:17:20 PM PDT 24
Finished Jul 14 04:17:22 PM PDT 24
Peak memory 180604 kb
Host smart-59580be4-e8be-4ace-9548-de330962a2b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157350899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.1157350899
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.419999743
Short name T508
Test name
Test status
Simulation time 34474988 ps
CPU time 0.55 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:11 PM PDT 24
Peak memory 182004 kb
Host smart-fbff8d1c-c6a2-4158-8f2d-05582d4a783a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419999743 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.419999743
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.1037869274
Short name T78
Test name
Test status
Simulation time 266977991 ps
CPU time 0.8 seconds
Started Jul 14 04:17:12 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 192468 kb
Host smart-300d7377-1219-4ae5-b48d-fc7e3c8dc7cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037869274 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.1037869274
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.2278096121
Short name T575
Test name
Test status
Simulation time 158150086 ps
CPU time 1.93 seconds
Started Jul 14 04:17:10 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 196480 kb
Host smart-6653c47c-e9be-4eb8-a1df-a0056315466c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278096121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.2278096121
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3926855790
Short name T95
Test name
Test status
Simulation time 320323627 ps
CPU time 1.06 seconds
Started Jul 14 04:17:12 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 190468 kb
Host smart-ec8bcdf1-92a6-4d58-ab67-a96b625312a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926855790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3926855790
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.2473778863
Short name T566
Test name
Test status
Simulation time 14222422 ps
CPU time 0.56 seconds
Started Jul 14 04:23:04 PM PDT 24
Finished Jul 14 04:23:08 PM PDT 24
Peak memory 179832 kb
Host smart-4e4166af-f4a4-4ad0-af97-c94b8f836291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473778863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.2473778863
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.83502770
Short name T549
Test name
Test status
Simulation time 13549044 ps
CPU time 0.6 seconds
Started Jul 14 04:22:00 PM PDT 24
Finished Jul 14 04:22:02 PM PDT 24
Peak memory 180376 kb
Host smart-bda07ecd-3797-44e1-b7d1-6e618496041e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83502770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.83502770
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3217934874
Short name T463
Test name
Test status
Simulation time 24262707 ps
CPU time 0.58 seconds
Started Jul 14 04:22:33 PM PDT 24
Finished Jul 14 04:22:36 PM PDT 24
Peak memory 180992 kb
Host smart-76138ca7-c2d2-47ea-b7f3-492625855976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217934874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3217934874
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3973471301
Short name T555
Test name
Test status
Simulation time 55936678 ps
CPU time 0.66 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:23:03 PM PDT 24
Peak memory 180312 kb
Host smart-8123e0f6-8874-46af-8399-d3a7a03b9914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973471301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3973471301
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2475340025
Short name T501
Test name
Test status
Simulation time 11882774 ps
CPU time 0.56 seconds
Started Jul 14 04:22:33 PM PDT 24
Finished Jul 14 04:22:36 PM PDT 24
Peak memory 180644 kb
Host smart-0823c372-e152-4004-bdaa-e9aa5daabdf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475340025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2475340025
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3282312335
Short name T451
Test name
Test status
Simulation time 46092056 ps
CPU time 0.58 seconds
Started Jul 14 04:23:03 PM PDT 24
Finished Jul 14 04:23:06 PM PDT 24
Peak memory 179792 kb
Host smart-20de8af4-7e3f-485d-991e-7feab4dc0039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282312335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3282312335
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2042629952
Short name T482
Test name
Test status
Simulation time 48679549 ps
CPU time 0.58 seconds
Started Jul 14 04:17:20 PM PDT 24
Finished Jul 14 04:17:22 PM PDT 24
Peak memory 180460 kb
Host smart-d0c15606-2118-4758-b375-f7b2729fe866
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042629952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2042629952
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.1221456937
Short name T552
Test name
Test status
Simulation time 40824241 ps
CPU time 0.63 seconds
Started Jul 14 04:17:28 PM PDT 24
Finished Jul 14 04:17:29 PM PDT 24
Peak memory 181968 kb
Host smart-67cfcc55-22f4-4ba7-acad-9952f3980241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221456937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.1221456937
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1197792546
Short name T518
Test name
Test status
Simulation time 30667018 ps
CPU time 0.64 seconds
Started Jul 14 04:17:20 PM PDT 24
Finished Jul 14 04:17:22 PM PDT 24
Peak memory 180240 kb
Host smart-6593d942-90c1-448e-b768-297c70737619
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197792546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1197792546
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.72308886
Short name T553
Test name
Test status
Simulation time 21845798 ps
CPU time 0.54 seconds
Started Jul 14 04:17:31 PM PDT 24
Finished Jul 14 04:17:32 PM PDT 24
Peak memory 181384 kb
Host smart-5b85c466-5898-4a71-9e1f-d0fbf808e333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72308886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.72308886
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.3260134957
Short name T516
Test name
Test status
Simulation time 164313620 ps
CPU time 0.7 seconds
Started Jul 14 04:18:07 PM PDT 24
Finished Jul 14 04:18:08 PM PDT 24
Peak memory 182052 kb
Host smart-9df1690d-478d-4247-8f9b-15c137ac1dd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260134957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.3260134957
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3428783134
Short name T568
Test name
Test status
Simulation time 521457376 ps
CPU time 1.59 seconds
Started Jul 14 04:17:45 PM PDT 24
Finished Jul 14 04:17:47 PM PDT 24
Peak memory 182220 kb
Host smart-9eae155b-47bd-4fa6-a393-03240f8a43d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428783134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3428783134
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2528786466
Short name T468
Test name
Test status
Simulation time 15534133 ps
CPU time 0.55 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:23:45 PM PDT 24
Peak memory 181804 kb
Host smart-ed68513a-c2dd-4c79-b546-aeb4bca7e508
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528786466 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2528786466
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.78953202
Short name T452
Test name
Test status
Simulation time 22233906 ps
CPU time 0.6 seconds
Started Jul 14 04:23:19 PM PDT 24
Finished Jul 14 04:23:21 PM PDT 24
Peak memory 193436 kb
Host smart-0e1b46f2-f14f-4bdd-86dc-076ded9b3938
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78953202 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.78953202
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2701793042
Short name T93
Test name
Test status
Simulation time 65870029 ps
CPU time 0.57 seconds
Started Jul 14 04:18:07 PM PDT 24
Finished Jul 14 04:18:08 PM PDT 24
Peak memory 182076 kb
Host smart-8454a480-bc20-421d-bbc6-be4bc4171ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701793042 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2701793042
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.2678908706
Short name T492
Test name
Test status
Simulation time 33087628 ps
CPU time 0.52 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:14 PM PDT 24
Peak memory 181044 kb
Host smart-8d8b830f-adcf-4060-a352-0e56a9451408
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678908706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.2678908706
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3601091080
Short name T550
Test name
Test status
Simulation time 104088658 ps
CPU time 0.72 seconds
Started Jul 14 04:17:18 PM PDT 24
Finished Jul 14 04:17:20 PM PDT 24
Peak memory 192404 kb
Host smart-1aea7eaf-da61-4713-a9dc-55162e097c2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601091080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.3601091080
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.4224979240
Short name T499
Test name
Test status
Simulation time 99115047 ps
CPU time 1.43 seconds
Started Jul 14 04:18:06 PM PDT 24
Finished Jul 14 04:18:08 PM PDT 24
Peak memory 196868 kb
Host smart-5d76bc14-e656-4672-8577-6a3dc0b0971c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224979240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.4224979240
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.3301146040
Short name T462
Test name
Test status
Simulation time 445300730 ps
CPU time 1.32 seconds
Started Jul 14 04:17:11 PM PDT 24
Finished Jul 14 04:17:15 PM PDT 24
Peak memory 194712 kb
Host smart-47e579ef-f7f0-4f2f-8e88-6f118872743d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301146040 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.3301146040
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3096419944
Short name T565
Test name
Test status
Simulation time 49252201 ps
CPU time 0.57 seconds
Started Jul 14 04:19:31 PM PDT 24
Finished Jul 14 04:19:32 PM PDT 24
Peak memory 181992 kb
Host smart-a80e64a5-1758-4a06-887c-e79b5aacd5cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096419944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3096419944
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.4051323215
Short name T578
Test name
Test status
Simulation time 51020759 ps
CPU time 0.59 seconds
Started Jul 14 04:17:36 PM PDT 24
Finished Jul 14 04:17:37 PM PDT 24
Peak memory 181892 kb
Host smart-299da615-006d-486c-a58d-299b7fe4673c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051323215 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.4051323215
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.523194498
Short name T579
Test name
Test status
Simulation time 49053539 ps
CPU time 0.55 seconds
Started Jul 14 04:22:23 PM PDT 24
Finished Jul 14 04:22:24 PM PDT 24
Peak memory 181848 kb
Host smart-ddb5034a-c57f-462d-9fb5-0f236d614ae3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523194498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.523194498
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.1159353893
Short name T562
Test name
Test status
Simulation time 42967795 ps
CPU time 0.53 seconds
Started Jul 14 04:22:22 PM PDT 24
Finished Jul 14 04:22:23 PM PDT 24
Peak memory 181992 kb
Host smart-963ac816-40ab-4b76-a516-8cbcd98194c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159353893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.1159353893
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.145045869
Short name T548
Test name
Test status
Simulation time 53998371 ps
CPU time 0.54 seconds
Started Jul 14 04:17:46 PM PDT 24
Finished Jul 14 04:17:47 PM PDT 24
Peak memory 181800 kb
Host smart-8f4d7449-9b0d-4650-aa9b-61a79276b3ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145045869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.145045869
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.747153079
Short name T481
Test name
Test status
Simulation time 13888362 ps
CPU time 0.57 seconds
Started Jul 14 04:17:41 PM PDT 24
Finished Jul 14 04:17:42 PM PDT 24
Peak memory 181624 kb
Host smart-92f03766-89d9-453c-b344-e4077c802189
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747153079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.747153079
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.633881917
Short name T450
Test name
Test status
Simulation time 75746288 ps
CPU time 0.55 seconds
Started Jul 14 04:18:19 PM PDT 24
Finished Jul 14 04:18:20 PM PDT 24
Peak memory 181940 kb
Host smart-64cae437-8455-4f7f-9c6a-eb4b2513ebb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633881917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.633881917
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2291607585
Short name T469
Test name
Test status
Simulation time 13643158 ps
CPU time 0.55 seconds
Started Jul 14 04:18:10 PM PDT 24
Finished Jul 14 04:18:11 PM PDT 24
Peak memory 181984 kb
Host smart-cfff36c6-05b3-4931-8e83-3b21c8df8e97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291607585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2291607585
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3868295272
Short name T503
Test name
Test status
Simulation time 39307287 ps
CPU time 0.55 seconds
Started Jul 14 04:17:46 PM PDT 24
Finished Jul 14 04:17:47 PM PDT 24
Peak memory 181332 kb
Host smart-852bb582-a165-4fd7-b138-23c44950232e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868295272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3868295272
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.491661255
Short name T495
Test name
Test status
Simulation time 22340216 ps
CPU time 0.54 seconds
Started Jul 14 04:17:42 PM PDT 24
Finished Jul 14 04:17:43 PM PDT 24
Peak memory 181628 kb
Host smart-70c43dcc-ee22-4e0d-ae47-72daad82610d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491661255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.491661255
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.3892177959
Short name T509
Test name
Test status
Simulation time 23415484 ps
CPU time 0.69 seconds
Started Jul 14 04:22:01 PM PDT 24
Finished Jul 14 04:22:03 PM PDT 24
Peak memory 194892 kb
Host smart-f8c7549b-93c4-4303-8bbf-5600e92cebfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892177959 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.3892177959
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2447722566
Short name T62
Test name
Test status
Simulation time 14325154 ps
CPU time 0.54 seconds
Started Jul 14 04:23:05 PM PDT 24
Finished Jul 14 04:23:07 PM PDT 24
Peak memory 181844 kb
Host smart-a34ff128-df43-479f-8182-d9b470846212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447722566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2447722566
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.2951124341
Short name T528
Test name
Test status
Simulation time 25979019 ps
CPU time 0.55 seconds
Started Jul 14 04:17:17 PM PDT 24
Finished Jul 14 04:17:19 PM PDT 24
Peak memory 181724 kb
Host smart-3d6872d3-cd79-4945-922c-bc5442deb278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951124341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.2951124341
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2997653736
Short name T558
Test name
Test status
Simulation time 18002114 ps
CPU time 0.76 seconds
Started Jul 14 04:17:16 PM PDT 24
Finished Jul 14 04:17:18 PM PDT 24
Peak memory 191624 kb
Host smart-e064bdc6-d318-4ef8-bd5c-3232ac59dcc9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997653736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2997653736
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4134502335
Short name T523
Test name
Test status
Simulation time 38340012 ps
CPU time 1.69 seconds
Started Jul 14 04:22:02 PM PDT 24
Finished Jul 14 04:22:04 PM PDT 24
Peak memory 196900 kb
Host smart-58cf197d-c3e0-44a2-8263-6bfacd385f14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134502335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4134502335
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3206925817
Short name T515
Test name
Test status
Simulation time 352695002 ps
CPU time 1.23 seconds
Started Jul 14 04:23:07 PM PDT 24
Finished Jul 14 04:23:09 PM PDT 24
Peak memory 180576 kb
Host smart-12a2a2b9-d43b-48e7-8d8f-6d1ba15bba72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206925817 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3206925817
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.3055283858
Short name T514
Test name
Test status
Simulation time 57469071 ps
CPU time 0.74 seconds
Started Jul 14 04:19:29 PM PDT 24
Finished Jul 14 04:19:30 PM PDT 24
Peak memory 194508 kb
Host smart-8502f088-3713-4bf6-b05a-0c1aac497f3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055283858 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.3055283858
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.800802097
Short name T69
Test name
Test status
Simulation time 16729280 ps
CPU time 0.58 seconds
Started Jul 14 04:17:16 PM PDT 24
Finished Jul 14 04:17:18 PM PDT 24
Peak memory 181232 kb
Host smart-8d5f4824-ea47-4b9e-866d-f72c88839022
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800802097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.800802097
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2966440293
Short name T534
Test name
Test status
Simulation time 45636113 ps
CPU time 0.51 seconds
Started Jul 14 04:17:17 PM PDT 24
Finished Jul 14 04:17:18 PM PDT 24
Peak memory 181204 kb
Host smart-205fc8dc-d1ec-480e-9c6f-9ada43d5e298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966440293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2966440293
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.600172867
Short name T64
Test name
Test status
Simulation time 50830846 ps
CPU time 0.71 seconds
Started Jul 14 04:23:07 PM PDT 24
Finished Jul 14 04:23:09 PM PDT 24
Peak memory 188644 kb
Host smart-7d3ea9ef-9f31-412f-bf87-d27ea3244943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600172867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.600172867
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.3119697177
Short name T457
Test name
Test status
Simulation time 374155877 ps
CPU time 2.08 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:22:11 PM PDT 24
Peak memory 195384 kb
Host smart-d2ef6e95-a386-422a-8385-7d41db9d6905
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119697177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.3119697177
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1022844742
Short name T31
Test name
Test status
Simulation time 295210866 ps
CPU time 1.07 seconds
Started Jul 14 04:18:04 PM PDT 24
Finished Jul 14 04:18:06 PM PDT 24
Peak memory 194428 kb
Host smart-b6d0451d-1b94-4cbc-a39f-3316f0eb050e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022844742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1022844742
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.1767821772
Short name T497
Test name
Test status
Simulation time 86353391 ps
CPU time 0.74 seconds
Started Jul 14 04:18:07 PM PDT 24
Finished Jul 14 04:18:09 PM PDT 24
Peak memory 194792 kb
Host smart-510886ca-c025-415b-baf7-f12030a19adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767821772 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.1767821772
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.2068240456
Short name T535
Test name
Test status
Simulation time 21489999 ps
CPU time 0.6 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:22:09 PM PDT 24
Peak memory 180456 kb
Host smart-e4d2e55f-e3dc-42a7-b124-ebfceca49630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068240456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.2068240456
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.3818475304
Short name T480
Test name
Test status
Simulation time 35466371 ps
CPU time 0.75 seconds
Started Jul 14 04:21:48 PM PDT 24
Finished Jul 14 04:21:49 PM PDT 24
Peak memory 190820 kb
Host smart-05aef069-0acb-442f-83ed-f4630d436e0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818475304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.3818475304
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.1806629080
Short name T478
Test name
Test status
Simulation time 29877330 ps
CPU time 1.28 seconds
Started Jul 14 04:21:20 PM PDT 24
Finished Jul 14 04:21:21 PM PDT 24
Peak memory 196924 kb
Host smart-1217fb98-e398-4636-8e4a-4dc325493387
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806629080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.1806629080
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.3072496982
Short name T51
Test name
Test status
Simulation time 241086282 ps
CPU time 1.29 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:23:35 PM PDT 24
Peak memory 194736 kb
Host smart-84ad6e9a-de9f-4f92-b7d6-a442224b0bcc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072496982 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.3072496982
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2601930564
Short name T476
Test name
Test status
Simulation time 70188229 ps
CPU time 1.06 seconds
Started Jul 14 04:17:17 PM PDT 24
Finished Jul 14 04:17:19 PM PDT 24
Peak memory 196496 kb
Host smart-42518c01-6264-4338-b418-5f4b21f19f40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601930564 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2601930564
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.532854641
Short name T569
Test name
Test status
Simulation time 19031937 ps
CPU time 0.59 seconds
Started Jul 14 04:18:07 PM PDT 24
Finished Jul 14 04:18:08 PM PDT 24
Peak memory 182084 kb
Host smart-9cdd6c7d-33c4-4150-9733-679a53a0f44f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532854641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.532854641
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2654369772
Short name T525
Test name
Test status
Simulation time 29681715 ps
CPU time 0.58 seconds
Started Jul 14 04:21:47 PM PDT 24
Finished Jul 14 04:21:49 PM PDT 24
Peak memory 180684 kb
Host smart-234fccaa-cd07-44f7-b288-4d316874d0c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654369772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2654369772
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1201734009
Short name T529
Test name
Test status
Simulation time 64483245 ps
CPU time 0.78 seconds
Started Jul 14 04:17:02 PM PDT 24
Finished Jul 14 04:17:03 PM PDT 24
Peak memory 193160 kb
Host smart-574538c0-57a9-4213-851b-cc202f50d1f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201734009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1201734009
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3219072809
Short name T454
Test name
Test status
Simulation time 370179522 ps
CPU time 2.01 seconds
Started Jul 14 04:17:18 PM PDT 24
Finished Jul 14 04:17:20 PM PDT 24
Peak memory 196840 kb
Host smart-178c1b8a-5bcc-4a65-94ad-e3997fe86e3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219072809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3219072809
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.3425438830
Short name T526
Test name
Test status
Simulation time 1862857821 ps
CPU time 1.27 seconds
Started Jul 14 04:22:23 PM PDT 24
Finished Jul 14 04:22:25 PM PDT 24
Peak memory 194540 kb
Host smart-d2c395ec-4248-48de-96ec-b0e2eceeb766
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425438830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.3425438830
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3376557828
Short name T32
Test name
Test status
Simulation time 60067387 ps
CPU time 0.71 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:23:15 PM PDT 24
Peak memory 194080 kb
Host smart-3ea8848a-e0d7-471e-b767-556bfddbc443
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376557828 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3376557828
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.945831338
Short name T74
Test name
Test status
Simulation time 55723853 ps
CPU time 0.57 seconds
Started Jul 14 04:18:04 PM PDT 24
Finished Jul 14 04:18:05 PM PDT 24
Peak memory 191328 kb
Host smart-b137465b-4aa2-4500-8a9b-32e98140d926
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945831338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.945831338
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.4081703506
Short name T506
Test name
Test status
Simulation time 15117514 ps
CPU time 0.52 seconds
Started Jul 14 04:23:08 PM PDT 24
Finished Jul 14 04:23:09 PM PDT 24
Peak memory 181716 kb
Host smart-38350685-5e03-4b74-84c7-fbbaa0e071d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081703506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.4081703506
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2913442091
Short name T496
Test name
Test status
Simulation time 18366060 ps
CPU time 0.63 seconds
Started Jul 14 04:17:50 PM PDT 24
Finished Jul 14 04:17:51 PM PDT 24
Peak memory 191144 kb
Host smart-c7c6d806-6e80-4422-90bb-e5c751e668d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913442091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2913442091
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.2150159721
Short name T561
Test name
Test status
Simulation time 86061843 ps
CPU time 1.82 seconds
Started Jul 14 04:23:07 PM PDT 24
Finished Jul 14 04:23:10 PM PDT 24
Peak memory 195092 kb
Host smart-f21bfb03-3088-4ef8-956a-1ee11bdf6949
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150159721 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.2150159721
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1024789956
Short name T522
Test name
Test status
Simulation time 111446852 ps
CPU time 1.2 seconds
Started Jul 14 04:21:19 PM PDT 24
Finished Jul 14 04:21:21 PM PDT 24
Peak memory 194732 kb
Host smart-ac46d460-6125-474a-a33b-5891ae40062b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024789956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1024789956
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2833514948
Short name T357
Test name
Test status
Simulation time 386238532104 ps
CPU time 306.77 seconds
Started Jul 14 04:17:43 PM PDT 24
Finished Jul 14 04:22:51 PM PDT 24
Peak memory 182904 kb
Host smart-280cc615-bba8-4005-a454-7e92280c19c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833514948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2833514948
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.437845328
Short name T245
Test name
Test status
Simulation time 85606968561 ps
CPU time 731.17 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:29:21 PM PDT 24
Peak memory 191088 kb
Host smart-bd6eceed-d560-49e4-8a16-8dc40428123a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437845328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.437845328
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2555855612
Short name T59
Test name
Test status
Simulation time 349234476614 ps
CPU time 181.84 seconds
Started Jul 14 04:22:02 PM PDT 24
Finished Jul 14 04:25:05 PM PDT 24
Peak memory 182880 kb
Host smart-6eaca53a-4bb3-40d0-bdda-5f1ac6782729
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555855612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2555855612
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.1984704688
Short name T28
Test name
Test status
Simulation time 27213235254 ps
CPU time 267.73 seconds
Started Jul 14 04:17:11 PM PDT 24
Finished Jul 14 04:21:42 PM PDT 24
Peak memory 197488 kb
Host smart-2fb53ee5-9ce1-4566-842c-47af0aecaf7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984704688 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.1984704688
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2784196922
Short name T121
Test name
Test status
Simulation time 572291547117 ps
CPU time 283.7 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:21:55 PM PDT 24
Peak memory 181276 kb
Host smart-6a8c6eb5-f41b-4f0e-8d75-a0c7a1c5a73b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784196922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2784196922
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.2061547394
Short name T441
Test name
Test status
Simulation time 4482294135 ps
CPU time 3.79 seconds
Started Jul 14 04:17:10 PM PDT 24
Finished Jul 14 04:17:17 PM PDT 24
Peak memory 193692 kb
Host smart-06dc0694-910b-4ba9-8860-d44c501e8947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061547394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.2061547394
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1448534805
Short name T15
Test name
Test status
Simulation time 58945882 ps
CPU time 0.94 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:12 PM PDT 24
Peak memory 211860 kb
Host smart-ce43a06b-fefb-4272-9628-8a9d1f34002f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448534805 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1448534805
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.3042706928
Short name T313
Test name
Test status
Simulation time 596345668053 ps
CPU time 320.08 seconds
Started Jul 14 04:22:27 PM PDT 24
Finished Jul 14 04:27:50 PM PDT 24
Peak memory 182592 kb
Host smart-2b1eb711-11cd-4e40-b20a-6973f6b0554c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042706928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.3042706928
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1323268445
Short name T387
Test name
Test status
Simulation time 128500302773 ps
CPU time 195.42 seconds
Started Jul 14 04:18:52 PM PDT 24
Finished Jul 14 04:22:08 PM PDT 24
Peak memory 182880 kb
Host smart-64b4ef02-14a0-4f38-9585-413a1fb1c62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323268445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1323268445
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3919599058
Short name T233
Test name
Test status
Simulation time 33315620392 ps
CPU time 231.56 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:26:33 PM PDT 24
Peak memory 182908 kb
Host smart-f831c4da-e95c-43ea-816a-552bb8a20456
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919599058 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3919599058
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.944739752
Short name T438
Test name
Test status
Simulation time 3561900987 ps
CPU time 2.14 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:22:44 PM PDT 24
Peak memory 193944 kb
Host smart-f70c8f09-85dc-4a40-aec0-70f3a9907d4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944739752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.944739752
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.3610056414
Short name T301
Test name
Test status
Simulation time 1309289048661 ps
CPU time 645.99 seconds
Started Jul 14 04:22:25 PM PDT 24
Finished Jul 14 04:33:12 PM PDT 24
Peak memory 195912 kb
Host smart-c7a6281e-94df-4bef-8b97-2418a614c7e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610056414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.3610056414
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.4200616137
Short name T329
Test name
Test status
Simulation time 41072323194 ps
CPU time 931.54 seconds
Started Jul 14 04:21:44 PM PDT 24
Finished Jul 14 04:37:17 PM PDT 24
Peak memory 191300 kb
Host smart-17b9b621-72f3-4a04-9582-45d4caaacd3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200616137 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.4200616137
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.1460046987
Short name T266
Test name
Test status
Simulation time 36248670469 ps
CPU time 26.19 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:23:29 PM PDT 24
Peak memory 181396 kb
Host smart-9a4bd1ad-c4ba-413e-992c-57420b476bba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460046987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.1460046987
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.1913980797
Short name T426
Test name
Test status
Simulation time 58977962844 ps
CPU time 37.16 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:23:40 PM PDT 24
Peak memory 182292 kb
Host smart-0e6f2232-eb56-4e31-a397-14678e1d5431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913980797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.1913980797
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.1211385007
Short name T400
Test name
Test status
Simulation time 43046615014 ps
CPU time 207 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:26:29 PM PDT 24
Peak memory 189168 kb
Host smart-ffd85e23-a54f-460f-b6e9-6dd374c9921f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211385007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.1211385007
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.4024158089
Short name T348
Test name
Test status
Simulation time 52438343639 ps
CPU time 212.13 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:26:35 PM PDT 24
Peak memory 190460 kb
Host smart-135e3fbf-8d38-4ad9-aa83-84e257842ebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024158089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.4024158089
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.851899029
Short name T163
Test name
Test status
Simulation time 394344967724 ps
CPU time 180.18 seconds
Started Jul 14 04:23:18 PM PDT 24
Finished Jul 14 04:26:20 PM PDT 24
Peak memory 191076 kb
Host smart-c55c6ca4-8567-4abd-83bc-b5bff3524b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851899029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.851899029
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3221264631
Short name T419
Test name
Test status
Simulation time 13631666541 ps
CPU time 20.36 seconds
Started Jul 14 04:18:50 PM PDT 24
Finished Jul 14 04:19:11 PM PDT 24
Peak memory 183060 kb
Host smart-2462bab4-c682-4c34-a68c-fd1676be7956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221264631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3221264631
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2440736278
Short name T417
Test name
Test status
Simulation time 37621421893 ps
CPU time 58.43 seconds
Started Jul 14 04:17:56 PM PDT 24
Finished Jul 14 04:18:55 PM PDT 24
Peak memory 182920 kb
Host smart-763e79f2-6968-4178-a048-366c7d7d8a11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440736278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2440736278
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2296802868
Short name T383
Test name
Test status
Simulation time 648838735 ps
CPU time 2.25 seconds
Started Jul 14 04:22:44 PM PDT 24
Finished Jul 14 04:22:50 PM PDT 24
Peak memory 192956 kb
Host smart-9e08a635-cb4d-4d1d-ae59-dbb42ae9c254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296802868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2296802868
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1805799029
Short name T360
Test name
Test status
Simulation time 88941918 ps
CPU time 0.67 seconds
Started Jul 14 04:22:45 PM PDT 24
Finished Jul 14 04:22:48 PM PDT 24
Peak memory 181232 kb
Host smart-9c6cb8ae-3d7a-46bf-8b22-56d4d3cb5e5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805799029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1805799029
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/110.rv_timer_random.1152150421
Short name T302
Test name
Test status
Simulation time 106379793927 ps
CPU time 161.74 seconds
Started Jul 14 04:23:18 PM PDT 24
Finished Jul 14 04:26:01 PM PDT 24
Peak memory 191076 kb
Host smart-9e0cdef0-7df5-41c9-ba2a-95fbe4d6c389
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152150421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.1152150421
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.2491538097
Short name T137
Test name
Test status
Simulation time 391903082927 ps
CPU time 238.72 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:25:54 PM PDT 24
Peak memory 191092 kb
Host smart-faa35b6f-9dec-4106-a19f-02768fd4837f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491538097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2491538097
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1814620662
Short name T376
Test name
Test status
Simulation time 85575070673 ps
CPU time 719.35 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:35:13 PM PDT 24
Peak memory 182488 kb
Host smart-ba17e195-edf8-42c2-81d4-c1e140215156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814620662 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1814620662
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3807916161
Short name T406
Test name
Test status
Simulation time 107659608759 ps
CPU time 44.8 seconds
Started Jul 14 04:21:55 PM PDT 24
Finished Jul 14 04:22:42 PM PDT 24
Peak memory 182928 kb
Host smart-e58cdda9-6761-4c13-8331-cb5d9ebabba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807916161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3807916161
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.1654035592
Short name T425
Test name
Test status
Simulation time 430785545011 ps
CPU time 298.7 seconds
Started Jul 14 04:22:02 PM PDT 24
Finished Jul 14 04:27:02 PM PDT 24
Peak memory 191120 kb
Host smart-86002c7b-78eb-4aaf-9cf6-fe18ba688968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654035592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.1654035592
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.2705555494
Short name T374
Test name
Test status
Simulation time 640245734094 ps
CPU time 198.89 seconds
Started Jul 14 04:18:53 PM PDT 24
Finished Jul 14 04:22:12 PM PDT 24
Peak memory 182912 kb
Host smart-f6453409-63ed-40e3-9bc7-caf9c1039d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705555494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.2705555494
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.2166420037
Short name T131
Test name
Test status
Simulation time 685722624461 ps
CPU time 479.74 seconds
Started Jul 14 04:17:56 PM PDT 24
Finished Jul 14 04:25:56 PM PDT 24
Peak memory 194624 kb
Host smart-a494258a-a8bd-4efa-8772-c555328f2599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166420037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2166420037
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.2526888005
Short name T271
Test name
Test status
Simulation time 66000257317 ps
CPU time 44.24 seconds
Started Jul 14 04:23:16 PM PDT 24
Finished Jul 14 04:24:02 PM PDT 24
Peak memory 194780 kb
Host smart-0ba4cbab-e2a2-4a63-8e82-7ecca6724ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526888005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.2526888005
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/122.rv_timer_random.364745967
Short name T89
Test name
Test status
Simulation time 355045688568 ps
CPU time 190.73 seconds
Started Jul 14 04:22:16 PM PDT 24
Finished Jul 14 04:25:27 PM PDT 24
Peak memory 194532 kb
Host smart-95ff66c8-05c6-467e-b622-0c006ebce256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364745967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.364745967
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1093160060
Short name T114
Test name
Test status
Simulation time 619409479025 ps
CPU time 716.82 seconds
Started Jul 14 04:23:43 PM PDT 24
Finished Jul 14 04:35:42 PM PDT 24
Peak memory 190664 kb
Host smart-67f266fb-ed68-4221-bbc8-804da1433f3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093160060 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1093160060
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.3942104777
Short name T5
Test name
Test status
Simulation time 81114265542 ps
CPU time 96.95 seconds
Started Jul 14 04:22:20 PM PDT 24
Finished Jul 14 04:23:58 PM PDT 24
Peak memory 191080 kb
Host smart-4b248474-5a96-401f-9ef7-51c9b5d52150
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942104777 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.3942104777
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.1019201927
Short name T346
Test name
Test status
Simulation time 251593005464 ps
CPU time 192.69 seconds
Started Jul 14 04:22:28 PM PDT 24
Finished Jul 14 04:25:42 PM PDT 24
Peak memory 194472 kb
Host smart-519e0bbb-0a67-4cb3-9f34-d33eabaf53fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019201927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.1019201927
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.178745831
Short name T372
Test name
Test status
Simulation time 214978757060 ps
CPU time 144.96 seconds
Started Jul 14 04:22:21 PM PDT 24
Finished Jul 14 04:24:47 PM PDT 24
Peak memory 191156 kb
Host smart-74a1cc4c-489e-4162-b52e-88e79ef8e66a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178745831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.178745831
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1064102858
Short name T367
Test name
Test status
Simulation time 165998136972 ps
CPU time 106.01 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:24:14 PM PDT 24
Peak memory 182668 kb
Host smart-cad4a649-12db-4e04-b3e3-f2ad97f7cd09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064102858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1064102858
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.1817593935
Short name T349
Test name
Test status
Simulation time 591943989305 ps
CPU time 154.76 seconds
Started Jul 14 04:23:03 PM PDT 24
Finished Jul 14 04:25:40 PM PDT 24
Peak memory 182080 kb
Host smart-56f57b28-ea3d-4b4a-9a4a-1fe7fedf84e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817593935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.1817593935
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.4100305684
Short name T420
Test name
Test status
Simulation time 877109843 ps
CPU time 1.78 seconds
Started Jul 14 04:22:24 PM PDT 24
Finished Jul 14 04:22:27 PM PDT 24
Peak memory 180728 kb
Host smart-29c40c71-d28c-4dd4-827a-c807c028def3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100305684 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.4100305684
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.562319217
Short name T354
Test name
Test status
Simulation time 366502743290 ps
CPU time 475.77 seconds
Started Jul 14 04:23:16 PM PDT 24
Finished Jul 14 04:31:13 PM PDT 24
Peak memory 190832 kb
Host smart-90d0ce24-25c0-4bda-aea1-20ebd8942f21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562319217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all.
562319217
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/132.rv_timer_random.2981038030
Short name T159
Test name
Test status
Simulation time 184804750627 ps
CPU time 296.79 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:27:43 PM PDT 24
Peak memory 191000 kb
Host smart-4d1e825c-0f12-4647-9aaa-08ef9e97227b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981038030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.2981038030
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.631167710
Short name T284
Test name
Test status
Simulation time 834646253128 ps
CPU time 433.81 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:29:55 PM PDT 24
Peak memory 191108 kb
Host smart-55508eb8-6a3d-4a62-b842-4ccfd0c93632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631167710 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.631167710
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.780274435
Short name T171
Test name
Test status
Simulation time 573830271745 ps
CPU time 769.92 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:35:22 PM PDT 24
Peak memory 191128 kb
Host smart-dab7d742-c108-4905-9f69-4906a0f77e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780274435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.780274435
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.3706420932
Short name T283
Test name
Test status
Simulation time 1194034762 ps
CPU time 2.51 seconds
Started Jul 14 04:22:35 PM PDT 24
Finished Jul 14 04:22:38 PM PDT 24
Peak memory 182716 kb
Host smart-e2f3008e-11c7-403f-9fd9-336e075d3e32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706420932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.3706420932
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3787648801
Short name T300
Test name
Test status
Simulation time 137429661057 ps
CPU time 52.41 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 182640 kb
Host smart-453eaa6b-4b81-48c6-8dd8-c63d7f6c44fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787648801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3787648801
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1253376012
Short name T123
Test name
Test status
Simulation time 566323145026 ps
CPU time 374.6 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:28:59 PM PDT 24
Peak memory 191044 kb
Host smart-72ef238b-1531-4868-991f-8e62c6a73bb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253376012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1253376012
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2448776381
Short name T240
Test name
Test status
Simulation time 57766264313 ps
CPU time 79.81 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:24:06 PM PDT 24
Peak memory 191020 kb
Host smart-92e89a4a-0f3c-43b3-95b1-f1c2ec6a1fdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448776381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2448776381
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.3909865241
Short name T391
Test name
Test status
Simulation time 70564025346 ps
CPU time 94.47 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:23:36 PM PDT 24
Peak memory 182632 kb
Host smart-e381132a-8bab-418b-9933-94f7032396fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909865241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.3909865241
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1352069648
Short name T174
Test name
Test status
Simulation time 69200062567 ps
CPU time 44.45 seconds
Started Jul 14 04:21:04 PM PDT 24
Finished Jul 14 04:21:49 PM PDT 24
Peak memory 182924 kb
Host smart-3a9a497d-e693-426a-a937-17ea52ed9882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352069648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1352069648
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.956872884
Short name T347
Test name
Test status
Simulation time 69164200255 ps
CPU time 36.74 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:23:22 PM PDT 24
Peak memory 182680 kb
Host smart-7ad1e942-a994-4151-b0cf-7b0db3a700c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956872884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.956872884
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.1839233400
Short name T58
Test name
Test status
Simulation time 689612488948 ps
CPU time 794.04 seconds
Started Jul 14 04:22:32 PM PDT 24
Finished Jul 14 04:35:49 PM PDT 24
Peak memory 189484 kb
Host smart-1d457379-abac-4a62-858e-e79dee32d80c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839233400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.1839233400
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/141.rv_timer_random.998920
Short name T336
Test name
Test status
Simulation time 204426127804 ps
CPU time 127.82 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:24:54 PM PDT 24
Peak memory 194204 kb
Host smart-aeb01be9-a474-4754-aaf6-d07db8d8aac5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.998920
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.3497395793
Short name T323
Test name
Test status
Simulation time 250990615010 ps
CPU time 212.23 seconds
Started Jul 14 04:23:33 PM PDT 24
Finished Jul 14 04:27:09 PM PDT 24
Peak memory 191912 kb
Host smart-303a89df-ad3c-4fe7-9d27-386c834a1eb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497395793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.3497395793
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2563176794
Short name T203
Test name
Test status
Simulation time 45321442934 ps
CPU time 71.22 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:23:57 PM PDT 24
Peak memory 190892 kb
Host smart-4dd9c82f-3245-4d20-ad70-aef2d9703677
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563176794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2563176794
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2986935821
Short name T22
Test name
Test status
Simulation time 457813902825 ps
CPU time 235.66 seconds
Started Jul 14 04:22:34 PM PDT 24
Finished Jul 14 04:26:31 PM PDT 24
Peak memory 191120 kb
Host smart-cfa1dc57-2361-4e0a-8890-0986a7fbd23f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986935821 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2986935821
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.2061417556
Short name T157
Test name
Test status
Simulation time 179246627281 ps
CPU time 410.29 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:29:23 PM PDT 24
Peak memory 191236 kb
Host smart-3bcc76c8-0e63-4b2e-aa10-e5cdcc50824e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061417556 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2061417556
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3325548212
Short name T296
Test name
Test status
Simulation time 612720527917 ps
CPU time 332.58 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:28:05 PM PDT 24
Peak memory 191156 kb
Host smart-5e9a8636-7039-4016-a279-375aa0e50a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325548212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3325548212
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3753674451
Short name T254
Test name
Test status
Simulation time 314104735457 ps
CPU time 259 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:27:00 PM PDT 24
Peak memory 191104 kb
Host smart-e3a3cc65-b48d-45c2-9315-ff0bda996899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753674451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3753674451
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1408035837
Short name T437
Test name
Test status
Simulation time 55944872606 ps
CPU time 87.51 seconds
Started Jul 14 04:19:52 PM PDT 24
Finished Jul 14 04:21:20 PM PDT 24
Peak memory 182948 kb
Host smart-27e8a867-997e-49a4-84c8-89e5cc2703a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408035837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1408035837
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.604377386
Short name T167
Test name
Test status
Simulation time 72148560122 ps
CPU time 101.64 seconds
Started Jul 14 04:21:04 PM PDT 24
Finished Jul 14 04:22:47 PM PDT 24
Peak memory 191512 kb
Host smart-336dc873-98cd-4614-9bbc-5f5aa84c96bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604377386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.604377386
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.538173781
Short name T21
Test name
Test status
Simulation time 246019013922 ps
CPU time 111.26 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:24:36 PM PDT 24
Peak memory 195080 kb
Host smart-0b86d1a7-edee-4e7d-9ba1-364444704ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538173781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.538173781
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.745931972
Short name T415
Test name
Test status
Simulation time 1024480374935 ps
CPU time 302.5 seconds
Started Jul 14 04:18:36 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 194688 kb
Host smart-743b94b8-e8ba-4e9b-8757-2c1c353d7435
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745931972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
745931972
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/151.rv_timer_random.3693878270
Short name T184
Test name
Test status
Simulation time 56075759375 ps
CPU time 102.03 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:24:24 PM PDT 24
Peak memory 193908 kb
Host smart-257db35e-8e2a-413a-beb3-2a1fc4166157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693878270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3693878270
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2545688296
Short name T83
Test name
Test status
Simulation time 65564997870 ps
CPU time 54.4 seconds
Started Jul 14 04:22:29 PM PDT 24
Finished Jul 14 04:23:26 PM PDT 24
Peak memory 182916 kb
Host smart-7c0bc51f-3955-4984-a16b-378e6e3bf80e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545688296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2545688296
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.1529529567
Short name T258
Test name
Test status
Simulation time 421704477577 ps
CPU time 234.31 seconds
Started Jul 14 04:22:38 PM PDT 24
Finished Jul 14 04:26:34 PM PDT 24
Peak memory 191096 kb
Host smart-2e98bcee-27b8-456e-9638-fb36b1036443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529529567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.1529529567
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.1109049427
Short name T422
Test name
Test status
Simulation time 174383844704 ps
CPU time 71.01 seconds
Started Jul 14 04:22:32 PM PDT 24
Finished Jul 14 04:23:45 PM PDT 24
Peak memory 182660 kb
Host smart-cab7df9d-36dd-4cb6-8b37-1ba08659bd70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109049427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.1109049427
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3950125132
Short name T239
Test name
Test status
Simulation time 106885665006 ps
CPU time 234.16 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:26:37 PM PDT 24
Peak memory 194616 kb
Host smart-d5263525-4787-4731-96c3-c54cf4ca9789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950125132 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3950125132
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1325882300
Short name T237
Test name
Test status
Simulation time 220287921984 ps
CPU time 182.02 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:25:48 PM PDT 24
Peak memory 190968 kb
Host smart-503e57ff-f28d-41e7-9451-096ba83ccb0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325882300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1325882300
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3454255733
Short name T201
Test name
Test status
Simulation time 40868982969 ps
CPU time 198.59 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:26:05 PM PDT 24
Peak memory 182560 kb
Host smart-de60d64c-b492-49b2-8ea8-1baa50ec3dba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454255733 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3454255733
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1724530732
Short name T259
Test name
Test status
Simulation time 36906621253 ps
CPU time 58.01 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:23:44 PM PDT 24
Peak memory 182676 kb
Host smart-51a0d685-0439-46cd-b78a-d12d7284c449
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724530732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1724530732
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3572652218
Short name T177
Test name
Test status
Simulation time 2132494339424 ps
CPU time 416.83 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:29:38 PM PDT 24
Peak memory 191104 kb
Host smart-8d666d7a-5930-4f50-b9e4-7aa804bc0fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572652218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3572652218
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.4229810449
Short name T272
Test name
Test status
Simulation time 447063988223 ps
CPU time 683.83 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:34:26 PM PDT 24
Peak memory 181236 kb
Host smart-af6b826c-b4a6-4482-82cf-5580833c4329
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229810449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.4229810449
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.1239032861
Short name T447
Test name
Test status
Simulation time 47557138419 ps
CPU time 60.18 seconds
Started Jul 14 04:21:47 PM PDT 24
Finished Jul 14 04:22:49 PM PDT 24
Peak memory 181728 kb
Host smart-af3cb956-14ee-4028-b4f4-b36ee759cebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239032861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.1239032861
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.504885352
Short name T333
Test name
Test status
Simulation time 1031995840540 ps
CPU time 191.56 seconds
Started Jul 14 04:22:03 PM PDT 24
Finished Jul 14 04:25:16 PM PDT 24
Peak memory 190088 kb
Host smart-8bd450c7-e534-4a5c-9f3e-a13e26382c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504885352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.504885352
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.1926432412
Short name T427
Test name
Test status
Simulation time 206170748692 ps
CPU time 1211.34 seconds
Started Jul 14 04:21:56 PM PDT 24
Finished Jul 14 04:42:10 PM PDT 24
Peak memory 194416 kb
Host smart-61272cb8-6b6d-4aa3-887a-b5f678029239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926432412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.1926432412
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.4165317576
Short name T382
Test name
Test status
Simulation time 16978976 ps
CPU time 0.61 seconds
Started Jul 14 04:22:03 PM PDT 24
Finished Jul 14 04:22:05 PM PDT 24
Peak memory 181696 kb
Host smart-e87e2695-3852-4738-b806-33ec1440e7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165317576 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.4165317576
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.463231346
Short name T187
Test name
Test status
Simulation time 191374959155 ps
CPU time 403.22 seconds
Started Jul 14 04:22:31 PM PDT 24
Finished Jul 14 04:29:17 PM PDT 24
Peak memory 191124 kb
Host smart-30cae5c1-e1c6-4ea1-81fe-4745b07bd697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463231346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.463231346
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.1005637162
Short name T295
Test name
Test status
Simulation time 271055483570 ps
CPU time 167.77 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:25:29 PM PDT 24
Peak memory 193324 kb
Host smart-d16e6ec7-ea8b-46aa-a04e-1d697a1a67a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005637162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.1005637162
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.1297250273
Short name T322
Test name
Test status
Simulation time 212364618953 ps
CPU time 83.76 seconds
Started Jul 14 04:23:33 PM PDT 24
Finished Jul 14 04:25:00 PM PDT 24
Peak memory 181388 kb
Host smart-dec99574-c43e-46f9-b4fe-ddfd9826eeb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297250273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1297250273
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.3197021236
Short name T276
Test name
Test status
Simulation time 46654060540 ps
CPU time 84.72 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:24:11 PM PDT 24
Peak memory 182876 kb
Host smart-b7f0641d-a89e-4d20-8485-6714f839fa68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197021236 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.3197021236
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1822451697
Short name T219
Test name
Test status
Simulation time 425492075236 ps
CPU time 667.65 seconds
Started Jul 14 04:22:37 PM PDT 24
Finished Jul 14 04:33:45 PM PDT 24
Peak memory 191284 kb
Host smart-470cd3fd-171e-46e4-bf81-ba861013d0d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822451697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1822451697
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2848979016
Short name T185
Test name
Test status
Simulation time 879060599264 ps
CPU time 692.16 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:34:13 PM PDT 24
Peak memory 191108 kb
Host smart-1c185896-7695-4d9e-8a2a-f9f0be255c11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848979016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2848979016
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.38727887
Short name T328
Test name
Test status
Simulation time 245080226309 ps
CPU time 123.8 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:24:50 PM PDT 24
Peak memory 190996 kb
Host smart-1b3415e6-1028-44f8-a388-73dc25eaf250
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38727887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.38727887
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2697832690
Short name T363
Test name
Test status
Simulation time 511309240211 ps
CPU time 148.9 seconds
Started Jul 14 04:21:57 PM PDT 24
Finished Jul 14 04:24:28 PM PDT 24
Peak memory 182696 kb
Host smart-9d2a0ada-b36e-47cb-a3c5-c03efd865491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697832690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2697832690
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.3620801669
Short name T289
Test name
Test status
Simulation time 35927470770 ps
CPU time 57.58 seconds
Started Jul 14 04:21:57 PM PDT 24
Finished Jul 14 04:22:56 PM PDT 24
Peak memory 182688 kb
Host smart-a38bdfc1-ce0f-4f02-944e-44f321a080ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620801669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.3620801669
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2678100192
Short name T424
Test name
Test status
Simulation time 340043618 ps
CPU time 0.7 seconds
Started Jul 14 04:22:09 PM PDT 24
Finished Jul 14 04:22:11 PM PDT 24
Peak memory 182940 kb
Host smart-8f53bf1e-97cc-4ea5-9c06-7fb543431319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678100192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2678100192
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2955185431
Short name T355
Test name
Test status
Simulation time 1593710049339 ps
CPU time 466.73 seconds
Started Jul 14 04:23:04 PM PDT 24
Finished Jul 14 04:30:52 PM PDT 24
Peak memory 190200 kb
Host smart-d0dbdd7e-2084-4a4b-9d48-8e3558c2c97c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955185431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2955185431
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all_with_rand_reset.1840356798
Short name T38
Test name
Test status
Simulation time 220096093689 ps
CPU time 389.09 seconds
Started Jul 14 04:21:57 PM PDT 24
Finished Jul 14 04:28:28 PM PDT 24
Peak memory 197400 kb
Host smart-124362e3-eb3e-4449-8b16-c6f946d22942
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840356798 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all_with_rand_reset.1840356798
Directory /workspace/17.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/170.rv_timer_random.2091377059
Short name T264
Test name
Test status
Simulation time 89171499097 ps
CPU time 1454.09 seconds
Started Jul 14 04:22:34 PM PDT 24
Finished Jul 14 04:46:50 PM PDT 24
Peak memory 182920 kb
Host smart-6d0b0505-36df-4558-b3e1-add6881f709e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091377059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.2091377059
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1314953261
Short name T161
Test name
Test status
Simulation time 340637250268 ps
CPU time 180.92 seconds
Started Jul 14 04:22:40 PM PDT 24
Finished Jul 14 04:25:42 PM PDT 24
Peak memory 191096 kb
Host smart-48b0845f-12e3-4a26-aa1f-202244ee9157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314953261 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1314953261
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.2270450164
Short name T246
Test name
Test status
Simulation time 1961966111 ps
CPU time 3.22 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:22:47 PM PDT 24
Peak memory 182748 kb
Host smart-8776ec08-a716-4943-aed0-06b00d98a0b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270450164 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.2270450164
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3014515855
Short name T278
Test name
Test status
Simulation time 321267506500 ps
CPU time 397.27 seconds
Started Jul 14 04:22:49 PM PDT 24
Finished Jul 14 04:29:27 PM PDT 24
Peak memory 191120 kb
Host smart-56b825f9-5347-4d1c-9ce0-1ff338cfe166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014515855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3014515855
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2595809011
Short name T188
Test name
Test status
Simulation time 109738632715 ps
CPU time 273.56 seconds
Started Jul 14 04:22:45 PM PDT 24
Finished Jul 14 04:27:21 PM PDT 24
Peak memory 191124 kb
Host smart-454ec90d-9116-473b-8c15-24aa8510dda4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595809011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2595809011
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3164270875
Short name T97
Test name
Test status
Simulation time 280415826660 ps
CPU time 707.02 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:34:32 PM PDT 24
Peak memory 191112 kb
Host smart-1620c423-50a6-4e22-a628-c13141b56342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164270875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3164270875
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1170803746
Short name T178
Test name
Test status
Simulation time 154063224590 ps
CPU time 1820.1 seconds
Started Jul 14 04:22:49 PM PDT 24
Finished Jul 14 04:53:10 PM PDT 24
Peak memory 191284 kb
Host smart-69d4fc33-e854-4de5-aab6-c7e5456a6c2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170803746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1170803746
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.3899808857
Short name T132
Test name
Test status
Simulation time 346533981017 ps
CPU time 175.24 seconds
Started Jul 14 04:22:45 PM PDT 24
Finished Jul 14 04:25:43 PM PDT 24
Peak memory 191140 kb
Host smart-5ed4ae8d-3a8b-43ca-8ce6-ad090e1ed693
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899808857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.3899808857
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3376999553
Short name T260
Test name
Test status
Simulation time 99003876433 ps
CPU time 162.24 seconds
Started Jul 14 04:22:18 PM PDT 24
Finished Jul 14 04:25:02 PM PDT 24
Peak memory 181908 kb
Host smart-3e97e92e-080d-495e-90b8-09ea7aef14b2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376999553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3376999553
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2743738455
Short name T403
Test name
Test status
Simulation time 698254921028 ps
CPU time 280.1 seconds
Started Jul 14 04:18:49 PM PDT 24
Finished Jul 14 04:23:30 PM PDT 24
Peak memory 182872 kb
Host smart-55a50835-090e-4a04-a5c5-69fd3374cda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743738455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2743738455
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.4153492297
Short name T244
Test name
Test status
Simulation time 652734197913 ps
CPU time 2006.82 seconds
Started Jul 14 04:23:31 PM PDT 24
Finished Jul 14 04:57:00 PM PDT 24
Peak memory 190872 kb
Host smart-f611ef15-bfda-40d7-ade1-8dfe909de86e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153492297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.4153492297
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.3738035539
Short name T309
Test name
Test status
Simulation time 200617154869 ps
CPU time 79.49 seconds
Started Jul 14 04:22:33 PM PDT 24
Finished Jul 14 04:23:54 PM PDT 24
Peak memory 182900 kb
Host smart-d38e2729-725d-41ce-bbcf-449b063364a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738035539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.3738035539
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.3822485888
Short name T175
Test name
Test status
Simulation time 275253831513 ps
CPU time 852.13 seconds
Started Jul 14 04:22:00 PM PDT 24
Finished Jul 14 04:36:14 PM PDT 24
Peak memory 194404 kb
Host smart-e0717928-3b16-4ee3-b371-43be4a889f0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822485888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.3822485888
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/183.rv_timer_random.3092908870
Short name T267
Test name
Test status
Simulation time 90312598256 ps
CPU time 44.08 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:23:27 PM PDT 24
Peak memory 193744 kb
Host smart-734b0b46-1a52-49df-85ea-d8765861a229
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092908870 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.3092908870
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3877945169
Short name T225
Test name
Test status
Simulation time 69404963620 ps
CPU time 420.48 seconds
Started Jul 14 04:22:50 PM PDT 24
Finished Jul 14 04:29:51 PM PDT 24
Peak memory 191176 kb
Host smart-2e7f526d-ae97-44b5-826b-25ff6c1535d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877945169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3877945169
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.2154802177
Short name T436
Test name
Test status
Simulation time 154745048650 ps
CPU time 129.27 seconds
Started Jul 14 04:22:54 PM PDT 24
Finished Jul 14 04:25:03 PM PDT 24
Peak memory 191064 kb
Host smart-16a36dce-4ef0-4f7f-ad44-7fa7ad9c332b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154802177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.2154802177
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.4117165079
Short name T290
Test name
Test status
Simulation time 163803782242 ps
CPU time 629.19 seconds
Started Jul 14 04:22:44 PM PDT 24
Finished Jul 14 04:33:16 PM PDT 24
Peak memory 191060 kb
Host smart-b3e9020f-8963-4d1e-86a4-557c66e06a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117165079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.4117165079
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.1901781047
Short name T9
Test name
Test status
Simulation time 31635822742 ps
CPU time 26.76 seconds
Started Jul 14 04:22:32 PM PDT 24
Finished Jul 14 04:23:01 PM PDT 24
Peak memory 182896 kb
Host smart-65d1ab37-fd7a-434f-b39d-0b0e514eeae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901781047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.1901781047
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.3442380265
Short name T90
Test name
Test status
Simulation time 26192065 ps
CPU time 0.55 seconds
Started Jul 14 04:17:57 PM PDT 24
Finished Jul 14 04:17:58 PM PDT 24
Peak memory 182740 kb
Host smart-6ca5261f-0068-492c-a693-ae3b17011a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442380265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.3442380265
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.1979528489
Short name T199
Test name
Test status
Simulation time 761951317607 ps
CPU time 169.46 seconds
Started Jul 14 04:22:00 PM PDT 24
Finished Jul 14 04:24:51 PM PDT 24
Peak memory 181644 kb
Host smart-6a1c12ee-c63b-42a5-97c1-9f168e948e41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979528489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.1979528489
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/192.rv_timer_random.2629670163
Short name T173
Test name
Test status
Simulation time 157325302532 ps
CPU time 705.61 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:34:32 PM PDT 24
Peak memory 191052 kb
Host smart-1b98cc9a-822d-4d34-9b4b-4455b0d3fbab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629670163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2629670163
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.376687596
Short name T241
Test name
Test status
Simulation time 172441962944 ps
CPU time 871.84 seconds
Started Jul 14 04:22:45 PM PDT 24
Finished Jul 14 04:37:19 PM PDT 24
Peak memory 193496 kb
Host smart-07062532-ff0e-4aa4-8e5b-73d0ba16458b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376687596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.376687596
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1815306580
Short name T84
Test name
Test status
Simulation time 211235567749 ps
CPU time 1120.61 seconds
Started Jul 14 04:22:46 PM PDT 24
Finished Jul 14 04:41:28 PM PDT 24
Peak memory 191156 kb
Host smart-ea107594-0995-4919-95f1-f7a91a3bd521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815306580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1815306580
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1756618641
Short name T297
Test name
Test status
Simulation time 3849545627 ps
CPU time 4.16 seconds
Started Jul 14 04:23:42 PM PDT 24
Finished Jul 14 04:23:48 PM PDT 24
Peak memory 182728 kb
Host smart-fdeb92ab-2052-4519-8ea8-a5ce4c3d547d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756618641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1756618641
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.464947893
Short name T320
Test name
Test status
Simulation time 104665519079 ps
CPU time 544.31 seconds
Started Jul 14 04:22:50 PM PDT 24
Finished Jul 14 04:31:55 PM PDT 24
Peak memory 191120 kb
Host smart-49db47b9-9933-4376-8415-3e1607440669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464947893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.464947893
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.2554564773
Short name T160
Test name
Test status
Simulation time 1098163648176 ps
CPU time 312.68 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:27:57 PM PDT 24
Peak memory 191112 kb
Host smart-6fd8b2e3-3c4e-4cc8-8753-824eec6df747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554564773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.2554564773
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3662473658
Short name T326
Test name
Test status
Simulation time 138749897689 ps
CPU time 55.62 seconds
Started Jul 14 04:22:42 PM PDT 24
Finished Jul 14 04:23:40 PM PDT 24
Peak memory 182908 kb
Host smart-3c91538a-1812-450c-9c77-566ffb610993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662473658 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3662473658
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1705634567
Short name T105
Test name
Test status
Simulation time 976178107628 ps
CPU time 436.44 seconds
Started Jul 14 04:17:12 PM PDT 24
Finished Jul 14 04:24:30 PM PDT 24
Peak memory 182688 kb
Host smart-4a51b4bc-44da-4a41-b402-ed65b66b847d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705634567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1705634567
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_random.311503204
Short name T106
Test name
Test status
Simulation time 184619422623 ps
CPU time 100.36 seconds
Started Jul 14 04:17:11 PM PDT 24
Finished Jul 14 04:18:54 PM PDT 24
Peak memory 190936 kb
Host smart-619cfb04-a43b-499b-8336-b4cdad1b543c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311503204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.311503204
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.3210892707
Short name T362
Test name
Test status
Simulation time 1309160835 ps
CPU time 1.71 seconds
Started Jul 14 04:21:49 PM PDT 24
Finished Jul 14 04:21:51 PM PDT 24
Peak memory 181724 kb
Host smart-0cfe6564-dc47-46cc-bbdb-902f8d3c1d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210892707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.3210892707
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2185064988
Short name T18
Test name
Test status
Simulation time 85973039 ps
CPU time 0.89 seconds
Started Jul 14 04:17:09 PM PDT 24
Finished Jul 14 04:17:11 PM PDT 24
Peak memory 214272 kb
Host smart-d0d07712-31a0-4ad4-9393-8ebf5f9e221f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185064988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2185064988
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.1542623989
Short name T1
Test name
Test status
Simulation time 1106400989758 ps
CPU time 520.97 seconds
Started Jul 14 04:17:11 PM PDT 24
Finished Jul 14 04:25:54 PM PDT 24
Peak memory 190936 kb
Host smart-07041777-393a-4bcd-8d69-b04fdb808da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542623989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
1542623989
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1835843490
Short name T197
Test name
Test status
Simulation time 658116483984 ps
CPU time 386.16 seconds
Started Jul 14 04:23:19 PM PDT 24
Finished Jul 14 04:29:47 PM PDT 24
Peak memory 182840 kb
Host smart-a8ac6018-84bc-4e29-8d16-6c6aaff8bf5e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835843490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1835843490
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.217518621
Short name T370
Test name
Test status
Simulation time 5378639541 ps
CPU time 7.93 seconds
Started Jul 14 04:23:03 PM PDT 24
Finished Jul 14 04:23:13 PM PDT 24
Peak memory 181948 kb
Host smart-776c892e-6f82-4c7b-b009-26bbfaa80728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217518621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.217518621
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1374991292
Short name T369
Test name
Test status
Simulation time 68145247816 ps
CPU time 115.83 seconds
Started Jul 14 04:23:05 PM PDT 24
Finished Jul 14 04:25:03 PM PDT 24
Peak memory 180996 kb
Host smart-6e5c2331-093d-4c47-af2e-54b61270fd61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374991292 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1374991292
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2462702557
Short name T390
Test name
Test status
Simulation time 24839454759 ps
CPU time 37.7 seconds
Started Jul 14 04:23:17 PM PDT 24
Finished Jul 14 04:23:56 PM PDT 24
Peak memory 182620 kb
Host smart-35e7e21f-9f00-4a2c-9628-31a2d080d9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462702557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2462702557
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2619298484
Short name T151
Test name
Test status
Simulation time 428439864573 ps
CPU time 1499.71 seconds
Started Jul 14 04:23:03 PM PDT 24
Finished Jul 14 04:48:05 PM PDT 24
Peak memory 188912 kb
Host smart-44ad8b31-d7f4-4548-882c-64b1e31041a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619298484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2619298484
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.1270953124
Short name T139
Test name
Test status
Simulation time 103659679774 ps
CPU time 81.77 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:23:23 PM PDT 24
Peak memory 182628 kb
Host smart-8b9cdacc-97aa-4c8c-b892-24b365f32695
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270953124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.1270953124
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.3961937474
Short name T352
Test name
Test status
Simulation time 23839220279 ps
CPU time 32.87 seconds
Started Jul 14 04:22:24 PM PDT 24
Finished Jul 14 04:22:58 PM PDT 24
Peak memory 181464 kb
Host smart-51c2fbc8-5a09-4d33-aac0-2120b761645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961937474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.3961937474
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random.3981877669
Short name T231
Test name
Test status
Simulation time 192124782553 ps
CPU time 293.43 seconds
Started Jul 14 04:22:01 PM PDT 24
Finished Jul 14 04:26:56 PM PDT 24
Peak memory 190840 kb
Host smart-f39fbbd3-071b-4bfe-a21a-e2a5ef9e195a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981877669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3981877669
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3361620157
Short name T222
Test name
Test status
Simulation time 540184169320 ps
CPU time 137.77 seconds
Started Jul 14 04:18:07 PM PDT 24
Finished Jul 14 04:20:26 PM PDT 24
Peak memory 191072 kb
Host smart-f90f803d-c49a-45a8-9011-8b0808b698a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361620157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3361620157
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4225704807
Short name T332
Test name
Test status
Simulation time 744890977427 ps
CPU time 228.65 seconds
Started Jul 14 04:21:52 PM PDT 24
Finished Jul 14 04:25:41 PM PDT 24
Peak memory 182008 kb
Host smart-9fb631cc-f1e6-4f5a-8d88-325b67391868
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225704807 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4225704807
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2210696521
Short name T402
Test name
Test status
Simulation time 320279703576 ps
CPU time 125.5 seconds
Started Jul 14 04:22:43 PM PDT 24
Finished Jul 14 04:24:52 PM PDT 24
Peak memory 182684 kb
Host smart-45e5d0f6-54e0-403f-a18e-26ef1be188ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210696521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2210696521
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1511727960
Short name T274
Test name
Test status
Simulation time 279561674638 ps
CPU time 123.25 seconds
Started Jul 14 04:22:00 PM PDT 24
Finished Jul 14 04:24:05 PM PDT 24
Peak memory 182632 kb
Host smart-9069fc75-1530-42ad-9b14-43a193190283
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511727960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1511727960
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2573871951
Short name T337
Test name
Test status
Simulation time 119961725437 ps
CPU time 451.61 seconds
Started Jul 14 04:22:32 PM PDT 24
Finished Jul 14 04:30:06 PM PDT 24
Peak memory 182552 kb
Host smart-4f08191d-1927-4d7a-8418-44a9a83a7863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573871951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2573871951
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2496256592
Short name T24
Test name
Test status
Simulation time 1199333652024 ps
CPU time 595.9 seconds
Started Jul 14 04:17:52 PM PDT 24
Finished Jul 14 04:27:48 PM PDT 24
Peak memory 191256 kb
Host smart-607bbe19-9be1-4a92-b50d-9606f05f1ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496256592 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2496256592
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3243908645
Short name T315
Test name
Test status
Simulation time 474289235988 ps
CPU time 404.98 seconds
Started Jul 14 04:18:06 PM PDT 24
Finished Jul 14 04:24:52 PM PDT 24
Peak memory 182872 kb
Host smart-9397d0d3-e5d0-430d-9837-34aba40eb9c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243908645 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3243908645
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2644567471
Short name T351
Test name
Test status
Simulation time 255474159395 ps
CPU time 108.83 seconds
Started Jul 14 04:23:19 PM PDT 24
Finished Jul 14 04:25:09 PM PDT 24
Peak memory 182780 kb
Host smart-0b17e096-b65c-4277-a4f2-fd7cc12e52a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644567471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2644567471
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2935546357
Short name T191
Test name
Test status
Simulation time 39798225020 ps
CPU time 64.82 seconds
Started Jul 14 04:17:45 PM PDT 24
Finished Jul 14 04:18:50 PM PDT 24
Peak memory 191112 kb
Host smart-ed03127a-692c-470f-b6af-e257da18ae27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935546357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2935546357
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.968677872
Short name T384
Test name
Test status
Simulation time 107182922871 ps
CPU time 153.74 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:24:30 PM PDT 24
Peak memory 182620 kb
Host smart-25e2f730-7e5f-42f6-bccb-864062c1a782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968677872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.968677872
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.3080754794
Short name T261
Test name
Test status
Simulation time 48866491448 ps
CPU time 382.53 seconds
Started Jul 14 04:17:38 PM PDT 24
Finished Jul 14 04:24:01 PM PDT 24
Peak memory 191516 kb
Host smart-f0ff9766-e4d8-4551-aa73-2e92f4ac69a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080754794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.3080754794
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1719236207
Short name T334
Test name
Test status
Simulation time 70873982922 ps
CPU time 426.24 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:29:15 PM PDT 24
Peak memory 191164 kb
Host smart-d39067d8-461b-4cbc-81e1-dd1b79252e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719236207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1719236207
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3387876514
Short name T373
Test name
Test status
Simulation time 84607543871 ps
CPU time 102.49 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 182620 kb
Host smart-544b1de5-359f-4f97-bc58-ab24eb7a3ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387876514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3387876514
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2898148371
Short name T60
Test name
Test status
Simulation time 4721770702 ps
CPU time 9.08 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:22:05 PM PDT 24
Peak memory 182224 kb
Host smart-5c5f4f88-03be-4b5a-a4d3-6941f0715a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898148371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2898148371
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.430474412
Short name T7
Test name
Test status
Simulation time 128833589307 ps
CPU time 197.6 seconds
Started Jul 14 04:17:59 PM PDT 24
Finished Jul 14 04:21:17 PM PDT 24
Peak memory 182924 kb
Host smart-7bd6f3b4-3afd-4e02-96bf-9c2f9ca1fdb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430474412 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
430474412
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.3518900876
Short name T395
Test name
Test status
Simulation time 3984745040 ps
CPU time 6.83 seconds
Started Jul 14 04:18:05 PM PDT 24
Finished Jul 14 04:18:12 PM PDT 24
Peak memory 182916 kb
Host smart-3ae6fe82-50cc-4c67-b893-595731a72311
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518900876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.3518900876
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.1978045570
Short name T423
Test name
Test status
Simulation time 175391588035 ps
CPU time 71.35 seconds
Started Jul 14 04:18:02 PM PDT 24
Finished Jul 14 04:19:13 PM PDT 24
Peak memory 182916 kb
Host smart-fe42294b-2a7e-42ba-a890-6bcf7e2e945b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978045570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.1978045570
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.1986556956
Short name T341
Test name
Test status
Simulation time 13131703462 ps
CPU time 18.3 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:22:26 PM PDT 24
Peak memory 182952 kb
Host smart-7c328091-a4ba-483b-8d61-410e50b6c8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986556956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.1986556956
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2929057878
Short name T408
Test name
Test status
Simulation time 72586943 ps
CPU time 0.6 seconds
Started Jul 14 04:22:09 PM PDT 24
Finished Jul 14 04:22:11 PM PDT 24
Peak memory 182768 kb
Host smart-171190c8-3414-4813-adf9-ab4351e3cb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929057878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2929057878
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.2362393782
Short name T206
Test name
Test status
Simulation time 867350593320 ps
CPU time 755.6 seconds
Started Jul 14 04:17:59 PM PDT 24
Finished Jul 14 04:30:35 PM PDT 24
Peak memory 182920 kb
Host smart-67e0e284-0843-4395-ad74-e5e6cb5f6989
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362393782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.2362393782
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2118572250
Short name T397
Test name
Test status
Simulation time 465535273777 ps
CPU time 202.05 seconds
Started Jul 14 04:23:14 PM PDT 24
Finished Jul 14 04:26:38 PM PDT 24
Peak memory 182924 kb
Host smart-cf787b52-cbda-4b90-bd2c-62e57925eb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118572250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2118572250
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2760662258
Short name T45
Test name
Test status
Simulation time 560590111435 ps
CPU time 1533.97 seconds
Started Jul 14 04:17:58 PM PDT 24
Finished Jul 14 04:43:33 PM PDT 24
Peak memory 191128 kb
Host smart-507e016c-84e2-4ea2-88eb-adf62c6d62e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760662258 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2760662258
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.1008411442
Short name T392
Test name
Test status
Simulation time 2203696835 ps
CPU time 2.28 seconds
Started Jul 14 04:21:17 PM PDT 24
Finished Jul 14 04:21:20 PM PDT 24
Peak memory 182816 kb
Host smart-40596192-89ee-4802-9a1d-9fada169901b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008411442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.1008411442
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.3083855477
Short name T143
Test name
Test status
Simulation time 1692991392156 ps
CPU time 1422.36 seconds
Started Jul 14 04:22:22 PM PDT 24
Finished Jul 14 04:46:05 PM PDT 24
Peak memory 191064 kb
Host smart-95d47edb-9fa5-4b99-89ab-48f5bf4c5402
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083855477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.3083855477
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.2886172240
Short name T35
Test name
Test status
Simulation time 54608703914 ps
CPU time 201.76 seconds
Started Jul 14 04:23:04 PM PDT 24
Finished Jul 14 04:26:29 PM PDT 24
Peak memory 203880 kb
Host smart-e02d6c1c-e0ba-4b29-a720-7a0e2a6bb739
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886172240 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.2886172240
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.3294091485
Short name T445
Test name
Test status
Simulation time 1161529469337 ps
CPU time 572.68 seconds
Started Jul 14 04:19:22 PM PDT 24
Finished Jul 14 04:28:56 PM PDT 24
Peak memory 183308 kb
Host smart-b6be48b2-89ee-4755-a560-dc2c30811984
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294091485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.3294091485
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.1252941049
Short name T389
Test name
Test status
Simulation time 330486133061 ps
CPU time 120.79 seconds
Started Jul 14 04:17:59 PM PDT 24
Finished Jul 14 04:20:00 PM PDT 24
Peak memory 182924 kb
Host smart-29ed500d-dae2-4eec-a913-63f5a742500c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252941049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.1252941049
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.1485231908
Short name T396
Test name
Test status
Simulation time 27095385 ps
CPU time 0.53 seconds
Started Jul 14 04:23:05 PM PDT 24
Finished Jul 14 04:23:08 PM PDT 24
Peak memory 181328 kb
Host smart-73980d41-caad-47dd-9bc8-918f71e720a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485231908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.1485231908
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.124971984
Short name T33
Test name
Test status
Simulation time 78312686753 ps
CPU time 433.83 seconds
Started Jul 14 04:19:45 PM PDT 24
Finished Jul 14 04:26:59 PM PDT 24
Peak memory 194392 kb
Host smart-d585f501-c31f-4ee4-997e-d11f562344e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124971984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
124971984
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.1556067257
Short name T318
Test name
Test status
Simulation time 567080911232 ps
CPU time 584.79 seconds
Started Jul 14 04:17:59 PM PDT 24
Finished Jul 14 04:27:44 PM PDT 24
Peak memory 191128 kb
Host smart-1935ce26-8561-4bef-8e68-445dfd92fff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556067257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1556067257
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.955970407
Short name T343
Test name
Test status
Simulation time 172182655046 ps
CPU time 191.93 seconds
Started Jul 14 04:17:55 PM PDT 24
Finished Jul 14 04:21:08 PM PDT 24
Peak memory 191252 kb
Host smart-a52ac502-9f67-4202-80a1-887f567255ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955970407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.955970407
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.2071002130
Short name T138
Test name
Test status
Simulation time 667917969880 ps
CPU time 380.48 seconds
Started Jul 14 04:18:27 PM PDT 24
Finished Jul 14 04:24:48 PM PDT 24
Peak memory 182860 kb
Host smart-68dde85e-0082-4ba5-8cf4-e15d9b133b0f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071002130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.2071002130
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.3133564566
Short name T88
Test name
Test status
Simulation time 393504933768 ps
CPU time 299.66 seconds
Started Jul 14 04:22:09 PM PDT 24
Finished Jul 14 04:27:10 PM PDT 24
Peak memory 182616 kb
Host smart-ae419fc5-0949-46af-907c-3a7b47b351dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133564566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.3133564566
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1007212387
Short name T345
Test name
Test status
Simulation time 79349368757 ps
CPU time 267.26 seconds
Started Jul 14 04:22:25 PM PDT 24
Finished Jul 14 04:26:53 PM PDT 24
Peak memory 191112 kb
Host smart-c10f01df-ffec-45b4-9d5b-f28faf41f9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007212387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1007212387
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.261514317
Short name T19
Test name
Test status
Simulation time 88624959 ps
CPU time 0.79 seconds
Started Jul 14 04:18:26 PM PDT 24
Finished Jul 14 04:18:27 PM PDT 24
Peak memory 213328 kb
Host smart-78022f34-36ca-43be-a259-9fdb94a709fc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261514317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.261514317
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1783346847
Short name T128
Test name
Test status
Simulation time 932947166567 ps
CPU time 686.5 seconds
Started Jul 14 04:17:55 PM PDT 24
Finished Jul 14 04:29:22 PM PDT 24
Peak memory 191196 kb
Host smart-c0b0fa4c-913b-4688-b242-c470c2212542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783346847 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1783346847
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.2626606330
Short name T39
Test name
Test status
Simulation time 32314431486 ps
CPU time 92.32 seconds
Started Jul 14 04:19:31 PM PDT 24
Finished Jul 14 04:21:04 PM PDT 24
Peak memory 197612 kb
Host smart-8654ee17-fefa-4765-8b28-142696e93385
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626606330 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.2626606330
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.756848609
Short name T262
Test name
Test status
Simulation time 277849872181 ps
CPU time 490.27 seconds
Started Jul 14 04:19:56 PM PDT 24
Finished Jul 14 04:28:06 PM PDT 24
Peak memory 182904 kb
Host smart-91e0b373-c914-4544-8a5b-d3f4c0782d3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756848609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.rv_timer_cfg_update_on_fly.756848609
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3858761669
Short name T393
Test name
Test status
Simulation time 51207262519 ps
CPU time 39.32 seconds
Started Jul 14 04:19:57 PM PDT 24
Finished Jul 14 04:20:36 PM PDT 24
Peak memory 182876 kb
Host smart-33746f7b-1581-402f-9627-aa2021de38cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858761669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3858761669
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.1177346363
Short name T405
Test name
Test status
Simulation time 101731448 ps
CPU time 0.7 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:22:34 PM PDT 24
Peak memory 182172 kb
Host smart-8bf59cb0-f22f-4181-b26d-87cc6623881e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177346363 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.1177346363
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3023059741
Short name T130
Test name
Test status
Simulation time 284154459435 ps
CPU time 535.34 seconds
Started Jul 14 04:22:20 PM PDT 24
Finished Jul 14 04:31:16 PM PDT 24
Peak memory 190928 kb
Host smart-e057e5a9-199b-4e7a-a3c9-443399223e18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023059741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3023059741
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3713102661
Short name T247
Test name
Test status
Simulation time 855527466586 ps
CPU time 795.18 seconds
Started Jul 14 04:22:23 PM PDT 24
Finished Jul 14 04:35:39 PM PDT 24
Peak memory 182856 kb
Host smart-3980452e-9581-490e-b134-9c14b09d4200
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713102661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3713102661
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.929195334
Short name T371
Test name
Test status
Simulation time 516856524263 ps
CPU time 145.6 seconds
Started Jul 14 04:19:43 PM PDT 24
Finished Jul 14 04:22:10 PM PDT 24
Peak memory 181200 kb
Host smart-48b689e2-9ad8-42ac-9825-f84bc1b793a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929195334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.929195334
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3738248565
Short name T385
Test name
Test status
Simulation time 28811923467 ps
CPU time 23.1 seconds
Started Jul 14 04:22:08 PM PDT 24
Finished Jul 14 04:22:32 PM PDT 24
Peak memory 182824 kb
Host smart-6e97de70-55d2-4d48-b623-403c9955301e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738248565 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3738248565
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3646543378
Short name T304
Test name
Test status
Simulation time 48056654737 ps
CPU time 76.64 seconds
Started Jul 14 04:17:57 PM PDT 24
Finished Jul 14 04:19:14 PM PDT 24
Peak memory 191252 kb
Host smart-25094427-da4b-41e9-9e56-c6fb38dc3486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646543378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3646543378
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.3727611778
Short name T34
Test name
Test status
Simulation time 35270894465 ps
CPU time 144.36 seconds
Started Jul 14 04:19:54 PM PDT 24
Finished Jul 14 04:22:19 PM PDT 24
Peak memory 205812 kb
Host smart-7079b435-9039-438a-a0b8-8b2a97425b18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727611778 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.3727611778
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1473164103
Short name T218
Test name
Test status
Simulation time 1310151722967 ps
CPU time 684.79 seconds
Started Jul 14 04:21:57 PM PDT 24
Finished Jul 14 04:33:24 PM PDT 24
Peak memory 182620 kb
Host smart-36c49320-308a-406d-8d81-8ebeb47c73f0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473164103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1473164103
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2882813407
Short name T413
Test name
Test status
Simulation time 351390045224 ps
CPU time 128.26 seconds
Started Jul 14 04:21:56 PM PDT 24
Finished Jul 14 04:24:07 PM PDT 24
Peak memory 181936 kb
Host smart-d714a9a3-08dd-43ed-9ef1-2d0da0b6d732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882813407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2882813407
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.29683795
Short name T166
Test name
Test status
Simulation time 92336048853 ps
CPU time 41.96 seconds
Started Jul 14 04:21:58 PM PDT 24
Finished Jul 14 04:22:42 PM PDT 24
Peak memory 190856 kb
Host smart-d838c9ec-63e3-4065-9a1e-d55fe7fd949a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29683795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.29683795
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3054198018
Short name T412
Test name
Test status
Simulation time 118516938818 ps
CPU time 171.21 seconds
Started Jul 14 04:22:22 PM PDT 24
Finished Jul 14 04:25:14 PM PDT 24
Peak memory 182856 kb
Host smart-be509c93-f929-41d5-a442-807b9e12798f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054198018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3054198018
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.1356891326
Short name T386
Test name
Test status
Simulation time 61689410754 ps
CPU time 89.07 seconds
Started Jul 14 04:23:34 PM PDT 24
Finished Jul 14 04:25:06 PM PDT 24
Peak memory 182784 kb
Host smart-d21f96c3-a620-4c79-b4da-7de784bf603d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356891326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.1356891326
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.3687069932
Short name T134
Test name
Test status
Simulation time 536452021005 ps
CPU time 390.82 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:29:14 PM PDT 24
Peak memory 191112 kb
Host smart-f45b53a2-a0ec-46d7-ad2d-ab1991b6e828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687069932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.3687069932
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.3341261943
Short name T217
Test name
Test status
Simulation time 467760091130 ps
CPU time 293.09 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:26:47 PM PDT 24
Peak memory 189668 kb
Host smart-221fd087-c221-449e-98f6-7280bfcdfc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341261943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.3341261943
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3238114790
Short name T285
Test name
Test status
Simulation time 85932798525 ps
CPU time 130.29 seconds
Started Jul 14 04:18:09 PM PDT 24
Finished Jul 14 04:20:20 PM PDT 24
Peak memory 191068 kb
Host smart-b15749fd-c224-439d-add7-b64a4ad4b667
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238114790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3238114790
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1871205825
Short name T37
Test name
Test status
Simulation time 78563256149 ps
CPU time 747.79 seconds
Started Jul 14 04:18:08 PM PDT 24
Finished Jul 14 04:30:36 PM PDT 24
Peak memory 200428 kb
Host smart-60c23884-a42d-43fc-a19b-a5a503add007
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871205825 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1871205825
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.3468329456
Short name T227
Test name
Test status
Simulation time 434232289685 ps
CPU time 229.72 seconds
Started Jul 14 04:18:20 PM PDT 24
Finished Jul 14 04:22:10 PM PDT 24
Peak memory 182880 kb
Host smart-bd9424cf-dccf-4940-b2b5-d02fcf871ea5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468329456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.3468329456
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.885647373
Short name T356
Test name
Test status
Simulation time 160388662449 ps
CPU time 171.98 seconds
Started Jul 14 04:18:16 PM PDT 24
Finished Jul 14 04:21:09 PM PDT 24
Peak memory 182884 kb
Host smart-cb5e87a0-b0f3-4bcd-aa80-222e2f37a3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885647373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.885647373
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.1493927798
Short name T378
Test name
Test status
Simulation time 129585260 ps
CPU time 0.6 seconds
Started Jul 14 04:19:32 PM PDT 24
Finished Jul 14 04:19:33 PM PDT 24
Peak memory 182760 kb
Host smart-d7954c60-b79b-473e-bfca-c8a1de9ff0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493927798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.1493927798
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.2068007586
Short name T56
Test name
Test status
Simulation time 477731218824 ps
CPU time 515.14 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:30:30 PM PDT 24
Peak memory 194480 kb
Host smart-254c1b6c-9851-4a6a-a9d6-c4cfc2aa1fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068007586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.2068007586
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.3800843426
Short name T414
Test name
Test status
Simulation time 59018634430 ps
CPU time 23.49 seconds
Started Jul 14 04:18:24 PM PDT 24
Finished Jul 14 04:18:48 PM PDT 24
Peak memory 183320 kb
Host smart-8d25339f-b021-4588-b67c-4500be8ee53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800843426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.3800843426
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.1184333933
Short name T428
Test name
Test status
Simulation time 245080768191 ps
CPU time 269.7 seconds
Started Jul 14 04:18:30 PM PDT 24
Finished Jul 14 04:23:00 PM PDT 24
Peak memory 191092 kb
Host smart-4462c869-3e75-48f1-b524-9faf300c95cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184333933 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.1184333933
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.4182263463
Short name T268
Test name
Test status
Simulation time 171544740494 ps
CPU time 76.86 seconds
Started Jul 14 04:19:28 PM PDT 24
Finished Jul 14 04:20:45 PM PDT 24
Peak memory 182948 kb
Host smart-857f168a-7c67-43d6-9e07-30d3ae460f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182263463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.4182263463
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.236893575
Short name T444
Test name
Test status
Simulation time 359654502285 ps
CPU time 276.48 seconds
Started Jul 14 04:18:32 PM PDT 24
Finished Jul 14 04:23:09 PM PDT 24
Peak memory 183044 kb
Host smart-cfaf9032-eaa3-4ca5-922f-fae6360abee4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236893575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
236893575
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.2341308394
Short name T416
Test name
Test status
Simulation time 26063208221 ps
CPU time 25.59 seconds
Started Jul 14 04:22:02 PM PDT 24
Finished Jul 14 04:22:29 PM PDT 24
Peak memory 182896 kb
Host smart-cf14e9ee-f4fd-4798-831f-c2396552cebd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341308394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.2341308394
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3799656610
Short name T410
Test name
Test status
Simulation time 116022367493 ps
CPU time 152.53 seconds
Started Jul 14 04:21:49 PM PDT 24
Finished Jul 14 04:24:22 PM PDT 24
Peak memory 181796 kb
Host smart-b7162a74-a350-4c6a-a152-90aa676726b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799656610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3799656610
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.1801006507
Short name T234
Test name
Test status
Simulation time 125028820827 ps
CPU time 292.27 seconds
Started Jul 14 04:22:21 PM PDT 24
Finished Jul 14 04:27:14 PM PDT 24
Peak memory 190980 kb
Host smart-baa145ee-e8f5-4541-b70e-2257e2939956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801006507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.1801006507
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3158858921
Short name T432
Test name
Test status
Simulation time 87877588987 ps
CPU time 43.74 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:22:53 PM PDT 24
Peak memory 193496 kb
Host smart-0ee1523e-fed4-4528-9847-8d191a7672a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158858921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3158858921
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.343476304
Short name T404
Test name
Test status
Simulation time 184970658696 ps
CPU time 462.25 seconds
Started Jul 14 04:21:47 PM PDT 24
Finished Jul 14 04:29:31 PM PDT 24
Peak memory 189812 kb
Host smart-08511252-9962-42e9-9587-973f74dc4316
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343476304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all.
343476304
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.423944689
Short name T214
Test name
Test status
Simulation time 3297965091 ps
CPU time 2.34 seconds
Started Jul 14 04:20:03 PM PDT 24
Finished Jul 14 04:20:06 PM PDT 24
Peak memory 182948 kb
Host smart-03ad75bf-d4c4-48fb-a1d1-e4982966dbff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423944689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.423944689
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.1623854465
Short name T375
Test name
Test status
Simulation time 301041122838 ps
CPU time 50.48 seconds
Started Jul 14 04:18:41 PM PDT 24
Finished Jul 14 04:19:32 PM PDT 24
Peak memory 183060 kb
Host smart-285d7b42-1842-4c74-bf0a-ee2860c53b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623854465 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.1623854465
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.2535093771
Short name T146
Test name
Test status
Simulation time 34942832241 ps
CPU time 52.31 seconds
Started Jul 14 04:18:36 PM PDT 24
Finished Jul 14 04:19:29 PM PDT 24
Peak memory 191252 kb
Host smart-c2ada9ad-0838-4125-b453-d8f39558566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535093771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.2535093771
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1958455163
Short name T440
Test name
Test status
Simulation time 1883802729 ps
CPU time 2.67 seconds
Started Jul 14 04:22:24 PM PDT 24
Finished Jul 14 04:22:27 PM PDT 24
Peak memory 182744 kb
Host smart-659271ac-d840-4726-ae77-725a84f653ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958455163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1958455163
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.1852698958
Short name T399
Test name
Test status
Simulation time 555700100538 ps
CPU time 213.01 seconds
Started Jul 14 04:22:45 PM PDT 24
Finished Jul 14 04:26:21 PM PDT 24
Peak memory 181532 kb
Host smart-c034c5c1-471f-4daf-a1f7-a31ef62c3349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852698958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.1852698958
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.3604536677
Short name T168
Test name
Test status
Simulation time 67321339929 ps
CPU time 51.28 seconds
Started Jul 14 04:22:09 PM PDT 24
Finished Jul 14 04:23:02 PM PDT 24
Peak memory 190388 kb
Host smart-cfa920eb-d437-40c9-8737-8dd53b2f1db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604536677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.3604536677
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1754381085
Short name T398
Test name
Test status
Simulation time 567843809576 ps
CPU time 210.22 seconds
Started Jul 14 04:23:00 PM PDT 24
Finished Jul 14 04:26:31 PM PDT 24
Peak memory 182844 kb
Host smart-83c6bd3f-8945-49d9-aafb-780504fdf6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754381085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1754381085
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.824482501
Short name T308
Test name
Test status
Simulation time 889226605842 ps
CPU time 383.61 seconds
Started Jul 14 04:23:13 PM PDT 24
Finished Jul 14 04:29:38 PM PDT 24
Peak memory 190832 kb
Host smart-5103f5d8-a735-49ca-8f4e-e243e31017f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824482501 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.824482501
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.223361329
Short name T446
Test name
Test status
Simulation time 1927768373 ps
CPU time 1.14 seconds
Started Jul 14 04:23:04 PM PDT 24
Finished Jul 14 04:23:07 PM PDT 24
Peak memory 182140 kb
Host smart-27433beb-6f81-4798-bdb3-860ca3235266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223361329 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.223361329
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.150118308
Short name T36
Test name
Test status
Simulation time 61615831713 ps
CPU time 444.04 seconds
Started Jul 14 04:23:05 PM PDT 24
Finished Jul 14 04:30:31 PM PDT 24
Peak memory 205292 kb
Host smart-18b51737-3acf-4c6c-a529-ca1aabe49f72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150118308 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.150118308
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.2719725618
Short name T312
Test name
Test status
Simulation time 296794376008 ps
CPU time 529.83 seconds
Started Jul 14 04:21:56 PM PDT 24
Finished Jul 14 04:30:48 PM PDT 24
Peak memory 182624 kb
Host smart-3f316b6c-6309-4ca5-897a-d4986c571707
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719725618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.2719725618
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.2890586787
Short name T350
Test name
Test status
Simulation time 237505478247 ps
CPU time 172.66 seconds
Started Jul 14 04:23:02 PM PDT 24
Finished Jul 14 04:25:56 PM PDT 24
Peak memory 182640 kb
Host smart-f97f6228-aee0-484c-a216-4343d15b477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890586787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.2890586787
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.694726270
Short name T249
Test name
Test status
Simulation time 739191897709 ps
CPU time 798.92 seconds
Started Jul 14 04:18:05 PM PDT 24
Finished Jul 14 04:31:24 PM PDT 24
Peak memory 191124 kb
Host smart-678ce391-d823-41d1-a306-0a9d21860183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694726270 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.694726270
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1944592698
Short name T17
Test name
Test status
Simulation time 87588477 ps
CPU time 0.94 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:21:57 PM PDT 24
Peak memory 213588 kb
Host smart-0fa215c9-67e8-4d17-9fc9-1f0b72e14072
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944592698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1944592698
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.3612312245
Short name T325
Test name
Test status
Simulation time 711373559570 ps
CPU time 852.75 seconds
Started Jul 14 04:23:19 PM PDT 24
Finished Jul 14 04:37:34 PM PDT 24
Peak memory 182896 kb
Host smart-20806b9b-4b1d-43e1-b59a-cc52f5b78f72
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612312245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.3612312245
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1324037203
Short name T388
Test name
Test status
Simulation time 123148664771 ps
CPU time 178.23 seconds
Started Jul 14 04:19:07 PM PDT 24
Finished Jul 14 04:22:06 PM PDT 24
Peak memory 182900 kb
Host smart-6c598413-2629-4cc7-901d-309d6c2051c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324037203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1324037203
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.4286540019
Short name T275
Test name
Test status
Simulation time 149622218065 ps
CPU time 199.41 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:25:20 PM PDT 24
Peak memory 191136 kb
Host smart-bb2b5439-8974-4caa-9e57-a680a9559dd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286540019 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.4286540019
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.1699101268
Short name T98
Test name
Test status
Simulation time 16158619701 ps
CPU time 26.39 seconds
Started Jul 14 04:23:05 PM PDT 24
Finished Jul 14 04:23:33 PM PDT 24
Peak memory 182608 kb
Host smart-e017459c-6278-46df-8832-0afeb0149682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699101268 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.1699101268
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2396063476
Short name T306
Test name
Test status
Simulation time 496096174325 ps
CPU time 2215.85 seconds
Started Jul 14 04:23:05 PM PDT 24
Finished Jul 14 05:00:03 PM PDT 24
Peak memory 190596 kb
Host smart-aa88b970-52b9-4d2b-a65b-3d7e416695b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396063476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2396063476
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all_with_rand_reset.1023715305
Short name T91
Test name
Test status
Simulation time 87039228288 ps
CPU time 906.94 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:37:04 PM PDT 24
Peak memory 209784 kb
Host smart-a71e950f-b908-4acf-ad6e-a3571cca87f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023715305 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all_with_rand_reset.1023715305
Directory /workspace/40.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.1437605108
Short name T288
Test name
Test status
Simulation time 143198954310 ps
CPU time 251.93 seconds
Started Jul 14 04:23:19 PM PDT 24
Finished Jul 14 04:27:32 PM PDT 24
Peak memory 182900 kb
Host smart-86666aeb-fe4a-4cd9-a1f2-7518f699f684
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437605108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.1437605108
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2153010812
Short name T353
Test name
Test status
Simulation time 552171172144 ps
CPU time 149 seconds
Started Jul 14 04:23:19 PM PDT 24
Finished Jul 14 04:25:50 PM PDT 24
Peak memory 182832 kb
Host smart-13e4d323-d936-4198-8b39-e3a2573c5e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153010812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2153010812
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2679898794
Short name T339
Test name
Test status
Simulation time 25720017158 ps
CPU time 41.16 seconds
Started Jul 14 04:21:58 PM PDT 24
Finished Jul 14 04:22:42 PM PDT 24
Peak memory 182856 kb
Host smart-74f02423-a0b6-4364-a3ba-b6ce740de191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679898794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2679898794
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.2037453136
Short name T200
Test name
Test status
Simulation time 268334203346 ps
CPU time 924.29 seconds
Started Jul 14 04:22:27 PM PDT 24
Finished Jul 14 04:37:53 PM PDT 24
Peak memory 190788 kb
Host smart-15e459db-2564-4c88-8a2d-cb7cc05d5cd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037453136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.2037453136
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all_with_rand_reset.1502823867
Short name T14
Test name
Test status
Simulation time 36943386611 ps
CPU time 377.48 seconds
Started Jul 14 04:21:18 PM PDT 24
Finished Jul 14 04:27:35 PM PDT 24
Peak memory 205856 kb
Host smart-2730bad9-58d5-4672-b208-2afa67f8e444
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502823867 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all_with_rand_reset.1502823867
Directory /workspace/41.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.753204256
Short name T418
Test name
Test status
Simulation time 73157140381 ps
CPU time 118.37 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:24:26 PM PDT 24
Peak memory 181956 kb
Host smart-3e90afad-cf7c-44eb-979f-8375c12c1615
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753204256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.rv_timer_cfg_update_on_fly.753204256
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3104623552
Short name T401
Test name
Test status
Simulation time 126045555257 ps
CPU time 156.88 seconds
Started Jul 14 04:19:10 PM PDT 24
Finished Jul 14 04:21:47 PM PDT 24
Peak memory 183060 kb
Host smart-32cb6273-924d-44eb-9b58-afe60c70692a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104623552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3104623552
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.2514989716
Short name T293
Test name
Test status
Simulation time 630005435971 ps
CPU time 830.42 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:36:19 PM PDT 24
Peak memory 190424 kb
Host smart-eea74910-02ca-43ca-afc6-01780e08dbac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514989716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.2514989716
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3879525970
Short name T310
Test name
Test status
Simulation time 9440814102 ps
CPU time 57.93 seconds
Started Jul 14 04:21:51 PM PDT 24
Finished Jul 14 04:22:50 PM PDT 24
Peak memory 181556 kb
Host smart-5fb1d6a3-32fd-44bb-8afe-1486a168927a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879525970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3879525970
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.4294537661
Short name T317
Test name
Test status
Simulation time 683367787619 ps
CPU time 289.83 seconds
Started Jul 14 04:19:14 PM PDT 24
Finished Jul 14 04:24:04 PM PDT 24
Peak memory 191116 kb
Host smart-3820c291-4a51-4c30-8b4d-dae22b1ff538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294537661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.4294537661
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.2644948034
Short name T421
Test name
Test status
Simulation time 16358474761 ps
CPU time 8.6 seconds
Started Jul 14 04:19:19 PM PDT 24
Finished Jul 14 04:19:28 PM PDT 24
Peak memory 182896 kb
Host smart-d0e6ad61-759a-436e-8d2f-ac4607dffd9a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644948034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.2644948034
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2858978247
Short name T364
Test name
Test status
Simulation time 206134506567 ps
CPU time 71.16 seconds
Started Jul 14 04:19:17 PM PDT 24
Finished Jul 14 04:20:29 PM PDT 24
Peak memory 183052 kb
Host smart-c0bb46af-8c23-4426-a7a5-1d38c11f0c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858978247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2858978247
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.2314233056
Short name T331
Test name
Test status
Simulation time 10877285146 ps
CPU time 17.67 seconds
Started Jul 14 04:19:14 PM PDT 24
Finished Jul 14 04:19:32 PM PDT 24
Peak memory 194768 kb
Host smart-413a32a2-3e62-45dd-aeed-166cd1867bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314233056 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.2314233056
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3662501802
Short name T124
Test name
Test status
Simulation time 81663253704 ps
CPU time 151.92 seconds
Started Jul 14 04:22:09 PM PDT 24
Finished Jul 14 04:24:42 PM PDT 24
Peak memory 182612 kb
Host smart-f55c1592-f4db-4c5c-a706-59aa5e710778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662501802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3662501802
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1123874479
Short name T236
Test name
Test status
Simulation time 3179454302169 ps
CPU time 1142.22 seconds
Started Jul 14 04:22:01 PM PDT 24
Finished Jul 14 04:41:05 PM PDT 24
Peak memory 182812 kb
Host smart-8c08b2b3-243f-43da-82fa-85e17c380e37
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123874479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1123874479
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.3079374143
Short name T42
Test name
Test status
Simulation time 149672998639 ps
CPU time 108.78 seconds
Started Jul 14 04:19:18 PM PDT 24
Finished Jul 14 04:21:07 PM PDT 24
Peak memory 182920 kb
Host smart-68a93eef-3302-4832-882b-91945f63a616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079374143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.3079374143
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.3827214781
Short name T443
Test name
Test status
Simulation time 45189613227 ps
CPU time 54.95 seconds
Started Jul 14 04:21:51 PM PDT 24
Finished Jul 14 04:22:47 PM PDT 24
Peak memory 190140 kb
Host smart-32740680-bf66-42a8-a9f0-b37359c54034
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827214781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.3827214781
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.4007092483
Short name T102
Test name
Test status
Simulation time 119644153683 ps
CPU time 578.04 seconds
Started Jul 14 04:21:58 PM PDT 24
Finished Jul 14 04:31:39 PM PDT 24
Peak memory 194128 kb
Host smart-58051b24-5780-4e17-b5b5-603e99f0457f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007092483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.4007092483
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.4170689455
Short name T195
Test name
Test status
Simulation time 815611866968 ps
CPU time 408.84 seconds
Started Jul 14 04:23:15 PM PDT 24
Finished Jul 14 04:30:05 PM PDT 24
Peak memory 195756 kb
Host smart-8b019458-1fa3-4016-a7e2-ca9127eaa185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170689455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.4170689455
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.719650917
Short name T92
Test name
Test status
Simulation time 160283098647 ps
CPU time 469.67 seconds
Started Jul 14 04:19:38 PM PDT 24
Finished Jul 14 04:27:28 PM PDT 24
Peak memory 205820 kb
Host smart-64e5446a-fada-4546-ab92-7e93bf906003
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719650917 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.719650917
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.3809187540
Short name T335
Test name
Test status
Simulation time 2068961132947 ps
CPU time 504.6 seconds
Started Jul 14 04:19:30 PM PDT 24
Finished Jul 14 04:27:55 PM PDT 24
Peak memory 182908 kb
Host smart-8652f633-78f0-4822-ab08-780b11e36e5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809187540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.3809187540
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.1004398209
Short name T359
Test name
Test status
Simulation time 94980984335 ps
CPU time 150.97 seconds
Started Jul 14 04:22:02 PM PDT 24
Finished Jul 14 04:24:34 PM PDT 24
Peak memory 182940 kb
Host smart-53ff56f0-7f1e-474c-b37e-81a2fb7f8f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004398209 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.1004398209
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1295136364
Short name T86
Test name
Test status
Simulation time 144226020214 ps
CPU time 337.51 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:27:39 PM PDT 24
Peak memory 190920 kb
Host smart-dc14ab4b-f85f-46b7-a68a-e2027fb0cc3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295136364 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1295136364
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.3699969724
Short name T433
Test name
Test status
Simulation time 37386666173 ps
CPU time 72.12 seconds
Started Jul 14 04:21:56 PM PDT 24
Finished Jul 14 04:23:10 PM PDT 24
Peak memory 182588 kb
Host smart-08bade0d-b912-42c2-a903-796d026844a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699969724 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.3699969724
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.2816075275
Short name T213
Test name
Test status
Simulation time 1174521696691 ps
CPU time 1087.18 seconds
Started Jul 14 04:19:36 PM PDT 24
Finished Jul 14 04:37:44 PM PDT 24
Peak memory 191092 kb
Host smart-7c198fa3-42fd-4a40-8d0d-46d80c49b068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816075275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.2816075275
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.2961751101
Short name T431
Test name
Test status
Simulation time 13276956925 ps
CPU time 12.83 seconds
Started Jul 14 04:20:05 PM PDT 24
Finished Jul 14 04:20:19 PM PDT 24
Peak memory 183040 kb
Host smart-5a37e51c-f3ea-4614-9517-2b3ae84f1590
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961751101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.2961751101
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.3707975605
Short name T358
Test name
Test status
Simulation time 375378083780 ps
CPU time 251.04 seconds
Started Jul 14 04:19:41 PM PDT 24
Finished Jul 14 04:23:52 PM PDT 24
Peak memory 182900 kb
Host smart-54700108-78a0-40f9-9611-59b92a9dfe5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707975605 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.3707975605
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.3174116436
Short name T319
Test name
Test status
Simulation time 53641353208 ps
CPU time 75.62 seconds
Started Jul 14 04:21:42 PM PDT 24
Finished Jul 14 04:22:59 PM PDT 24
Peak memory 182212 kb
Host smart-7ce50b80-93a2-4a40-8f62-6a43edbd7239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174116436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.3174116436
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.4147874128
Short name T368
Test name
Test status
Simulation time 19982472149 ps
CPU time 9.76 seconds
Started Jul 14 04:19:44 PM PDT 24
Finished Jul 14 04:19:55 PM PDT 24
Peak memory 191268 kb
Host smart-52b3586f-3246-4335-9076-a47bd6dd878f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147874128 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.4147874128
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.1833465633
Short name T366
Test name
Test status
Simulation time 98188946015 ps
CPU time 155.54 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:24:32 PM PDT 24
Peak memory 182668 kb
Host smart-5dad6d69-9ecd-469c-8a64-c5032804a8a1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833465633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.1833465633
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.438671207
Short name T377
Test name
Test status
Simulation time 140813628431 ps
CPU time 77.29 seconds
Started Jul 14 04:19:39 PM PDT 24
Finished Jul 14 04:20:57 PM PDT 24
Peak memory 183052 kb
Host smart-12cde5b9-04e9-41e8-8b3f-c4f93bfc5958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438671207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.438671207
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1558339146
Short name T147
Test name
Test status
Simulation time 765006150359 ps
CPU time 369.71 seconds
Started Jul 14 04:21:56 PM PDT 24
Finished Jul 14 04:28:07 PM PDT 24
Peak memory 190868 kb
Host smart-70016c80-fab8-41c7-b3ec-5a8ca03233a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558339146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1558339146
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3973045212
Short name T303
Test name
Test status
Simulation time 29316351941 ps
CPU time 55.69 seconds
Started Jul 14 04:19:46 PM PDT 24
Finished Jul 14 04:20:43 PM PDT 24
Peak memory 194904 kb
Host smart-fc19364a-1367-479c-8110-709c24b6883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973045212 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3973045212
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3226591546
Short name T330
Test name
Test status
Simulation time 266510897015 ps
CPU time 401.08 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:28:43 PM PDT 24
Peak memory 182400 kb
Host smart-17b10f49-4462-4988-80c4-0297aa723af5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226591546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3226591546
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2432450359
Short name T361
Test name
Test status
Simulation time 16938189340 ps
CPU time 24.46 seconds
Started Jul 14 04:19:58 PM PDT 24
Finished Jul 14 04:20:23 PM PDT 24
Peak memory 182880 kb
Host smart-6c9b84bf-c3aa-4758-a456-b9763fb14489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432450359 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2432450359
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2115213944
Short name T379
Test name
Test status
Simulation time 43221113 ps
CPU time 0.55 seconds
Started Jul 14 04:21:59 PM PDT 24
Finished Jul 14 04:22:02 PM PDT 24
Peak memory 182284 kb
Host smart-fe8b10b7-d727-40aa-95cb-00d205721441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115213944 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2115213944
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.1695480580
Short name T381
Test name
Test status
Simulation time 334732752044 ps
CPU time 125.16 seconds
Started Jul 14 04:21:46 PM PDT 24
Finished Jul 14 04:23:52 PM PDT 24
Peak memory 182212 kb
Host smart-ad8bdaf4-6d0f-429a-b546-ba13fdc012cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695480580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.1695480580
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.265913190
Short name T380
Test name
Test status
Simulation time 31968281023 ps
CPU time 14.88 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:23:50 PM PDT 24
Peak memory 182728 kb
Host smart-c856f279-1a85-4bac-b993-aaae0ddb0e3a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265913190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.rv_timer_cfg_update_on_fly.265913190
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.2280059469
Short name T411
Test name
Test status
Simulation time 300759426121 ps
CPU time 149.9 seconds
Started Jul 14 04:23:32 PM PDT 24
Finished Jul 14 04:26:05 PM PDT 24
Peak memory 182748 kb
Host smart-54e648aa-56df-4b8f-a9c2-aa1ba79148b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280059469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.2280059469
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2170436245
Short name T196
Test name
Test status
Simulation time 599772619522 ps
CPU time 1768.8 seconds
Started Jul 14 04:22:39 PM PDT 24
Finished Jul 14 04:52:09 PM PDT 24
Peak memory 190860 kb
Host smart-56991392-77e8-4808-a2fd-52de7da5f991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170436245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2170436245
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1573974860
Short name T179
Test name
Test status
Simulation time 32657480279 ps
CPU time 233.04 seconds
Started Jul 14 04:23:04 PM PDT 24
Finished Jul 14 04:26:58 PM PDT 24
Peak memory 194336 kb
Host smart-132aa634-9fd9-45e2-97dc-511cd22e9c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573974860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1573974860
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3483405229
Short name T407
Test name
Test status
Simulation time 332685825517 ps
CPU time 126.38 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:24:02 PM PDT 24
Peak memory 182116 kb
Host smart-f0ad00c4-fe59-4a87-ad73-94661ea07b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483405229 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3483405229
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.3752031416
Short name T104
Test name
Test status
Simulation time 182229129203 ps
CPU time 1346.5 seconds
Started Jul 14 04:22:54 PM PDT 24
Finished Jul 14 04:45:22 PM PDT 24
Peak memory 190356 kb
Host smart-8683b4af-c10d-4a26-9a79-a20e6995d39d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752031416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.3752031416
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2503844564
Short name T229
Test name
Test status
Simulation time 211284701429 ps
CPU time 307.1 seconds
Started Jul 14 04:22:07 PM PDT 24
Finished Jul 14 04:27:15 PM PDT 24
Peak memory 191128 kb
Host smart-aff23afd-fcb8-44f2-a8af-99bbe0a3b73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503844564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2503844564
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.824204115
Short name T107
Test name
Test status
Simulation time 1217429879861 ps
CPU time 780.1 seconds
Started Jul 14 04:20:19 PM PDT 24
Finished Jul 14 04:33:20 PM PDT 24
Peak memory 191252 kb
Host smart-d712bef1-8c9b-4ae8-8404-ba588c56c7c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824204115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.824204115
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3430758108
Short name T281
Test name
Test status
Simulation time 16174716373 ps
CPU time 44.3 seconds
Started Jul 14 04:22:04 PM PDT 24
Finished Jul 14 04:22:49 PM PDT 24
Peak memory 182956 kb
Host smart-798367f2-8d24-4b1a-a6ed-e6d82b075fdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430758108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3430758108
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/52.rv_timer_random.849306191
Short name T165
Test name
Test status
Simulation time 1454242634785 ps
CPU time 530.71 seconds
Started Jul 14 04:23:18 PM PDT 24
Finished Jul 14 04:32:10 PM PDT 24
Peak memory 191088 kb
Host smart-dbbef471-abf2-4a86-ae26-ea5a14907b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849306191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.849306191
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3733768409
Short name T153
Test name
Test status
Simulation time 179044490836 ps
CPU time 302.18 seconds
Started Jul 14 04:22:27 PM PDT 24
Finished Jul 14 04:27:31 PM PDT 24
Peak memory 190808 kb
Host smart-54ab791c-c786-4469-92e0-07ca2512278e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733768409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3733768409
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.1361982097
Short name T224
Test name
Test status
Simulation time 859262360405 ps
CPU time 598.36 seconds
Started Jul 14 04:20:19 PM PDT 24
Finished Jul 14 04:30:18 PM PDT 24
Peak memory 191260 kb
Host smart-88f4fc35-c7d0-4307-8cee-12d28472e363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361982097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.1361982097
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3127191032
Short name T342
Test name
Test status
Simulation time 1171197109 ps
CPU time 2.37 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:21:58 PM PDT 24
Peak memory 182608 kb
Host smart-56fc3a49-75c1-430d-ad12-715c5136f804
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127191032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3127191032
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.1042049924
Short name T193
Test name
Test status
Simulation time 69889781342 ps
CPU time 77.04 seconds
Started Jul 14 04:21:56 PM PDT 24
Finished Jul 14 04:23:15 PM PDT 24
Peak memory 182896 kb
Host smart-54ff4117-2a0e-4631-99b6-a015645c9a2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042049924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.1042049924
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1798167272
Short name T150
Test name
Test status
Simulation time 2035237748390 ps
CPU time 397.72 seconds
Started Jul 14 04:21:56 PM PDT 24
Finished Jul 14 04:28:35 PM PDT 24
Peak memory 191096 kb
Host smart-79ae9b01-cea4-4ba9-8ae7-92cfb582ccc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798167272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1798167272
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.424255905
Short name T252
Test name
Test status
Simulation time 286048697160 ps
CPU time 261.11 seconds
Started Jul 14 04:20:24 PM PDT 24
Finished Jul 14 04:24:45 PM PDT 24
Peak memory 191124 kb
Host smart-62ae5932-35e6-46b1-8791-1986f126a136
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424255905 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.424255905
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1234790874
Short name T279
Test name
Test status
Simulation time 1663597310616 ps
CPU time 412.02 seconds
Started Jul 14 04:21:58 PM PDT 24
Finished Jul 14 04:28:52 PM PDT 24
Peak memory 182908 kb
Host smart-140d689e-e228-43d3-8216-cc11edf4bcd1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234790874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1234790874
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2423438392
Short name T430
Test name
Test status
Simulation time 53488146151 ps
CPU time 67.34 seconds
Started Jul 14 04:21:45 PM PDT 24
Finished Jul 14 04:22:54 PM PDT 24
Peak memory 182688 kb
Host smart-006e8a1a-6a81-47eb-8b2e-7494c0ee5edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423438392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2423438392
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.279705690
Short name T340
Test name
Test status
Simulation time 160787592617 ps
CPU time 113.04 seconds
Started Jul 14 04:21:54 PM PDT 24
Finished Jul 14 04:23:50 PM PDT 24
Peak memory 190824 kb
Host smart-503b12c8-e1b5-485a-bddc-7dae7293e9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279705690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.279705690
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.4264095735
Short name T103
Test name
Test status
Simulation time 513388573709 ps
CPU time 1546.63 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:47:41 PM PDT 24
Peak memory 190872 kb
Host smart-05dbbe76-87fb-447e-8084-ec5dd18c5f1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264095735 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.4264095735
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3207499626
Short name T176
Test name
Test status
Simulation time 235363639729 ps
CPU time 259.83 seconds
Started Jul 14 04:21:53 PM PDT 24
Finished Jul 14 04:26:15 PM PDT 24
Peak memory 190872 kb
Host smart-5136c18a-9cf2-4dbc-ae4c-fe5d302c8ab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207499626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3207499626
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.156618301
Short name T4
Test name
Test status
Simulation time 80391666324 ps
CPU time 453.28 seconds
Started Jul 14 04:22:33 PM PDT 24
Finished Jul 14 04:30:08 PM PDT 24
Peak memory 182596 kb
Host smart-26f5a3e8-c426-4729-8aa8-2f4f85bddc16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156618301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.156618301
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.735379935
Short name T307
Test name
Test status
Simulation time 170601442995 ps
CPU time 189.47 seconds
Started Jul 14 04:22:41 PM PDT 24
Finished Jul 14 04:25:53 PM PDT 24
Peak memory 190848 kb
Host smart-dd2b2941-c0ee-4488-a780-3d95185f1e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735379935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.735379935
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.2254080681
Short name T324
Test name
Test status
Simulation time 96929923992 ps
CPU time 750.05 seconds
Started Jul 14 04:22:39 PM PDT 24
Finished Jul 14 04:35:10 PM PDT 24
Peak memory 182580 kb
Host smart-8a4d0b2d-9901-4d7f-a171-2577b3c5cd40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254080681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.2254080681
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1897519049
Short name T198
Test name
Test status
Simulation time 543658971319 ps
CPU time 1221.84 seconds
Started Jul 14 04:20:44 PM PDT 24
Finished Jul 14 04:41:06 PM PDT 24
Peak memory 191288 kb
Host smart-9d03a2ca-5c58-461b-ad70-b0f86f9db26b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897519049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1897519049
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.197245083
Short name T135
Test name
Test status
Simulation time 86177362510 ps
CPU time 43.14 seconds
Started Jul 14 04:22:39 PM PDT 24
Finished Jul 14 04:23:23 PM PDT 24
Peak memory 182612 kb
Host smart-dd787088-1553-476e-9958-4c602b5fe0ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197245083 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.197245083
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.2451791953
Short name T87
Test name
Test status
Simulation time 168669269419 ps
CPU time 103.07 seconds
Started Jul 14 04:22:25 PM PDT 24
Finished Jul 14 04:24:09 PM PDT 24
Peak memory 182668 kb
Host smart-d78e6475-9542-494b-a41e-4678e23020b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451791953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.2451791953
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1659107211
Short name T344
Test name
Test status
Simulation time 63203689010 ps
CPU time 30.98 seconds
Started Jul 14 04:18:52 PM PDT 24
Finished Jul 14 04:19:24 PM PDT 24
Peak memory 182872 kb
Host smart-daa5a62a-4fb3-4225-a039-8f5e7d05f2ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659107211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1659107211
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3623164624
Short name T365
Test name
Test status
Simulation time 53037596670 ps
CPU time 78.34 seconds
Started Jul 14 04:18:38 PM PDT 24
Finished Jul 14 04:19:57 PM PDT 24
Peak memory 182912 kb
Host smart-10fa7ff0-9b85-407f-a0b8-35d12c9798c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623164624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3623164624
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.3435130785
Short name T291
Test name
Test status
Simulation time 160875749357 ps
CPU time 88.93 seconds
Started Jul 14 04:20:07 PM PDT 24
Finished Jul 14 04:21:37 PM PDT 24
Peak memory 191100 kb
Host smart-525454d6-29b8-4991-8131-8234ff4acc39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435130785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.3435130785
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.2496838328
Short name T238
Test name
Test status
Simulation time 43340662333 ps
CPU time 76.17 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:23:43 PM PDT 24
Peak memory 190952 kb
Host smart-39d7a95b-1fe1-479c-999f-09059300f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496838328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.2496838328
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1355183517
Short name T182
Test name
Test status
Simulation time 421196523102 ps
CPU time 632.85 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:33:01 PM PDT 24
Peak memory 190900 kb
Host smart-afdacb2f-465a-4f06-9bf7-829b4c6c5ad5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355183517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1355183517
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.2083897928
Short name T13
Test name
Test status
Simulation time 24129747754 ps
CPU time 173.22 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:25:21 PM PDT 24
Peak memory 205612 kb
Host smart-fe9ef538-39be-4168-a606-0f4fdb72895b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083897928 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.2083897928
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.234317422
Short name T253
Test name
Test status
Simulation time 166499328815 ps
CPU time 62.15 seconds
Started Jul 14 04:20:53 PM PDT 24
Finished Jul 14 04:21:55 PM PDT 24
Peak memory 182904 kb
Host smart-be4a14b4-8ed9-49c3-8d11-c7f30e558746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234317422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.234317422
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3959266580
Short name T126
Test name
Test status
Simulation time 36253570110 ps
CPU time 26.45 seconds
Started Jul 14 04:20:49 PM PDT 24
Finished Jul 14 04:21:16 PM PDT 24
Peak memory 182948 kb
Host smart-29cd316e-d87b-43fc-9e38-22a849a35c5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959266580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3959266580
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1067964900
Short name T190
Test name
Test status
Simulation time 265894676758 ps
CPU time 123.46 seconds
Started Jul 14 04:20:51 PM PDT 24
Finished Jul 14 04:22:55 PM PDT 24
Peak memory 194444 kb
Host smart-852d85cc-1d17-4a57-8ae3-2878291349f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067964900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1067964900
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.4211684313
Short name T127
Test name
Test status
Simulation time 305617719837 ps
CPU time 415.95 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:29:28 PM PDT 24
Peak memory 190916 kb
Host smart-a3818a4e-efda-48c8-8857-fa829caeab9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211684313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.4211684313
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3608656331
Short name T248
Test name
Test status
Simulation time 66288483195 ps
CPU time 1564.34 seconds
Started Jul 14 04:22:29 PM PDT 24
Finished Jul 14 04:48:36 PM PDT 24
Peak memory 190816 kb
Host smart-fc904596-7f9c-4f0c-ac87-0b12d4e4e14b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608656331 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3608656331
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.1362409946
Short name T286
Test name
Test status
Simulation time 192806298108 ps
CPU time 184.41 seconds
Started Jul 14 04:20:55 PM PDT 24
Finished Jul 14 04:24:00 PM PDT 24
Peak memory 182920 kb
Host smart-ef272f8f-1dfc-42c2-b94f-92613415149d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362409946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.1362409946
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.471063936
Short name T183
Test name
Test status
Simulation time 134788229788 ps
CPU time 59.4 seconds
Started Jul 14 04:22:38 PM PDT 24
Finished Jul 14 04:23:39 PM PDT 24
Peak memory 182916 kb
Host smart-f6f6a7d6-c7eb-4801-8f6d-220faf597183
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471063936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.471063936
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1821477960
Short name T170
Test name
Test status
Simulation time 174484722910 ps
CPU time 472.47 seconds
Started Jul 14 04:21:10 PM PDT 24
Finished Jul 14 04:29:03 PM PDT 24
Peak memory 191128 kb
Host smart-c527d738-edca-44af-8ead-d8fb3cfc4eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821477960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1821477960
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.260590130
Short name T435
Test name
Test status
Simulation time 31982539486 ps
CPU time 47.97 seconds
Started Jul 14 04:23:16 PM PDT 24
Finished Jul 14 04:24:05 PM PDT 24
Peak memory 182912 kb
Host smart-8b0d607e-9be8-4e12-a1c7-bc0de25caeff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260590130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.260590130
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3271254764
Short name T210
Test name
Test status
Simulation time 64243491378 ps
CPU time 112.99 seconds
Started Jul 14 04:22:29 PM PDT 24
Finished Jul 14 04:24:23 PM PDT 24
Peak memory 181736 kb
Host smart-e3bafa5b-b608-44e3-9196-3151db58017a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271254764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3271254764
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2485446918
Short name T27
Test name
Test status
Simulation time 385647546045 ps
CPU time 264.44 seconds
Started Jul 14 04:22:20 PM PDT 24
Finished Jul 14 04:26:45 PM PDT 24
Peak memory 182612 kb
Host smart-747950ad-344a-474b-b7c1-436fcea7fd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485446918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2485446918
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2461544467
Short name T155
Test name
Test status
Simulation time 62950296795 ps
CPU time 517.4 seconds
Started Jul 14 04:22:26 PM PDT 24
Finished Jul 14 04:31:05 PM PDT 24
Peak memory 189964 kb
Host smart-9059add0-cd8c-4324-b499-bf8beff4a01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461544467 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2461544467
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.4182850876
Short name T439
Test name
Test status
Simulation time 4663535556 ps
CPU time 4.36 seconds
Started Jul 14 04:23:03 PM PDT 24
Finished Jul 14 04:23:09 PM PDT 24
Peak memory 182548 kb
Host smart-12559aca-6379-4539-801f-39b14ffa9699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182850876 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.4182850876
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/81.rv_timer_random.1797428343
Short name T226
Test name
Test status
Simulation time 389120730151 ps
CPU time 1586.56 seconds
Started Jul 14 04:21:45 PM PDT 24
Finished Jul 14 04:48:13 PM PDT 24
Peak memory 191116 kb
Host smart-ecf81907-9a29-4691-9bbe-b89888f9c3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797428343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1797428343
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.965260317
Short name T164
Test name
Test status
Simulation time 142822690239 ps
CPU time 245.27 seconds
Started Jul 14 04:22:38 PM PDT 24
Finished Jul 14 04:26:44 PM PDT 24
Peak memory 182908 kb
Host smart-9052146a-e3f2-4835-bde7-5160ac2fd337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965260317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.965260317
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.740281781
Short name T112
Test name
Test status
Simulation time 114761139431 ps
CPU time 293.42 seconds
Started Jul 14 04:23:02 PM PDT 24
Finished Jul 14 04:27:57 PM PDT 24
Peak memory 189740 kb
Host smart-9e465d67-5505-4a55-a209-85cb11b8f549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740281781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.740281781
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.976817227
Short name T265
Test name
Test status
Simulation time 41914123291 ps
CPU time 69.51 seconds
Started Jul 14 04:22:37 PM PDT 24
Finished Jul 14 04:23:47 PM PDT 24
Peak memory 182592 kb
Host smart-c0b50a10-65e6-4626-bab8-1b258dcc78b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976817227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.976817227
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2829136655
Short name T25
Test name
Test status
Simulation time 293323230567 ps
CPU time 1546.87 seconds
Started Jul 14 04:21:19 PM PDT 24
Finished Jul 14 04:47:06 PM PDT 24
Peak memory 191124 kb
Host smart-3f217b46-bb14-40e6-8205-f0e4cd1f4993
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829136655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2829136655
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.472889426
Short name T442
Test name
Test status
Simulation time 562206315844 ps
CPU time 488.36 seconds
Started Jul 14 04:22:38 PM PDT 24
Finished Jul 14 04:30:47 PM PDT 24
Peak memory 190872 kb
Host smart-f5eb956b-0e19-4253-b5d2-3fd014a2c336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472889426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.472889426
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1482691992
Short name T215
Test name
Test status
Simulation time 52397737718 ps
CPU time 80.59 seconds
Started Jul 14 04:21:25 PM PDT 24
Finished Jul 14 04:22:46 PM PDT 24
Peak memory 191248 kb
Host smart-242ded88-d76e-4c85-bf7b-a38c17bbf0fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482691992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1482691992
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.1044082800
Short name T149
Test name
Test status
Simulation time 44903528831 ps
CPU time 17.7 seconds
Started Jul 14 04:22:30 PM PDT 24
Finished Jul 14 04:22:50 PM PDT 24
Peak memory 182692 kb
Host smart-d6653fda-f69e-4654-bcf5-33e4a56b2f25
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044082800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.1044082800
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.2090747793
Short name T429
Test name
Test status
Simulation time 207576118944 ps
CPU time 155.85 seconds
Started Jul 14 04:22:29 PM PDT 24
Finished Jul 14 04:25:07 PM PDT 24
Peak memory 181568 kb
Host smart-8aa4e280-4a4b-4f71-ba3f-93b25a65ba21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090747793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.2090747793
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.3350354700
Short name T125
Test name
Test status
Simulation time 148507023391 ps
CPU time 208.62 seconds
Started Jul 14 04:23:01 PM PDT 24
Finished Jul 14 04:26:31 PM PDT 24
Peak memory 189996 kb
Host smart-0070c7d6-617e-4944-8622-a6eafc7adf28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350354700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.3350354700
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1059646955
Short name T40
Test name
Test status
Simulation time 19658634 ps
CPU time 0.54 seconds
Started Jul 14 04:18:43 PM PDT 24
Finished Jul 14 04:18:44 PM PDT 24
Peak memory 182716 kb
Host smart-622d5e34-88d2-414e-8640-f3157b672fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059646955 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1059646955
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.709887346
Short name T54
Test name
Test status
Simulation time 647252996993 ps
CPU time 208.71 seconds
Started Jul 14 04:21:45 PM PDT 24
Finished Jul 14 04:25:15 PM PDT 24
Peak memory 194712 kb
Host smart-21844d4f-8f07-4683-95d7-5bb6573b73e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709887346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.709887346
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.4135458003
Short name T273
Test name
Test status
Simulation time 41911886078 ps
CPU time 66.46 seconds
Started Jul 14 04:23:03 PM PDT 24
Finished Jul 14 04:24:11 PM PDT 24
Peak memory 182936 kb
Host smart-f926778f-c246-4725-a7d3-73471bc7e8bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135458003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.4135458003
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3785777828
Short name T120
Test name
Test status
Simulation time 657430492999 ps
CPU time 476.37 seconds
Started Jul 14 04:22:50 PM PDT 24
Finished Jul 14 04:30:47 PM PDT 24
Peak memory 191044 kb
Host smart-186a138c-10e9-4bd3-92c5-2a492f1f623f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785777828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3785777828
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.1147038902
Short name T394
Test name
Test status
Simulation time 48971771084 ps
CPU time 80.55 seconds
Started Jul 14 04:21:23 PM PDT 24
Finished Jul 14 04:22:44 PM PDT 24
Peak memory 182928 kb
Host smart-2b3ff0da-6263-4b63-bd10-404a782b3419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147038902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.1147038902
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.868405313
Short name T242
Test name
Test status
Simulation time 124363703537 ps
CPU time 271.96 seconds
Started Jul 14 04:22:51 PM PDT 24
Finished Jul 14 04:27:24 PM PDT 24
Peak memory 194356 kb
Host smart-3f2671e2-c6a8-43e7-a1a6-99ef7692f215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868405313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.868405313
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.2385541631
Short name T316
Test name
Test status
Simulation time 131041081153 ps
CPU time 184.18 seconds
Started Jul 14 04:22:49 PM PDT 24
Finished Jul 14 04:25:54 PM PDT 24
Peak memory 189700 kb
Host smart-16624efe-ab59-4a0b-a69f-8fe6c22eddd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385541631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.2385541631
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.529456190
Short name T189
Test name
Test status
Simulation time 115515067509 ps
CPU time 1707.32 seconds
Started Jul 14 04:21:29 PM PDT 24
Finished Jul 14 04:49:56 PM PDT 24
Peak memory 191296 kb
Host smart-00d458c7-c395-4b0d-b683-1696d10c4c36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529456190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.529456190
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2958355571
Short name T158
Test name
Test status
Simulation time 219607022745 ps
CPU time 476.76 seconds
Started Jul 14 04:22:51 PM PDT 24
Finished Jul 14 04:30:48 PM PDT 24
Peak memory 191036 kb
Host smart-1d28ac74-0dff-488b-b5eb-dae79498764c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958355571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2958355571
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.2419075787
Short name T311
Test name
Test status
Simulation time 52134462107 ps
CPU time 89.88 seconds
Started Jul 14 04:21:40 PM PDT 24
Finished Jul 14 04:23:10 PM PDT 24
Peak memory 191124 kb
Host smart-76371104-ce68-4b2b-9f68-8a97f8e3bd94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419075787 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.2419075787
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2444479897
Short name T85
Test name
Test status
Simulation time 178900114539 ps
CPU time 860.54 seconds
Started Jul 14 04:22:49 PM PDT 24
Finished Jul 14 04:37:10 PM PDT 24
Peak memory 190164 kb
Host smart-77434629-894a-4f1e-b9b1-eee68c1f0c16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444479897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2444479897
Directory /workspace/99.rv_timer_random/latest
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