Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.59 99.36 98.73 100.00 100.00 100.00 99.43


Total test records in report: 575
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T507 /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.4145185352 Jul 15 04:50:44 PM PDT 24 Jul 15 04:50:47 PM PDT 24 54359666 ps
T508 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2687375738 Jul 15 04:50:42 PM PDT 24 Jul 15 04:50:44 PM PDT 24 432887205 ps
T509 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1010548457 Jul 15 04:50:44 PM PDT 24 Jul 15 04:50:45 PM PDT 24 45467273 ps
T510 /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2275766366 Jul 15 04:51:04 PM PDT 24 Jul 15 04:51:06 PM PDT 24 13122745 ps
T511 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3360682167 Jul 15 04:50:31 PM PDT 24 Jul 15 04:50:35 PM PDT 24 738026923 ps
T512 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1067944101 Jul 15 04:50:53 PM PDT 24 Jul 15 04:50:57 PM PDT 24 36999829 ps
T513 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2476620307 Jul 15 04:50:57 PM PDT 24 Jul 15 04:51:00 PM PDT 24 24413109 ps
T514 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3631226081 Jul 15 04:50:37 PM PDT 24 Jul 15 04:50:40 PM PDT 24 18414584 ps
T515 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2182938454 Jul 15 04:50:57 PM PDT 24 Jul 15 04:50:59 PM PDT 24 14651962 ps
T516 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2690938664 Jul 15 04:50:46 PM PDT 24 Jul 15 04:50:49 PM PDT 24 18415229 ps
T517 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2780885908 Jul 15 04:50:37 PM PDT 24 Jul 15 04:50:39 PM PDT 24 49162157 ps
T518 /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4218781235 Jul 15 04:50:44 PM PDT 24 Jul 15 04:50:49 PM PDT 24 213534267 ps
T519 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1103124801 Jul 15 04:50:35 PM PDT 24 Jul 15 04:50:37 PM PDT 24 25717759 ps
T520 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1650510446 Jul 15 04:50:56 PM PDT 24 Jul 15 04:50:59 PM PDT 24 43710654 ps
T87 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1612844095 Jul 15 04:50:45 PM PDT 24 Jul 15 04:50:48 PM PDT 24 22385886 ps
T88 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3929975618 Jul 15 04:50:48 PM PDT 24 Jul 15 04:50:50 PM PDT 24 15537642 ps
T521 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1418023527 Jul 15 04:50:57 PM PDT 24 Jul 15 04:51:01 PM PDT 24 89628896 ps
T522 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1481116311 Jul 15 04:50:47 PM PDT 24 Jul 15 04:50:50 PM PDT 24 147633073 ps
T523 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3172069429 Jul 15 04:50:36 PM PDT 24 Jul 15 04:50:37 PM PDT 24 13646109 ps
T524 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1220359034 Jul 15 04:50:58 PM PDT 24 Jul 15 04:51:00 PM PDT 24 92841855 ps
T525 /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3789275610 Jul 15 04:50:44 PM PDT 24 Jul 15 04:50:49 PM PDT 24 43300658 ps
T526 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1606420483 Jul 15 04:50:54 PM PDT 24 Jul 15 04:50:57 PM PDT 24 605953329 ps
T527 /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1605291488 Jul 15 04:50:45 PM PDT 24 Jul 15 04:50:48 PM PDT 24 72208221 ps
T528 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2629538967 Jul 15 04:50:52 PM PDT 24 Jul 15 04:50:54 PM PDT 24 15610458 ps
T529 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2060580731 Jul 15 04:50:44 PM PDT 24 Jul 15 04:50:47 PM PDT 24 35020459 ps
T530 /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4172515247 Jul 15 04:50:42 PM PDT 24 Jul 15 04:50:43 PM PDT 24 15075366 ps
T531 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3334934551 Jul 15 04:51:01 PM PDT 24 Jul 15 04:51:04 PM PDT 24 125753730 ps
T532 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.647235746 Jul 15 04:50:52 PM PDT 24 Jul 15 04:50:55 PM PDT 24 63911898 ps
T533 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.684758350 Jul 15 04:50:43 PM PDT 24 Jul 15 04:50:46 PM PDT 24 37775616 ps
T534 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4178685355 Jul 15 04:51:04 PM PDT 24 Jul 15 04:51:06 PM PDT 24 10654328 ps
T535 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2921694507 Jul 15 04:50:54 PM PDT 24 Jul 15 04:50:57 PM PDT 24 51844869 ps
T536 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1478161583 Jul 15 04:50:56 PM PDT 24 Jul 15 04:50:59 PM PDT 24 71025242 ps
T537 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2999193528 Jul 15 04:51:02 PM PDT 24 Jul 15 04:51:05 PM PDT 24 26138419 ps
T538 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1720984141 Jul 15 04:50:45 PM PDT 24 Jul 15 04:50:48 PM PDT 24 118893217 ps
T539 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.327285382 Jul 15 04:50:56 PM PDT 24 Jul 15 04:50:58 PM PDT 24 32696158 ps
T540 /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4071954 Jul 15 04:50:44 PM PDT 24 Jul 15 04:50:48 PM PDT 24 59681561 ps
T541 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3475334418 Jul 15 04:50:52 PM PDT 24 Jul 15 04:50:54 PM PDT 24 23177431 ps
T542 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1444397114 Jul 15 04:50:57 PM PDT 24 Jul 15 04:50:59 PM PDT 24 142542600 ps
T93 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1451513537 Jul 15 04:50:51 PM PDT 24 Jul 15 04:50:53 PM PDT 24 33159072 ps
T90 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.4093702046 Jul 15 04:50:52 PM PDT 24 Jul 15 04:50:55 PM PDT 24 17529311 ps
T543 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3802857045 Jul 15 04:51:01 PM PDT 24 Jul 15 04:51:04 PM PDT 24 56594487 ps
T544 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1470110866 Jul 15 04:51:01 PM PDT 24 Jul 15 04:51:04 PM PDT 24 30398559 ps
T545 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2180449379 Jul 15 04:50:53 PM PDT 24 Jul 15 04:50:56 PM PDT 24 17471969 ps
T546 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1902415427 Jul 15 04:50:45 PM PDT 24 Jul 15 04:50:48 PM PDT 24 30658543 ps
T547 /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.361046004 Jul 15 04:50:58 PM PDT 24 Jul 15 04:51:02 PM PDT 24 63578241 ps
T548 /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2226177106 Jul 15 04:51:05 PM PDT 24 Jul 15 04:51:07 PM PDT 24 69711961 ps
T549 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.785240912 Jul 15 04:51:02 PM PDT 24 Jul 15 04:51:05 PM PDT 24 54113096 ps
T550 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.245543229 Jul 15 04:51:13 PM PDT 24 Jul 15 04:51:15 PM PDT 24 73911354 ps
T91 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3083574217 Jul 15 04:50:40 PM PDT 24 Jul 15 04:50:42 PM PDT 24 44679978 ps
T92 /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3162656903 Jul 15 04:50:45 PM PDT 24 Jul 15 04:50:50 PM PDT 24 658367653 ps
T551 /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1778137459 Jul 15 04:50:43 PM PDT 24 Jul 15 04:50:45 PM PDT 24 54668212 ps
T552 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2304649406 Jul 15 04:50:36 PM PDT 24 Jul 15 04:50:38 PM PDT 24 608419898 ps
T553 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1622430463 Jul 15 04:50:42 PM PDT 24 Jul 15 04:50:43 PM PDT 24 31281490 ps
T554 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3298592476 Jul 15 04:50:46 PM PDT 24 Jul 15 04:50:50 PM PDT 24 124288933 ps
T555 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1476928754 Jul 15 04:50:48 PM PDT 24 Jul 15 04:50:53 PM PDT 24 59497491 ps
T556 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3478899874 Jul 15 04:51:00 PM PDT 24 Jul 15 04:51:03 PM PDT 24 29296366 ps
T557 /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2028501871 Jul 15 04:50:43 PM PDT 24 Jul 15 04:50:45 PM PDT 24 13537200 ps
T558 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.4022201302 Jul 15 04:50:45 PM PDT 24 Jul 15 04:50:47 PM PDT 24 31387524 ps
T559 /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3383365171 Jul 15 04:51:02 PM PDT 24 Jul 15 04:51:05 PM PDT 24 12498590 ps
T560 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.400513342 Jul 15 04:50:41 PM PDT 24 Jul 15 04:50:44 PM PDT 24 492578560 ps
T561 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1154321669 Jul 15 04:50:49 PM PDT 24 Jul 15 04:50:51 PM PDT 24 47780684 ps
T562 /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1512624165 Jul 15 04:50:45 PM PDT 24 Jul 15 04:50:48 PM PDT 24 19500598 ps
T563 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1547174122 Jul 15 04:50:55 PM PDT 24 Jul 15 04:50:57 PM PDT 24 34624917 ps
T564 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1019786195 Jul 15 04:50:59 PM PDT 24 Jul 15 04:51:03 PM PDT 24 42474113 ps
T565 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1757541474 Jul 15 04:50:52 PM PDT 24 Jul 15 04:50:55 PM PDT 24 11701312 ps
T566 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3176613964 Jul 15 04:50:35 PM PDT 24 Jul 15 04:50:37 PM PDT 24 17421684 ps
T567 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2129171839 Jul 15 04:51:03 PM PDT 24 Jul 15 04:51:05 PM PDT 24 36597482 ps
T568 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2257858560 Jul 15 04:51:01 PM PDT 24 Jul 15 04:51:04 PM PDT 24 102118662 ps
T569 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1004621686 Jul 15 04:50:47 PM PDT 24 Jul 15 04:50:52 PM PDT 24 114379501 ps
T570 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4071983998 Jul 15 04:50:35 PM PDT 24 Jul 15 04:50:37 PM PDT 24 140500299 ps
T571 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2287043475 Jul 15 04:51:03 PM PDT 24 Jul 15 04:51:05 PM PDT 24 46227477 ps
T572 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.4117255192 Jul 15 04:50:47 PM PDT 24 Jul 15 04:50:50 PM PDT 24 60925385 ps
T573 /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.754283913 Jul 15 04:50:37 PM PDT 24 Jul 15 04:50:39 PM PDT 24 15134938 ps
T574 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2256080987 Jul 15 04:50:58 PM PDT 24 Jul 15 04:51:01 PM PDT 24 19871503 ps
T575 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2486152741 Jul 15 04:50:44 PM PDT 24 Jul 15 04:50:48 PM PDT 24 512630998 ps

Test location /workspace/coverage/default/21.rv_timer_stress_all.1228416902
Short name T2
Test name
Test status
Simulation time 5575928771501 ps
CPU time 1782.61 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 04:59:33 PM PDT 24
Peak memory 191044 kb
Host smart-2ac0f00f-a615-4a70-8cd1-00f46705a9f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228416902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1228416902
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3135410716
Short name T13
Test name
Test status
Simulation time 642568646726 ps
CPU time 1153.54 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:49:03 PM PDT 24
Peak memory 214016 kb
Host smart-34b066bc-8b0a-420e-89d2-567993b8227e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135410716 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3135410716
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2929602978
Short name T6
Test name
Test status
Simulation time 1976049088888 ps
CPU time 3772.62 seconds
Started Jul 15 04:29:45 PM PDT 24
Finished Jul 15 05:32:40 PM PDT 24
Peak memory 191096 kb
Host smart-72d9bfd7-cff9-4350-8463-0d5cca25d423
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929602978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2929602978
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.3515972723
Short name T29
Test name
Test status
Simulation time 223676991 ps
CPU time 0.78 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 182408 kb
Host smart-7e5a3423-7c0f-410c-966b-68c5562a2ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515972723 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_i
ntg_err.3515972723
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.3799227762
Short name T23
Test name
Test status
Simulation time 1445632939574 ps
CPU time 1203.54 seconds
Started Jul 15 04:29:25 PM PDT 24
Finished Jul 15 04:49:30 PM PDT 24
Peak memory 190948 kb
Host smart-b5ab6a4e-758c-40e7-85bf-81e82995341f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799227762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
3799227762
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.1633499303
Short name T66
Test name
Test status
Simulation time 2626695087095 ps
CPU time 2598.22 seconds
Started Jul 15 04:30:41 PM PDT 24
Finished Jul 15 05:14:01 PM PDT 24
Peak memory 195236 kb
Host smart-88040e40-cd7d-49a0-b205-a8f84a69cc62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633499303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all
.1633499303
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3004933422
Short name T54
Test name
Test status
Simulation time 2249992790986 ps
CPU time 1204.5 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 04:50:00 PM PDT 24
Peak memory 191056 kb
Host smart-c4f3f128-6a82-4ff5-aa55-13043ab93399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004933422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3004933422
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.3692913978
Short name T17
Test name
Test status
Simulation time 40912423 ps
CPU time 0.76 seconds
Started Jul 15 04:27:40 PM PDT 24
Finished Jul 15 04:27:44 PM PDT 24
Peak memory 212456 kb
Host smart-66e14dce-ccc6-4d20-9d70-7765ca74b342
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692913978 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.3692913978
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.4181331227
Short name T143
Test name
Test status
Simulation time 816881259601 ps
CPU time 2768.01 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 05:15:59 PM PDT 24
Peak memory 191072 kb
Host smart-85fbf95b-75d9-4edb-a3dc-b9e44a0d0da4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181331227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.4181331227
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2443008769
Short name T220
Test name
Test status
Simulation time 1303042017054 ps
CPU time 1510.26 seconds
Started Jul 15 04:26:41 PM PDT 24
Finished Jul 15 04:51:51 PM PDT 24
Peak memory 191092 kb
Host smart-1bfdc505-9819-4530-bc16-feda5c613361
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443008769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2443008769
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.1039997167
Short name T189
Test name
Test status
Simulation time 4750074554656 ps
CPU time 3922.29 seconds
Started Jul 15 04:29:43 PM PDT 24
Finished Jul 15 05:35:06 PM PDT 24
Peak memory 191080 kb
Host smart-c96658e3-8dca-4806-b987-4900a51ff9b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039997167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all
.1039997167
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3087493315
Short name T150
Test name
Test status
Simulation time 549440028576 ps
CPU time 1175.34 seconds
Started Jul 15 04:27:37 PM PDT 24
Finished Jul 15 04:47:17 PM PDT 24
Peak memory 189584 kb
Host smart-c02a82a3-8876-41c7-a10c-b1b4a608e64f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087493315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3087493315
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.2345870334
Short name T60
Test name
Test status
Simulation time 1721947201985 ps
CPU time 1189.92 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:49:39 PM PDT 24
Peak memory 191116 kb
Host smart-8b5ca3ae-86ef-4542-a1fc-39f24618ed74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345870334 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.2345870334
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3129627952
Short name T57
Test name
Test status
Simulation time 1014696160248 ps
CPU time 1388.95 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 04:52:59 PM PDT 24
Peak memory 195536 kb
Host smart-a2a79ea5-1865-4bc0-9a3e-35485af95b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129627952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3129627952
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.281014349
Short name T58
Test name
Test status
Simulation time 1510828738710 ps
CPU time 1529.46 seconds
Started Jul 15 04:29:58 PM PDT 24
Finished Jul 15 04:55:29 PM PDT 24
Peak memory 196144 kb
Host smart-f6e89c0e-9c35-48e5-a39a-ae84eb08224b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281014349 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
281014349
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/106.rv_timer_random.74636790
Short name T110
Test name
Test status
Simulation time 313023103841 ps
CPU time 339.86 seconds
Started Jul 15 04:30:08 PM PDT 24
Finished Jul 15 04:35:49 PM PDT 24
Peak memory 193168 kb
Host smart-a1c30e7c-461a-4194-af7a-13193b1ba491
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74636790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.74636790
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.3198543068
Short name T155
Test name
Test status
Simulation time 5601003690156 ps
CPU time 1808.92 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 05:00:04 PM PDT 24
Peak memory 191072 kb
Host smart-4a683509-c2a3-4180-af42-f9937e502a4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198543068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all
.3198543068
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3126515957
Short name T53
Test name
Test status
Simulation time 1030429208685 ps
CPU time 1128.11 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:48:44 PM PDT 24
Peak memory 191108 kb
Host smart-8e81eedb-48be-47bb-8aaf-9ffbc4adeec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126515957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3126515957
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/142.rv_timer_random.1222252759
Short name T266
Test name
Test status
Simulation time 97364670948 ps
CPU time 154.62 seconds
Started Jul 15 04:30:19 PM PDT 24
Finished Jul 15 04:32:55 PM PDT 24
Peak memory 191092 kb
Host smart-4ee12375-ef9f-407a-bb88-2bb4c07fdde3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222252759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.1222252759
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.2591365323
Short name T104
Test name
Test status
Simulation time 1157304310143 ps
CPU time 908.34 seconds
Started Jul 15 04:29:54 PM PDT 24
Finished Jul 15 04:45:05 PM PDT 24
Peak memory 191076 kb
Host smart-885b11c6-cb91-45ad-8957-dde11acf3c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591365323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.2591365323
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.450181237
Short name T138
Test name
Test status
Simulation time 480541285011 ps
CPU time 1032.62 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 04:47:04 PM PDT 24
Peak memory 191108 kb
Host smart-95d977fe-d89e-4af2-9a54-9c7ad9902db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450181237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
450181237
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/134.rv_timer_random.3163964063
Short name T166
Test name
Test status
Simulation time 522208833786 ps
CPU time 617.36 seconds
Started Jul 15 04:30:21 PM PDT 24
Finished Jul 15 04:40:40 PM PDT 24
Peak memory 191060 kb
Host smart-afb4c19d-cd95-44dd-b7c7-7793a50f7986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163964063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.3163964063
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2907578021
Short name T115
Test name
Test status
Simulation time 160451416816 ps
CPU time 452.29 seconds
Started Jul 15 04:29:54 PM PDT 24
Finished Jul 15 04:37:29 PM PDT 24
Peak memory 191100 kb
Host smart-f3e22403-a9fc-48aa-be56-5d195fc610fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907578021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2907578021
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.75821725
Short name T141
Test name
Test status
Simulation time 193975945292 ps
CPU time 357.74 seconds
Started Jul 15 04:30:15 PM PDT 24
Finished Jul 15 04:36:15 PM PDT 24
Peak memory 193288 kb
Host smart-7f783013-c1f9-4ce9-a7ec-8aed0cf51329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75821725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.75821725
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.2477180834
Short name T59
Test name
Test status
Simulation time 1089605293724 ps
CPU time 1124.59 seconds
Started Jul 15 04:30:09 PM PDT 24
Finished Jul 15 04:48:55 PM PDT 24
Peak memory 191096 kb
Host smart-198e22da-e625-401d-ac36-57df86ade748
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477180834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.2477180834
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_random.3733542253
Short name T160
Test name
Test status
Simulation time 1818408461922 ps
CPU time 664.12 seconds
Started Jul 15 04:29:45 PM PDT 24
Finished Jul 15 04:40:51 PM PDT 24
Peak memory 191064 kb
Host smart-f59686b5-9afd-4325-9ae1-00104349ef80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733542253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3733542253
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.3256184051
Short name T259
Test name
Test status
Simulation time 138322600538 ps
CPU time 196.84 seconds
Started Jul 15 04:30:18 PM PDT 24
Finished Jul 15 04:33:36 PM PDT 24
Peak memory 191100 kb
Host smart-ae00af9d-926c-4e5e-91d6-6d24688021f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256184051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3256184051
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random.159132806
Short name T327
Test name
Test status
Simulation time 608768641198 ps
CPU time 337.48 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 04:35:29 PM PDT 24
Peak memory 191072 kb
Host smart-317acc4a-7e7e-4850-81a0-d6c0ba3dab44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159132806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.159132806
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.959383029
Short name T247
Test name
Test status
Simulation time 218013906680 ps
CPU time 375.99 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:36:11 PM PDT 24
Peak memory 183000 kb
Host smart-fb2f2027-a0c5-4b8c-982e-463060514e13
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959383029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.rv_timer_cfg_update_on_fly.959383029
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2741333016
Short name T181
Test name
Test status
Simulation time 151725165444 ps
CPU time 270.03 seconds
Started Jul 15 04:22:10 PM PDT 24
Finished Jul 15 04:26:40 PM PDT 24
Peak memory 191432 kb
Host smart-891468f8-8dcf-47d5-965c-3a4a00775d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741333016 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2741333016
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/124.rv_timer_random.223517207
Short name T186
Test name
Test status
Simulation time 106836083475 ps
CPU time 1925.92 seconds
Started Jul 15 04:30:08 PM PDT 24
Finished Jul 15 05:02:16 PM PDT 24
Peak memory 191204 kb
Host smart-c1dd6b44-e8e2-47f0-9926-86f31436f350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223517207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.223517207
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.3895483945
Short name T268
Test name
Test status
Simulation time 293296092789 ps
CPU time 133.85 seconds
Started Jul 15 04:29:37 PM PDT 24
Finished Jul 15 04:31:52 PM PDT 24
Peak memory 191124 kb
Host smart-18822756-33bb-4000-92b4-477329f209d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895483945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.3895483945
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/132.rv_timer_random.4275283926
Short name T193
Test name
Test status
Simulation time 126613934269 ps
CPU time 322.39 seconds
Started Jul 15 04:30:06 PM PDT 24
Finished Jul 15 04:35:30 PM PDT 24
Peak memory 191064 kb
Host smart-6432d123-171c-49c3-bd48-2e86b7a30ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275283926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.4275283926
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.710562322
Short name T127
Test name
Test status
Simulation time 441560638224 ps
CPU time 578.17 seconds
Started Jul 15 04:30:17 PM PDT 24
Finished Jul 15 04:39:57 PM PDT 24
Peak memory 191024 kb
Host smart-47868131-fc2d-4d96-bbc3-c008f2d08ca5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710562322 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.710562322
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.1710944335
Short name T255
Test name
Test status
Simulation time 289328886910 ps
CPU time 587.63 seconds
Started Jul 15 04:30:17 PM PDT 24
Finished Jul 15 04:40:06 PM PDT 24
Peak memory 191068 kb
Host smart-76646914-23ef-42f5-9fb7-e8cc0f32c927
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710944335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.1710944335
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random.648282697
Short name T195
Test name
Test status
Simulation time 91229397377 ps
CPU time 411.06 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:36:41 PM PDT 24
Peak memory 191084 kb
Host smart-1ee0a658-5d4f-492f-add2-d317d924eebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648282697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.648282697
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.4258493404
Short name T176
Test name
Test status
Simulation time 93549054719 ps
CPU time 139.66 seconds
Started Jul 15 04:30:22 PM PDT 24
Finished Jul 15 04:32:43 PM PDT 24
Peak memory 191068 kb
Host smart-8030622e-7f65-47ac-8158-f49072edd9a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258493404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.4258493404
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/121.rv_timer_random.3433974453
Short name T245
Test name
Test status
Simulation time 159575035444 ps
CPU time 224.75 seconds
Started Jul 15 04:30:24 PM PDT 24
Finished Jul 15 04:34:10 PM PDT 24
Peak memory 194332 kb
Host smart-bcf2bd4e-bdb8-463d-9cea-319a4b62b8c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433974453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.3433974453
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.307309895
Short name T228
Test name
Test status
Simulation time 154872503560 ps
CPU time 79.6 seconds
Started Jul 15 04:30:21 PM PDT 24
Finished Jul 15 04:31:42 PM PDT 24
Peak memory 191076 kb
Host smart-fc699c64-2dd4-45c6-b319-5325f004cd50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307309895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.307309895
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.3446419047
Short name T112
Test name
Test status
Simulation time 1502516808907 ps
CPU time 875.05 seconds
Started Jul 15 04:30:13 PM PDT 24
Finished Jul 15 04:44:51 PM PDT 24
Peak memory 191112 kb
Host smart-268991b2-8408-47ef-8161-c4465dbc03af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446419047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.3446419047
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.559475088
Short name T179
Test name
Test status
Simulation time 227398781053 ps
CPU time 372.86 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 04:35:58 PM PDT 24
Peak memory 191064 kb
Host smart-1f85dbb7-d770-4c58-ba1d-8c57c81f61a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559475088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all.
559475088
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_random.2699043374
Short name T203
Test name
Test status
Simulation time 78251074444 ps
CPU time 130.19 seconds
Started Jul 15 04:29:39 PM PDT 24
Finished Jul 15 04:31:50 PM PDT 24
Peak memory 191108 kb
Host smart-e21f5e67-b485-43eb-8746-c8d91f0b9273
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699043374 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.2699043374
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.3481020423
Short name T20
Test name
Test status
Simulation time 1421620611254 ps
CPU time 669.69 seconds
Started Jul 15 04:24:06 PM PDT 24
Finished Jul 15 04:35:17 PM PDT 24
Peak memory 182204 kb
Host smart-5d23e546-718c-473d-8790-16737362e44a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481020423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.3481020423
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2986548552
Short name T100
Test name
Test status
Simulation time 224063764 ps
CPU time 1.39 seconds
Started Jul 15 04:50:57 PM PDT 24
Finished Jul 15 04:51:00 PM PDT 24
Peak memory 194924 kb
Host smart-504e6a0e-7f1b-4e1e-987a-7d86a945cec8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986548552 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.2986548552
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/168.rv_timer_random.1859842813
Short name T248
Test name
Test status
Simulation time 568640305777 ps
CPU time 379.56 seconds
Started Jul 15 04:30:17 PM PDT 24
Finished Jul 15 04:36:38 PM PDT 24
Peak memory 193744 kb
Host smart-560e0267-9b76-48e3-a99d-db00c549e15e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859842813 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.1859842813
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.86349027
Short name T130
Test name
Test status
Simulation time 235035846079 ps
CPU time 308.03 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:35:24 PM PDT 24
Peak memory 191080 kb
Host smart-5137356f-5ef1-4c72-b39b-c90ed267f835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86349027 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.86349027
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.1955275625
Short name T298
Test name
Test status
Simulation time 504557037986 ps
CPU time 432.5 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:37:29 PM PDT 24
Peak memory 191104 kb
Host smart-339c23af-909d-40cc-8cb6-7b36de64cbe5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955275625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.1955275625
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.3077099959
Short name T1
Test name
Test status
Simulation time 124908007176 ps
CPU time 398.26 seconds
Started Jul 15 04:30:20 PM PDT 24
Finished Jul 15 04:37:00 PM PDT 24
Peak memory 191176 kb
Host smart-0d10ef67-9412-4576-a3e8-d5b29ab0b130
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077099959 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.3077099959
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.516797012
Short name T158
Test name
Test status
Simulation time 1445671627505 ps
CPU time 3529.3 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 05:28:34 PM PDT 24
Peak memory 191048 kb
Host smart-cd9b645f-368c-425e-960e-e7b53d194f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516797012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all.
516797012
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3787763758
Short name T3
Test name
Test status
Simulation time 463475742331 ps
CPU time 875.93 seconds
Started Jul 15 04:30:05 PM PDT 24
Finished Jul 15 04:44:43 PM PDT 24
Peak memory 194680 kb
Host smart-181cbcec-e075-4705-bf57-b9a6e7dc85fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787763758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3787763758
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/52.rv_timer_random.3120290381
Short name T210
Test name
Test status
Simulation time 188637765042 ps
CPU time 474.48 seconds
Started Jul 15 04:29:58 PM PDT 24
Finished Jul 15 04:37:54 PM PDT 24
Peak memory 191240 kb
Host smart-5d1cfd20-507b-4b69-adb5-5f15d37ae035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120290381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3120290381
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.747470659
Short name T215
Test name
Test status
Simulation time 74832194812 ps
CPU time 230.7 seconds
Started Jul 15 04:30:03 PM PDT 24
Finished Jul 15 04:33:55 PM PDT 24
Peak memory 194396 kb
Host smart-c1832a11-1e9a-40b6-b860-f0344c3f322d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747470659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.747470659
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.3452585831
Short name T49
Test name
Test status
Simulation time 34256975 ps
CPU time 0.88 seconds
Started Jul 15 04:50:33 PM PDT 24
Finished Jul 15 04:50:36 PM PDT 24
Peak memory 192212 kb
Host smart-7784b9ac-eada-4527-b7b1-63b704df12cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452585831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alia
sing.3452585831
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.3016883398
Short name T97
Test name
Test status
Simulation time 120375457 ps
CPU time 0.77 seconds
Started Jul 15 04:50:53 PM PDT 24
Finished Jul 15 04:50:56 PM PDT 24
Peak memory 191076 kb
Host smart-341e9d50-033a-43a8-858e-195192bc3c8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016883398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.3016883398
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_timer_random.1954736424
Short name T261
Test name
Test status
Simulation time 1098627277554 ps
CPU time 648.25 seconds
Started Jul 15 04:27:58 PM PDT 24
Finished Jul 15 04:38:51 PM PDT 24
Peak memory 191128 kb
Host smart-11ac6478-f7fb-43ec-9970-55546f51bf42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954736424 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.1954736424
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random.2995394089
Short name T241
Test name
Test status
Simulation time 160007517571 ps
CPU time 219.02 seconds
Started Jul 15 04:29:33 PM PDT 24
Finished Jul 15 04:33:14 PM PDT 24
Peak memory 191100 kb
Host smart-47d108bb-009d-4a01-b316-9e5f1fecefbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995394089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.2995394089
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random.3981748918
Short name T278
Test name
Test status
Simulation time 113778879994 ps
CPU time 1738.73 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:58:53 PM PDT 24
Peak memory 191044 kb
Host smart-0db7f526-ba8f-402a-9cdd-951b457bfbc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981748918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.3981748918
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.2961750861
Short name T106
Test name
Test status
Simulation time 318685904067 ps
CPU time 437.55 seconds
Started Jul 15 04:30:10 PM PDT 24
Finished Jul 15 04:37:29 PM PDT 24
Peak memory 191200 kb
Host smart-5c80346e-4fe1-445b-bb89-7cff24d3daea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961750861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.2961750861
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.3570329796
Short name T114
Test name
Test status
Simulation time 357751647617 ps
CPU time 1903.22 seconds
Started Jul 15 04:30:04 PM PDT 24
Finished Jul 15 05:01:49 PM PDT 24
Peak memory 194196 kb
Host smart-99d138b0-02e7-411b-8697-7641e9b5e701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570329796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.3570329796
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.464109072
Short name T214
Test name
Test status
Simulation time 342452772950 ps
CPU time 536.13 seconds
Started Jul 15 04:29:38 PM PDT 24
Finished Jul 15 04:38:36 PM PDT 24
Peak memory 182824 kb
Host smart-89fcbbf7-8012-4fef-8dab-0bb6ce5c4180
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464109072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.464109072
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.4236432913
Short name T55
Test name
Test status
Simulation time 94971431604 ps
CPU time 33.82 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:30:59 PM PDT 24
Peak memory 190404 kb
Host smart-1511677a-79c9-46b6-96ac-cf052ba88eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236432913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.4236432913
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/125.rv_timer_random.1465216904
Short name T280
Test name
Test status
Simulation time 309246631943 ps
CPU time 232.7 seconds
Started Jul 15 04:30:16 PM PDT 24
Finished Jul 15 04:34:11 PM PDT 24
Peak memory 191208 kb
Host smart-6a0544ac-7177-49ad-a0fa-a7ff9a1babc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465216904 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1465216904
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3029333833
Short name T188
Test name
Test status
Simulation time 94891782332 ps
CPU time 1072.43 seconds
Started Jul 15 04:30:30 PM PDT 24
Finished Jul 15 04:48:25 PM PDT 24
Peak memory 194736 kb
Host smart-957207ff-cba7-4511-920d-30d767226e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029333833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3029333833
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random.1575181638
Short name T173
Test name
Test status
Simulation time 358590133453 ps
CPU time 499.61 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:38:10 PM PDT 24
Peak memory 191064 kb
Host smart-d045023e-005a-41e0-9f19-7662b57b8b45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575181638 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1575181638
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.3039429705
Short name T329
Test name
Test status
Simulation time 293041070112 ps
CPU time 461.09 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:37:31 PM PDT 24
Peak memory 182880 kb
Host smart-c8741a60-6600-4c99-809c-b118af8e9299
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039429705 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.rv_timer_cfg_update_on_fly.3039429705
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.518364957
Short name T285
Test name
Test status
Simulation time 159879213776 ps
CPU time 696.23 seconds
Started Jul 15 04:29:49 PM PDT 24
Finished Jul 15 04:41:28 PM PDT 24
Peak memory 194584 kb
Host smart-230f5714-bf94-497f-a97c-f310d53065d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518364957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.518364957
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all_with_rand_reset.142763027
Short name T36
Test name
Test status
Simulation time 67144238201 ps
CPU time 1267.64 seconds
Started Jul 15 04:29:49 PM PDT 24
Finished Jul 15 04:51:00 PM PDT 24
Peak memory 207080 kb
Host smart-bc571b19-fa34-4e25-9f1b-f8bd3fcbad10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142763027 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all_with_rand_reset.142763027
Directory /workspace/32.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.2197738759
Short name T289
Test name
Test status
Simulation time 1461545821770 ps
CPU time 720.79 seconds
Started Jul 15 04:29:54 PM PDT 24
Finished Jul 15 04:41:58 PM PDT 24
Peak memory 182868 kb
Host smart-8d8f48fa-d1c1-4c5e-84c0-954ea595db2e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197738759 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.2197738759
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2641699080
Short name T202
Test name
Test status
Simulation time 743514669554 ps
CPU time 1216.47 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 04:50:12 PM PDT 24
Peak memory 195560 kb
Host smart-8ab5d880-5e5c-44a7-9401-c3f23c816a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641699080 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2641699080
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.4002754264
Short name T198
Test name
Test status
Simulation time 4301672678533 ps
CPU time 1549.31 seconds
Started Jul 15 04:29:59 PM PDT 24
Finished Jul 15 04:55:49 PM PDT 24
Peak memory 191076 kb
Host smart-752cab73-578f-43aa-8148-11704fd96d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002754264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.4002754264
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_random.878783139
Short name T244
Test name
Test status
Simulation time 193220866998 ps
CPU time 480.09 seconds
Started Jul 15 04:27:44 PM PDT 24
Finished Jul 15 04:35:46 PM PDT 24
Peak memory 191056 kb
Host smart-bfbb1758-a9c9-45e0-b00b-cd85a45b798b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878783139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.878783139
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.805029050
Short name T307
Test name
Test status
Simulation time 1068541223257 ps
CPU time 535.33 seconds
Started Jul 15 04:23:34 PM PDT 24
Finished Jul 15 04:32:30 PM PDT 24
Peak memory 182896 kb
Host smart-ae075c24-39c6-412a-bc7b-f7b175b042e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805029050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.rv_timer_cfg_update_on_fly.805029050
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.633600699
Short name T185
Test name
Test status
Simulation time 83225190550 ps
CPU time 38.46 seconds
Started Jul 15 04:29:43 PM PDT 24
Finished Jul 15 04:30:22 PM PDT 24
Peak memory 183032 kb
Host smart-8f54baf2-80e7-43fc-ad17-dae539facd6b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633600699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.633600699
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/104.rv_timer_random.854636599
Short name T153
Test name
Test status
Simulation time 46234415655 ps
CPU time 68.76 seconds
Started Jul 15 04:30:00 PM PDT 24
Finished Jul 15 04:31:10 PM PDT 24
Peak memory 191196 kb
Host smart-b618e751-953b-4f15-acf7-ad82168c15e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854636599 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.854636599
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3148130958
Short name T216
Test name
Test status
Simulation time 39522131733 ps
CPU time 65.22 seconds
Started Jul 15 04:29:58 PM PDT 24
Finished Jul 15 04:31:04 PM PDT 24
Peak memory 181944 kb
Host smart-91d01c2f-ba19-496b-80c1-0de1dd753c3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148130958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3148130958
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.3871132674
Short name T358
Test name
Test status
Simulation time 84237940874 ps
CPU time 146.82 seconds
Started Jul 15 04:30:21 PM PDT 24
Finished Jul 15 04:32:49 PM PDT 24
Peak memory 194292 kb
Host smart-6d5a8a93-89d7-4bfa-af16-804c0ebe5bd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871132674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.3871132674
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.2324712092
Short name T227
Test name
Test status
Simulation time 223685438977 ps
CPU time 523.77 seconds
Started Jul 15 04:30:10 PM PDT 24
Finished Jul 15 04:38:56 PM PDT 24
Peak memory 191060 kb
Host smart-a36e1ea1-fba3-47e9-8340-fd6adfe35bff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324712092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.2324712092
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3431819628
Short name T312
Test name
Test status
Simulation time 846887114635 ps
CPU time 393.85 seconds
Started Jul 15 04:29:30 PM PDT 24
Finished Jul 15 04:36:06 PM PDT 24
Peak memory 182888 kb
Host smart-568d674c-1f76-40eb-be8f-64e733fbb68f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431819628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3431819628
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.3388490913
Short name T51
Test name
Test status
Simulation time 1067867611982 ps
CPU time 353.53 seconds
Started Jul 15 04:29:42 PM PDT 24
Finished Jul 15 04:35:37 PM PDT 24
Peak memory 191104 kb
Host smart-0474d7c8-1b36-4a15-81f3-c9c3419b58e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388490913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all
.3388490913
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_random.4174092706
Short name T331
Test name
Test status
Simulation time 227545988223 ps
CPU time 204.41 seconds
Started Jul 15 04:29:34 PM PDT 24
Finished Jul 15 04:32:59 PM PDT 24
Peak memory 191116 kb
Host smart-0c8c415b-0c8d-47cf-b860-0e7b5a3472f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174092706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.4174092706
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/150.rv_timer_random.3940142233
Short name T269
Test name
Test status
Simulation time 47000218790 ps
CPU time 276.88 seconds
Started Jul 15 04:30:10 PM PDT 24
Finished Jul 15 04:34:48 PM PDT 24
Peak memory 194696 kb
Host smart-08cc1f68-9f61-42d0-88dd-d3bd70353631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940142233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.3940142233
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.2761337790
Short name T111
Test name
Test status
Simulation time 147886612698 ps
CPU time 236.31 seconds
Started Jul 15 04:30:16 PM PDT 24
Finished Jul 15 04:34:14 PM PDT 24
Peak memory 191112 kb
Host smart-9f021154-f01d-4bdd-b536-af7aab8d8156
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761337790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.2761337790
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1018706052
Short name T183
Test name
Test status
Simulation time 438571797916 ps
CPU time 187.37 seconds
Started Jul 15 04:30:09 PM PDT 24
Finished Jul 15 04:33:17 PM PDT 24
Peak memory 191108 kb
Host smart-00d65f1b-68b5-4c93-89fb-710adb2be337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018706052 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1018706052
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.931648946
Short name T304
Test name
Test status
Simulation time 363478218511 ps
CPU time 255.85 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:34:31 PM PDT 24
Peak memory 191120 kb
Host smart-88c1011f-13fa-4e0d-ac35-bf6cae520242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931648946 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.931648946
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.1565003746
Short name T151
Test name
Test status
Simulation time 79456967802 ps
CPU time 241.74 seconds
Started Jul 15 04:30:06 PM PDT 24
Finished Jul 15 04:34:09 PM PDT 24
Peak memory 191108 kb
Host smart-76b39b35-8193-4bfa-ac41-4c4d2d5eab8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565003746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.1565003746
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.4238063284
Short name T4
Test name
Test status
Simulation time 1520475521120 ps
CPU time 669.22 seconds
Started Jul 15 04:30:24 PM PDT 24
Finished Jul 15 04:41:35 PM PDT 24
Peak memory 191100 kb
Host smart-312933df-97d6-4927-a1ae-95ad9eb57de0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238063284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.4238063284
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.1788670160
Short name T240
Test name
Test status
Simulation time 611408764112 ps
CPU time 53.02 seconds
Started Jul 15 04:30:22 PM PDT 24
Finished Jul 15 04:31:16 PM PDT 24
Peak memory 183248 kb
Host smart-9df6e367-4819-4c65-9a47-181144c70c96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788670160 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.1788670160
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3878574225
Short name T275
Test name
Test status
Simulation time 77171696274 ps
CPU time 234.34 seconds
Started Jul 15 04:30:13 PM PDT 24
Finished Jul 15 04:34:10 PM PDT 24
Peak memory 191108 kb
Host smart-8d24e6cf-2fee-4d2d-a796-a9c4bd35db49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878574225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3878574225
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1351197634
Short name T177
Test name
Test status
Simulation time 288526089877 ps
CPU time 454.51 seconds
Started Jul 15 04:29:28 PM PDT 24
Finished Jul 15 04:37:04 PM PDT 24
Peak memory 182900 kb
Host smart-3e7cb21b-4cac-41e6-846d-02159d177525
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351197634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1351197634
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.3644951403
Short name T146
Test name
Test status
Simulation time 24109087670 ps
CPU time 39.69 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:30:34 PM PDT 24
Peak memory 182840 kb
Host smart-af23e092-b4cc-4656-a89c-4ebd733e260e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644951403 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.3644951403
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_random.1145544798
Short name T21
Test name
Test status
Simulation time 154711955116 ps
CPU time 62.81 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:30:52 PM PDT 24
Peak memory 193536 kb
Host smart-0b58ea77-9114-4085-9512-f4167154a974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145544798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.1145544798
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.372406763
Short name T157
Test name
Test status
Simulation time 1364997832674 ps
CPU time 2610.11 seconds
Started Jul 15 04:29:46 PM PDT 24
Finished Jul 15 05:13:19 PM PDT 24
Peak memory 195032 kb
Host smart-a1b16ea9-98c0-4e58-b98f-09c140871cbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372406763 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
372406763
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_random.3852081265
Short name T217
Test name
Test status
Simulation time 67245811134 ps
CPU time 121.45 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:31:55 PM PDT 24
Peak memory 191024 kb
Host smart-a28c67ac-6707-4e72-ac56-67bd83129820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852081265 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3852081265
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.414633149
Short name T351
Test name
Test status
Simulation time 125114668450 ps
CPU time 62.32 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:30:58 PM PDT 24
Peak memory 191068 kb
Host smart-1965c75d-f301-433c-a884-136519c98428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414633149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.414633149
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1236967607
Short name T9
Test name
Test status
Simulation time 174214715716 ps
CPU time 237.69 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 04:33:48 PM PDT 24
Peak memory 182884 kb
Host smart-f53c5c71-6a48-4d79-b9b0-38040a61f861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236967607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1236967607
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.4109954979
Short name T294
Test name
Test status
Simulation time 5964932475 ps
CPU time 9.19 seconds
Started Jul 15 04:29:56 PM PDT 24
Finished Jul 15 04:30:06 PM PDT 24
Peak memory 182892 kb
Host smart-87d40a12-6801-4ba8-bac1-ea732f061cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109954979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.4109954979
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.943731219
Short name T56
Test name
Test status
Simulation time 290816521157 ps
CPU time 505.2 seconds
Started Jul 15 04:30:06 PM PDT 24
Finished Jul 15 04:38:33 PM PDT 24
Peak memory 195596 kb
Host smart-800871fb-8622-490a-a57b-81b0966720e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943731219 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all.
943731219
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/56.rv_timer_random.3175794545
Short name T65
Test name
Test status
Simulation time 54450439102 ps
CPU time 281.29 seconds
Started Jul 15 04:30:07 PM PDT 24
Finished Jul 15 04:34:55 PM PDT 24
Peak memory 191088 kb
Host smart-bc95539d-2880-48fc-8af4-c68d69127b13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175794545 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3175794545
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/61.rv_timer_random.583540664
Short name T224
Test name
Test status
Simulation time 499347939891 ps
CPU time 1009.55 seconds
Started Jul 15 04:30:09 PM PDT 24
Finished Jul 15 04:47:01 PM PDT 24
Peak memory 191104 kb
Host smart-72b46fad-fa9f-40f2-9a82-6dda24882304
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583540664 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.583540664
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.1077440021
Short name T142
Test name
Test status
Simulation time 243889437661 ps
CPU time 1196.7 seconds
Started Jul 15 04:30:01 PM PDT 24
Finished Jul 15 04:49:59 PM PDT 24
Peak memory 191112 kb
Host smart-4f4cc0e3-885d-43af-8254-1b0ae79a0611
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077440021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.1077440021
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.2176640230
Short name T355
Test name
Test status
Simulation time 78522245157 ps
CPU time 117.03 seconds
Started Jul 15 04:29:54 PM PDT 24
Finished Jul 15 04:31:53 PM PDT 24
Peak memory 193316 kb
Host smart-aadf8975-08e0-467a-93a9-ca0fbfb30c69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176640230 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.2176640230
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.3088612302
Short name T239
Test name
Test status
Simulation time 63917696894 ps
CPU time 27.82 seconds
Started Jul 15 04:29:36 PM PDT 24
Finished Jul 15 04:30:06 PM PDT 24
Peak memory 182868 kb
Host smart-357cdbd7-ed79-49d1-ac67-afd2ba7ebd64
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088612302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.3088612302
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.4084876853
Short name T86
Test name
Test status
Simulation time 16380718 ps
CPU time 0.77 seconds
Started Jul 15 04:50:37 PM PDT 24
Finished Jul 15 04:50:39 PM PDT 24
Peak memory 182204 kb
Host smart-e1a14584-74c6-4c56-a8df-586336e6aac1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084876853 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.4084876853
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3360682167
Short name T511
Test name
Test status
Simulation time 738026923 ps
CPU time 2.79 seconds
Started Jul 15 04:50:31 PM PDT 24
Finished Jul 15 04:50:35 PM PDT 24
Peak memory 190512 kb
Host smart-801469fa-b46a-4327-8f9b-ecb74aa99f6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360682167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3360682167
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.555292879
Short name T33
Test name
Test status
Simulation time 15243785 ps
CPU time 0.56 seconds
Started Jul 15 04:50:45 PM PDT 24
Finished Jul 15 04:50:47 PM PDT 24
Peak memory 182096 kb
Host smart-e3784364-cbef-4f78-9615-ffd7b3263cf1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555292879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.555292879
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.264798814
Short name T504
Test name
Test status
Simulation time 30744796 ps
CPU time 0.89 seconds
Started Jul 15 04:50:37 PM PDT 24
Finished Jul 15 04:50:39 PM PDT 24
Peak memory 196344 kb
Host smart-6ddafbe9-83c7-40cb-9c84-c4bbcee6e504
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264798814 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.264798814
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.3546533640
Short name T43
Test name
Test status
Simulation time 27625192 ps
CPU time 0.58 seconds
Started Jul 15 04:50:37 PM PDT 24
Finished Jul 15 04:50:38 PM PDT 24
Peak memory 182220 kb
Host smart-f0c0df52-7f79-4146-ac72-c6cf39b2595e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546533640 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.3546533640
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3176613964
Short name T566
Test name
Test status
Simulation time 17421684 ps
CPU time 0.55 seconds
Started Jul 15 04:50:35 PM PDT 24
Finished Jul 15 04:50:37 PM PDT 24
Peak memory 182128 kb
Host smart-2ebf0dad-670c-46d0-ab17-5985512f7573
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176613964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3176613964
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1636667577
Short name T484
Test name
Test status
Simulation time 245413968 ps
CPU time 0.76 seconds
Started Jul 15 04:50:35 PM PDT 24
Finished Jul 15 04:50:36 PM PDT 24
Peak memory 192896 kb
Host smart-927b3091-28c1-4096-a6d5-76fc19bf03d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636667577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1636667577
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3256022985
Short name T461
Test name
Test status
Simulation time 48837601 ps
CPU time 1.3 seconds
Started Jul 15 04:50:32 PM PDT 24
Finished Jul 15 04:50:34 PM PDT 24
Peak memory 196960 kb
Host smart-2de190e6-40f6-4aa6-b947-f3d2f506f7f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256022985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3256022985
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.1593141345
Short name T98
Test name
Test status
Simulation time 52658945 ps
CPU time 0.85 seconds
Started Jul 15 04:50:40 PM PDT 24
Finished Jul 15 04:50:42 PM PDT 24
Peak memory 193124 kb
Host smart-3eaa0aaa-0e72-4721-84e8-bb230a061c9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593141345 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.1593141345
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.3162656903
Short name T92
Test name
Test status
Simulation time 658367653 ps
CPU time 3.6 seconds
Started Jul 15 04:50:45 PM PDT 24
Finished Jul 15 04:50:50 PM PDT 24
Peak memory 193336 kb
Host smart-b375f71a-ff87-429d-9d11-8c1b6eaa8f2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162656903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.3162656903
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.3631226081
Short name T514
Test name
Test status
Simulation time 18414584 ps
CPU time 0.61 seconds
Started Jul 15 04:50:37 PM PDT 24
Finished Jul 15 04:50:40 PM PDT 24
Peak memory 182236 kb
Host smart-a4cb8ca9-6f44-4724-9c74-792ef4eaa079
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631226081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_r
eset.3631226081
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.740656217
Short name T503
Test name
Test status
Simulation time 150217133 ps
CPU time 0.76 seconds
Started Jul 15 04:50:39 PM PDT 24
Finished Jul 15 04:50:40 PM PDT 24
Peak memory 194816 kb
Host smart-9c869027-8dfc-485f-a889-c42f11fa1731
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740656217 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.740656217
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3083574217
Short name T91
Test name
Test status
Simulation time 44679978 ps
CPU time 0.6 seconds
Started Jul 15 04:50:40 PM PDT 24
Finished Jul 15 04:50:42 PM PDT 24
Peak memory 181996 kb
Host smart-f971be71-6f4c-43ba-b89a-3dea4eb9a7dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083574217 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3083574217
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.474130679
Short name T492
Test name
Test status
Simulation time 37439353 ps
CPU time 0.54 seconds
Started Jul 15 04:50:40 PM PDT 24
Finished Jul 15 04:50:41 PM PDT 24
Peak memory 181512 kb
Host smart-c183b29c-be91-40c9-b70d-b15ea5eb2e56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474130679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.474130679
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.399174542
Short name T481
Test name
Test status
Simulation time 36846953 ps
CPU time 0.68 seconds
Started Jul 15 04:50:38 PM PDT 24
Finished Jul 15 04:50:40 PM PDT 24
Peak memory 191564 kb
Host smart-b9bb851c-682f-4147-9dee-9712ac106603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399174542 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_tim
er_same_csr_outstanding.399174542
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3516486386
Short name T463
Test name
Test status
Simulation time 34714094 ps
CPU time 1.12 seconds
Started Jul 15 04:50:48 PM PDT 24
Finished Jul 15 04:50:51 PM PDT 24
Peak memory 196644 kb
Host smart-0d5ddcd8-479a-4117-bbfc-1daeec6ea556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516486386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3516486386
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4071983998
Short name T570
Test name
Test status
Simulation time 140500299 ps
CPU time 0.84 seconds
Started Jul 15 04:50:35 PM PDT 24
Finished Jul 15 04:50:37 PM PDT 24
Peak memory 193284 kb
Host smart-e2b45f35-555f-4334-a1c1-71904ff644f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071983998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.4071983998
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.1116083977
Short name T506
Test name
Test status
Simulation time 25073920 ps
CPU time 0.84 seconds
Started Jul 15 04:50:46 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 195092 kb
Host smart-fb193a13-d7e3-44a6-ba55-a7c347b6cf11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116083977 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.1116083977
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.1778137459
Short name T551
Test name
Test status
Simulation time 54668212 ps
CPU time 0.54 seconds
Started Jul 15 04:50:43 PM PDT 24
Finished Jul 15 04:50:45 PM PDT 24
Peak memory 181636 kb
Host smart-5f65c397-a96a-4354-8b0c-6063745a1d03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778137459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.1778137459
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.4022201302
Short name T558
Test name
Test status
Simulation time 31387524 ps
CPU time 0.57 seconds
Started Jul 15 04:50:45 PM PDT 24
Finished Jul 15 04:50:47 PM PDT 24
Peak memory 182052 kb
Host smart-3be13b89-677e-43bd-a541-41efc72c34a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022201302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.4022201302
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.684758350
Short name T533
Test name
Test status
Simulation time 37775616 ps
CPU time 0.78 seconds
Started Jul 15 04:50:43 PM PDT 24
Finished Jul 15 04:50:46 PM PDT 24
Peak memory 192624 kb
Host smart-2c9b906a-a8c6-4505-a4a8-f7cbe88fb84d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684758350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_ti
mer_same_csr_outstanding.684758350
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.1004621686
Short name T569
Test name
Test status
Simulation time 114379501 ps
CPU time 2.92 seconds
Started Jul 15 04:50:47 PM PDT 24
Finished Jul 15 04:50:52 PM PDT 24
Peak memory 196944 kb
Host smart-ec7aca97-db5d-457d-862c-28cdab4349bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004621686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.1004621686
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2640065678
Short name T476
Test name
Test status
Simulation time 87431590 ps
CPU time 0.86 seconds
Started Jul 15 04:50:46 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 182724 kb
Host smart-33181860-89a6-4b7f-95a3-174ba6a32094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640065678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2640065678
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3466843481
Short name T39
Test name
Test status
Simulation time 49343374 ps
CPU time 1.18 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 196932 kb
Host smart-c4433152-b29a-467b-b7f6-6989e27fa6cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466843481 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3466843481
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.4168016575
Short name T42
Test name
Test status
Simulation time 39532474 ps
CPU time 0.59 seconds
Started Jul 15 04:50:51 PM PDT 24
Finished Jul 15 04:50:52 PM PDT 24
Peak memory 182152 kb
Host smart-3c01d9fc-8444-464e-9999-a085f4b1995d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168016575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.4168016575
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.3475334418
Short name T541
Test name
Test status
Simulation time 23177431 ps
CPU time 0.51 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:54 PM PDT 24
Peak memory 181512 kb
Host smart-8332eb20-4cf7-4f53-a16f-ec790f7fcff1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475334418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.3475334418
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.1478161583
Short name T536
Test name
Test status
Simulation time 71025242 ps
CPU time 0.85 seconds
Started Jul 15 04:50:56 PM PDT 24
Finished Jul 15 04:50:59 PM PDT 24
Peak memory 190400 kb
Host smart-c77a04f7-dac7-4599-ad7a-763dd4be05f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478161583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.1478161583
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2486152741
Short name T575
Test name
Test status
Simulation time 512630998 ps
CPU time 1.75 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 196936 kb
Host smart-580097c0-8bf9-41aa-8455-e50a60945cf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486152741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2486152741
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.1481116311
Short name T522
Test name
Test status
Simulation time 147633073 ps
CPU time 0.8 seconds
Started Jul 15 04:50:47 PM PDT 24
Finished Jul 15 04:50:50 PM PDT 24
Peak memory 193000 kb
Host smart-986ffd47-3245-44cb-b549-3c4ba896d9da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481116311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.1481116311
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.957078763
Short name T50
Test name
Test status
Simulation time 69779372 ps
CPU time 0.7 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 193576 kb
Host smart-8bd1bd55-85af-4666-bb08-881ffd490ccb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957078763 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.957078763
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.210846647
Short name T81
Test name
Test status
Simulation time 72834044 ps
CPU time 0.6 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:54 PM PDT 24
Peak memory 182164 kb
Host smart-c6ae33b7-eae2-4475-bb6d-7cd7ae1a4a72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210846647 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.210846647
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.1757541474
Short name T565
Test name
Test status
Simulation time 11701312 ps
CPU time 0.54 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 181552 kb
Host smart-9122c2c2-dcf8-49b4-9007-d37ac0877afa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757541474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.1757541474
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1067944101
Short name T512
Test name
Test status
Simulation time 36999829 ps
CPU time 1.78 seconds
Started Jul 15 04:50:53 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 196968 kb
Host smart-d43114ba-a2b9-4cc2-87d7-29f9d57396e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067944101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1067944101
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.493153059
Short name T459
Test name
Test status
Simulation time 158574008 ps
CPU time 0.76 seconds
Started Jul 15 04:50:54 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 194592 kb
Host smart-5128e2a8-41f7-4bdb-97b9-884dce5aa77e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493153059 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.493153059
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3773529525
Short name T31
Test name
Test status
Simulation time 74416228 ps
CPU time 0.56 seconds
Started Jul 15 04:50:55 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 182176 kb
Host smart-5ae3bc9d-2746-41fb-a349-8c198df649fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773529525 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3773529525
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.2257858560
Short name T568
Test name
Test status
Simulation time 102118662 ps
CPU time 0.55 seconds
Started Jul 15 04:51:01 PM PDT 24
Finished Jul 15 04:51:04 PM PDT 24
Peak memory 182092 kb
Host smart-39ff1db0-75b1-4efa-b18e-02571e5baa91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257858560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.2257858560
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1547174122
Short name T563
Test name
Test status
Simulation time 34624917 ps
CPU time 0.76 seconds
Started Jul 15 04:50:55 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 192596 kb
Host smart-d0c63347-e01a-46e7-94b3-5cb6815b090a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547174122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1547174122
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.2468660437
Short name T505
Test name
Test status
Simulation time 180238465 ps
CPU time 1.9 seconds
Started Jul 15 04:50:53 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 196888 kb
Host smart-a561ef26-42fb-40f0-8f28-b251edd67219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468660437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.2468660437
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3867188760
Short name T99
Test name
Test status
Simulation time 307634175 ps
CPU time 1.08 seconds
Started Jul 15 04:50:53 PM PDT 24
Finished Jul 15 04:50:56 PM PDT 24
Peak memory 194368 kb
Host smart-d8d0dd35-1e62-4171-9f26-b6586224d114
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867188760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3867188760
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1679519325
Short name T45
Test name
Test status
Simulation time 23993352 ps
CPU time 0.75 seconds
Started Jul 15 04:50:57 PM PDT 24
Finished Jul 15 04:50:59 PM PDT 24
Peak memory 193536 kb
Host smart-84c5434b-4336-404e-86fc-6af386bda6bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679519325 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1679519325
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.1444397114
Short name T542
Test name
Test status
Simulation time 142542600 ps
CPU time 0.53 seconds
Started Jul 15 04:50:57 PM PDT 24
Finished Jul 15 04:50:59 PM PDT 24
Peak memory 181876 kb
Host smart-a744a705-add7-4f7a-878e-282fd23fc066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444397114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.1444397114
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3894222357
Short name T466
Test name
Test status
Simulation time 13499769 ps
CPU time 0.57 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 182036 kb
Host smart-b97d01ea-adc8-4caa-ac54-1924973310f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894222357 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3894222357
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.2921694507
Short name T535
Test name
Test status
Simulation time 51844869 ps
CPU time 0.74 seconds
Started Jul 15 04:50:54 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 192724 kb
Host smart-2bc689da-bfe0-4526-9b04-f323fa48de36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921694507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.2921694507
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.2540426969
Short name T70
Test name
Test status
Simulation time 188244767 ps
CPU time 1.53 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 196944 kb
Host smart-566f92b7-6ccb-4404-969f-0e96cdc72ded
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540426969 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.2540426969
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.2595958033
Short name T102
Test name
Test status
Simulation time 1336848176 ps
CPU time 1.08 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 193648 kb
Host smart-3dd8be57-bf14-4afd-bdb8-9da060cfa256
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595958033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.2595958033
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2151071753
Short name T469
Test name
Test status
Simulation time 41985300 ps
CPU time 0.99 seconds
Started Jul 15 04:50:54 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 196188 kb
Host smart-aee65f5a-bfd2-4d5b-8cd7-8de341e64735
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151071753 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2151071753
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.3656859134
Short name T453
Test name
Test status
Simulation time 13790246 ps
CPU time 0.55 seconds
Started Jul 15 04:50:58 PM PDT 24
Finished Jul 15 04:51:00 PM PDT 24
Peak memory 182184 kb
Host smart-53a59a58-63b4-4acc-9986-26d177f3385f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656859134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.3656859134
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3802857045
Short name T543
Test name
Test status
Simulation time 56594487 ps
CPU time 0.57 seconds
Started Jul 15 04:51:01 PM PDT 24
Finished Jul 15 04:51:04 PM PDT 24
Peak memory 181992 kb
Host smart-a61aadaf-d4af-4a63-b910-c0f5ad74938d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802857045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3802857045
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3649644233
Short name T47
Test name
Test status
Simulation time 23204910 ps
CPU time 0.62 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 191356 kb
Host smart-d8ab1529-ce3a-4a0a-8175-9a2badaccf40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649644233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3649644233
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1418023527
Short name T521
Test name
Test status
Simulation time 89628896 ps
CPU time 1.53 seconds
Started Jul 15 04:50:57 PM PDT 24
Finished Jul 15 04:51:01 PM PDT 24
Peak memory 196880 kb
Host smart-280f463d-b3c3-46be-9977-69b06e050490
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418023527 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1418023527
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.748873732
Short name T101
Test name
Test status
Simulation time 390749101 ps
CPU time 1.08 seconds
Started Jul 15 04:50:57 PM PDT 24
Finished Jul 15 04:51:00 PM PDT 24
Peak memory 194588 kb
Host smart-c3c87c0f-7d28-4471-bf3e-6b1d81f0a456
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748873732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_in
tg_err.748873732
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3142931943
Short name T487
Test name
Test status
Simulation time 96094987 ps
CPU time 1.27 seconds
Started Jul 15 04:50:58 PM PDT 24
Finished Jul 15 04:51:07 PM PDT 24
Peak memory 196960 kb
Host smart-043ea29d-33a1-427c-833c-cf59491c3695
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142931943 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3142931943
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.1451513537
Short name T93
Test name
Test status
Simulation time 33159072 ps
CPU time 0.52 seconds
Started Jul 15 04:50:51 PM PDT 24
Finished Jul 15 04:50:53 PM PDT 24
Peak memory 182008 kb
Host smart-09d8e40e-e6e3-4131-baf1-9058a18f3abc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451513537 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.1451513537
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2287043475
Short name T571
Test name
Test status
Simulation time 46227477 ps
CPU time 0.56 seconds
Started Jul 15 04:51:03 PM PDT 24
Finished Jul 15 04:51:05 PM PDT 24
Peak memory 181492 kb
Host smart-bc973abf-4303-485e-8ca0-9c5fbfbb0ecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287043475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2287043475
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.2118596284
Short name T95
Test name
Test status
Simulation time 65223597 ps
CPU time 0.8 seconds
Started Jul 15 04:50:56 PM PDT 24
Finished Jul 15 04:50:59 PM PDT 24
Peak memory 192732 kb
Host smart-f2352b64-ed68-4bc4-9202-7de1596697b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118596284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.2118596284
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2374303655
Short name T501
Test name
Test status
Simulation time 217172273 ps
CPU time 3.7 seconds
Started Jul 15 04:50:50 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 196920 kb
Host smart-358a4b9b-493d-426f-8aa5-67f369f1727b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374303655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2374303655
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.1606420483
Short name T526
Test name
Test status
Simulation time 605953329 ps
CPU time 1.47 seconds
Started Jul 15 04:50:54 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 194616 kb
Host smart-b8600267-90a8-42ed-adfc-64d97b3f6d13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606420483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.1606420483
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2180449379
Short name T545
Test name
Test status
Simulation time 17471969 ps
CPU time 0.74 seconds
Started Jul 15 04:50:53 PM PDT 24
Finished Jul 15 04:50:56 PM PDT 24
Peak memory 194108 kb
Host smart-73f48c36-f7a2-4145-9066-bb95f42988f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180449379 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2180449379
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.1650510446
Short name T520
Test name
Test status
Simulation time 43710654 ps
CPU time 0.54 seconds
Started Jul 15 04:50:56 PM PDT 24
Finished Jul 15 04:50:59 PM PDT 24
Peak memory 182148 kb
Host smart-0e45d15a-b0d6-47d7-9aa8-851d0408a80f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650510446 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.1650510446
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.3316980420
Short name T468
Test name
Test status
Simulation time 95824443 ps
CPU time 0.58 seconds
Started Jul 15 04:50:55 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 182064 kb
Host smart-39a8146e-c32a-4b4b-9e8c-bca5ba026ec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316980420 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.3316980420
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3587996066
Short name T80
Test name
Test status
Simulation time 45231075 ps
CPU time 0.59 seconds
Started Jul 15 04:50:58 PM PDT 24
Finished Jul 15 04:51:01 PM PDT 24
Peak memory 190876 kb
Host smart-8cfb17b3-cc0a-4456-be5d-1dacf59928ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587996066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3587996066
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.361046004
Short name T547
Test name
Test status
Simulation time 63578241 ps
CPU time 1.3 seconds
Started Jul 15 04:50:58 PM PDT 24
Finished Jul 15 04:51:02 PM PDT 24
Peak memory 196968 kb
Host smart-31321657-44dc-4a2b-bfc5-511fdc2561f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361046004 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.361046004
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1664444276
Short name T464
Test name
Test status
Simulation time 88294902 ps
CPU time 0.89 seconds
Started Jul 15 04:50:53 PM PDT 24
Finished Jul 15 04:50:56 PM PDT 24
Peak memory 192172 kb
Host smart-ae52ad26-343c-4d4f-8b09-6cbfe0093d27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664444276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.1664444276
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.245543229
Short name T550
Test name
Test status
Simulation time 73911354 ps
CPU time 0.97 seconds
Started Jul 15 04:51:13 PM PDT 24
Finished Jul 15 04:51:15 PM PDT 24
Peak memory 196808 kb
Host smart-1e0933af-1017-4897-8251-6355b4ffdad8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245543229 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.245543229
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.3789158154
Short name T83
Test name
Test status
Simulation time 23873724 ps
CPU time 0.59 seconds
Started Jul 15 04:50:54 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 182160 kb
Host smart-900aa382-6cac-4ac3-b01d-47afd5e88f56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789158154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.3789158154
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1067616557
Short name T494
Test name
Test status
Simulation time 32357395 ps
CPU time 0.56 seconds
Started Jul 15 04:50:55 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 181704 kb
Host smart-ba394c70-028c-4eee-84fa-c65bbe847a54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067616557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1067616557
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.839317830
Short name T94
Test name
Test status
Simulation time 35296005 ps
CPU time 0.62 seconds
Started Jul 15 04:50:51 PM PDT 24
Finished Jul 15 04:50:53 PM PDT 24
Peak memory 190772 kb
Host smart-162a8205-f261-4f95-ad83-d3fd01741bb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839317830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.839317830
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.1563628744
Short name T480
Test name
Test status
Simulation time 78817360 ps
CPU time 1.74 seconds
Started Jul 15 04:50:51 PM PDT 24
Finished Jul 15 04:50:54 PM PDT 24
Peak memory 197008 kb
Host smart-d58fce6d-b421-4981-8385-bc46304d4fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563628744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.1563628744
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.2375849463
Short name T496
Test name
Test status
Simulation time 115839068 ps
CPU time 1.42 seconds
Started Jul 15 04:50:53 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 194760 kb
Host smart-9d9874d9-494c-4315-a0e9-e288892ed0f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375849463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.2375849463
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.647235746
Short name T532
Test name
Test status
Simulation time 63911898 ps
CPU time 0.65 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 193764 kb
Host smart-29c38555-5e2a-4d93-9218-c2edc5313497
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647235746 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.647235746
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.4093702046
Short name T90
Test name
Test status
Simulation time 17529311 ps
CPU time 0.59 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:55 PM PDT 24
Peak memory 182168 kb
Host smart-011ab342-f20b-4a8f-b2c0-97eb8bf482a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093702046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.4093702046
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.538734418
Short name T502
Test name
Test status
Simulation time 71627357 ps
CPU time 0.57 seconds
Started Jul 15 04:50:53 PM PDT 24
Finished Jul 15 04:50:56 PM PDT 24
Peak memory 182020 kb
Host smart-08e16820-af4b-4f1a-aca0-43094f0947f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538734418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.538734418
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.2256080987
Short name T574
Test name
Test status
Simulation time 19871503 ps
CPU time 0.73 seconds
Started Jul 15 04:50:58 PM PDT 24
Finished Jul 15 04:51:01 PM PDT 24
Peak memory 192824 kb
Host smart-abd21087-6eae-47c5-af98-aeeb000b651b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256080987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.2256080987
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2625067995
Short name T462
Test name
Test status
Simulation time 535687677 ps
CPU time 2.59 seconds
Started Jul 15 04:50:53 PM PDT 24
Finished Jul 15 04:50:58 PM PDT 24
Peak memory 196988 kb
Host smart-eb80bbc4-8a22-4fb9-bf71-c8d9cbde514c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625067995 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2625067995
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1902415427
Short name T546
Test name
Test status
Simulation time 30658543 ps
CPU time 0.73 seconds
Started Jul 15 04:50:45 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 182096 kb
Host smart-e09772f9-efd6-4e2f-93db-f9a839c68449
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902415427 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1902415427
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.1615168993
Short name T493
Test name
Test status
Simulation time 88554510 ps
CPU time 3.09 seconds
Started Jul 15 04:50:38 PM PDT 24
Finished Jul 15 04:50:42 PM PDT 24
Peak memory 190512 kb
Host smart-6fc4fa4d-40dc-4b5a-8c0c-3966ff3c3cce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615168993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.1615168993
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1612844095
Short name T87
Test name
Test status
Simulation time 22385886 ps
CPU time 0.57 seconds
Started Jul 15 04:50:45 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 182096 kb
Host smart-fc3655c0-263a-4c3a-a20f-85a6b1b919b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612844095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1612844095
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3303885088
Short name T479
Test name
Test status
Simulation time 76234492 ps
CPU time 0.75 seconds
Started Jul 15 04:50:48 PM PDT 24
Finished Jul 15 04:50:50 PM PDT 24
Peak memory 194900 kb
Host smart-fe6b6af6-6163-44ac-ac5f-b53045279ce0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303885088 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3303885088
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.3172069429
Short name T523
Test name
Test status
Simulation time 13646109 ps
CPU time 0.61 seconds
Started Jul 15 04:50:36 PM PDT 24
Finished Jul 15 04:50:37 PM PDT 24
Peak memory 182172 kb
Host smart-ed8f695a-4a50-414e-84ba-018d3a98fb10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172069429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.3172069429
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.2592878620
Short name T477
Test name
Test status
Simulation time 30580272 ps
CPU time 0.56 seconds
Started Jul 15 04:50:40 PM PDT 24
Finished Jul 15 04:50:41 PM PDT 24
Peak memory 182032 kb
Host smart-638f9226-424e-4a44-a3cd-25414599b36e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592878620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.2592878620
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.2780885908
Short name T517
Test name
Test status
Simulation time 49162157 ps
CPU time 0.73 seconds
Started Jul 15 04:50:37 PM PDT 24
Finished Jul 15 04:50:39 PM PDT 24
Peak memory 192564 kb
Host smart-196a208e-922a-4152-8fcb-e4da336ace0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780885908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.2780885908
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1103124801
Short name T519
Test name
Test status
Simulation time 25717759 ps
CPU time 1.27 seconds
Started Jul 15 04:50:35 PM PDT 24
Finished Jul 15 04:50:37 PM PDT 24
Peak memory 196628 kb
Host smart-9a4a61fa-c27d-48e1-8dbb-2b9edcbfa9bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103124801 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1103124801
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.2304649406
Short name T552
Test name
Test status
Simulation time 608419898 ps
CPU time 1.36 seconds
Started Jul 15 04:50:36 PM PDT 24
Finished Jul 15 04:50:38 PM PDT 24
Peak memory 193976 kb
Host smart-a8ae6cdd-f81b-4921-96b5-9d6b54cb9335
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304649406 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.2304649406
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.1154321669
Short name T561
Test name
Test status
Simulation time 47780684 ps
CPU time 0.57 seconds
Started Jul 15 04:50:49 PM PDT 24
Finished Jul 15 04:50:51 PM PDT 24
Peak memory 182144 kb
Host smart-0b399b44-0abe-4d99-8058-e6adffa062de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154321669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.1154321669
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.327285382
Short name T539
Test name
Test status
Simulation time 32696158 ps
CPU time 0.55 seconds
Started Jul 15 04:50:56 PM PDT 24
Finished Jul 15 04:50:58 PM PDT 24
Peak memory 181532 kb
Host smart-6b1fb9f8-773a-4e02-94f6-a5697f942b59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327285382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.327285382
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.738612877
Short name T485
Test name
Test status
Simulation time 51669284 ps
CPU time 0.58 seconds
Started Jul 15 04:50:51 PM PDT 24
Finished Jul 15 04:50:52 PM PDT 24
Peak memory 182092 kb
Host smart-1ef638a2-b40e-43c4-b562-7a89d4ecf232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738612877 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.738612877
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2476620307
Short name T513
Test name
Test status
Simulation time 24413109 ps
CPU time 0.6 seconds
Started Jul 15 04:50:57 PM PDT 24
Finished Jul 15 04:51:00 PM PDT 24
Peak memory 182124 kb
Host smart-a2051529-361d-45dd-8088-d685ca879e1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476620307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2476620307
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.165156587
Short name T452
Test name
Test status
Simulation time 33310981 ps
CPU time 0.57 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:54 PM PDT 24
Peak memory 182056 kb
Host smart-3b3d66cf-4488-414c-b256-c979f79951b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165156587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.165156587
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2629538967
Short name T528
Test name
Test status
Simulation time 15610458 ps
CPU time 0.57 seconds
Started Jul 15 04:50:52 PM PDT 24
Finished Jul 15 04:50:54 PM PDT 24
Peak memory 182044 kb
Host smart-bbcf808c-2fed-44f6-87b0-c24d9115e62b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629538967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2629538967
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.1355360751
Short name T456
Test name
Test status
Simulation time 38289088 ps
CPU time 0.54 seconds
Started Jul 15 04:50:55 PM PDT 24
Finished Jul 15 04:50:57 PM PDT 24
Peak memory 181552 kb
Host smart-a917f0cb-047b-4581-8144-97146df641d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355360751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.1355360751
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.1457295250
Short name T498
Test name
Test status
Simulation time 35683195 ps
CPU time 0.57 seconds
Started Jul 15 04:50:51 PM PDT 24
Finished Jul 15 04:50:52 PM PDT 24
Peak memory 181392 kb
Host smart-dc642cbe-95b0-440f-95e3-2896ea5bfd68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457295250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.1457295250
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1470110866
Short name T544
Test name
Test status
Simulation time 30398559 ps
CPU time 0.56 seconds
Started Jul 15 04:51:01 PM PDT 24
Finished Jul 15 04:51:04 PM PDT 24
Peak memory 182088 kb
Host smart-5d6fadbd-316f-46f4-a5d7-2196b7fc9d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470110866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1470110866
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.3108363578
Short name T483
Test name
Test status
Simulation time 53710473 ps
CPU time 0.6 seconds
Started Jul 15 04:50:51 PM PDT 24
Finished Jul 15 04:50:52 PM PDT 24
Peak memory 181956 kb
Host smart-8c336257-b177-4709-86be-55cc9d28b1cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108363578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.3108363578
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3249746591
Short name T85
Test name
Test status
Simulation time 263398228 ps
CPU time 0.72 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:47 PM PDT 24
Peak memory 182192 kb
Host smart-e81ea4e7-8b0b-4f5e-a57b-6036d891f5bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249746591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3249746591
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.1435026922
Short name T89
Test name
Test status
Simulation time 600813608 ps
CPU time 3.42 seconds
Started Jul 15 04:50:36 PM PDT 24
Finished Jul 15 04:50:40 PM PDT 24
Peak memory 193460 kb
Host smart-8c88ea6a-236a-4567-b97b-16cc62eec5ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435026922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.1435026922
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.3929975618
Short name T88
Test name
Test status
Simulation time 15537642 ps
CPU time 0.6 seconds
Started Jul 15 04:50:48 PM PDT 24
Finished Jul 15 04:50:50 PM PDT 24
Peak memory 182196 kb
Host smart-b208f36b-7909-45b1-8df8-379ddf01515a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929975618 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_r
eset.3929975618
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.2060580731
Short name T529
Test name
Test status
Simulation time 35020459 ps
CPU time 0.89 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:47 PM PDT 24
Peak memory 196748 kb
Host smart-4a3565b3-f03b-449f-a13f-0f6fc6920da5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060580731 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.2060580731
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.754283913
Short name T573
Test name
Test status
Simulation time 15134938 ps
CPU time 0.58 seconds
Started Jul 15 04:50:37 PM PDT 24
Finished Jul 15 04:50:39 PM PDT 24
Peak memory 182168 kb
Host smart-bfb9024f-93fe-430f-b8cc-bb8e731acd51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754283913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.754283913
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1227049783
Short name T458
Test name
Test status
Simulation time 29636721 ps
CPU time 0.53 seconds
Started Jul 15 04:50:38 PM PDT 24
Finished Jul 15 04:50:40 PM PDT 24
Peak memory 182020 kb
Host smart-194211eb-62c3-4e93-ab53-6491c0cbc997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227049783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1227049783
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4172515247
Short name T530
Test name
Test status
Simulation time 15075366 ps
CPU time 0.71 seconds
Started Jul 15 04:50:42 PM PDT 24
Finished Jul 15 04:50:43 PM PDT 24
Peak memory 192012 kb
Host smart-937c0707-4488-401c-9b8d-2648fb31f8f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172515247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.4172515247
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.1476928754
Short name T555
Test name
Test status
Simulation time 59497491 ps
CPU time 3.17 seconds
Started Jul 15 04:50:48 PM PDT 24
Finished Jul 15 04:50:53 PM PDT 24
Peak memory 196856 kb
Host smart-5f21c3d2-41e6-451c-a319-34bef46c4f91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476928754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.1476928754
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3995709405
Short name T486
Test name
Test status
Simulation time 906081251 ps
CPU time 1.05 seconds
Started Jul 15 04:50:45 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 193236 kb
Host smart-ee8d0f2c-4df0-4fe4-8a7a-d5d288cf1b21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995709405 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3995709405
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.1824329703
Short name T478
Test name
Test status
Simulation time 27288159 ps
CPU time 0.58 seconds
Started Jul 15 04:50:51 PM PDT 24
Finished Jul 15 04:50:52 PM PDT 24
Peak memory 181740 kb
Host smart-580a3e60-e48e-4a46-bff9-414aa0847c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824329703 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.1824329703
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2182938454
Short name T515
Test name
Test status
Simulation time 14651962 ps
CPU time 0.57 seconds
Started Jul 15 04:50:57 PM PDT 24
Finished Jul 15 04:50:59 PM PDT 24
Peak memory 182004 kb
Host smart-712aa379-1fc3-41d4-9042-17fe9c3c3910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182938454 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2182938454
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.3789195831
Short name T467
Test name
Test status
Simulation time 33390440 ps
CPU time 0.57 seconds
Started Jul 15 04:50:55 PM PDT 24
Finished Jul 15 04:50:58 PM PDT 24
Peak memory 182008 kb
Host smart-646cdb50-c2ff-4035-9e5e-7917acf9e468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789195831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.3789195831
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.2129171839
Short name T567
Test name
Test status
Simulation time 36597482 ps
CPU time 0.54 seconds
Started Jul 15 04:51:03 PM PDT 24
Finished Jul 15 04:51:05 PM PDT 24
Peak memory 181476 kb
Host smart-190c2758-dbdc-4dd3-be0e-6884254c826d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129171839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.2129171839
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2181766315
Short name T470
Test name
Test status
Simulation time 49964564 ps
CPU time 0.56 seconds
Started Jul 15 04:50:57 PM PDT 24
Finished Jul 15 04:50:59 PM PDT 24
Peak memory 182064 kb
Host smart-fc49595d-b81d-46d9-8c4b-4e87ad2215fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181766315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2181766315
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2999193528
Short name T537
Test name
Test status
Simulation time 26138419 ps
CPU time 0.58 seconds
Started Jul 15 04:51:02 PM PDT 24
Finished Jul 15 04:51:05 PM PDT 24
Peak memory 182072 kb
Host smart-ecc09581-801b-4f2a-a74f-1f45bf8fd048
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999193528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2999193528
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3478899874
Short name T556
Test name
Test status
Simulation time 29296366 ps
CPU time 0.54 seconds
Started Jul 15 04:51:00 PM PDT 24
Finished Jul 15 04:51:03 PM PDT 24
Peak memory 182052 kb
Host smart-ec7ad55f-6768-477c-b123-99e553431b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478899874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3478899874
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.3383365171
Short name T559
Test name
Test status
Simulation time 12498590 ps
CPU time 0.53 seconds
Started Jul 15 04:51:02 PM PDT 24
Finished Jul 15 04:51:05 PM PDT 24
Peak memory 181548 kb
Host smart-635954e5-a76d-40ce-951b-e259f2222c7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383365171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.3383365171
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.1019786195
Short name T564
Test name
Test status
Simulation time 42474113 ps
CPU time 0.59 seconds
Started Jul 15 04:50:59 PM PDT 24
Finished Jul 15 04:51:03 PM PDT 24
Peak memory 182052 kb
Host smart-fe8a7bfc-990e-4ae2-8a3f-c5c33b752bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019786195 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.1019786195
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.4178685355
Short name T534
Test name
Test status
Simulation time 10654328 ps
CPU time 0.55 seconds
Started Jul 15 04:51:04 PM PDT 24
Finished Jul 15 04:51:06 PM PDT 24
Peak memory 181548 kb
Host smart-baca4934-11e9-44e8-aeec-8dfa05b90885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178685355 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.4178685355
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.306350796
Short name T84
Test name
Test status
Simulation time 52218561 ps
CPU time 0.82 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:47 PM PDT 24
Peak memory 191324 kb
Host smart-9b44a3ac-1945-4ca7-88c7-2feb2438d538
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306350796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alias
ing.306350796
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.400513342
Short name T560
Test name
Test status
Simulation time 492578560 ps
CPU time 2.81 seconds
Started Jul 15 04:50:41 PM PDT 24
Finished Jul 15 04:50:44 PM PDT 24
Peak memory 192956 kb
Host smart-17a66c9f-f797-4e1e-8f09-ca120807caff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400513342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_b
ash.400513342
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.1010548457
Short name T509
Test name
Test status
Simulation time 45467273 ps
CPU time 0.56 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:45 PM PDT 24
Peak memory 182120 kb
Host smart-ba2a7502-34a8-47fe-b654-2a69ad1da0bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010548457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.1010548457
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.3480478886
Short name T474
Test name
Test status
Simulation time 30981831 ps
CPU time 0.8 seconds
Started Jul 15 04:50:48 PM PDT 24
Finished Jul 15 04:50:50 PM PDT 24
Peak memory 194536 kb
Host smart-c14fde66-37ec-4b6a-976e-b08c2ece131f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480478886 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.3480478886
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.733118168
Short name T473
Test name
Test status
Simulation time 21661105 ps
CPU time 0.54 seconds
Started Jul 15 04:50:43 PM PDT 24
Finished Jul 15 04:50:45 PM PDT 24
Peak memory 182160 kb
Host smart-61e44d71-3af5-4f35-bac1-935bff852058
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733118168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.733118168
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1540977163
Short name T465
Test name
Test status
Simulation time 43691336 ps
CPU time 0.59 seconds
Started Jul 15 04:50:47 PM PDT 24
Finished Jul 15 04:50:49 PM PDT 24
Peak memory 182108 kb
Host smart-12b5436e-e41f-466f-a0a1-b0c3b832e398
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540977163 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1540977163
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.4108415540
Short name T44
Test name
Test status
Simulation time 33613200 ps
CPU time 0.76 seconds
Started Jul 15 04:50:46 PM PDT 24
Finished Jul 15 04:50:49 PM PDT 24
Peak memory 192672 kb
Host smart-d29f5f32-4312-4d44-9913-a46597ab783f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108415540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.4108415540
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3789275610
Short name T525
Test name
Test status
Simulation time 43300658 ps
CPU time 2.08 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:49 PM PDT 24
Peak memory 196932 kb
Host smart-0c95f5b4-f7a9-431d-b383-b662a179f165
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789275610 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3789275610
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.1720984141
Short name T538
Test name
Test status
Simulation time 118893217 ps
CPU time 1.42 seconds
Started Jul 15 04:50:45 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 182724 kb
Host smart-c083f2c2-f32d-42b1-9179-bdb088e2d9dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720984141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.1720984141
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.3334934551
Short name T531
Test name
Test status
Simulation time 125753730 ps
CPU time 0.57 seconds
Started Jul 15 04:51:01 PM PDT 24
Finished Jul 15 04:51:04 PM PDT 24
Peak memory 182068 kb
Host smart-a591c5f3-1885-439f-8a3a-88094e23d6a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334934551 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.3334934551
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.785240912
Short name T549
Test name
Test status
Simulation time 54113096 ps
CPU time 0.55 seconds
Started Jul 15 04:51:02 PM PDT 24
Finished Jul 15 04:51:05 PM PDT 24
Peak memory 182112 kb
Host smart-775a8848-896a-463a-a4f4-588b13924919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785240912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.785240912
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2808651386
Short name T455
Test name
Test status
Simulation time 39689369 ps
CPU time 0.52 seconds
Started Jul 15 04:50:59 PM PDT 24
Finished Jul 15 04:51:03 PM PDT 24
Peak memory 181524 kb
Host smart-ee278e84-71b2-4a21-973b-aab2ced5932d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808651386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2808651386
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.712652811
Short name T475
Test name
Test status
Simulation time 17448424 ps
CPU time 0.54 seconds
Started Jul 15 04:50:59 PM PDT 24
Finished Jul 15 04:51:02 PM PDT 24
Peak memory 181540 kb
Host smart-7a20339a-10b2-4f30-a30d-ea752708e862
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712652811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.712652811
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.2468101304
Short name T457
Test name
Test status
Simulation time 49090976 ps
CPU time 0.55 seconds
Started Jul 15 04:50:59 PM PDT 24
Finished Jul 15 04:51:06 PM PDT 24
Peak memory 182064 kb
Host smart-194d7db9-ec66-498c-a40b-5e63c56b44c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468101304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.2468101304
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.2226177106
Short name T548
Test name
Test status
Simulation time 69711961 ps
CPU time 0.54 seconds
Started Jul 15 04:51:05 PM PDT 24
Finished Jul 15 04:51:07 PM PDT 24
Peak memory 182060 kb
Host smart-690c3f7e-0dd8-4170-88c4-17128d78b88a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226177106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.2226177106
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.2513043988
Short name T471
Test name
Test status
Simulation time 17169187 ps
CPU time 0.57 seconds
Started Jul 15 04:50:56 PM PDT 24
Finished Jul 15 04:50:59 PM PDT 24
Peak memory 182012 kb
Host smart-fa372db9-4a78-47a8-b70c-770edd0016bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513043988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.2513043988
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2275766366
Short name T510
Test name
Test status
Simulation time 13122745 ps
CPU time 0.56 seconds
Started Jul 15 04:51:04 PM PDT 24
Finished Jul 15 04:51:06 PM PDT 24
Peak memory 181544 kb
Host smart-9c0776e4-8ff2-4d56-8033-31c692f3e4be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275766366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2275766366
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.4103132829
Short name T460
Test name
Test status
Simulation time 15790149 ps
CPU time 0.6 seconds
Started Jul 15 04:50:56 PM PDT 24
Finished Jul 15 04:50:59 PM PDT 24
Peak memory 182044 kb
Host smart-bd71f748-d1b4-47f2-a8c8-598ebc2de81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103132829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.4103132829
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1220359034
Short name T524
Test name
Test status
Simulation time 92841855 ps
CPU time 0.56 seconds
Started Jul 15 04:50:58 PM PDT 24
Finished Jul 15 04:51:00 PM PDT 24
Peak memory 182048 kb
Host smart-6179f353-3876-4504-a367-7166276ad35c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220359034 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1220359034
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.4237087761
Short name T490
Test name
Test status
Simulation time 33838658 ps
CPU time 0.88 seconds
Started Jul 15 04:50:47 PM PDT 24
Finished Jul 15 04:50:50 PM PDT 24
Peak memory 195924 kb
Host smart-b68fb88e-1228-4615-9f1b-018de3188c27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237087761 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.4237087761
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.1622430463
Short name T553
Test name
Test status
Simulation time 31281490 ps
CPU time 0.57 seconds
Started Jul 15 04:50:42 PM PDT 24
Finished Jul 15 04:50:43 PM PDT 24
Peak memory 182192 kb
Host smart-7bb1268b-6b0d-4035-bbd1-fda40a26a06d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622430463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.1622430463
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.4150594282
Short name T488
Test name
Test status
Simulation time 16449590 ps
CPU time 0.55 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:47 PM PDT 24
Peak memory 181968 kb
Host smart-81c909b3-de7f-4a2d-a569-c468431cdff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150594282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.4150594282
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.4117255192
Short name T572
Test name
Test status
Simulation time 60925385 ps
CPU time 1.03 seconds
Started Jul 15 04:50:47 PM PDT 24
Finished Jul 15 04:50:50 PM PDT 24
Peak memory 192828 kb
Host smart-8f26d120-87d1-479e-95e7-88b0118c436b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117255192 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.4117255192
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.4218781235
Short name T518
Test name
Test status
Simulation time 213534267 ps
CPU time 2.65 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:49 PM PDT 24
Peak memory 196800 kb
Host smart-8490fffa-b1b7-4194-b147-1d8ba2465dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218781235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.4218781235
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.3298592476
Short name T554
Test name
Test status
Simulation time 124288933 ps
CPU time 1.43 seconds
Started Jul 15 04:50:46 PM PDT 24
Finished Jul 15 04:50:50 PM PDT 24
Peak memory 182780 kb
Host smart-54ae2485-c4ce-4845-abb4-660ed33a1abd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298592476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.3298592476
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.4176344376
Short name T48
Test name
Test status
Simulation time 96119044 ps
CPU time 0.79 seconds
Started Jul 15 04:50:42 PM PDT 24
Finished Jul 15 04:50:44 PM PDT 24
Peak memory 194348 kb
Host smart-74d6aef4-ee99-421e-8c0a-648fe687dd0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176344376 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.4176344376
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.1558616094
Short name T495
Test name
Test status
Simulation time 39750661 ps
CPU time 0.59 seconds
Started Jul 15 04:50:43 PM PDT 24
Finished Jul 15 04:50:45 PM PDT 24
Peak memory 182260 kb
Host smart-a1a8ce3a-8074-430f-8495-18af252cd5c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558616094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.1558616094
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2944182299
Short name T500
Test name
Test status
Simulation time 14240543 ps
CPU time 0.56 seconds
Started Jul 15 04:50:43 PM PDT 24
Finished Jul 15 04:50:44 PM PDT 24
Peak memory 182056 kb
Host smart-02040cce-1fc5-488d-83d0-45752b2cb990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944182299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2944182299
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.4145185352
Short name T507
Test name
Test status
Simulation time 54359666 ps
CPU time 0.77 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:47 PM PDT 24
Peak memory 192724 kb
Host smart-368dde3f-9ad2-4381-b527-c78ad534f5de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145185352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_ti
mer_same_csr_outstanding.4145185352
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.4071954
Short name T540
Test name
Test status
Simulation time 59681561 ps
CPU time 1.46 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 196944 kb
Host smart-7ed862dc-0df8-465d-bfdc-b8d6cae9dc53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071954 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.4071954
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2574339448
Short name T482
Test name
Test status
Simulation time 164769609 ps
CPU time 1.16 seconds
Started Jul 15 04:50:42 PM PDT 24
Finished Jul 15 04:50:44 PM PDT 24
Peak memory 194672 kb
Host smart-ef548c65-0623-4bdd-93c7-5fad940d0d8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574339448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2574339448
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2690938664
Short name T516
Test name
Test status
Simulation time 18415229 ps
CPU time 0.89 seconds
Started Jul 15 04:50:46 PM PDT 24
Finished Jul 15 04:50:49 PM PDT 24
Peak memory 195836 kb
Host smart-649636c5-ab9b-4188-af20-4173331d0cfc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690938664 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2690938664
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.3462577661
Short name T454
Test name
Test status
Simulation time 16920209 ps
CPU time 0.58 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:47 PM PDT 24
Peak memory 182172 kb
Host smart-601ee40b-d9cd-4fca-b6cc-4e778ded329f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462577661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.3462577661
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.700218942
Short name T451
Test name
Test status
Simulation time 46556884 ps
CPU time 0.58 seconds
Started Jul 15 04:50:43 PM PDT 24
Finished Jul 15 04:50:44 PM PDT 24
Peak memory 182044 kb
Host smart-af722153-d209-4b02-b0e3-65b5fbc8f542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700218942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.700218942
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1044265918
Short name T46
Test name
Test status
Simulation time 28546136 ps
CPU time 0.7 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:47 PM PDT 24
Peak memory 191080 kb
Host smart-4872c0a6-d353-4b70-b710-0d93a11bfb9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044265918 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1044265918
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.974155506
Short name T497
Test name
Test status
Simulation time 162464860 ps
CPU time 1.64 seconds
Started Jul 15 04:50:45 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 196968 kb
Host smart-856eab3e-e3ed-4dc2-9531-c9caaddba22b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974155506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.974155506
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.2645676699
Short name T30
Test name
Test status
Simulation time 161356766 ps
CPU time 0.83 seconds
Started Jul 15 04:50:43 PM PDT 24
Finished Jul 15 04:50:45 PM PDT 24
Peak memory 193144 kb
Host smart-76808786-296e-4c14-ab66-6f45a89e182c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645676699 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.2645676699
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.1605291488
Short name T527
Test name
Test status
Simulation time 72208221 ps
CPU time 0.99 seconds
Started Jul 15 04:50:45 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 196804 kb
Host smart-620119cb-5c61-40f7-b9ff-8aa47bfa54f1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605291488 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.1605291488
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.1512624165
Short name T562
Test name
Test status
Simulation time 19500598 ps
CPU time 0.6 seconds
Started Jul 15 04:50:45 PM PDT 24
Finished Jul 15 04:50:48 PM PDT 24
Peak memory 182176 kb
Host smart-9ae16a33-f108-491f-89c2-73a1885eb4be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512624165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.1512624165
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2028501871
Short name T557
Test name
Test status
Simulation time 13537200 ps
CPU time 0.55 seconds
Started Jul 15 04:50:43 PM PDT 24
Finished Jul 15 04:50:45 PM PDT 24
Peak memory 181532 kb
Host smart-6c13d550-b7da-4b63-982d-11849518614a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028501871 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2028501871
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.3917962414
Short name T96
Test name
Test status
Simulation time 13472595 ps
CPU time 0.64 seconds
Started Jul 15 04:50:42 PM PDT 24
Finished Jul 15 04:50:44 PM PDT 24
Peak memory 191380 kb
Host smart-a78926f8-63ee-4366-ac55-b79af26c88eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917962414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.3917962414
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3881955862
Short name T499
Test name
Test status
Simulation time 150811319 ps
CPU time 1.52 seconds
Started Jul 15 04:50:48 PM PDT 24
Finished Jul 15 04:50:52 PM PDT 24
Peak memory 196960 kb
Host smart-eaf53874-6ca9-4833-861b-a17ba5f03e25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881955862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3881955862
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2687375738
Short name T508
Test name
Test status
Simulation time 432887205 ps
CPU time 1.45 seconds
Started Jul 15 04:50:42 PM PDT 24
Finished Jul 15 04:50:44 PM PDT 24
Peak memory 182496 kb
Host smart-120b498b-b293-446c-81ec-6a653c6abcc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687375738 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2687375738
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.214342843
Short name T491
Test name
Test status
Simulation time 71559475 ps
CPU time 0.82 seconds
Started Jul 15 04:50:48 PM PDT 24
Finished Jul 15 04:50:50 PM PDT 24
Peak memory 194648 kb
Host smart-f56b56b2-125d-424b-8841-072035c14175
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214342843 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.214342843
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.1512142144
Short name T82
Test name
Test status
Simulation time 11182465 ps
CPU time 0.56 seconds
Started Jul 15 04:50:44 PM PDT 24
Finished Jul 15 04:50:46 PM PDT 24
Peak memory 181940 kb
Host smart-390e068a-f692-4051-9cf0-59c73099e128
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512142144 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.1512142144
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.2594691450
Short name T472
Test name
Test status
Simulation time 11363406 ps
CPU time 0.59 seconds
Started Jul 15 04:50:42 PM PDT 24
Finished Jul 15 04:50:44 PM PDT 24
Peak memory 181528 kb
Host smart-cf37dc00-b9df-4c16-a701-460dffb84aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594691450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.2594691450
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2630822245
Short name T32
Test name
Test status
Simulation time 193519999 ps
CPU time 0.82 seconds
Started Jul 15 04:50:43 PM PDT 24
Finished Jul 15 04:50:46 PM PDT 24
Peak memory 192324 kb
Host smart-0d7aa882-0cab-4bc1-b0f9-5523636be578
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630822245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2630822245
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1849379692
Short name T489
Test name
Test status
Simulation time 69824093 ps
CPU time 1.14 seconds
Started Jul 15 04:50:42 PM PDT 24
Finished Jul 15 04:50:44 PM PDT 24
Peak memory 196568 kb
Host smart-1a76aa68-31a7-43b1-93fc-7a0fb04f1fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849379692 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1849379692
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.324048471
Short name T28
Test name
Test status
Simulation time 286595929 ps
CPU time 1.03 seconds
Started Jul 15 04:50:47 PM PDT 24
Finished Jul 15 04:50:50 PM PDT 24
Peak memory 194568 kb
Host smart-1e7e5ebb-1b0c-4172-941c-cbd08d66703f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324048471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_int
g_err.324048471
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.2154715175
Short name T409
Test name
Test status
Simulation time 3344619970 ps
CPU time 5.83 seconds
Started Jul 15 04:27:58 PM PDT 24
Finished Jul 15 04:28:09 PM PDT 24
Peak memory 182732 kb
Host smart-362c7a73-6a84-45b1-9159-1cf9e39056ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154715175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.2154715175
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2725462716
Short name T73
Test name
Test status
Simulation time 116486362170 ps
CPU time 175.78 seconds
Started Jul 15 04:27:56 PM PDT 24
Finished Jul 15 04:30:57 PM PDT 24
Peak memory 182848 kb
Host smart-752b9922-89c1-4dab-8f17-b842dbd60f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725462716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2725462716
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2555311986
Short name T437
Test name
Test status
Simulation time 469501030091 ps
CPU time 93.22 seconds
Started Jul 15 04:25:26 PM PDT 24
Finished Jul 15 04:27:00 PM PDT 24
Peak memory 191092 kb
Host smart-cc3e33fd-554e-4f38-9dc1-1cc3ea6278da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555311986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2555311986
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.2448385184
Short name T19
Test name
Test status
Simulation time 326260880005 ps
CPU time 103.92 seconds
Started Jul 15 04:26:41 PM PDT 24
Finished Jul 15 04:28:26 PM PDT 24
Peak memory 183048 kb
Host smart-8109a1be-a9c1-4635-98aa-ec359a1fa72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448385184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.2448385184
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.552072369
Short name T129
Test name
Test status
Simulation time 52895763976 ps
CPU time 130.37 seconds
Started Jul 15 04:27:50 PM PDT 24
Finished Jul 15 04:30:04 PM PDT 24
Peak memory 190960 kb
Host smart-d8ef20b1-69fe-472b-af7a-4e497fb1811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552072369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.552072369
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.1497057088
Short name T14
Test name
Test status
Simulation time 336627976 ps
CPU time 0.97 seconds
Started Jul 15 04:27:40 PM PDT 24
Finished Jul 15 04:27:45 PM PDT 24
Peak memory 213584 kb
Host smart-fe201c3c-9c34-4796-af96-a50dce3affb5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497057088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.1497057088
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all_with_rand_reset.2869355621
Short name T12
Test name
Test status
Simulation time 84051841696 ps
CPU time 668.4 seconds
Started Jul 15 04:22:37 PM PDT 24
Finished Jul 15 04:33:46 PM PDT 24
Peak memory 205836 kb
Host smart-c9d386c6-fbbc-4a6c-9f88-8afe6d482deb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869355621 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all_with_rand_reset.2869355621
Directory /workspace/1.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.215619808
Short name T379
Test name
Test status
Simulation time 83296825096 ps
CPU time 64.21 seconds
Started Jul 15 04:29:28 PM PDT 24
Finished Jul 15 04:30:33 PM PDT 24
Peak memory 183016 kb
Host smart-d5e993ab-5a07-4be9-b8cc-f3f320b028cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215619808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.215619808
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2694846477
Short name T406
Test name
Test status
Simulation time 169454255 ps
CPU time 1.58 seconds
Started Jul 15 04:29:25 PM PDT 24
Finished Jul 15 04:29:28 PM PDT 24
Peak memory 194000 kb
Host smart-e6bc69cb-a08d-45e3-863a-e4401c7a5e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694846477 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2694846477
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.1127868679
Short name T61
Test name
Test status
Simulation time 325858128611 ps
CPU time 210.22 seconds
Started Jul 15 04:29:32 PM PDT 24
Finished Jul 15 04:33:04 PM PDT 24
Peak memory 182888 kb
Host smart-d13a9401-d4bc-4d11-b01a-923ec966e2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127868679 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.1127868679
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/100.rv_timer_random.458853306
Short name T119
Test name
Test status
Simulation time 413540881559 ps
CPU time 537.72 seconds
Started Jul 15 04:30:05 PM PDT 24
Finished Jul 15 04:39:05 PM PDT 24
Peak memory 191096 kb
Host smart-63d486ca-e51d-469c-8320-78ca5cc9c0aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458853306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.458853306
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.1267978956
Short name T118
Test name
Test status
Simulation time 892400676218 ps
CPU time 941.66 seconds
Started Jul 15 04:30:05 PM PDT 24
Finished Jul 15 04:45:48 PM PDT 24
Peak memory 191052 kb
Host smart-445499db-3b47-4f0c-b15b-2be035f0db0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267978956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.1267978956
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.3186069974
Short name T423
Test name
Test status
Simulation time 555597671049 ps
CPU time 230.42 seconds
Started Jul 15 04:30:05 PM PDT 24
Finished Jul 15 04:33:57 PM PDT 24
Peak memory 182844 kb
Host smart-606857de-888f-4603-9a70-dde829e79ac4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186069974 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.3186069974
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/103.rv_timer_random.2935731855
Short name T126
Test name
Test status
Simulation time 74088129973 ps
CPU time 108.82 seconds
Started Jul 15 04:29:58 PM PDT 24
Finished Jul 15 04:31:48 PM PDT 24
Peak memory 191080 kb
Host smart-b215baad-431c-4823-b9e8-77b3752e28bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935731855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.2935731855
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2244027655
Short name T447
Test name
Test status
Simulation time 34787422316 ps
CPU time 53.97 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:31:09 PM PDT 24
Peak memory 191064 kb
Host smart-8fa8d014-92ea-4f3a-85ca-1e18ea3b4860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244027655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2244027655
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.437824256
Short name T311
Test name
Test status
Simulation time 42123652058 ps
CPU time 66.76 seconds
Started Jul 15 04:30:09 PM PDT 24
Finished Jul 15 04:31:17 PM PDT 24
Peak memory 182892 kb
Host smart-bf1f7d70-d8f4-433d-9407-4d8cba594c66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437824256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.437824256
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.2771160002
Short name T322
Test name
Test status
Simulation time 203592956004 ps
CPU time 66.07 seconds
Started Jul 15 04:30:15 PM PDT 24
Finished Jul 15 04:31:24 PM PDT 24
Peak memory 182784 kb
Host smart-04e9cc56-ff0c-46a5-9632-21685b480904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771160002 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.2771160002
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.3310664513
Short name T350
Test name
Test status
Simulation time 30066868592 ps
CPU time 15.99 seconds
Started Jul 15 04:29:20 PM PDT 24
Finished Jul 15 04:29:37 PM PDT 24
Peak memory 182864 kb
Host smart-00eaa02c-15a7-416a-9ff8-c39cd2e62940
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310664513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.3310664513
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2613699259
Short name T380
Test name
Test status
Simulation time 492391423894 ps
CPU time 68.4 seconds
Started Jul 15 04:29:40 PM PDT 24
Finished Jul 15 04:30:49 PM PDT 24
Peak memory 182860 kb
Host smart-8346d4e4-4cc4-468f-a7c8-4ca92c77b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613699259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2613699259
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.2420876985
Short name T79
Test name
Test status
Simulation time 339884368969 ps
CPU time 113.35 seconds
Started Jul 15 04:29:49 PM PDT 24
Finished Jul 15 04:31:45 PM PDT 24
Peak memory 182880 kb
Host smart-7aef9d01-fb51-4695-827a-48ba32fdd8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420876985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.2420876985
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/110.rv_timer_random.4106167392
Short name T161
Test name
Test status
Simulation time 769114292997 ps
CPU time 657.07 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:41:22 PM PDT 24
Peak memory 191232 kb
Host smart-a517cdb8-b0e2-444c-8900-bace458641f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106167392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.4106167392
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.812646317
Short name T334
Test name
Test status
Simulation time 42737139195 ps
CPU time 79.98 seconds
Started Jul 15 04:30:05 PM PDT 24
Finished Jul 15 04:31:26 PM PDT 24
Peak memory 191112 kb
Host smart-8d733a7c-4c9e-4d42-a604-8535b55afbbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812646317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.812646317
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.4110945700
Short name T413
Test name
Test status
Simulation time 79853773418 ps
CPU time 327.14 seconds
Started Jul 15 04:30:07 PM PDT 24
Finished Jul 15 04:35:36 PM PDT 24
Peak memory 182876 kb
Host smart-829b3621-e0a6-4118-b168-17d0e153edcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110945700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.4110945700
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.2595851875
Short name T75
Test name
Test status
Simulation time 169738028320 ps
CPU time 549.05 seconds
Started Jul 15 04:30:11 PM PDT 24
Finished Jul 15 04:39:22 PM PDT 24
Peak memory 191088 kb
Host smart-9617ea88-5455-4a49-9a7b-7a6860484357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595851875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.2595851875
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.828493588
Short name T209
Test name
Test status
Simulation time 44563637269 ps
CPU time 66.8 seconds
Started Jul 15 04:30:01 PM PDT 24
Finished Jul 15 04:31:09 PM PDT 24
Peak memory 182788 kb
Host smart-56d121e4-b59c-47a3-be9d-1a0436c799e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828493588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.828493588
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.1527595687
Short name T408
Test name
Test status
Simulation time 36204709893 ps
CPU time 66.29 seconds
Started Jul 15 04:30:22 PM PDT 24
Finished Jul 15 04:31:29 PM PDT 24
Peak memory 191064 kb
Host smart-ce8ff47f-8815-4801-a068-7d21b912e2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527595687 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.1527595687
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3293949951
Short name T223
Test name
Test status
Simulation time 34390003955 ps
CPU time 235.7 seconds
Started Jul 15 04:30:15 PM PDT 24
Finished Jul 15 04:34:13 PM PDT 24
Peak memory 191092 kb
Host smart-61be9cef-bea0-427a-a5f9-fa2b45daa707
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293949951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3293949951
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.783084025
Short name T396
Test name
Test status
Simulation time 61968914138 ps
CPU time 91.63 seconds
Started Jul 15 04:29:34 PM PDT 24
Finished Jul 15 04:31:07 PM PDT 24
Peak memory 182904 kb
Host smart-466267df-d109-4601-a71d-a118fa948dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783084025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.783084025
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3449807337
Short name T136
Test name
Test status
Simulation time 156756838765 ps
CPU time 1545.6 seconds
Started Jul 15 04:29:28 PM PDT 24
Finished Jul 15 04:55:15 PM PDT 24
Peak memory 191100 kb
Host smart-7bd7a235-477f-4b9a-bbe0-ebcc32668c05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449807337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3449807337
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.4224140828
Short name T347
Test name
Test status
Simulation time 5111485031 ps
CPU time 157.39 seconds
Started Jul 15 04:29:40 PM PDT 24
Finished Jul 15 04:32:19 PM PDT 24
Peak memory 191060 kb
Host smart-c49cf4de-26eb-483a-8261-de01eb62d222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224140828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.4224140828
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all_with_rand_reset.2853187290
Short name T34
Test name
Test status
Simulation time 105916500730 ps
CPU time 250.73 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:34:01 PM PDT 24
Peak memory 197576 kb
Host smart-b035f191-e4ce-401d-8fef-22673acec83b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853187290 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all_with_rand_reset.2853187290
Directory /workspace/12.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.3380665043
Short name T262
Test name
Test status
Simulation time 336646488273 ps
CPU time 136.04 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:32:32 PM PDT 24
Peak memory 191104 kb
Host smart-738f5c5f-981a-4b7d-a3aa-b383c0a8e6e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380665043 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.3380665043
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2380491108
Short name T357
Test name
Test status
Simulation time 406781722935 ps
CPU time 566.36 seconds
Started Jul 15 04:30:04 PM PDT 24
Finished Jul 15 04:39:32 PM PDT 24
Peak memory 191432 kb
Host smart-bb00a3f7-0310-494b-b6f0-48c1ac52dfd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380491108 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2380491108
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.2403864436
Short name T430
Test name
Test status
Simulation time 20653435283 ps
CPU time 17.02 seconds
Started Jul 15 04:30:10 PM PDT 24
Finished Jul 15 04:30:28 PM PDT 24
Peak memory 182908 kb
Host smart-0e70a856-1f56-4390-84a9-539e134b3532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403864436 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.2403864436
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3796787089
Short name T309
Test name
Test status
Simulation time 47942457572 ps
CPU time 21.77 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:30:35 PM PDT 24
Peak memory 182864 kb
Host smart-f9653aa3-9bcd-4b45-aae2-e6a68ec0b757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796787089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3796787089
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.408548287
Short name T253
Test name
Test status
Simulation time 62244111347 ps
CPU time 20.55 seconds
Started Jul 15 04:30:11 PM PDT 24
Finished Jul 15 04:30:33 PM PDT 24
Peak memory 182868 kb
Host smart-be5a9104-4651-4b78-aa02-6a6ab6923adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408548287 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.408548287
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.4095298480
Short name T341
Test name
Test status
Simulation time 272974440976 ps
CPU time 239.02 seconds
Started Jul 15 04:30:16 PM PDT 24
Finished Jul 15 04:34:17 PM PDT 24
Peak memory 191088 kb
Host smart-c4eca82b-6f8e-4bf4-b4ac-736f0d706e4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095298480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.4095298480
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2101834365
Short name T353
Test name
Test status
Simulation time 1447343430034 ps
CPU time 724.71 seconds
Started Jul 15 04:29:29 PM PDT 24
Finished Jul 15 04:41:36 PM PDT 24
Peak memory 182912 kb
Host smart-951fd3b1-e431-4223-8754-635621830bb6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101834365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2101834365
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.4257356740
Short name T372
Test name
Test status
Simulation time 345632125894 ps
CPU time 125.6 seconds
Started Jul 15 04:29:24 PM PDT 24
Finished Jul 15 04:31:30 PM PDT 24
Peak memory 182860 kb
Host smart-5d2ea75d-2379-466d-b5c7-06bb42dd5eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257356740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.4257356740
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.4251029884
Short name T392
Test name
Test status
Simulation time 1386165961616 ps
CPU time 217.86 seconds
Started Jul 15 04:29:14 PM PDT 24
Finished Jul 15 04:32:53 PM PDT 24
Peak memory 194588 kb
Host smart-1948f702-8d02-49c2-b7a2-457d32028e0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251029884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.4251029884
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/130.rv_timer_random.4141587242
Short name T290
Test name
Test status
Simulation time 155580137003 ps
CPU time 261.6 seconds
Started Jul 15 04:30:05 PM PDT 24
Finished Jul 15 04:34:28 PM PDT 24
Peak memory 191208 kb
Host smart-6288d988-e6a9-4c42-a8bd-b1c3951f284d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141587242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.4141587242
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.1763727793
Short name T201
Test name
Test status
Simulation time 190828130746 ps
CPU time 399.77 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:36:55 PM PDT 24
Peak memory 193280 kb
Host smart-322a6e8d-b673-44bc-b3d2-7a7c31c0caf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763727793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.1763727793
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.2771411559
Short name T306
Test name
Test status
Simulation time 286858810243 ps
CPU time 204.11 seconds
Started Jul 15 04:30:06 PM PDT 24
Finished Jul 15 04:33:32 PM PDT 24
Peak memory 182868 kb
Host smart-ab222b20-9fb6-46ae-9b7b-fdb112c267fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771411559 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.2771411559
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.80944674
Short name T134
Test name
Test status
Simulation time 84368264084 ps
CPU time 292.74 seconds
Started Jul 15 04:30:20 PM PDT 24
Finished Jul 15 04:35:14 PM PDT 24
Peak memory 191108 kb
Host smart-0671b95b-cfbe-48af-9a65-a07a45349946
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80944674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.80944674
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1185168935
Short name T277
Test name
Test status
Simulation time 198780268344 ps
CPU time 165.16 seconds
Started Jul 15 04:30:17 PM PDT 24
Finished Jul 15 04:33:04 PM PDT 24
Peak memory 191232 kb
Host smart-dcb88b7c-f596-490c-a04d-c84999257d6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185168935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1185168935
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.3513721591
Short name T308
Test name
Test status
Simulation time 502212881528 ps
CPU time 638 seconds
Started Jul 15 04:30:15 PM PDT 24
Finished Jul 15 04:40:55 PM PDT 24
Peak memory 191096 kb
Host smart-d4d81f61-5be6-4228-93d8-7aa5a9cbefbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513721591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.3513721591
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.1219025841
Short name T384
Test name
Test status
Simulation time 221046399093 ps
CPU time 82.93 seconds
Started Jul 15 04:29:29 PM PDT 24
Finished Jul 15 04:30:54 PM PDT 24
Peak memory 182900 kb
Host smart-cb6507a9-f119-4fec-84e9-7bdaedf30557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219025841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.1219025841
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1749730146
Short name T233
Test name
Test status
Simulation time 163247805372 ps
CPU time 167.5 seconds
Started Jul 15 04:29:31 PM PDT 24
Finished Jul 15 04:32:20 PM PDT 24
Peak memory 191104 kb
Host smart-58043b2e-f019-4230-99b1-6b0521f6b603
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749730146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1749730146
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.797034574
Short name T443
Test name
Test status
Simulation time 36996170 ps
CPU time 0.72 seconds
Started Jul 15 04:29:31 PM PDT 24
Finished Jul 15 04:29:33 PM PDT 24
Peak memory 182768 kb
Host smart-3932a7a2-a71d-4b3a-870e-10d1d2fb6166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797034574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.797034574
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.3897323063
Short name T10
Test name
Test status
Simulation time 573977103741 ps
CPU time 370.37 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:36:28 PM PDT 24
Peak memory 191024 kb
Host smart-b8c7ef26-af46-48ed-8e3d-87cefd3feb00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897323063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.3897323063
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.3785379861
Short name T148
Test name
Test status
Simulation time 108488562694 ps
CPU time 175.63 seconds
Started Jul 15 04:30:11 PM PDT 24
Finished Jul 15 04:33:08 PM PDT 24
Peak memory 191104 kb
Host smart-9796f840-529c-47ee-9973-fe82f06c20a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785379861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.3785379861
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.2008471339
Short name T78
Test name
Test status
Simulation time 172817982713 ps
CPU time 523.17 seconds
Started Jul 15 04:30:16 PM PDT 24
Finished Jul 15 04:39:01 PM PDT 24
Peak memory 191052 kb
Host smart-0e877dde-01b4-475d-b79e-09b32baae659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008471339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.2008471339
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.3159711303
Short name T170
Test name
Test status
Simulation time 106191978979 ps
CPU time 805.62 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:43:43 PM PDT 24
Peak memory 191044 kb
Host smart-f859713b-3d38-437b-8935-b3743aafd4c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159711303 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.3159711303
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.1056141741
Short name T337
Test name
Test status
Simulation time 79128210154 ps
CPU time 562.36 seconds
Started Jul 15 04:30:20 PM PDT 24
Finished Jul 15 04:39:44 PM PDT 24
Peak memory 191104 kb
Host smart-34c9a799-a870-4d4b-a0b4-f7ed034eb1bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056141741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.1056141741
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.3185865457
Short name T174
Test name
Test status
Simulation time 234588327642 ps
CPU time 340.71 seconds
Started Jul 15 04:30:19 PM PDT 24
Finished Jul 15 04:36:01 PM PDT 24
Peak memory 193604 kb
Host smart-6651c3be-c6df-4fb1-8375-3af5bf5850eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185865457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.3185865457
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.1347577260
Short name T230
Test name
Test status
Simulation time 212744748051 ps
CPU time 168.34 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 04:32:34 PM PDT 24
Peak memory 183016 kb
Host smart-d0ed5151-6066-46f2-8739-5d1b4fb068c5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347577260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.1347577260
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.446561369
Short name T436
Test name
Test status
Simulation time 57854747356 ps
CPU time 78.73 seconds
Started Jul 15 04:29:33 PM PDT 24
Finished Jul 15 04:30:53 PM PDT 24
Peak memory 182920 kb
Host smart-7963e92a-e452-430b-88c4-cc7dd31c6893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446561369 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.446561369
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.241217657
Short name T424
Test name
Test status
Simulation time 744937809 ps
CPU time 1.64 seconds
Started Jul 15 04:29:40 PM PDT 24
Finished Jul 15 04:29:43 PM PDT 24
Peak memory 182860 kb
Host smart-b804e3a4-43a2-432b-ac93-ad30ceed04e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241217657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.241217657
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/151.rv_timer_random.2160322416
Short name T123
Test name
Test status
Simulation time 457420663832 ps
CPU time 390.1 seconds
Started Jul 15 04:30:11 PM PDT 24
Finished Jul 15 04:36:43 PM PDT 24
Peak memory 191068 kb
Host smart-7f8009e9-6ca9-4bc3-9847-ec8c582acdef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160322416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.2160322416
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2070713718
Short name T270
Test name
Test status
Simulation time 238672286061 ps
CPU time 116.61 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:32:21 PM PDT 24
Peak memory 182824 kb
Host smart-fc9e3519-c979-467a-b89c-b779e1116759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070713718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2070713718
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.734367125
Short name T159
Test name
Test status
Simulation time 21576881601 ps
CPU time 15.6 seconds
Started Jul 15 04:30:07 PM PDT 24
Finished Jul 15 04:30:24 PM PDT 24
Peak memory 182900 kb
Host smart-2ed889fc-532d-4b48-ac13-9a2925f38e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734367125 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.734367125
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.196449378
Short name T296
Test name
Test status
Simulation time 72606224617 ps
CPU time 108.61 seconds
Started Jul 15 04:30:04 PM PDT 24
Finished Jul 15 04:31:54 PM PDT 24
Peak memory 191236 kb
Host smart-8bd9166b-58c6-4751-ad03-9a1379a19c79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196449378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.196449378
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.3115335407
Short name T422
Test name
Test status
Simulation time 42123046597 ps
CPU time 21.43 seconds
Started Jul 15 04:30:26 PM PDT 24
Finished Jul 15 04:30:49 PM PDT 24
Peak memory 182920 kb
Host smart-5d511d0d-37f8-465b-8fe7-4a50842e23bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115335407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.3115335407
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.3452624913
Short name T345
Test name
Test status
Simulation time 3278130879 ps
CPU time 5.78 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:30:30 PM PDT 24
Peak memory 182880 kb
Host smart-b0b8f9cf-16bc-4c02-a832-a0f6ef5300b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452624913 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.3452624913
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.686037197
Short name T284
Test name
Test status
Simulation time 240749891599 ps
CPU time 2030.89 seconds
Started Jul 15 04:30:20 PM PDT 24
Finished Jul 15 05:04:12 PM PDT 24
Peak memory 191108 kb
Host smart-24e4834b-67c0-4486-be18-015b6d07e7e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686037197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.686037197
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.3118978739
Short name T333
Test name
Test status
Simulation time 200725551116 ps
CPU time 105.95 seconds
Started Jul 15 04:29:34 PM PDT 24
Finished Jul 15 04:31:21 PM PDT 24
Peak memory 182900 kb
Host smart-6018dc78-8ab0-44c1-bee4-bb75d300d18d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118978739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.3118978739
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.776979381
Short name T381
Test name
Test status
Simulation time 514245138126 ps
CPU time 211 seconds
Started Jul 15 04:29:40 PM PDT 24
Finished Jul 15 04:33:12 PM PDT 24
Peak memory 183048 kb
Host smart-693c558f-234e-4827-a9e8-1e092838d00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776979381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.776979381
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.2055568185
Short name T200
Test name
Test status
Simulation time 650523587359 ps
CPU time 398.12 seconds
Started Jul 15 04:29:25 PM PDT 24
Finished Jul 15 04:36:04 PM PDT 24
Peak memory 191092 kb
Host smart-9d425efc-ed5b-4ba2-8fbd-40384d8bfc3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055568185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.2055568185
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.273296523
Short name T336
Test name
Test status
Simulation time 98869664524 ps
CPU time 782.11 seconds
Started Jul 15 04:29:30 PM PDT 24
Finished Jul 15 04:42:34 PM PDT 24
Peak memory 191100 kb
Host smart-8d2c55ca-7bd0-43f5-8e5f-1d676f2dc5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273296523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.273296523
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.2539947494
Short name T132
Test name
Test status
Simulation time 407797195135 ps
CPU time 811.47 seconds
Started Jul 15 04:30:43 PM PDT 24
Finished Jul 15 04:44:16 PM PDT 24
Peak memory 190864 kb
Host smart-0c12d6da-e5fa-4666-a5ba-94c822c82e17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539947494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.2539947494
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.1793702166
Short name T335
Test name
Test status
Simulation time 342881958586 ps
CPU time 260.82 seconds
Started Jul 15 04:30:20 PM PDT 24
Finished Jul 15 04:34:42 PM PDT 24
Peak memory 194440 kb
Host smart-b386ad37-d7bb-4688-8f85-e4e992474b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793702166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.1793702166
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3370419233
Short name T393
Test name
Test status
Simulation time 300152509542 ps
CPU time 439.76 seconds
Started Jul 15 04:30:20 PM PDT 24
Finished Jul 15 04:37:41 PM PDT 24
Peak memory 191156 kb
Host smart-340a9dde-3126-4178-b189-807fa8030393
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370419233 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3370419233
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.2016319398
Short name T305
Test name
Test status
Simulation time 104272713471 ps
CPU time 172.12 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:33:07 PM PDT 24
Peak memory 193396 kb
Host smart-6080e64d-28ac-4dbc-9407-4ff0e5a181a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016319398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.2016319398
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.1050859530
Short name T7
Test name
Test status
Simulation time 53171693168 ps
CPU time 78.06 seconds
Started Jul 15 04:30:16 PM PDT 24
Finished Jul 15 04:31:36 PM PDT 24
Peak memory 191044 kb
Host smart-4ad7ad90-4fd9-4931-85cb-981cdeec57d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050859530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.1050859530
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.3472112394
Short name T267
Test name
Test status
Simulation time 96644635371 ps
CPU time 119.04 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:32:16 PM PDT 24
Peak memory 191092 kb
Host smart-1f14ee5b-26d4-482d-9c40-6915f1ff1f87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472112394 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.3472112394
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.660404902
Short name T387
Test name
Test status
Simulation time 144676614845 ps
CPU time 69.67 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:31:34 PM PDT 24
Peak memory 182880 kb
Host smart-64a3fb9f-5d61-43dc-8558-8324d49e8a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660404902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.660404902
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.3996132298
Short name T197
Test name
Test status
Simulation time 3313461890 ps
CPU time 4.7 seconds
Started Jul 15 04:30:06 PM PDT 24
Finished Jul 15 04:30:12 PM PDT 24
Peak memory 182808 kb
Host smart-5d5f927e-0aa6-4bc9-8ac3-f1d5886b4e5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996132298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.3996132298
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.1673256652
Short name T169
Test name
Test status
Simulation time 97161711407 ps
CPU time 82.96 seconds
Started Jul 15 04:30:06 PM PDT 24
Finished Jul 15 04:31:30 PM PDT 24
Peak memory 191084 kb
Host smart-380ad4a0-cf13-4a48-8a3d-e133eaebcb63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673256652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.1673256652
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.4126082653
Short name T319
Test name
Test status
Simulation time 394732689912 ps
CPU time 551.28 seconds
Started Jul 15 04:29:26 PM PDT 24
Finished Jul 15 04:38:39 PM PDT 24
Peak memory 182908 kb
Host smart-b501870f-e024-4045-a959-af52ccc48f49
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126082653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.4126082653
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.2833679226
Short name T369
Test name
Test status
Simulation time 473018384164 ps
CPU time 183.69 seconds
Started Jul 15 04:29:40 PM PDT 24
Finished Jul 15 04:32:45 PM PDT 24
Peak memory 182916 kb
Host smart-941f655c-5767-429c-a313-ea4fd4b2192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833679226 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.2833679226
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.37985549
Short name T320
Test name
Test status
Simulation time 5614096988 ps
CPU time 9.56 seconds
Started Jul 15 04:29:26 PM PDT 24
Finished Jul 15 04:29:37 PM PDT 24
Peak memory 182888 kb
Host smart-a5ac3875-5a1c-4f25-ab77-fa0a7e1f034e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37985549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.37985549
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.1766944690
Short name T376
Test name
Test status
Simulation time 136435026 ps
CPU time 0.66 seconds
Started Jul 15 04:29:36 PM PDT 24
Finished Jul 15 04:29:38 PM PDT 24
Peak memory 191376 kb
Host smart-173849a4-53bd-419d-86d7-d785e8fdb2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766944690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.1766944690
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.527678860
Short name T145
Test name
Test status
Simulation time 9600379460383 ps
CPU time 4081.39 seconds
Started Jul 15 04:29:54 PM PDT 24
Finished Jul 15 05:37:58 PM PDT 24
Peak memory 191448 kb
Host smart-a68bef0a-8944-4ee9-97c8-d05c36c56fa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527678860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all.
527678860
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/171.rv_timer_random.109238880
Short name T302
Test name
Test status
Simulation time 6885202952 ps
CPU time 9.15 seconds
Started Jul 15 04:30:24 PM PDT 24
Finished Jul 15 04:30:34 PM PDT 24
Peak memory 182792 kb
Host smart-28f0b391-23ca-4360-88d6-1a4f6131ffb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109238880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.109238880
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.505742789
Short name T182
Test name
Test status
Simulation time 1070708757190 ps
CPU time 1857.64 seconds
Started Jul 15 04:30:10 PM PDT 24
Finished Jul 15 05:01:10 PM PDT 24
Peak memory 191088 kb
Host smart-62ed5a61-39db-4f7a-ab51-3a2c0c05c085
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505742789 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.505742789
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.650535909
Short name T184
Test name
Test status
Simulation time 354339266310 ps
CPU time 275.51 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:34:50 PM PDT 24
Peak memory 193312 kb
Host smart-4f22b994-7e9a-446a-aa9f-db9dfc86ee25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650535909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.650535909
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.2184490992
Short name T283
Test name
Test status
Simulation time 378814031888 ps
CPU time 536.04 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:39:13 PM PDT 24
Peak memory 191016 kb
Host smart-13f03d28-46ac-4f92-a925-3c8a3097bced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184490992 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.2184490992
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1315054825
Short name T252
Test name
Test status
Simulation time 271736105786 ps
CPU time 123.44 seconds
Started Jul 15 04:30:27 PM PDT 24
Finished Jul 15 04:32:32 PM PDT 24
Peak memory 191080 kb
Host smart-417119bf-947f-4e0d-a19f-93b7f6b924bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315054825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1315054825
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3814094129
Short name T263
Test name
Test status
Simulation time 29513459421 ps
CPU time 49.53 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:30:45 PM PDT 24
Peak memory 182904 kb
Host smart-d8d14100-59d7-449e-9667-a4b106990495
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814094129 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3814094129
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.2736625313
Short name T433
Test name
Test status
Simulation time 331040293362 ps
CPU time 130.15 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:31:59 PM PDT 24
Peak memory 182912 kb
Host smart-bdd5d431-784f-488a-8a61-2d434544429d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736625313 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.2736625313
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2652379809
Short name T211
Test name
Test status
Simulation time 76297394957 ps
CPU time 311.87 seconds
Started Jul 15 04:29:36 PM PDT 24
Finished Jul 15 04:34:50 PM PDT 24
Peak memory 191072 kb
Host smart-a7af54b5-b0a6-4d10-a84d-16ca8fb1c0ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652379809 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2652379809
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.1970025528
Short name T450
Test name
Test status
Simulation time 82368833 ps
CPU time 0.79 seconds
Started Jul 15 04:29:45 PM PDT 24
Finished Jul 15 04:29:48 PM PDT 24
Peak memory 182760 kb
Host smart-895c89ba-f539-44bf-95e4-96e38e76abe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970025528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.1970025528
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.1457776096
Short name T390
Test name
Test status
Simulation time 195726192012 ps
CPU time 256.72 seconds
Started Jul 15 04:29:46 PM PDT 24
Finished Jul 15 04:34:05 PM PDT 24
Peak memory 194980 kb
Host smart-e4edc3b8-aa50-4ab8-b151-5ef9489b1f27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457776096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.1457776096
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/183.rv_timer_random.1989561377
Short name T301
Test name
Test status
Simulation time 553637686476 ps
CPU time 292.92 seconds
Started Jul 15 04:30:25 PM PDT 24
Finished Jul 15 04:35:19 PM PDT 24
Peak memory 191080 kb
Host smart-79fcb519-d205-4a7b-b3d1-a7f0e8999f04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989561377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.1989561377
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.3685816276
Short name T26
Test name
Test status
Simulation time 368157573150 ps
CPU time 858.89 seconds
Started Jul 15 04:30:19 PM PDT 24
Finished Jul 15 04:44:39 PM PDT 24
Peak memory 193736 kb
Host smart-bbff9446-3053-4907-970b-fe138678ae60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685816276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.3685816276
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.3361899991
Short name T264
Test name
Test status
Simulation time 234975046206 ps
CPU time 1763.57 seconds
Started Jul 15 04:30:24 PM PDT 24
Finished Jul 15 04:59:49 PM PDT 24
Peak memory 191060 kb
Host smart-14e5df5e-e3ed-4cf4-8492-426a12b70fe7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361899991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.3361899991
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.3726436923
Short name T321
Test name
Test status
Simulation time 208569818895 ps
CPU time 177.84 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:33:15 PM PDT 24
Peak memory 193652 kb
Host smart-dac0513f-c01e-4464-928c-c29b798c0f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726436923 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.3726436923
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.684206402
Short name T27
Test name
Test status
Simulation time 21791366167 ps
CPU time 35.75 seconds
Started Jul 15 04:30:30 PM PDT 24
Finished Jul 15 04:31:08 PM PDT 24
Peak memory 182904 kb
Host smart-a192d277-7fd8-4688-92a6-92484eea3a58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684206402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.684206402
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.2829063753
Short name T295
Test name
Test status
Simulation time 74859725698 ps
CPU time 65.73 seconds
Started Jul 15 04:30:24 PM PDT 24
Finished Jul 15 04:31:31 PM PDT 24
Peak memory 191240 kb
Host smart-60291437-7042-40fb-8765-b51a32ac5236
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829063753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.2829063753
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2452449035
Short name T260
Test name
Test status
Simulation time 479378221373 ps
CPU time 275.79 seconds
Started Jul 15 04:29:46 PM PDT 24
Finished Jul 15 04:34:24 PM PDT 24
Peak memory 182912 kb
Host smart-21156867-061b-431c-b8be-ddf44ec96a85
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452449035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2452449035
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.2069966223
Short name T377
Test name
Test status
Simulation time 153170693783 ps
CPU time 65.36 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 04:30:56 PM PDT 24
Peak memory 182872 kb
Host smart-46a9a4fd-76ca-4a91-9113-f02470e559ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069966223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.2069966223
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.4201329294
Short name T271
Test name
Test status
Simulation time 44128940551 ps
CPU time 695.51 seconds
Started Jul 15 04:29:38 PM PDT 24
Finished Jul 15 04:41:15 PM PDT 24
Peak memory 191116 kb
Host smart-88990f16-0580-4a68-9a15-d2f67773b972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201329294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.4201329294
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.669641588
Short name T226
Test name
Test status
Simulation time 23405332240 ps
CPU time 38.46 seconds
Started Jul 15 04:29:50 PM PDT 24
Finished Jul 15 04:30:32 PM PDT 24
Peak memory 193300 kb
Host smart-e4e75256-742d-4d47-a1ec-49cde9c72d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669641588 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.669641588
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3204677736
Short name T317
Test name
Test status
Simulation time 213923791417 ps
CPU time 139.44 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:32:09 PM PDT 24
Peak memory 191064 kb
Host smart-3cb1113b-0b76-4f73-890d-0f7c7e36ea1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204677736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3204677736
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/190.rv_timer_random.3225906275
Short name T225
Test name
Test status
Simulation time 97521964118 ps
CPU time 759.05 seconds
Started Jul 15 04:30:13 PM PDT 24
Finished Jul 15 04:42:55 PM PDT 24
Peak memory 191096 kb
Host smart-3fdca9b7-fb70-4021-ab28-85110bfdac29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225906275 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.3225906275
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2974808827
Short name T175
Test name
Test status
Simulation time 83262768362 ps
CPU time 129.98 seconds
Started Jul 15 04:30:15 PM PDT 24
Finished Jul 15 04:32:28 PM PDT 24
Peak memory 194564 kb
Host smart-6f87d1ef-381e-4f8f-b7f1-11ef3a3535c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974808827 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2974808827
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.2863945259
Short name T316
Test name
Test status
Simulation time 37238269341 ps
CPU time 16.85 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:30:34 PM PDT 24
Peak memory 182908 kb
Host smart-8c01f600-2652-4ac7-b0cf-5e8cfc0105a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863945259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.2863945259
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.1297983942
Short name T24
Test name
Test status
Simulation time 612560389347 ps
CPU time 172.54 seconds
Started Jul 15 04:30:26 PM PDT 24
Finished Jul 15 04:33:20 PM PDT 24
Peak memory 191116 kb
Host smart-bc4a4a3a-33d5-4013-aff2-5b7e95c4bb3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297983942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1297983942
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.547108370
Short name T206
Test name
Test status
Simulation time 66001605820 ps
CPU time 103.01 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:32:07 PM PDT 24
Peak memory 192540 kb
Host smart-d2301a5b-45b5-44e0-bb90-3579fddee904
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547108370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.547108370
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.1794587243
Short name T232
Test name
Test status
Simulation time 392222868846 ps
CPU time 1031.62 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:47:36 PM PDT 24
Peak memory 191096 kb
Host smart-f9f000bf-d36e-41f6-b452-62cc7768aebd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794587243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.1794587243
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.3621259770
Short name T41
Test name
Test status
Simulation time 872391743734 ps
CPU time 614.43 seconds
Started Jul 15 04:30:18 PM PDT 24
Finished Jul 15 04:40:33 PM PDT 24
Peak memory 191120 kb
Host smart-55aa089e-8d6e-4bba-8165-1f6800d7d337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621259770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.3621259770
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.445364111
Short name T128
Test name
Test status
Simulation time 220014101291 ps
CPU time 78.43 seconds
Started Jul 15 04:30:25 PM PDT 24
Finished Jul 15 04:31:45 PM PDT 24
Peak memory 191080 kb
Host smart-c54e09b0-8b42-4aea-a4f5-681f9883a399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445364111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.445364111
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.3568633938
Short name T282
Test name
Test status
Simulation time 217074201059 ps
CPU time 195.23 seconds
Started Jul 15 04:26:41 PM PDT 24
Finished Jul 15 04:29:57 PM PDT 24
Peak memory 183024 kb
Host smart-4649a58a-23a2-48b5-bbff-6bf86213318c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568633938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.3568633938
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3793800273
Short name T374
Test name
Test status
Simulation time 163636185364 ps
CPU time 112.75 seconds
Started Jul 15 04:26:49 PM PDT 24
Finished Jul 15 04:28:44 PM PDT 24
Peak memory 182500 kb
Host smart-a92b03ab-e748-4b82-87be-033c4d44cc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793800273 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3793800273
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1922149666
Short name T314
Test name
Test status
Simulation time 106627690237 ps
CPU time 777.34 seconds
Started Jul 15 04:26:39 PM PDT 24
Finished Jul 15 04:39:38 PM PDT 24
Peak memory 190388 kb
Host smart-39645392-5001-413e-96a6-d52c5a10dbd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922149666 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1922149666
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.2917923395
Short name T363
Test name
Test status
Simulation time 1082205844 ps
CPU time 1.03 seconds
Started Jul 15 04:27:37 PM PDT 24
Finished Jul 15 04:27:43 PM PDT 24
Peak memory 181220 kb
Host smart-12a6433f-df34-4c60-88ce-90b95909dced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917923395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.2917923395
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.28477929
Short name T15
Test name
Test status
Simulation time 395382274 ps
CPU time 0.91 seconds
Started Jul 15 04:26:24 PM PDT 24
Finished Jul 15 04:26:27 PM PDT 24
Peak memory 212500 kb
Host smart-4f022b74-f093-47aa-b0b9-a8a8acfed110
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28477929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.28477929
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all_with_rand_reset.3885715988
Short name T11
Test name
Test status
Simulation time 92235526057 ps
CPU time 854.19 seconds
Started Jul 15 04:21:47 PM PDT 24
Finished Jul 15 04:36:02 PM PDT 24
Peak memory 209580 kb
Host smart-327c7f71-1ddc-4b53-9e1e-a84b73ba0cb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885715988 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all_with_rand_reset.3885715988
Directory /workspace/2.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.2528812691
Short name T62
Test name
Test status
Simulation time 28572228504 ps
CPU time 88.4 seconds
Started Jul 15 04:29:46 PM PDT 24
Finished Jul 15 04:31:17 PM PDT 24
Peak memory 182916 kb
Host smart-ba4eedc0-f303-42dd-a876-70cf355ce04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528812691 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.2528812691
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.3529806296
Short name T401
Test name
Test status
Simulation time 251349102176 ps
CPU time 171.97 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:32:46 PM PDT 24
Peak memory 191100 kb
Host smart-06d1078f-e250-4b72-9228-155d71c86f0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529806296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.3529806296
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_disabled.4089067179
Short name T445
Test name
Test status
Simulation time 141842328014 ps
CPU time 220.63 seconds
Started Jul 15 04:29:42 PM PDT 24
Finished Jul 15 04:33:23 PM PDT 24
Peak memory 182924 kb
Host smart-da0eda6b-f08c-4062-9c6d-6ba16669ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089067179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_disabled.4089067179
Directory /workspace/21.rv_timer_disabled/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.1307362171
Short name T67
Test name
Test status
Simulation time 378569397216 ps
CPU time 57.29 seconds
Started Jul 15 04:29:45 PM PDT 24
Finished Jul 15 04:30:44 PM PDT 24
Peak memory 194564 kb
Host smart-2214b2e1-9a88-4c0a-934b-ae04e07bd470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307362171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.1307362171
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1655076494
Short name T63
Test name
Test status
Simulation time 184029459151 ps
CPU time 160.86 seconds
Started Jul 15 04:29:35 PM PDT 24
Finished Jul 15 04:32:17 PM PDT 24
Peak memory 182844 kb
Host smart-0f29318d-8ea2-4aec-a2bf-5e34debb7eeb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655076494 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1655076494
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.3584464796
Short name T368
Test name
Test status
Simulation time 184593713370 ps
CPU time 66.13 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 04:30:51 PM PDT 24
Peak memory 182900 kb
Host smart-9b6f5823-eb00-4b04-843b-4a7d7eda55bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584464796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.3584464796
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.2983204447
Short name T238
Test name
Test status
Simulation time 1143680097336 ps
CPU time 2423.24 seconds
Started Jul 15 04:29:49 PM PDT 24
Finished Jul 15 05:10:20 PM PDT 24
Peak memory 191116 kb
Host smart-43e9a314-6270-4971-8192-0d11854c99bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983204447 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.2983204447
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.3668433340
Short name T421
Test name
Test status
Simulation time 183902022 ps
CPU time 0.81 seconds
Started Jul 15 04:29:45 PM PDT 24
Finished Jul 15 04:29:47 PM PDT 24
Peak memory 182740 kb
Host smart-f091f26f-a25b-4b52-96c1-faffaab101ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668433340 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.3668433340
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all_with_rand_reset.3470417318
Short name T38
Test name
Test status
Simulation time 74771819126 ps
CPU time 601.92 seconds
Started Jul 15 04:29:37 PM PDT 24
Finished Jul 15 04:39:41 PM PDT 24
Peak memory 197588 kb
Host smart-783ccf97-6090-4bf2-af1c-42fcd35f555f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470417318 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all_with_rand_reset.3470417318
Directory /workspace/22.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.303781309
Short name T411
Test name
Test status
Simulation time 166832833956 ps
CPU time 149.5 seconds
Started Jul 15 04:29:50 PM PDT 24
Finished Jul 15 04:32:23 PM PDT 24
Peak memory 182872 kb
Host smart-a91c653c-5e2e-416b-8c63-eb247b6eff39
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303781309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.rv_timer_cfg_update_on_fly.303781309
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.460190113
Short name T375
Test name
Test status
Simulation time 204532997199 ps
CPU time 314.57 seconds
Started Jul 15 04:29:40 PM PDT 24
Finished Jul 15 04:34:56 PM PDT 24
Peak memory 182912 kb
Host smart-73acf4f1-89a5-4e1e-bba4-36bbe6520d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460190113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.460190113
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1103449396
Short name T171
Test name
Test status
Simulation time 84563943864 ps
CPU time 80.71 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 04:31:07 PM PDT 24
Peak memory 191108 kb
Host smart-eb396344-e1f4-4a8c-bc3d-f18aaeab49d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103449396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1103449396
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.4269878064
Short name T156
Test name
Test status
Simulation time 188461077177 ps
CPU time 161.24 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:32:31 PM PDT 24
Peak memory 191084 kb
Host smart-e6bfac07-fe80-483d-8b91-31815098970b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269878064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.4269878064
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.1505994794
Short name T105
Test name
Test status
Simulation time 285454790028 ps
CPU time 257.45 seconds
Started Jul 15 04:30:02 PM PDT 24
Finished Jul 15 04:34:20 PM PDT 24
Peak memory 191108 kb
Host smart-64660e43-1b7a-495f-95e7-2577fb435f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505994794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.1505994794
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.4047866309
Short name T440
Test name
Test status
Simulation time 60916676307 ps
CPU time 79.35 seconds
Started Jul 15 04:29:50 PM PDT 24
Finished Jul 15 04:31:13 PM PDT 24
Peak memory 183004 kb
Host smart-2a7f1e8c-0042-4cba-b0b5-671dedc8f551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047866309 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.4047866309
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.1786741694
Short name T420
Test name
Test status
Simulation time 13655203704 ps
CPU time 22.34 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 04:30:17 PM PDT 24
Peak memory 191092 kb
Host smart-b79cb29d-d2fd-474f-8342-16a38a9d3f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786741694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.1786741694
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.3677501115
Short name T402
Test name
Test status
Simulation time 404435673028 ps
CPU time 332.96 seconds
Started Jul 15 04:29:40 PM PDT 24
Finished Jul 15 04:35:14 PM PDT 24
Peak memory 182888 kb
Host smart-987ce6f2-c4e3-48c7-ae59-b01972d5bf7b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677501115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.3677501115
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.2874055899
Short name T388
Test name
Test status
Simulation time 78905348999 ps
CPU time 111.28 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 04:31:36 PM PDT 24
Peak memory 182896 kb
Host smart-0843d83c-9b20-4073-9325-5aee3fe3ae91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874055899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.2874055899
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random.3733802242
Short name T324
Test name
Test status
Simulation time 75767680990 ps
CPU time 45.18 seconds
Started Jul 15 04:29:46 PM PDT 24
Finished Jul 15 04:30:33 PM PDT 24
Peak memory 182868 kb
Host smart-e20e4663-a643-4a00-8b9c-56e30b04f616
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733802242 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.3733802242
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.3690545191
Short name T149
Test name
Test status
Simulation time 220995965933 ps
CPU time 911.05 seconds
Started Jul 15 04:29:41 PM PDT 24
Finished Jul 15 04:44:53 PM PDT 24
Peak memory 191148 kb
Host smart-d9a24aac-3601-4103-a44c-cf8448eef2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690545191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.3690545191
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1492388747
Short name T235
Test name
Test status
Simulation time 417009633603 ps
CPU time 193.39 seconds
Started Jul 15 04:29:41 PM PDT 24
Finished Jul 15 04:32:55 PM PDT 24
Peak memory 182888 kb
Host smart-e9fe6464-11bc-4b45-920a-8169b76edda5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492388747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1492388747
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.968405245
Short name T370
Test name
Test status
Simulation time 394757332410 ps
CPU time 161.45 seconds
Started Jul 15 04:29:42 PM PDT 24
Finished Jul 15 04:32:24 PM PDT 24
Peak memory 182908 kb
Host smart-5c3a1fd9-4e17-4084-bd1b-35e932e02d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968405245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.968405245
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.2261457859
Short name T231
Test name
Test status
Simulation time 4605822026 ps
CPU time 75.12 seconds
Started Jul 15 04:29:39 PM PDT 24
Finished Jul 15 04:30:55 PM PDT 24
Peak memory 182900 kb
Host smart-eafd7e21-5ea4-4073-9e90-0c8af889e3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261457859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.2261457859
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3537661550
Short name T356
Test name
Test status
Simulation time 443670673012 ps
CPU time 1260.51 seconds
Started Jul 15 04:29:43 PM PDT 24
Finished Jul 15 04:50:45 PM PDT 24
Peak memory 191172 kb
Host smart-05e944a0-3af0-42ed-801e-0a9db4c03246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537661550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3537661550
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3403919623
Short name T187
Test name
Test status
Simulation time 209966223329 ps
CPU time 338.83 seconds
Started Jul 15 04:29:46 PM PDT 24
Finished Jul 15 04:35:27 PM PDT 24
Peak memory 182860 kb
Host smart-9aed4074-37ae-4f4d-b531-8be58b42f4a9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403919623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3403919623
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.2576522680
Short name T386
Test name
Test status
Simulation time 149617874396 ps
CPU time 217.07 seconds
Started Jul 15 04:29:37 PM PDT 24
Finished Jul 15 04:33:16 PM PDT 24
Peak memory 182872 kb
Host smart-f918ac0b-e4b5-4fdf-957c-fbb35668520b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576522680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.2576522680
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random.2543709392
Short name T265
Test name
Test status
Simulation time 208099133292 ps
CPU time 792.48 seconds
Started Jul 15 04:29:50 PM PDT 24
Finished Jul 15 04:43:06 PM PDT 24
Peak memory 191228 kb
Host smart-e1a1c79e-0d1c-413e-afbb-2b3ef157d300
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543709392 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.2543709392
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.4140269875
Short name T365
Test name
Test status
Simulation time 86637273 ps
CPU time 0.69 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 04:29:52 PM PDT 24
Peak memory 182728 kb
Host smart-b5fa42d0-5d21-4321-9733-8ca1356a5fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140269875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.4140269875
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.4121607550
Short name T140
Test name
Test status
Simulation time 973993302028 ps
CPU time 469.8 seconds
Started Jul 15 04:29:35 PM PDT 24
Finished Jul 15 04:37:26 PM PDT 24
Peak memory 182884 kb
Host smart-a06c0b3c-7207-4a67-a6b5-bf332760ca67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121607550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.4121607550
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3732853279
Short name T366
Test name
Test status
Simulation time 596023939439 ps
CPU time 206.43 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 04:33:11 PM PDT 24
Peak memory 182904 kb
Host smart-6b023100-d6f2-4b35-a592-9129a2cf7f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732853279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3732853279
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.2781148748
Short name T229
Test name
Test status
Simulation time 93225705097 ps
CPU time 137.51 seconds
Started Jul 15 04:29:50 PM PDT 24
Finished Jul 15 04:32:10 PM PDT 24
Peak memory 191100 kb
Host smart-101dcef1-2f0d-4c4c-90f4-cf5810ff5b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781148748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.2781148748
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.990008765
Short name T287
Test name
Test status
Simulation time 90668062957 ps
CPU time 31.71 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:30:21 PM PDT 24
Peak memory 182828 kb
Host smart-7befdbdf-e06a-47d9-9351-1b1d708daa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990008765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.990008765
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1083096095
Short name T438
Test name
Test status
Simulation time 137928468585 ps
CPU time 222.88 seconds
Started Jul 15 04:29:45 PM PDT 24
Finished Jul 15 04:33:36 PM PDT 24
Peak memory 182912 kb
Host smart-03cd6056-4c75-49ba-b71a-08c3d02fb516
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083096095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1083096095
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2237627240
Short name T400
Test name
Test status
Simulation time 106295324342 ps
CPU time 100.02 seconds
Started Jul 15 04:29:50 PM PDT 24
Finished Jul 15 04:31:41 PM PDT 24
Peak memory 182852 kb
Host smart-28978988-79e0-4ac8-a86d-7f847966065b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237627240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2237627240
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.2354408025
Short name T191
Test name
Test status
Simulation time 441578160249 ps
CPU time 1183.25 seconds
Started Jul 15 04:29:49 PM PDT 24
Finished Jul 15 04:49:35 PM PDT 24
Peak memory 191096 kb
Host smart-601c1513-5862-42d8-ae4a-05f648e7128a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354408025 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2354408025
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.806543254
Short name T361
Test name
Test status
Simulation time 191058652844 ps
CPU time 548.42 seconds
Started Jul 15 04:29:40 PM PDT 24
Finished Jul 15 04:38:50 PM PDT 24
Peak memory 195256 kb
Host smart-fc466b20-6799-42b5-a704-f4ed40d83b95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806543254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
806543254
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.3072243333
Short name T352
Test name
Test status
Simulation time 1555578225805 ps
CPU time 728.4 seconds
Started Jul 15 04:27:57 PM PDT 24
Finished Jul 15 04:40:11 PM PDT 24
Peak memory 182912 kb
Host smart-40e85c21-16ae-4f96-8ac5-9dbd8ada037d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072243333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.3072243333
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.1833693207
Short name T426
Test name
Test status
Simulation time 71784642438 ps
CPU time 57.82 seconds
Started Jul 15 04:23:57 PM PDT 24
Finished Jul 15 04:24:55 PM PDT 24
Peak memory 182884 kb
Host smart-ed6a6141-9d93-416d-bfd6-ee51c01d4197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833693207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.1833693207
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.344413421
Short name T293
Test name
Test status
Simulation time 13796814779 ps
CPU time 8.13 seconds
Started Jul 15 04:23:15 PM PDT 24
Finished Jul 15 04:23:24 PM PDT 24
Peak memory 183240 kb
Host smart-b319f5b6-7a56-4e39-b65a-5df896b68730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344413421 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.344413421
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.1615738383
Short name T297
Test name
Test status
Simulation time 520839039954 ps
CPU time 142.28 seconds
Started Jul 15 04:23:44 PM PDT 24
Finished Jul 15 04:26:06 PM PDT 24
Peak memory 183008 kb
Host smart-cd1dc0ff-a82e-466c-a20f-5a09e9a316b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615738383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.1615738383
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.889811793
Short name T16
Test name
Test status
Simulation time 260691170 ps
CPU time 0.8 seconds
Started Jul 15 04:27:50 PM PDT 24
Finished Jul 15 04:27:54 PM PDT 24
Peak memory 213080 kb
Host smart-5d25f117-0f1c-4ed8-99fb-6aa8dce4ea55
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889811793 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.889811793
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.280300855
Short name T273
Test name
Test status
Simulation time 1083408805486 ps
CPU time 478.99 seconds
Started Jul 15 04:27:29 PM PDT 24
Finished Jul 15 04:35:29 PM PDT 24
Peak memory 191204 kb
Host smart-90161849-3344-4f1b-b541-ecda2d060452
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280300855 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.280300855
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2012669886
Short name T137
Test name
Test status
Simulation time 391833384879 ps
CPU time 624.96 seconds
Started Jul 15 04:29:45 PM PDT 24
Finished Jul 15 04:40:12 PM PDT 24
Peak memory 182908 kb
Host smart-058b4dd2-af94-4a52-8854-1915661f6b60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012669886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2012669886
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3057697092
Short name T434
Test name
Test status
Simulation time 506394175366 ps
CPU time 201.29 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:33:11 PM PDT 24
Peak memory 182932 kb
Host smart-9f240aa6-915d-45fb-a61d-3c30775c1d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057697092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3057697092
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.850846994
Short name T52
Test name
Test status
Simulation time 572512129108 ps
CPU time 466.04 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:37:40 PM PDT 24
Peak memory 182852 kb
Host smart-bb41e85c-aff0-4514-b7e0-6a70cbcc1374
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850846994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all.
850846994
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3311545981
Short name T415
Test name
Test status
Simulation time 272038177203 ps
CPU time 235.29 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 04:33:40 PM PDT 24
Peak memory 182900 kb
Host smart-50a421c3-9677-4b92-8dec-7a337f8220cb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311545981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3311545981
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2237237021
Short name T383
Test name
Test status
Simulation time 166001026768 ps
CPU time 224.96 seconds
Started Jul 15 04:29:34 PM PDT 24
Finished Jul 15 04:33:20 PM PDT 24
Peak memory 182876 kb
Host smart-c3d7c84e-5c38-4996-b0f9-625cd4d15c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237237021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2237237021
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.4130765099
Short name T147
Test name
Test status
Simulation time 182935766985 ps
CPU time 138.71 seconds
Started Jul 15 04:29:35 PM PDT 24
Finished Jul 15 04:31:56 PM PDT 24
Peak memory 191236 kb
Host smart-817a63f5-5b7b-4d42-b356-8b361de6db78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130765099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.4130765099
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.3906251171
Short name T40
Test name
Test status
Simulation time 3342367884 ps
CPU time 61.8 seconds
Started Jul 15 04:29:39 PM PDT 24
Finished Jul 15 04:30:42 PM PDT 24
Peak memory 182848 kb
Host smart-b117df12-fdd4-4376-9af5-72d683be776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906251171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.3906251171
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3134254951
Short name T315
Test name
Test status
Simulation time 802702785739 ps
CPU time 3590.91 seconds
Started Jul 15 04:29:50 PM PDT 24
Finished Jul 15 05:29:44 PM PDT 24
Peak memory 191052 kb
Host smart-f6765661-0ce6-4354-a798-16f3df35b683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134254951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3134254951
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.3363576528
Short name T272
Test name
Test status
Simulation time 923441726185 ps
CPU time 829.54 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 04:43:40 PM PDT 24
Peak memory 182904 kb
Host smart-54a526d1-9c70-485c-8280-923af1d27004
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363576528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.3363576528
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.276505238
Short name T399
Test name
Test status
Simulation time 58275281316 ps
CPU time 88.75 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 04:31:27 PM PDT 24
Peak memory 182912 kb
Host smart-468b6bd0-9e55-4a2a-8026-dea28016dd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276505238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.276505238
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.3143276740
Short name T5
Test name
Test status
Simulation time 100830962233 ps
CPU time 1981.9 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 05:02:57 PM PDT 24
Peak memory 191204 kb
Host smart-6ae95b97-2409-45d7-8fa5-8082f6e4c3b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143276740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.3143276740
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.616523396
Short name T344
Test name
Test status
Simulation time 159462672857 ps
CPU time 123.45 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:31:59 PM PDT 24
Peak memory 182868 kb
Host smart-f0a8bf18-cb70-448d-aa37-7b36575021fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616523396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all.
616523396
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.4127457314
Short name T414
Test name
Test status
Simulation time 79005782977 ps
CPU time 53.78 seconds
Started Jul 15 04:29:57 PM PDT 24
Finished Jul 15 04:30:52 PM PDT 24
Peak memory 182888 kb
Host smart-002093eb-2357-4125-a6c0-a2912c67d7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127457314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.4127457314
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.2774015649
Short name T256
Test name
Test status
Simulation time 563236636602 ps
CPU time 165.98 seconds
Started Jul 15 04:30:03 PM PDT 24
Finished Jul 15 04:32:50 PM PDT 24
Peak memory 191444 kb
Host smart-dcfcbcbe-d0be-45c9-8980-84e19e203edd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774015649 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.2774015649
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.655670996
Short name T109
Test name
Test status
Simulation time 53187687929 ps
CPU time 538.8 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:38:49 PM PDT 24
Peak memory 191080 kb
Host smart-2daac958-753a-445b-8868-300f9dea63cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655670996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.655670996
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.803227112
Short name T37
Test name
Test status
Simulation time 59678897804 ps
CPU time 646.38 seconds
Started Jul 15 04:29:49 PM PDT 24
Finished Jul 15 04:40:38 PM PDT 24
Peak memory 205808 kb
Host smart-1b871d90-b3e5-462b-9377-0dd9a340c6b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803227112 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.803227112
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.68370925
Short name T204
Test name
Test status
Simulation time 375630557271 ps
CPU time 172.76 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:32:49 PM PDT 24
Peak memory 182932 kb
Host smart-6025cd6e-fea7-4e40-bd08-732fa1e312da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68370925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.rv_timer_cfg_update_on_fly.68370925
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.3720888435
Short name T378
Test name
Test status
Simulation time 115058832609 ps
CPU time 81.81 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 04:31:08 PM PDT 24
Peak memory 182976 kb
Host smart-5c15029e-3e4b-4362-9865-c46d58f8c417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720888435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.3720888435
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.2262598031
Short name T234
Test name
Test status
Simulation time 56982506214 ps
CPU time 47.48 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:30:37 PM PDT 24
Peak memory 182860 kb
Host smart-15c71658-5bc4-4bd0-b62a-7cfd11a2e8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262598031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.2262598031
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.4084279557
Short name T323
Test name
Test status
Simulation time 735894949848 ps
CPU time 2267.82 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 05:07:37 PM PDT 24
Peak memory 191108 kb
Host smart-58c95b46-ea82-43c0-b830-3374d203b678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084279557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.4084279557
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.1081447410
Short name T64
Test name
Test status
Simulation time 37127181593 ps
CPU time 20.2 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:30:14 PM PDT 24
Peak memory 182900 kb
Host smart-a3f1fd4f-ea3a-44a5-bd8e-e1f5d31003c1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081447410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.1081447410
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2119667429
Short name T397
Test name
Test status
Simulation time 276487851833 ps
CPU time 213.51 seconds
Started Jul 15 04:29:56 PM PDT 24
Finished Jul 15 04:33:31 PM PDT 24
Peak memory 182900 kb
Host smart-3fb51af9-d0b5-4512-b51f-0126c9b37a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119667429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2119667429
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.56092251
Short name T74
Test name
Test status
Simulation time 11427981607 ps
CPU time 18.24 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:30:12 PM PDT 24
Peak memory 191096 kb
Host smart-9bc5f465-0a26-4a4d-967d-2882c10f5a60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56092251 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.56092251
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.1265776734
Short name T417
Test name
Test status
Simulation time 21129885069 ps
CPU time 78.14 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 04:31:09 PM PDT 24
Peak memory 191096 kb
Host smart-3cc1f27a-1e1f-4c78-9d70-71e5b8675b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265776734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.1265776734
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.912138429
Short name T325
Test name
Test status
Simulation time 562492733152 ps
CPU time 1120.24 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:48:35 PM PDT 24
Peak memory 191068 kb
Host smart-bab55871-3a56-4fce-932e-dc225167a637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912138429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
912138429
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.272041734
Short name T276
Test name
Test status
Simulation time 22903670818 ps
CPU time 25.16 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 04:30:11 PM PDT 24
Peak memory 182852 kb
Host smart-d9d01b95-152f-4e72-b991-ac40790baeca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272041734 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.rv_timer_cfg_update_on_fly.272041734
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3515052139
Short name T391
Test name
Test status
Simulation time 21366935372 ps
CPU time 17.55 seconds
Started Jul 15 04:30:00 PM PDT 24
Finished Jul 15 04:30:19 PM PDT 24
Peak memory 182892 kb
Host smart-455eab59-bb0f-4403-ab54-da931bd4c5cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515052139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3515052139
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.1430474968
Short name T303
Test name
Test status
Simulation time 26200764303 ps
CPU time 40.81 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 04:30:36 PM PDT 24
Peak memory 182860 kb
Host smart-d4f4b1bb-daa5-4c0c-b8de-97bf091638ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430474968 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.1430474968
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1809060520
Short name T71
Test name
Test status
Simulation time 28533252889 ps
CPU time 16.94 seconds
Started Jul 15 04:30:08 PM PDT 24
Finished Jul 15 04:30:26 PM PDT 24
Peak memory 182900 kb
Host smart-56d22902-6575-40d4-a9a7-875679f050a7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809060520 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1809060520
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3643046327
Short name T404
Test name
Test status
Simulation time 38097265280 ps
CPU time 26.44 seconds
Started Jul 15 04:30:24 PM PDT 24
Finished Jul 15 04:30:52 PM PDT 24
Peak memory 182880 kb
Host smart-922a58ca-116b-4817-a47a-85aa1e049772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643046327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3643046327
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random.1432256685
Short name T330
Test name
Test status
Simulation time 241177360268 ps
CPU time 135.51 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:32:12 PM PDT 24
Peak memory 191060 kb
Host smart-6758b856-0027-4a12-a807-6df27f98a1c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432256685 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.1432256685
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.4018586792
Short name T313
Test name
Test status
Simulation time 171210185022 ps
CPU time 82.6 seconds
Started Jul 15 04:29:50 PM PDT 24
Finished Jul 15 04:31:16 PM PDT 24
Peak memory 191040 kb
Host smart-9a7a21a4-f770-49a9-8ce2-902ebba0b1cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018586792 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.4018586792
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.3567091020
Short name T205
Test name
Test status
Simulation time 251642631541 ps
CPU time 765.58 seconds
Started Jul 15 04:29:49 PM PDT 24
Finished Jul 15 04:42:38 PM PDT 24
Peak memory 191068 kb
Host smart-953d9b0d-f394-4c53-b5e7-f13e4115f73d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567091020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.3567091020
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.951602860
Short name T194
Test name
Test status
Simulation time 139577195232 ps
CPU time 134.94 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 04:32:10 PM PDT 24
Peak memory 183012 kb
Host smart-d2ee580f-3642-4c71-992b-dcea3b2a4a94
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951602860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.rv_timer_cfg_update_on_fly.951602860
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.27591318
Short name T412
Test name
Test status
Simulation time 359782774565 ps
CPU time 225.73 seconds
Started Jul 15 04:30:00 PM PDT 24
Finished Jul 15 04:33:47 PM PDT 24
Peak memory 182904 kb
Host smart-edaa1dac-d5f9-4907-bffc-18e31933c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27591318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.27591318
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.3090748920
Short name T180
Test name
Test status
Simulation time 274010301413 ps
CPU time 601.22 seconds
Started Jul 15 04:30:00 PM PDT 24
Finished Jul 15 04:40:03 PM PDT 24
Peak memory 191100 kb
Host smart-97054742-b6eb-42d9-8768-bdf078e6140a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090748920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.3090748920
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1385884235
Short name T364
Test name
Test status
Simulation time 14493979700 ps
CPU time 21.72 seconds
Started Jul 15 04:29:49 PM PDT 24
Finished Jul 15 04:30:14 PM PDT 24
Peak memory 182872 kb
Host smart-a56fcb9c-3a9b-49b2-83a7-9f846735ccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385884235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1385884235
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3484845218
Short name T168
Test name
Test status
Simulation time 4997856633520 ps
CPU time 1169.54 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 04:49:25 PM PDT 24
Peak memory 182820 kb
Host smart-58db3d83-e9d2-46f2-bf31-48f6cde3e82a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484845218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3484845218
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.2155654102
Short name T69
Test name
Test status
Simulation time 178687278601 ps
CPU time 117.76 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:31:52 PM PDT 24
Peak memory 183048 kb
Host smart-f9199139-021b-4e6e-9aa1-9cc26675e5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155654102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.2155654102
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.79677151
Short name T435
Test name
Test status
Simulation time 607394405398 ps
CPU time 371.98 seconds
Started Jul 15 04:29:59 PM PDT 24
Finished Jul 15 04:36:12 PM PDT 24
Peak memory 191040 kb
Host smart-7e6a4db7-ea4f-4deb-adae-331b593a427c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79677151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.79677151
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.2525193333
Short name T360
Test name
Test status
Simulation time 223868749942 ps
CPU time 436.54 seconds
Started Jul 15 04:30:42 PM PDT 24
Finished Jul 15 04:38:00 PM PDT 24
Peak memory 190872 kb
Host smart-7b5dbc5c-6cf0-4b20-bc49-ce2a0ab63fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525193333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.2525193333
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.894879837
Short name T385
Test name
Test status
Simulation time 176358459043 ps
CPU time 134.56 seconds
Started Jul 15 04:26:20 PM PDT 24
Finished Jul 15 04:28:37 PM PDT 24
Peak memory 182204 kb
Host smart-eab15b25-8176-47fe-a7ad-a6cb3dfcadd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894879837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.894879837
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.4214061628
Short name T164
Test name
Test status
Simulation time 157711968172 ps
CPU time 166.64 seconds
Started Jul 15 04:26:49 PM PDT 24
Finished Jul 15 04:29:38 PM PDT 24
Peak memory 190596 kb
Host smart-6d4662e6-dd70-4dd9-8e76-8c615509800a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214061628 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.4214061628
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.2144799511
Short name T178
Test name
Test status
Simulation time 171313403295 ps
CPU time 233.47 seconds
Started Jul 15 04:22:27 PM PDT 24
Finished Jul 15 04:26:21 PM PDT 24
Peak memory 191120 kb
Host smart-296e410d-79c2-4863-bf3e-6720ab979e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144799511 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.2144799511
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.1124004577
Short name T18
Test name
Test status
Simulation time 71390659 ps
CPU time 0.74 seconds
Started Jul 15 04:29:27 PM PDT 24
Finished Jul 15 04:29:29 PM PDT 24
Peak memory 213232 kb
Host smart-bc29a815-0f41-47f9-b07c-361c7bd467b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124004577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.1124004577
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.4256805951
Short name T107
Test name
Test status
Simulation time 810343686576 ps
CPU time 776.09 seconds
Started Jul 15 04:26:48 PM PDT 24
Finished Jul 15 04:39:46 PM PDT 24
Peak memory 190796 kb
Host smart-58ca162c-3819-4067-aea5-cfa5a4d306be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256805951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
4256805951
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.2018148245
Short name T76
Test name
Test status
Simulation time 105834418589 ps
CPU time 166.04 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:33:03 PM PDT 24
Peak memory 182896 kb
Host smart-d5382213-5752-4bd1-a8a3-a7b21bcb9255
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018148245 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.2018148245
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.440682589
Short name T410
Test name
Test status
Simulation time 135164837055 ps
CPU time 193.75 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:33:03 PM PDT 24
Peak memory 182844 kb
Host smart-11613dad-4d01-4fba-9be6-9b8391b80710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440682589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.440682589
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.3874513021
Short name T258
Test name
Test status
Simulation time 171073442763 ps
CPU time 838.22 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 04:43:53 PM PDT 24
Peak memory 191068 kb
Host smart-83ac7f01-88b3-431d-89dc-4d8a2c10a8be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874513021 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.3874513021
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.694554580
Short name T22
Test name
Test status
Simulation time 662206324 ps
CPU time 0.8 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 04:29:55 PM PDT 24
Peak memory 191372 kb
Host smart-9400d8ae-fc1f-415c-ac10-786d4eadbefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694554580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.694554580
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.2356836324
Short name T25
Test name
Test status
Simulation time 313327510871 ps
CPU time 265.55 seconds
Started Jul 15 04:29:57 PM PDT 24
Finished Jul 15 04:34:24 PM PDT 24
Peak memory 182956 kb
Host smart-55409802-3ece-4375-a041-3965303fbfcb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356836324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.rv_timer_cfg_update_on_fly.2356836324
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.2990935785
Short name T448
Test name
Test status
Simulation time 90606738950 ps
CPU time 141.75 seconds
Started Jul 15 04:29:56 PM PDT 24
Finished Jul 15 04:32:19 PM PDT 24
Peak memory 182828 kb
Host smart-8ee9d2ef-7edc-4b69-8823-ec49438a2b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990935785 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.2990935785
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.3377432867
Short name T190
Test name
Test status
Simulation time 424550967468 ps
CPU time 150.12 seconds
Started Jul 15 04:30:07 PM PDT 24
Finished Jul 15 04:32:38 PM PDT 24
Peak memory 191120 kb
Host smart-69b22c25-096e-4d71-90bb-ee109d7121fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377432867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.3377432867
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.502283426
Short name T418
Test name
Test status
Simulation time 6920567429 ps
CPU time 11.33 seconds
Started Jul 15 04:29:55 PM PDT 24
Finished Jul 15 04:30:08 PM PDT 24
Peak memory 191120 kb
Host smart-89953bda-5f39-4329-bfe1-8198ce52a35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502283426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.502283426
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3207977476
Short name T237
Test name
Test status
Simulation time 3173983345475 ps
CPU time 807.72 seconds
Started Jul 15 04:29:56 PM PDT 24
Finished Jul 15 04:43:25 PM PDT 24
Peak memory 182904 kb
Host smart-c8978414-c929-41c1-8a90-9c8519b4fa5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207977476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3207977476
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3592459308
Short name T428
Test name
Test status
Simulation time 88626257302 ps
CPU time 70.92 seconds
Started Jul 15 04:30:09 PM PDT 24
Finished Jul 15 04:31:21 PM PDT 24
Peak memory 182880 kb
Host smart-28b0c9fd-f600-449f-a885-c6f97a473275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592459308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3592459308
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.3863295062
Short name T199
Test name
Test status
Simulation time 39596767941 ps
CPU time 169.66 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:32:40 PM PDT 24
Peak memory 194620 kb
Host smart-b03fb50c-f38e-406e-a40c-50022da58518
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863295062 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.3863295062
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3289075213
Short name T310
Test name
Test status
Simulation time 467972924153 ps
CPU time 238.05 seconds
Started Jul 15 04:29:54 PM PDT 24
Finished Jul 15 04:33:54 PM PDT 24
Peak memory 182860 kb
Host smart-0918b979-5718-4414-8d09-1d7c73cad7a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289075213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3289075213
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.136283780
Short name T394
Test name
Test status
Simulation time 290336484066 ps
CPU time 205.03 seconds
Started Jul 15 04:29:52 PM PDT 24
Finished Jul 15 04:33:20 PM PDT 24
Peak memory 182900 kb
Host smart-7384b9c5-616a-4812-bb50-0e8dbd4a0b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136283780 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.136283780
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.613591204
Short name T122
Test name
Test status
Simulation time 12359285123 ps
CPU time 21.63 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:30:16 PM PDT 24
Peak memory 182912 kb
Host smart-5219f1d0-84c4-48ae-b96e-53fd2d1a6e9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613591204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.613591204
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3063210961
Short name T432
Test name
Test status
Simulation time 2119123425 ps
CPU time 2.37 seconds
Started Jul 15 04:29:49 PM PDT 24
Finished Jul 15 04:29:55 PM PDT 24
Peak memory 191020 kb
Host smart-4b9cb9c9-3406-4c13-8d73-5b4ef9045ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063210961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3063210961
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.12062256
Short name T318
Test name
Test status
Simulation time 636872780765 ps
CPU time 359.83 seconds
Started Jul 15 04:29:49 PM PDT 24
Finished Jul 15 04:35:52 PM PDT 24
Peak memory 191116 kb
Host smart-b5984200-7449-4576-81ad-6c24024b68ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12062256 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all.12062256
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.3191563471
Short name T328
Test name
Test status
Simulation time 878719902679 ps
CPU time 777.67 seconds
Started Jul 15 04:29:57 PM PDT 24
Finished Jul 15 04:42:56 PM PDT 24
Peak memory 182824 kb
Host smart-76422bf6-2c7e-4d4d-b924-f123de9381c6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191563471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.3191563471
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.2954682577
Short name T427
Test name
Test status
Simulation time 126919454750 ps
CPU time 168.59 seconds
Started Jul 15 04:30:02 PM PDT 24
Finished Jul 15 04:32:52 PM PDT 24
Peak memory 182888 kb
Host smart-15f85a13-d079-4b1c-99c0-154482084bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954682577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.2954682577
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.1114989414
Short name T103
Test name
Test status
Simulation time 191853593438 ps
CPU time 299.92 seconds
Started Jul 15 04:29:46 PM PDT 24
Finished Jul 15 04:34:48 PM PDT 24
Peak memory 194828 kb
Host smart-896c7ea4-4ee0-400d-b1ca-e7d93747147a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114989414 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.1114989414
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.4136793194
Short name T346
Test name
Test status
Simulation time 51105007731 ps
CPU time 34.4 seconds
Started Jul 15 04:29:56 PM PDT 24
Finished Jul 15 04:30:32 PM PDT 24
Peak memory 182932 kb
Host smart-76b9450e-15c3-4270-a3b1-7ca2f735bcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136793194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.4136793194
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.208959230
Short name T35
Test name
Test status
Simulation time 31806479862 ps
CPU time 153.71 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:32:23 PM PDT 24
Peak memory 197148 kb
Host smart-2e6ce35d-b576-47ce-a845-b9e24638e453
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208959230 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.208959230
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.3821138920
Short name T405
Test name
Test status
Simulation time 71078870793 ps
CPU time 100.06 seconds
Started Jul 15 04:30:11 PM PDT 24
Finished Jul 15 04:31:52 PM PDT 24
Peak memory 182936 kb
Host smart-ec1ede9e-acd7-4d7f-99d2-da7e462e76e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821138920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.3821138920
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1467593675
Short name T349
Test name
Test status
Simulation time 101719499814 ps
CPU time 137.06 seconds
Started Jul 15 04:29:48 PM PDT 24
Finished Jul 15 04:32:08 PM PDT 24
Peak memory 191072 kb
Host smart-81947275-1128-4abb-970b-d0631322092f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467593675 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1467593675
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2935454461
Short name T131
Test name
Test status
Simulation time 64010477292 ps
CPU time 202.81 seconds
Started Jul 15 04:29:56 PM PDT 24
Finished Jul 15 04:33:25 PM PDT 24
Peak memory 182816 kb
Host smart-4d77ec55-084c-4164-abcd-34dbe1882dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935454461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2935454461
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1220254284
Short name T439
Test name
Test status
Simulation time 109479863603 ps
CPU time 169.67 seconds
Started Jul 15 04:29:54 PM PDT 24
Finished Jul 15 04:32:46 PM PDT 24
Peak memory 182892 kb
Host smart-cdf67e00-54f5-410b-a16b-bd06587a48e7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220254284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1220254284
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.2435732521
Short name T441
Test name
Test status
Simulation time 493227647742 ps
CPU time 198.72 seconds
Started Jul 15 04:29:58 PM PDT 24
Finished Jul 15 04:33:18 PM PDT 24
Peak memory 181976 kb
Host smart-f38ef433-a315-4ed9-ad68-4ea406fe6e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435732521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.2435732521
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.2547358387
Short name T279
Test name
Test status
Simulation time 100473873404 ps
CPU time 206.79 seconds
Started Jul 15 04:29:59 PM PDT 24
Finished Jul 15 04:33:27 PM PDT 24
Peak memory 191084 kb
Host smart-8e4e60d2-2a7a-46d0-b68d-7fd8178fc321
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547358387 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2547358387
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.3262175321
Short name T416
Test name
Test status
Simulation time 30974957903 ps
CPU time 51.06 seconds
Started Jul 15 04:29:51 PM PDT 24
Finished Jul 15 04:30:45 PM PDT 24
Peak memory 194468 kb
Host smart-0c00eb60-a143-4632-874f-c699881a1c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262175321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.3262175321
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2728837416
Short name T251
Test name
Test status
Simulation time 225819136580 ps
CPU time 336.41 seconds
Started Jul 15 04:29:54 PM PDT 24
Finished Jul 15 04:35:33 PM PDT 24
Peak memory 183228 kb
Host smart-859664f8-0093-4b66-8fb2-a4b9d221f112
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728837416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2728837416
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.859458396
Short name T429
Test name
Test status
Simulation time 60053770294 ps
CPU time 21.19 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:30:17 PM PDT 24
Peak memory 182880 kb
Host smart-0f2c2f1b-7a61-4bba-8bb1-d470b99e8568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859458396 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.859458396
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.1491852096
Short name T291
Test name
Test status
Simulation time 131687281626 ps
CPU time 457.7 seconds
Started Jul 15 04:30:03 PM PDT 24
Finished Jul 15 04:37:42 PM PDT 24
Peak memory 191108 kb
Host smart-f6ee5eec-f8c3-4404-bea3-d0670a2126ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491852096 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.1491852096
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.3771106535
Short name T389
Test name
Test status
Simulation time 169560695 ps
CPU time 1.27 seconds
Started Jul 15 04:30:01 PM PDT 24
Finished Jul 15 04:30:03 PM PDT 24
Peak memory 191076 kb
Host smart-74eba38a-9bb3-4016-bb07-8a5766e08d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771106535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.3771106535
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.419864746
Short name T286
Test name
Test status
Simulation time 1113697526403 ps
CPU time 388.46 seconds
Started Jul 15 04:29:55 PM PDT 24
Finished Jul 15 04:36:26 PM PDT 24
Peak memory 195916 kb
Host smart-242009ba-43e4-4774-a7a3-23b018e79d74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419864746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all.
419864746
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.751384886
Short name T288
Test name
Test status
Simulation time 109098920765 ps
CPU time 166.78 seconds
Started Jul 15 04:30:01 PM PDT 24
Finished Jul 15 04:32:49 PM PDT 24
Peak memory 182908 kb
Host smart-8a35806d-64e0-4ea5-acbe-d6b55a1f0a47
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751384886 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.rv_timer_cfg_update_on_fly.751384886
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2009725826
Short name T403
Test name
Test status
Simulation time 86845961864 ps
CPU time 120.66 seconds
Started Jul 15 04:30:15 PM PDT 24
Finished Jul 15 04:32:18 PM PDT 24
Peak memory 182852 kb
Host smart-825ad2b4-9116-4500-9882-e5296383ea1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009725826 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2009725826
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.749547400
Short name T167
Test name
Test status
Simulation time 595720628772 ps
CPU time 502.14 seconds
Started Jul 15 04:29:55 PM PDT 24
Finished Jul 15 04:38:19 PM PDT 24
Peak memory 191076 kb
Host smart-f81265c4-a97e-40cb-aa3a-58994bf75087
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749547400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.749547400
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.1424021980
Short name T431
Test name
Test status
Simulation time 97703010 ps
CPU time 0.66 seconds
Started Jul 15 04:30:04 PM PDT 24
Finished Jul 15 04:30:06 PM PDT 24
Peak memory 182704 kb
Host smart-89c6aec1-328e-4a6c-9057-376d98a9eedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424021980 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.1424021980
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2792896024
Short name T165
Test name
Test status
Simulation time 16295266159 ps
CPU time 14.04 seconds
Started Jul 15 04:29:54 PM PDT 24
Finished Jul 15 04:30:10 PM PDT 24
Peak memory 182968 kb
Host smart-99daa658-4c72-4526-9a86-5f407f679eed
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792896024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2792896024
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1067148018
Short name T8
Test name
Test status
Simulation time 304038524137 ps
CPU time 78.32 seconds
Started Jul 15 04:30:06 PM PDT 24
Finished Jul 15 04:31:26 PM PDT 24
Peak memory 182920 kb
Host smart-ddb094f0-a208-4fef-b7b0-38501214c3c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067148018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1067148018
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.984618818
Short name T192
Test name
Test status
Simulation time 1278057207355 ps
CPU time 267.99 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:34:24 PM PDT 24
Peak memory 191080 kb
Host smart-ceed2c1c-5629-400d-a46a-3edc73a296af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984618818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.984618818
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1925988742
Short name T362
Test name
Test status
Simulation time 12336268905 ps
CPU time 24.32 seconds
Started Jul 15 04:30:10 PM PDT 24
Finished Jul 15 04:30:36 PM PDT 24
Peak memory 182880 kb
Host smart-542f58b1-403b-43d8-b6b1-712065df38d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925988742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1925988742
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.4202092613
Short name T326
Test name
Test status
Simulation time 188427895985 ps
CPU time 71.07 seconds
Started Jul 15 04:29:15 PM PDT 24
Finished Jul 15 04:30:27 PM PDT 24
Peak memory 182904 kb
Host smart-6ba39002-5826-492c-a8f5-d6534d27c06a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202092613 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.4202092613
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3978456090
Short name T373
Test name
Test status
Simulation time 332284774047 ps
CPU time 134.52 seconds
Started Jul 15 04:29:29 PM PDT 24
Finished Jul 15 04:31:45 PM PDT 24
Peak memory 182868 kb
Host smart-a3585f4f-1a0a-4543-83dc-43f3a3125757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978456090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3978456090
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1106669122
Short name T72
Test name
Test status
Simulation time 124534205333 ps
CPU time 59.03 seconds
Started Jul 15 04:29:26 PM PDT 24
Finished Jul 15 04:30:26 PM PDT 24
Peak memory 182920 kb
Host smart-e73ca874-66b0-4ab0-9bb8-b779eef7703d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106669122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1106669122
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.704641346
Short name T367
Test name
Test status
Simulation time 17611294 ps
CPU time 0.54 seconds
Started Jul 15 04:29:37 PM PDT 24
Finished Jul 15 04:29:40 PM PDT 24
Peak memory 182728 kb
Host smart-46c89a96-ebd7-4bb4-8b2b-dc426724192f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704641346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.704641346
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.3301125584
Short name T398
Test name
Test status
Simulation time 2281937932175 ps
CPU time 618.56 seconds
Started Jul 15 04:29:21 PM PDT 24
Finished Jul 15 04:39:40 PM PDT 24
Peak memory 191060 kb
Host smart-f0731edd-248f-4d16-af18-99ad3b90a9de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301125584 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
3301125584
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.3198268748
Short name T274
Test name
Test status
Simulation time 399882260498 ps
CPU time 283.8 seconds
Started Jul 15 04:29:59 PM PDT 24
Finished Jul 15 04:34:44 PM PDT 24
Peak memory 191120 kb
Host smart-8d6374ea-d300-4963-976b-65e010f1ae66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198268748 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.3198268748
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.1929888908
Short name T249
Test name
Test status
Simulation time 1367971705859 ps
CPU time 319.78 seconds
Started Jul 15 04:30:05 PM PDT 24
Finished Jul 15 04:35:27 PM PDT 24
Peak memory 191116 kb
Host smart-63ee3a39-7d8b-481d-bf0b-1fae9b4af299
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929888908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.1929888908
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.3834554005
Short name T250
Test name
Test status
Simulation time 143200910404 ps
CPU time 806.37 seconds
Started Jul 15 04:30:03 PM PDT 24
Finished Jul 15 04:43:31 PM PDT 24
Peak memory 191044 kb
Host smart-b3e435c4-8208-4e38-ae26-db49aa7f429a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834554005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.3834554005
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.4098303104
Short name T449
Test name
Test status
Simulation time 133008409680 ps
CPU time 139.5 seconds
Started Jul 15 04:30:02 PM PDT 24
Finished Jul 15 04:32:22 PM PDT 24
Peak memory 194480 kb
Host smart-04d9368f-3b55-49b1-abc4-966b3d847981
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098303104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.4098303104
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.2330485536
Short name T359
Test name
Test status
Simulation time 446721824213 ps
CPU time 222.93 seconds
Started Jul 15 04:30:09 PM PDT 24
Finished Jul 15 04:33:54 PM PDT 24
Peak memory 191068 kb
Host smart-bc767afe-9b20-4c8b-bb7e-94c0de478b48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330485536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.2330485536
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.493425398
Short name T446
Test name
Test status
Simulation time 73293679345 ps
CPU time 110.83 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:31:47 PM PDT 24
Peak memory 191072 kb
Host smart-faa67c9c-4767-4ff0-94dd-568a89f0cbb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493425398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.493425398
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3052632731
Short name T68
Test name
Test status
Simulation time 4110921546455 ps
CPU time 1441.8 seconds
Started Jul 15 04:29:37 PM PDT 24
Finished Jul 15 04:53:41 PM PDT 24
Peak memory 182892 kb
Host smart-46446938-b4f5-4246-a604-52d75ff25d91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052632731 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3052632731
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.512082639
Short name T395
Test name
Test status
Simulation time 47583719819 ps
CPU time 21.09 seconds
Started Jul 15 04:29:19 PM PDT 24
Finished Jul 15 04:29:40 PM PDT 24
Peak memory 182904 kb
Host smart-5f14264b-634b-4dce-91b6-ddba72d45381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512082639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.512082639
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.2082943051
Short name T207
Test name
Test status
Simulation time 133558160234 ps
CPU time 165.03 seconds
Started Jul 15 04:29:14 PM PDT 24
Finished Jul 15 04:32:00 PM PDT 24
Peak memory 191108 kb
Host smart-d13c68b2-b491-4377-b028-1ec73ea77d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082943051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.2082943051
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1879788973
Short name T444
Test name
Test status
Simulation time 43983105814 ps
CPU time 21.11 seconds
Started Jul 15 04:29:36 PM PDT 24
Finished Jul 15 04:29:59 PM PDT 24
Peak memory 194000 kb
Host smart-67d996b0-56e2-47b8-8920-f8e970d8f54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879788973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1879788973
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/60.rv_timer_random.1495420769
Short name T425
Test name
Test status
Simulation time 15119395859 ps
CPU time 24.94 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:30:42 PM PDT 24
Peak memory 182872 kb
Host smart-d7e7b5cc-0344-400d-b95f-48130491a10f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495420769 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1495420769
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.798461247
Short name T154
Test name
Test status
Simulation time 141872599023 ps
CPU time 208.87 seconds
Started Jul 15 04:29:59 PM PDT 24
Finished Jul 15 04:33:29 PM PDT 24
Peak memory 191036 kb
Host smart-4c0198c1-4d62-4b0f-82e4-ced0058a75d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798461247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.798461247
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.455593449
Short name T332
Test name
Test status
Simulation time 166957034241 ps
CPU time 277.25 seconds
Started Jul 15 04:30:09 PM PDT 24
Finished Jul 15 04:34:47 PM PDT 24
Peak memory 191040 kb
Host smart-41ae367f-a974-4025-9158-d9620c862887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455593449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.455593449
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.2962524979
Short name T338
Test name
Test status
Simulation time 29313586754 ps
CPU time 91.34 seconds
Started Jul 15 04:29:58 PM PDT 24
Finished Jul 15 04:31:30 PM PDT 24
Peak memory 191124 kb
Host smart-934fe060-e145-4cca-b827-3c98c9783249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962524979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.2962524979
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.1338633863
Short name T343
Test name
Test status
Simulation time 83466201159 ps
CPU time 146.09 seconds
Started Jul 15 04:30:10 PM PDT 24
Finished Jul 15 04:32:37 PM PDT 24
Peak memory 191120 kb
Host smart-a552d4d9-fef4-459c-a052-88d9c95433c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338633863 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.1338633863
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.783828749
Short name T300
Test name
Test status
Simulation time 165337321110 ps
CPU time 599.59 seconds
Started Jul 15 04:29:58 PM PDT 24
Finished Jul 15 04:39:58 PM PDT 24
Peak memory 191228 kb
Host smart-dfb0f77b-7b78-415e-b870-ff0ccc7a9fa6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783828749 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.783828749
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.521441091
Short name T113
Test name
Test status
Simulation time 475830810378 ps
CPU time 141.25 seconds
Started Jul 15 04:29:57 PM PDT 24
Finished Jul 15 04:32:19 PM PDT 24
Peak memory 191040 kb
Host smart-e2c10e81-1982-4129-a5f4-647d7f3ff3bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521441091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.521441091
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1812451343
Short name T342
Test name
Test status
Simulation time 522759387855 ps
CPU time 1931.47 seconds
Started Jul 15 04:29:57 PM PDT 24
Finished Jul 15 05:02:10 PM PDT 24
Peak memory 191076 kb
Host smart-eb5a4015-eaec-4abd-9f30-1f2239eb7b9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812451343 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1812451343
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.2112066014
Short name T348
Test name
Test status
Simulation time 1006693385775 ps
CPU time 485.95 seconds
Started Jul 15 04:29:29 PM PDT 24
Finished Jul 15 04:37:36 PM PDT 24
Peak memory 182908 kb
Host smart-046e1a04-fc8a-4a6e-8c50-daf03a92644f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112066014 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.2112066014
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.4278874902
Short name T419
Test name
Test status
Simulation time 93933608203 ps
CPU time 129.28 seconds
Started Jul 15 04:29:25 PM PDT 24
Finished Jul 15 04:31:36 PM PDT 24
Peak memory 182724 kb
Host smart-eaa508ce-374f-4f10-9998-b1ffc92f1e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278874902 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.4278874902
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.2701860375
Short name T221
Test name
Test status
Simulation time 14038206817 ps
CPU time 21.74 seconds
Started Jul 15 04:29:24 PM PDT 24
Finished Jul 15 04:29:46 PM PDT 24
Peak memory 191024 kb
Host smart-21b616a1-9840-43c1-ae3b-017af0f0a1b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701860375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.2701860375
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1462611593
Short name T144
Test name
Test status
Simulation time 76981407977 ps
CPU time 419.41 seconds
Started Jul 15 04:29:21 PM PDT 24
Finished Jul 15 04:36:26 PM PDT 24
Peak memory 194376 kb
Host smart-c806f639-98b3-434a-9d85-84038998dbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462611593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1462611593
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.296779740
Short name T407
Test name
Test status
Simulation time 673788326765 ps
CPU time 241.84 seconds
Started Jul 15 04:29:23 PM PDT 24
Finished Jul 15 04:33:25 PM PDT 24
Peak memory 191116 kb
Host smart-3344699a-8d63-4843-91cf-758e5497f100
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296779740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.296779740
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/70.rv_timer_random.968419697
Short name T196
Test name
Test status
Simulation time 200223570185 ps
CPU time 318.47 seconds
Started Jul 15 04:29:59 PM PDT 24
Finished Jul 15 04:35:18 PM PDT 24
Peak memory 191224 kb
Host smart-3f014dd0-3307-4d38-a1ae-c095b921a317
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968419697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.968419697
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.3237957694
Short name T163
Test name
Test status
Simulation time 603069039128 ps
CPU time 1375.35 seconds
Started Jul 15 04:30:01 PM PDT 24
Finished Jul 15 04:52:57 PM PDT 24
Peak memory 191084 kb
Host smart-6e36da74-d76d-42e2-8976-b84eb34378d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237957694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.3237957694
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2291298949
Short name T172
Test name
Test status
Simulation time 85620254594 ps
CPU time 1472.78 seconds
Started Jul 15 04:29:55 PM PDT 24
Finished Jul 15 04:54:30 PM PDT 24
Peak memory 191240 kb
Host smart-d8d036c2-a7c2-4fa9-b8e6-476cf7c886a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291298949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2291298949
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.4171250581
Short name T222
Test name
Test status
Simulation time 109723742514 ps
CPU time 713.18 seconds
Started Jul 15 04:30:02 PM PDT 24
Finished Jul 15 04:41:56 PM PDT 24
Peak memory 191108 kb
Host smart-ad763d16-89ac-47f0-a296-96a988a2ba0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171250581 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.4171250581
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.2626369804
Short name T133
Test name
Test status
Simulation time 35695694950 ps
CPU time 65.33 seconds
Started Jul 15 04:30:02 PM PDT 24
Finished Jul 15 04:31:08 PM PDT 24
Peak memory 191084 kb
Host smart-0139d5dd-6aff-4ad7-9374-ef3b12f766f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626369804 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.2626369804
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1822561190
Short name T139
Test name
Test status
Simulation time 223948538736 ps
CPU time 213.43 seconds
Started Jul 15 04:30:03 PM PDT 24
Finished Jul 15 04:33:37 PM PDT 24
Peak memory 191116 kb
Host smart-51591a71-bd57-45c8-8eb8-e8f4cd1ca37b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822561190 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1822561190
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3090903929
Short name T340
Test name
Test status
Simulation time 567054381469 ps
CPU time 130.35 seconds
Started Jul 15 04:30:05 PM PDT 24
Finished Jul 15 04:32:18 PM PDT 24
Peak memory 191072 kb
Host smart-ddbb17d3-dae8-4c71-a461-b3900d064dd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090903929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3090903929
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.768047648
Short name T257
Test name
Test status
Simulation time 19251746629 ps
CPU time 62.72 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:31:27 PM PDT 24
Peak memory 191088 kb
Host smart-5f24a92a-5424-4725-943c-33194c28b8f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768047648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.768047648
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1790472074
Short name T354
Test name
Test status
Simulation time 247624823524 ps
CPU time 233.99 seconds
Started Jul 15 04:29:50 PM PDT 24
Finished Jul 15 04:33:47 PM PDT 24
Peak memory 191076 kb
Host smart-3a7abf4b-5ada-45c7-8c08-63d6d00b7844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790472074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1790472074
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random.3076484389
Short name T213
Test name
Test status
Simulation time 42211645036 ps
CPU time 81.77 seconds
Started Jul 15 04:29:35 PM PDT 24
Finished Jul 15 04:30:59 PM PDT 24
Peak memory 182876 kb
Host smart-f1b03612-d49a-46bf-a25c-0c199641226f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076484389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3076484389
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.2348852706
Short name T371
Test name
Test status
Simulation time 894013003 ps
CPU time 0.83 seconds
Started Jul 15 04:29:25 PM PDT 24
Finished Jul 15 04:29:27 PM PDT 24
Peak memory 182700 kb
Host smart-ac2be362-9306-432c-b917-72b1974d3017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348852706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.2348852706
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4046867087
Short name T339
Test name
Test status
Simulation time 2928436879543 ps
CPU time 1018.93 seconds
Started Jul 15 04:29:45 PM PDT 24
Finished Jul 15 04:46:46 PM PDT 24
Peak memory 191088 kb
Host smart-177e5242-ca5e-44f3-bb30-2a3484fa8024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046867087 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4046867087
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/80.rv_timer_random.541072429
Short name T236
Test name
Test status
Simulation time 218781709731 ps
CPU time 291.56 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:34:47 PM PDT 24
Peak memory 191116 kb
Host smart-aec9710e-448f-4acb-aa82-182d918befbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541072429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.541072429
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.3443429045
Short name T254
Test name
Test status
Simulation time 291219481633 ps
CPU time 470.09 seconds
Started Jul 15 04:30:09 PM PDT 24
Finished Jul 15 04:38:01 PM PDT 24
Peak memory 191092 kb
Host smart-9a87ce65-3808-45d0-b60b-90dbcb717a0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443429045 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.3443429045
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.624966142
Short name T208
Test name
Test status
Simulation time 490525825812 ps
CPU time 308.38 seconds
Started Jul 15 04:29:59 PM PDT 24
Finished Jul 15 04:35:08 PM PDT 24
Peak memory 191104 kb
Host smart-47c4fed9-66ee-4a90-bc09-35130d8e93ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624966142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.624966142
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.846982211
Short name T108
Test name
Test status
Simulation time 212331263731 ps
CPU time 452.53 seconds
Started Jul 15 04:29:53 PM PDT 24
Finished Jul 15 04:37:28 PM PDT 24
Peak memory 191052 kb
Host smart-52e68a21-2839-45f8-845e-1a019a127017
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846982211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.846982211
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.3762780033
Short name T243
Test name
Test status
Simulation time 26417439763 ps
CPU time 77.61 seconds
Started Jul 15 04:30:08 PM PDT 24
Finished Jul 15 04:31:26 PM PDT 24
Peak memory 191072 kb
Host smart-68dfc723-a6db-4e31-9d89-72fda36c7495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762780033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3762780033
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.4290972107
Short name T219
Test name
Test status
Simulation time 137283061336 ps
CPU time 739.32 seconds
Started Jul 15 04:30:07 PM PDT 24
Finished Jul 15 04:42:28 PM PDT 24
Peak memory 193372 kb
Host smart-4f8aa40c-521c-4c99-9019-0558112286a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290972107 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.4290972107
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.951784619
Short name T442
Test name
Test status
Simulation time 45597562467 ps
CPU time 45.39 seconds
Started Jul 15 04:30:07 PM PDT 24
Finished Jul 15 04:30:54 PM PDT 24
Peak memory 182868 kb
Host smart-d29b87c8-d101-4293-a9bf-bbcd6b111b2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951784619 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.951784619
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.479752856
Short name T299
Test name
Test status
Simulation time 328740371622 ps
CPU time 307.81 seconds
Started Jul 15 04:30:13 PM PDT 24
Finished Jul 15 04:35:24 PM PDT 24
Peak memory 191092 kb
Host smart-425ee486-8648-460d-b93c-e696f7480f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479752856 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.479752856
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.3171203368
Short name T162
Test name
Test status
Simulation time 377341753879 ps
CPU time 179.77 seconds
Started Jul 15 04:30:04 PM PDT 24
Finished Jul 15 04:33:05 PM PDT 24
Peak memory 191044 kb
Host smart-91af1cbf-802f-44f0-b7fb-911220526ec3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171203368 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.3171203368
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.1037252484
Short name T246
Test name
Test status
Simulation time 983098854869 ps
CPU time 1402.2 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:53:46 PM PDT 24
Peak memory 191240 kb
Host smart-8c441f1d-b30f-4fc4-a6e7-c28837617c99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037252484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.1037252484
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2498282151
Short name T135
Test name
Test status
Simulation time 203848440569 ps
CPU time 89.52 seconds
Started Jul 15 04:29:29 PM PDT 24
Finished Jul 15 04:31:00 PM PDT 24
Peak memory 182896 kb
Host smart-934a37bd-06fd-46d1-a28b-21750dd15a69
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498282151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2498282151
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3153136143
Short name T382
Test name
Test status
Simulation time 276757677747 ps
CPU time 233.12 seconds
Started Jul 15 04:29:44 PM PDT 24
Finished Jul 15 04:33:39 PM PDT 24
Peak memory 182924 kb
Host smart-476faadb-1077-43b9-821c-62c36a3d69da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153136143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3153136143
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.747928994
Short name T292
Test name
Test status
Simulation time 92776484054 ps
CPU time 65.81 seconds
Started Jul 15 04:29:34 PM PDT 24
Finished Jul 15 04:30:41 PM PDT 24
Peak memory 182904 kb
Host smart-cbf64383-3590-4622-9543-1886702506d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747928994 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.747928994
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3220318498
Short name T121
Test name
Test status
Simulation time 62595590588 ps
CPU time 43.5 seconds
Started Jul 15 04:29:13 PM PDT 24
Finished Jul 15 04:29:57 PM PDT 24
Peak memory 191140 kb
Host smart-a8659ed5-9534-4ba4-80b3-7084be334c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220318498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3220318498
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.248296426
Short name T117
Test name
Test status
Simulation time 159437981841 ps
CPU time 228.67 seconds
Started Jul 15 04:29:47 PM PDT 24
Finished Jul 15 04:33:39 PM PDT 24
Peak memory 194736 kb
Host smart-3e2d55a6-36cd-4b2a-8d4f-0f59467d773b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248296426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.248296426
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.490398325
Short name T125
Test name
Test status
Simulation time 65301378758 ps
CPU time 105.29 seconds
Started Jul 15 04:30:23 PM PDT 24
Finished Jul 15 04:32:10 PM PDT 24
Peak memory 191208 kb
Host smart-fff3d81b-bb3a-497e-8902-9de26df74a9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490398325 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.490398325
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3249694437
Short name T218
Test name
Test status
Simulation time 67826225213 ps
CPU time 171.22 seconds
Started Jul 15 04:30:11 PM PDT 24
Finished Jul 15 04:33:04 PM PDT 24
Peak memory 191124 kb
Host smart-d314cd66-cdf8-419d-83b8-3facff50d7a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249694437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3249694437
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.3041873578
Short name T124
Test name
Test status
Simulation time 1009072928673 ps
CPU time 423.49 seconds
Started Jul 15 04:30:04 PM PDT 24
Finished Jul 15 04:37:09 PM PDT 24
Peak memory 193236 kb
Host smart-c2b1a654-572f-42d6-b49d-6362f57250ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041873578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.3041873578
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.114067880
Short name T281
Test name
Test status
Simulation time 488684936652 ps
CPU time 212.18 seconds
Started Jul 15 04:30:11 PM PDT 24
Finished Jul 15 04:33:45 PM PDT 24
Peak memory 191064 kb
Host smart-1f9dab7f-0eb9-495b-a85b-922789f4ccd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114067880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.114067880
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.1826904589
Short name T152
Test name
Test status
Simulation time 63103363983 ps
CPU time 554.98 seconds
Started Jul 15 04:30:13 PM PDT 24
Finished Jul 15 04:39:31 PM PDT 24
Peak memory 191088 kb
Host smart-ab3b5afc-9e05-4ae6-a952-f7c820e91458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826904589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.1826904589
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2161859081
Short name T212
Test name
Test status
Simulation time 140504224243 ps
CPU time 3421.18 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 05:27:19 PM PDT 24
Peak memory 191112 kb
Host smart-4d1247d2-0f94-47aa-a794-64cd1136cf05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161859081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2161859081
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.1352328279
Short name T116
Test name
Test status
Simulation time 94383808748 ps
CPU time 83.84 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:31:41 PM PDT 24
Peak memory 191060 kb
Host smart-da2e743f-390b-4e9b-8141-ee1592850478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352328279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.1352328279
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.1288376148
Short name T77
Test name
Test status
Simulation time 9187599359 ps
CPU time 13.3 seconds
Started Jul 15 04:30:14 PM PDT 24
Finished Jul 15 04:30:30 PM PDT 24
Peak memory 182788 kb
Host smart-41e2a321-09a7-4493-a77c-cc1a8921371d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288376148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.1288376148
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.1290985626
Short name T120
Test name
Test status
Simulation time 187957404925 ps
CPU time 193.97 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:33:29 PM PDT 24
Peak memory 191116 kb
Host smart-f377cfb9-1d90-4666-92fc-61be831bdbec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290985626 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.1290985626
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.604520622
Short name T242
Test name
Test status
Simulation time 84792848194 ps
CPU time 357.96 seconds
Started Jul 15 04:30:12 PM PDT 24
Finished Jul 15 04:36:11 PM PDT 24
Peak memory 191064 kb
Host smart-4558162f-abb2-4674-ab37-7a46ae4cd473
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604520622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.604520622
Directory /workspace/99.rv_timer_random/latest
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