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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.62 99.36 98.73 100.00 100.00 100.00 99.66


Total test records in report: 585
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T512 /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.732464875 Jul 16 04:53:38 PM PDT 24 Jul 16 04:53:41 PM PDT 24 19349066 ps
T513 /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3010469455 Jul 16 04:53:20 PM PDT 24 Jul 16 04:53:24 PM PDT 24 346504119 ps
T514 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2783184090 Jul 16 04:53:40 PM PDT 24 Jul 16 04:53:43 PM PDT 24 37826179 ps
T515 /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.155818446 Jul 16 04:53:21 PM PDT 24 Jul 16 04:53:24 PM PDT 24 86451340 ps
T516 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1272944849 Jul 16 04:53:37 PM PDT 24 Jul 16 04:53:40 PM PDT 24 12428775 ps
T517 /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2437181811 Jul 16 04:53:40 PM PDT 24 Jul 16 04:53:43 PM PDT 24 18424428 ps
T518 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1754853327 Jul 16 04:53:23 PM PDT 24 Jul 16 04:53:26 PM PDT 24 30542870 ps
T519 /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.351546908 Jul 16 04:53:06 PM PDT 24 Jul 16 04:53:08 PM PDT 24 1958124092 ps
T520 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2989275152 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:39 PM PDT 24 17170740 ps
T521 /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2345932498 Jul 16 04:53:21 PM PDT 24 Jul 16 04:53:23 PM PDT 24 20787641 ps
T522 /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2734851660 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:41 PM PDT 24 238215986 ps
T523 /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4122780092 Jul 16 04:53:21 PM PDT 24 Jul 16 04:53:23 PM PDT 24 36255166 ps
T524 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4120885984 Jul 16 04:53:30 PM PDT 24 Jul 16 04:53:32 PM PDT 24 78390707 ps
T525 /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.408242764 Jul 16 04:53:32 PM PDT 24 Jul 16 04:53:33 PM PDT 24 17082476 ps
T526 /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2962980572 Jul 16 04:53:21 PM PDT 24 Jul 16 04:53:23 PM PDT 24 129111779 ps
T527 /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1436455656 Jul 16 04:53:35 PM PDT 24 Jul 16 04:53:37 PM PDT 24 48648133 ps
T528 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.550783694 Jul 16 04:53:08 PM PDT 24 Jul 16 04:53:10 PM PDT 24 265027432 ps
T529 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2704545366 Jul 16 04:53:22 PM PDT 24 Jul 16 04:53:25 PM PDT 24 43869287 ps
T93 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2110567627 Jul 16 04:53:35 PM PDT 24 Jul 16 04:53:37 PM PDT 24 116798956 ps
T97 /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2173034338 Jul 16 04:53:20 PM PDT 24 Jul 16 04:53:22 PM PDT 24 13723371 ps
T530 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1933099282 Jul 16 04:53:37 PM PDT 24 Jul 16 04:53:41 PM PDT 24 50435290 ps
T94 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.34981622 Jul 16 04:53:23 PM PDT 24 Jul 16 04:53:25 PM PDT 24 28333994 ps
T531 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3263808070 Jul 16 04:53:20 PM PDT 24 Jul 16 04:53:22 PM PDT 24 149106368 ps
T532 /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1943630182 Jul 16 04:53:14 PM PDT 24 Jul 16 04:53:16 PM PDT 24 41419582 ps
T533 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3493387767 Jul 16 04:53:41 PM PDT 24 Jul 16 04:53:43 PM PDT 24 13135510 ps
T534 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.680658315 Jul 16 04:53:39 PM PDT 24 Jul 16 04:53:42 PM PDT 24 12512611 ps
T535 /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3542259323 Jul 16 04:53:21 PM PDT 24 Jul 16 04:53:24 PM PDT 24 49707651 ps
T536 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4267881512 Jul 16 04:53:34 PM PDT 24 Jul 16 04:53:36 PM PDT 24 45636456 ps
T537 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1844682221 Jul 16 04:53:35 PM PDT 24 Jul 16 04:53:38 PM PDT 24 54890886 ps
T538 /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2984689831 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:38 PM PDT 24 73703736 ps
T539 /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3141654673 Jul 16 04:53:05 PM PDT 24 Jul 16 04:53:06 PM PDT 24 136532045 ps
T540 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1948834755 Jul 16 04:53:21 PM PDT 24 Jul 16 04:53:23 PM PDT 24 41779688 ps
T541 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2020171636 Jul 16 04:53:23 PM PDT 24 Jul 16 04:53:25 PM PDT 24 56062160 ps
T542 /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1855823333 Jul 16 04:53:23 PM PDT 24 Jul 16 04:53:25 PM PDT 24 14756170 ps
T543 /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2157431575 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:39 PM PDT 24 24505283 ps
T544 /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2950027502 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:39 PM PDT 24 159083431 ps
T545 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2394193484 Jul 16 04:53:35 PM PDT 24 Jul 16 04:53:36 PM PDT 24 61053691 ps
T546 /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3227766933 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:38 PM PDT 24 94611447 ps
T547 /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1705286451 Jul 16 04:53:20 PM PDT 24 Jul 16 04:53:21 PM PDT 24 44595088 ps
T115 /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.558028603 Jul 16 04:53:23 PM PDT 24 Jul 16 04:53:25 PM PDT 24 112277363 ps
T548 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.4004905046 Jul 16 04:53:18 PM PDT 24 Jul 16 04:53:19 PM PDT 24 42024471 ps
T116 /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3433261410 Jul 16 04:53:30 PM PDT 24 Jul 16 04:53:32 PM PDT 24 134855894 ps
T549 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1644711167 Jul 16 04:53:32 PM PDT 24 Jul 16 04:53:34 PM PDT 24 90195518 ps
T550 /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3071360161 Jul 16 04:53:33 PM PDT 24 Jul 16 04:53:35 PM PDT 24 202555662 ps
T551 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1598972312 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:39 PM PDT 24 16370050 ps
T552 /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3941448883 Jul 16 04:53:35 PM PDT 24 Jul 16 04:53:37 PM PDT 24 16098795 ps
T553 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1595085657 Jul 16 04:53:39 PM PDT 24 Jul 16 04:53:43 PM PDT 24 204009810 ps
T554 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3443950485 Jul 16 04:53:38 PM PDT 24 Jul 16 04:53:42 PM PDT 24 113983936 ps
T555 /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1865854347 Jul 16 04:53:31 PM PDT 24 Jul 16 04:53:32 PM PDT 24 60671143 ps
T95 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.4132536411 Jul 16 04:53:32 PM PDT 24 Jul 16 04:53:33 PM PDT 24 12566698 ps
T556 /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.484577977 Jul 16 04:53:06 PM PDT 24 Jul 16 04:53:07 PM PDT 24 57489481 ps
T557 /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2632544007 Jul 16 04:53:38 PM PDT 24 Jul 16 04:53:41 PM PDT 24 29788903 ps
T96 /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.863410758 Jul 16 04:53:34 PM PDT 24 Jul 16 04:53:35 PM PDT 24 17069996 ps
T558 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3529993216 Jul 16 04:53:23 PM PDT 24 Jul 16 04:53:26 PM PDT 24 195865121 ps
T559 /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2370851323 Jul 16 04:53:35 PM PDT 24 Jul 16 04:53:38 PM PDT 24 23502583 ps
T560 /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.640412410 Jul 16 04:53:40 PM PDT 24 Jul 16 04:53:43 PM PDT 24 19645515 ps
T561 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4032000381 Jul 16 04:53:07 PM PDT 24 Jul 16 04:53:09 PM PDT 24 205412972 ps
T562 /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1580395752 Jul 16 04:53:20 PM PDT 24 Jul 16 04:53:23 PM PDT 24 199589682 ps
T101 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.855894828 Jul 16 04:53:22 PM PDT 24 Jul 16 04:53:25 PM PDT 24 44270914 ps
T563 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4246178030 Jul 16 04:53:42 PM PDT 24 Jul 16 04:53:44 PM PDT 24 70182812 ps
T564 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.496887423 Jul 16 04:53:09 PM PDT 24 Jul 16 04:53:10 PM PDT 24 175998587 ps
T98 /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3939127338 Jul 16 04:53:10 PM PDT 24 Jul 16 04:53:11 PM PDT 24 94068487 ps
T565 /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1983371624 Jul 16 04:53:32 PM PDT 24 Jul 16 04:53:34 PM PDT 24 1637297682 ps
T566 /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.967993240 Jul 16 04:53:37 PM PDT 24 Jul 16 04:53:41 PM PDT 24 22748892 ps
T567 /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3355835981 Jul 16 04:53:35 PM PDT 24 Jul 16 04:53:36 PM PDT 24 46945146 ps
T568 /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.358614332 Jul 16 04:53:41 PM PDT 24 Jul 16 04:53:43 PM PDT 24 15711635 ps
T569 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.768026491 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:39 PM PDT 24 140366688 ps
T570 /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.581695271 Jul 16 04:53:42 PM PDT 24 Jul 16 04:53:44 PM PDT 24 13814426 ps
T571 /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2012394317 Jul 16 04:53:07 PM PDT 24 Jul 16 04:53:11 PM PDT 24 291226758 ps
T572 /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3023557655 Jul 16 04:53:07 PM PDT 24 Jul 16 04:53:09 PM PDT 24 46140631 ps
T573 /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1327346162 Jul 16 04:53:41 PM PDT 24 Jul 16 04:53:44 PM PDT 24 15912356 ps
T574 /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2243381521 Jul 16 04:53:32 PM PDT 24 Jul 16 04:53:34 PM PDT 24 30969958 ps
T99 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1491667906 Jul 16 04:53:08 PM PDT 24 Jul 16 04:53:09 PM PDT 24 14223593 ps
T575 /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2146915529 Jul 16 04:53:35 PM PDT 24 Jul 16 04:53:36 PM PDT 24 15187080 ps
T576 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2191803057 Jul 16 04:53:20 PM PDT 24 Jul 16 04:53:22 PM PDT 24 109281258 ps
T577 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3433529967 Jul 16 04:53:07 PM PDT 24 Jul 16 04:53:09 PM PDT 24 161898735 ps
T578 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.104747416 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:39 PM PDT 24 89977670 ps
T579 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1621344037 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:39 PM PDT 24 30885667 ps
T580 /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1065565550 Jul 16 04:53:38 PM PDT 24 Jul 16 04:53:41 PM PDT 24 208796018 ps
T581 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.864801529 Jul 16 04:53:23 PM PDT 24 Jul 16 04:53:26 PM PDT 24 23902521 ps
T582 /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2228230794 Jul 16 04:53:36 PM PDT 24 Jul 16 04:53:39 PM PDT 24 35043007 ps
T583 /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3207839847 Jul 16 04:53:34 PM PDT 24 Jul 16 04:53:36 PM PDT 24 100077588 ps
T100 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3204535271 Jul 16 04:53:18 PM PDT 24 Jul 16 04:53:20 PM PDT 24 46184841 ps
T584 /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2183506988 Jul 16 04:53:20 PM PDT 24 Jul 16 04:53:22 PM PDT 24 15144299 ps
T585 /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.223203932 Jul 16 04:53:35 PM PDT 24 Jul 16 04:53:36 PM PDT 24 19192694 ps

Test location /workspace/coverage/default/76.rv_timer_random.384616068
Short name T7
Test name
Test status
Simulation time 1474989578859 ps
CPU time 499.42 seconds
Started Jul 16 04:37:02 PM PDT 24
Finished Jul 16 04:45:22 PM PDT 24
Peak memory 191252 kb
Host smart-caea3d32-e35e-4a80-842c-147204f4f747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384616068 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.384616068
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.1941724651
Short name T17
Test name
Test status
Simulation time 66959454766 ps
CPU time 116.43 seconds
Started Jul 16 04:40:43 PM PDT 24
Finished Jul 16 04:42:40 PM PDT 24
Peak memory 197544 kb
Host smart-ffb88047-3af1-42b4-85ad-f2c5e337dcd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941724651 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.1941724651
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.1153121276
Short name T11
Test name
Test status
Simulation time 2330150703641 ps
CPU time 4048.9 seconds
Started Jul 16 04:40:13 PM PDT 24
Finished Jul 16 05:47:44 PM PDT 24
Peak memory 190864 kb
Host smart-1d74f454-4bcb-4014-9db6-9e0384c9ded5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153121276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
1153121276
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2715898449
Short name T33
Test name
Test status
Simulation time 165090848 ps
CPU time 1.09 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:40 PM PDT 24
Peak memory 194272 kb
Host smart-ae0af147-109d-492c-93cd-06a0f6657d04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715898449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2715898449
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.6198631
Short name T156
Test name
Test status
Simulation time 4692166709730 ps
CPU time 2360.81 seconds
Started Jul 16 04:40:22 PM PDT 24
Finished Jul 16 05:19:44 PM PDT 24
Peak memory 190772 kb
Host smart-086d5655-6197-48e5-9cea-795a825fbbd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6198631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress_a
ll_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all.6198631
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.715177937
Short name T258
Test name
Test status
Simulation time 2693371902200 ps
CPU time 2054.1 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 05:14:27 PM PDT 24
Peak memory 190864 kb
Host smart-b8f1b1eb-1671-4fe4-90ae-dc14a5c39492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715177937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all.
715177937
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.1169540557
Short name T50
Test name
Test status
Simulation time 1170688919925 ps
CPU time 1264.85 seconds
Started Jul 16 04:39:43 PM PDT 24
Finished Jul 16 05:00:49 PM PDT 24
Peak memory 189720 kb
Host smart-08fc7fc0-86c5-4102-b64b-bdf1085ffb8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169540557 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.
1169540557
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2879128580
Short name T174
Test name
Test status
Simulation time 2240049281110 ps
CPU time 3332.1 seconds
Started Jul 16 04:37:58 PM PDT 24
Finished Jul 16 05:33:31 PM PDT 24
Peak memory 191256 kb
Host smart-3a58db06-9838-432e-8251-501d10f537e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879128580 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2879128580
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.764723373
Short name T31
Test name
Test status
Simulation time 403960229654 ps
CPU time 1433.73 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 05:04:01 PM PDT 24
Peak memory 193960 kb
Host smart-7ea31e48-3938-4b03-be93-176fef368dea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764723373 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
764723373
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.527443453
Short name T340
Test name
Test status
Simulation time 487700404703 ps
CPU time 973.02 seconds
Started Jul 16 04:39:51 PM PDT 24
Finished Jul 16 04:56:05 PM PDT 24
Peak memory 195392 kb
Host smart-cc10e0dc-1768-4577-ac81-a4ef0da9c099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527443453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.527443453
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.3967791725
Short name T241
Test name
Test status
Simulation time 525636853035 ps
CPU time 5054.42 seconds
Started Jul 16 04:37:08 PM PDT 24
Finished Jul 16 06:01:23 PM PDT 24
Peak memory 191172 kb
Host smart-09e0beaa-2174-4645-8741-b27f0006a570
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967791725 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all
.3967791725
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.3409769367
Short name T139
Test name
Test status
Simulation time 502281269810 ps
CPU time 2226.38 seconds
Started Jul 16 04:39:56 PM PDT 24
Finished Jul 16 05:17:03 PM PDT 24
Peak memory 190644 kb
Host smart-4dbd2318-fd1e-4038-a42b-c6e34959505a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409769367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.3409769367
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.387480157
Short name T60
Test name
Test status
Simulation time 182018627 ps
CPU time 0.74 seconds
Started Jul 16 04:53:08 PM PDT 24
Finished Jul 16 04:53:10 PM PDT 24
Peak memory 182176 kb
Host smart-32ff039c-fc8d-4e9c-b8ce-4a2ddf3167a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387480157 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.387480157
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2554367921
Short name T73
Test name
Test status
Simulation time 2078717775160 ps
CPU time 1712.25 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 05:08:40 PM PDT 24
Peak memory 190888 kb
Host smart-0334be7e-a8dd-49e5-8753-23c5c4466d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554367921 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2554367921
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3992206248
Short name T208
Test name
Test status
Simulation time 534223231812 ps
CPU time 1764.06 seconds
Started Jul 16 04:36:52 PM PDT 24
Finished Jul 16 05:06:17 PM PDT 24
Peak memory 191136 kb
Host smart-5de6133d-c941-4344-a1b3-fb0a204300df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992206248 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3992206248
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.1203685346
Short name T21
Test name
Test status
Simulation time 393634264 ps
CPU time 0.79 seconds
Started Jul 16 04:40:08 PM PDT 24
Finished Jul 16 04:40:11 PM PDT 24
Peak memory 213016 kb
Host smart-ddbef955-36d6-4845-85bc-4eefa748e322
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203685346 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.1203685346
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.927898611
Short name T48
Test name
Test status
Simulation time 849128323789 ps
CPU time 790.86 seconds
Started Jul 16 04:40:01 PM PDT 24
Finished Jul 16 04:53:14 PM PDT 24
Peak memory 189416 kb
Host smart-d028e2c5-d820-4c01-a861-5fc18bea2ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927898611 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
927898611
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.1780822837
Short name T255
Test name
Test status
Simulation time 1992842592034 ps
CPU time 1418.67 seconds
Started Jul 16 04:40:15 PM PDT 24
Finished Jul 16 05:03:56 PM PDT 24
Peak memory 191084 kb
Host smart-0343448f-ce02-426c-ae28-3e484e707279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780822837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
1780822837
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/193.rv_timer_random.1870353506
Short name T49
Test name
Test status
Simulation time 219287067656 ps
CPU time 368.43 seconds
Started Jul 16 04:40:15 PM PDT 24
Finished Jul 16 04:46:25 PM PDT 24
Peak memory 190852 kb
Host smart-ca6381ba-4936-4a2c-8b2f-f0aa2381d912
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870353506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.1870353506
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.311691688
Short name T239
Test name
Test status
Simulation time 820450305102 ps
CPU time 1813.18 seconds
Started Jul 16 04:40:42 PM PDT 24
Finished Jul 16 05:10:56 PM PDT 24
Peak memory 191088 kb
Host smart-2c3ebb00-5f16-480c-9dda-cd1c20900413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311691688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all.
311691688
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3840109633
Short name T318
Test name
Test status
Simulation time 451378526982 ps
CPU time 3011.21 seconds
Started Jul 16 04:40:36 PM PDT 24
Finished Jul 16 05:30:48 PM PDT 24
Peak memory 195160 kb
Host smart-10181549-79cd-4085-b3b2-b08df133044b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840109633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3840109633
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.3134562908
Short name T183
Test name
Test status
Simulation time 1086436993561 ps
CPU time 3411.54 seconds
Started Jul 16 04:40:42 PM PDT 24
Finished Jul 16 05:37:35 PM PDT 24
Peak memory 191112 kb
Host smart-bc137a50-b86b-4f69-9470-20fe4d7a9d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134562908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.3134562908
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.4049873589
Short name T161
Test name
Test status
Simulation time 1609995770852 ps
CPU time 1114.85 seconds
Started Jul 16 04:38:00 PM PDT 24
Finished Jul 16 04:56:35 PM PDT 24
Peak memory 191120 kb
Host smart-cf84c285-f5f5-415f-a8f0-c1fe827face8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049873589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.4049873589
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/52.rv_timer_random.3302612149
Short name T186
Test name
Test status
Simulation time 640614960513 ps
CPU time 235.39 seconds
Started Jul 16 04:40:21 PM PDT 24
Finished Jul 16 04:44:18 PM PDT 24
Peak memory 188808 kb
Host smart-ba74cd87-6b68-4a2b-ae77-97784728ff95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302612149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.3302612149
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.3621933523
Short name T66
Test name
Test status
Simulation time 973054363026 ps
CPU time 3407.83 seconds
Started Jul 16 04:40:44 PM PDT 24
Finished Jul 16 05:37:33 PM PDT 24
Peak memory 191092 kb
Host smart-9f89d636-3cb6-4c72-bb3c-2667327f84e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621933523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.3621933523
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/109.rv_timer_random.558233207
Short name T281
Test name
Test status
Simulation time 143866592896 ps
CPU time 348.76 seconds
Started Jul 16 04:37:05 PM PDT 24
Finished Jul 16 04:42:54 PM PDT 24
Peak memory 194320 kb
Host smart-2eb12fa9-fe17-4223-85cd-ba9f46e5c0f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558233207 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.558233207
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.3343599010
Short name T266
Test name
Test status
Simulation time 761606527509 ps
CPU time 752.03 seconds
Started Jul 16 04:37:18 PM PDT 24
Finished Jul 16 04:49:50 PM PDT 24
Peak memory 191260 kb
Host smart-bc5ca4e3-7717-4f4c-9a85-63d33a82e3e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343599010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.3343599010
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.177530502
Short name T290
Test name
Test status
Simulation time 95653331262 ps
CPU time 336.03 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 04:45:53 PM PDT 24
Peak memory 190856 kb
Host smart-7ba247a7-581a-4630-9e50-4149d219d88e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177530502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.177530502
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.1878167341
Short name T10
Test name
Test status
Simulation time 175000086027 ps
CPU time 1105.88 seconds
Started Jul 16 04:40:15 PM PDT 24
Finished Jul 16 04:58:43 PM PDT 24
Peak memory 190852 kb
Host smart-1149a5e7-9923-431c-a2f7-26e248e87911
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878167341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.1878167341
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/190.rv_timer_random.563972174
Short name T26
Test name
Test status
Simulation time 589116871177 ps
CPU time 302.46 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:45:10 PM PDT 24
Peak memory 190268 kb
Host smart-304e663f-24d3-4ae0-9e26-fa2e4275a71b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563972174 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.563972174
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.2721213655
Short name T145
Test name
Test status
Simulation time 990826445610 ps
CPU time 1914.63 seconds
Started Jul 16 04:37:20 PM PDT 24
Finished Jul 16 05:09:15 PM PDT 24
Peak memory 192212 kb
Host smart-492fa411-05aa-49f2-88dd-67de6f19030c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721213655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.2721213655
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3185164834
Short name T9
Test name
Test status
Simulation time 782681775653 ps
CPU time 428.73 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 04:47:16 PM PDT 24
Peak memory 190876 kb
Host smart-bf0e4d4f-6db4-4879-b920-dfbb03e72403
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185164834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3185164834
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3355140391
Short name T146
Test name
Test status
Simulation time 152881194757 ps
CPU time 273.11 seconds
Started Jul 16 04:40:26 PM PDT 24
Finished Jul 16 04:45:00 PM PDT 24
Peak memory 190872 kb
Host smart-9113e224-705a-4abc-8758-ed56a218de6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355140391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3355140391
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random.3172931066
Short name T198
Test name
Test status
Simulation time 157903124372 ps
CPU time 255.56 seconds
Started Jul 16 04:35:26 PM PDT 24
Finished Jul 16 04:39:42 PM PDT 24
Peak memory 191128 kb
Host smart-3c91d03b-8880-496c-9e98-1b4f49bb6a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172931066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.3172931066
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.243720936
Short name T192
Test name
Test status
Simulation time 1313723422437 ps
CPU time 646 seconds
Started Jul 16 04:37:45 PM PDT 24
Finished Jul 16 04:48:32 PM PDT 24
Peak memory 182844 kb
Host smart-fc02abf1-9046-4f4e-9fa8-8ab3bf18c7b7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243720936 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.rv_timer_cfg_update_on_fly.243720936
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.3930284672
Short name T39
Test name
Test status
Simulation time 43024746 ps
CPU time 0.85 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 193964 kb
Host smart-28abc12d-07ed-4042-98d8-31a7ca9727c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930284672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_t
imer_same_csr_outstanding.3930284672
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/100.rv_timer_random.3701213371
Short name T165
Test name
Test status
Simulation time 74082059331 ps
CPU time 532.25 seconds
Started Jul 16 04:39:48 PM PDT 24
Finished Jul 16 04:48:41 PM PDT 24
Peak memory 190812 kb
Host smart-1e18d647-16bd-4ddf-af7d-c2eaa097edce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701213371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.3701213371
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.3595593961
Short name T212
Test name
Test status
Simulation time 213971889531 ps
CPU time 449.36 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:47:39 PM PDT 24
Peak memory 189712 kb
Host smart-5dba55c3-ddb2-43d9-a6db-a7a29312a6ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595593961 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.3595593961
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.4156609567
Short name T194
Test name
Test status
Simulation time 306810065798 ps
CPU time 724.91 seconds
Started Jul 16 04:39:52 PM PDT 24
Finished Jul 16 04:51:57 PM PDT 24
Peak memory 190812 kb
Host smart-7bfab7fd-bc32-484d-aa86-5c1289a3015a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156609567 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.4156609567
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.1464147642
Short name T150
Test name
Test status
Simulation time 1026588422579 ps
CPU time 1017.04 seconds
Started Jul 16 04:38:24 PM PDT 24
Finished Jul 16 04:55:22 PM PDT 24
Peak memory 191476 kb
Host smart-1752d88c-3913-4c18-ad1c-c5febf1bd7fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464147642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.1464147642
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.2190187622
Short name T313
Test name
Test status
Simulation time 159615524496 ps
CPU time 237.43 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 04:44:05 PM PDT 24
Peak memory 189328 kb
Host smart-9544d072-2823-4b74-88c9-d8847766ee4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190187622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.2190187622
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.216643398
Short name T140
Test name
Test status
Simulation time 484626572643 ps
CPU time 717 seconds
Started Jul 16 04:39:38 PM PDT 24
Finished Jul 16 04:51:37 PM PDT 24
Peak memory 193132 kb
Host smart-1bfd8d8c-e679-4007-9b41-ba78a516c4ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216643398 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
216643398
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/67.rv_timer_random.2248936377
Short name T223
Test name
Test status
Simulation time 363556275228 ps
CPU time 166.21 seconds
Started Jul 16 04:39:51 PM PDT 24
Finished Jul 16 04:42:38 PM PDT 24
Peak memory 190408 kb
Host smart-5d2a4b56-a563-45c6-bd49-a405a0be4a0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248936377 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.2248936377
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.649538260
Short name T196
Test name
Test status
Simulation time 682038282383 ps
CPU time 817.3 seconds
Started Jul 16 04:40:11 PM PDT 24
Finished Jul 16 04:53:49 PM PDT 24
Peak memory 190964 kb
Host smart-6d3eb8bf-f411-4d4a-a912-a236f5d3db99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649538260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.649538260
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/84.rv_timer_random.3248981774
Short name T126
Test name
Test status
Simulation time 275347459991 ps
CPU time 210.81 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:43:40 PM PDT 24
Peak memory 190832 kb
Host smart-b2e7d1fe-045f-46c3-9434-76e30c710e58
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248981774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.3248981774
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.3128421409
Short name T79
Test name
Test status
Simulation time 656217078067 ps
CPU time 730.45 seconds
Started Jul 16 04:37:55 PM PDT 24
Finished Jul 16 04:50:06 PM PDT 24
Peak memory 194352 kb
Host smart-ecb7e7d9-8438-4bf5-8391-b7da93f5f511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128421409 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.3128421409
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.90351585
Short name T167
Test name
Test status
Simulation time 167739427118 ps
CPU time 292.56 seconds
Started Jul 16 04:40:05 PM PDT 24
Finished Jul 16 04:44:58 PM PDT 24
Peak memory 190864 kb
Host smart-9a91f15c-57ad-4580-b27f-fffcb9e64260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90351585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.90351585
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.312648609
Short name T275
Test name
Test status
Simulation time 202268908589 ps
CPU time 186.95 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 04:43:24 PM PDT 24
Peak memory 189220 kb
Host smart-87b16e66-0106-4fa0-a51b-889f21486aa7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312648609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.312648609
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.3588866823
Short name T148
Test name
Test status
Simulation time 179301516137 ps
CPU time 109.04 seconds
Started Jul 16 04:39:01 PM PDT 24
Finished Jul 16 04:40:51 PM PDT 24
Peak memory 183272 kb
Host smart-e3e6dc2c-cd24-45b9-99e0-9c2634b011d2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588866823 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.3588866823
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_random.3051084895
Short name T204
Test name
Test status
Simulation time 530508694890 ps
CPU time 768.36 seconds
Started Jul 16 04:40:38 PM PDT 24
Finished Jul 16 04:53:27 PM PDT 24
Peak memory 193952 kb
Host smart-cc81e21d-31dc-4cde-87c4-1aab4741f211
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051084895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3051084895
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.1439600707
Short name T330
Test name
Test status
Simulation time 1014375282207 ps
CPU time 470.35 seconds
Started Jul 16 04:39:53 PM PDT 24
Finished Jul 16 04:47:44 PM PDT 24
Peak memory 189612 kb
Host smart-24ef5618-7e50-4ffb-b838-4687e6288f35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439600707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.1439600707
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.3474677698
Short name T325
Test name
Test status
Simulation time 171342465321 ps
CPU time 168.03 seconds
Started Jul 16 04:36:49 PM PDT 24
Finished Jul 16 04:39:38 PM PDT 24
Peak memory 193340 kb
Host smart-73be4f34-8a34-4bef-b854-c02d4e0b7cf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474677698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.3474677698
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.1491667906
Short name T99
Test name
Test status
Simulation time 14223593 ps
CPU time 0.6 seconds
Started Jul 16 04:53:08 PM PDT 24
Finished Jul 16 04:53:09 PM PDT 24
Peak memory 182080 kb
Host smart-23607aaa-3dbd-43a9-8798-e23f48f8da0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491667906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.1491667906
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3433261410
Short name T116
Test name
Test status
Simulation time 134855894 ps
CPU time 1.36 seconds
Started Jul 16 04:53:30 PM PDT 24
Finished Jul 16 04:53:32 PM PDT 24
Peak memory 182760 kb
Host smart-6561c952-a803-403a-af1a-6d8b1811d02a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433261410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_i
ntg_err.3433261410
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/110.rv_timer_random.2781129587
Short name T178
Test name
Test status
Simulation time 96777990472 ps
CPU time 387.86 seconds
Started Jul 16 04:40:24 PM PDT 24
Finished Jul 16 04:46:52 PM PDT 24
Peak memory 190824 kb
Host smart-1541cf5c-2867-4059-a5e1-29a9ac0cfcae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781129587 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2781129587
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2143830047
Short name T68
Test name
Test status
Simulation time 380565426152 ps
CPU time 1004.81 seconds
Started Jul 16 04:37:12 PM PDT 24
Finished Jul 16 04:53:57 PM PDT 24
Peak memory 191152 kb
Host smart-ea481d30-1c56-4da4-a67f-ec71212ecbfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143830047 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2143830047
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random.3897782176
Short name T294
Test name
Test status
Simulation time 220470324258 ps
CPU time 625.13 seconds
Started Jul 16 04:38:11 PM PDT 24
Finished Jul 16 04:48:37 PM PDT 24
Peak memory 194872 kb
Host smart-1a95af34-a0ab-4df8-9c36-2fa88c007f16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897782176 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3897782176
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.283214757
Short name T138
Test name
Test status
Simulation time 148779623703 ps
CPU time 231.04 seconds
Started Jul 16 04:40:18 PM PDT 24
Finished Jul 16 04:44:10 PM PDT 24
Peak memory 190804 kb
Host smart-b8206655-e456-4812-b9d5-61ef2c60227d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283214757 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.283214757
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.553131505
Short name T231
Test name
Test status
Simulation time 528991540777 ps
CPU time 543.86 seconds
Started Jul 16 04:40:18 PM PDT 24
Finished Jul 16 04:49:22 PM PDT 24
Peak memory 190804 kb
Host smart-47fcfdc5-bf53-4c24-a8f7-443edbe346bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553131505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.553131505
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/180.rv_timer_random.1522626426
Short name T257
Test name
Test status
Simulation time 95803951406 ps
CPU time 570.12 seconds
Started Jul 16 04:37:54 PM PDT 24
Finished Jul 16 04:47:25 PM PDT 24
Peak memory 191100 kb
Host smart-4e42cf03-f1a9-4cfa-830a-6313c490d1f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522626426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.1522626426
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.1883439423
Short name T244
Test name
Test status
Simulation time 336955627660 ps
CPU time 350.03 seconds
Started Jul 16 04:40:36 PM PDT 24
Finished Jul 16 04:46:26 PM PDT 24
Peak memory 190856 kb
Host smart-153617f3-a303-413c-bb60-325accb8ad2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883439423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.1883439423
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.2060632428
Short name T365
Test name
Test status
Simulation time 146424317625 ps
CPU time 697 seconds
Started Jul 16 04:35:56 PM PDT 24
Finished Jul 16 04:47:33 PM PDT 24
Peak memory 191140 kb
Host smart-20ec7c30-173f-4be4-9f56-ea3c7d2e75ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060632428 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
2060632428
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_random.2765723123
Short name T203
Test name
Test status
Simulation time 239122515948 ps
CPU time 409.11 seconds
Started Jul 16 04:40:11 PM PDT 24
Finished Jul 16 04:47:01 PM PDT 24
Peak memory 190904 kb
Host smart-c416a0ef-d2b1-414c-8004-e8c12f2ffa91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765723123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.2765723123
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.1002932126
Short name T284
Test name
Test status
Simulation time 67951118146 ps
CPU time 355.11 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 04:46:02 PM PDT 24
Peak memory 189812 kb
Host smart-7928c63e-3143-4a8c-9252-456437090364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002932126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.1002932126
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random.3910058284
Short name T181
Test name
Test status
Simulation time 279697576737 ps
CPU time 335.48 seconds
Started Jul 16 04:40:03 PM PDT 24
Finished Jul 16 04:45:39 PM PDT 24
Peak memory 190872 kb
Host smart-6f1ff6fe-0b9e-465f-8211-5aa0e90f6163
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910058284 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.3910058284
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random.2510304177
Short name T121
Test name
Test status
Simulation time 118343196790 ps
CPU time 151.57 seconds
Started Jul 16 04:39:47 PM PDT 24
Finished Jul 16 04:42:19 PM PDT 24
Peak memory 189968 kb
Host smart-2cd08971-85b6-4ab4-9aea-70ff366e6660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510304177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.2510304177
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random.4076979676
Short name T237
Test name
Test status
Simulation time 150871922453 ps
CPU time 121.34 seconds
Started Jul 16 04:36:46 PM PDT 24
Finished Jul 16 04:38:48 PM PDT 24
Peak memory 193768 kb
Host smart-d19235d1-e721-4e8d-b27a-832a03e0aff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076979676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.4076979676
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.3214665783
Short name T261
Test name
Test status
Simulation time 103203587439 ps
CPU time 154.22 seconds
Started Jul 16 04:39:54 PM PDT 24
Finished Jul 16 04:42:29 PM PDT 24
Peak memory 190804 kb
Host smart-92888cd1-086a-4dbd-91b7-3770d09550fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214665783 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.3214665783
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1318479802
Short name T350
Test name
Test status
Simulation time 188064546741 ps
CPU time 195.48 seconds
Started Jul 16 04:39:53 PM PDT 24
Finished Jul 16 04:43:09 PM PDT 24
Peak memory 189168 kb
Host smart-075f8c4b-c362-4236-8055-0efd49ef80dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318479802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1318479802
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.576589772
Short name T195
Test name
Test status
Simulation time 148324309980 ps
CPU time 238.84 seconds
Started Jul 16 04:40:11 PM PDT 24
Finished Jul 16 04:44:11 PM PDT 24
Peak memory 182716 kb
Host smart-60a089c2-e12a-4ce2-a060-2a3c5cec82a5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576589772 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.rv_timer_cfg_update_on_fly.576589772
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/93.rv_timer_random.2092670830
Short name T120
Test name
Test status
Simulation time 255708348610 ps
CPU time 334.61 seconds
Started Jul 16 04:40:02 PM PDT 24
Finished Jul 16 04:45:38 PM PDT 24
Peak memory 190872 kb
Host smart-11b97e00-5ed7-436a-a60a-94c6e32c0687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092670830 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.2092670830
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_random.2320517561
Short name T307
Test name
Test status
Simulation time 209991990410 ps
CPU time 334.74 seconds
Started Jul 16 04:35:26 PM PDT 24
Finished Jul 16 04:41:01 PM PDT 24
Peak memory 191124 kb
Host smart-1a76ae90-b384-448a-95ef-2a94bd542844
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320517561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.2320517561
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.2388690026
Short name T74
Test name
Test status
Simulation time 172126114263 ps
CPU time 575 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 04:49:43 PM PDT 24
Peak memory 190872 kb
Host smart-d0c4b88a-814b-454d-a8c2-959bb7aabfd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388690026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
2388690026
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/103.rv_timer_random.3415879667
Short name T249
Test name
Test status
Simulation time 372411682558 ps
CPU time 174.72 seconds
Started Jul 16 04:39:51 PM PDT 24
Finished Jul 16 04:42:47 PM PDT 24
Peak memory 189908 kb
Host smart-17c1f4ad-f792-4349-ab2a-bbc8b736fc88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415879667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.3415879667
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/112.rv_timer_random.3053277815
Short name T273
Test name
Test status
Simulation time 58546175689 ps
CPU time 355.54 seconds
Started Jul 16 04:40:11 PM PDT 24
Finished Jul 16 04:46:08 PM PDT 24
Peak memory 190864 kb
Host smart-a1c046ef-57b4-4e8b-a7cb-37a947be53f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053277815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3053277815
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3033837747
Short name T228
Test name
Test status
Simulation time 132604403010 ps
CPU time 305.73 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 04:45:19 PM PDT 24
Peak memory 190868 kb
Host smart-56cd9da8-c03e-4ee0-b580-159fb22a66d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033837747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3033837747
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3730845907
Short name T352
Test name
Test status
Simulation time 67801385990 ps
CPU time 206.06 seconds
Started Jul 16 04:40:19 PM PDT 24
Finished Jul 16 04:43:46 PM PDT 24
Peak memory 188900 kb
Host smart-58fe58ed-572b-4748-81f4-8de209bb1746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730845907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3730845907
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.2806345308
Short name T303
Test name
Test status
Simulation time 171458879096 ps
CPU time 252.53 seconds
Started Jul 16 04:40:13 PM PDT 24
Finished Jul 16 04:44:27 PM PDT 24
Peak memory 190772 kb
Host smart-60aa4c7f-2518-4ae4-8461-02d2275795c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806345308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2806345308
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.1286508445
Short name T199
Test name
Test status
Simulation time 504466788312 ps
CPU time 236.51 seconds
Started Jul 16 04:40:01 PM PDT 24
Finished Jul 16 04:43:59 PM PDT 24
Peak memory 190400 kb
Host smart-b49ccfcc-586e-4a74-ac1b-3a0d95c256a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286508445 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.1286508445
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/130.rv_timer_random.344785505
Short name T171
Test name
Test status
Simulation time 143921927327 ps
CPU time 601.57 seconds
Started Jul 16 04:40:04 PM PDT 24
Finished Jul 16 04:50:07 PM PDT 24
Peak memory 190864 kb
Host smart-bba77144-2c1c-4d51-b08c-df7b6286d792
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344785505 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.344785505
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1369341976
Short name T64
Test name
Test status
Simulation time 122819977622 ps
CPU time 196.62 seconds
Started Jul 16 04:39:48 PM PDT 24
Finished Jul 16 04:43:06 PM PDT 24
Peak memory 190068 kb
Host smart-0f322ea2-2595-425c-b988-127199b6e769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369341976 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1369341976
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2705736416
Short name T176
Test name
Test status
Simulation time 738813781885 ps
CPU time 598.02 seconds
Started Jul 16 04:40:08 PM PDT 24
Finished Jul 16 04:50:08 PM PDT 24
Peak memory 182632 kb
Host smart-d34febc9-129b-4d37-b75b-7c8be3ffa920
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705736416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2705736416
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.1136442700
Short name T179
Test name
Test status
Simulation time 423864534668 ps
CPU time 95.81 seconds
Started Jul 16 04:40:09 PM PDT 24
Finished Jul 16 04:41:46 PM PDT 24
Peak memory 182652 kb
Host smart-eb938638-8daf-46c2-8d89-d268890f3135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136442700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.1136442700
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/165.rv_timer_random.3920619103
Short name T349
Test name
Test status
Simulation time 55639600199 ps
CPU time 99.86 seconds
Started Jul 16 04:38:01 PM PDT 24
Finished Jul 16 04:39:41 PM PDT 24
Peak memory 183000 kb
Host smart-1e6e8e86-f821-4ba6-b2f1-dc9194b7c161
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920619103 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.3920619103
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2485634851
Short name T1
Test name
Test status
Simulation time 352493930325 ps
CPU time 746.31 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 04:52:40 PM PDT 24
Peak memory 190852 kb
Host smart-2b6bd786-9384-43c2-841e-4b15d1c943ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485634851 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2485634851
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.1169914544
Short name T276
Test name
Test status
Simulation time 86600135745 ps
CPU time 132.26 seconds
Started Jul 16 04:35:24 PM PDT 24
Finished Jul 16 04:37:37 PM PDT 24
Peak memory 194568 kb
Host smart-9dadcc8d-29d0-4b86-90ba-002544c3e65e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169914544 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.1169914544
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1335624938
Short name T164
Test name
Test status
Simulation time 1074753157930 ps
CPU time 1288.68 seconds
Started Jul 16 04:37:42 PM PDT 24
Finished Jul 16 04:59:11 PM PDT 24
Peak memory 182968 kb
Host smart-8440f2f1-09e5-4048-93f8-e38aea4b4523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335624938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1335624938
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_random.670692629
Short name T353
Test name
Test status
Simulation time 105650786419 ps
CPU time 160.29 seconds
Started Jul 16 04:40:21 PM PDT 24
Finished Jul 16 04:43:03 PM PDT 24
Peak memory 188336 kb
Host smart-e2d84200-a7e5-440f-af14-7471895a3aaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670692629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.670692629
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1546809469
Short name T169
Test name
Test status
Simulation time 152406323465 ps
CPU time 251.32 seconds
Started Jul 16 04:39:54 PM PDT 24
Finished Jul 16 04:44:06 PM PDT 24
Peak memory 182512 kb
Host smart-4034b54d-be60-4aad-8cf9-42e6f99c3f32
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546809469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1546809469
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_random.2618318200
Short name T173
Test name
Test status
Simulation time 227575380851 ps
CPU time 543.31 seconds
Started Jul 16 04:40:00 PM PDT 24
Finished Jul 16 04:49:04 PM PDT 24
Peak memory 190596 kb
Host smart-6b5f9b38-b187-4fda-ac75-eae92f606999
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618318200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.2618318200
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random.3312728072
Short name T124
Test name
Test status
Simulation time 681606946916 ps
CPU time 1972.79 seconds
Started Jul 16 04:36:39 PM PDT 24
Finished Jul 16 05:09:33 PM PDT 24
Peak memory 190988 kb
Host smart-1ac616d2-50dd-44c4-ac00-a0a848c742fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312728072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.3312728072
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random.1920449634
Short name T357
Test name
Test status
Simulation time 1051613616345 ps
CPU time 760.81 seconds
Started Jul 16 04:35:34 PM PDT 24
Finished Jul 16 04:48:16 PM PDT 24
Peak memory 188576 kb
Host smart-93c49bac-f6d6-4fc0-a6fd-7f65d5d025e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920449634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1920449634
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3997710186
Short name T90
Test name
Test status
Simulation time 12997281 ps
CPU time 0.64 seconds
Started Jul 16 04:53:08 PM PDT 24
Finished Jul 16 04:53:09 PM PDT 24
Peak memory 182084 kb
Host smart-17236006-b990-4bb8-846d-30cd30c98685
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997710186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3997710186
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.2012394317
Short name T571
Test name
Test status
Simulation time 291226758 ps
CPU time 3.5 seconds
Started Jul 16 04:53:07 PM PDT 24
Finished Jul 16 04:53:11 PM PDT 24
Peak memory 182452 kb
Host smart-84cdeb72-4def-4987-a67c-ccb445af659d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012394317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.2012394317
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.496887423
Short name T564
Test name
Test status
Simulation time 175998587 ps
CPU time 0.57 seconds
Started Jul 16 04:53:09 PM PDT 24
Finished Jul 16 04:53:10 PM PDT 24
Peak memory 182056 kb
Host smart-d6b12233-621f-4b04-8430-51f47e61e8bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496887423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_re
set.496887423
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.4032000381
Short name T561
Test name
Test status
Simulation time 205412972 ps
CPU time 0.87 seconds
Started Jul 16 04:53:07 PM PDT 24
Finished Jul 16 04:53:09 PM PDT 24
Peak memory 196196 kb
Host smart-a1235497-edf9-4b00-baab-e748ee83175b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032000381 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.4032000381
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.484577977
Short name T556
Test name
Test status
Simulation time 57489481 ps
CPU time 0.55 seconds
Started Jul 16 04:53:06 PM PDT 24
Finished Jul 16 04:53:07 PM PDT 24
Peak memory 181992 kb
Host smart-982b6fc5-b5bd-4508-a160-1bd35d0b3747
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484577977 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.484577977
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1943630182
Short name T532
Test name
Test status
Simulation time 41419582 ps
CPU time 0.63 seconds
Started Jul 16 04:53:14 PM PDT 24
Finished Jul 16 04:53:16 PM PDT 24
Peak memory 191012 kb
Host smart-5ce572b7-ad69-4581-8925-d1dce0042476
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943630182 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_ti
mer_same_csr_outstanding.1943630182
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.3433529967
Short name T577
Test name
Test status
Simulation time 161898735 ps
CPU time 1.55 seconds
Started Jul 16 04:53:07 PM PDT 24
Finished Jul 16 04:53:09 PM PDT 24
Peak memory 196904 kb
Host smart-5aed304f-f881-4b78-884a-731256c62a71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433529967 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.3433529967
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.550783694
Short name T528
Test name
Test status
Simulation time 265027432 ps
CPU time 0.85 seconds
Started Jul 16 04:53:08 PM PDT 24
Finished Jul 16 04:53:10 PM PDT 24
Peak memory 182684 kb
Host smart-c9f1853f-b71f-4380-9018-dfcc306a82c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550783694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_int
g_err.550783694
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.1430566092
Short name T89
Test name
Test status
Simulation time 2283047920 ps
CPU time 2.63 seconds
Started Jul 16 04:53:06 PM PDT 24
Finished Jul 16 04:53:10 PM PDT 24
Peak memory 190520 kb
Host smart-73f89337-fcb1-4510-9fd8-ac296cc8e115
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430566092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.1430566092
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.216020558
Short name T497
Test name
Test status
Simulation time 40302394 ps
CPU time 0.53 seconds
Started Jul 16 04:53:05 PM PDT 24
Finished Jul 16 04:53:07 PM PDT 24
Peak memory 181808 kb
Host smart-a0a0d033-2ffd-4ca6-aa7b-d74cf2c45a5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216020558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.216020558
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.4248315074
Short name T58
Test name
Test status
Simulation time 64151531 ps
CPU time 0.74 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:21 PM PDT 24
Peak memory 193704 kb
Host smart-3e73517d-fcfc-4c16-b989-61e4963d4d3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248315074 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.4248315074
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.3939127338
Short name T98
Test name
Test status
Simulation time 94068487 ps
CPU time 0.6 seconds
Started Jul 16 04:53:10 PM PDT 24
Finished Jul 16 04:53:11 PM PDT 24
Peak memory 182092 kb
Host smart-73ebf29d-5daa-4a56-8651-1a26769c80dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939127338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.3939127338
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.3023557655
Short name T572
Test name
Test status
Simulation time 46140631 ps
CPU time 0.64 seconds
Started Jul 16 04:53:07 PM PDT 24
Finished Jul 16 04:53:09 PM PDT 24
Peak memory 182416 kb
Host smart-96b3f8cc-fc4b-4ded-92f9-d92bf7fc5da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023557655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.3023557655
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.2684066011
Short name T108
Test name
Test status
Simulation time 35494499 ps
CPU time 0.6 seconds
Started Jul 16 04:53:09 PM PDT 24
Finished Jul 16 04:53:10 PM PDT 24
Peak memory 191292 kb
Host smart-63cb1987-d986-4e05-87b0-d1c6a12d9355
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684066011 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.2684066011
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.351546908
Short name T519
Test name
Test status
Simulation time 1958124092 ps
CPU time 1.83 seconds
Started Jul 16 04:53:06 PM PDT 24
Finished Jul 16 04:53:08 PM PDT 24
Peak memory 196820 kb
Host smart-bdd73c39-b794-4ecb-a69d-5b762c7d5f46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351546908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.351546908
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.3141654673
Short name T539
Test name
Test status
Simulation time 136532045 ps
CPU time 1.08 seconds
Started Jul 16 04:53:05 PM PDT 24
Finished Jul 16 04:53:06 PM PDT 24
Peak memory 194580 kb
Host smart-a84fd6d7-5fac-495d-830e-6f84356fa125
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141654673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.3141654673
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.3071360161
Short name T550
Test name
Test status
Simulation time 202555662 ps
CPU time 1.22 seconds
Started Jul 16 04:53:33 PM PDT 24
Finished Jul 16 04:53:35 PM PDT 24
Peak memory 196916 kb
Host smart-8d029e91-82b0-4704-8c19-1e7a2d1a110a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071360161 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.3071360161
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3126000022
Short name T110
Test name
Test status
Simulation time 16014047 ps
CPU time 0.59 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:40 PM PDT 24
Peak memory 182072 kb
Host smart-6acde992-c3f5-4f0b-b574-da5686add271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126000022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3126000022
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.753295678
Short name T471
Test name
Test status
Simulation time 15911454 ps
CPU time 0.53 seconds
Started Jul 16 04:53:33 PM PDT 24
Finished Jul 16 04:53:34 PM PDT 24
Peak memory 181452 kb
Host smart-484e39f5-fbfd-406c-9c5e-5a408d522083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753295678 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.753295678
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.4246178030
Short name T563
Test name
Test status
Simulation time 70182812 ps
CPU time 0.81 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:44 PM PDT 24
Peak memory 192800 kb
Host smart-9596133b-465c-4235-a463-e2a88826a691
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246178030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.4246178030
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.3570895395
Short name T494
Test name
Test status
Simulation time 132483248 ps
CPU time 1.68 seconds
Started Jul 16 04:53:31 PM PDT 24
Finished Jul 16 04:53:33 PM PDT 24
Peak memory 196740 kb
Host smart-8727cb86-ae2a-4185-9bea-8b4226198c13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570895395 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.3570895395
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.36000202
Short name T112
Test name
Test status
Simulation time 62171345 ps
CPU time 0.84 seconds
Started Jul 16 04:53:34 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 192956 kb
Host smart-c047114d-4853-4d42-8405-c7a4cfb5b894
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36000202 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_int
g_err.36000202
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.2043246725
Short name T38
Test name
Test status
Simulation time 41404307 ps
CPU time 0.99 seconds
Started Jul 16 04:53:39 PM PDT 24
Finished Jul 16 04:53:42 PM PDT 24
Peak memory 196732 kb
Host smart-c9df9fec-f2cc-44b4-91a4-3a0a6ebef7c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043246725 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.2043246725
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.2185108714
Short name T510
Test name
Test status
Simulation time 14526471 ps
CPU time 0.58 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:38 PM PDT 24
Peak memory 182020 kb
Host smart-193657c5-e13e-4acf-94ee-b6e2cdc8cd13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185108714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.2185108714
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.1865854347
Short name T555
Test name
Test status
Simulation time 60671143 ps
CPU time 0.6 seconds
Started Jul 16 04:53:31 PM PDT 24
Finished Jul 16 04:53:32 PM PDT 24
Peak memory 182036 kb
Host smart-2e3bf35a-5299-4e2b-a97d-ba4b0d6852ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865854347 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.1865854347
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.967993240
Short name T566
Test name
Test status
Simulation time 22748892 ps
CPU time 0.66 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:41 PM PDT 24
Peak memory 191508 kb
Host smart-7213f657-19c7-4880-87d2-485620f56f30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967993240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_ti
mer_same_csr_outstanding.967993240
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.960963029
Short name T511
Test name
Test status
Simulation time 242673537 ps
CPU time 1.95 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:45 PM PDT 24
Peak memory 196972 kb
Host smart-6845d129-6465-4bf1-9db8-107db799e8a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960963029 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.960963029
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.1005175040
Short name T504
Test name
Test status
Simulation time 83924543 ps
CPU time 1.08 seconds
Started Jul 16 04:53:34 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 197140 kb
Host smart-fa072766-3f45-4def-a1c1-197fdf6d157c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005175040 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.1005175040
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.223203932
Short name T585
Test name
Test status
Simulation time 19192694 ps
CPU time 0.59 seconds
Started Jul 16 04:53:35 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 182088 kb
Host smart-2ba8830a-7f76-4f97-a3f0-606ebb9be27e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223203932 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.223203932
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.3669485837
Short name T496
Test name
Test status
Simulation time 16139967 ps
CPU time 0.54 seconds
Started Jul 16 04:53:30 PM PDT 24
Finished Jul 16 04:53:31 PM PDT 24
Peak memory 182032 kb
Host smart-0969dd37-829f-46f1-bdc8-9a81009f7dd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669485837 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.3669485837
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.2243381521
Short name T574
Test name
Test status
Simulation time 30969958 ps
CPU time 0.84 seconds
Started Jul 16 04:53:32 PM PDT 24
Finished Jul 16 04:53:34 PM PDT 24
Peak memory 192708 kb
Host smart-882d6bf9-6a35-4fe4-b75e-12bf6d414f35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243381521 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.2243381521
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.1985813693
Short name T71
Test name
Test status
Simulation time 92563031 ps
CPU time 1.74 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:42 PM PDT 24
Peak memory 196780 kb
Host smart-040459a4-616e-4a22-859c-3aec2df40e6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985813693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.1985813693
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.1595085657
Short name T553
Test name
Test status
Simulation time 204009810 ps
CPU time 1.11 seconds
Started Jul 16 04:53:39 PM PDT 24
Finished Jul 16 04:53:43 PM PDT 24
Peak memory 194716 kb
Host smart-171cf0a6-5a6d-4a6a-8163-cf655d287521
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595085657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.1595085657
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.3207839847
Short name T583
Test name
Test status
Simulation time 100077588 ps
CPU time 1.03 seconds
Started Jul 16 04:53:34 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 196696 kb
Host smart-dfd1d670-645c-404d-89ed-b0b34de00107
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207839847 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.3207839847
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.732899127
Short name T91
Test name
Test status
Simulation time 15464348 ps
CPU time 0.55 seconds
Started Jul 16 04:53:34 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 182172 kb
Host smart-edc00129-0eb5-489d-9847-d679b8634010
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732899127 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.732899127
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.581695271
Short name T570
Test name
Test status
Simulation time 13814426 ps
CPU time 0.53 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:44 PM PDT 24
Peak memory 181452 kb
Host smart-18e0df6d-9bb7-46f3-a6a4-33f33cb5e55f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581695271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.581695271
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1436455656
Short name T527
Test name
Test status
Simulation time 48648133 ps
CPU time 0.71 seconds
Started Jul 16 04:53:35 PM PDT 24
Finished Jul 16 04:53:37 PM PDT 24
Peak memory 191036 kb
Host smart-2cc9ebcb-1781-4c89-af87-56e82c11e566
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436455656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1436455656
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.4120885984
Short name T524
Test name
Test status
Simulation time 78390707 ps
CPU time 1.68 seconds
Started Jul 16 04:53:30 PM PDT 24
Finished Jul 16 04:53:32 PM PDT 24
Peak memory 196880 kb
Host smart-4835f803-9be4-4b9d-a412-21bcd474bc7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120885984 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.4120885984
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.1644711167
Short name T549
Test name
Test status
Simulation time 90195518 ps
CPU time 0.85 seconds
Started Jul 16 04:53:32 PM PDT 24
Finished Jul 16 04:53:34 PM PDT 24
Peak memory 192868 kb
Host smart-61625361-8e19-4fbe-bc0d-06b58f4dd3d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644711167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.1644711167
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.1501095723
Short name T495
Test name
Test status
Simulation time 43438042 ps
CPU time 0.92 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:38 PM PDT 24
Peak memory 196504 kb
Host smart-5620bded-f5eb-4b0f-ae5d-096cde0cf26b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501095723 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.1501095723
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.863410758
Short name T96
Test name
Test status
Simulation time 17069996 ps
CPU time 0.56 seconds
Started Jul 16 04:53:34 PM PDT 24
Finished Jul 16 04:53:35 PM PDT 24
Peak memory 182088 kb
Host smart-0e3e2b03-daf9-43db-839a-4512d95ef77c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863410758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.863410758
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.2935841191
Short name T492
Test name
Test status
Simulation time 44501259 ps
CPU time 0.54 seconds
Started Jul 16 04:53:34 PM PDT 24
Finished Jul 16 04:53:35 PM PDT 24
Peak memory 181996 kb
Host smart-62d911c2-b5c9-4132-8dc0-b04e57c00dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935841191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.2935841191
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.3941448883
Short name T552
Test name
Test status
Simulation time 16098795 ps
CPU time 0.7 seconds
Started Jul 16 04:53:35 PM PDT 24
Finished Jul 16 04:53:37 PM PDT 24
Peak memory 192636 kb
Host smart-28cfb48b-92cd-45ad-a98f-8c74ea3dbcbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941448883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.3941448883
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.1227500688
Short name T472
Test name
Test status
Simulation time 44881220 ps
CPU time 2.04 seconds
Started Jul 16 04:53:34 PM PDT 24
Finished Jul 16 04:53:37 PM PDT 24
Peak memory 196900 kb
Host smart-c7e05ccc-29d7-4cdf-a0af-304e61b4f84a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227500688 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.1227500688
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.104747416
Short name T578
Test name
Test status
Simulation time 89977670 ps
CPU time 0.79 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 182648 kb
Host smart-7d9bc06e-3486-47b5-9981-637e8727b669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104747416 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_in
tg_err.104747416
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.1621344037
Short name T579
Test name
Test status
Simulation time 30885667 ps
CPU time 0.83 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 195996 kb
Host smart-b079a942-4ee3-423f-bf52-aadc021c3b92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621344037 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.1621344037
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1272944849
Short name T516
Test name
Test status
Simulation time 12428775 ps
CPU time 0.62 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:40 PM PDT 24
Peak memory 182112 kb
Host smart-7a6ad60d-1dca-43e6-abd7-fd8caed0a16c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272944849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1272944849
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.1598972312
Short name T551
Test name
Test status
Simulation time 16370050 ps
CPU time 0.56 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 182004 kb
Host smart-3c1574d1-8fb6-4f04-88c2-8abd6e3207c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598972312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.1598972312
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.2228230794
Short name T582
Test name
Test status
Simulation time 35043007 ps
CPU time 0.75 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 192624 kb
Host smart-2c9ecf24-4ad0-44df-aa9a-8fdf0149cc54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228230794 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.2228230794
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.4267881512
Short name T536
Test name
Test status
Simulation time 45636456 ps
CPU time 1.97 seconds
Started Jul 16 04:53:34 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 196892 kb
Host smart-73e4f3f9-658a-474b-9607-359455b1d01b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267881512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.4267881512
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1983371624
Short name T565
Test name
Test status
Simulation time 1637297682 ps
CPU time 1.33 seconds
Started Jul 16 04:53:32 PM PDT 24
Finished Jul 16 04:53:34 PM PDT 24
Peak memory 182504 kb
Host smart-4e73b71d-61d1-4fe3-ab34-a3c091e4a0f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983371624 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1983371624
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.2016877725
Short name T59
Test name
Test status
Simulation time 47141463 ps
CPU time 0.73 seconds
Started Jul 16 04:53:31 PM PDT 24
Finished Jul 16 04:53:32 PM PDT 24
Peak memory 193932 kb
Host smart-92e4a2c2-83e6-446c-8807-cad2e749e154
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016877725 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.2016877725
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.2486944124
Short name T70
Test name
Test status
Simulation time 205975369 ps
CPU time 0.55 seconds
Started Jul 16 04:53:34 PM PDT 24
Finished Jul 16 04:53:35 PM PDT 24
Peak memory 182120 kb
Host smart-02a21aac-1ec6-4e7f-b77f-fd4799869a22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486944124 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.2486944124
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2531269585
Short name T498
Test name
Test status
Simulation time 32756511 ps
CPU time 0.58 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:40 PM PDT 24
Peak memory 181980 kb
Host smart-b7b10e5e-3a57-486e-99b9-a6d65690785a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531269585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2531269585
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1844682221
Short name T537
Test name
Test status
Simulation time 54890886 ps
CPU time 0.62 seconds
Started Jul 16 04:53:35 PM PDT 24
Finished Jul 16 04:53:38 PM PDT 24
Peak memory 191016 kb
Host smart-950ca7da-2e64-421e-af25-875da2cdb3bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844682221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1844682221
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.4284238487
Short name T480
Test name
Test status
Simulation time 128593490 ps
CPU time 1.46 seconds
Started Jul 16 04:53:38 PM PDT 24
Finished Jul 16 04:53:42 PM PDT 24
Peak memory 196800 kb
Host smart-0616452a-e35f-46d3-a5dc-0a49e2062925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284238487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.4284238487
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2950027502
Short name T544
Test name
Test status
Simulation time 159083431 ps
CPU time 0.77 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 182396 kb
Host smart-ac24d631-15cf-40cc-b59b-0340c216683b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950027502 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_i
ntg_err.2950027502
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.2984689831
Short name T538
Test name
Test status
Simulation time 73703736 ps
CPU time 0.72 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:38 PM PDT 24
Peak memory 194844 kb
Host smart-77cb5f22-b3f2-4fc0-8671-64b0a20aa872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984689831 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.2984689831
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2989275152
Short name T520
Test name
Test status
Simulation time 17170740 ps
CPU time 0.61 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 182112 kb
Host smart-5d48287d-86d9-480e-b4d6-75e3103fb2f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989275152 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2989275152
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.2146915529
Short name T575
Test name
Test status
Simulation time 15187080 ps
CPU time 0.53 seconds
Started Jul 16 04:53:35 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 181532 kb
Host smart-259f3b5d-8ead-4fda-9d1a-296b6b72d627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146915529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.2146915529
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.1410827249
Short name T469
Test name
Test status
Simulation time 46313331 ps
CPU time 2.42 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:40 PM PDT 24
Peak memory 196880 kb
Host smart-e77fef48-3c90-41ba-8acd-e43023aad5c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410827249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.1410827249
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.2488817339
Short name T114
Test name
Test status
Simulation time 87408903 ps
CPU time 1.08 seconds
Started Jul 16 04:53:34 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 194324 kb
Host smart-5f25cf3a-96dd-437a-8887-a17a3c056f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488817339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.2488817339
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.3227766933
Short name T546
Test name
Test status
Simulation time 94611447 ps
CPU time 0.95 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:38 PM PDT 24
Peak memory 196308 kb
Host smart-a97ee46e-f1b8-4962-90d8-179967754d1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227766933 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.3227766933
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.2110567627
Short name T93
Test name
Test status
Simulation time 116798956 ps
CPU time 0.56 seconds
Started Jul 16 04:53:35 PM PDT 24
Finished Jul 16 04:53:37 PM PDT 24
Peak memory 182084 kb
Host smart-a9bda1e6-b476-4b5f-866a-d7bc33523f80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110567627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.2110567627
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.511373799
Short name T493
Test name
Test status
Simulation time 70922532 ps
CPU time 0.59 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 181960 kb
Host smart-7c0e9154-5414-4dad-bbc7-83bf8172a2a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511373799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.511373799
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.3768531650
Short name T107
Test name
Test status
Simulation time 68253029 ps
CPU time 0.76 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:40 PM PDT 24
Peak memory 192708 kb
Host smart-fab19323-dcd1-44a8-b7fb-502f301c78d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768531650 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_t
imer_same_csr_outstanding.3768531650
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.857328139
Short name T499
Test name
Test status
Simulation time 48659967 ps
CPU time 2.16 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:41 PM PDT 24
Peak memory 196896 kb
Host smart-523c3a2f-f179-4dde-baa2-d22ed02ebd5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857328139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.857328139
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3475638661
Short name T113
Test name
Test status
Simulation time 154405182 ps
CPU time 0.85 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 182388 kb
Host smart-a0b7b763-11b9-4ab5-a66b-fc27df2d52d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475638661 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_i
ntg_err.3475638661
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.768026491
Short name T569
Test name
Test status
Simulation time 140366688 ps
CPU time 0.93 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 196864 kb
Host smart-77abac9a-4c3a-47e5-92c3-4a5fe2a8678d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768026491 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.768026491
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.1043211652
Short name T111
Test name
Test status
Simulation time 24071335 ps
CPU time 0.54 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:40 PM PDT 24
Peak memory 182072 kb
Host smart-4e3906de-91cc-48af-b1cd-377c67d80fb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043211652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.1043211652
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.732464875
Short name T512
Test name
Test status
Simulation time 19349066 ps
CPU time 0.58 seconds
Started Jul 16 04:53:38 PM PDT 24
Finished Jul 16 04:53:41 PM PDT 24
Peak memory 181232 kb
Host smart-6c4b789d-8d6e-4344-acbe-f99c5c0582c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732464875 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.732464875
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.1421987616
Short name T87
Test name
Test status
Simulation time 114160235 ps
CPU time 0.79 seconds
Started Jul 16 04:53:33 PM PDT 24
Finished Jul 16 04:53:35 PM PDT 24
Peak memory 192912 kb
Host smart-e1529727-1518-4967-8002-7ff451a55a36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421987616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_t
imer_same_csr_outstanding.1421987616
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2734851660
Short name T522
Test name
Test status
Simulation time 238215986 ps
CPU time 2.95 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:41 PM PDT 24
Peak memory 197044 kb
Host smart-e837348a-3568-4e50-9667-2c62c1940e40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734851660 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2734851660
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.790653307
Short name T470
Test name
Test status
Simulation time 395203239 ps
CPU time 0.8 seconds
Started Jul 16 04:53:38 PM PDT 24
Finished Jul 16 04:53:41 PM PDT 24
Peak memory 192900 kb
Host smart-dbe798e5-d789-4b40-bf2d-de5e87dfa51a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790653307 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.790653307
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.1754853327
Short name T518
Test name
Test status
Simulation time 30542870 ps
CPU time 0.71 seconds
Started Jul 16 04:53:23 PM PDT 24
Finished Jul 16 04:53:26 PM PDT 24
Peak memory 191336 kb
Host smart-5ecf8319-4480-4493-932f-207a0f68052a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754853327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.1754853327
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3263808070
Short name T531
Test name
Test status
Simulation time 149106368 ps
CPU time 1.62 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:22 PM PDT 24
Peak memory 190528 kb
Host smart-70c0637f-8f56-4520-b9c3-ad59cfbc6a0d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263808070 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3263808070
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.1613706860
Short name T92
Test name
Test status
Simulation time 41465372 ps
CPU time 0.55 seconds
Started Jul 16 04:53:17 PM PDT 24
Finished Jul 16 04:53:18 PM PDT 24
Peak memory 182104 kb
Host smart-a56ed9a4-0003-4eb3-a052-243b25a83f74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613706860 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.1613706860
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2489977185
Short name T488
Test name
Test status
Simulation time 189894903 ps
CPU time 1.46 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:23 PM PDT 24
Peak memory 197056 kb
Host smart-2decd91f-8548-453e-a13c-aa3e9a804ac3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489977185 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.2489977185
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.4122780092
Short name T523
Test name
Test status
Simulation time 36255166 ps
CPU time 0.59 seconds
Started Jul 16 04:53:21 PM PDT 24
Finished Jul 16 04:53:23 PM PDT 24
Peak memory 182004 kb
Host smart-673ea16c-8a9d-4aa3-86c4-bbf9b609a19f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122780092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.4122780092
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.4004905046
Short name T548
Test name
Test status
Simulation time 42024471 ps
CPU time 0.52 seconds
Started Jul 16 04:53:18 PM PDT 24
Finished Jul 16 04:53:19 PM PDT 24
Peak memory 181456 kb
Host smart-9abddce6-7501-4d01-b043-553167b6dab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004905046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.4004905046
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.3529993216
Short name T558
Test name
Test status
Simulation time 195865121 ps
CPU time 0.81 seconds
Started Jul 16 04:53:23 PM PDT 24
Finished Jul 16 04:53:26 PM PDT 24
Peak memory 192400 kb
Host smart-00f3e1da-e45d-4823-bde2-0be25d7da1d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529993216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.3529993216
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1363162549
Short name T489
Test name
Test status
Simulation time 131818312 ps
CPU time 2.49 seconds
Started Jul 16 04:53:22 PM PDT 24
Finished Jul 16 04:53:27 PM PDT 24
Peak memory 197224 kb
Host smart-b9ec81bc-fd59-457f-b527-7712ee824e98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363162549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1363162549
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.558028603
Short name T115
Test name
Test status
Simulation time 112277363 ps
CPU time 1.32 seconds
Started Jul 16 04:53:23 PM PDT 24
Finished Jul 16 04:53:25 PM PDT 24
Peak memory 194596 kb
Host smart-492c953b-a1eb-4e08-bcdd-9e89ad3f76a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558028603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_int
g_err.558028603
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.408242764
Short name T525
Test name
Test status
Simulation time 17082476 ps
CPU time 0.56 seconds
Started Jul 16 04:53:32 PM PDT 24
Finished Jul 16 04:53:33 PM PDT 24
Peak memory 182000 kb
Host smart-9b87de1c-8354-4701-941c-c6dfc7d89e94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408242764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.408242764
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.1933099282
Short name T530
Test name
Test status
Simulation time 50435290 ps
CPU time 0.58 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:41 PM PDT 24
Peak memory 182004 kb
Host smart-5b00f014-b514-46c2-8e35-64517c8789b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933099282 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.1933099282
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.567081806
Short name T501
Test name
Test status
Simulation time 11061631 ps
CPU time 0.56 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:38 PM PDT 24
Peak memory 182100 kb
Host smart-7ea0db26-284c-4d34-81a5-549fedc4aadd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567081806 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.567081806
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.2473476822
Short name T467
Test name
Test status
Simulation time 33123195 ps
CPU time 0.55 seconds
Started Jul 16 04:53:33 PM PDT 24
Finished Jul 16 04:53:34 PM PDT 24
Peak memory 182004 kb
Host smart-68837ba2-ff31-40d7-b4e4-544419e5a2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473476822 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.2473476822
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2632544007
Short name T557
Test name
Test status
Simulation time 29788903 ps
CPU time 0.67 seconds
Started Jul 16 04:53:38 PM PDT 24
Finished Jul 16 04:53:41 PM PDT 24
Peak memory 181988 kb
Host smart-2a28c4c1-52c0-4d4c-8b2c-94416c66d308
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632544007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2632544007
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.1065565550
Short name T580
Test name
Test status
Simulation time 208796018 ps
CPU time 0.56 seconds
Started Jul 16 04:53:38 PM PDT 24
Finished Jul 16 04:53:41 PM PDT 24
Peak memory 181208 kb
Host smart-9725f717-2145-4477-aded-eb8166dcf986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065565550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.1065565550
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.2783184090
Short name T514
Test name
Test status
Simulation time 37826179 ps
CPU time 0.57 seconds
Started Jul 16 04:53:40 PM PDT 24
Finished Jul 16 04:53:43 PM PDT 24
Peak memory 181556 kb
Host smart-3d66c19b-d631-4092-8806-b0d9782305cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783184090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.2783184090
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.3466677927
Short name T476
Test name
Test status
Simulation time 59436911 ps
CPU time 0.58 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:44 PM PDT 24
Peak memory 182020 kb
Host smart-1b2f47f5-22a1-4981-a797-7ce608145095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466677927 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.3466677927
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.2437181811
Short name T517
Test name
Test status
Simulation time 18424428 ps
CPU time 0.56 seconds
Started Jul 16 04:53:40 PM PDT 24
Finished Jul 16 04:53:43 PM PDT 24
Peak memory 182076 kb
Host smart-e9325574-125d-41c1-bb03-9d8ce38d6cef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437181811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.2437181811
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.2394193484
Short name T545
Test name
Test status
Simulation time 61053691 ps
CPU time 0.56 seconds
Started Jul 16 04:53:35 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 182024 kb
Host smart-eb210f7a-3299-4b0f-aa4b-0e64b0fe454a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394193484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.2394193484
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.3204535271
Short name T100
Test name
Test status
Simulation time 46184841 ps
CPU time 0.74 seconds
Started Jul 16 04:53:18 PM PDT 24
Finished Jul 16 04:53:20 PM PDT 24
Peak memory 182028 kb
Host smart-86ce9271-a0b0-4db0-aab2-f218c20d0e35
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204535271 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.3204535271
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.3011345917
Short name T483
Test name
Test status
Simulation time 195907653 ps
CPU time 2.47 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:23 PM PDT 24
Peak memory 190460 kb
Host smart-267ee533-6bdb-454f-8e67-7315fb908167
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011345917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.3011345917
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.638447104
Short name T485
Test name
Test status
Simulation time 22716054 ps
CPU time 0.64 seconds
Started Jul 16 04:53:22 PM PDT 24
Finished Jul 16 04:53:24 PM PDT 24
Peak memory 182084 kb
Host smart-a12d3f37-b480-40b8-b73a-5bbae5100292
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638447104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.638447104
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.155818446
Short name T515
Test name
Test status
Simulation time 86451340 ps
CPU time 0.89 seconds
Started Jul 16 04:53:21 PM PDT 24
Finished Jul 16 04:53:24 PM PDT 24
Peak memory 196556 kb
Host smart-352879e1-48e6-4b30-a13e-ca394cb83712
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155818446 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.155818446
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3053062524
Short name T508
Test name
Test status
Simulation time 12814812 ps
CPU time 0.57 seconds
Started Jul 16 04:53:16 PM PDT 24
Finished Jul 16 04:53:18 PM PDT 24
Peak memory 181844 kb
Host smart-96d88e17-b5a8-4284-9008-35811bfc8285
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053062524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3053062524
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1948834755
Short name T540
Test name
Test status
Simulation time 41779688 ps
CPU time 0.56 seconds
Started Jul 16 04:53:21 PM PDT 24
Finished Jul 16 04:53:23 PM PDT 24
Peak memory 182008 kb
Host smart-f32a7838-14f1-4c48-8a7f-ee767b92976b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948834755 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1948834755
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.3657019602
Short name T102
Test name
Test status
Simulation time 31936668 ps
CPU time 0.67 seconds
Started Jul 16 04:53:21 PM PDT 24
Finished Jul 16 04:53:22 PM PDT 24
Peak memory 191468 kb
Host smart-a645c438-48c2-4bef-a9b8-5683a46cb97c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657019602 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.3657019602
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.3542259323
Short name T535
Test name
Test status
Simulation time 49707651 ps
CPU time 1.22 seconds
Started Jul 16 04:53:21 PM PDT 24
Finished Jul 16 04:53:24 PM PDT 24
Peak memory 196720 kb
Host smart-10c3d985-d8e2-4f91-b474-ae2c4dd690c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542259323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.3542259323
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.3617250399
Short name T118
Test name
Test status
Simulation time 316808293 ps
CPU time 1.09 seconds
Started Jul 16 04:53:23 PM PDT 24
Finished Jul 16 04:53:26 PM PDT 24
Peak memory 194272 kb
Host smart-b7eaf6cf-4295-4cef-969c-a8beae978eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617250399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.3617250399
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.3728053372
Short name T464
Test name
Test status
Simulation time 52983780 ps
CPU time 0.61 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:45 PM PDT 24
Peak memory 182080 kb
Host smart-8eccc16b-dc39-4a48-9ea4-5bea73d882ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728053372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.3728053372
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.3355835981
Short name T567
Test name
Test status
Simulation time 46945146 ps
CPU time 0.57 seconds
Started Jul 16 04:53:35 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 182028 kb
Host smart-4d24321d-0963-4633-a251-2f56f75d00ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355835981 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.3355835981
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.358614332
Short name T568
Test name
Test status
Simulation time 15711635 ps
CPU time 0.55 seconds
Started Jul 16 04:53:41 PM PDT 24
Finished Jul 16 04:53:43 PM PDT 24
Peak memory 182060 kb
Host smart-193bf8f6-fd21-46af-81e5-bbbdabc1dbbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358614332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.358614332
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.919655656
Short name T473
Test name
Test status
Simulation time 19668981 ps
CPU time 0.58 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:44 PM PDT 24
Peak memory 182084 kb
Host smart-e94b2176-7cfa-4a0b-85bc-deac357e02c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919655656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.919655656
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.2370851323
Short name T559
Test name
Test status
Simulation time 23502583 ps
CPU time 0.58 seconds
Started Jul 16 04:53:35 PM PDT 24
Finished Jul 16 04:53:38 PM PDT 24
Peak memory 181936 kb
Host smart-6d8420d3-9e8e-46b0-8d42-068fd1b4da8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370851323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.2370851323
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.3443950485
Short name T554
Test name
Test status
Simulation time 113983936 ps
CPU time 0.53 seconds
Started Jul 16 04:53:38 PM PDT 24
Finished Jul 16 04:53:42 PM PDT 24
Peak memory 181664 kb
Host smart-29adce8b-1716-487c-98ba-960a311807e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443950485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.3443950485
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.2995359849
Short name T491
Test name
Test status
Simulation time 192751011 ps
CPU time 0.58 seconds
Started Jul 16 04:55:06 PM PDT 24
Finished Jul 16 04:55:10 PM PDT 24
Peak memory 182164 kb
Host smart-7d1f3fac-d912-4fc6-ab12-275b727d2505
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995359849 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.2995359849
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2999050241
Short name T474
Test name
Test status
Simulation time 25160023 ps
CPU time 0.53 seconds
Started Jul 16 04:53:40 PM PDT 24
Finished Jul 16 04:53:43 PM PDT 24
Peak memory 181448 kb
Host smart-feae09a9-c4dc-47a4-91c3-0b2df2b9d80e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999050241 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2999050241
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.2157431575
Short name T543
Test name
Test status
Simulation time 24505283 ps
CPU time 0.54 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 181920 kb
Host smart-1d2c8894-d6fe-42b8-915a-45c9778822c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157431575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.2157431575
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.3928902211
Short name T466
Test name
Test status
Simulation time 115231105 ps
CPU time 0.52 seconds
Started Jul 16 04:53:40 PM PDT 24
Finished Jul 16 04:53:42 PM PDT 24
Peak memory 181196 kb
Host smart-959cabec-b4ca-4681-b264-e45c743c6f99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928902211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.3928902211
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.34981622
Short name T94
Test name
Test status
Simulation time 28333994 ps
CPU time 0.74 seconds
Started Jul 16 04:53:23 PM PDT 24
Finished Jul 16 04:53:25 PM PDT 24
Peak memory 191328 kb
Host smart-8fe89ad3-8623-4a8e-a47c-77b106056ca1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34981622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_aliasi
ng.34981622
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3010469455
Short name T513
Test name
Test status
Simulation time 346504119 ps
CPU time 2.73 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:24 PM PDT 24
Peak memory 190604 kb
Host smart-4d3876f6-fdd7-40b9-a296-a0652868850d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010469455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3010469455
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.2183506988
Short name T584
Test name
Test status
Simulation time 15144299 ps
CPU time 0.6 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:22 PM PDT 24
Peak memory 182080 kb
Host smart-0362c335-9ff5-4900-b122-24f32ed62fb7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183506988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_r
eset.2183506988
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.2020171636
Short name T541
Test name
Test status
Simulation time 56062160 ps
CPU time 0.67 seconds
Started Jul 16 04:53:23 PM PDT 24
Finished Jul 16 04:53:25 PM PDT 24
Peak memory 192684 kb
Host smart-64ca0255-7d28-4e8f-8d96-86c184b16001
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020171636 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.2020171636
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2962980572
Short name T526
Test name
Test status
Simulation time 129111779 ps
CPU time 0.58 seconds
Started Jul 16 04:53:21 PM PDT 24
Finished Jul 16 04:53:23 PM PDT 24
Peak memory 182084 kb
Host smart-07b8a2e9-922c-493c-9798-103a5669be0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962980572 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2962980572
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.1855823333
Short name T542
Test name
Test status
Simulation time 14756170 ps
CPU time 0.57 seconds
Started Jul 16 04:53:23 PM PDT 24
Finished Jul 16 04:53:25 PM PDT 24
Peak memory 181996 kb
Host smart-d71d80c6-eb8b-40db-b8d0-73bca191af44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855823333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.1855823333
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.2005567627
Short name T103
Test name
Test status
Simulation time 129565224 ps
CPU time 0.7 seconds
Started Jul 16 04:53:19 PM PDT 24
Finished Jul 16 04:53:21 PM PDT 24
Peak memory 191332 kb
Host smart-f83a6b50-1262-4f49-9e6a-311f5716680c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005567627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_ti
mer_same_csr_outstanding.2005567627
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.3038754643
Short name T482
Test name
Test status
Simulation time 17686809 ps
CPU time 0.88 seconds
Started Jul 16 04:53:19 PM PDT 24
Finished Jul 16 04:53:21 PM PDT 24
Peak memory 194600 kb
Host smart-f139cc96-da8d-48de-abf5-956136976700
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038754643 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.3038754643
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.2704545366
Short name T529
Test name
Test status
Simulation time 43869287 ps
CPU time 0.89 seconds
Started Jul 16 04:53:22 PM PDT 24
Finished Jul 16 04:53:25 PM PDT 24
Peak memory 192120 kb
Host smart-5d1a8425-27d8-4d32-a28c-1d9e3b374d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704545366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.2704545366
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.680658315
Short name T534
Test name
Test status
Simulation time 12512611 ps
CPU time 0.53 seconds
Started Jul 16 04:53:39 PM PDT 24
Finished Jul 16 04:53:42 PM PDT 24
Peak memory 181464 kb
Host smart-a6c56da1-055c-4ca1-9e75-b096ca3461e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680658315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.680658315
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.640412410
Short name T560
Test name
Test status
Simulation time 19645515 ps
CPU time 0.53 seconds
Started Jul 16 04:53:40 PM PDT 24
Finished Jul 16 04:53:43 PM PDT 24
Peak memory 181652 kb
Host smart-a39da755-b89c-4edd-9af5-eb35063e8d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640412410 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.640412410
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.4087769316
Short name T502
Test name
Test status
Simulation time 16774190 ps
CPU time 0.57 seconds
Started Jul 16 04:53:40 PM PDT 24
Finished Jul 16 04:53:43 PM PDT 24
Peak memory 181732 kb
Host smart-bd8fa6cb-be22-463c-83e6-cca7f59d9b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087769316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.4087769316
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.2499393177
Short name T468
Test name
Test status
Simulation time 13273479 ps
CPU time 0.56 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:44 PM PDT 24
Peak memory 181488 kb
Host smart-222b9193-1a89-4021-b398-f6bb4c13a3b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499393177 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.2499393177
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.3493387767
Short name T533
Test name
Test status
Simulation time 13135510 ps
CPU time 0.55 seconds
Started Jul 16 04:53:41 PM PDT 24
Finished Jul 16 04:53:43 PM PDT 24
Peak memory 181984 kb
Host smart-09d2b615-1079-4c53-8376-485bc902d200
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493387767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.3493387767
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.17146547
Short name T481
Test name
Test status
Simulation time 33011471 ps
CPU time 0.55 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:45 PM PDT 24
Peak memory 182012 kb
Host smart-a6f02ab3-816d-42bc-8914-e388a7884d9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17146547 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.17146547
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.773204716
Short name T477
Test name
Test status
Simulation time 32609032 ps
CPU time 0.6 seconds
Started Jul 16 04:53:42 PM PDT 24
Finished Jul 16 04:53:44 PM PDT 24
Peak memory 181800 kb
Host smart-877c7d4e-0f42-430d-b028-492e7a2901f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773204716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.773204716
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2018213484
Short name T479
Test name
Test status
Simulation time 47861524 ps
CPU time 0.54 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:40 PM PDT 24
Peak memory 181956 kb
Host smart-15e8b1f6-19e1-4d8e-9917-60cba67e36fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018213484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2018213484
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.3782530051
Short name T503
Test name
Test status
Simulation time 44499810 ps
CPU time 0.55 seconds
Started Jul 16 04:53:35 PM PDT 24
Finished Jul 16 04:53:36 PM PDT 24
Peak memory 182364 kb
Host smart-42fe34f5-94ad-4346-94f2-552bcb129cc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782530051 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.3782530051
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.1327346162
Short name T573
Test name
Test status
Simulation time 15912356 ps
CPU time 0.54 seconds
Started Jul 16 04:53:41 PM PDT 24
Finished Jul 16 04:53:44 PM PDT 24
Peak memory 182088 kb
Host smart-bdf837de-5cb9-495e-9670-7e303ef10afb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327346162 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.1327346162
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.2191803057
Short name T576
Test name
Test status
Simulation time 109281258 ps
CPU time 0.9 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:22 PM PDT 24
Peak memory 196408 kb
Host smart-e08af8f7-53cb-4055-a183-b191ed5cd94e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191803057 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.2191803057
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2173034338
Short name T97
Test name
Test status
Simulation time 13723371 ps
CPU time 0.64 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:22 PM PDT 24
Peak memory 182072 kb
Host smart-4c3e10e6-eeaf-428c-a8fd-0d7190a887f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173034338 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2173034338
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1428676141
Short name T490
Test name
Test status
Simulation time 109287344 ps
CPU time 0.56 seconds
Started Jul 16 04:53:22 PM PDT 24
Finished Jul 16 04:53:25 PM PDT 24
Peak memory 182036 kb
Host smart-e91d7632-1da8-42f9-a376-2584a2d9b6ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428676141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1428676141
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.2658396438
Short name T105
Test name
Test status
Simulation time 37001477 ps
CPU time 0.67 seconds
Started Jul 16 04:53:19 PM PDT 24
Finished Jul 16 04:53:20 PM PDT 24
Peak memory 190844 kb
Host smart-6c7bde14-877e-499c-97c6-f5a79e7954cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658396438 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.2658396438
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.468008620
Short name T505
Test name
Test status
Simulation time 55107452 ps
CPU time 1.26 seconds
Started Jul 16 04:53:21 PM PDT 24
Finished Jul 16 04:53:24 PM PDT 24
Peak memory 196696 kb
Host smart-620db244-6d76-47ac-9ee1-b6c28bbfa45c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468008620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.468008620
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2954221435
Short name T117
Test name
Test status
Simulation time 70886090 ps
CPU time 0.79 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:22 PM PDT 24
Peak memory 182468 kb
Host smart-751506c5-8690-459d-89fc-bcf5cd48e3ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954221435 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2954221435
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.307985268
Short name T475
Test name
Test status
Simulation time 19596171 ps
CPU time 0.88 seconds
Started Jul 16 04:53:26 PM PDT 24
Finished Jul 16 04:53:27 PM PDT 24
Peak memory 196072 kb
Host smart-865faa78-b2ca-4fab-88a3-67bda3d1ba9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307985268 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.307985268
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.855894828
Short name T101
Test name
Test status
Simulation time 44270914 ps
CPU time 0.54 seconds
Started Jul 16 04:53:22 PM PDT 24
Finished Jul 16 04:53:25 PM PDT 24
Peak memory 182328 kb
Host smart-42b3d11e-7b56-4e5a-b366-ef1d9c2aba82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855894828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.855894828
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.2345932498
Short name T521
Test name
Test status
Simulation time 20787641 ps
CPU time 0.63 seconds
Started Jul 16 04:53:21 PM PDT 24
Finished Jul 16 04:53:23 PM PDT 24
Peak memory 181968 kb
Host smart-70a4d02e-5d89-48ae-8809-fb7cb4ad1919
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345932498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.2345932498
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.194302948
Short name T509
Test name
Test status
Simulation time 40552344 ps
CPU time 0.83 seconds
Started Jul 16 04:53:21 PM PDT 24
Finished Jul 16 04:53:24 PM PDT 24
Peak memory 192764 kb
Host smart-d27a0b00-20f0-4908-9a1b-14e1f7d216d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194302948 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_tim
er_same_csr_outstanding.194302948
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.558505667
Short name T500
Test name
Test status
Simulation time 581327670 ps
CPU time 2.6 seconds
Started Jul 16 04:53:24 PM PDT 24
Finished Jul 16 04:53:29 PM PDT 24
Peak memory 196880 kb
Host smart-bc4a0a67-e169-4281-a67e-c9058ce5160e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558505667 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.558505667
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.1580395752
Short name T562
Test name
Test status
Simulation time 199589682 ps
CPU time 1.33 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:23 PM PDT 24
Peak memory 194820 kb
Host smart-c35f65b1-7f07-4480-bc71-c369e2b8627c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580395752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.1580395752
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.3364178066
Short name T465
Test name
Test status
Simulation time 92731563 ps
CPU time 1.11 seconds
Started Jul 16 04:53:22 PM PDT 24
Finished Jul 16 04:53:24 PM PDT 24
Peak memory 196840 kb
Host smart-ebe96610-4b71-4847-a976-b4c3d7defa9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364178066 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.3364178066
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1705286451
Short name T547
Test name
Test status
Simulation time 44595088 ps
CPU time 0.62 seconds
Started Jul 16 04:53:20 PM PDT 24
Finished Jul 16 04:53:21 PM PDT 24
Peak memory 182084 kb
Host smart-7f23caf7-224a-4cef-a1f1-51ca99c9026d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705286451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1705286451
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.3575104833
Short name T484
Test name
Test status
Simulation time 18311109 ps
CPU time 0.56 seconds
Started Jul 16 04:53:22 PM PDT 24
Finished Jul 16 04:53:25 PM PDT 24
Peak memory 181984 kb
Host smart-10cae453-30e0-4fd4-83c4-23f6c49c3e0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575104833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.3575104833
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.2727392696
Short name T37
Test name
Test status
Simulation time 99754812 ps
CPU time 0.79 seconds
Started Jul 16 04:53:21 PM PDT 24
Finished Jul 16 04:53:23 PM PDT 24
Peak memory 190944 kb
Host smart-11f44ae0-565d-4d1c-aec3-c8b201d17888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727392696 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.2727392696
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.2100537433
Short name T478
Test name
Test status
Simulation time 148057447 ps
CPU time 1.09 seconds
Started Jul 16 04:53:22 PM PDT 24
Finished Jul 16 04:53:25 PM PDT 24
Peak memory 195184 kb
Host smart-2a6ac232-5bff-4819-ac59-2b2764b2d71b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100537433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.2100537433
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1684334018
Short name T35
Test name
Test status
Simulation time 287506509 ps
CPU time 1.07 seconds
Started Jul 16 04:53:23 PM PDT 24
Finished Jul 16 04:53:25 PM PDT 24
Peak memory 194652 kb
Host smart-98eb6d5b-7b1a-4a4b-aaca-09aa79d0f3e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684334018 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1684334018
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.2808877076
Short name T57
Test name
Test status
Simulation time 130724484 ps
CPU time 0.87 seconds
Started Jul 16 04:53:31 PM PDT 24
Finished Jul 16 04:53:32 PM PDT 24
Peak memory 196560 kb
Host smart-8326a578-7938-4341-9ea7-f1939071d72e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808877076 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.2808877076
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3938612648
Short name T88
Test name
Test status
Simulation time 38219212 ps
CPU time 0.57 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:40 PM PDT 24
Peak memory 182100 kb
Host smart-7f055095-6ccc-42e1-8fe6-823910f9071a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938612648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3938612648
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.1210948201
Short name T506
Test name
Test status
Simulation time 17603128 ps
CPU time 0.55 seconds
Started Jul 16 04:53:38 PM PDT 24
Finished Jul 16 04:53:41 PM PDT 24
Peak memory 181964 kb
Host smart-0ae123e8-60b0-4670-9fb1-90919be7cd54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210948201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.1210948201
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.2876695987
Short name T106
Test name
Test status
Simulation time 69359273 ps
CPU time 0.76 seconds
Started Jul 16 04:53:33 PM PDT 24
Finished Jul 16 04:53:35 PM PDT 24
Peak memory 192700 kb
Host smart-c8ff3c04-f067-472b-ab66-40851c7cd6e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876695987 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.2876695987
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.864801529
Short name T581
Test name
Test status
Simulation time 23902521 ps
CPU time 1.12 seconds
Started Jul 16 04:53:23 PM PDT 24
Finished Jul 16 04:53:26 PM PDT 24
Peak memory 196880 kb
Host smart-f566c1e7-8803-45bc-a6de-6355aa4dbce8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864801529 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.864801529
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.1563132821
Short name T507
Test name
Test status
Simulation time 112553170 ps
CPU time 1.25 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:41 PM PDT 24
Peak memory 196752 kb
Host smart-e92d5f55-572b-486f-9dfa-f2cf4ce01a4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563132821 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.1563132821
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.4132536411
Short name T95
Test name
Test status
Simulation time 12566698 ps
CPU time 0.58 seconds
Started Jul 16 04:53:32 PM PDT 24
Finished Jul 16 04:53:33 PM PDT 24
Peak memory 182092 kb
Host smart-d4402e38-eb83-4c53-a5d9-4bc605647cf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132536411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.4132536411
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.430108937
Short name T486
Test name
Test status
Simulation time 76785227 ps
CPU time 0.54 seconds
Started Jul 16 04:53:37 PM PDT 24
Finished Jul 16 04:53:40 PM PDT 24
Peak memory 181964 kb
Host smart-edb52af0-f39f-4575-8bec-c076ca7f5781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430108937 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.430108937
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2448089603
Short name T104
Test name
Test status
Simulation time 167997348 ps
CPU time 0.65 seconds
Started Jul 16 04:53:36 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 190892 kb
Host smart-f30490ba-dd07-40d7-bbfc-64a3e206e990
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448089603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2448089603
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.1342870115
Short name T487
Test name
Test status
Simulation time 77394792 ps
CPU time 1.32 seconds
Started Jul 16 04:53:32 PM PDT 24
Finished Jul 16 04:53:34 PM PDT 24
Peak memory 196888 kb
Host smart-e8bca5e6-b30b-40df-bba1-2cd828ef4da8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342870115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.1342870115
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1238390130
Short name T34
Test name
Test status
Simulation time 160972180 ps
CPU time 1.09 seconds
Started Jul 16 04:53:38 PM PDT 24
Finished Jul 16 04:53:42 PM PDT 24
Peak memory 182644 kb
Host smart-d1f7e76e-1031-4502-882e-d1b636ad37f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238390130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1238390130
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.339978819
Short name T445
Test name
Test status
Simulation time 67471950049 ps
CPU time 117.31 seconds
Started Jul 16 04:40:14 PM PDT 24
Finished Jul 16 04:42:13 PM PDT 24
Peak memory 182696 kb
Host smart-64180d8f-214d-489b-a381-435ab3393262
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339978819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.rv_timer_cfg_update_on_fly.339978819
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.900600408
Short name T454
Test name
Test status
Simulation time 48905613908 ps
CPU time 64.69 seconds
Started Jul 16 04:38:49 PM PDT 24
Finished Jul 16 04:39:54 PM PDT 24
Peak memory 182980 kb
Host smart-aaf9dc1b-b6a3-49af-9d88-4829366af8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900600408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.900600408
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.2433581328
Short name T362
Test name
Test status
Simulation time 259423379051 ps
CPU time 66.9 seconds
Started Jul 16 04:40:14 PM PDT 24
Finished Jul 16 04:41:22 PM PDT 24
Peak memory 182580 kb
Host smart-1abd70bb-6fec-4cf3-a98e-9976f33876f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433581328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.2433581328
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all_with_rand_reset.694554681
Short name T109
Test name
Test status
Simulation time 182968741816 ps
CPU time 467.6 seconds
Started Jul 16 04:37:08 PM PDT 24
Finished Jul 16 04:44:56 PM PDT 24
Peak memory 206192 kb
Host smart-7d852c31-5e57-4fbc-8d59-ebd6fbf81a3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694554681 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all_with_rand_reset.694554681
Directory /workspace/0.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.2444779049
Short name T339
Test name
Test status
Simulation time 247294955804 ps
CPU time 236.93 seconds
Started Jul 16 04:35:24 PM PDT 24
Finished Jul 16 04:39:22 PM PDT 24
Peak memory 182864 kb
Host smart-c1891794-9d10-4fd7-9ee0-6517addeee1b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444779049 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.2444779049
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.1808277657
Short name T376
Test name
Test status
Simulation time 334273754985 ps
CPU time 129.43 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:42:18 PM PDT 24
Peak memory 182692 kb
Host smart-6ebc83df-d75b-4965-8078-08537f91b103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808277657 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.1808277657
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.2352711069
Short name T206
Test name
Test status
Simulation time 794951105195 ps
CPU time 1835.5 seconds
Started Jul 16 04:37:03 PM PDT 24
Finished Jul 16 05:07:40 PM PDT 24
Peak memory 191152 kb
Host smart-5c318b07-c269-405b-a027-f7f016524cf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352711069 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.2352711069
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_random_reset.3337061411
Short name T379
Test name
Test status
Simulation time 44294185 ps
CPU time 0.57 seconds
Started Jul 16 04:35:31 PM PDT 24
Finished Jul 16 04:35:32 PM PDT 24
Peak memory 182796 kb
Host smart-4c31a5f7-a650-4333-b10f-bddfe13d3d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337061411 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random_reset.3337061411
Directory /workspace/1.rv_timer_random_reset/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.4178145149
Short name T22
Test name
Test status
Simulation time 60939085 ps
CPU time 0.8 seconds
Started Jul 16 04:41:05 PM PDT 24
Finished Jul 16 04:41:07 PM PDT 24
Peak memory 213148 kb
Host smart-8250c73a-2054-444d-af24-c2b3b8ab8bb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178145149 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.4178145149
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.2986968991
Short name T292
Test name
Test status
Simulation time 1079966288625 ps
CPU time 564.29 seconds
Started Jul 16 04:35:43 PM PDT 24
Finished Jul 16 04:45:08 PM PDT 24
Peak memory 182884 kb
Host smart-1a9d2474-c67f-4665-8965-f411b042b218
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986968991 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.rv_timer_cfg_update_on_fly.2986968991
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.1420653067
Short name T401
Test name
Test status
Simulation time 146704416308 ps
CPU time 195.52 seconds
Started Jul 16 04:36:40 PM PDT 24
Finished Jul 16 04:39:56 PM PDT 24
Peak memory 182932 kb
Host smart-e75e33f7-9f41-4f25-b5c3-a2b74271ae82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420653067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.1420653067
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.1851197413
Short name T216
Test name
Test status
Simulation time 71590308356 ps
CPU time 103.32 seconds
Started Jul 16 04:40:00 PM PDT 24
Finished Jul 16 04:41:44 PM PDT 24
Peak memory 190624 kb
Host smart-36e68b08-cdf2-403a-8240-2e712a1c2164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851197413 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.1851197413
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.3946329100
Short name T322
Test name
Test status
Simulation time 124010263796 ps
CPU time 185.63 seconds
Started Jul 16 04:36:39 PM PDT 24
Finished Jul 16 04:39:46 PM PDT 24
Peak memory 191156 kb
Host smart-fd18bd7b-4fba-4797-a6d8-9548fd43e499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946329100 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.3946329100
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.2657762216
Short name T432
Test name
Test status
Simulation time 292175074296 ps
CPU time 371.86 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 04:46:29 PM PDT 24
Peak memory 190856 kb
Host smart-1b5f264b-4271-40ba-996b-bdae739153df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657762216 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all
.2657762216
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/101.rv_timer_random.3737511408
Short name T133
Test name
Test status
Simulation time 147142196246 ps
CPU time 130.88 seconds
Started Jul 16 04:39:51 PM PDT 24
Finished Jul 16 04:42:03 PM PDT 24
Peak memory 189472 kb
Host smart-27d4e5d8-f97e-413c-a47a-70fecab0df54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737511408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.3737511408
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.2497874415
Short name T254
Test name
Test status
Simulation time 714610411233 ps
CPU time 245.75 seconds
Started Jul 16 04:39:37 PM PDT 24
Finished Jul 16 04:43:44 PM PDT 24
Peak memory 188816 kb
Host smart-008b686c-35e3-44bb-9550-12d2943b5286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497874415 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.2497874415
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.2219481641
Short name T272
Test name
Test status
Simulation time 363439100480 ps
CPU time 1759.57 seconds
Started Jul 16 04:40:03 PM PDT 24
Finished Jul 16 05:09:24 PM PDT 24
Peak memory 190408 kb
Host smart-4f9d3e72-f050-4ea7-80e9-595efb6ef44f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219481641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.2219481641
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.2058048003
Short name T236
Test name
Test status
Simulation time 596099281098 ps
CPU time 491.1 seconds
Started Jul 16 04:39:37 PM PDT 24
Finished Jul 16 04:47:49 PM PDT 24
Peak memory 188744 kb
Host smart-c0906ee2-c1f4-4973-b07c-a47170bf9c62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058048003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.2058048003
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.1937014659
Short name T323
Test name
Test status
Simulation time 80317136141 ps
CPU time 1645.93 seconds
Started Jul 16 04:40:01 PM PDT 24
Finished Jul 16 05:07:28 PM PDT 24
Peak memory 194076 kb
Host smart-429c11d9-1e2b-48fb-9cb0-74adab4a4739
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937014659 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.1937014659
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2431053797
Short name T297
Test name
Test status
Simulation time 74611650632 ps
CPU time 62.29 seconds
Started Jul 16 04:39:48 PM PDT 24
Finished Jul 16 04:40:50 PM PDT 24
Peak memory 182552 kb
Host smart-72397ce9-6a71-434a-8d76-87e21ab8242b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431053797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2431053797
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.4121846985
Short name T447
Test name
Test status
Simulation time 54191959303 ps
CPU time 487.05 seconds
Started Jul 16 04:40:05 PM PDT 24
Finished Jul 16 04:48:13 PM PDT 24
Peak memory 190820 kb
Host smart-5ab05fda-8b33-453c-b938-76161ecf64c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121846985 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.4121846985
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.2174240563
Short name T264
Test name
Test status
Simulation time 690777121194 ps
CPU time 358.14 seconds
Started Jul 16 04:40:10 PM PDT 24
Finished Jul 16 04:46:09 PM PDT 24
Peak memory 182572 kb
Host smart-8b783a8f-aab6-4646-b025-32f0b6dd4251
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174240563 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.rv_timer_cfg_update_on_fly.2174240563
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.3582239964
Short name T431
Test name
Test status
Simulation time 59628707875 ps
CPU time 95.02 seconds
Started Jul 16 04:40:19 PM PDT 24
Finished Jul 16 04:41:55 PM PDT 24
Peak memory 181776 kb
Host smart-9278bea0-8686-464c-8c87-eeeb4a0ef056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582239964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.3582239964
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random.2441646054
Short name T235
Test name
Test status
Simulation time 211322059771 ps
CPU time 221.68 seconds
Started Jul 16 04:40:15 PM PDT 24
Finished Jul 16 04:43:58 PM PDT 24
Peak memory 190848 kb
Host smart-04fbbb42-2cea-4847-92cc-227e83190296
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441646054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.2441646054
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.1840565255
Short name T384
Test name
Test status
Simulation time 43053436 ps
CPU time 0.72 seconds
Started Jul 16 04:36:42 PM PDT 24
Finished Jul 16 04:36:43 PM PDT 24
Peak memory 182788 kb
Host smart-f907aeed-54a1-451f-86cf-55c69e07a328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840565255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.1840565255
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/111.rv_timer_random.2228657899
Short name T53
Test name
Test status
Simulation time 205582189495 ps
CPU time 988.56 seconds
Started Jul 16 04:40:13 PM PDT 24
Finished Jul 16 04:56:43 PM PDT 24
Peak memory 182624 kb
Host smart-3a8be411-2945-4cd7-aec3-f36354efef16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228657899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.2228657899
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.2102291484
Short name T247
Test name
Test status
Simulation time 598736403280 ps
CPU time 316.95 seconds
Started Jul 16 04:40:13 PM PDT 24
Finished Jul 16 04:45:32 PM PDT 24
Peak memory 190672 kb
Host smart-466f27c3-3a9b-4541-bd84-dafa97ec828f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102291484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.2102291484
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.3851536812
Short name T182
Test name
Test status
Simulation time 566859331596 ps
CPU time 263.82 seconds
Started Jul 16 04:40:23 PM PDT 24
Finished Jul 16 04:44:48 PM PDT 24
Peak memory 190316 kb
Host smart-95982236-d941-4440-897c-143a872525f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851536812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.3851536812
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.4008920172
Short name T191
Test name
Test status
Simulation time 169872380866 ps
CPU time 145.98 seconds
Started Jul 16 04:37:09 PM PDT 24
Finished Jul 16 04:39:35 PM PDT 24
Peak memory 191152 kb
Host smart-c2cbd12d-84a4-4b3b-be05-691a5371f725
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008920172 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.4008920172
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.3985196706
Short name T158
Test name
Test status
Simulation time 206436768350 ps
CPU time 200.45 seconds
Started Jul 16 04:40:24 PM PDT 24
Finished Jul 16 04:43:45 PM PDT 24
Peak memory 190776 kb
Host smart-99a9f686-f629-4755-8e01-4f76c7959ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985196706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.3985196706
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.1650327426
Short name T293
Test name
Test status
Simulation time 160040344652 ps
CPU time 241.39 seconds
Started Jul 16 04:39:48 PM PDT 24
Finished Jul 16 04:43:50 PM PDT 24
Peak memory 182604 kb
Host smart-e4447121-d29a-472a-af61-02d2d3090af3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650327426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.rv_timer_cfg_update_on_fly.1650327426
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.4095605022
Short name T414
Test name
Test status
Simulation time 347657287190 ps
CPU time 145.07 seconds
Started Jul 16 04:35:19 PM PDT 24
Finished Jul 16 04:37:44 PM PDT 24
Peak memory 182936 kb
Host smart-24cfcf13-f46a-465d-8b20-5bee6ba5b3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095605022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.4095605022
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random.3416919026
Short name T452
Test name
Test status
Simulation time 47338557984 ps
CPU time 74.16 seconds
Started Jul 16 04:36:03 PM PDT 24
Finished Jul 16 04:37:18 PM PDT 24
Peak memory 182944 kb
Host smart-5e26163e-3b20-4336-aa8d-d367c3cc23aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416919026 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.3416919026
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.3554171161
Short name T381
Test name
Test status
Simulation time 938229621 ps
CPU time 1.98 seconds
Started Jul 16 04:37:06 PM PDT 24
Finished Jul 16 04:37:08 PM PDT 24
Peak memory 191404 kb
Host smart-b8733b10-4da1-4704-8092-140640dbf514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554171161 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.3554171161
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/120.rv_timer_random.1367231055
Short name T15
Test name
Test status
Simulation time 14706735133 ps
CPU time 6.12 seconds
Started Jul 16 04:37:39 PM PDT 24
Finished Jul 16 04:37:46 PM PDT 24
Peak memory 182828 kb
Host smart-f82e0eea-03db-4f0b-9ca4-4e21e1b9b945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367231055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.1367231055
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.131871564
Short name T213
Test name
Test status
Simulation time 303300310145 ps
CPU time 345.58 seconds
Started Jul 16 04:38:30 PM PDT 24
Finished Jul 16 04:44:16 PM PDT 24
Peak memory 191100 kb
Host smart-56beaf91-4fd3-476c-b276-ac97d9b6297d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131871564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.131871564
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.4250142344
Short name T149
Test name
Test status
Simulation time 39238077327 ps
CPU time 29.35 seconds
Started Jul 16 04:40:01 PM PDT 24
Finished Jul 16 04:40:32 PM PDT 24
Peak memory 182180 kb
Host smart-6bed7320-000e-4700-9313-e356db04a859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250142344 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.4250142344
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.1261096646
Short name T343
Test name
Test status
Simulation time 23829383106 ps
CPU time 38.02 seconds
Started Jul 16 04:37:09 PM PDT 24
Finished Jul 16 04:37:47 PM PDT 24
Peak memory 183284 kb
Host smart-83189f74-f47a-4c02-8e68-430a6f2f1be2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261096646 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.1261096646
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.3022671973
Short name T310
Test name
Test status
Simulation time 126496130340 ps
CPU time 59.04 seconds
Started Jul 16 04:40:05 PM PDT 24
Finished Jul 16 04:41:05 PM PDT 24
Peak memory 190872 kb
Host smart-9f2ae46f-df6f-4148-b71b-5b04c7503275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022671973 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.3022671973
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.1817098404
Short name T289
Test name
Test status
Simulation time 359959663416 ps
CPU time 210.62 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 04:43:48 PM PDT 24
Peak memory 190848 kb
Host smart-693f436b-d6b3-4cd9-a723-21c3680690af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817098404 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.1817098404
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.2276412872
Short name T238
Test name
Test status
Simulation time 553232559286 ps
CPU time 273.17 seconds
Started Jul 16 04:36:25 PM PDT 24
Finished Jul 16 04:40:58 PM PDT 24
Peak memory 182896 kb
Host smart-eb7b2fde-01d0-4145-8159-84b89033beb0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276412872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.rv_timer_cfg_update_on_fly.2276412872
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.194493218
Short name T450
Test name
Test status
Simulation time 224367454499 ps
CPU time 169.13 seconds
Started Jul 16 04:40:22 PM PDT 24
Finished Jul 16 04:43:12 PM PDT 24
Peak memory 182588 kb
Host smart-3b7299ce-f6fe-454e-a67e-eb0a93f05cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194493218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.194493218
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.249879848
Short name T13
Test name
Test status
Simulation time 13418988262 ps
CPU time 10.82 seconds
Started Jul 16 04:40:21 PM PDT 24
Finished Jul 16 04:40:33 PM PDT 24
Peak memory 189072 kb
Host smart-286fa427-0150-44dc-b2b1-c0866edb7b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249879848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.249879848
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all_with_rand_reset.2342829533
Short name T46
Test name
Test status
Simulation time 88359508070 ps
CPU time 184.09 seconds
Started Jul 16 04:36:51 PM PDT 24
Finished Jul 16 04:39:56 PM PDT 24
Peak memory 205864 kb
Host smart-c211b535-a902-4d22-b2d6-6d061fa8f8f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342829533 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all_with_rand_reset.2342829533
Directory /workspace/13.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/131.rv_timer_random.509139751
Short name T28
Test name
Test status
Simulation time 688897469613 ps
CPU time 617.83 seconds
Started Jul 16 04:40:04 PM PDT 24
Finished Jul 16 04:50:23 PM PDT 24
Peak memory 190864 kb
Host smart-1ead7cc6-5345-42e6-957b-402476d17775
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509139751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.509139751
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.7021812
Short name T435
Test name
Test status
Simulation time 488850096768 ps
CPU time 396.92 seconds
Started Jul 16 04:40:05 PM PDT 24
Finished Jul 16 04:46:43 PM PDT 24
Peak memory 190860 kb
Host smart-94b8aba7-64d4-4c4e-b002-165eb7d1c574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7021812 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.7021812
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3192681498
Short name T153
Test name
Test status
Simulation time 87825725622 ps
CPU time 230.11 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 04:44:08 PM PDT 24
Peak memory 190372 kb
Host smart-f7530238-b29b-4af6-8dfc-cbf7ce8b0eca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192681498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3192681498
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2257978075
Short name T36
Test name
Test status
Simulation time 219641671715 ps
CPU time 244.58 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 04:44:22 PM PDT 24
Peak memory 190848 kb
Host smart-f07a6895-9eda-4a31-b035-a786b9228e43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257978075 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2257978075
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.4273898899
Short name T132
Test name
Test status
Simulation time 334392246532 ps
CPU time 338.74 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 04:45:56 PM PDT 24
Peak memory 189676 kb
Host smart-1fb08586-af64-4fa8-860e-174523f29045
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273898899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.4273898899
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.1841658457
Short name T344
Test name
Test status
Simulation time 126675614632 ps
CPU time 256.14 seconds
Started Jul 16 04:37:24 PM PDT 24
Finished Jul 16 04:41:41 PM PDT 24
Peak memory 191016 kb
Host smart-907b4379-bc7e-4fbb-9858-1566df58dc97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841658457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.1841658457
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.599685800
Short name T279
Test name
Test status
Simulation time 152799971753 ps
CPU time 1343.73 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 05:02:41 PM PDT 24
Peak memory 188776 kb
Host smart-1e93d9e4-5df4-4122-b1f8-31fa9e80f478
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599685800 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.599685800
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.2055706484
Short name T300
Test name
Test status
Simulation time 1059588311760 ps
CPU time 1836.57 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 05:10:46 PM PDT 24
Peak memory 181436 kb
Host smart-776ed630-071b-4afa-b482-47add98882da
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055706484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.2055706484
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.4059439754
Short name T368
Test name
Test status
Simulation time 5689175866 ps
CPU time 9.03 seconds
Started Jul 16 04:39:49 PM PDT 24
Finished Jul 16 04:39:58 PM PDT 24
Peak memory 182112 kb
Host smart-356be429-ddc0-402e-b06a-294057241264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059439754 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.4059439754
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random.1626267607
Short name T308
Test name
Test status
Simulation time 43744119265 ps
CPU time 496.98 seconds
Started Jul 16 04:40:36 PM PDT 24
Finished Jul 16 04:48:54 PM PDT 24
Peak memory 182052 kb
Host smart-5195de84-0e0d-46e3-8305-1390dc2463e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626267607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1626267607
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.3525279142
Short name T434
Test name
Test status
Simulation time 7580140156 ps
CPU time 10.06 seconds
Started Jul 16 04:36:18 PM PDT 24
Finished Jul 16 04:36:29 PM PDT 24
Peak memory 183288 kb
Host smart-b57d0f69-92b0-44dc-ade9-d1219e431ce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525279142 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.3525279142
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.880435457
Short name T243
Test name
Test status
Simulation time 1226570121251 ps
CPU time 417.9 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 04:47:15 PM PDT 24
Peak memory 194380 kb
Host smart-004c9b8e-71e9-4bde-ae09-422facaf667f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880435457 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
880435457
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all_with_rand_reset.3861834925
Short name T55
Test name
Test status
Simulation time 147140432771 ps
CPU time 1067.09 seconds
Started Jul 16 04:40:02 PM PDT 24
Finished Jul 16 04:57:50 PM PDT 24
Peak memory 211156 kb
Host smart-7aedf34c-4e38-4647-a78b-99c90a71d936
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861834925 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all_with_rand_reset.3861834925
Directory /workspace/14.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1909648752
Short name T83
Test name
Test status
Simulation time 116510666672 ps
CPU time 61.07 seconds
Started Jul 16 04:37:48 PM PDT 24
Finished Jul 16 04:38:49 PM PDT 24
Peak memory 182916 kb
Host smart-a6ca7eaf-1434-49f8-8154-5bf6f3090b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909648752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1909648752
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.2530240023
Short name T207
Test name
Test status
Simulation time 699921933451 ps
CPU time 207.27 seconds
Started Jul 16 04:40:05 PM PDT 24
Finished Jul 16 04:43:33 PM PDT 24
Peak memory 190872 kb
Host smart-8ffafefd-916e-403e-995b-bb0aaea66441
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530240023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.2530240023
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.3943464308
Short name T427
Test name
Test status
Simulation time 289672826162 ps
CPU time 1895.17 seconds
Started Jul 16 04:40:14 PM PDT 24
Finished Jul 16 05:11:52 PM PDT 24
Peak memory 190808 kb
Host smart-192f07d0-fb54-4d14-8e70-535f24a420db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943464308 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.3943464308
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.1772519223
Short name T286
Test name
Test status
Simulation time 705802685837 ps
CPU time 403.42 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 04:47:01 PM PDT 24
Peak memory 188948 kb
Host smart-2e22f1f2-eb5e-40d4-9e36-a30578efceee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772519223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.1772519223
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/146.rv_timer_random.3752844352
Short name T63
Test name
Test status
Simulation time 83157515486 ps
CPU time 151.58 seconds
Started Jul 16 04:39:48 PM PDT 24
Finished Jul 16 04:42:21 PM PDT 24
Peak memory 182048 kb
Host smart-a5eaddf6-2bcb-4c67-9ac6-f37d489ae311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752844352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.3752844352
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.1937623031
Short name T399
Test name
Test status
Simulation time 265301709312 ps
CPU time 114.3 seconds
Started Jul 16 04:40:17 PM PDT 24
Finished Jul 16 04:42:12 PM PDT 24
Peak memory 182600 kb
Host smart-6e384594-783a-4981-9d37-3dd14b36d223
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937623031 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.1937623031
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.3980193998
Short name T360
Test name
Test status
Simulation time 232830943184 ps
CPU time 646.6 seconds
Started Jul 16 04:40:08 PM PDT 24
Finished Jul 16 04:50:57 PM PDT 24
Peak memory 190852 kb
Host smart-6f222881-054c-4906-8ae1-e1cdd8c522c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980193998 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.3980193998
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.593573623
Short name T437
Test name
Test status
Simulation time 88290719426 ps
CPU time 38.34 seconds
Started Jul 16 04:40:08 PM PDT 24
Finished Jul 16 04:40:48 PM PDT 24
Peak memory 182652 kb
Host smart-42b57c90-0c1c-43ba-98c4-e8e66fd55f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593573623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.593573623
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random.3220653020
Short name T355
Test name
Test status
Simulation time 122039987056 ps
CPU time 112.53 seconds
Started Jul 16 04:37:46 PM PDT 24
Finished Jul 16 04:39:39 PM PDT 24
Peak memory 194568 kb
Host smart-1909db11-8142-40a7-9d32-97d36db16752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220653020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.3220653020
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.534642159
Short name T152
Test name
Test status
Simulation time 181867480872 ps
CPU time 582.41 seconds
Started Jul 16 04:40:08 PM PDT 24
Finished Jul 16 04:49:52 PM PDT 24
Peak memory 190780 kb
Host smart-859940b0-f6c0-4f3a-9420-d671138919fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534642159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all.
534642159
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.1484823782
Short name T440
Test name
Test status
Simulation time 343886613115 ps
CPU time 773.68 seconds
Started Jul 16 04:40:15 PM PDT 24
Finished Jul 16 04:53:11 PM PDT 24
Peak memory 206900 kb
Host smart-3afe12b9-2e2f-462c-93e6-c1d6896a40b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484823782 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.1484823782
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.1958347958
Short name T295
Test name
Test status
Simulation time 619021853167 ps
CPU time 1082.12 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 04:58:09 PM PDT 24
Peak memory 190872 kb
Host smart-77bc5ac1-9624-479a-bacc-2ab42577ed85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958347958 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1958347958
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.30843496
Short name T3
Test name
Test status
Simulation time 47892625267 ps
CPU time 24.38 seconds
Started Jul 16 04:40:21 PM PDT 24
Finished Jul 16 04:40:46 PM PDT 24
Peak memory 182608 kb
Host smart-ed688042-c189-4282-b17c-11ac11fd2aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30843496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.30843496
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.2452835561
Short name T81
Test name
Test status
Simulation time 217942676287 ps
CPU time 275.3 seconds
Started Jul 16 04:37:34 PM PDT 24
Finished Jul 16 04:42:09 PM PDT 24
Peak memory 193204 kb
Host smart-7db48197-2089-4f81-9d0c-00d9454c757f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452835561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.2452835561
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.2374422736
Short name T166
Test name
Test status
Simulation time 74963003588 ps
CPU time 856.5 seconds
Started Jul 16 04:40:11 PM PDT 24
Finished Jul 16 04:54:29 PM PDT 24
Peak memory 194048 kb
Host smart-ab8c5e9d-51b1-4f6f-851c-931cd2abab7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374422736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.2374422736
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/154.rv_timer_random.3405521126
Short name T347
Test name
Test status
Simulation time 230719488986 ps
CPU time 528.66 seconds
Started Jul 16 04:40:16 PM PDT 24
Finished Jul 16 04:49:07 PM PDT 24
Peak memory 190804 kb
Host smart-7450f7e9-bc8e-40fd-89a8-ae4436f83f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405521126 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.3405521126
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3996059381
Short name T253
Test name
Test status
Simulation time 241940869011 ps
CPU time 524.97 seconds
Started Jul 16 04:40:21 PM PDT 24
Finished Jul 16 04:49:06 PM PDT 24
Peak memory 190812 kb
Host smart-0c6679a3-5af4-4710-9c39-ef2b063540c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996059381 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3996059381
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.614802884
Short name T128
Test name
Test status
Simulation time 266642651625 ps
CPU time 113.85 seconds
Started Jul 16 04:40:08 PM PDT 24
Finished Jul 16 04:42:04 PM PDT 24
Peak memory 190880 kb
Host smart-92c7d000-2c02-4b29-9466-8d336aab8b53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614802884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.614802884
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/157.rv_timer_random.2816705240
Short name T309
Test name
Test status
Simulation time 141660589017 ps
CPU time 80.61 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 04:41:27 PM PDT 24
Peak memory 182664 kb
Host smart-2ee01dff-b7c0-4200-9578-e22d3cde846b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816705240 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.2816705240
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.3275788311
Short name T426
Test name
Test status
Simulation time 234383449848 ps
CPU time 91.09 seconds
Started Jul 16 04:40:20 PM PDT 24
Finished Jul 16 04:41:52 PM PDT 24
Peak memory 191532 kb
Host smart-3e74a045-3c5a-4abb-938e-fb901097359c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275788311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.3275788311
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.1529400864
Short name T256
Test name
Test status
Simulation time 12486408412 ps
CPU time 20.22 seconds
Started Jul 16 04:35:31 PM PDT 24
Finished Jul 16 04:35:52 PM PDT 24
Peak memory 182920 kb
Host smart-f52bf196-1e11-4502-b4b5-6451eda67b64
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529400864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.rv_timer_cfg_update_on_fly.1529400864
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.3390919543
Short name T69
Test name
Test status
Simulation time 47530575201 ps
CPU time 61.89 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:41:11 PM PDT 24
Peak memory 182680 kb
Host smart-c2f073f5-a4fe-4858-949e-de652a2497d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390919543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.3390919543
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.3421870653
Short name T263
Test name
Test status
Simulation time 228783662098 ps
CPU time 1092.91 seconds
Started Jul 16 04:39:58 PM PDT 24
Finished Jul 16 04:58:12 PM PDT 24
Peak memory 190412 kb
Host smart-10b65708-72a1-4832-92ac-7b436b594590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421870653 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.3421870653
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3150328400
Short name T412
Test name
Test status
Simulation time 1668643271 ps
CPU time 1.16 seconds
Started Jul 16 04:40:19 PM PDT 24
Finished Jul 16 04:40:21 PM PDT 24
Peak memory 182652 kb
Host smart-23793953-da99-4d8a-90cd-53947e9c5d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150328400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3150328400
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all_with_rand_reset.2039325354
Short name T56
Test name
Test status
Simulation time 108831549589 ps
CPU time 210.4 seconds
Started Jul 16 04:36:21 PM PDT 24
Finished Jul 16 04:39:52 PM PDT 24
Peak memory 205864 kb
Host smart-c98213d7-07cd-4385-8dee-90b8b2fdd4f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039325354 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all_with_rand_reset.2039325354
Directory /workspace/16.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/160.rv_timer_random.488919857
Short name T314
Test name
Test status
Simulation time 784406108757 ps
CPU time 1611.17 seconds
Started Jul 16 04:37:45 PM PDT 24
Finished Jul 16 05:04:37 PM PDT 24
Peak memory 191052 kb
Host smart-2c4ea122-ec20-4d0c-857c-5dff14ecb835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488919857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.488919857
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/162.rv_timer_random.55696471
Short name T262
Test name
Test status
Simulation time 295748636286 ps
CPU time 373.72 seconds
Started Jul 16 04:38:27 PM PDT 24
Finished Jul 16 04:44:41 PM PDT 24
Peak memory 191116 kb
Host smart-9e49e07a-b136-423a-9f66-c1976897a59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55696471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.55696471
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4105806865
Short name T260
Test name
Test status
Simulation time 9815499866 ps
CPU time 9.92 seconds
Started Jul 16 04:40:08 PM PDT 24
Finished Jul 16 04:40:20 PM PDT 24
Peak memory 181748 kb
Host smart-2469793b-9128-43b8-8613-b5053998b7bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105806865 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4105806865
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.2407558690
Short name T248
Test name
Test status
Simulation time 2869465677407 ps
CPU time 776.75 seconds
Started Jul 16 04:38:00 PM PDT 24
Finished Jul 16 04:50:58 PM PDT 24
Peak memory 191260 kb
Host smart-48613473-3373-4363-9f35-97efb99df3e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407558690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.2407558690
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.2913001148
Short name T135
Test name
Test status
Simulation time 98235514805 ps
CPU time 91.87 seconds
Started Jul 16 04:40:17 PM PDT 24
Finished Jul 16 04:41:50 PM PDT 24
Peak memory 190800 kb
Host smart-7a6cf9d3-cef4-469d-bcb6-80d96dc2225f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913001148 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.2913001148
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.2245895249
Short name T407
Test name
Test status
Simulation time 2272373360 ps
CPU time 4.36 seconds
Started Jul 16 04:40:18 PM PDT 24
Finished Jul 16 04:40:23 PM PDT 24
Peak memory 182512 kb
Host smart-d65215b1-925b-4a89-9269-f0320da062f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245895249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.2245895249
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.4098479825
Short name T413
Test name
Test status
Simulation time 183205520668 ps
CPU time 1695.2 seconds
Started Jul 16 04:37:45 PM PDT 24
Finished Jul 16 05:06:01 PM PDT 24
Peak memory 191156 kb
Host smart-3fd70c5c-b763-4234-bf41-a182d9adb45c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098479825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.4098479825
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.1929972866
Short name T320
Test name
Test status
Simulation time 298218654038 ps
CPU time 519.23 seconds
Started Jul 16 04:36:33 PM PDT 24
Finished Jul 16 04:45:12 PM PDT 24
Peak memory 182884 kb
Host smart-f483748f-f334-4076-b77b-cf3b8246fefe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929972866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.rv_timer_cfg_update_on_fly.1929972866
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.408559562
Short name T378
Test name
Test status
Simulation time 461297935712 ps
CPU time 297.08 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 04:45:10 PM PDT 24
Peak memory 182612 kb
Host smart-6378612a-e164-46c8-afac-03097d7096e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408559562 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.408559562
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random.2080495615
Short name T364
Test name
Test status
Simulation time 68662639613 ps
CPU time 129.38 seconds
Started Jul 16 04:38:49 PM PDT 24
Finished Jul 16 04:40:59 PM PDT 24
Peak memory 182956 kb
Host smart-529088e2-c762-41f7-a749-d26b0ed3bab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080495615 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.2080495615
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.4288886966
Short name T312
Test name
Test status
Simulation time 11935017739 ps
CPU time 24.18 seconds
Started Jul 16 04:40:03 PM PDT 24
Finished Jul 16 04:40:29 PM PDT 24
Peak memory 190876 kb
Host smart-90126b37-7915-4b01-be21-039e84bae171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288886966 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.4288886966
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.2356575753
Short name T460
Test name
Test status
Simulation time 308774703032 ps
CPU time 120.37 seconds
Started Jul 16 04:40:11 PM PDT 24
Finished Jul 16 04:42:12 PM PDT 24
Peak memory 182764 kb
Host smart-ff77e40d-8edd-4e95-93db-d1391ab8a696
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356575753 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.2356575753
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/170.rv_timer_random.3272512451
Short name T222
Test name
Test status
Simulation time 565752437613 ps
CPU time 2961.07 seconds
Started Jul 16 04:40:17 PM PDT 24
Finished Jul 16 05:29:39 PM PDT 24
Peak memory 190792 kb
Host smart-2a683690-dfa5-46b1-829c-2180d15969bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272512451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.3272512451
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.4208042306
Short name T296
Test name
Test status
Simulation time 501536193163 ps
CPU time 294.26 seconds
Started Jul 16 04:39:56 PM PDT 24
Finished Jul 16 04:44:51 PM PDT 24
Peak memory 192504 kb
Host smart-847d5d47-64a8-4b99-9072-5ff5f698c137
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208042306 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.4208042306
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/172.rv_timer_random.3901969504
Short name T225
Test name
Test status
Simulation time 169294361904 ps
CPU time 342.92 seconds
Started Jul 16 04:37:45 PM PDT 24
Finished Jul 16 04:43:28 PM PDT 24
Peak memory 191484 kb
Host smart-b41a76b8-2ef0-4432-a6fc-4a11f0648c2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901969504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3901969504
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.228754630
Short name T85
Test name
Test status
Simulation time 136059402328 ps
CPU time 1163.38 seconds
Started Jul 16 04:37:47 PM PDT 24
Finished Jul 16 04:57:11 PM PDT 24
Peak memory 191128 kb
Host smart-5b53405b-b302-43fc-a940-afb2b2866d26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228754630 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.228754630
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2962616206
Short name T458
Test name
Test status
Simulation time 20512333209 ps
CPU time 27.9 seconds
Started Jul 16 04:39:58 PM PDT 24
Finished Jul 16 04:40:26 PM PDT 24
Peak memory 190772 kb
Host smart-e12286b4-2921-43cc-8b06-3833da7e6fbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962616206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2962616206
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.3656995372
Short name T125
Test name
Test status
Simulation time 112070165099 ps
CPU time 199.37 seconds
Started Jul 16 04:37:41 PM PDT 24
Finished Jul 16 04:41:01 PM PDT 24
Peak memory 191436 kb
Host smart-f938b0f2-11df-47a7-9cbe-6d7eca29e21a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656995372 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.3656995372
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.3851771568
Short name T283
Test name
Test status
Simulation time 306153576100 ps
CPU time 354.32 seconds
Started Jul 16 04:37:49 PM PDT 24
Finished Jul 16 04:43:44 PM PDT 24
Peak memory 191192 kb
Host smart-cad63dc3-f0e6-48d2-a021-5687489a7815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851771568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.3851771568
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.2896068693
Short name T211
Test name
Test status
Simulation time 66387894039 ps
CPU time 104.91 seconds
Started Jul 16 04:40:08 PM PDT 24
Finished Jul 16 04:41:55 PM PDT 24
Peak memory 190040 kb
Host smart-7ed42c88-b7fc-4486-950f-6d954c242b5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896068693 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.2896068693
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1198730179
Short name T189
Test name
Test status
Simulation time 234530916329 ps
CPU time 664.32 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 04:51:18 PM PDT 24
Peak memory 190828 kb
Host smart-b4b894ab-a2a7-40d4-85a7-0a23da33f705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198730179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1198730179
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3398745700
Short name T403
Test name
Test status
Simulation time 123584269028 ps
CPU time 169.84 seconds
Started Jul 16 04:35:40 PM PDT 24
Finished Jul 16 04:38:30 PM PDT 24
Peak memory 182836 kb
Host smart-6314ad9d-52aa-4e78-be0a-8f26b84de9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398745700 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3398745700
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.43182596
Short name T408
Test name
Test status
Simulation time 63685237181 ps
CPU time 163.61 seconds
Started Jul 16 04:40:04 PM PDT 24
Finished Jul 16 04:42:49 PM PDT 24
Peak memory 190864 kb
Host smart-9b867a2b-7ec3-41ef-846e-182e80064868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43182596 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.43182596
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.453306208
Short name T80
Test name
Test status
Simulation time 14232570258 ps
CPU time 19.19 seconds
Started Jul 16 04:40:40 PM PDT 24
Finished Jul 16 04:41:00 PM PDT 24
Peak memory 181336 kb
Host smart-15449b7f-3382-4239-8036-71751bade9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453306208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.453306208
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/181.rv_timer_random.2894432500
Short name T233
Test name
Test status
Simulation time 36957480106 ps
CPU time 204.03 seconds
Started Jul 16 04:40:14 PM PDT 24
Finished Jul 16 04:43:40 PM PDT 24
Peak memory 193584 kb
Host smart-ea4c095d-19a8-4fe8-a70d-560af12636d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894432500 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2894432500
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.721486165
Short name T354
Test name
Test status
Simulation time 141822024629 ps
CPU time 72.33 seconds
Started Jul 16 04:40:17 PM PDT 24
Finished Jul 16 04:41:31 PM PDT 24
Peak memory 190408 kb
Host smart-69a90f1e-56fc-4451-9871-e7535b4d08cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721486165 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.721486165
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.2239139000
Short name T324
Test name
Test status
Simulation time 213469601580 ps
CPU time 113.66 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 04:42:07 PM PDT 24
Peak memory 194520 kb
Host smart-1d43c54f-d36b-4b2f-9da4-4211e7a777c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239139000 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.2239139000
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.1198213205
Short name T201
Test name
Test status
Simulation time 608237387494 ps
CPU time 233.34 seconds
Started Jul 16 04:37:54 PM PDT 24
Finished Jul 16 04:41:48 PM PDT 24
Peak memory 191156 kb
Host smart-29bcc4c7-8b58-4ef0-8037-f6429910de2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198213205 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.1198213205
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.1950182312
Short name T160
Test name
Test status
Simulation time 461670329812 ps
CPU time 424.08 seconds
Started Jul 16 04:40:03 PM PDT 24
Finished Jul 16 04:47:07 PM PDT 24
Peak memory 194144 kb
Host smart-673e5b94-6465-4c2c-ba20-d87e5da6bf7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950182312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.1950182312
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.2253523186
Short name T358
Test name
Test status
Simulation time 48231482585 ps
CPU time 106.92 seconds
Started Jul 16 04:37:58 PM PDT 24
Finished Jul 16 04:39:45 PM PDT 24
Peak memory 182960 kb
Host smart-0e241545-4fea-453a-a9e3-58a24a1e6412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253523186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.2253523186
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.3911321450
Short name T252
Test name
Test status
Simulation time 45952612425 ps
CPU time 34.92 seconds
Started Jul 16 04:40:14 PM PDT 24
Finished Jul 16 04:40:51 PM PDT 24
Peak memory 182580 kb
Host smart-c722bfa9-a840-4634-9d97-a175dcaf3de1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911321450 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.3911321450
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2569233479
Short name T123
Test name
Test status
Simulation time 5939172716 ps
CPU time 10.87 seconds
Started Jul 16 04:35:43 PM PDT 24
Finished Jul 16 04:35:55 PM PDT 24
Peak memory 182884 kb
Host smart-bc7add39-e9b9-45a4-8b6c-aeb9611359ea
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569233479 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.rv_timer_cfg_update_on_fly.2569233479
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.996718828
Short name T2
Test name
Test status
Simulation time 155847031098 ps
CPU time 122.04 seconds
Started Jul 16 04:36:32 PM PDT 24
Finished Jul 16 04:38:35 PM PDT 24
Peak memory 182816 kb
Host smart-eec10e68-f985-40c7-9622-83d2512b9980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996718828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.996718828
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.1610462250
Short name T52
Test name
Test status
Simulation time 380249872685 ps
CPU time 138.19 seconds
Started Jul 16 04:36:42 PM PDT 24
Finished Jul 16 04:39:00 PM PDT 24
Peak memory 191260 kb
Host smart-9a8e2988-0d4c-4520-bccc-033cf74348e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610462250 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.1610462250
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.272397326
Short name T404
Test name
Test status
Simulation time 1275459663 ps
CPU time 1.25 seconds
Started Jul 16 04:35:21 PM PDT 24
Finished Jul 16 04:35:23 PM PDT 24
Peak memory 192784 kb
Host smart-bab09049-9e55-4a68-93db-9d93bbcff09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272397326 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.272397326
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.220495781
Short name T383
Test name
Test status
Simulation time 148904721326 ps
CPU time 197.05 seconds
Started Jul 16 04:40:01 PM PDT 24
Finished Jul 16 04:43:20 PM PDT 24
Peak memory 192564 kb
Host smart-621e46f4-2be2-463d-b38d-427ae7122d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220495781 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all.
220495781
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/191.rv_timer_random.10709988
Short name T30
Test name
Test status
Simulation time 124322607180 ps
CPU time 328.85 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 04:45:37 PM PDT 24
Peak memory 189128 kb
Host smart-6b0a50e1-ddb8-4a63-8218-5622e8fbb2ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10709988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.10709988
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.3703666323
Short name T172
Test name
Test status
Simulation time 88856016234 ps
CPU time 183.19 seconds
Started Jul 16 04:40:26 PM PDT 24
Finished Jul 16 04:43:30 PM PDT 24
Peak memory 190368 kb
Host smart-b002b581-e744-41cb-a076-c51436ad20a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703666323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.3703666323
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.1494672028
Short name T147
Test name
Test status
Simulation time 61042815911 ps
CPU time 665.56 seconds
Started Jul 16 04:40:36 PM PDT 24
Finished Jul 16 04:51:43 PM PDT 24
Peak memory 190872 kb
Host smart-b8545974-9d17-4c88-8a39-001b697affb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494672028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.1494672028
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.3364993568
Short name T329
Test name
Test status
Simulation time 296862138411 ps
CPU time 177.87 seconds
Started Jul 16 04:37:59 PM PDT 24
Finished Jul 16 04:40:57 PM PDT 24
Peak memory 191148 kb
Host smart-8c86a73a-090a-4f4d-becd-4a164f9283a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364993568 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.3364993568
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.412022417
Short name T287
Test name
Test status
Simulation time 41954063366 ps
CPU time 34.76 seconds
Started Jul 16 04:38:13 PM PDT 24
Finished Jul 16 04:38:48 PM PDT 24
Peak memory 191488 kb
Host smart-8c9de083-b019-4430-954e-8bafeae5da57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412022417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.412022417
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1104691211
Short name T154
Test name
Test status
Simulation time 284907423868 ps
CPU time 605.44 seconds
Started Jul 16 04:38:16 PM PDT 24
Finished Jul 16 04:48:22 PM PDT 24
Peak memory 191040 kb
Host smart-c66c0129-f8b4-49fe-98fd-971ad9f52bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104691211 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1104691211
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.2340127054
Short name T335
Test name
Test status
Simulation time 51308016633 ps
CPU time 28.09 seconds
Started Jul 16 04:35:31 PM PDT 24
Finished Jul 16 04:35:59 PM PDT 24
Peak memory 183056 kb
Host smart-b7af4c61-6e99-4612-9953-742a2e57499d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340127054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.2340127054
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.3684580964
Short name T451
Test name
Test status
Simulation time 64926091500 ps
CPU time 83.52 seconds
Started Jul 16 04:40:26 PM PDT 24
Finished Jul 16 04:41:50 PM PDT 24
Peak memory 182008 kb
Host smart-03982742-0637-40de-bdba-8df826686050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684580964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.3684580964
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random.1854563532
Short name T159
Test name
Test status
Simulation time 63184731403 ps
CPU time 92.7 seconds
Started Jul 16 04:36:29 PM PDT 24
Finished Jul 16 04:38:03 PM PDT 24
Peak memory 191128 kb
Host smart-160b978b-37ba-4106-ab04-a77a711919b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854563532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.1854563532
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.863499033
Short name T342
Test name
Test status
Simulation time 203404007454 ps
CPU time 86.82 seconds
Started Jul 16 04:40:43 PM PDT 24
Finished Jul 16 04:42:11 PM PDT 24
Peak memory 182852 kb
Host smart-ca0ac010-142f-4044-ba16-5759fa50a59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863499033 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.863499033
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.2620815375
Short name T20
Test name
Test status
Simulation time 1005567939 ps
CPU time 1.01 seconds
Started Jul 16 04:40:14 PM PDT 24
Finished Jul 16 04:40:17 PM PDT 24
Peak memory 213636 kb
Host smart-3a6094df-d762-4179-956e-0a19d8a16bde
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620815375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.2620815375
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.1809519001
Short name T141
Test name
Test status
Simulation time 2512354484194 ps
CPU time 584.13 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:49:54 PM PDT 24
Peak memory 182564 kb
Host smart-8fd96335-e7d9-4976-a3d9-d3717ef74f91
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809519001 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.1809519001
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.3015600834
Short name T444
Test name
Test status
Simulation time 165371977878 ps
CPU time 39.14 seconds
Started Jul 16 04:35:26 PM PDT 24
Finished Jul 16 04:36:05 PM PDT 24
Peak memory 182908 kb
Host smart-8397dd7a-d31b-406f-94f1-557f4bd593e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015600834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.3015600834
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.3787493013
Short name T298
Test name
Test status
Simulation time 152038410575 ps
CPU time 78.24 seconds
Started Jul 16 04:34:44 PM PDT 24
Finished Jul 16 04:36:02 PM PDT 24
Peak memory 194420 kb
Host smart-761457c1-c0cb-423e-8cc6-d864df00dcd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787493013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.3787493013
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.88597828
Short name T229
Test name
Test status
Simulation time 866856906453 ps
CPU time 1505.28 seconds
Started Jul 16 04:40:04 PM PDT 24
Finished Jul 16 05:05:11 PM PDT 24
Peak memory 181376 kb
Host smart-2124512e-460b-44ae-ab7a-8d34f2731504
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88597828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.rv_timer_cfg_update_on_fly.88597828
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_random.3982344508
Short name T441
Test name
Test status
Simulation time 25861882699 ps
CPU time 42.37 seconds
Started Jul 16 04:40:20 PM PDT 24
Finished Jul 16 04:41:03 PM PDT 24
Peak memory 190808 kb
Host smart-ab4f690f-ab8b-4f00-910e-d8b62c48c536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982344508 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3982344508
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3310979393
Short name T402
Test name
Test status
Simulation time 369311623 ps
CPU time 1.1 seconds
Started Jul 16 04:40:19 PM PDT 24
Finished Jul 16 04:40:21 PM PDT 24
Peak memory 180744 kb
Host smart-b8801037-8013-4725-b100-42a0a478b79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310979393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3310979393
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.1784866866
Short name T345
Test name
Test status
Simulation time 482987798909 ps
CPU time 239.32 seconds
Started Jul 16 04:40:15 PM PDT 24
Finished Jul 16 04:44:17 PM PDT 24
Peak memory 181732 kb
Host smart-3c3a0851-d63c-4fc7-8a73-442d32b7183a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784866866 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.1784866866
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_disabled.2710749526
Short name T406
Test name
Test status
Simulation time 43934319451 ps
CPU time 57.98 seconds
Started Jul 16 04:35:01 PM PDT 24
Finished Jul 16 04:36:00 PM PDT 24
Peak memory 183240 kb
Host smart-db2a3d29-7905-4f84-87fe-17df2d8ee776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710749526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_disabled.2710749526
Directory /workspace/22.rv_timer_disabled/latest

Test location /workspace/coverage/default/22.rv_timer_random.1356134999
Short name T131
Test name
Test status
Simulation time 218068919093 ps
CPU time 547.11 seconds
Started Jul 16 04:40:20 PM PDT 24
Finished Jul 16 04:49:28 PM PDT 24
Peak memory 190404 kb
Host smart-317e9aaa-2fc7-4741-b59e-355bfcbb4fe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356134999 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.1356134999
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.1694033312
Short name T301
Test name
Test status
Simulation time 345458606144 ps
CPU time 148.68 seconds
Started Jul 16 04:35:05 PM PDT 24
Finished Jul 16 04:37:35 PM PDT 24
Peak memory 182304 kb
Host smart-39a9bc2f-7d56-42cc-9212-297dc9489446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694033312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.1694033312
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.1801907050
Short name T221
Test name
Test status
Simulation time 752418741641 ps
CPU time 1415.51 seconds
Started Jul 16 04:34:56 PM PDT 24
Finished Jul 16 04:58:32 PM PDT 24
Peak memory 191076 kb
Host smart-23fc22f2-c5d7-4dad-9d9a-7ff4b62ac053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801907050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.1801907050
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3842619943
Short name T453
Test name
Test status
Simulation time 3125264687056 ps
CPU time 796.08 seconds
Started Jul 16 04:40:21 PM PDT 24
Finished Jul 16 04:53:39 PM PDT 24
Peak memory 182220 kb
Host smart-1896cf7c-316d-483e-8959-ce5cff450e40
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842619943 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3842619943
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.842245482
Short name T82
Test name
Test status
Simulation time 78015094498 ps
CPU time 118.65 seconds
Started Jul 16 04:37:50 PM PDT 24
Finished Jul 16 04:39:49 PM PDT 24
Peak memory 183060 kb
Host smart-f1310095-26ad-4805-abcd-b84d6d7a5c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842245482 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.842245482
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.1393677050
Short name T291
Test name
Test status
Simulation time 281887053006 ps
CPU time 458.29 seconds
Started Jul 16 04:35:05 PM PDT 24
Finished Jul 16 04:42:44 PM PDT 24
Peak memory 190236 kb
Host smart-2a1aeecd-6465-4487-b97f-5f8bc789b124
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393677050 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.1393677050
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.2097269220
Short name T332
Test name
Test status
Simulation time 35518545311 ps
CPU time 54.34 seconds
Started Jul 16 04:36:19 PM PDT 24
Finished Jul 16 04:37:14 PM PDT 24
Peak memory 191488 kb
Host smart-030bfa82-d257-4fd8-9e15-d4e075f3aec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097269220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.2097269220
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.2302967629
Short name T456
Test name
Test status
Simulation time 20696198 ps
CPU time 0.6 seconds
Started Jul 16 04:35:13 PM PDT 24
Finished Jul 16 04:35:14 PM PDT 24
Peak memory 182716 kb
Host smart-304584dd-70b3-4142-864b-826786ef038a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302967629 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all
.2302967629
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all_with_rand_reset.3513308146
Short name T18
Test name
Test status
Simulation time 38390430950 ps
CPU time 154.04 seconds
Started Jul 16 04:40:21 PM PDT 24
Finished Jul 16 04:42:56 PM PDT 24
Peak memory 195140 kb
Host smart-9285282a-ed8a-4c29-93b6-72462aa9c20a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513308146 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all_with_rand_reset.3513308146
Directory /workspace/23.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.956172591
Short name T410
Test name
Test status
Simulation time 482547985598 ps
CPU time 410.65 seconds
Started Jul 16 04:35:13 PM PDT 24
Finished Jul 16 04:42:04 PM PDT 24
Peak memory 182876 kb
Host smart-35f3c9d2-7058-4a19-a0d2-6c991aeed05c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956172591 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.956172591
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.432462811
Short name T372
Test name
Test status
Simulation time 118071757578 ps
CPU time 180.44 seconds
Started Jul 16 04:40:20 PM PDT 24
Finished Jul 16 04:43:21 PM PDT 24
Peak memory 181992 kb
Host smart-8060d40f-b8e6-47d8-845a-0a9d639d7d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432462811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.432462811
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2626728612
Short name T267
Test name
Test status
Simulation time 814513642480 ps
CPU time 366.93 seconds
Started Jul 16 04:37:35 PM PDT 24
Finished Jul 16 04:43:43 PM PDT 24
Peak memory 191128 kb
Host smart-1fc6f58a-de74-454c-b27b-737b202ccc05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626728612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2626728612
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3240457339
Short name T367
Test name
Test status
Simulation time 257015068 ps
CPU time 0.96 seconds
Started Jul 16 04:40:10 PM PDT 24
Finished Jul 16 04:40:12 PM PDT 24
Peak memory 193032 kb
Host smart-79c5c912-b018-4bdd-bd8e-959e1e7d96bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240457339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3240457339
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.3779419729
Short name T136
Test name
Test status
Simulation time 306837256476 ps
CPU time 156.66 seconds
Started Jul 16 04:35:02 PM PDT 24
Finished Jul 16 04:37:39 PM PDT 24
Peak memory 183236 kb
Host smart-d217b6ff-5bbf-40d8-aecb-d210f8ab1f43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779419729 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.3779419729
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2496252113
Short name T328
Test name
Test status
Simulation time 255676548685 ps
CPU time 250.68 seconds
Started Jul 16 04:36:37 PM PDT 24
Finished Jul 16 04:40:48 PM PDT 24
Peak memory 182944 kb
Host smart-b73da667-c03f-4ec0-aa37-f69d4e324e20
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496252113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2496252113
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.928634098
Short name T374
Test name
Test status
Simulation time 137194427061 ps
CPU time 50.61 seconds
Started Jul 16 04:40:15 PM PDT 24
Finished Jul 16 04:41:07 PM PDT 24
Peak memory 182660 kb
Host smart-5a0d6e7c-7ceb-4935-8a11-0acbe04ebc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928634098 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.928634098
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.2033023762
Short name T24
Test name
Test status
Simulation time 1519416685 ps
CPU time 1.75 seconds
Started Jul 16 04:35:14 PM PDT 24
Finished Jul 16 04:35:17 PM PDT 24
Peak memory 191048 kb
Host smart-665ad56f-df5b-425d-95ce-eb67efabeda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033023762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.2033023762
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.3824961882
Short name T187
Test name
Test status
Simulation time 236954419673 ps
CPU time 560.25 seconds
Started Jul 16 04:35:21 PM PDT 24
Finished Jul 16 04:44:42 PM PDT 24
Peak memory 195664 kb
Host smart-0896f0a3-ee39-4b84-8224-92f9f6908d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824961882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.3824961882
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1492208266
Short name T134
Test name
Test status
Simulation time 758442836335 ps
CPU time 646.73 seconds
Started Jul 16 04:38:02 PM PDT 24
Finished Jul 16 04:48:49 PM PDT 24
Peak memory 183276 kb
Host smart-40e7edc2-a330-40e9-95d9-0d66838209d6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492208266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1492208266
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_random.916348460
Short name T234
Test name
Test status
Simulation time 41582513332 ps
CPU time 74 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:41:24 PM PDT 24
Peak memory 191048 kb
Host smart-82094a00-236a-41cd-bed3-22845c067d7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916348460 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.916348460
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.1062143524
Short name T397
Test name
Test status
Simulation time 70975677710 ps
CPU time 129.15 seconds
Started Jul 16 04:39:48 PM PDT 24
Finished Jul 16 04:41:58 PM PDT 24
Peak memory 194788 kb
Host smart-f2ba91c8-8918-4e02-a97d-754b9cf3c2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062143524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.1062143524
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.3520700697
Short name T436
Test name
Test status
Simulation time 544781808340 ps
CPU time 241.12 seconds
Started Jul 16 04:38:15 PM PDT 24
Finished Jul 16 04:42:16 PM PDT 24
Peak memory 182924 kb
Host smart-456eeeaf-e737-4a52-8ac8-478cb7a6cd17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520700697 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all
.3520700697
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3828881993
Short name T143
Test name
Test status
Simulation time 90192264415 ps
CPU time 139.21 seconds
Started Jul 16 04:35:20 PM PDT 24
Finished Jul 16 04:37:40 PM PDT 24
Peak memory 183048 kb
Host smart-c908cac6-504d-455f-abe9-36ce7bcb8269
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828881993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3828881993
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_disabled.3272143938
Short name T425
Test name
Test status
Simulation time 143133409403 ps
CPU time 60.89 seconds
Started Jul 16 04:35:21 PM PDT 24
Finished Jul 16 04:36:22 PM PDT 24
Peak memory 183060 kb
Host smart-9924af54-c727-46f2-8851-012267562aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272143938 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_disabled.3272143938
Directory /workspace/27.rv_timer_disabled/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.3940060742
Short name T430
Test name
Test status
Simulation time 92289968786 ps
CPU time 120.62 seconds
Started Jul 16 04:35:31 PM PDT 24
Finished Jul 16 04:37:33 PM PDT 24
Peak memory 191144 kb
Host smart-ea881b23-cd25-4365-a5fc-9a82def2d1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940060742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.3940060742
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.1025811544
Short name T47
Test name
Test status
Simulation time 38838392197 ps
CPU time 413.27 seconds
Started Jul 16 04:37:37 PM PDT 24
Finished Jul 16 04:44:30 PM PDT 24
Peak memory 205860 kb
Host smart-44db033a-1964-479a-990b-3742743ecc36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025811544 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.1025811544
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.2800318797
Short name T200
Test name
Test status
Simulation time 370132107404 ps
CPU time 298.25 seconds
Started Jul 16 04:39:57 PM PDT 24
Finished Jul 16 04:44:56 PM PDT 24
Peak memory 182208 kb
Host smart-ae138757-63a0-4f49-9e3b-730bd42bbb2d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800318797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.2800318797
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.162214957
Short name T29
Test name
Test status
Simulation time 29361598692 ps
CPU time 22.19 seconds
Started Jul 16 04:35:21 PM PDT 24
Finished Jul 16 04:35:43 PM PDT 24
Peak memory 183060 kb
Host smart-fd7f5f12-8ee8-4c60-8207-2f74e3cf3b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162214957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.162214957
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.1450627925
Short name T271
Test name
Test status
Simulation time 153350154447 ps
CPU time 242.11 seconds
Started Jul 16 04:40:15 PM PDT 24
Finished Jul 16 04:44:19 PM PDT 24
Peak memory 190856 kb
Host smart-cbc586e6-e1be-4788-b33b-50775bd81b19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450627925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.1450627925
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.4144088612
Short name T209
Test name
Test status
Simulation time 303067764795 ps
CPU time 180.04 seconds
Started Jul 16 04:37:04 PM PDT 24
Finished Jul 16 04:40:05 PM PDT 24
Peak memory 182964 kb
Host smart-bf13d9c4-ee5c-4ff3-b854-33a9afbb6c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144088612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.4144088612
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.984314194
Short name T242
Test name
Test status
Simulation time 669482886928 ps
CPU time 2380.86 seconds
Started Jul 16 04:35:27 PM PDT 24
Finished Jul 16 05:15:09 PM PDT 24
Peak memory 190860 kb
Host smart-3c25c40a-185c-4de5-9e6e-abd293cda5cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984314194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all.
984314194
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.766944758
Short name T42
Test name
Test status
Simulation time 53289345511 ps
CPU time 105.11 seconds
Started Jul 16 04:39:39 PM PDT 24
Finished Jul 16 04:41:25 PM PDT 24
Peak memory 205508 kb
Host smart-f7ce825f-599a-4e16-b6a2-e0a80eff5dbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766944758 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.766944758
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.2745600204
Short name T382
Test name
Test status
Simulation time 145651660812 ps
CPU time 117.75 seconds
Started Jul 16 04:35:39 PM PDT 24
Finished Jul 16 04:37:37 PM PDT 24
Peak memory 182876 kb
Host smart-03a64733-918f-4db2-9793-99af8b18cf96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745600204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.2745600204
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random.1317299393
Short name T6
Test name
Test status
Simulation time 172913438007 ps
CPU time 344.54 seconds
Started Jul 16 04:39:53 PM PDT 24
Finished Jul 16 04:45:38 PM PDT 24
Peak memory 189544 kb
Host smart-6f8b3424-eb34-44b5-868a-443389f8e5cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317299393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.1317299393
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.2112849561
Short name T446
Test name
Test status
Simulation time 230127123781 ps
CPU time 116.68 seconds
Started Jul 16 04:39:53 PM PDT 24
Finished Jul 16 04:41:51 PM PDT 24
Peak memory 189788 kb
Host smart-14024d8f-6030-459d-bc97-6d54c4203e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112849561 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.2112849561
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.601740952
Short name T259
Test name
Test status
Simulation time 128904909595 ps
CPU time 212.38 seconds
Started Jul 16 04:40:28 PM PDT 24
Finished Jul 16 04:44:01 PM PDT 24
Peak memory 183008 kb
Host smart-e57bf2be-3e84-4e54-b370-5837832c0723
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601740952 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.rv_timer_cfg_update_on_fly.601740952
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.2287813517
Short name T373
Test name
Test status
Simulation time 221846547261 ps
CPU time 142.62 seconds
Started Jul 16 04:39:54 PM PDT 24
Finished Jul 16 04:42:18 PM PDT 24
Peak memory 182172 kb
Host smart-bbe34ff6-8b84-42c5-bb21-531733517707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287813517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.2287813517
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random.4136933953
Short name T218
Test name
Test status
Simulation time 14515515303 ps
CPU time 22.09 seconds
Started Jul 16 04:40:28 PM PDT 24
Finished Jul 16 04:40:50 PM PDT 24
Peak memory 183008 kb
Host smart-af23cbce-1125-4081-84a1-2375e5a707aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136933953 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.4136933953
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.3330201760
Short name T341
Test name
Test status
Simulation time 57612323813 ps
CPU time 96.42 seconds
Started Jul 16 04:40:24 PM PDT 24
Finished Jul 16 04:42:01 PM PDT 24
Peak memory 190764 kb
Host smart-2e6f9663-48d9-4a5f-bd90-d4628259cc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330201760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.3330201760
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.4114987690
Short name T23
Test name
Test status
Simulation time 105135416 ps
CPU time 0.79 seconds
Started Jul 16 04:39:43 PM PDT 24
Finished Jul 16 04:39:45 PM PDT 24
Peak memory 212860 kb
Host smart-494b2051-9cbc-4837-981e-3012b89d0d30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114987690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.4114987690
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all_with_rand_reset.3683689176
Short name T44
Test name
Test status
Simulation time 70702494526 ps
CPU time 589.13 seconds
Started Jul 16 04:34:55 PM PDT 24
Finished Jul 16 04:44:44 PM PDT 24
Peak memory 205776 kb
Host smart-157da4a7-b49f-48d1-840d-06716ada6c6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683689176 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all_with_rand_reset.3683689176
Directory /workspace/3.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.3615356167
Short name T327
Test name
Test status
Simulation time 434904196451 ps
CPU time 234.35 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:44:03 PM PDT 24
Peak memory 182516 kb
Host smart-657175e7-f985-44ad-8081-3dd6e7f561c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615356167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.3615356167
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.3083496337
Short name T395
Test name
Test status
Simulation time 505720973957 ps
CPU time 201.69 seconds
Started Jul 16 04:39:38 PM PDT 24
Finished Jul 16 04:43:01 PM PDT 24
Peak memory 181156 kb
Host smart-9eada440-f524-46e5-9312-98e206b7889a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083496337 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.3083496337
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.3960414389
Short name T122
Test name
Test status
Simulation time 130573667243 ps
CPU time 153.62 seconds
Started Jul 16 04:40:14 PM PDT 24
Finished Jul 16 04:42:50 PM PDT 24
Peak memory 182644 kb
Host smart-bfa47ae1-c502-44ee-ae28-9f13b7cc0ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960414389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.3960414389
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3172203383
Short name T333
Test name
Test status
Simulation time 57058178626 ps
CPU time 88.61 seconds
Started Jul 16 04:40:03 PM PDT 24
Finished Jul 16 04:41:33 PM PDT 24
Peak memory 181656 kb
Host smart-6adf0c04-3f82-43bd-a24e-927fe1f116a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172203383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3172203383
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.3957330035
Short name T375
Test name
Test status
Simulation time 103893438509 ps
CPU time 154.98 seconds
Started Jul 16 04:40:43 PM PDT 24
Finished Jul 16 04:43:19 PM PDT 24
Peak memory 182892 kb
Host smart-8bb284d1-eded-49e6-8ed9-3634b7d9f83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957330035 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.3957330035
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.2934139059
Short name T319
Test name
Test status
Simulation time 32853584504 ps
CPU time 16.34 seconds
Started Jul 16 04:36:01 PM PDT 24
Finished Jul 16 04:36:18 PM PDT 24
Peak memory 182664 kb
Host smart-742dd0ff-4b0d-4273-ba64-eb3068abbec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934139059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.2934139059
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.1294030451
Short name T84
Test name
Test status
Simulation time 22803534162 ps
CPU time 35.51 seconds
Started Jul 16 04:39:38 PM PDT 24
Finished Jul 16 04:40:15 PM PDT 24
Peak memory 189156 kb
Host smart-38184aa9-daa9-4851-b075-f05638d9dbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294030451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.1294030451
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.1479026917
Short name T245
Test name
Test status
Simulation time 576200446583 ps
CPU time 979.35 seconds
Started Jul 16 04:40:13 PM PDT 24
Finished Jul 16 04:56:34 PM PDT 24
Peak memory 182664 kb
Host smart-b1f1921f-3554-4fd9-92bd-c464ab883f46
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479026917 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.rv_timer_cfg_update_on_fly.1479026917
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.2801263764
Short name T391
Test name
Test status
Simulation time 207768985214 ps
CPU time 80.75 seconds
Started Jul 16 04:40:14 PM PDT 24
Finished Jul 16 04:41:37 PM PDT 24
Peak memory 182644 kb
Host smart-14727092-288c-4539-978e-b9d782aa6914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801263764 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.2801263764
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.46668915
Short name T210
Test name
Test status
Simulation time 94172031170 ps
CPU time 151.73 seconds
Started Jul 16 04:36:33 PM PDT 24
Finished Jul 16 04:39:05 PM PDT 24
Peak memory 182900 kb
Host smart-0ed2eda4-67a0-4213-930d-163e88c66e5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46668915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.46668915
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.1084565854
Short name T429
Test name
Test status
Simulation time 9152581434 ps
CPU time 13.31 seconds
Started Jul 16 04:37:07 PM PDT 24
Finished Jul 16 04:37:21 PM PDT 24
Peak memory 182988 kb
Host smart-c12be9ac-c694-49e9-9a8b-01181796fc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084565854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.1084565854
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.1473675790
Short name T77
Test name
Test status
Simulation time 351112326789 ps
CPU time 764.69 seconds
Started Jul 16 04:39:53 PM PDT 24
Finished Jul 16 04:52:39 PM PDT 24
Peak memory 194272 kb
Host smart-d4205049-a969-423b-8622-a4bd505b2aa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473675790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.1473675790
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3386542023
Short name T188
Test name
Test status
Simulation time 379284278449 ps
CPU time 365.27 seconds
Started Jul 16 04:40:04 PM PDT 24
Finished Jul 16 04:46:10 PM PDT 24
Peak memory 182512 kb
Host smart-c064b968-a953-4380-8e4b-f18fab5ae05f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386542023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3386542023
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.4079608840
Short name T455
Test name
Test status
Simulation time 14876009291 ps
CPU time 20.14 seconds
Started Jul 16 04:37:41 PM PDT 24
Finished Jul 16 04:38:01 PM PDT 24
Peak memory 182908 kb
Host smart-f1c2a60e-6223-4a73-b659-9febaf5ac1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079608840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.4079608840
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1095875741
Short name T230
Test name
Test status
Simulation time 47990915861 ps
CPU time 25.45 seconds
Started Jul 16 04:37:18 PM PDT 24
Finished Jul 16 04:37:44 PM PDT 24
Peak memory 182844 kb
Host smart-dbf67cc8-966d-46fd-8b87-8fd61c3d3a66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095875741 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1095875741
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1584878017
Short name T215
Test name
Test status
Simulation time 110223657055 ps
CPU time 83.25 seconds
Started Jul 16 04:39:39 PM PDT 24
Finished Jul 16 04:41:03 PM PDT 24
Peak memory 190324 kb
Host smart-68389698-f8a5-43ef-a8bc-3491b34e9a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584878017 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1584878017
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2185845560
Short name T67
Test name
Test status
Simulation time 525711205229 ps
CPU time 875.28 seconds
Started Jul 16 04:40:19 PM PDT 24
Finished Jul 16 04:54:55 PM PDT 24
Peak memory 182800 kb
Host smart-8ec74158-38a1-466d-881f-6d31e4d2b5e3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185845560 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2185845560
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_random.3573314906
Short name T305
Test name
Test status
Simulation time 123170820442 ps
CPU time 654.1 seconds
Started Jul 16 04:37:03 PM PDT 24
Finished Jul 16 04:47:58 PM PDT 24
Peak memory 191436 kb
Host smart-5adafaf3-13b0-480f-b02c-9cf074276ba7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573314906 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3573314906
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.828789333
Short name T226
Test name
Test status
Simulation time 520497499751 ps
CPU time 479.29 seconds
Started Jul 16 04:40:14 PM PDT 24
Finished Jul 16 04:48:15 PM PDT 24
Peak memory 194268 kb
Host smart-a8fb4e13-91a0-4e8c-aa7f-5b1b4e04717c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828789333 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.828789333
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1562275371
Short name T288
Test name
Test status
Simulation time 2940137495066 ps
CPU time 2771.76 seconds
Started Jul 16 04:40:14 PM PDT 24
Finished Jul 16 05:26:28 PM PDT 24
Peak memory 190840 kb
Host smart-f5560f2e-3caa-4a2c-b709-a10425cab653
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562275371 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1562275371
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all_with_rand_reset.3920118936
Short name T86
Test name
Test status
Simulation time 243243585625 ps
CPU time 453.5 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 04:47:41 PM PDT 24
Peak memory 210864 kb
Host smart-3f92cc6f-edb5-4f85-95cb-9175de446788
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920118936 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all_with_rand_reset.3920118936
Directory /workspace/34.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.369249841
Short name T363
Test name
Test status
Simulation time 8845097960 ps
CPU time 15.86 seconds
Started Jul 16 04:36:01 PM PDT 24
Finished Jul 16 04:36:18 PM PDT 24
Peak memory 182644 kb
Host smart-149ddba7-cb78-47bc-8604-48c2fdb4d8a3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369249841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.rv_timer_cfg_update_on_fly.369249841
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.2385045523
Short name T387
Test name
Test status
Simulation time 190028203485 ps
CPU time 141.74 seconds
Started Jul 16 04:40:43 PM PDT 24
Finished Jul 16 04:43:06 PM PDT 24
Peak memory 182892 kb
Host smart-9e63921e-f61b-4ad4-a6f1-dfdf47ff8859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385045523 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.2385045523
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random.771992055
Short name T8
Test name
Test status
Simulation time 72901244180 ps
CPU time 374.76 seconds
Started Jul 16 04:39:38 PM PDT 24
Finished Jul 16 04:45:54 PM PDT 24
Peak memory 189316 kb
Host smart-7b390b07-3cfa-4c30-aade-0fa28d3f0d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771992055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.771992055
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.120330279
Short name T421
Test name
Test status
Simulation time 41613074673 ps
CPU time 191.81 seconds
Started Jul 16 04:37:27 PM PDT 24
Finished Jul 16 04:40:40 PM PDT 24
Peak memory 182988 kb
Host smart-220d299b-16d3-489a-9c35-ff4d3a8299bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120330279 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.120330279
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.3520824854
Short name T377
Test name
Test status
Simulation time 157692669034 ps
CPU time 46.28 seconds
Started Jul 16 04:37:28 PM PDT 24
Finished Jul 16 04:38:15 PM PDT 24
Peak memory 183056 kb
Host smart-4121811b-2a90-4e6a-a651-83048b243657
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520824854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all
.3520824854
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.3631187113
Short name T449
Test name
Test status
Simulation time 233734263330 ps
CPU time 361.72 seconds
Started Jul 16 04:37:18 PM PDT 24
Finished Jul 16 04:43:20 PM PDT 24
Peak memory 183224 kb
Host smart-0b84cf88-afec-4bf0-8ae4-181500e4016f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631187113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.3631187113
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.2079670012
Short name T369
Test name
Test status
Simulation time 398080904196 ps
CPU time 126.79 seconds
Started Jul 16 04:40:24 PM PDT 24
Finished Jul 16 04:42:31 PM PDT 24
Peak memory 182340 kb
Host smart-fcdd4627-2cf0-4033-b58b-286af09ce4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079670012 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.2079670012
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.3170942117
Short name T409
Test name
Test status
Simulation time 430594793 ps
CPU time 0.71 seconds
Started Jul 16 04:35:43 PM PDT 24
Finished Jul 16 04:35:44 PM PDT 24
Peak memory 182780 kb
Host smart-f9ce6c96-dc94-4ea7-b30a-dfc8e947cf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170942117 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.3170942117
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.3882544249
Short name T72
Test name
Test status
Simulation time 351938055200 ps
CPU time 545.42 seconds
Started Jul 16 04:36:14 PM PDT 24
Finished Jul 16 04:45:21 PM PDT 24
Peak memory 182972 kb
Host smart-d5e4f026-7f2d-4d54-b44d-eb097327033c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882544249 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.3882544249
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.1145548393
Short name T390
Test name
Test status
Simulation time 233395042966 ps
CPU time 360.77 seconds
Started Jul 16 04:36:39 PM PDT 24
Finished Jul 16 04:42:41 PM PDT 24
Peak memory 182976 kb
Host smart-83e195bd-3d00-41c8-9996-25ea3104e4c3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145548393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.rv_timer_cfg_update_on_fly.1145548393
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_disabled.3758261850
Short name T380
Test name
Test status
Simulation time 131020085317 ps
CPU time 25.16 seconds
Started Jul 16 04:40:43 PM PDT 24
Finished Jul 16 04:41:09 PM PDT 24
Peak memory 182840 kb
Host smart-e08c1cce-8439-41f8-8e8a-fd67615f78db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758261850 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_disabled.3758261850
Directory /workspace/37.rv_timer_disabled/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.3343978782
Short name T405
Test name
Test status
Simulation time 214193782 ps
CPU time 0.6 seconds
Started Jul 16 04:39:59 PM PDT 24
Finished Jul 16 04:40:00 PM PDT 24
Peak memory 182076 kb
Host smart-3fb4edd1-baff-40c6-ae8d-ab5ff715c67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343978782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.3343978782
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1605951941
Short name T40
Test name
Test status
Simulation time 1341937057755 ps
CPU time 1290.21 seconds
Started Jul 16 04:40:37 PM PDT 24
Finished Jul 16 05:02:08 PM PDT 24
Peak memory 191036 kb
Host smart-a12d0c70-1a33-47fd-b0be-db5774279031
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605951941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1605951941
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.3018572299
Short name T304
Test name
Test status
Simulation time 505143819949 ps
CPU time 612.96 seconds
Started Jul 16 04:40:10 PM PDT 24
Finished Jul 16 04:50:24 PM PDT 24
Peak memory 182652 kb
Host smart-f62c2c7e-02e5-47e7-9c0e-4b600a35a7c9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018572299 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.3018572299
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2195458672
Short name T415
Test name
Test status
Simulation time 100740526665 ps
CPU time 75.52 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 04:41:29 PM PDT 24
Peak memory 182664 kb
Host smart-b41d8ad0-e5aa-42e0-816d-cc04157dc79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195458672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2195458672
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.4142100095
Short name T177
Test name
Test status
Simulation time 372815830416 ps
CPU time 537.53 seconds
Started Jul 16 04:35:59 PM PDT 24
Finished Jul 16 04:44:57 PM PDT 24
Peak memory 191096 kb
Host smart-8e218959-9697-4a29-bdf3-300dc7098ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142100095 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.4142100095
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.1902301513
Short name T366
Test name
Test status
Simulation time 1434930192 ps
CPU time 1.58 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 04:40:15 PM PDT 24
Peak memory 182596 kb
Host smart-d153b4f8-7c6f-4294-92ca-2695db1492d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902301513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.1902301513
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.4001483442
Short name T61
Test name
Test status
Simulation time 189479594467 ps
CPU time 85.62 seconds
Started Jul 16 04:40:03 PM PDT 24
Finished Jul 16 04:41:30 PM PDT 24
Peak memory 194828 kb
Host smart-ec12ce5d-ec67-40ef-a166-fad738a9753d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001483442 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.4001483442
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.1400679323
Short name T270
Test name
Test status
Simulation time 166614225639 ps
CPU time 153.45 seconds
Started Jul 16 04:36:10 PM PDT 24
Finished Jul 16 04:38:44 PM PDT 24
Peak memory 182880 kb
Host smart-f1224c7e-12a3-4916-87a5-a84a05c14d35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400679323 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.1400679323
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.1940374803
Short name T462
Test name
Test status
Simulation time 108771871509 ps
CPU time 137.24 seconds
Started Jul 16 04:40:19 PM PDT 24
Finished Jul 16 04:42:38 PM PDT 24
Peak memory 181804 kb
Host smart-3171c2bb-bb73-4464-a61d-2fca2b81500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940374803 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.1940374803
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.1742592517
Short name T337
Test name
Test status
Simulation time 260495840956 ps
CPU time 119.11 seconds
Started Jul 16 04:40:04 PM PDT 24
Finished Jul 16 04:42:04 PM PDT 24
Peak memory 190884 kb
Host smart-db33b1bc-952c-444e-bef3-e82e453634f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742592517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.1742592517
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.972582573
Short name T202
Test name
Test status
Simulation time 1501837342973 ps
CPU time 1167.7 seconds
Started Jul 16 04:39:54 PM PDT 24
Finished Jul 16 04:59:23 PM PDT 24
Peak memory 190416 kb
Host smart-c5f78969-4e43-4310-bbd5-2a80358177eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972582573 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all.
972582573
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.1124254809
Short name T16
Test name
Test status
Simulation time 317442287545 ps
CPU time 559.07 seconds
Started Jul 16 04:40:04 PM PDT 24
Finished Jul 16 04:49:24 PM PDT 24
Peak memory 207488 kb
Host smart-073d8fea-72ea-42f9-a3f4-96579f3ca8d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124254809 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.1124254809
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.1895213522
Short name T361
Test name
Test status
Simulation time 149122041412 ps
CPU time 248.17 seconds
Started Jul 16 04:39:43 PM PDT 24
Finished Jul 16 04:43:52 PM PDT 24
Peak memory 182568 kb
Host smart-1412ca23-cb4c-4e0e-b5de-819972749f1e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895213522 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.1895213522
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.638699832
Short name T419
Test name
Test status
Simulation time 143054560502 ps
CPU time 179.73 seconds
Started Jul 16 04:39:57 PM PDT 24
Finished Jul 16 04:42:57 PM PDT 24
Peak memory 182968 kb
Host smart-e7e6336f-f676-4ba2-a829-f272ca45cfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638699832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.638699832
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random.2876974910
Short name T137
Test name
Test status
Simulation time 66610158369 ps
CPU time 123.75 seconds
Started Jul 16 04:39:59 PM PDT 24
Finished Jul 16 04:42:04 PM PDT 24
Peak memory 190792 kb
Host smart-6fb528cd-b985-4e32-aa7c-a7749dce3b5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876974910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.2876974910
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1389161234
Short name T151
Test name
Test status
Simulation time 217683215549 ps
CPU time 454.92 seconds
Started Jul 16 04:39:43 PM PDT 24
Finished Jul 16 04:47:19 PM PDT 24
Peak memory 190980 kb
Host smart-efbb7016-f08a-4f41-9e49-9ed8d2c80528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389161234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1389161234
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.2244069302
Short name T19
Test name
Test status
Simulation time 113833432 ps
CPU time 0.85 seconds
Started Jul 16 04:35:34 PM PDT 24
Finished Jul 16 04:35:36 PM PDT 24
Peak memory 210620 kb
Host smart-fc3750ed-5cca-438d-8a3c-7e33b1e33faf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244069302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.2244069302
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.1135072895
Short name T356
Test name
Test status
Simulation time 343722608676 ps
CPU time 508.48 seconds
Started Jul 16 04:40:19 PM PDT 24
Finished Jul 16 04:48:49 PM PDT 24
Peak memory 182564 kb
Host smart-dc5e8e81-b74b-4092-b9a0-3250ead851b1
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135072895 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.1135072895
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.2891154709
Short name T394
Test name
Test status
Simulation time 413516573139 ps
CPU time 172.56 seconds
Started Jul 16 04:40:37 PM PDT 24
Finished Jul 16 04:43:30 PM PDT 24
Peak memory 182664 kb
Host smart-45396996-e14d-4222-bc15-c4a778a8eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891154709 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.2891154709
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.291436114
Short name T170
Test name
Test status
Simulation time 144746826970 ps
CPU time 220.86 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 04:43:54 PM PDT 24
Peak memory 190876 kb
Host smart-c264f7b3-6500-43f2-92a0-b4778d5a0d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291436114 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.291436114
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.2990377575
Short name T388
Test name
Test status
Simulation time 40169147403 ps
CPU time 68.79 seconds
Started Jul 16 04:38:03 PM PDT 24
Finished Jul 16 04:39:13 PM PDT 24
Peak memory 182988 kb
Host smart-0195e78c-03a8-4bc0-9f16-146e1a76c2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990377575 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.2990377575
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.3107572498
Short name T411
Test name
Test status
Simulation time 87291080159 ps
CPU time 86.27 seconds
Started Jul 16 04:40:04 PM PDT 24
Finished Jul 16 04:41:32 PM PDT 24
Peak memory 192716 kb
Host smart-75d5ed69-b5b2-4dac-8fe7-82ea5925e3a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107572498 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.3107572498
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.3877430553
Short name T400
Test name
Test status
Simulation time 37741952317 ps
CPU time 25.51 seconds
Started Jul 16 04:38:03 PM PDT 24
Finished Jul 16 04:38:29 PM PDT 24
Peak memory 182984 kb
Host smart-bb6346a1-8b5b-4c2d-a292-6eb51a5e0c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877430553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.3877430553
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.2572131654
Short name T14
Test name
Test status
Simulation time 823705120447 ps
CPU time 505.18 seconds
Started Jul 16 04:40:26 PM PDT 24
Finished Jul 16 04:48:52 PM PDT 24
Peak memory 190196 kb
Host smart-f375964a-c8f2-4008-a38b-a9eca6c33c06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572131654 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.2572131654
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.2157737120
Short name T461
Test name
Test status
Simulation time 380224649 ps
CPU time 1.19 seconds
Started Jul 16 04:36:17 PM PDT 24
Finished Jul 16 04:36:18 PM PDT 24
Peak memory 182852 kb
Host smart-40fd4a60-a279-4635-a049-b5f17771ccf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157737120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.2157737120
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.2707832252
Short name T463
Test name
Test status
Simulation time 484176617003 ps
CPU time 459.55 seconds
Started Jul 16 04:40:22 PM PDT 24
Finished Jul 16 04:48:02 PM PDT 24
Peak memory 181536 kb
Host smart-ed24e1ad-550b-4864-99c9-51f86648e8bf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707832252 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.2707832252
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.3531625752
Short name T371
Test name
Test status
Simulation time 203757468224 ps
CPU time 146.34 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:42:35 PM PDT 24
Peak memory 181396 kb
Host smart-b9695be1-1f7e-49e7-b78e-d281cadb0a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531625752 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.3531625752
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.1587254808
Short name T214
Test name
Test status
Simulation time 182830419999 ps
CPU time 237.45 seconds
Started Jul 16 04:39:58 PM PDT 24
Finished Jul 16 04:43:56 PM PDT 24
Peak memory 190692 kb
Host smart-a7220549-c6e9-49ae-a241-024a139cffd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587254808 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.1587254808
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.2963270131
Short name T423
Test name
Test status
Simulation time 38355165371 ps
CPU time 55.62 seconds
Started Jul 16 04:40:10 PM PDT 24
Finished Jul 16 04:41:07 PM PDT 24
Peak memory 182668 kb
Host smart-0dd7e656-f5ab-43f3-8e81-2281257aeca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963270131 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.2963270131
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1901083519
Short name T398
Test name
Test status
Simulation time 21436503 ps
CPU time 0.57 seconds
Started Jul 16 04:37:22 PM PDT 24
Finished Jul 16 04:37:23 PM PDT 24
Peak memory 182704 kb
Host smart-90e1110e-1476-42ff-a50e-396ffa3d35f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901083519 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1901083519
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.3289567965
Short name T185
Test name
Test status
Simulation time 78374828664 ps
CPU time 38.63 seconds
Started Jul 16 04:39:56 PM PDT 24
Finished Jul 16 04:40:35 PM PDT 24
Peak memory 182608 kb
Host smart-2d689df5-a33c-4afe-8d58-ae357e245274
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289567965 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.rv_timer_cfg_update_on_fly.3289567965
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.2401124151
Short name T386
Test name
Test status
Simulation time 24329630090 ps
CPU time 38.3 seconds
Started Jul 16 04:39:56 PM PDT 24
Finished Jul 16 04:40:35 PM PDT 24
Peak memory 182220 kb
Host smart-be924fe4-bbf1-448c-ba31-3c0f47991a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401124151 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.2401124151
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random.3047523225
Short name T331
Test name
Test status
Simulation time 993479181561 ps
CPU time 245.19 seconds
Started Jul 16 04:39:56 PM PDT 24
Finished Jul 16 04:44:02 PM PDT 24
Peak memory 190796 kb
Host smart-b954a2df-135c-4dfc-9e59-223e91a76787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047523225 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.3047523225
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.3127130919
Short name T418
Test name
Test status
Simulation time 24334891000 ps
CPU time 21.44 seconds
Started Jul 16 04:37:14 PM PDT 24
Finished Jul 16 04:37:35 PM PDT 24
Peak memory 182948 kb
Host smart-47803722-c872-4f59-97b1-2b425e554edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127130919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.3127130919
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2496233079
Short name T142
Test name
Test status
Simulation time 2668208406344 ps
CPU time 2194.51 seconds
Started Jul 16 04:38:04 PM PDT 24
Finished Jul 16 05:14:39 PM PDT 24
Peak memory 191180 kb
Host smart-74bfae74-14b3-4740-b38d-3e9fd54c4585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496233079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2496233079
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.2344332995
Short name T43
Test name
Test status
Simulation time 91653434165 ps
CPU time 116.82 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 04:42:05 PM PDT 24
Peak memory 195768 kb
Host smart-c11b9fb2-2589-482c-a916-659ad68ac389
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344332995 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.2344332995
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.1283276920
Short name T278
Test name
Test status
Simulation time 240631147355 ps
CPU time 368.5 seconds
Started Jul 16 04:37:10 PM PDT 24
Finished Jul 16 04:43:19 PM PDT 24
Peak memory 182892 kb
Host smart-106bd5a8-74ea-4a16-b991-dac4f252220c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283276920 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.rv_timer_cfg_update_on_fly.1283276920
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.26482234
Short name T385
Test name
Test status
Simulation time 618260803920 ps
CPU time 121.7 seconds
Started Jul 16 04:36:29 PM PDT 24
Finished Jul 16 04:38:31 PM PDT 24
Peak memory 182876 kb
Host smart-3d3595df-d3a5-4b78-b2c0-46353afe028c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26482234 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.26482234
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random.281423600
Short name T334
Test name
Test status
Simulation time 272252633495 ps
CPU time 662.01 seconds
Started Jul 16 04:40:10 PM PDT 24
Finished Jul 16 04:51:13 PM PDT 24
Peak memory 191828 kb
Host smart-e1d3eecc-6284-4dbf-a6ea-b10eb207980f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281423600 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.281423600
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3202960773
Short name T422
Test name
Test status
Simulation time 20685684 ps
CPU time 0.55 seconds
Started Jul 16 04:37:52 PM PDT 24
Finished Jul 16 04:37:53 PM PDT 24
Peak memory 182708 kb
Host smart-c10ec9d4-4fe1-4966-9601-22db71253666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202960773 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3202960773
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all_with_rand_reset.3950944954
Short name T416
Test name
Test status
Simulation time 35567686450 ps
CPU time 166.17 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:42:56 PM PDT 24
Peak memory 197304 kb
Host smart-2c2163e9-fc78-4131-9d93-06f396396b07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950944954 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all_with_rand_reset.3950944954
Directory /workspace/44.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.1270142342
Short name T326
Test name
Test status
Simulation time 21000309609 ps
CPU time 11.38 seconds
Started Jul 16 04:39:57 PM PDT 24
Finished Jul 16 04:40:09 PM PDT 24
Peak memory 182608 kb
Host smart-bd5c8e16-143d-4606-84fd-b1eb87fdae93
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270142342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.1270142342
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.303026104
Short name T32
Test name
Test status
Simulation time 575782822680 ps
CPU time 198.48 seconds
Started Jul 16 04:36:22 PM PDT 24
Finished Jul 16 04:39:41 PM PDT 24
Peak memory 182896 kb
Host smart-a70d7f5d-18ee-4da4-9f12-acc7f2f27ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303026104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.303026104
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1549177059
Short name T119
Test name
Test status
Simulation time 2920403462846 ps
CPU time 1016.12 seconds
Started Jul 16 04:37:12 PM PDT 24
Finished Jul 16 04:54:08 PM PDT 24
Peak memory 191488 kb
Host smart-dc413237-7fce-4ab6-b53c-7f2bc6eeed98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549177059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1549177059
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2602261636
Short name T265
Test name
Test status
Simulation time 218008327446 ps
CPU time 519.97 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:48:48 PM PDT 24
Peak memory 182584 kb
Host smart-92325a21-9bb0-4243-990e-b6e1a2292e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602261636 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2602261636
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3513643706
Short name T76
Test name
Test status
Simulation time 167427945286 ps
CPU time 625.35 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 04:50:39 PM PDT 24
Peak memory 194048 kb
Host smart-8a289283-23a0-4a08-bbaa-f6b4550ff0ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513643706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3513643706
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all_with_rand_reset.393143460
Short name T41
Test name
Test status
Simulation time 144486371982 ps
CPU time 405.55 seconds
Started Jul 16 04:40:21 PM PDT 24
Finished Jul 16 04:47:08 PM PDT 24
Peak memory 204608 kb
Host smart-a19d9b6d-79ea-42fb-8042-513d51907ad0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393143460 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all_with_rand_reset.393143460
Directory /workspace/45.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.1793298312
Short name T219
Test name
Test status
Simulation time 44146239948 ps
CPU time 20.75 seconds
Started Jul 16 04:39:47 PM PDT 24
Finished Jul 16 04:40:08 PM PDT 24
Peak memory 181716 kb
Host smart-8e772ce3-ef7b-4c6a-85c0-9e5fba2474e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793298312 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.rv_timer_cfg_update_on_fly.1793298312
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.287763316
Short name T4
Test name
Test status
Simulation time 69070519219 ps
CPU time 91.76 seconds
Started Jul 16 04:40:21 PM PDT 24
Finished Jul 16 04:41:55 PM PDT 24
Peak memory 181212 kb
Host smart-6f9e41e0-ecaf-4b08-a5c9-938a64e75323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287763316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.287763316
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.96499506
Short name T459
Test name
Test status
Simulation time 62386173568 ps
CPU time 116.72 seconds
Started Jul 16 04:37:24 PM PDT 24
Finished Jul 16 04:39:21 PM PDT 24
Peak memory 182820 kb
Host smart-a8604e29-c002-4fec-aa75-16089367e18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96499506 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.96499506
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.3500229400
Short name T193
Test name
Test status
Simulation time 1407170934753 ps
CPU time 366.05 seconds
Started Jul 16 04:37:04 PM PDT 24
Finished Jul 16 04:43:10 PM PDT 24
Peak memory 191480 kb
Host smart-5e36ad62-3d2c-4b2f-98d3-5db38d15365d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500229400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.3500229400
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2321027595
Short name T129
Test name
Test status
Simulation time 438557731774 ps
CPU time 767.15 seconds
Started Jul 16 04:40:11 PM PDT 24
Finished Jul 16 04:53:00 PM PDT 24
Peak memory 182664 kb
Host smart-2dfce497-26f5-49d4-ab48-695349a1fb3b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321027595 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2321027595
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1456430115
Short name T396
Test name
Test status
Simulation time 380077244625 ps
CPU time 149.34 seconds
Started Jul 16 04:40:21 PM PDT 24
Finished Jul 16 04:42:52 PM PDT 24
Peak memory 180088 kb
Host smart-8d34db1d-8932-441b-8eb0-901ab573e903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456430115 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1456430115
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.749145220
Short name T175
Test name
Test status
Simulation time 224912313331 ps
CPU time 271.46 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:44:41 PM PDT 24
Peak memory 190360 kb
Host smart-9641bb8f-b8e7-4081-b07a-d29841f49c8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749145220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.749145220
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.669224257
Short name T62
Test name
Test status
Simulation time 94173778047 ps
CPU time 77.12 seconds
Started Jul 16 04:40:04 PM PDT 24
Finished Jul 16 04:41:22 PM PDT 24
Peak memory 190868 kb
Host smart-ddd569cb-d07a-4b23-97b4-a470af909f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669224257 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.669224257
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all_with_rand_reset.3820707450
Short name T78
Test name
Test status
Simulation time 67282645368 ps
CPU time 381.59 seconds
Started Jul 16 04:40:06 PM PDT 24
Finished Jul 16 04:46:29 PM PDT 24
Peak memory 205596 kb
Host smart-447a6e40-18be-411e-a731-f183aba77d01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820707450 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all_with_rand_reset.3820707450
Directory /workspace/47.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.3447866464
Short name T443
Test name
Test status
Simulation time 364534323311 ps
CPU time 170.97 seconds
Started Jul 16 04:40:43 PM PDT 24
Finished Jul 16 04:43:35 PM PDT 24
Peak memory 182756 kb
Host smart-4e562e50-bf29-4ed4-8aa7-7cb9786cef7e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447866464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.3447866464
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.2127707294
Short name T392
Test name
Test status
Simulation time 352227629022 ps
CPU time 257.25 seconds
Started Jul 16 04:36:35 PM PDT 24
Finished Jul 16 04:40:52 PM PDT 24
Peak memory 182892 kb
Host smart-395338f9-20b8-493c-9b5a-0791c5ad256f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127707294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.2127707294
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.620255097
Short name T424
Test name
Test status
Simulation time 71273811556 ps
CPU time 62.37 seconds
Started Jul 16 04:39:59 PM PDT 24
Finished Jul 16 04:41:02 PM PDT 24
Peak memory 190836 kb
Host smart-ee3430a7-fe92-42c8-8174-3115e025a94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620255097 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.620255097
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.4197077146
Short name T280
Test name
Test status
Simulation time 214628388436 ps
CPU time 346.2 seconds
Started Jul 16 04:36:46 PM PDT 24
Finished Jul 16 04:42:33 PM PDT 24
Peak memory 182788 kb
Host smart-8afd3cd5-136d-495e-978c-36f0f39e6499
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197077146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.4197077146
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.1830043524
Short name T5
Test name
Test status
Simulation time 64392284212 ps
CPU time 96.12 seconds
Started Jul 16 04:39:51 PM PDT 24
Finished Jul 16 04:41:28 PM PDT 24
Peak memory 181740 kb
Host smart-97836296-1c63-4983-841f-5562ae9a279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830043524 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.1830043524
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1796309829
Short name T12
Test name
Test status
Simulation time 2042457307 ps
CPU time 3.84 seconds
Started Jul 16 04:40:26 PM PDT 24
Finished Jul 16 04:40:31 PM PDT 24
Peak memory 181616 kb
Host smart-777a04d9-a94e-4205-bf35-bec73cb63329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796309829 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1796309829
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3561633732
Short name T163
Test name
Test status
Simulation time 100505542716 ps
CPU time 161.33 seconds
Started Jul 16 04:35:41 PM PDT 24
Finished Jul 16 04:38:24 PM PDT 24
Peak memory 182680 kb
Host smart-ad1ad2e0-d316-4e92-83bd-b38e46e95e8b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561633732 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3561633732
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.1107558112
Short name T433
Test name
Test status
Simulation time 155429868220 ps
CPU time 62.08 seconds
Started Jul 16 04:35:34 PM PDT 24
Finished Jul 16 04:36:37 PM PDT 24
Peak memory 180408 kb
Host smart-302865c0-9f9a-4d7d-b916-5b54ae4e9f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107558112 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.1107558112
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.907087656
Short name T205
Test name
Test status
Simulation time 222054668307 ps
CPU time 112.09 seconds
Started Jul 16 04:35:34 PM PDT 24
Finished Jul 16 04:37:27 PM PDT 24
Peak memory 188812 kb
Host smart-a69ae49e-5896-49ab-ac15-95a0d735d6bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907087656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.907087656
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/50.rv_timer_random.985843848
Short name T180
Test name
Test status
Simulation time 183536535730 ps
CPU time 313.55 seconds
Started Jul 16 04:39:52 PM PDT 24
Finished Jul 16 04:45:06 PM PDT 24
Peak memory 193208 kb
Host smart-a86daf75-f25f-4f16-af86-5b21787791a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985843848 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.985843848
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3392460166
Short name T190
Test name
Test status
Simulation time 379789632635 ps
CPU time 772.29 seconds
Started Jul 16 04:39:51 PM PDT 24
Finished Jul 16 04:52:44 PM PDT 24
Peak memory 190152 kb
Host smart-d85d7b14-0e53-41b5-a8cc-92c90e119900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392460166 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3392460166
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.4124288854
Short name T417
Test name
Test status
Simulation time 90156884282 ps
CPU time 34.2 seconds
Started Jul 16 04:40:12 PM PDT 24
Finished Jul 16 04:40:47 PM PDT 24
Peak memory 182656 kb
Host smart-ade427a7-21e7-4aaf-b03a-56896bf96566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124288854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.4124288854
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.2404395820
Short name T420
Test name
Test status
Simulation time 231203545529 ps
CPU time 158.43 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:42:48 PM PDT 24
Peak memory 190704 kb
Host smart-70756d8a-5cc2-450d-9b99-c668aa43c644
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404395820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.2404395820
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2004583828
Short name T306
Test name
Test status
Simulation time 177826604728 ps
CPU time 334.19 seconds
Started Jul 16 04:39:52 PM PDT 24
Finished Jul 16 04:45:27 PM PDT 24
Peak memory 190776 kb
Host smart-db3b7486-3367-45ca-b35b-736481943ad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004583828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2004583828
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3862300342
Short name T246
Test name
Test status
Simulation time 19156100349 ps
CPU time 28.51 seconds
Started Jul 16 04:40:01 PM PDT 24
Finished Jul 16 04:40:30 PM PDT 24
Peak memory 182636 kb
Host smart-611af696-02c6-4587-823b-2bf7189cc82e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862300342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3862300342
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3963173690
Short name T127
Test name
Test status
Simulation time 49346725331 ps
CPU time 57.78 seconds
Started Jul 16 04:40:00 PM PDT 24
Finished Jul 16 04:40:59 PM PDT 24
Peak memory 190392 kb
Host smart-a60da51c-41c7-42be-874b-494519ef4fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963173690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3963173690
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.4043557317
Short name T317
Test name
Test status
Simulation time 22971107405 ps
CPU time 19.98 seconds
Started Jul 16 04:41:05 PM PDT 24
Finished Jul 16 04:41:25 PM PDT 24
Peak memory 182848 kb
Host smart-6d03f604-e980-4587-8201-0fc1daf501c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043557317 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.4043557317
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.1511480453
Short name T157
Test name
Test status
Simulation time 613154283988 ps
CPU time 398.59 seconds
Started Jul 16 04:40:02 PM PDT 24
Finished Jul 16 04:46:41 PM PDT 24
Peak memory 190816 kb
Host smart-fe874196-9769-4c6d-b9ab-2e0416ab103c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511480453 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.1511480453
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.3244699852
Short name T315
Test name
Test status
Simulation time 829644496364 ps
CPU time 443.75 seconds
Started Jul 16 04:36:48 PM PDT 24
Finished Jul 16 04:44:13 PM PDT 24
Peak memory 182828 kb
Host smart-7ba3fa43-6621-4c6f-9c52-4ce8aafc46c7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244699852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.3244699852
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.880959294
Short name T393
Test name
Test status
Simulation time 158986230811 ps
CPU time 64.83 seconds
Started Jul 16 04:37:45 PM PDT 24
Finished Jul 16 04:38:50 PM PDT 24
Peak memory 182856 kb
Host smart-9a9b05ea-9ee6-459a-a9db-821a2266fc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880959294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.880959294
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.61264893
Short name T277
Test name
Test status
Simulation time 153715122674 ps
CPU time 266.7 seconds
Started Jul 16 04:40:37 PM PDT 24
Finished Jul 16 04:45:04 PM PDT 24
Peak memory 190392 kb
Host smart-ec79a86f-fee5-4439-8b31-6795fd7142ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61264893 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.61264893
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.1484357204
Short name T25
Test name
Test status
Simulation time 1250719813 ps
CPU time 1.51 seconds
Started Jul 16 04:36:32 PM PDT 24
Finished Jul 16 04:36:34 PM PDT 24
Peak memory 182744 kb
Host smart-e2f5e515-ae88-4566-aea7-3562d2797cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484357204 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.1484357204
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.1489107382
Short name T162
Test name
Test status
Simulation time 1261209853640 ps
CPU time 767.08 seconds
Started Jul 16 04:36:48 PM PDT 24
Finished Jul 16 04:49:36 PM PDT 24
Peak memory 195636 kb
Host smart-8d77e657-b615-45ed-a84f-d3c26bb75306
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489107382 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
1489107382
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all_with_rand_reset.2058639841
Short name T45
Test name
Test status
Simulation time 251470742219 ps
CPU time 471.24 seconds
Started Jul 16 04:38:27 PM PDT 24
Finished Jul 16 04:46:18 PM PDT 24
Peak memory 197604 kb
Host smart-ddc6aab3-5709-497f-a660-c821a1400044
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058639841 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all_with_rand_reset.2058639841
Directory /workspace/6.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.1931580797
Short name T359
Test name
Test status
Simulation time 103138148735 ps
CPU time 88.82 seconds
Started Jul 16 04:36:49 PM PDT 24
Finished Jul 16 04:38:18 PM PDT 24
Peak memory 182992 kb
Host smart-b01d870c-4066-440b-a38a-20a45b3c05bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931580797 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.1931580797
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.1039876038
Short name T155
Test name
Test status
Simulation time 81736250886 ps
CPU time 247.64 seconds
Started Jul 16 04:36:45 PM PDT 24
Finished Jul 16 04:40:53 PM PDT 24
Peak memory 191096 kb
Host smart-d7d5f790-5fe3-4160-96ec-dbc1a8bb2b8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039876038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.1039876038
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.4207896844
Short name T351
Test name
Test status
Simulation time 201195023156 ps
CPU time 96.06 seconds
Started Jul 16 04:39:53 PM PDT 24
Finished Jul 16 04:41:31 PM PDT 24
Peak memory 181912 kb
Host smart-8596f112-c7e5-4a9c-b6dd-56f416312409
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207896844 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.4207896844
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.456972456
Short name T285
Test name
Test status
Simulation time 144561510297 ps
CPU time 244.95 seconds
Started Jul 16 04:38:27 PM PDT 24
Finished Jul 16 04:42:32 PM PDT 24
Peak memory 191156 kb
Host smart-09c97d6e-de44-44ac-b55f-5a913ac12b82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456972456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.456972456
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.949565811
Short name T336
Test name
Test status
Simulation time 382305433774 ps
CPU time 514.51 seconds
Started Jul 16 04:41:05 PM PDT 24
Finished Jul 16 04:49:40 PM PDT 24
Peak memory 191044 kb
Host smart-ee17dac1-dcc1-4137-aca3-bc0cd0cb46cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949565811 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.949565811
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.1089623689
Short name T197
Test name
Test status
Simulation time 282677735147 ps
CPU time 121.13 seconds
Started Jul 16 04:40:26 PM PDT 24
Finished Jul 16 04:42:28 PM PDT 24
Peak memory 189940 kb
Host smart-c44b5d4f-8bfe-4c0d-b3ca-f5d672e7f8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089623689 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.1089623689
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.4267052819
Short name T438
Test name
Test status
Simulation time 667129989455 ps
CPU time 378.47 seconds
Started Jul 16 04:39:53 PM PDT 24
Finished Jul 16 04:46:13 PM PDT 24
Peak memory 181748 kb
Host smart-7970b29e-cc27-4961-ba45-557fb169dd8c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267052819 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.4267052819
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.3212342802
Short name T439
Test name
Test status
Simulation time 29187492462 ps
CPU time 43.57 seconds
Started Jul 16 04:39:50 PM PDT 24
Finished Jul 16 04:40:34 PM PDT 24
Peak memory 181632 kb
Host smart-38055228-44d4-463e-aa2a-102464809ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212342802 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.3212342802
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.746508461
Short name T51
Test name
Test status
Simulation time 357319683253 ps
CPU time 440.57 seconds
Started Jul 16 04:35:09 PM PDT 24
Finished Jul 16 04:42:30 PM PDT 24
Peak memory 191096 kb
Host smart-1a0b4a89-58ff-49f0-b3e8-d0887ffdc08b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746508461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.746508461
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.1524562085
Short name T457
Test name
Test status
Simulation time 14995085618 ps
CPU time 24.91 seconds
Started Jul 16 04:39:50 PM PDT 24
Finished Jul 16 04:40:16 PM PDT 24
Peak memory 181648 kb
Host smart-cd397383-f07b-43f5-89c3-5c6c6f591142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524562085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.1524562085
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.1020160322
Short name T442
Test name
Test status
Simulation time 460713343289 ps
CPU time 642.78 seconds
Started Jul 16 04:40:08 PM PDT 24
Finished Jul 16 04:50:53 PM PDT 24
Peak memory 206608 kb
Host smart-79881130-d305-45e9-a994-f79f0773d08c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020160322 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.1020160322
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/70.rv_timer_random.2458315597
Short name T346
Test name
Test status
Simulation time 27147422648 ps
CPU time 37.07 seconds
Started Jul 16 04:40:01 PM PDT 24
Finished Jul 16 04:40:38 PM PDT 24
Peak memory 182616 kb
Host smart-fc2e4138-43fa-4c48-b215-80269532f64f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458315597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.2458315597
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/71.rv_timer_random.1650123222
Short name T240
Test name
Test status
Simulation time 351219355521 ps
CPU time 717.94 seconds
Started Jul 16 04:36:45 PM PDT 24
Finished Jul 16 04:48:43 PM PDT 24
Peak memory 191148 kb
Host smart-7f998f47-335d-49fb-99be-1c61009078e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650123222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.1650123222
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.1212969402
Short name T184
Test name
Test status
Simulation time 201843315857 ps
CPU time 2835.32 seconds
Started Jul 16 04:38:26 PM PDT 24
Finished Jul 16 05:25:42 PM PDT 24
Peak memory 191184 kb
Host smart-b2a444bb-31a8-4db3-bacd-4144fa775a94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212969402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.1212969402
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.2473012154
Short name T220
Test name
Test status
Simulation time 99664066360 ps
CPU time 173.04 seconds
Started Jul 16 04:40:15 PM PDT 24
Finished Jul 16 04:43:10 PM PDT 24
Peak memory 189696 kb
Host smart-a8858f9d-74b7-4607-8045-b136a7a80432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473012154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.2473012154
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.3680393470
Short name T65
Test name
Test status
Simulation time 68686914398 ps
CPU time 384.06 seconds
Started Jul 16 04:41:05 PM PDT 24
Finished Jul 16 04:47:29 PM PDT 24
Peak memory 191040 kb
Host smart-0e89a72d-0dc6-41e9-a500-0be6fb1d8b3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680393470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.3680393470
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.344292408
Short name T311
Test name
Test status
Simulation time 176460934844 ps
CPU time 197.74 seconds
Started Jul 16 04:41:05 PM PDT 24
Finished Jul 16 04:44:24 PM PDT 24
Peak memory 191044 kb
Host smart-f2f97a34-cd0b-4f61-a97e-039784cd5b0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344292408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.344292408
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.1030384171
Short name T54
Test name
Test status
Simulation time 53598436457 ps
CPU time 45.05 seconds
Started Jul 16 04:38:50 PM PDT 24
Finished Jul 16 04:39:36 PM PDT 24
Peak memory 191160 kb
Host smart-31d0d4e3-1190-4130-99e7-0e6ffdd01b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030384171 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.1030384171
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.1900950145
Short name T338
Test name
Test status
Simulation time 482106951228 ps
CPU time 260.77 seconds
Started Jul 16 04:40:18 PM PDT 24
Finished Jul 16 04:44:40 PM PDT 24
Peak memory 190796 kb
Host smart-86288a4a-df7d-49c2-9856-bc1696bc7b17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900950145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.1900950145
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1408304539
Short name T224
Test name
Test status
Simulation time 1198658958574 ps
CPU time 1101.29 seconds
Started Jul 16 04:40:42 PM PDT 24
Finished Jul 16 04:59:04 PM PDT 24
Peak memory 191096 kb
Host smart-97b1b1b4-969a-4398-8aed-3c71e9de1da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408304539 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1408304539
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.2316671318
Short name T27
Test name
Test status
Simulation time 39218587590 ps
CPU time 66.11 seconds
Started Jul 16 04:37:28 PM PDT 24
Finished Jul 16 04:38:35 PM PDT 24
Peak memory 182880 kb
Host smart-b15d0a7a-b997-425b-8caa-531c449ec406
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316671318 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.2316671318
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2026744459
Short name T389
Test name
Test status
Simulation time 311611832399 ps
CPU time 118.25 seconds
Started Jul 16 04:35:21 PM PDT 24
Finished Jul 16 04:37:20 PM PDT 24
Peak memory 183064 kb
Host smart-a4deb159-247f-4a6d-b769-904d06105c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026744459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2026744459
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.2353363298
Short name T232
Test name
Test status
Simulation time 359021130263 ps
CPU time 171.93 seconds
Started Jul 16 04:37:16 PM PDT 24
Finished Jul 16 04:40:09 PM PDT 24
Peak memory 191076 kb
Host smart-095375a5-3463-4c50-9db0-5d87798788a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353363298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.2353363298
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.178422718
Short name T144
Test name
Test status
Simulation time 219068569125 ps
CPU time 163.33 seconds
Started Jul 16 04:37:26 PM PDT 24
Finished Jul 16 04:40:10 PM PDT 24
Peak memory 182904 kb
Host smart-de4796d4-b5d5-471f-ba66-1e5f063f71e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178422718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.178422718
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/80.rv_timer_random.230935227
Short name T316
Test name
Test status
Simulation time 37069443959 ps
CPU time 188.65 seconds
Started Jul 16 04:39:54 PM PDT 24
Finished Jul 16 04:43:03 PM PDT 24
Peak memory 182592 kb
Host smart-cb42b039-22d3-4ae1-a4e0-19bd1bbd7fc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230935227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.230935227
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/default/81.rv_timer_random.2402019909
Short name T299
Test name
Test status
Simulation time 58251473602 ps
CPU time 31.49 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:40:41 PM PDT 24
Peak memory 182608 kb
Host smart-674f6c61-0cf9-43b3-b797-c90ee38407a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402019909 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.2402019909
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.963775194
Short name T302
Test name
Test status
Simulation time 165854904849 ps
CPU time 1236.81 seconds
Started Jul 16 04:39:53 PM PDT 24
Finished Jul 16 05:00:31 PM PDT 24
Peak memory 189284 kb
Host smart-7affc081-814c-403a-b9a1-5e85a11a1516
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963775194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.963775194
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.4031590867
Short name T448
Test name
Test status
Simulation time 1107166920870 ps
CPU time 668.06 seconds
Started Jul 16 04:36:49 PM PDT 24
Finished Jul 16 04:47:58 PM PDT 24
Peak memory 191060 kb
Host smart-dc437f6b-3c90-4996-aad6-f4ffd7cd51f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031590867 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.4031590867
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.2574933281
Short name T321
Test name
Test status
Simulation time 1265750241845 ps
CPU time 240.1 seconds
Started Jul 16 04:40:50 PM PDT 24
Finished Jul 16 04:44:51 PM PDT 24
Peak memory 190292 kb
Host smart-206bef92-5a1e-41ad-99a7-81c45f1fcbda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574933281 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.2574933281
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.1564569532
Short name T251
Test name
Test status
Simulation time 4289492583 ps
CPU time 6.75 seconds
Started Jul 16 04:40:05 PM PDT 24
Finished Jul 16 04:40:13 PM PDT 24
Peak memory 182608 kb
Host smart-d0deaa55-95f6-4cc6-a368-48f4472b4d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564569532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.1564569532
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.552368386
Short name T274
Test name
Test status
Simulation time 41380220513 ps
CPU time 59.75 seconds
Started Jul 16 04:39:53 PM PDT 24
Finished Jul 16 04:40:53 PM PDT 24
Peak memory 189188 kb
Host smart-8c523a2c-7e6d-44a8-b19d-50a97cce2d04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552368386 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.552368386
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.747599633
Short name T370
Test name
Test status
Simulation time 18367884111 ps
CPU time 26.94 seconds
Started Jul 16 04:40:07 PM PDT 24
Finished Jul 16 04:40:36 PM PDT 24
Peak memory 182664 kb
Host smart-10fdf362-112d-4ffd-a6ed-d42dac436494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747599633 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.747599633
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.2229067065
Short name T428
Test name
Test status
Simulation time 13317882746 ps
CPU time 22.58 seconds
Started Jul 16 04:36:16 PM PDT 24
Finished Jul 16 04:36:39 PM PDT 24
Peak memory 182952 kb
Host smart-5acce97a-27ca-4557-8ccd-9db87423f5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229067065 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.2229067065
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.1518434293
Short name T282
Test name
Test status
Simulation time 279002033633 ps
CPU time 84.62 seconds
Started Jul 16 04:40:08 PM PDT 24
Finished Jul 16 04:41:35 PM PDT 24
Peak memory 182684 kb
Host smart-eb731438-533b-4674-9b6a-22ccddb0a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518434293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.1518434293
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.1136292879
Short name T75
Test name
Test status
Simulation time 43614689 ps
CPU time 0.55 seconds
Started Jul 16 04:40:11 PM PDT 24
Finished Jul 16 04:40:13 PM PDT 24
Peak memory 182588 kb
Host smart-1cbdf183-b455-4eee-aed9-7d18ae93546f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136292879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.
1136292879
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/90.rv_timer_random.1936727872
Short name T269
Test name
Test status
Simulation time 64170064706 ps
CPU time 296.8 seconds
Started Jul 16 04:39:52 PM PDT 24
Finished Jul 16 04:44:49 PM PDT 24
Peak memory 190820 kb
Host smart-824f9a35-563c-4f8f-aef7-df49d507ca16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936727872 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.1936727872
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.48813910
Short name T227
Test name
Test status
Simulation time 188293841762 ps
CPU time 96.09 seconds
Started Jul 16 04:36:58 PM PDT 24
Finished Jul 16 04:38:35 PM PDT 24
Peak memory 191096 kb
Host smart-6996580f-f933-4ec3-8287-735c45e2252a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48813910 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.48813910
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.448747198
Short name T250
Test name
Test status
Simulation time 108541458431 ps
CPU time 133.77 seconds
Started Jul 16 04:39:48 PM PDT 24
Finished Jul 16 04:42:02 PM PDT 24
Peak memory 190744 kb
Host smart-3043de93-5fec-4086-93a0-aee8c2fc3f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448747198 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.448747198
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.2133822714
Short name T130
Test name
Test status
Simulation time 757535911572 ps
CPU time 350.89 seconds
Started Jul 16 04:39:37 PM PDT 24
Finished Jul 16 04:45:29 PM PDT 24
Peak memory 192504 kb
Host smart-ec27ee65-6ae3-4b0f-b4c1-f7b14ef59d47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133822714 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.2133822714
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.2959835048
Short name T217
Test name
Test status
Simulation time 218783729293 ps
CPU time 216.71 seconds
Started Jul 16 04:37:39 PM PDT 24
Finished Jul 16 04:41:16 PM PDT 24
Peak memory 191128 kb
Host smart-c5201019-53ec-4727-ac11-5ffec3706eb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959835048 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.2959835048
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.3603103155
Short name T268
Test name
Test status
Simulation time 59271333932 ps
CPU time 93.67 seconds
Started Jul 16 04:39:51 PM PDT 24
Finished Jul 16 04:41:26 PM PDT 24
Peak memory 189496 kb
Host smart-6cd2917c-9e15-42a4-b184-d81326d3e646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603103155 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.3603103155
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3312102673
Short name T348
Test name
Test status
Simulation time 127096408973 ps
CPU time 83.3 seconds
Started Jul 16 04:37:03 PM PDT 24
Finished Jul 16 04:38:27 PM PDT 24
Peak memory 182956 kb
Host smart-12caf80b-48ca-4ee6-8672-f6193d7aab2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312102673 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3312102673
Directory /workspace/98.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.2860583839
Short name T168
Test name
Test status
Simulation time 132301380698 ps
CPU time 224.94 seconds
Started Jul 16 04:39:37 PM PDT 24
Finished Jul 16 04:43:23 PM PDT 24
Peak memory 189532 kb
Host smart-1bfcd5c2-5b25-4449-b764-29439a3afc37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860583839 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.2860583839
Directory /workspace/99.rv_timer_random/latest
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