Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.57 99.36 98.73 100.00 100.00 100.00 99.32


Total test records in report: 580
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html
T510 /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4053120153 Jul 17 06:42:30 PM PDT 24 Jul 17 06:42:32 PM PDT 24 802569859 ps
T511 /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4112750139 Jul 17 06:42:41 PM PDT 24 Jul 17 06:42:44 PM PDT 24 44242316 ps
T512 /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1514657332 Jul 17 06:42:41 PM PDT 24 Jul 17 06:42:44 PM PDT 24 28589617 ps
T513 /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3944531488 Jul 17 06:42:40 PM PDT 24 Jul 17 06:42:42 PM PDT 24 16911924 ps
T514 /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.537449621 Jul 17 06:42:52 PM PDT 24 Jul 17 06:42:54 PM PDT 24 26975907 ps
T515 /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3575900352 Jul 17 06:42:27 PM PDT 24 Jul 17 06:42:29 PM PDT 24 297288342 ps
T516 /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2967699111 Jul 17 06:42:17 PM PDT 24 Jul 17 06:42:19 PM PDT 24 175753958 ps
T517 /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.43578175 Jul 17 06:42:42 PM PDT 24 Jul 17 06:42:47 PM PDT 24 81199772 ps
T518 /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2680378081 Jul 17 06:42:43 PM PDT 24 Jul 17 06:42:47 PM PDT 24 478331656 ps
T519 /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4050757767 Jul 17 06:42:17 PM PDT 24 Jul 17 06:42:21 PM PDT 24 217650780 ps
T520 /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3319582066 Jul 17 06:42:42 PM PDT 24 Jul 17 06:42:46 PM PDT 24 219633781 ps
T521 /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1393737006 Jul 17 06:42:43 PM PDT 24 Jul 17 06:42:47 PM PDT 24 66828782 ps
T78 /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1212410609 Jul 17 06:42:06 PM PDT 24 Jul 17 06:42:08 PM PDT 24 59125414 ps
T522 /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2899750078 Jul 17 06:41:58 PM PDT 24 Jul 17 06:42:00 PM PDT 24 46105525 ps
T523 /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.959094715 Jul 17 06:41:57 PM PDT 24 Jul 17 06:41:59 PM PDT 24 58574445 ps
T79 /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.268326099 Jul 17 06:42:43 PM PDT 24 Jul 17 06:42:47 PM PDT 24 33643173 ps
T524 /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3882928247 Jul 17 06:42:28 PM PDT 24 Jul 17 06:42:30 PM PDT 24 79397206 ps
T525 /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3723170530 Jul 17 06:41:56 PM PDT 24 Jul 17 06:41:59 PM PDT 24 36913876 ps
T526 /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.4183493796 Jul 17 06:42:20 PM PDT 24 Jul 17 06:42:21 PM PDT 24 18514772 ps
T527 /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2056634756 Jul 17 06:42:16 PM PDT 24 Jul 17 06:42:18 PM PDT 24 85694451 ps
T528 /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3479911423 Jul 17 06:42:41 PM PDT 24 Jul 17 06:42:45 PM PDT 24 29056965 ps
T529 /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.521366708 Jul 17 06:42:41 PM PDT 24 Jul 17 06:42:43 PM PDT 24 24601921 ps
T530 /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1584185718 Jul 17 06:42:39 PM PDT 24 Jul 17 06:42:42 PM PDT 24 221091873 ps
T531 /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4241340683 Jul 17 06:42:00 PM PDT 24 Jul 17 06:42:02 PM PDT 24 59281102 ps
T80 /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.447227903 Jul 17 06:42:40 PM PDT 24 Jul 17 06:42:43 PM PDT 24 58303656 ps
T532 /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.961874294 Jul 17 06:42:32 PM PDT 24 Jul 17 06:42:33 PM PDT 24 51439111 ps
T533 /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2833729869 Jul 17 06:42:06 PM PDT 24 Jul 17 06:42:08 PM PDT 24 38889007 ps
T81 /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3675283073 Jul 17 06:41:55 PM PDT 24 Jul 17 06:41:57 PM PDT 24 40294063 ps
T99 /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1215842402 Jul 17 06:42:15 PM PDT 24 Jul 17 06:42:17 PM PDT 24 97998796 ps
T534 /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3107334929 Jul 17 06:41:58 PM PDT 24 Jul 17 06:42:00 PM PDT 24 179909610 ps
T535 /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1756825179 Jul 17 06:42:40 PM PDT 24 Jul 17 06:42:42 PM PDT 24 13320757 ps
T536 /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1200177897 Jul 17 06:42:08 PM PDT 24 Jul 17 06:42:10 PM PDT 24 38711456 ps
T537 /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.32528440 Jul 17 06:42:42 PM PDT 24 Jul 17 06:42:47 PM PDT 24 84403724 ps
T538 /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2874092690 Jul 17 06:42:43 PM PDT 24 Jul 17 06:42:47 PM PDT 24 115188992 ps
T539 /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4164228700 Jul 17 06:42:40 PM PDT 24 Jul 17 06:42:42 PM PDT 24 26023455 ps
T540 /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4216451214 Jul 17 06:42:07 PM PDT 24 Jul 17 06:42:10 PM PDT 24 188040904 ps
T541 /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.592170353 Jul 17 06:42:52 PM PDT 24 Jul 17 06:42:54 PM PDT 24 121607147 ps
T542 /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3566619328 Jul 17 06:42:06 PM PDT 24 Jul 17 06:42:08 PM PDT 24 71700399 ps
T543 /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1482038890 Jul 17 06:42:16 PM PDT 24 Jul 17 06:42:18 PM PDT 24 25562553 ps
T84 /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.535379422 Jul 17 06:42:06 PM PDT 24 Jul 17 06:42:08 PM PDT 24 19796390 ps
T544 /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1254731104 Jul 17 06:41:56 PM PDT 24 Jul 17 06:41:58 PM PDT 24 12929795 ps
T545 /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2537694010 Jul 17 06:41:56 PM PDT 24 Jul 17 06:41:58 PM PDT 24 34511866 ps
T546 /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1547746253 Jul 17 06:42:27 PM PDT 24 Jul 17 06:42:31 PM PDT 24 277221074 ps
T547 /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2380915032 Jul 17 06:41:55 PM PDT 24 Jul 17 06:41:57 PM PDT 24 53747696 ps
T548 /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3779265747 Jul 17 06:42:29 PM PDT 24 Jul 17 06:42:31 PM PDT 24 38750008 ps
T549 /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.697031088 Jul 17 06:42:15 PM PDT 24 Jul 17 06:42:17 PM PDT 24 54559085 ps
T550 /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.700242739 Jul 17 06:42:16 PM PDT 24 Jul 17 06:42:20 PM PDT 24 138044478 ps
T551 /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2206608957 Jul 17 06:41:58 PM PDT 24 Jul 17 06:42:03 PM PDT 24 719773367 ps
T552 /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1859518509 Jul 17 06:42:15 PM PDT 24 Jul 17 06:42:17 PM PDT 24 70735949 ps
T82 /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1676724222 Jul 17 06:42:44 PM PDT 24 Jul 17 06:42:48 PM PDT 24 17421212 ps
T553 /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.508287063 Jul 17 06:41:56 PM PDT 24 Jul 17 06:41:58 PM PDT 24 476083148 ps
T554 /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2067985841 Jul 17 06:42:40 PM PDT 24 Jul 17 06:42:41 PM PDT 24 51520678 ps
T555 /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.210677564 Jul 17 06:42:16 PM PDT 24 Jul 17 06:42:18 PM PDT 24 45506512 ps
T556 /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.619977342 Jul 17 06:42:42 PM PDT 24 Jul 17 06:42:47 PM PDT 24 12859810 ps
T557 /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.640267297 Jul 17 06:42:16 PM PDT 24 Jul 17 06:42:20 PM PDT 24 115199480 ps
T558 /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.734959223 Jul 17 06:42:42 PM PDT 24 Jul 17 06:42:46 PM PDT 24 15566091 ps
T559 /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2692787341 Jul 17 06:42:28 PM PDT 24 Jul 17 06:42:32 PM PDT 24 473164157 ps
T560 /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.648247091 Jul 17 06:42:40 PM PDT 24 Jul 17 06:42:41 PM PDT 24 69279494 ps
T561 /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.310379005 Jul 17 06:42:41 PM PDT 24 Jul 17 06:42:44 PM PDT 24 43673404 ps
T562 /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3508107838 Jul 17 06:42:43 PM PDT 24 Jul 17 06:42:47 PM PDT 24 33714206 ps
T83 /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2225183790 Jul 17 06:41:58 PM PDT 24 Jul 17 06:42:00 PM PDT 24 67669377 ps
T563 /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2932682315 Jul 17 06:42:42 PM PDT 24 Jul 17 06:42:47 PM PDT 24 19867234 ps
T564 /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1400935153 Jul 17 06:42:08 PM PDT 24 Jul 17 06:42:10 PM PDT 24 325668412 ps
T565 /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1466899408 Jul 17 06:42:16 PM PDT 24 Jul 17 06:42:17 PM PDT 24 58218277 ps
T566 /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3014007464 Jul 17 06:42:15 PM PDT 24 Jul 17 06:42:17 PM PDT 24 73723126 ps
T567 /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2449465173 Jul 17 06:42:06 PM PDT 24 Jul 17 06:42:09 PM PDT 24 206318380 ps
T568 /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2171267540 Jul 17 06:42:40 PM PDT 24 Jul 17 06:42:41 PM PDT 24 63562419 ps
T569 /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2566004550 Jul 17 06:42:16 PM PDT 24 Jul 17 06:42:19 PM PDT 24 411321053 ps
T570 /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2733833694 Jul 17 06:42:08 PM PDT 24 Jul 17 06:42:10 PM PDT 24 136713726 ps
T571 /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1417051873 Jul 17 06:41:56 PM PDT 24 Jul 17 06:42:01 PM PDT 24 337814014 ps
T572 /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.771660093 Jul 17 06:42:07 PM PDT 24 Jul 17 06:42:09 PM PDT 24 16347035 ps
T573 /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2591243252 Jul 17 06:42:00 PM PDT 24 Jul 17 06:42:01 PM PDT 24 47832541 ps
T574 /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.36350793 Jul 17 06:42:30 PM PDT 24 Jul 17 06:42:32 PM PDT 24 29848728 ps
T575 /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2071102862 Jul 17 06:42:17 PM PDT 24 Jul 17 06:42:19 PM PDT 24 127677187 ps
T576 /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.4234506513 Jul 17 06:42:29 PM PDT 24 Jul 17 06:42:33 PM PDT 24 130485215 ps
T85 /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1005713130 Jul 17 06:42:05 PM PDT 24 Jul 17 06:42:07 PM PDT 24 25862858 ps
T577 /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2416145156 Jul 17 06:42:32 PM PDT 24 Jul 17 06:42:34 PM PDT 24 121122553 ps
T578 /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4254685116 Jul 17 06:42:00 PM PDT 24 Jul 17 06:42:05 PM PDT 24 1181013209 ps
T579 /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1916722101 Jul 17 06:41:56 PM PDT 24 Jul 17 06:41:58 PM PDT 24 19368801 ps
T580 /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.697744426 Jul 17 06:42:43 PM PDT 24 Jul 17 06:42:47 PM PDT 24 443645497 ps

Test location /workspace/coverage/default/29.rv_timer_cfg_update_on_fly.1652026321
Short name T4
Test name
Test status
Simulation time 163715237684 ps
CPU time 282.56 seconds
Started Jul 17 06:43:27 PM PDT 24
Finished Jul 17 06:48:12 PM PDT 24
Peak memory 183132 kb
Host smart-eadcf8cb-f4e5-4aea-8b86-731df9ffc2f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652026321 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.rv_timer_cfg_update_on_fly.1652026321
Directory /workspace/29.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all_with_rand_reset.3872001149
Short name T11
Test name
Test status
Simulation time 110270338811 ps
CPU time 434.27 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:50:43 PM PDT 24
Peak memory 197812 kb
Host smart-bfadfdf4-6983-4b0c-a65b-5b2f5dc7f0d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872001149 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all_with_rand_reset.3872001149
Directory /workspace/27.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all.3361385370
Short name T103
Test name
Test status
Simulation time 3170919167121 ps
CPU time 2233.71 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 07:20:18 PM PDT 24
Peak memory 195532 kb
Host smart-2eb442bd-a99d-4fdb-88de-d3767c0cc16f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361385370 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all
.3361385370
Directory /workspace/15.rv_timer_stress_all/latest

Test location /workspace/coverage/default/0.rv_timer_sec_cm.4100231776
Short name T14
Test name
Test status
Simulation time 37567806 ps
CPU time 0.79 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:42:56 PM PDT 24
Peak memory 213420 kb
Host smart-74ada535-f69a-40ea-968b-840745bf310e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100231776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_sec_cm.4100231776
Directory /workspace/0.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/19.rv_timer_stress_all.3439218201
Short name T121
Test name
Test status
Simulation time 1576275169370 ps
CPU time 1130.1 seconds
Started Jul 17 06:43:14 PM PDT 24
Finished Jul 17 07:02:06 PM PDT 24
Peak memory 191340 kb
Host smart-a5def0ca-9554-4851-9dac-4c58e267aefd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439218201 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_stress_all
.3439218201
Directory /workspace/19.rv_timer_stress_all/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all.1037767314
Short name T113
Test name
Test status
Simulation time 2086093983086 ps
CPU time 4645.25 seconds
Started Jul 17 06:43:45 PM PDT 24
Finished Jul 17 08:01:11 PM PDT 24
Peak memory 191284 kb
Host smart-e82cff68-e3cd-4023-b7b0-00eac0e3c6cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037767314 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all
.1037767314
Directory /workspace/39.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all.2612507469
Short name T210
Test name
Test status
Simulation time 1086490579079 ps
CPU time 1272.58 seconds
Started Jul 17 06:44:03 PM PDT 24
Finished Jul 17 07:05:18 PM PDT 24
Peak memory 194128 kb
Host smart-1157ef37-2011-4657-a36d-76326fcf954e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612507469 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all
.2612507469
Directory /workspace/43.rv_timer_stress_all/latest

Test location /workspace/coverage/default/34.rv_timer_stress_all.1752588990
Short name T9
Test name
Test status
Simulation time 914148049569 ps
CPU time 1560.64 seconds
Started Jul 17 06:43:37 PM PDT 24
Finished Jul 17 07:09:40 PM PDT 24
Peak memory 191296 kb
Host smart-8cd4c0f4-cee6-4c22-9cac-ec044e5ffcc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752588990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_stress_all
.1752588990
Directory /workspace/34.rv_timer_stress_all/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all.2070486057
Short name T258
Test name
Test status
Simulation time 559535296785 ps
CPU time 2174.81 seconds
Started Jul 17 06:42:55 PM PDT 24
Finished Jul 17 07:19:11 PM PDT 24
Peak memory 191332 kb
Host smart-0772496c-37bd-4d53-b516-b6ceca2bc604
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070486057 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all.
2070486057
Directory /workspace/7.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_stress_all.2307791916
Short name T185
Test name
Test status
Simulation time 2393662454294 ps
CPU time 2236.77 seconds
Started Jul 17 06:43:13 PM PDT 24
Finished Jul 17 07:20:32 PM PDT 24
Peak memory 191424 kb
Host smart-e258cbab-5f76-457a-9c0b-2ae10c4b4986
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307791916 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_stress_all
.2307791916
Directory /workspace/20.rv_timer_stress_all/latest

Test location /workspace/coverage/default/6.rv_timer_stress_all.4254566996
Short name T114
Test name
Test status
Simulation time 711694756486 ps
CPU time 1766.89 seconds
Started Jul 17 06:42:58 PM PDT 24
Finished Jul 17 07:12:25 PM PDT 24
Peak memory 191500 kb
Host smart-449dd86a-abdd-44a0-945a-af2b10f9f73a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254566996 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_stress_all.
4254566996
Directory /workspace/6.rv_timer_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_intg_err.1620120254
Short name T28
Test name
Test status
Simulation time 1769100674 ps
CPU time 1.4 seconds
Started Jul 17 06:42:06 PM PDT 24
Finished Jul 17 06:42:09 PM PDT 24
Peak memory 195164 kb
Host smart-59e143fd-b620-4ce5-8da3-6b6c7510f8e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620120254 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_in
tg_err.1620120254
Directory /workspace/1.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_bit_bash.4165654578
Short name T74
Test name
Test status
Simulation time 634140262 ps
CPU time 3.16 seconds
Started Jul 17 06:41:56 PM PDT 24
Finished Jul 17 06:42:00 PM PDT 24
Peak memory 190824 kb
Host smart-ad57513d-e8f4-424e-9c36-776005ebfd26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165654578 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_bit_
bash.4165654578
Directory /workspace/1.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/default/10.rv_timer_stress_all.326108143
Short name T249
Test name
Test status
Simulation time 591751817325 ps
CPU time 5255.63 seconds
Started Jul 17 06:43:03 PM PDT 24
Finished Jul 17 08:10:41 PM PDT 24
Peak memory 196292 kb
Host smart-6bcc0fa3-c342-4933-ae08-62c953d168cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326108143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_stress_all.
326108143
Directory /workspace/10.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_stress_all.1402988768
Short name T21
Test name
Test status
Simulation time 324967159698 ps
CPU time 1035.08 seconds
Started Jul 17 06:43:27 PM PDT 24
Finished Jul 17 07:00:45 PM PDT 24
Peak memory 195984 kb
Host smart-a7c90410-5cdd-44cb-9662-a9cbcd8f9f45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402988768 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_stress_all
.1402988768
Directory /workspace/24.rv_timer_stress_all/latest

Test location /workspace/coverage/default/27.rv_timer_stress_all.369376532
Short name T221
Test name
Test status
Simulation time 865551728523 ps
CPU time 1231.17 seconds
Started Jul 17 06:43:24 PM PDT 24
Finished Jul 17 07:03:56 PM PDT 24
Peak memory 191332 kb
Host smart-5f275b81-df94-4989-aa50-59b118eb53e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369376532 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_stress_all.
369376532
Directory /workspace/27.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_stress_all.3758811054
Short name T234
Test name
Test status
Simulation time 1196744138436 ps
CPU time 1258.12 seconds
Started Jul 17 06:44:14 PM PDT 24
Finished Jul 17 07:05:14 PM PDT 24
Peak memory 195680 kb
Host smart-3b2714b8-1d61-493b-8979-10dfb2c27047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758811054 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_stress_all
.3758811054
Directory /workspace/45.rv_timer_stress_all/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all.3464382278
Short name T186
Test name
Test status
Simulation time 360984648007 ps
CPU time 1253.3 seconds
Started Jul 17 06:43:27 PM PDT 24
Finished Jul 17 07:04:23 PM PDT 24
Peak memory 191280 kb
Host smart-1f3d1aec-9def-4dae-ace6-ccfb1ac95783
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464382278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all
.3464382278
Directory /workspace/28.rv_timer_stress_all/latest

Test location /workspace/coverage/default/46.rv_timer_stress_all.4200549046
Short name T214
Test name
Test status
Simulation time 6481026020001 ps
CPU time 1615.72 seconds
Started Jul 17 06:44:15 PM PDT 24
Finished Jul 17 07:11:12 PM PDT 24
Peak memory 191340 kb
Host smart-f966d7e2-3a81-40cf-a979-dc4933495b8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200549046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_stress_all
.4200549046
Directory /workspace/46.rv_timer_stress_all/latest

Test location /workspace/coverage/default/13.rv_timer_stress_all.3385096858
Short name T349
Test name
Test status
Simulation time 742835168090 ps
CPU time 1730.12 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 07:11:53 PM PDT 24
Peak memory 191340 kb
Host smart-8bc6f667-2b35-4b86-8850-6c3714751239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385096858 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_stress_all
.3385096858
Directory /workspace/13.rv_timer_stress_all/latest

Test location /workspace/coverage/default/12.rv_timer_random.2475014159
Short name T242
Test name
Test status
Simulation time 1687245874543 ps
CPU time 529.67 seconds
Started Jul 17 06:43:05 PM PDT 24
Finished Jul 17 06:51:57 PM PDT 24
Peak memory 191292 kb
Host smart-521adfac-5e3d-4342-a5e6-6c3b5cecf0f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475014159 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random.2475014159
Directory /workspace/12.rv_timer_random/latest

Test location /workspace/coverage/default/142.rv_timer_random.4247845609
Short name T145
Test name
Test status
Simulation time 1782294615649 ps
CPU time 682.15 seconds
Started Jul 17 06:45:58 PM PDT 24
Finished Jul 17 06:57:20 PM PDT 24
Peak memory 191340 kb
Host smart-2b3daa91-a2cb-4c67-b1cd-208ebaca4bca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247845609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.rv_timer_random.4247845609
Directory /workspace/142.rv_timer_random/latest

Test location /workspace/coverage/default/84.rv_timer_random.1579028549
Short name T178
Test name
Test status
Simulation time 181417364452 ps
CPU time 619.13 seconds
Started Jul 17 06:44:48 PM PDT 24
Finished Jul 17 06:55:08 PM PDT 24
Peak memory 191264 kb
Host smart-9ba23c93-39ec-4c38-9945-a1dd5fac394e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579028549 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.rv_timer_random.1579028549
Directory /workspace/84.rv_timer_random/latest

Test location /workspace/coverage/default/110.rv_timer_random.2842647761
Short name T204
Test name
Test status
Simulation time 648637547863 ps
CPU time 713.24 seconds
Started Jul 17 06:45:22 PM PDT 24
Finished Jul 17 06:57:16 PM PDT 24
Peak memory 191336 kb
Host smart-031c501f-bbd2-47fc-b191-739f6ecf9a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842647761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.rv_timer_random.2842647761
Directory /workspace/110.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_stress_all.743643497
Short name T244
Test name
Test status
Simulation time 283538672621 ps
CPU time 237.88 seconds
Started Jul 17 06:43:03 PM PDT 24
Finished Jul 17 06:47:04 PM PDT 24
Peak memory 193452 kb
Host smart-aaed1cae-7607-4c5e-9c38-28ad00d2547e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743643497 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_stress_all.
743643497
Directory /workspace/14.rv_timer_stress_all/latest

Test location /workspace/coverage/default/154.rv_timer_random.214226221
Short name T66
Test name
Test status
Simulation time 160081851102 ps
CPU time 1697.52 seconds
Started Jul 17 06:46:10 PM PDT 24
Finished Jul 17 07:14:29 PM PDT 24
Peak memory 191340 kb
Host smart-9c74d9b4-84f2-4875-8ef4-1f6e5c585a4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214226221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.rv_timer_random.214226221
Directory /workspace/154.rv_timer_random/latest

Test location /workspace/coverage/default/115.rv_timer_random.3622929243
Short name T170
Test name
Test status
Simulation time 809291409096 ps
CPU time 668.54 seconds
Started Jul 17 06:45:21 PM PDT 24
Finished Jul 17 06:56:30 PM PDT 24
Peak memory 191304 kb
Host smart-a323d106-f0e8-4d63-aa7e-cb164d6bcda7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622929243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.rv_timer_random.3622929243
Directory /workspace/115.rv_timer_random/latest

Test location /workspace/coverage/default/116.rv_timer_random.1811181942
Short name T136
Test name
Test status
Simulation time 122295794045 ps
CPU time 187.11 seconds
Started Jul 17 06:45:21 PM PDT 24
Finished Jul 17 06:48:29 PM PDT 24
Peak memory 191352 kb
Host smart-bab133ef-c001-43fb-9b00-ef717c966136
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811181942 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.rv_timer_random.1811181942
Directory /workspace/116.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_stress_all.212482627
Short name T164
Test name
Test status
Simulation time 438924852754 ps
CPU time 899.21 seconds
Started Jul 17 06:43:28 PM PDT 24
Finished Jul 17 06:58:29 PM PDT 24
Peak memory 191348 kb
Host smart-e7b727f6-1d27-437e-8585-ea3d8592734b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212482627 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_stress_all.
212482627
Directory /workspace/26.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_random.679073656
Short name T265
Test name
Test status
Simulation time 733219783902 ps
CPU time 673.19 seconds
Started Jul 17 06:43:46 PM PDT 24
Finished Jul 17 06:55:00 PM PDT 24
Peak memory 191332 kb
Host smart-19d011c2-53b6-452f-86ae-45f3373ba28e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679073656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random.679073656
Directory /workspace/35.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_same_csr_outstanding.1375475951
Short name T69
Test name
Test status
Simulation time 80028098 ps
CPU time 0.68 seconds
Started Jul 17 06:42:27 PM PDT 24
Finished Jul 17 06:42:29 PM PDT 24
Peak memory 191456 kb
Host smart-d0710237-1a89-4375-80bf-a40838e73cd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375475951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_t
imer_same_csr_outstanding.1375475951
Directory /workspace/12.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/default/157.rv_timer_random.4216027922
Short name T175
Test name
Test status
Simulation time 145948307564 ps
CPU time 685.4 seconds
Started Jul 17 06:46:10 PM PDT 24
Finished Jul 17 06:57:37 PM PDT 24
Peak memory 191344 kb
Host smart-0de0939b-344b-4446-9ff5-8875b0254720
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216027922 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.rv_timer_random.4216027922
Directory /workspace/157.rv_timer_random/latest

Test location /workspace/coverage/default/25.rv_timer_random.414105385
Short name T149
Test name
Test status
Simulation time 159469373205 ps
CPU time 298.57 seconds
Started Jul 17 06:43:24 PM PDT 24
Finished Jul 17 06:48:24 PM PDT 24
Peak memory 193388 kb
Host smart-eecea8f9-823f-41be-88f1-73644e400ab8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414105385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random.414105385
Directory /workspace/25.rv_timer_random/latest

Test location /workspace/coverage/default/37.rv_timer_random.3752503208
Short name T157
Test name
Test status
Simulation time 541083007046 ps
CPU time 2340.98 seconds
Started Jul 17 06:43:38 PM PDT 24
Finished Jul 17 07:22:41 PM PDT 24
Peak memory 191336 kb
Host smart-674f84cb-1285-4d40-99c0-452e299d1e92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752503208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random.3752503208
Directory /workspace/37.rv_timer_random/latest

Test location /workspace/coverage/default/70.rv_timer_random.3508125437
Short name T312
Test name
Test status
Simulation time 84396560965 ps
CPU time 242.69 seconds
Started Jul 17 06:44:36 PM PDT 24
Finished Jul 17 06:48:39 PM PDT 24
Peak memory 191344 kb
Host smart-5fd3b3f1-3152-420f-b52a-0ec7c80702e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508125437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.rv_timer_random.3508125437
Directory /workspace/70.rv_timer_random/latest

Test location /workspace/coverage/default/114.rv_timer_random.2694671510
Short name T305
Test name
Test status
Simulation time 1053792137514 ps
CPU time 848.98 seconds
Started Jul 17 06:45:21 PM PDT 24
Finished Jul 17 06:59:31 PM PDT 24
Peak memory 191500 kb
Host smart-be41c939-84c5-498c-a4cf-c7594d33b970
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694671510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.rv_timer_random.2694671510
Directory /workspace/114.rv_timer_random/latest

Test location /workspace/coverage/default/131.rv_timer_random.2581907816
Short name T123
Test name
Test status
Simulation time 926460230540 ps
CPU time 587.66 seconds
Started Jul 17 06:45:44 PM PDT 24
Finished Jul 17 06:55:33 PM PDT 24
Peak memory 191344 kb
Host smart-5d99d81b-f6a9-4636-a5c6-37dcb4fc4dec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581907816 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.rv_timer_random.2581907816
Directory /workspace/131.rv_timer_random/latest

Test location /workspace/coverage/default/138.rv_timer_random.1098132540
Short name T160
Test name
Test status
Simulation time 134462944930 ps
CPU time 247.52 seconds
Started Jul 17 06:45:55 PM PDT 24
Finished Jul 17 06:50:03 PM PDT 24
Peak memory 191332 kb
Host smart-a46df392-cfa2-4e32-b882-4911480acae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098132540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.rv_timer_random.1098132540
Directory /workspace/138.rv_timer_random/latest

Test location /workspace/coverage/default/168.rv_timer_random.4188538880
Short name T316
Test name
Test status
Simulation time 517496598261 ps
CPU time 318.7 seconds
Started Jul 17 06:46:20 PM PDT 24
Finished Jul 17 06:51:39 PM PDT 24
Peak memory 191284 kb
Host smart-461e9d0c-235f-4c28-9454-1dc329bd0c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188538880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.rv_timer_random.4188538880
Directory /workspace/168.rv_timer_random/latest

Test location /workspace/coverage/default/171.rv_timer_random.1533801621
Short name T5
Test name
Test status
Simulation time 300277766706 ps
CPU time 286.93 seconds
Started Jul 17 06:46:23 PM PDT 24
Finished Jul 17 06:51:10 PM PDT 24
Peak memory 191348 kb
Host smart-014ad132-51e2-4349-bc37-f5e0b045c751
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533801621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.rv_timer_random.1533801621
Directory /workspace/171.rv_timer_random/latest

Test location /workspace/coverage/default/174.rv_timer_random.2287259555
Short name T104
Test name
Test status
Simulation time 505700228090 ps
CPU time 653.51 seconds
Started Jul 17 06:46:22 PM PDT 24
Finished Jul 17 06:57:17 PM PDT 24
Peak memory 191348 kb
Host smart-12247f8c-ba2e-4571-b480-b54bc64da010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287259555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.rv_timer_random.2287259555
Directory /workspace/174.rv_timer_random/latest

Test location /workspace/coverage/default/175.rv_timer_random.633344203
Short name T191
Test name
Test status
Simulation time 123808411879 ps
CPU time 307.81 seconds
Started Jul 17 06:46:20 PM PDT 24
Finished Jul 17 06:51:29 PM PDT 24
Peak memory 191336 kb
Host smart-c7cb2a72-4015-4512-b224-47b4db3970fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633344203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.rv_timer_random.633344203
Directory /workspace/175.rv_timer_random/latest

Test location /workspace/coverage/default/44.rv_timer_random.616891631
Short name T167
Test name
Test status
Simulation time 142311619668 ps
CPU time 477.22 seconds
Started Jul 17 06:44:02 PM PDT 24
Finished Jul 17 06:52:01 PM PDT 24
Peak memory 191352 kb
Host smart-b40015a0-d2a7-47b3-8088-939942ee7bcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616891631 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random.616891631
Directory /workspace/44.rv_timer_random/latest

Test location /workspace/coverage/default/0.rv_timer_stress_all.1554913350
Short name T200
Test name
Test status
Simulation time 372603644201 ps
CPU time 1597.34 seconds
Started Jul 17 06:42:51 PM PDT 24
Finished Jul 17 07:09:29 PM PDT 24
Peak memory 183080 kb
Host smart-88b2c731-5855-4495-ad7f-637605cfed2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554913350 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_stress_all.
1554913350
Directory /workspace/0.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_random_reset.2939360716
Short name T340
Test name
Test status
Simulation time 400221396293 ps
CPU time 265.8 seconds
Started Jul 17 06:43:04 PM PDT 24
Finished Jul 17 06:47:32 PM PDT 24
Peak memory 195236 kb
Host smart-07608195-6cdc-4c78-a340-804fa11dd49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939360716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random_reset.2939360716
Directory /workspace/10.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_random.1068106341
Short name T108
Test name
Test status
Simulation time 390349254980 ps
CPU time 215.99 seconds
Started Jul 17 06:43:04 PM PDT 24
Finished Jul 17 06:46:42 PM PDT 24
Peak memory 193732 kb
Host smart-0ec0c6b3-22de-4e82-b716-76cf13dd1eb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068106341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random.1068106341
Directory /workspace/11.rv_timer_random/latest

Test location /workspace/coverage/default/111.rv_timer_random.1889031140
Short name T247
Test name
Test status
Simulation time 1902624116131 ps
CPU time 2739.17 seconds
Started Jul 17 06:45:23 PM PDT 24
Finished Jul 17 07:31:03 PM PDT 24
Peak memory 191540 kb
Host smart-d7b45cf2-eeb7-4281-83d9-ca4b35181c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889031140 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.rv_timer_random.1889031140
Directory /workspace/111.rv_timer_random/latest

Test location /workspace/coverage/default/169.rv_timer_random.407414473
Short name T287
Test name
Test status
Simulation time 74390650607 ps
CPU time 115.97 seconds
Started Jul 17 06:46:22 PM PDT 24
Finished Jul 17 06:48:18 PM PDT 24
Peak memory 191340 kb
Host smart-4cdc44bf-2f97-4d6d-b16c-f9c44d32b32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407414473 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.rv_timer_random.407414473
Directory /workspace/169.rv_timer_random/latest

Test location /workspace/coverage/default/191.rv_timer_random.2014597102
Short name T224
Test name
Test status
Simulation time 548529272124 ps
CPU time 945.22 seconds
Started Jul 17 06:46:43 PM PDT 24
Finished Jul 17 07:02:29 PM PDT 24
Peak memory 191288 kb
Host smart-74db0817-6acf-4aa9-a299-fe7963644f98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014597102 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.rv_timer_random.2014597102
Directory /workspace/191.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_stress_all.1211995116
Short name T270
Test name
Test status
Simulation time 62178850273 ps
CPU time 116.56 seconds
Started Jul 17 06:43:14 PM PDT 24
Finished Jul 17 06:45:13 PM PDT 24
Peak memory 191340 kb
Host smart-b8c1b3e4-8805-4875-83f0-88d845a9bd45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211995116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_stress_all
.1211995116
Directory /workspace/21.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_random.2590476277
Short name T294
Test name
Test status
Simulation time 2942294302433 ps
CPU time 1261.58 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 07:04:30 PM PDT 24
Peak memory 191344 kb
Host smart-4abfca5c-2213-4ddf-a695-31fc5b34dc61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590476277 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random.2590476277
Directory /workspace/29.rv_timer_random/latest

Test location /workspace/coverage/default/54.rv_timer_random.661766383
Short name T63
Test name
Test status
Simulation time 178881154990 ps
CPU time 1212.73 seconds
Started Jul 17 06:44:25 PM PDT 24
Finished Jul 17 07:04:39 PM PDT 24
Peak memory 191304 kb
Host smart-800e84c1-6fa7-4505-8234-62dd5507f7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661766383 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.rv_timer_random.661766383
Directory /workspace/54.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_intg_err.3754837143
Short name T95
Test name
Test status
Simulation time 239439794 ps
CPU time 1.37 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:46 PM PDT 24
Peak memory 195156 kb
Host smart-a8fbb5f5-de14-43b7-a320-92d5bc441fcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754837143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_i
ntg_err.3754837143
Directory /workspace/17.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_cfg_update_on_fly.3955055283
Short name T442
Test name
Test status
Simulation time 543047865690 ps
CPU time 636.49 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:53:31 PM PDT 24
Peak memory 183144 kb
Host smart-3db1e6dc-0284-4e97-b922-220896aff36d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955055283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.rv_timer_cfg_update_on_fly.3955055283
Directory /workspace/0.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/0.rv_timer_random_reset.328946504
Short name T223
Test name
Test status
Simulation time 28639256753 ps
CPU time 28.4 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:43:22 PM PDT 24
Peak memory 183160 kb
Host smart-8f77bfe4-285b-4295-ab38-79130b1790f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328946504 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random_reset.328946504
Directory /workspace/0.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_cfg_update_on_fly.752161221
Short name T194
Test name
Test status
Simulation time 401412659927 ps
CPU time 380.58 seconds
Started Jul 17 06:43:05 PM PDT 24
Finished Jul 17 06:49:27 PM PDT 24
Peak memory 183144 kb
Host smart-59ddbb4e-f28d-464c-9d77-3ed00b3c4442
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752161221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.rv_timer_cfg_update_on_fly.752161221
Directory /workspace/12.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/146.rv_timer_random.2397138489
Short name T241
Test name
Test status
Simulation time 2038273965097 ps
CPU time 739.04 seconds
Started Jul 17 06:45:57 PM PDT 24
Finished Jul 17 06:58:16 PM PDT 24
Peak memory 191316 kb
Host smart-37b2a537-a355-4cf4-9e63-06a1b6fb662b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397138489 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.rv_timer_random.2397138489
Directory /workspace/146.rv_timer_random/latest

Test location /workspace/coverage/default/155.rv_timer_random.3933616989
Short name T102
Test name
Test status
Simulation time 159711508503 ps
CPU time 630.8 seconds
Started Jul 17 06:46:09 PM PDT 24
Finished Jul 17 06:56:41 PM PDT 24
Peak memory 193424 kb
Host smart-be935f6c-2fdc-4ee8-b1b8-2cf151290451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933616989 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.rv_timer_random.3933616989
Directory /workspace/155.rv_timer_random/latest

Test location /workspace/coverage/default/164.rv_timer_random.550554888
Short name T166
Test name
Test status
Simulation time 104003159454 ps
CPU time 136.71 seconds
Started Jul 17 06:46:09 PM PDT 24
Finished Jul 17 06:48:26 PM PDT 24
Peak memory 191288 kb
Host smart-a665b1d5-d9b7-433c-abca-e7124bd12f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550554888 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.rv_timer_random.550554888
Directory /workspace/164.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_random.1792285485
Short name T352
Test name
Test status
Simulation time 176805825493 ps
CPU time 1827.51 seconds
Started Jul 17 06:43:04 PM PDT 24
Finished Jul 17 07:13:34 PM PDT 24
Peak memory 183332 kb
Host smart-52b9745f-b80d-4475-8339-ae0b0fe2f71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792285485 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random.1792285485
Directory /workspace/17.rv_timer_random/latest

Test location /workspace/coverage/default/192.rv_timer_random.545660718
Short name T126
Test name
Test status
Simulation time 715214239562 ps
CPU time 338.23 seconds
Started Jul 17 06:46:44 PM PDT 24
Finished Jul 17 06:52:23 PM PDT 24
Peak memory 191288 kb
Host smart-9a7aa2c0-3869-43e8-8119-fd3be869061c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545660718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.rv_timer_random.545660718
Directory /workspace/192.rv_timer_random/latest

Test location /workspace/coverage/default/27.rv_timer_random.751904798
Short name T217
Test name
Test status
Simulation time 172377903942 ps
CPU time 75.94 seconds
Started Jul 17 06:43:26 PM PDT 24
Finished Jul 17 06:44:45 PM PDT 24
Peak memory 195208 kb
Host smart-1aa47b85-b2a2-4196-ab93-ee076071a66b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751904798 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random.751904798
Directory /workspace/27.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_cfg_update_on_fly.1914022088
Short name T120
Test name
Test status
Simulation time 2189541957075 ps
CPU time 928.28 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:58:56 PM PDT 24
Peak memory 183076 kb
Host smart-521c77f0-6099-417b-8852-a062af7d9958
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914022088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.rv_timer_cfg_update_on_fly.1914022088
Directory /workspace/28.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_random_reset.820142335
Short name T115
Test name
Test status
Simulation time 61435005613 ps
CPU time 28.79 seconds
Started Jul 17 06:43:36 PM PDT 24
Finished Jul 17 06:44:06 PM PDT 24
Peak memory 191352 kb
Host smart-2ff05ff8-82f3-4ba9-ae10-f71c0bf9ec09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820142335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random_reset.820142335
Directory /workspace/32.rv_timer_random_reset/latest

Test location /workspace/coverage/default/36.rv_timer_stress_all.4074413194
Short name T197
Test name
Test status
Simulation time 245556640623 ps
CPU time 431.68 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:50:53 PM PDT 24
Peak memory 191136 kb
Host smart-22340b72-365f-4ad5-9ff9-1db81ed7ad76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074413194 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_stress_all
.4074413194
Directory /workspace/36.rv_timer_stress_all/latest

Test location /workspace/coverage/default/43.rv_timer_random.303218541
Short name T273
Test name
Test status
Simulation time 692174166272 ps
CPU time 414.34 seconds
Started Jul 17 06:43:52 PM PDT 24
Finished Jul 17 06:50:48 PM PDT 24
Peak memory 191336 kb
Host smart-5bf6b77d-908f-4796-ba91-fe15bbddc275
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303218541 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random.303218541
Directory /workspace/43.rv_timer_random/latest

Test location /workspace/coverage/default/99.rv_timer_random.720115897
Short name T212
Test name
Test status
Simulation time 111399916727 ps
CPU time 597.24 seconds
Started Jul 17 06:45:10 PM PDT 24
Finished Jul 17 06:55:08 PM PDT 24
Peak memory 191240 kb
Host smart-00939037-40b6-47a3-8695-aa539e88f30f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720115897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.rv_timer_random.720115897
Directory /workspace/99.rv_timer_random/latest

Test location /workspace/coverage/default/10.rv_timer_cfg_update_on_fly.367490669
Short name T320
Test name
Test status
Simulation time 332338956880 ps
CPU time 166.53 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 06:45:50 PM PDT 24
Peak memory 183140 kb
Host smart-8f54172a-b737-4825-bcf0-f703f46700a8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367490669 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.rv_timer_cfg_update_on_fly.367490669
Directory /workspace/10.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/103.rv_timer_random.525874941
Short name T276
Test name
Test status
Simulation time 715628677425 ps
CPU time 553.21 seconds
Started Jul 17 06:45:12 PM PDT 24
Finished Jul 17 06:54:26 PM PDT 24
Peak memory 191288 kb
Host smart-de953b17-c0b5-4104-8dd4-65b52397035e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525874941 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.rv_timer_random.525874941
Directory /workspace/103.rv_timer_random/latest

Test location /workspace/coverage/default/105.rv_timer_random.3723605452
Short name T278
Test name
Test status
Simulation time 127877997274 ps
CPU time 76.13 seconds
Started Jul 17 06:45:21 PM PDT 24
Finished Jul 17 06:46:38 PM PDT 24
Peak memory 193336 kb
Host smart-0e5055f3-fe8b-484d-b2f0-de31234acdf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723605452 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.rv_timer_random.3723605452
Directory /workspace/105.rv_timer_random/latest

Test location /workspace/coverage/default/108.rv_timer_random.993365706
Short name T279
Test name
Test status
Simulation time 407154021200 ps
CPU time 461.56 seconds
Started Jul 17 06:45:22 PM PDT 24
Finished Jul 17 06:53:05 PM PDT 24
Peak memory 191280 kb
Host smart-b22bb765-dee3-480a-9caa-80b77019290a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993365706 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.rv_timer_random.993365706
Directory /workspace/108.rv_timer_random/latest

Test location /workspace/coverage/default/120.rv_timer_random.391426191
Short name T354
Test name
Test status
Simulation time 825020929461 ps
CPU time 349.73 seconds
Started Jul 17 06:46:04 PM PDT 24
Finished Jul 17 06:51:54 PM PDT 24
Peak memory 191344 kb
Host smart-951e50e2-c010-49b5-b7b7-1ffed3d456f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391426191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.rv_timer_random.391426191
Directory /workspace/120.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_cfg_update_on_fly.769098451
Short name T46
Test name
Test status
Simulation time 521469309912 ps
CPU time 311.5 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 06:48:16 PM PDT 24
Peak memory 183100 kb
Host smart-b26b0ee2-367c-45ba-92de-943d68e73ac7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769098451 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.rv_timer_cfg_update_on_fly.769098451
Directory /workspace/13.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_cfg_update_on_fly.3944078206
Short name T259
Test name
Test status
Simulation time 1204105286221 ps
CPU time 456.96 seconds
Started Jul 17 06:43:10 PM PDT 24
Finished Jul 17 06:50:49 PM PDT 24
Peak memory 183136 kb
Host smart-60474993-bced-4ac9-9e90-43d944c8b94d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944078206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.rv_timer_cfg_update_on_fly.3944078206
Directory /workspace/14.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/14.rv_timer_random.1887592912
Short name T330
Test name
Test status
Simulation time 19834519974 ps
CPU time 38 seconds
Started Jul 17 06:43:03 PM PDT 24
Finished Jul 17 06:43:43 PM PDT 24
Peak memory 183064 kb
Host smart-9fe9da3f-42fa-4f63-b599-638c740e3e47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887592912 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random.1887592912
Directory /workspace/14.rv_timer_random/latest

Test location /workspace/coverage/default/148.rv_timer_random.2276897514
Short name T350
Test name
Test status
Simulation time 10116820779 ps
CPU time 15.53 seconds
Started Jul 17 06:46:09 PM PDT 24
Finished Jul 17 06:46:26 PM PDT 24
Peak memory 183092 kb
Host smart-27e75c9a-b91c-4382-a264-0f5e2300c6e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276897514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.rv_timer_random.2276897514
Directory /workspace/148.rv_timer_random/latest

Test location /workspace/coverage/default/149.rv_timer_random.889185366
Short name T245
Test name
Test status
Simulation time 119758870722 ps
CPU time 1431.88 seconds
Started Jul 17 06:46:08 PM PDT 24
Finished Jul 17 07:10:01 PM PDT 24
Peak memory 191256 kb
Host smart-1689d427-83e0-43b9-89ac-1c9942ce85f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889185366 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.rv_timer_random.889185366
Directory /workspace/149.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_random.1950650820
Short name T280
Test name
Test status
Simulation time 127799600786 ps
CPU time 204.43 seconds
Started Jul 17 06:43:05 PM PDT 24
Finished Jul 17 06:46:32 PM PDT 24
Peak memory 191292 kb
Host smart-416d91cf-c3b8-400a-89af-bf984cbd9ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950650820 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random.1950650820
Directory /workspace/15.rv_timer_random/latest

Test location /workspace/coverage/default/152.rv_timer_random.3154157081
Short name T322
Test name
Test status
Simulation time 298409398784 ps
CPU time 255.22 seconds
Started Jul 17 06:46:10 PM PDT 24
Finished Jul 17 06:50:27 PM PDT 24
Peak memory 191292 kb
Host smart-95a07d8e-2048-4cd4-89f2-d839ef03632e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154157081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.rv_timer_random.3154157081
Directory /workspace/152.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_random_reset.3209214712
Short name T233
Test name
Test status
Simulation time 75255325528 ps
CPU time 388.08 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 06:49:32 PM PDT 24
Peak memory 194660 kb
Host smart-f33b996b-456c-4f5e-b163-67d58613756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209214712 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random_reset.3209214712
Directory /workspace/16.rv_timer_random_reset/latest

Test location /workspace/coverage/default/162.rv_timer_random.1726569569
Short name T110
Test name
Test status
Simulation time 480446337541 ps
CPU time 480.79 seconds
Started Jul 17 06:46:09 PM PDT 24
Finished Jul 17 06:54:12 PM PDT 24
Peak memory 191296 kb
Host smart-f7f1a699-b7c5-4f99-b68f-b8782e96fb50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726569569 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.rv_timer_random.1726569569
Directory /workspace/162.rv_timer_random/latest

Test location /workspace/coverage/default/170.rv_timer_random.1789841788
Short name T199
Test name
Test status
Simulation time 509225983874 ps
CPU time 1025.15 seconds
Started Jul 17 06:46:20 PM PDT 24
Finished Jul 17 07:03:26 PM PDT 24
Peak memory 191328 kb
Host smart-080f30eb-db6f-4f64-9409-1e0a4dac1eff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789841788 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.rv_timer_random.1789841788
Directory /workspace/170.rv_timer_random/latest

Test location /workspace/coverage/default/181.rv_timer_random.2800697037
Short name T192
Test name
Test status
Simulation time 108918785302 ps
CPU time 623.64 seconds
Started Jul 17 06:46:31 PM PDT 24
Finished Jul 17 06:56:55 PM PDT 24
Peak memory 191296 kb
Host smart-f442e5d4-f66e-4ebb-9445-6034870c2a3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800697037 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.rv_timer_random.2800697037
Directory /workspace/181.rv_timer_random/latest

Test location /workspace/coverage/default/182.rv_timer_random.3473284746
Short name T122
Test name
Test status
Simulation time 469564832559 ps
CPU time 247.55 seconds
Started Jul 17 06:46:29 PM PDT 24
Finished Jul 17 06:50:37 PM PDT 24
Peak memory 191336 kb
Host smart-64463cb1-537a-43ae-bb1b-279e663bb192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473284746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.rv_timer_random.3473284746
Directory /workspace/182.rv_timer_random/latest

Test location /workspace/coverage/default/183.rv_timer_random.265041055
Short name T154
Test name
Test status
Simulation time 134720921416 ps
CPU time 1380.42 seconds
Started Jul 17 06:46:31 PM PDT 24
Finished Jul 17 07:09:32 PM PDT 24
Peak memory 191292 kb
Host smart-7a301d9b-41eb-42de-955b-7143703a34b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265041055 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.rv_timer_random.265041055
Directory /workspace/183.rv_timer_random/latest

Test location /workspace/coverage/default/184.rv_timer_random.4217000746
Short name T190
Test name
Test status
Simulation time 159097007062 ps
CPU time 156.05 seconds
Started Jul 17 06:46:31 PM PDT 24
Finished Jul 17 06:49:07 PM PDT 24
Peak memory 191336 kb
Host smart-0a7ff9b4-222d-42e8-b809-1a384d26c843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217000746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.rv_timer_random.4217000746
Directory /workspace/184.rv_timer_random/latest

Test location /workspace/coverage/default/194.rv_timer_random.4086353101
Short name T189
Test name
Test status
Simulation time 110790864769 ps
CPU time 265.9 seconds
Started Jul 17 06:46:45 PM PDT 24
Finished Jul 17 06:51:12 PM PDT 24
Peak memory 183136 kb
Host smart-9f0b637a-b153-42da-a1cf-1ca731aeb3ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086353101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.rv_timer_random.4086353101
Directory /workspace/194.rv_timer_random/latest

Test location /workspace/coverage/default/195.rv_timer_random.312499327
Short name T128
Test name
Test status
Simulation time 838359856818 ps
CPU time 542.96 seconds
Started Jul 17 06:46:43 PM PDT 24
Finished Jul 17 06:55:48 PM PDT 24
Peak memory 191276 kb
Host smart-1cf095ca-9964-4a1f-8773-a3e96fd1dfb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312499327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.rv_timer_random.312499327
Directory /workspace/195.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_random.2628752926
Short name T216
Test name
Test status
Simulation time 330137935948 ps
CPU time 272.84 seconds
Started Jul 17 06:42:51 PM PDT 24
Finished Jul 17 06:47:25 PM PDT 24
Peak memory 191356 kb
Host smart-77d9181b-1168-4f7e-b3b6-9128e59b7355
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628752926 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random.2628752926
Directory /workspace/2.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_cfg_update_on_fly.3088570695
Short name T318
Test name
Test status
Simulation time 154259920779 ps
CPU time 43.1 seconds
Started Jul 17 06:43:15 PM PDT 24
Finished Jul 17 06:44:00 PM PDT 24
Peak memory 183136 kb
Host smart-f5cffdf7-53c4-4862-9a78-c8db0ffeeac0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088570695 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.rv_timer_cfg_update_on_fly.3088570695
Directory /workspace/23.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/26.rv_timer_cfg_update_on_fly.1684158983
Short name T315
Test name
Test status
Simulation time 18636421921 ps
CPU time 17.59 seconds
Started Jul 17 06:43:24 PM PDT 24
Finished Jul 17 06:43:44 PM PDT 24
Peak memory 183068 kb
Host smart-c1eba264-2b81-4cff-a9af-34042669e8ee
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684158983 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.rv_timer_cfg_update_on_fly.1684158983
Directory /workspace/26.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_random.2005491589
Short name T319
Test name
Test status
Simulation time 787703667481 ps
CPU time 663.68 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:53:58 PM PDT 24
Peak memory 191340 kb
Host smart-48ef5884-2d51-48df-a8e1-1ef68219a9bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005491589 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random.2005491589
Directory /workspace/3.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_random_reset.4194959227
Short name T159
Test name
Test status
Simulation time 7834815678 ps
CPU time 7.47 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:43:35 PM PDT 24
Peak memory 193408 kb
Host smart-d6f92a94-7d7d-4e1c-9f9e-6dc81930c883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194959227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random_reset.4194959227
Directory /workspace/31.rv_timer_random_reset/latest

Test location /workspace/coverage/default/32.rv_timer_stress_all.4235254461
Short name T62
Test name
Test status
Simulation time 537472251535 ps
CPU time 1261.22 seconds
Started Jul 17 06:43:41 PM PDT 24
Finished Jul 17 07:04:44 PM PDT 24
Peak memory 191492 kb
Host smart-bf9e9e43-fa11-4c5d-9c08-bb1492141ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235254461 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_stress_all
.4235254461
Directory /workspace/32.rv_timer_stress_all/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all.682753146
Short name T54
Test name
Test status
Simulation time 278195209224 ps
CPU time 387.3 seconds
Started Jul 17 06:43:45 PM PDT 24
Finished Jul 17 06:50:13 PM PDT 24
Peak memory 196044 kb
Host smart-29f93da7-84ce-45b9-a8a0-15da2a2ea985
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682753146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all.
682753146
Directory /workspace/33.rv_timer_stress_all/latest

Test location /workspace/coverage/default/4.rv_timer_random.3233614928
Short name T243
Test name
Test status
Simulation time 41668166207 ps
CPU time 58.87 seconds
Started Jul 17 06:42:50 PM PDT 24
Finished Jul 17 06:43:50 PM PDT 24
Peak memory 191336 kb
Host smart-be384ce6-b1f5-4f74-9b56-8c22ff5caa20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233614928 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random.3233614928
Directory /workspace/4.rv_timer_random/latest

Test location /workspace/coverage/default/45.rv_timer_random_reset.2275989332
Short name T306
Test name
Test status
Simulation time 1451884938 ps
CPU time 8.27 seconds
Started Jul 17 06:44:02 PM PDT 24
Finished Jul 17 06:44:12 PM PDT 24
Peak memory 191296 kb
Host smart-12aaee89-c46d-4662-95c8-ac3383f4ce14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275989332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random_reset.2275989332
Directory /workspace/45.rv_timer_random_reset/latest

Test location /workspace/coverage/default/52.rv_timer_random.377479869
Short name T131
Test name
Test status
Simulation time 342878079751 ps
CPU time 835.53 seconds
Started Jul 17 06:44:28 PM PDT 24
Finished Jul 17 06:58:24 PM PDT 24
Peak memory 194584 kb
Host smart-78517c86-2097-4cfc-803e-a10136b9ee1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377479869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.rv_timer_random.377479869
Directory /workspace/52.rv_timer_random/latest

Test location /workspace/coverage/default/60.rv_timer_random.2841798030
Short name T274
Test name
Test status
Simulation time 971583111620 ps
CPU time 307.39 seconds
Started Jul 17 06:44:30 PM PDT 24
Finished Jul 17 06:49:38 PM PDT 24
Peak memory 191308 kb
Host smart-ab4a2dea-ae01-4105-957d-89df22f5f439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841798030 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.rv_timer_random.2841798030
Directory /workspace/60.rv_timer_random/latest

Test location /workspace/coverage/default/80.rv_timer_random.4167631434
Short name T65
Test name
Test status
Simulation time 214389460103 ps
CPU time 2537.54 seconds
Started Jul 17 06:44:49 PM PDT 24
Finished Jul 17 07:27:08 PM PDT 24
Peak memory 191540 kb
Host smart-dcf68e59-39ee-4700-a89d-ffc660d10192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167631434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.rv_timer_random.4167631434
Directory /workspace/80.rv_timer_random/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_aliasing.3675283073
Short name T81
Test name
Test status
Simulation time 40294063 ps
CPU time 0.77 seconds
Started Jul 17 06:41:55 PM PDT 24
Finished Jul 17 06:41:57 PM PDT 24
Peak memory 191788 kb
Host smart-d16f342d-d0c5-4623-a14b-1ee8a272bccf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675283073 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_alia
sing.3675283073
Directory /workspace/0.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3642187795
Short name T506
Test name
Test status
Simulation time 1109092404 ps
CPU time 3.66 seconds
Started Jul 17 06:41:58 PM PDT 24
Finished Jul 17 06:42:03 PM PDT 24
Peak memory 192516 kb
Host smart-6fe52ae6-31e3-40b8-8d06-0ee7ec3173dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642187795 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_bit_
bash.3642187795
Directory /workspace/0.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.2899750078
Short name T522
Test name
Test status
Simulation time 46105525 ps
CPU time 0.55 seconds
Started Jul 17 06:41:58 PM PDT 24
Finished Jul 17 06:42:00 PM PDT 24
Peak memory 182544 kb
Host smart-d858c6fe-980c-4fe6-a474-9886d3300ce8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899750078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_hw_r
eset.2899750078
Directory /workspace/0.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2591243252
Short name T573
Test name
Test status
Simulation time 47832541 ps
CPU time 1.01 seconds
Started Jul 17 06:42:00 PM PDT 24
Finished Jul 17 06:42:01 PM PDT 24
Peak memory 197216 kb
Host smart-f112bab7-1e82-4b57-88e2-dc1bc33d1b8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591243252 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.rv_timer_csr_mem_rw_with_rand_reset.2591243252
Directory /workspace/0.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_csr_rw.2537694010
Short name T545
Test name
Test status
Simulation time 34511866 ps
CPU time 0.53 seconds
Started Jul 17 06:41:56 PM PDT 24
Finished Jul 17 06:41:58 PM PDT 24
Peak memory 182552 kb
Host smart-51fa1cb8-41b6-4a85-9a44-aeda9904468e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537694010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_csr_rw.2537694010
Directory /workspace/0.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_intr_test.3197643571
Short name T499
Test name
Test status
Simulation time 36304024 ps
CPU time 0.56 seconds
Started Jul 17 06:41:59 PM PDT 24
Finished Jul 17 06:42:00 PM PDT 24
Peak memory 182608 kb
Host smart-8fd0b1d2-9e2e-4cf8-b29a-66de43a9449b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197643571 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_intr_test.3197643571
Directory /workspace/0.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.449508852
Short name T89
Test name
Test status
Simulation time 122191043 ps
CPU time 0.73 seconds
Started Jul 17 06:41:56 PM PDT 24
Finished Jul 17 06:41:57 PM PDT 24
Peak memory 192020 kb
Host smart-a8f923d2-7a1a-462c-bd7a-15d658c6e956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449508852 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_tim
er_same_csr_outstanding.449508852
Directory /workspace/0.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_errors.2206608957
Short name T551
Test name
Test status
Simulation time 719773367 ps
CPU time 3.4 seconds
Started Jul 17 06:41:58 PM PDT 24
Finished Jul 17 06:42:03 PM PDT 24
Peak memory 197264 kb
Host smart-0aa99930-91bd-4273-a57e-67e2effce52f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206608957 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_errors.2206608957
Directory /workspace/0.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3107334929
Short name T534
Test name
Test status
Simulation time 179909610 ps
CPU time 1.11 seconds
Started Jul 17 06:41:58 PM PDT 24
Finished Jul 17 06:42:00 PM PDT 24
Peak memory 182812 kb
Host smart-d8348f07-0cea-474e-a128-6b6a6a1ea3c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107334929 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_timer_tl_in
tg_err.3107334929
Directory /workspace/0.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_aliasing.508287063
Short name T553
Test name
Test status
Simulation time 476083148 ps
CPU time 0.88 seconds
Started Jul 17 06:41:56 PM PDT 24
Finished Jul 17 06:41:58 PM PDT 24
Peak memory 192544 kb
Host smart-c31f95c3-0fe7-4d00-b57d-da1b55df37c4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508287063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_alias
ing.508287063
Directory /workspace/1.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_hw_reset.959094715
Short name T523
Test name
Test status
Simulation time 58574445 ps
CPU time 0.57 seconds
Started Jul 17 06:41:57 PM PDT 24
Finished Jul 17 06:41:59 PM PDT 24
Peak memory 182560 kb
Host smart-ab98f5d3-bc50-49e6-9ef7-279840ae21e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959094715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_hw_re
set.959094715
Directory /workspace/1.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.3571559195
Short name T476
Test name
Test status
Simulation time 43498802 ps
CPU time 0.77 seconds
Started Jul 17 06:41:55 PM PDT 24
Finished Jul 17 06:41:57 PM PDT 24
Peak memory 195324 kb
Host smart-f3eba69a-117e-46ef-a06d-ef0c7779a98d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571559195 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.rv_timer_csr_mem_rw_with_rand_reset.3571559195
Directory /workspace/1.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_csr_rw.729194167
Short name T53
Test name
Test status
Simulation time 198774241 ps
CPU time 0.6 seconds
Started Jul 17 06:41:55 PM PDT 24
Finished Jul 17 06:41:57 PM PDT 24
Peak memory 182536 kb
Host smart-f4b6a672-72f0-48ba-9f15-05e6fb95fdd4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729194167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_csr_rw.729194167
Directory /workspace/1.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_intr_test.34684483
Short name T496
Test name
Test status
Simulation time 75285580 ps
CPU time 0.55 seconds
Started Jul 17 06:41:55 PM PDT 24
Finished Jul 17 06:41:56 PM PDT 24
Peak memory 182492 kb
Host smart-86a41d7b-aa60-422a-a09f-9fc1e6c99299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34684483 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_intr_test.34684483
Directory /workspace/1.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.1192207964
Short name T73
Test name
Test status
Simulation time 26895897 ps
CPU time 0.76 seconds
Started Jul 17 06:42:00 PM PDT 24
Finished Jul 17 06:42:02 PM PDT 24
Peak memory 191492 kb
Host smart-562b1b53-3d87-4b4e-b18a-bda3394afa6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192207964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_ti
mer_same_csr_outstanding.1192207964
Directory /workspace/1.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_timer_tl_errors.3494928449
Short name T486
Test name
Test status
Simulation time 85653282 ps
CPU time 1.38 seconds
Started Jul 17 06:41:56 PM PDT 24
Finished Jul 17 06:41:59 PM PDT 24
Peak memory 197448 kb
Host smart-e4964830-803b-4511-9c03-61512d8c514f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494928449 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_timer_tl_errors.3494928449
Directory /workspace/1.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_mem_rw_with_rand_reset.4029135250
Short name T33
Test name
Test status
Simulation time 31822933 ps
CPU time 0.69 seconds
Started Jul 17 06:42:14 PM PDT 24
Finished Jul 17 06:42:16 PM PDT 24
Peak memory 194240 kb
Host smart-87b4bd11-9a6c-42d8-8fdd-67de1669efc9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029135250 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.rv_timer_csr_mem_rw_with_rand_reset.4029135250
Directory /workspace/10.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_csr_rw.3984781059
Short name T490
Test name
Test status
Simulation time 13333456 ps
CPU time 0.56 seconds
Started Jul 17 06:42:16 PM PDT 24
Finished Jul 17 06:42:18 PM PDT 24
Peak memory 182540 kb
Host smart-db1785aa-439e-4d7a-8588-cecc04b79d71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984781059 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_csr_rw.3984781059
Directory /workspace/10.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_intr_test.697031088
Short name T549
Test name
Test status
Simulation time 54559085 ps
CPU time 0.57 seconds
Started Jul 17 06:42:15 PM PDT 24
Finished Jul 17 06:42:17 PM PDT 24
Peak memory 182464 kb
Host smart-5e903331-49dd-4e7d-a2c8-0164ae1e7065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697031088 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_intr_test.697031088
Directory /workspace/10.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_same_csr_outstanding.2071102862
Short name T575
Test name
Test status
Simulation time 127677187 ps
CPU time 0.76 seconds
Started Jul 17 06:42:17 PM PDT 24
Finished Jul 17 06:42:19 PM PDT 24
Peak memory 193172 kb
Host smart-b5de2e23-cc07-4143-b466-2fe19e49cc19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071102862 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_t
imer_same_csr_outstanding.2071102862
Directory /workspace/10.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_errors.4050757767
Short name T519
Test name
Test status
Simulation time 217650780 ps
CPU time 2.52 seconds
Started Jul 17 06:42:17 PM PDT 24
Finished Jul 17 06:42:21 PM PDT 24
Peak memory 197280 kb
Host smart-81055251-47dd-4147-8529-4c5eb0ac3b37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050757767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_errors.4050757767
Directory /workspace/10.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_timer_tl_intg_err.2967699111
Short name T516
Test name
Test status
Simulation time 175753958 ps
CPU time 0.87 seconds
Started Jul 17 06:42:17 PM PDT 24
Finished Jul 17 06:42:19 PM PDT 24
Peak memory 192968 kb
Host smart-9bc15ec3-c199-4360-aa41-bfa7b0c5083c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967699111 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_timer_tl_i
ntg_err.2967699111
Directory /workspace/10.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_mem_rw_with_rand_reset.3711085302
Short name T483
Test name
Test status
Simulation time 46229840 ps
CPU time 0.68 seconds
Started Jul 17 06:42:29 PM PDT 24
Finished Jul 17 06:42:31 PM PDT 24
Peak memory 193796 kb
Host smart-e4aa79ae-276f-45d1-a5a9-094c7977143a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711085302 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.rv_timer_csr_mem_rw_with_rand_reset.3711085302
Directory /workspace/11.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_csr_rw.3623237475
Short name T75
Test name
Test status
Simulation time 16776475 ps
CPU time 0.57 seconds
Started Jul 17 06:42:30 PM PDT 24
Finished Jul 17 06:42:32 PM PDT 24
Peak memory 182576 kb
Host smart-797e4d99-051e-48f9-91d9-6e01e10641f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623237475 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_csr_rw.3623237475
Directory /workspace/11.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_intr_test.4161019683
Short name T455
Test name
Test status
Simulation time 265864933 ps
CPU time 0.58 seconds
Started Jul 17 06:42:29 PM PDT 24
Finished Jul 17 06:42:31 PM PDT 24
Peak memory 182412 kb
Host smart-d8232313-b62f-4283-9ccd-fee7f94c29cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161019683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_intr_test.4161019683
Directory /workspace/11.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_same_csr_outstanding.2320788146
Short name T502
Test name
Test status
Simulation time 164765768 ps
CPU time 0.83 seconds
Started Jul 17 06:42:29 PM PDT 24
Finished Jul 17 06:42:31 PM PDT 24
Peak memory 191512 kb
Host smart-1e152f0c-6906-4e65-8410-1a5cafb14c3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320788146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_t
imer_same_csr_outstanding.2320788146
Directory /workspace/11.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_errors.2416145156
Short name T577
Test name
Test status
Simulation time 121122553 ps
CPU time 1.48 seconds
Started Jul 17 06:42:32 PM PDT 24
Finished Jul 17 06:42:34 PM PDT 24
Peak memory 197304 kb
Host smart-ad97526d-e7ce-4045-916b-2181145d54aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416145156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_errors.2416145156
Directory /workspace/11.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_timer_tl_intg_err.378591389
Short name T461
Test name
Test status
Simulation time 231943998 ps
CPU time 1.4 seconds
Started Jul 17 06:42:28 PM PDT 24
Finished Jul 17 06:42:30 PM PDT 24
Peak memory 194788 kb
Host smart-528544e8-f541-4a0a-9b6a-05cb844d88d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378591389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_timer_tl_in
tg_err.378591389
Directory /workspace/11.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_mem_rw_with_rand_reset.36350793
Short name T574
Test name
Test status
Simulation time 29848728 ps
CPU time 0.84 seconds
Started Jul 17 06:42:30 PM PDT 24
Finished Jul 17 06:42:32 PM PDT 24
Peak memory 196212 kb
Host smart-15a6cde9-59d4-4286-b59d-c33338211010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36350793 -assert nopostproc +UVM_TESTNAME=r
v_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.rv_timer_csr_mem_rw_with_rand_reset.36350793
Directory /workspace/12.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_csr_rw.60883674
Short name T503
Test name
Test status
Simulation time 11137617 ps
CPU time 0.57 seconds
Started Jul 17 06:42:27 PM PDT 24
Finished Jul 17 06:42:28 PM PDT 24
Peak memory 182536 kb
Host smart-009b193a-bb12-45b0-a58f-cc58ad63da42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60883674 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_csr_rw.60883674
Directory /workspace/12.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_intr_test.961874294
Short name T532
Test name
Test status
Simulation time 51439111 ps
CPU time 0.56 seconds
Started Jul 17 06:42:32 PM PDT 24
Finished Jul 17 06:42:33 PM PDT 24
Peak memory 182444 kb
Host smart-4117d53d-a3e8-4334-982a-38c377567fd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961874294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_intr_test.961874294
Directory /workspace/12.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_errors.2692787341
Short name T559
Test name
Test status
Simulation time 473164157 ps
CPU time 2 seconds
Started Jul 17 06:42:28 PM PDT 24
Finished Jul 17 06:42:32 PM PDT 24
Peak memory 197320 kb
Host smart-7260bb83-68ca-482e-b622-22fabc4c4dba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692787341 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_errors.2692787341
Directory /workspace/12.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_timer_tl_intg_err.4053120153
Short name T510
Test name
Test status
Simulation time 802569859 ps
CPU time 1.46 seconds
Started Jul 17 06:42:30 PM PDT 24
Finished Jul 17 06:42:32 PM PDT 24
Peak memory 195220 kb
Host smart-560ff9aa-434c-4361-a9d8-6923afd12ad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053120153 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_timer_tl_i
ntg_err.4053120153
Directory /workspace/12.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_mem_rw_with_rand_reset.2727295093
Short name T494
Test name
Test status
Simulation time 16737100 ps
CPU time 0.64 seconds
Started Jul 17 06:42:28 PM PDT 24
Finished Jul 17 06:42:30 PM PDT 24
Peak memory 193288 kb
Host smart-1339a18f-7d26-4bc5-93b8-91aa7d9e65a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727295093 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.rv_timer_csr_mem_rw_with_rand_reset.2727295093
Directory /workspace/13.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_csr_rw.3693053389
Short name T71
Test name
Test status
Simulation time 206445520 ps
CPU time 0.55 seconds
Started Jul 17 06:42:27 PM PDT 24
Finished Jul 17 06:42:29 PM PDT 24
Peak memory 182564 kb
Host smart-3dbf9626-0861-4c84-a6c6-2e47eced0e1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693053389 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_csr_rw.3693053389
Directory /workspace/13.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_intr_test.1609972367
Short name T505
Test name
Test status
Simulation time 39711573 ps
CPU time 0.56 seconds
Started Jul 17 06:42:28 PM PDT 24
Finished Jul 17 06:42:30 PM PDT 24
Peak memory 182448 kb
Host smart-cf7695c0-f9cb-4345-9438-9f860195ea78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609972367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_intr_test.1609972367
Directory /workspace/13.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_same_csr_outstanding.1425994425
Short name T72
Test name
Test status
Simulation time 38059736 ps
CPU time 0.68 seconds
Started Jul 17 06:42:28 PM PDT 24
Finished Jul 17 06:42:29 PM PDT 24
Peak memory 191464 kb
Host smart-94ae5df6-40e9-49e2-9899-bd704c254edf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425994425 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_t
imer_same_csr_outstanding.1425994425
Directory /workspace/13.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_errors.1547746253
Short name T546
Test name
Test status
Simulation time 277221074 ps
CPU time 2.51 seconds
Started Jul 17 06:42:27 PM PDT 24
Finished Jul 17 06:42:31 PM PDT 24
Peak memory 197264 kb
Host smart-d5aa15c6-a178-439b-95a9-d7fcb9160554
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547746253 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_errors.1547746253
Directory /workspace/13.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_timer_tl_intg_err.3882928247
Short name T524
Test name
Test status
Simulation time 79397206 ps
CPU time 0.82 seconds
Started Jul 17 06:42:28 PM PDT 24
Finished Jul 17 06:42:30 PM PDT 24
Peak memory 193348 kb
Host smart-6cd26f96-08e8-4b71-9e84-afa3912e39c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882928247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_timer_tl_i
ntg_err.3882928247
Directory /workspace/13.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_mem_rw_with_rand_reset.2895618435
Short name T481
Test name
Test status
Simulation time 41514797 ps
CPU time 0.71 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:41 PM PDT 24
Peak memory 195056 kb
Host smart-d8d7c8e0-c8f2-4e2a-8e33-aaf872152ee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895618435 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.rv_timer_csr_mem_rw_with_rand_reset.2895618435
Directory /workspace/14.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_csr_rw.3245535964
Short name T76
Test name
Test status
Simulation time 17095553 ps
CPU time 0.62 seconds
Started Jul 17 06:42:29 PM PDT 24
Finished Jul 17 06:42:31 PM PDT 24
Peak memory 182504 kb
Host smart-475ff146-5fa7-48c7-8920-e58625f641c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245535964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_csr_rw.3245535964
Directory /workspace/14.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_intr_test.3779265747
Short name T548
Test name
Test status
Simulation time 38750008 ps
CPU time 0.55 seconds
Started Jul 17 06:42:29 PM PDT 24
Finished Jul 17 06:42:31 PM PDT 24
Peak memory 181896 kb
Host smart-15556337-ba5d-4ffb-ab93-e863284c62cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779265747 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_intr_test.3779265747
Directory /workspace/14.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_same_csr_outstanding.1991525038
Short name T87
Test name
Test status
Simulation time 129201428 ps
CPU time 0.8 seconds
Started Jul 17 06:42:44 PM PDT 24
Finished Jul 17 06:42:48 PM PDT 24
Peak memory 191416 kb
Host smart-c227f850-521a-485d-a0d6-97794dd7b748
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991525038 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_t
imer_same_csr_outstanding.1991525038
Directory /workspace/14.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_errors.4234506513
Short name T576
Test name
Test status
Simulation time 130485215 ps
CPU time 2.16 seconds
Started Jul 17 06:42:29 PM PDT 24
Finished Jul 17 06:42:33 PM PDT 24
Peak memory 197256 kb
Host smart-57290025-9e01-4d59-b018-32a7a6a56f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234506513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_errors.4234506513
Directory /workspace/14.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_timer_tl_intg_err.3575900352
Short name T515
Test name
Test status
Simulation time 297288342 ps
CPU time 1.14 seconds
Started Jul 17 06:42:27 PM PDT 24
Finished Jul 17 06:42:29 PM PDT 24
Peak memory 194928 kb
Host smart-20f35baa-66ae-4455-8bbb-3229fc43163c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575900352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_timer_tl_i
ntg_err.3575900352
Directory /workspace/14.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_mem_rw_with_rand_reset.2680378081
Short name T518
Test name
Test status
Simulation time 478331656 ps
CPU time 0.92 seconds
Started Jul 17 06:42:43 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 196628 kb
Host smart-48282f4c-2601-4328-bf3e-1da31ae04249
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680378081 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.rv_timer_csr_mem_rw_with_rand_reset.2680378081
Directory /workspace/15.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_csr_rw.1676724222
Short name T82
Test name
Test status
Simulation time 17421212 ps
CPU time 0.6 seconds
Started Jul 17 06:42:44 PM PDT 24
Finished Jul 17 06:42:48 PM PDT 24
Peak memory 182544 kb
Host smart-d96131ca-14dc-46ae-90a1-b41f977034f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676724222 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_csr_rw.1676724222
Directory /workspace/15.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_intr_test.3944531488
Short name T513
Test name
Test status
Simulation time 16911924 ps
CPU time 0.58 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:42 PM PDT 24
Peak memory 182396 kb
Host smart-30b929e3-ef36-4c57-9ed6-f0737d8fdd82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944531488 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_intr_test.3944531488
Directory /workspace/15.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_same_csr_outstanding.3867278736
Short name T88
Test name
Test status
Simulation time 114712672 ps
CPU time 0.76 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:46 PM PDT 24
Peak memory 193136 kb
Host smart-84d5a293-0257-468e-8d93-3bc185c2cf21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867278736 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_t
imer_same_csr_outstanding.3867278736
Directory /workspace/15.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_errors.1584185718
Short name T530
Test name
Test status
Simulation time 221091873 ps
CPU time 1.44 seconds
Started Jul 17 06:42:39 PM PDT 24
Finished Jul 17 06:42:42 PM PDT 24
Peak memory 197476 kb
Host smart-a9e66e6d-e10c-483c-82e4-512b85b3ab23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584185718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_errors.1584185718
Directory /workspace/15.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_timer_tl_intg_err.1869530680
Short name T98
Test name
Test status
Simulation time 175604606 ps
CPU time 1.03 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:45 PM PDT 24
Peak memory 182884 kb
Host smart-8ff8d02c-70db-4de7-b764-ee61137437c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869530680 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_timer_tl_i
ntg_err.1869530680
Directory /workspace/15.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_mem_rw_with_rand_reset.3330198829
Short name T32
Test name
Test status
Simulation time 47894942 ps
CPU time 1.2 seconds
Started Jul 17 06:42:45 PM PDT 24
Finished Jul 17 06:42:49 PM PDT 24
Peak memory 197272 kb
Host smart-4ebf0761-441c-4cd4-937a-1b82b0c0264d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330198829 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.rv_timer_csr_mem_rw_with_rand_reset.3330198829
Directory /workspace/16.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_csr_rw.447227903
Short name T80
Test name
Test status
Simulation time 58303656 ps
CPU time 0.58 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:43 PM PDT 24
Peak memory 182576 kb
Host smart-3105301e-e5e4-4a79-a227-f15f51d813b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447227903 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_csr_rw.447227903
Directory /workspace/16.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_intr_test.2067985841
Short name T554
Test name
Test status
Simulation time 51520678 ps
CPU time 0.6 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:41 PM PDT 24
Peak memory 182444 kb
Host smart-358f1de7-08a7-448d-b233-a805fcf4824a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067985841 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_intr_test.2067985841
Directory /workspace/16.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_same_csr_outstanding.1514657332
Short name T512
Test name
Test status
Simulation time 28589617 ps
CPU time 0.64 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:44 PM PDT 24
Peak memory 191776 kb
Host smart-77028cd6-dfb5-41bb-a64a-e1b12328dca4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514657332 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_t
imer_same_csr_outstanding.1514657332
Directory /workspace/16.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_errors.2127564375
Short name T465
Test name
Test status
Simulation time 73776712 ps
CPU time 1.43 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:46 PM PDT 24
Peak memory 196948 kb
Host smart-92dbd5c6-9d26-4b88-be9e-3e5141dc2674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127564375 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_errors.2127564375
Directory /workspace/16.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_timer_tl_intg_err.413790861
Short name T29
Test name
Test status
Simulation time 270283937 ps
CPU time 0.86 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:44 PM PDT 24
Peak memory 192612 kb
Host smart-72f2c154-8489-4405-addd-0dd630a672cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413790861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_timer_tl_in
tg_err.413790861
Directory /workspace/16.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_mem_rw_with_rand_reset.3220186420
Short name T482
Test name
Test status
Simulation time 234694091 ps
CPU time 0.76 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:43 PM PDT 24
Peak memory 195388 kb
Host smart-0ff32378-bdd3-4aee-a95e-4e47dda96cef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220186420 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.rv_timer_csr_mem_rw_with_rand_reset.3220186420
Directory /workspace/17.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_csr_rw.2171267540
Short name T568
Test name
Test status
Simulation time 63562419 ps
CPU time 0.54 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:41 PM PDT 24
Peak memory 182564 kb
Host smart-42dd80e7-2785-4c3b-8006-d017dd7d9050
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171267540 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_csr_rw.2171267540
Directory /workspace/17.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_intr_test.1018784962
Short name T484
Test name
Test status
Simulation time 45575863 ps
CPU time 0.55 seconds
Started Jul 17 06:42:43 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182400 kb
Host smart-dd311182-c4ac-4f29-9a83-01ea317c4f7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018784962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_intr_test.1018784962
Directory /workspace/17.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_same_csr_outstanding.648247091
Short name T560
Test name
Test status
Simulation time 69279494 ps
CPU time 0.73 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:41 PM PDT 24
Peak memory 193104 kb
Host smart-a06d3d2d-8853-44dc-b2fd-986611f4da8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648247091 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_ti
mer_same_csr_outstanding.648247091
Directory /workspace/17.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_timer_tl_errors.3369204089
Short name T497
Test name
Test status
Simulation time 594266204 ps
CPU time 2.42 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:44 PM PDT 24
Peak memory 197296 kb
Host smart-41c9fac0-d949-4cb5-8724-677ed299457e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369204089 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_timer_tl_errors.3369204089
Directory /workspace/17.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_mem_rw_with_rand_reset.1647743068
Short name T473
Test name
Test status
Simulation time 23810079 ps
CPU time 1.01 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 197180 kb
Host smart-3683a965-32da-4203-bb23-28b213dd788c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647743068 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.rv_timer_csr_mem_rw_with_rand_reset.1647743068
Directory /workspace/18.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_csr_rw.268326099
Short name T79
Test name
Test status
Simulation time 33643173 ps
CPU time 0.53 seconds
Started Jul 17 06:42:43 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182324 kb
Host smart-30a79f01-2bd8-4924-baf8-60e00089ed33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268326099 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_csr_rw.268326099
Directory /workspace/18.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_intr_test.1179274634
Short name T471
Test name
Test status
Simulation time 83145107 ps
CPU time 0.54 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:42 PM PDT 24
Peak memory 182376 kb
Host smart-93e16ca2-2e5e-4ab4-b11a-1f3f5fe1f44d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179274634 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_intr_test.1179274634
Directory /workspace/18.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_same_csr_outstanding.302863408
Short name T86
Test name
Test status
Simulation time 174956610 ps
CPU time 0.77 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:46 PM PDT 24
Peak memory 191376 kb
Host smart-b85a9587-ce39-4680-9725-4b9719741e97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302863408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_ti
mer_same_csr_outstanding.302863408
Directory /workspace/18.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_errors.2471784407
Short name T457
Test name
Test status
Simulation time 134220398 ps
CPU time 2.44 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 197272 kb
Host smart-fa92ad98-a947-4407-aea8-908daf247819
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471784407 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_errors.2471784407
Directory /workspace/18.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_timer_tl_intg_err.32528440
Short name T537
Test name
Test status
Simulation time 84403724 ps
CPU time 1.13 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182856 kb
Host smart-bedc8360-f008-4085-b436-870bd8e54762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32528440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_timer_tl_int
g_err.32528440
Directory /workspace/18.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_mem_rw_with_rand_reset.4164228700
Short name T539
Test name
Test status
Simulation time 26023455 ps
CPU time 0.74 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:42 PM PDT 24
Peak memory 195292 kb
Host smart-238dbe95-dd9b-4886-89fe-77db5ddcf95b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164228700 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.rv_timer_csr_mem_rw_with_rand_reset.4164228700
Directory /workspace/19.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_csr_rw.2932682315
Short name T563
Test name
Test status
Simulation time 19867234 ps
CPU time 0.65 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182568 kb
Host smart-ad01e4c3-eaac-4ceb-b9fe-782ef51ef598
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932682315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_csr_rw.2932682315
Directory /workspace/19.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_intr_test.4137916044
Short name T460
Test name
Test status
Simulation time 15601310 ps
CPU time 0.54 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:45 PM PDT 24
Peak memory 181920 kb
Host smart-4a3d807b-41a2-4e31-9b66-a65df171c25a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137916044 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_intr_test.4137916044
Directory /workspace/19.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_same_csr_outstanding.43578175
Short name T517
Test name
Test status
Simulation time 81199772 ps
CPU time 0.68 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 191504 kb
Host smart-188d4799-f348-41cf-a399-8538b3a55b1c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43578175 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_tim
er_same_csr_outstanding.43578175
Directory /workspace/19.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_errors.2978012476
Short name T492
Test name
Test status
Simulation time 647636647 ps
CPU time 2.5 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 197428 kb
Host smart-29be62b9-aadd-4f83-b6a8-0dd037fecdfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978012476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_errors.2978012476
Directory /workspace/19.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_timer_tl_intg_err.697744426
Short name T580
Test name
Test status
Simulation time 443645497 ps
CPU time 0.86 seconds
Started Jul 17 06:42:43 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 193332 kb
Host smart-a4dc07c9-e8a6-4334-8bab-d00dc508a8e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697744426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_timer_tl_in
tg_err.697744426
Directory /workspace/19.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_aliasing.2225183790
Short name T83
Test name
Test status
Simulation time 67669377 ps
CPU time 0.64 seconds
Started Jul 17 06:41:58 PM PDT 24
Finished Jul 17 06:42:00 PM PDT 24
Peak memory 182552 kb
Host smart-046cb9eb-4b30-4958-966a-f3a9f409a9e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225183790 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_alia
sing.2225183790
Directory /workspace/2.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_bit_bash.3723170530
Short name T525
Test name
Test status
Simulation time 36913876 ps
CPU time 1.54 seconds
Started Jul 17 06:41:56 PM PDT 24
Finished Jul 17 06:41:59 PM PDT 24
Peak memory 193720 kb
Host smart-a125bf1e-a853-45cf-a8d5-82fcfe9a8491
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723170530 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_bit_
bash.3723170530
Directory /workspace/2.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_hw_reset.2380915032
Short name T547
Test name
Test status
Simulation time 53747696 ps
CPU time 0.55 seconds
Started Jul 17 06:41:55 PM PDT 24
Finished Jul 17 06:41:57 PM PDT 24
Peak memory 182560 kb
Host smart-433738f9-eab8-40fe-ae99-87e28d98e1cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380915032 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_hw_r
eset.2380915032
Directory /workspace/2.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.3845725932
Short name T475
Test name
Test status
Simulation time 25634960 ps
CPU time 1.14 seconds
Started Jul 17 06:42:00 PM PDT 24
Finished Jul 17 06:42:02 PM PDT 24
Peak memory 197284 kb
Host smart-890b4b5f-8711-4082-b6b9-b3cd65070e6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845725932 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.rv_timer_csr_mem_rw_with_rand_reset.3845725932
Directory /workspace/2.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_csr_rw.620793169
Short name T488
Test name
Test status
Simulation time 11208262 ps
CPU time 0.51 seconds
Started Jul 17 06:41:54 PM PDT 24
Finished Jul 17 06:41:55 PM PDT 24
Peak memory 182568 kb
Host smart-e7efe7e3-96d4-455f-8cf1-e4bd98fc8f3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620793169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_csr_rw.620793169
Directory /workspace/2.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_intr_test.1254731104
Short name T544
Test name
Test status
Simulation time 12929795 ps
CPU time 0.57 seconds
Started Jul 17 06:41:56 PM PDT 24
Finished Jul 17 06:41:58 PM PDT 24
Peak memory 182404 kb
Host smart-cc3d8f4f-2987-464e-9ec9-ad2631695b10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254731104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_intr_test.1254731104
Directory /workspace/2.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.4241340683
Short name T531
Test name
Test status
Simulation time 59281102 ps
CPU time 0.78 seconds
Started Jul 17 06:42:00 PM PDT 24
Finished Jul 17 06:42:02 PM PDT 24
Peak memory 193180 kb
Host smart-2da91103-1381-48d2-ba8f-ff72c2f5eb92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241340683 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_ti
mer_same_csr_outstanding.4241340683
Directory /workspace/2.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_errors.1417051873
Short name T571
Test name
Test status
Simulation time 337814014 ps
CPU time 2.74 seconds
Started Jul 17 06:41:56 PM PDT 24
Finished Jul 17 06:42:01 PM PDT 24
Peak memory 197364 kb
Host smart-851cde7d-9d30-4beb-9ac5-f97f39ba8382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417051873 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_errors.1417051873
Directory /workspace/2.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_timer_tl_intg_err.1472225007
Short name T30
Test name
Test status
Simulation time 369633241 ps
CPU time 1.34 seconds
Started Jul 17 06:41:58 PM PDT 24
Finished Jul 17 06:42:01 PM PDT 24
Peak memory 195056 kb
Host smart-1c5f81e3-e8da-4cf3-ab33-ed98dda5128e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472225007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_timer_tl_in
tg_err.1472225007
Directory /workspace/2.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_timer_intr_test.4121459868
Short name T485
Test name
Test status
Simulation time 16305034 ps
CPU time 0.58 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:44 PM PDT 24
Peak memory 181896 kb
Host smart-39e69b4b-e0f1-490f-86ad-f7cdcb06456b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121459868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rv_timer_intr_test.4121459868
Directory /workspace/20.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.rv_timer_intr_test.3319582066
Short name T520
Test name
Test status
Simulation time 219633781 ps
CPU time 0.57 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:46 PM PDT 24
Peak memory 182436 kb
Host smart-d1f69b50-22c9-4b34-bd2a-b5d8a9d61624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319582066 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rv_timer_intr_test.3319582066
Directory /workspace/21.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.rv_timer_intr_test.2343656964
Short name T458
Test name
Test status
Simulation time 12324097 ps
CPU time 0.53 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:43 PM PDT 24
Peak memory 181928 kb
Host smart-e16db767-b313-4638-902b-40114ba6e2ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343656964 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rv_timer_intr_test.2343656964
Directory /workspace/22.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_timer_intr_test.310379005
Short name T561
Test name
Test status
Simulation time 43673404 ps
CPU time 0.54 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:44 PM PDT 24
Peak memory 181920 kb
Host smart-afa1e69c-64e5-4cba-870b-4752eebb3910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310379005 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rv_timer_intr_test.310379005
Directory /workspace/23.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.rv_timer_intr_test.2205686751
Short name T468
Test name
Test status
Simulation time 10835794 ps
CPU time 0.53 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:43 PM PDT 24
Peak memory 182480 kb
Host smart-65f3ddf5-55e1-43d3-9d2b-ff030e481341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205686751 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rv_timer_intr_test.2205686751
Directory /workspace/24.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.rv_timer_intr_test.2052014513
Short name T491
Test name
Test status
Simulation time 19868687 ps
CPU time 0.56 seconds
Started Jul 17 06:42:43 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182108 kb
Host smart-e0d69e79-f786-4c09-8072-c87c5d98a45e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052014513 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.rv_timer_intr_test.2052014513
Directory /workspace/25.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.rv_timer_intr_test.619977342
Short name T556
Test name
Test status
Simulation time 12859810 ps
CPU time 0.6 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182436 kb
Host smart-c655ce32-feb8-4e8b-974d-26357a9d6742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619977342 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.rv_timer_intr_test.619977342
Directory /workspace/26.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.rv_timer_intr_test.734959223
Short name T558
Test name
Test status
Simulation time 15566091 ps
CPU time 0.54 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:46 PM PDT 24
Peak memory 182120 kb
Host smart-8b4b407a-cb44-40db-91d1-6254d22b8dfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734959223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.rv_timer_intr_test.734959223
Directory /workspace/27.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.rv_timer_intr_test.1330339471
Short name T507
Test name
Test status
Simulation time 45019787 ps
CPU time 0.57 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:42 PM PDT 24
Peak memory 182400 kb
Host smart-d657a398-4485-473f-ae12-e1d3bd44bb9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330339471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.rv_timer_intr_test.1330339471
Directory /workspace/28.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.rv_timer_intr_test.4112750139
Short name T511
Test name
Test status
Simulation time 44242316 ps
CPU time 0.54 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:44 PM PDT 24
Peak memory 182116 kb
Host smart-3f23e9ae-a7ff-401e-9213-b07f16018aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112750139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.rv_timer_intr_test.4112750139
Directory /workspace/29.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_aliasing.1212410609
Short name T78
Test name
Test status
Simulation time 59125414 ps
CPU time 0.76 seconds
Started Jul 17 06:42:06 PM PDT 24
Finished Jul 17 06:42:08 PM PDT 24
Peak memory 182564 kb
Host smart-1e4a2848-0f64-4384-bcf6-434a4d1b8ee6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212410609 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_alia
sing.1212410609
Directory /workspace/3.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_bit_bash.4254685116
Short name T578
Test name
Test status
Simulation time 1181013209 ps
CPU time 3.7 seconds
Started Jul 17 06:42:00 PM PDT 24
Finished Jul 17 06:42:05 PM PDT 24
Peak memory 193680 kb
Host smart-e28a32b0-20a2-471b-8d00-7117aab29cba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254685116 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_bit_
bash.4254685116
Directory /workspace/3.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_hw_reset.535379422
Short name T84
Test name
Test status
Simulation time 19796390 ps
CPU time 0.6 seconds
Started Jul 17 06:42:06 PM PDT 24
Finished Jul 17 06:42:08 PM PDT 24
Peak memory 182568 kb
Host smart-1c193c07-a60b-413d-aea3-9ddaadc709a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535379422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_hw_re
set.535379422
Directory /workspace/3.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.229768118
Short name T500
Test name
Test status
Simulation time 105249181 ps
CPU time 1.41 seconds
Started Jul 17 06:41:59 PM PDT 24
Finished Jul 17 06:42:01 PM PDT 24
Peak memory 197476 kb
Host smart-3d393e92-bc94-4149-9fd1-0ea3e0541fe1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229768118 -assert nopostproc +UVM_TESTNAME=
rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.rv_timer_csr_mem_rw_with_rand_reset.229768118
Directory /workspace/3.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_csr_rw.3053231975
Short name T92
Test name
Test status
Simulation time 17961629 ps
CPU time 0.61 seconds
Started Jul 17 06:42:06 PM PDT 24
Finished Jul 17 06:42:08 PM PDT 24
Peak memory 182564 kb
Host smart-0cb0ccb7-ef26-4453-95eb-7554123c4f0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053231975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_csr_rw.3053231975
Directory /workspace/3.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_intr_test.1916722101
Short name T579
Test name
Test status
Simulation time 19368801 ps
CPU time 0.52 seconds
Started Jul 17 06:41:56 PM PDT 24
Finished Jul 17 06:41:58 PM PDT 24
Peak memory 181920 kb
Host smart-d75c3f0b-fc3c-4acd-b64c-821fd45addcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916722101 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_intr_test.1916722101
Directory /workspace/3.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.4241901971
Short name T509
Test name
Test status
Simulation time 48748704 ps
CPU time 0.72 seconds
Started Jul 17 06:42:01 PM PDT 24
Finished Jul 17 06:42:02 PM PDT 24
Peak memory 191504 kb
Host smart-54d879f9-4b8d-4d52-85fc-de15a94e6e23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241901971 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_ti
mer_same_csr_outstanding.4241901971
Directory /workspace/3.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_errors.657657220
Short name T478
Test name
Test status
Simulation time 497352030 ps
CPU time 2.31 seconds
Started Jul 17 06:42:06 PM PDT 24
Finished Jul 17 06:42:10 PM PDT 24
Peak memory 197352 kb
Host smart-ff826008-a2a4-46ee-8ad6-ac672673fa17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657657220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_errors.657657220
Directory /workspace/3.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_timer_tl_intg_err.2449465173
Short name T567
Test name
Test status
Simulation time 206318380 ps
CPU time 1.51 seconds
Started Jul 17 06:42:06 PM PDT 24
Finished Jul 17 06:42:09 PM PDT 24
Peak memory 195028 kb
Host smart-5cca6540-0471-4214-a6c3-7bf0e78d0a20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449465173 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_timer_tl_in
tg_err.2449465173
Directory /workspace/3.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.rv_timer_intr_test.521366708
Short name T529
Test name
Test status
Simulation time 24601921 ps
CPU time 0.53 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:43 PM PDT 24
Peak memory 181884 kb
Host smart-c642feb2-3165-44f3-9854-7ec66035628c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521366708 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.rv_timer_intr_test.521366708
Directory /workspace/30.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.rv_timer_intr_test.2849802854
Short name T489
Test name
Test status
Simulation time 18568162 ps
CPU time 0.58 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:45 PM PDT 24
Peak memory 182416 kb
Host smart-384ef8df-dbc4-47ba-ab4b-cf8fc519b3aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849802854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.rv_timer_intr_test.2849802854
Directory /workspace/31.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.rv_timer_intr_test.2017812247
Short name T480
Test name
Test status
Simulation time 14137547 ps
CPU time 0.56 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182440 kb
Host smart-5cb315f1-8266-4dfd-815c-bd46e1f46e00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017812247 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.rv_timer_intr_test.2017812247
Directory /workspace/32.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.rv_timer_intr_test.3508107838
Short name T562
Test name
Test status
Simulation time 33714206 ps
CPU time 0.56 seconds
Started Jul 17 06:42:43 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182488 kb
Host smart-08f38505-fe0e-4fa1-aa8e-f12bdca3d1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508107838 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.rv_timer_intr_test.3508107838
Directory /workspace/33.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.rv_timer_intr_test.3725545620
Short name T487
Test name
Test status
Simulation time 14305713 ps
CPU time 0.54 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:43 PM PDT 24
Peak memory 182436 kb
Host smart-bdbd1ae6-52ab-4f9b-bbd3-07d4799a51ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725545620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.rv_timer_intr_test.3725545620
Directory /workspace/34.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.rv_timer_intr_test.2874092690
Short name T538
Test name
Test status
Simulation time 115188992 ps
CPU time 0.57 seconds
Started Jul 17 06:42:43 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182444 kb
Host smart-ff176061-337d-40f3-a0ae-d1a5467dd8bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874092690 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.rv_timer_intr_test.2874092690
Directory /workspace/35.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.rv_timer_intr_test.3479911423
Short name T528
Test name
Test status
Simulation time 29056965 ps
CPU time 0.54 seconds
Started Jul 17 06:42:41 PM PDT 24
Finished Jul 17 06:42:45 PM PDT 24
Peak memory 182480 kb
Host smart-5a247318-4218-40b8-9e11-61d437e26387
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479911423 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.rv_timer_intr_test.3479911423
Directory /workspace/36.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.rv_timer_intr_test.2882029009
Short name T477
Test name
Test status
Simulation time 160048291 ps
CPU time 0.54 seconds
Started Jul 17 06:42:45 PM PDT 24
Finished Jul 17 06:42:48 PM PDT 24
Peak memory 182080 kb
Host smart-9d92029d-0480-47ac-ba20-017c94c636b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882029009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.rv_timer_intr_test.2882029009
Directory /workspace/37.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.rv_timer_intr_test.31082698
Short name T466
Test name
Test status
Simulation time 32792826 ps
CPU time 0.54 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:45 PM PDT 24
Peak memory 182404 kb
Host smart-8c442d5f-8f7a-4761-abb7-e6a8949f2a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31082698 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.rv_timer_intr_test.31082698
Directory /workspace/38.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.rv_timer_intr_test.1393737006
Short name T521
Test name
Test status
Simulation time 66828782 ps
CPU time 0.54 seconds
Started Jul 17 06:42:43 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182380 kb
Host smart-cc6176bc-02d2-4ba2-b23a-15ddfff33095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393737006 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.rv_timer_intr_test.1393737006
Directory /workspace/39.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_aliasing.1005713130
Short name T85
Test name
Test status
Simulation time 25862858 ps
CPU time 0.69 seconds
Started Jul 17 06:42:05 PM PDT 24
Finished Jul 17 06:42:07 PM PDT 24
Peak memory 182540 kb
Host smart-0d7a5656-4850-4f4c-b59a-2efa8705ec9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005713130 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_alia
sing.1005713130
Directory /workspace/4.rv_timer_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_bit_bash.3490620121
Short name T70
Test name
Test status
Simulation time 2759892754 ps
CPU time 2.72 seconds
Started Jul 17 06:42:08 PM PDT 24
Finished Jul 17 06:42:12 PM PDT 24
Peak memory 193980 kb
Host smart-45fcb2d9-15ed-44a3-adeb-1ae427abb708
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490620121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_bit_
bash.3490620121
Directory /workspace/4.rv_timer_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_hw_reset.692856868
Short name T493
Test name
Test status
Simulation time 32505456 ps
CPU time 0.61 seconds
Started Jul 17 06:42:05 PM PDT 24
Finished Jul 17 06:42:07 PM PDT 24
Peak memory 191780 kb
Host smart-91fdc9a6-c825-4c90-bf83-3699b50dbb5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692856868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_hw_re
set.692856868
Directory /workspace/4.rv_timer_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.1400935153
Short name T564
Test name
Test status
Simulation time 325668412 ps
CPU time 0.83 seconds
Started Jul 17 06:42:08 PM PDT 24
Finished Jul 17 06:42:10 PM PDT 24
Peak memory 195440 kb
Host smart-d9be7a90-8b09-4a2e-8504-139b3bfbfd6d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400935153 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.rv_timer_csr_mem_rw_with_rand_reset.1400935153
Directory /workspace/4.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_csr_rw.2553687061
Short name T93
Test name
Test status
Simulation time 14467549 ps
CPU time 0.55 seconds
Started Jul 17 06:42:08 PM PDT 24
Finished Jul 17 06:42:10 PM PDT 24
Peak memory 182568 kb
Host smart-205a6e9c-08b2-412b-9f9a-b6be5be52085
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553687061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_csr_rw.2553687061
Directory /workspace/4.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_intr_test.3967874378
Short name T479
Test name
Test status
Simulation time 11131666 ps
CPU time 0.54 seconds
Started Jul 17 06:42:07 PM PDT 24
Finished Jul 17 06:42:08 PM PDT 24
Peak memory 182484 kb
Host smart-7b94e45a-5558-4fee-b2d9-1f1684b32237
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967874378 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_intr_test.3967874378
Directory /workspace/4.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.771660093
Short name T572
Test name
Test status
Simulation time 16347035 ps
CPU time 0.69 seconds
Started Jul 17 06:42:07 PM PDT 24
Finished Jul 17 06:42:09 PM PDT 24
Peak memory 192140 kb
Host smart-04161134-365e-493b-85db-ef82bb0c3812
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771660093 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_tim
er_same_csr_outstanding.771660093
Directory /workspace/4.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_errors.1419535399
Short name T467
Test name
Test status
Simulation time 19676924 ps
CPU time 0.94 seconds
Started Jul 17 06:41:56 PM PDT 24
Finished Jul 17 06:41:59 PM PDT 24
Peak memory 196272 kb
Host smart-96fc616d-a312-478d-93e2-f2e5fd4a993f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419535399 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_errors.1419535399
Directory /workspace/4.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_timer_tl_intg_err.4216451214
Short name T540
Test name
Test status
Simulation time 188040904 ps
CPU time 0.85 seconds
Started Jul 17 06:42:07 PM PDT 24
Finished Jul 17 06:42:10 PM PDT 24
Peak memory 193844 kb
Host smart-8ec4417b-fcf8-4d12-a480-e6de9d2a3735
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216451214 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_timer_tl_in
tg_err.4216451214
Directory /workspace/4.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.rv_timer_intr_test.1756825179
Short name T535
Test name
Test status
Simulation time 13320757 ps
CPU time 0.55 seconds
Started Jul 17 06:42:40 PM PDT 24
Finished Jul 17 06:42:42 PM PDT 24
Peak memory 182076 kb
Host smart-575cf56d-d848-43f8-a087-4afb41758f51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756825179 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.rv_timer_intr_test.1756825179
Directory /workspace/40.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.rv_timer_intr_test.342241935
Short name T464
Test name
Test status
Simulation time 42041887 ps
CPU time 0.56 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:46 PM PDT 24
Peak memory 182444 kb
Host smart-b3101bb4-c71f-47a9-b399-31e2eeb1be8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342241935 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.rv_timer_intr_test.342241935
Directory /workspace/41.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.rv_timer_intr_test.2868978092
Short name T469
Test name
Test status
Simulation time 12691282 ps
CPU time 0.58 seconds
Started Jul 17 06:42:42 PM PDT 24
Finished Jul 17 06:42:47 PM PDT 24
Peak memory 182376 kb
Host smart-dc9c5358-55a3-4a6f-9041-fe129ebd73dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868978092 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.rv_timer_intr_test.2868978092
Directory /workspace/42.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.rv_timer_intr_test.592170353
Short name T541
Test name
Test status
Simulation time 121607147 ps
CPU time 0.56 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:42:54 PM PDT 24
Peak memory 182120 kb
Host smart-7c3b6ed0-d36a-4bfb-8ff4-54d6ce92e921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592170353 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.rv_timer_intr_test.592170353
Directory /workspace/43.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.rv_timer_intr_test.537449621
Short name T514
Test name
Test status
Simulation time 26975907 ps
CPU time 0.59 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:42:54 PM PDT 24
Peak memory 182360 kb
Host smart-f1059afd-0e6b-4486-8ba8-c44e9fb7c9c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537449621 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.rv_timer_intr_test.537449621
Directory /workspace/44.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.rv_timer_intr_test.3990821891
Short name T463
Test name
Test status
Simulation time 12140957 ps
CPU time 0.56 seconds
Started Jul 17 06:42:49 PM PDT 24
Finished Jul 17 06:42:51 PM PDT 24
Peak memory 182088 kb
Host smart-991d4721-4e53-49a7-8c92-045445128a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990821891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.rv_timer_intr_test.3990821891
Directory /workspace/45.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.rv_timer_intr_test.4062702085
Short name T459
Test name
Test status
Simulation time 50570321 ps
CPU time 0.54 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:42:55 PM PDT 24
Peak memory 182420 kb
Host smart-68910030-f76a-422f-9f66-8e79676adf40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062702085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.rv_timer_intr_test.4062702085
Directory /workspace/46.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.rv_timer_intr_test.2025338439
Short name T501
Test name
Test status
Simulation time 18202103 ps
CPU time 0.53 seconds
Started Jul 17 06:42:51 PM PDT 24
Finished Jul 17 06:42:52 PM PDT 24
Peak memory 181928 kb
Host smart-919d555d-7021-4e99-afb3-450586917c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025338439 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.rv_timer_intr_test.2025338439
Directory /workspace/47.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.rv_timer_intr_test.1522322891
Short name T472
Test name
Test status
Simulation time 12707774 ps
CPU time 0.55 seconds
Started Jul 17 06:42:50 PM PDT 24
Finished Jul 17 06:42:52 PM PDT 24
Peak memory 181892 kb
Host smart-244b378d-2c4b-43e0-a384-c64ef9a2bea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522322891 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.rv_timer_intr_test.1522322891
Directory /workspace/48.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.rv_timer_intr_test.25123677
Short name T462
Test name
Test status
Simulation time 17975104 ps
CPU time 0.59 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:42:54 PM PDT 24
Peak memory 182460 kb
Host smart-f256f80b-ce2b-4bdb-ba8c-8e680cf8b58e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25123677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.rv_timer_intr_test.25123677
Directory /workspace/49.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_mem_rw_with_rand_reset.1200177897
Short name T536
Test name
Test status
Simulation time 38711456 ps
CPU time 0.88 seconds
Started Jul 17 06:42:08 PM PDT 24
Finished Jul 17 06:42:10 PM PDT 24
Peak memory 196436 kb
Host smart-f1ec0d08-34ea-4f0b-b818-2524b5702fa1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200177897 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.rv_timer_csr_mem_rw_with_rand_reset.1200177897
Directory /workspace/5.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_csr_rw.2362313899
Short name T94
Test name
Test status
Simulation time 23589831 ps
CPU time 0.6 seconds
Started Jul 17 06:42:08 PM PDT 24
Finished Jul 17 06:42:10 PM PDT 24
Peak memory 182548 kb
Host smart-98d9e416-a59d-40ff-8b45-59c70afb40db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362313899 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_csr_rw.2362313899
Directory /workspace/5.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_intr_test.1625168169
Short name T470
Test name
Test status
Simulation time 40668806 ps
CPU time 0.54 seconds
Started Jul 17 06:42:09 PM PDT 24
Finished Jul 17 06:42:11 PM PDT 24
Peak memory 182120 kb
Host smart-1babcddf-6257-4c4d-bea3-2e40b8f2d8eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625168169 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_intr_test.1625168169
Directory /workspace/5.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_same_csr_outstanding.3566619328
Short name T542
Test name
Test status
Simulation time 71700399 ps
CPU time 0.79 seconds
Started Jul 17 06:42:06 PM PDT 24
Finished Jul 17 06:42:08 PM PDT 24
Peak memory 191520 kb
Host smart-f4ee5088-b476-4277-9bf9-3b2e9763815b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566619328 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_ti
mer_same_csr_outstanding.3566619328
Directory /workspace/5.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_errors.3497997028
Short name T504
Test name
Test status
Simulation time 373875917 ps
CPU time 1.77 seconds
Started Jul 17 06:42:07 PM PDT 24
Finished Jul 17 06:42:10 PM PDT 24
Peak memory 197336 kb
Host smart-1d7d735b-55b8-4e86-8940-f2d9232a1d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497997028 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_errors.3497997028
Directory /workspace/5.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2733833694
Short name T570
Test name
Test status
Simulation time 136713726 ps
CPU time 0.79 seconds
Started Jul 17 06:42:08 PM PDT 24
Finished Jul 17 06:42:10 PM PDT 24
Peak memory 193420 kb
Host smart-e31120ca-4b19-4dc1-8373-fbd9064fc3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733833694 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_timer_tl_in
tg_err.2733833694
Directory /workspace/5.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_mem_rw_with_rand_reset.1466899408
Short name T565
Test name
Test status
Simulation time 58218277 ps
CPU time 0.89 seconds
Started Jul 17 06:42:16 PM PDT 24
Finished Jul 17 06:42:17 PM PDT 24
Peak memory 196476 kb
Host smart-6af6c3f1-4a25-47bb-8d95-79b14f26dbca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466899408 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.rv_timer_csr_mem_rw_with_rand_reset.1466899408
Directory /workspace/6.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_csr_rw.2833729869
Short name T533
Test name
Test status
Simulation time 38889007 ps
CPU time 0.54 seconds
Started Jul 17 06:42:06 PM PDT 24
Finished Jul 17 06:42:08 PM PDT 24
Peak memory 182392 kb
Host smart-518978db-c898-4573-89e3-8f07eb1aa337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833729869 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_csr_rw.2833729869
Directory /workspace/6.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_intr_test.3934979742
Short name T495
Test name
Test status
Simulation time 11622982 ps
CPU time 0.56 seconds
Started Jul 17 06:42:06 PM PDT 24
Finished Jul 17 06:42:07 PM PDT 24
Peak memory 182124 kb
Host smart-7e06b247-2740-4444-8817-2b2a3d42ac92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934979742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_intr_test.3934979742
Directory /workspace/6.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_same_csr_outstanding.49103094
Short name T498
Test name
Test status
Simulation time 28738820 ps
CPU time 0.66 seconds
Started Jul 17 06:42:15 PM PDT 24
Finished Jul 17 06:42:16 PM PDT 24
Peak memory 191796 kb
Host smart-790ec607-5bab-45ab-9dc7-9eada1307fac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49103094 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_
timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_time
r_same_csr_outstanding.49103094
Directory /workspace/6.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_errors.748433883
Short name T508
Test name
Test status
Simulation time 447846318 ps
CPU time 2.44 seconds
Started Jul 17 06:42:08 PM PDT 24
Finished Jul 17 06:42:12 PM PDT 24
Peak memory 197328 kb
Host smart-74521976-9881-4b00-9a89-ac11291fbb25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748433883 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_errors.748433883
Directory /workspace/6.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_timer_tl_intg_err.2368580924
Short name T96
Test name
Test status
Simulation time 138586572 ps
CPU time 1.39 seconds
Started Jul 17 06:42:07 PM PDT 24
Finished Jul 17 06:42:10 PM PDT 24
Peak memory 182948 kb
Host smart-aa83c3d5-062f-4184-92dd-46433e97dc97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368580924 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_timer_tl_in
tg_err.2368580924
Directory /workspace/6.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_mem_rw_with_rand_reset.2056634756
Short name T527
Test name
Test status
Simulation time 85694451 ps
CPU time 0.76 seconds
Started Jul 17 06:42:16 PM PDT 24
Finished Jul 17 06:42:18 PM PDT 24
Peak memory 195468 kb
Host smart-3cd49da9-3189-4349-8625-ea597030a0e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056634756 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.rv_timer_csr_mem_rw_with_rand_reset.2056634756
Directory /workspace/7.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_csr_rw.1270644081
Short name T77
Test name
Test status
Simulation time 54824815 ps
CPU time 0.59 seconds
Started Jul 17 06:42:15 PM PDT 24
Finished Jul 17 06:42:17 PM PDT 24
Peak memory 182536 kb
Host smart-ffabc1f2-587f-4705-96a9-15a4818d4630
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270644081 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_csr_rw.1270644081
Directory /workspace/7.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_intr_test.210677564
Short name T555
Test name
Test status
Simulation time 45506512 ps
CPU time 0.54 seconds
Started Jul 17 06:42:16 PM PDT 24
Finished Jul 17 06:42:18 PM PDT 24
Peak memory 182416 kb
Host smart-04ea5caf-4379-45a3-a12f-82e9940f69d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210677564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_intr_test.210677564
Directory /workspace/7.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_same_csr_outstanding.1859518509
Short name T552
Test name
Test status
Simulation time 70735949 ps
CPU time 0.82 seconds
Started Jul 17 06:42:15 PM PDT 24
Finished Jul 17 06:42:17 PM PDT 24
Peak memory 193428 kb
Host smart-240581eb-2593-46ab-af0a-5d78a5bfe591
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859518509 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_ti
mer_same_csr_outstanding.1859518509
Directory /workspace/7.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_errors.640267297
Short name T557
Test name
Test status
Simulation time 115199480 ps
CPU time 2.33 seconds
Started Jul 17 06:42:16 PM PDT 24
Finished Jul 17 06:42:20 PM PDT 24
Peak memory 197304 kb
Host smart-c327c36e-3627-424f-accf-b1b413298c26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640267297 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_errors.640267297
Directory /workspace/7.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_timer_tl_intg_err.1215842402
Short name T99
Test name
Test status
Simulation time 97998796 ps
CPU time 1.38 seconds
Started Jul 17 06:42:15 PM PDT 24
Finished Jul 17 06:42:17 PM PDT 24
Peak memory 194820 kb
Host smart-0e5cbb91-a32a-436c-9fd5-a32b1bcb1b93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215842402 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_timer_tl_in
tg_err.1215842402
Directory /workspace/7.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_mem_rw_with_rand_reset.3120100375
Short name T52
Test name
Test status
Simulation time 119970775 ps
CPU time 0.81 seconds
Started Jul 17 06:42:17 PM PDT 24
Finished Jul 17 06:42:19 PM PDT 24
Peak memory 196276 kb
Host smart-7e7e1bcb-43c8-47ae-bed3-17e6654c5d5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120100375 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.rv_timer_csr_mem_rw_with_rand_reset.3120100375
Directory /workspace/8.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_csr_rw.3509123455
Short name T31
Test name
Test status
Simulation time 13579892 ps
CPU time 0.6 seconds
Started Jul 17 06:42:24 PM PDT 24
Finished Jul 17 06:42:25 PM PDT 24
Peak memory 182564 kb
Host smart-6434f909-47c4-421c-adb1-7610ffac6bfe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509123455 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_csr_rw.3509123455
Directory /workspace/8.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_intr_test.2576169426
Short name T474
Test name
Test status
Simulation time 72193896 ps
CPU time 0.6 seconds
Started Jul 17 06:42:16 PM PDT 24
Finished Jul 17 06:42:18 PM PDT 24
Peak memory 182488 kb
Host smart-f41439b7-0e5a-4b14-b510-87ebad24630d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576169426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_intr_test.2576169426
Directory /workspace/8.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_same_csr_outstanding.1694676617
Short name T68
Test name
Test status
Simulation time 40092099 ps
CPU time 0.76 seconds
Started Jul 17 06:42:17 PM PDT 24
Finished Jul 17 06:42:19 PM PDT 24
Peak memory 191712 kb
Host smart-a0971e7c-56c8-44ad-8c27-fc94c6224247
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694676617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_ti
mer_same_csr_outstanding.1694676617
Directory /workspace/8.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_errors.3014007464
Short name T566
Test name
Test status
Simulation time 73723126 ps
CPU time 1.02 seconds
Started Jul 17 06:42:15 PM PDT 24
Finished Jul 17 06:42:17 PM PDT 24
Peak memory 196392 kb
Host smart-31b05685-4063-4953-9c45-b177e8804766
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014007464 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_errors.3014007464
Directory /workspace/8.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_timer_tl_intg_err.2566004550
Short name T569
Test name
Test status
Simulation time 411321053 ps
CPU time 1.39 seconds
Started Jul 17 06:42:16 PM PDT 24
Finished Jul 17 06:42:19 PM PDT 24
Peak memory 183244 kb
Host smart-c3498c21-d19d-437f-ae1e-77198e03f13d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566004550 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_timer_tl_in
tg_err.2566004550
Directory /workspace/8.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_mem_rw_with_rand_reset.3463179671
Short name T456
Test name
Test status
Simulation time 24583384 ps
CPU time 0.74 seconds
Started Jul 17 06:42:24 PM PDT 24
Finished Jul 17 06:42:25 PM PDT 24
Peak memory 195316 kb
Host smart-a4107b04-9321-4707-b964-2962363b531e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463179671 -assert nopostproc +UVM_TESTNAME
=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.rv_timer_csr_mem_rw_with_rand_reset.3463179671
Directory /workspace/9.rv_timer_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_csr_rw.4183493796
Short name T526
Test name
Test status
Simulation time 18514772 ps
CPU time 0.58 seconds
Started Jul 17 06:42:20 PM PDT 24
Finished Jul 17 06:42:21 PM PDT 24
Peak memory 182564 kb
Host smart-5c9cafe4-f233-4318-b037-7041329b0cc4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183493796 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_csr_rw.4183493796
Directory /workspace/9.rv_timer_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_intr_test.1482038890
Short name T543
Test name
Test status
Simulation time 25562553 ps
CPU time 0.54 seconds
Started Jul 17 06:42:16 PM PDT 24
Finished Jul 17 06:42:18 PM PDT 24
Peak memory 182404 kb
Host smart-6257c07d-dc20-4100-8203-43de0a55f94e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482038890 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_intr_test.1482038890
Directory /workspace/9.rv_timer_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_same_csr_outstanding.2734067085
Short name T90
Test name
Test status
Simulation time 51406783 ps
CPU time 0.61 seconds
Started Jul 17 06:42:17 PM PDT 24
Finished Jul 17 06:42:19 PM PDT 24
Peak memory 191780 kb
Host smart-917f3932-15e6-4861-a2fe-0e9a7507591c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734067085 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_ti
mer_same_csr_outstanding.2734067085
Directory /workspace/9.rv_timer_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_errors.700242739
Short name T550
Test name
Test status
Simulation time 138044478 ps
CPU time 2.81 seconds
Started Jul 17 06:42:16 PM PDT 24
Finished Jul 17 06:42:20 PM PDT 24
Peak memory 197296 kb
Host smart-832ece35-6256-427a-802d-3ca774c50d78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700242739 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_errors.700242739
Directory /workspace/9.rv_timer_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1811015988
Short name T97
Test name
Test status
Simulation time 494928599 ps
CPU time 1.35 seconds
Started Jul 17 06:42:17 PM PDT 24
Finished Jul 17 06:42:20 PM PDT 24
Peak memory 183336 kb
Host smart-230d02ac-6c6c-4e01-832c-7b574ebdae9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811015988 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_timer_tl_in
tg_err.1811015988
Directory /workspace/9.rv_timer_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_timer_disabled.2899069825
Short name T368
Test name
Test status
Simulation time 179391598592 ps
CPU time 279.7 seconds
Started Jul 17 06:42:51 PM PDT 24
Finished Jul 17 06:47:31 PM PDT 24
Peak memory 183144 kb
Host smart-d288bac2-b86b-4bea-81a6-b669e1ed5f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899069825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_disabled.2899069825
Directory /workspace/0.rv_timer_disabled/latest

Test location /workspace/coverage/default/0.rv_timer_random.170468197
Short name T348
Test name
Test status
Simulation time 15089418001 ps
CPU time 33.79 seconds
Started Jul 17 06:42:51 PM PDT 24
Finished Jul 17 06:43:26 PM PDT 24
Peak memory 191308 kb
Host smart-c5bdc995-c096-4c84-b6ac-dc32627372e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170468197 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_timer_random.170468197
Directory /workspace/0.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_cfg_update_on_fly.1258342078
Short name T42
Test name
Test status
Simulation time 106161417996 ps
CPU time 105.45 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:44:42 PM PDT 24
Peak memory 183136 kb
Host smart-b974aad8-e161-4b02-b7c8-fa08a412921e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258342078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.rv_timer_cfg_update_on_fly.1258342078
Directory /workspace/1.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/1.rv_timer_disabled.3518644598
Short name T377
Test name
Test status
Simulation time 22948382708 ps
CPU time 31.12 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:43:25 PM PDT 24
Peak memory 183144 kb
Host smart-23ef0b64-ad0d-4cf0-b4d4-4e07167ea19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518644598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_disabled.3518644598
Directory /workspace/1.rv_timer_disabled/latest

Test location /workspace/coverage/default/1.rv_timer_random.3977888898
Short name T327
Test name
Test status
Simulation time 67483564740 ps
CPU time 139.9 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:45:13 PM PDT 24
Peak memory 191344 kb
Host smart-9c1c1bb1-f332-4411-918f-cecfa42a9f68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977888898 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_random.3977888898
Directory /workspace/1.rv_timer_random/latest

Test location /workspace/coverage/default/1.rv_timer_sec_cm.2672483644
Short name T15
Test name
Test status
Simulation time 183077977 ps
CPU time 0.94 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:42:58 PM PDT 24
Peak memory 214476 kb
Host smart-dacef806-8c98-4915-967f-2c0cbdb80a6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672483644 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_sec_cm.2672483644
Directory /workspace/1.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/1.rv_timer_stress_all.2594340648
Short name T183
Test name
Test status
Simulation time 2947472411200 ps
CPU time 3887.65 seconds
Started Jul 17 06:42:51 PM PDT 24
Finished Jul 17 07:47:40 PM PDT 24
Peak memory 194976 kb
Host smart-32fdf998-d9c4-4cd7-8e9d-90508a71bca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594340648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_timer_stress_all.
2594340648
Directory /workspace/1.rv_timer_stress_all/latest

Test location /workspace/coverage/default/10.rv_timer_disabled.3061756728
Short name T392
Test name
Test status
Simulation time 138052575594 ps
CPU time 181.07 seconds
Started Jul 17 06:43:05 PM PDT 24
Finished Jul 17 06:46:08 PM PDT 24
Peak memory 183092 kb
Host smart-92154910-e391-498e-bdd7-c175ce609a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061756728 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_disabled.3061756728
Directory /workspace/10.rv_timer_disabled/latest

Test location /workspace/coverage/default/10.rv_timer_random.3773134294
Short name T268
Test name
Test status
Simulation time 423176613227 ps
CPU time 845.95 seconds
Started Jul 17 06:43:06 PM PDT 24
Finished Jul 17 06:57:13 PM PDT 24
Peak memory 191300 kb
Host smart-e98e6980-e9eb-411e-929d-3bfc08335910
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773134294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_timer_random.3773134294
Directory /workspace/10.rv_timer_random/latest

Test location /workspace/coverage/default/100.rv_timer_random.564056882
Short name T339
Test name
Test status
Simulation time 431049763953 ps
CPU time 617.13 seconds
Started Jul 17 06:45:13 PM PDT 24
Finished Jul 17 06:55:31 PM PDT 24
Peak memory 191560 kb
Host smart-34348701-7e09-4636-a9b6-6112c0e957a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564056882 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.rv_timer_random.564056882
Directory /workspace/100.rv_timer_random/latest

Test location /workspace/coverage/default/101.rv_timer_random.748291213
Short name T359
Test name
Test status
Simulation time 61663627993 ps
CPU time 47.96 seconds
Started Jul 17 06:45:11 PM PDT 24
Finished Jul 17 06:45:59 PM PDT 24
Peak memory 182996 kb
Host smart-03471311-0194-4639-8626-7e7608e667b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748291213 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.rv_timer_random.748291213
Directory /workspace/101.rv_timer_random/latest

Test location /workspace/coverage/default/102.rv_timer_random.4164030907
Short name T335
Test name
Test status
Simulation time 32245124170 ps
CPU time 31.49 seconds
Started Jul 17 06:45:11 PM PDT 24
Finished Jul 17 06:45:43 PM PDT 24
Peak memory 183144 kb
Host smart-a4e35a48-ab0d-4a66-933a-29a183725721
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164030907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.rv_timer_random.4164030907
Directory /workspace/102.rv_timer_random/latest

Test location /workspace/coverage/default/104.rv_timer_random.1630106243
Short name T428
Test name
Test status
Simulation time 119229045520 ps
CPU time 252.9 seconds
Started Jul 17 06:45:13 PM PDT 24
Finished Jul 17 06:49:26 PM PDT 24
Peak memory 191280 kb
Host smart-a2d05d3b-87cb-4e92-a5bc-1079e6906565
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630106243 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.rv_timer_random.1630106243
Directory /workspace/104.rv_timer_random/latest

Test location /workspace/coverage/default/106.rv_timer_random.2311488832
Short name T156
Test name
Test status
Simulation time 30147179684 ps
CPU time 50.45 seconds
Started Jul 17 06:45:21 PM PDT 24
Finished Jul 17 06:46:12 PM PDT 24
Peak memory 191340 kb
Host smart-c7cc9aa8-1585-4c3a-879f-5f3036413b04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311488832 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.rv_timer_random.2311488832
Directory /workspace/106.rv_timer_random/latest

Test location /workspace/coverage/default/107.rv_timer_random.2840355566
Short name T148
Test name
Test status
Simulation time 140900657210 ps
CPU time 253.67 seconds
Started Jul 17 06:45:20 PM PDT 24
Finished Jul 17 06:49:34 PM PDT 24
Peak memory 194444 kb
Host smart-8524f84b-6977-488b-9773-3e11d6ed5490
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840355566 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.rv_timer_random.2840355566
Directory /workspace/107.rv_timer_random/latest

Test location /workspace/coverage/default/109.rv_timer_random.1543928064
Short name T336
Test name
Test status
Simulation time 1778820655295 ps
CPU time 280.27 seconds
Started Jul 17 06:45:21 PM PDT 24
Finished Jul 17 06:50:02 PM PDT 24
Peak memory 191348 kb
Host smart-7e9a6ba9-0ed8-40d4-ab1b-8da6b3111813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543928064 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.rv_timer_random.1543928064
Directory /workspace/109.rv_timer_random/latest

Test location /workspace/coverage/default/11.rv_timer_cfg_update_on_fly.675539272
Short name T229
Test name
Test status
Simulation time 277618779820 ps
CPU time 478.77 seconds
Started Jul 17 06:43:03 PM PDT 24
Finished Jul 17 06:51:04 PM PDT 24
Peak memory 183136 kb
Host smart-f91930af-6f0f-4148-9b1e-7463bc8df085
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675539272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.rv_timer_cfg_update_on_fly.675539272
Directory /workspace/11.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/11.rv_timer_disabled.2311540880
Short name T23
Test name
Test status
Simulation time 247348543675 ps
CPU time 91.83 seconds
Started Jul 17 06:43:03 PM PDT 24
Finished Jul 17 06:44:38 PM PDT 24
Peak memory 183328 kb
Host smart-b5b28635-e176-4a81-bb12-2e3c542b89e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311540880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_disabled.2311540880
Directory /workspace/11.rv_timer_disabled/latest

Test location /workspace/coverage/default/11.rv_timer_random_reset.513923799
Short name T237
Test name
Test status
Simulation time 61171057052 ps
CPU time 709.68 seconds
Started Jul 17 06:43:04 PM PDT 24
Finished Jul 17 06:54:56 PM PDT 24
Peak memory 193608 kb
Host smart-7940a39c-ef66-4de0-8182-775772de9177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513923799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_random_reset.513923799
Directory /workspace/11.rv_timer_random_reset/latest

Test location /workspace/coverage/default/11.rv_timer_stress_all.559360907
Short name T439
Test name
Test status
Simulation time 696810018094 ps
CPU time 264.99 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 06:47:28 PM PDT 24
Peak memory 183144 kb
Host smart-84b35b4b-3ad2-4042-99ac-a0f2d6e0bdd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559360907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_timer_stress_all.
559360907
Directory /workspace/11.rv_timer_stress_all/latest

Test location /workspace/coverage/default/112.rv_timer_random.3691413716
Short name T298
Test name
Test status
Simulation time 205168566385 ps
CPU time 150.3 seconds
Started Jul 17 06:45:22 PM PDT 24
Finished Jul 17 06:47:53 PM PDT 24
Peak memory 183252 kb
Host smart-a1952afb-b995-47b2-8b8f-918e9e045e30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691413716 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.rv_timer_random.3691413716
Directory /workspace/112.rv_timer_random/latest

Test location /workspace/coverage/default/113.rv_timer_random.1794116143
Short name T127
Test name
Test status
Simulation time 112974176281 ps
CPU time 390.41 seconds
Started Jul 17 06:45:22 PM PDT 24
Finished Jul 17 06:51:53 PM PDT 24
Peak memory 194572 kb
Host smart-16630e2c-e0c9-4a09-bf32-89fd90baee6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794116143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.rv_timer_random.1794116143
Directory /workspace/113.rv_timer_random/latest

Test location /workspace/coverage/default/117.rv_timer_random.1942129188
Short name T449
Test name
Test status
Simulation time 425905024299 ps
CPU time 81.92 seconds
Started Jul 17 06:45:21 PM PDT 24
Finished Jul 17 06:46:44 PM PDT 24
Peak memory 191344 kb
Host smart-2c046c67-c1ff-4207-9ff5-5c287f85021a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942129188 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.rv_timer_random.1942129188
Directory /workspace/117.rv_timer_random/latest

Test location /workspace/coverage/default/118.rv_timer_random.3199673023
Short name T246
Test name
Test status
Simulation time 167665995732 ps
CPU time 783.08 seconds
Started Jul 17 06:45:32 PM PDT 24
Finished Jul 17 06:58:36 PM PDT 24
Peak memory 191296 kb
Host smart-0a259b5d-db68-4afe-9926-fa662b5e8532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199673023 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.rv_timer_random.3199673023
Directory /workspace/118.rv_timer_random/latest

Test location /workspace/coverage/default/119.rv_timer_random.2161640840
Short name T309
Test name
Test status
Simulation time 83292381962 ps
CPU time 136.03 seconds
Started Jul 17 06:45:31 PM PDT 24
Finished Jul 17 06:47:48 PM PDT 24
Peak memory 191352 kb
Host smart-7aa2c864-fcb2-4e52-b8a5-f1e7c9aaf779
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161640840 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.rv_timer_random.2161640840
Directory /workspace/119.rv_timer_random/latest

Test location /workspace/coverage/default/12.rv_timer_disabled.1159957264
Short name T410
Test name
Test status
Simulation time 87236239558 ps
CPU time 131.14 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 06:45:16 PM PDT 24
Peak memory 183108 kb
Host smart-66f0e58f-e341-45c4-97e5-b0ae95ad9765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159957264 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_disabled.1159957264
Directory /workspace/12.rv_timer_disabled/latest

Test location /workspace/coverage/default/12.rv_timer_random_reset.365416231
Short name T313
Test name
Test status
Simulation time 296606911830 ps
CPU time 128.6 seconds
Started Jul 17 06:43:03 PM PDT 24
Finished Jul 17 06:45:13 PM PDT 24
Peak memory 183140 kb
Host smart-4a303aa2-bfc0-47c2-b641-e44ca30da738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365416231 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_random_reset.365416231
Directory /workspace/12.rv_timer_random_reset/latest

Test location /workspace/coverage/default/12.rv_timer_stress_all.3766176267
Short name T292
Test name
Test status
Simulation time 1311021200470 ps
CPU time 1028.04 seconds
Started Jul 17 06:43:06 PM PDT 24
Finished Jul 17 07:00:16 PM PDT 24
Peak memory 191280 kb
Host smart-96d17164-f8ac-4169-ab7a-3e88de92cca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766176267 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_timer_stress_all
.3766176267
Directory /workspace/12.rv_timer_stress_all/latest

Test location /workspace/coverage/default/121.rv_timer_random.2854157897
Short name T302
Test name
Test status
Simulation time 173988177933 ps
CPU time 377.75 seconds
Started Jul 17 06:45:33 PM PDT 24
Finished Jul 17 06:51:51 PM PDT 24
Peak memory 183144 kb
Host smart-c1f587b3-c446-4b7a-9c49-72813c850344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854157897 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.rv_timer_random.2854157897
Directory /workspace/121.rv_timer_random/latest

Test location /workspace/coverage/default/122.rv_timer_random.2867448145
Short name T182
Test name
Test status
Simulation time 229982324067 ps
CPU time 212.9 seconds
Started Jul 17 06:52:39 PM PDT 24
Finished Jul 17 06:56:14 PM PDT 24
Peak memory 191344 kb
Host smart-83b232c0-575a-4a64-a0a5-661ac7025f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867448145 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.rv_timer_random.2867448145
Directory /workspace/122.rv_timer_random/latest

Test location /workspace/coverage/default/123.rv_timer_random.992547655
Short name T263
Test name
Test status
Simulation time 18815752535 ps
CPU time 16.08 seconds
Started Jul 17 06:45:33 PM PDT 24
Finished Jul 17 06:45:50 PM PDT 24
Peak memory 183088 kb
Host smart-05eded70-5d48-4910-a61e-1e829b6813f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992547655 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.rv_timer_random.992547655
Directory /workspace/123.rv_timer_random/latest

Test location /workspace/coverage/default/124.rv_timer_random.3075178121
Short name T325
Test name
Test status
Simulation time 28519706736 ps
CPU time 63.93 seconds
Started Jul 17 06:45:33 PM PDT 24
Finished Jul 17 06:46:38 PM PDT 24
Peak memory 191260 kb
Host smart-e91991f5-a422-4472-97b3-28024a2bb08c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075178121 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.rv_timer_random.3075178121
Directory /workspace/124.rv_timer_random/latest

Test location /workspace/coverage/default/125.rv_timer_random.114695422
Short name T329
Test name
Test status
Simulation time 31379625260 ps
CPU time 47.6 seconds
Started Jul 17 06:45:33 PM PDT 24
Finished Jul 17 06:46:21 PM PDT 24
Peak memory 183152 kb
Host smart-273e9400-5dc5-4a32-a297-abb9d34ffeb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114695422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.rv_timer_random.114695422
Directory /workspace/125.rv_timer_random/latest

Test location /workspace/coverage/default/126.rv_timer_random.121371516
Short name T293
Test name
Test status
Simulation time 595454392733 ps
CPU time 794.26 seconds
Started Jul 17 06:45:32 PM PDT 24
Finished Jul 17 06:58:46 PM PDT 24
Peak memory 191348 kb
Host smart-99d4153b-5a10-463b-9032-c5164c91787a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121371516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.rv_timer_random.121371516
Directory /workspace/126.rv_timer_random/latest

Test location /workspace/coverage/default/127.rv_timer_random.1604336972
Short name T301
Test name
Test status
Simulation time 194922041374 ps
CPU time 148.06 seconds
Started Jul 17 06:45:33 PM PDT 24
Finished Jul 17 06:48:02 PM PDT 24
Peak memory 192372 kb
Host smart-1e979d6e-a671-4564-aa83-3781f81d364b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604336972 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.rv_timer_random.1604336972
Directory /workspace/127.rv_timer_random/latest

Test location /workspace/coverage/default/128.rv_timer_random.3770958434
Short name T356
Test name
Test status
Simulation time 96428140677 ps
CPU time 535.25 seconds
Started Jul 17 06:45:33 PM PDT 24
Finished Jul 17 06:54:28 PM PDT 24
Peak memory 183136 kb
Host smart-03c1d881-a06b-4a46-adac-6ef333103fbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770958434 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.rv_timer_random.3770958434
Directory /workspace/128.rv_timer_random/latest

Test location /workspace/coverage/default/129.rv_timer_random.2222534986
Short name T437
Test name
Test status
Simulation time 31459789773 ps
CPU time 108.24 seconds
Started Jul 17 06:45:46 PM PDT 24
Finished Jul 17 06:47:35 PM PDT 24
Peak memory 191352 kb
Host smart-c2c0d58a-1ef4-4b8a-ab11-e965beaeae4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222534986 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.rv_timer_random.2222534986
Directory /workspace/129.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_disabled.90043134
Short name T429
Test name
Test status
Simulation time 46532321979 ps
CPU time 18.92 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 06:43:23 PM PDT 24
Peak memory 183140 kb
Host smart-026dba80-688c-48f7-a80d-87b3240cfa35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90043134 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_disabled.90043134
Directory /workspace/13.rv_timer_disabled/latest

Test location /workspace/coverage/default/13.rv_timer_random.3565655799
Short name T111
Test name
Test status
Simulation time 433030999094 ps
CPU time 98.04 seconds
Started Jul 17 06:43:03 PM PDT 24
Finished Jul 17 06:44:43 PM PDT 24
Peak memory 191304 kb
Host smart-b68e5fc4-ac78-4f61-b806-74894390f99f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565655799 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random.3565655799
Directory /workspace/13.rv_timer_random/latest

Test location /workspace/coverage/default/13.rv_timer_random_reset.2948189686
Short name T402
Test name
Test status
Simulation time 339288071 ps
CPU time 1.83 seconds
Started Jul 17 06:43:05 PM PDT 24
Finished Jul 17 06:43:09 PM PDT 24
Peak memory 183088 kb
Host smart-413dc870-ce2e-4897-b21f-3e1ebe3b069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948189686 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_timer_random_reset.2948189686
Directory /workspace/13.rv_timer_random_reset/latest

Test location /workspace/coverage/default/130.rv_timer_random.2742866146
Short name T235
Test name
Test status
Simulation time 83710176219 ps
CPU time 88.17 seconds
Started Jul 17 06:45:46 PM PDT 24
Finished Jul 17 06:47:14 PM PDT 24
Peak memory 183156 kb
Host smart-5cc37e3c-2c7d-4339-a1fe-b08fa370c5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742866146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.rv_timer_random.2742866146
Directory /workspace/130.rv_timer_random/latest

Test location /workspace/coverage/default/132.rv_timer_random.4201152993
Short name T261
Test name
Test status
Simulation time 452251033098 ps
CPU time 155.52 seconds
Started Jul 17 06:45:46 PM PDT 24
Finished Jul 17 06:48:22 PM PDT 24
Peak memory 191284 kb
Host smart-8cedef97-e696-4f4a-8424-6e44ced2a004
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201152993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.rv_timer_random.4201152993
Directory /workspace/132.rv_timer_random/latest

Test location /workspace/coverage/default/133.rv_timer_random.3539119276
Short name T291
Test name
Test status
Simulation time 43495168506 ps
CPU time 239.16 seconds
Started Jul 17 06:45:46 PM PDT 24
Finished Jul 17 06:49:46 PM PDT 24
Peak memory 191352 kb
Host smart-f89dd4c4-66f6-48a5-9b11-463ded36b49a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539119276 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.rv_timer_random.3539119276
Directory /workspace/133.rv_timer_random/latest

Test location /workspace/coverage/default/134.rv_timer_random.2401870417
Short name T332
Test name
Test status
Simulation time 220062142800 ps
CPU time 246.43 seconds
Started Jul 17 06:45:58 PM PDT 24
Finished Jul 17 06:50:05 PM PDT 24
Peak memory 183140 kb
Host smart-a599c57a-73cd-4bea-9f0b-22cbcbc3e08d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401870417 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.rv_timer_random.2401870417
Directory /workspace/134.rv_timer_random/latest

Test location /workspace/coverage/default/135.rv_timer_random.521623218
Short name T151
Test name
Test status
Simulation time 712198868603 ps
CPU time 738.75 seconds
Started Jul 17 06:45:55 PM PDT 24
Finished Jul 17 06:58:14 PM PDT 24
Peak memory 191316 kb
Host smart-703e1e46-ec75-4b85-a2cd-526983600683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521623218 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.rv_timer_random.521623218
Directory /workspace/135.rv_timer_random/latest

Test location /workspace/coverage/default/136.rv_timer_random.1461790603
Short name T333
Test name
Test status
Simulation time 95251499856 ps
CPU time 179.81 seconds
Started Jul 17 06:45:57 PM PDT 24
Finished Jul 17 06:48:57 PM PDT 24
Peak memory 191344 kb
Host smart-3ee5a6af-84a8-4c9e-9c98-dce857b7594e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461790603 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.rv_timer_random.1461790603
Directory /workspace/136.rv_timer_random/latest

Test location /workspace/coverage/default/137.rv_timer_random.3640099776
Short name T331
Test name
Test status
Simulation time 91152756073 ps
CPU time 820.33 seconds
Started Jul 17 06:45:55 PM PDT 24
Finished Jul 17 06:59:36 PM PDT 24
Peak memory 191336 kb
Host smart-331826dc-52df-4e89-8e59-4c1f50bbf52d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640099776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.rv_timer_random.3640099776
Directory /workspace/137.rv_timer_random/latest

Test location /workspace/coverage/default/139.rv_timer_random.2514844632
Short name T147
Test name
Test status
Simulation time 785147707133 ps
CPU time 361.14 seconds
Started Jul 17 06:45:55 PM PDT 24
Finished Jul 17 06:51:57 PM PDT 24
Peak memory 191340 kb
Host smart-1068e2ac-e7ba-4caf-8517-0cf70aede2a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514844632 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.rv_timer_random.2514844632
Directory /workspace/139.rv_timer_random/latest

Test location /workspace/coverage/default/14.rv_timer_disabled.2898798294
Short name T447
Test name
Test status
Simulation time 129583326894 ps
CPU time 181.28 seconds
Started Jul 17 06:43:03 PM PDT 24
Finished Jul 17 06:46:06 PM PDT 24
Peak memory 183136 kb
Host smart-04de6f70-b7df-4596-bc00-3afea96b844c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898798294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_disabled.2898798294
Directory /workspace/14.rv_timer_disabled/latest

Test location /workspace/coverage/default/14.rv_timer_random_reset.1852091463
Short name T361
Test name
Test status
Simulation time 118345583591 ps
CPU time 176.15 seconds
Started Jul 17 06:43:04 PM PDT 24
Finished Jul 17 06:46:02 PM PDT 24
Peak memory 195252 kb
Host smart-2478e59c-d4aa-470d-a269-72c8704b33ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852091463 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_timer_random_reset.1852091463
Directory /workspace/14.rv_timer_random_reset/latest

Test location /workspace/coverage/default/140.rv_timer_random.1979490285
Short name T227
Test name
Test status
Simulation time 538000424865 ps
CPU time 481.33 seconds
Started Jul 17 06:45:54 PM PDT 24
Finished Jul 17 06:53:56 PM PDT 24
Peak memory 191452 kb
Host smart-8baa2a2c-1ef5-4284-842c-aa6fd0bffb4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979490285 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.rv_timer_random.1979490285
Directory /workspace/140.rv_timer_random/latest

Test location /workspace/coverage/default/141.rv_timer_random.3422991553
Short name T155
Test name
Test status
Simulation time 30618268330 ps
CPU time 48.28 seconds
Started Jul 17 06:45:54 PM PDT 24
Finished Jul 17 06:46:43 PM PDT 24
Peak memory 183132 kb
Host smart-1e560cc4-4b9f-47bc-9df5-ea0123a9f7db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422991553 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.rv_timer_random.3422991553
Directory /workspace/141.rv_timer_random/latest

Test location /workspace/coverage/default/143.rv_timer_random.1711433622
Short name T295
Test name
Test status
Simulation time 382643018084 ps
CPU time 231.68 seconds
Started Jul 17 06:45:56 PM PDT 24
Finished Jul 17 06:49:48 PM PDT 24
Peak memory 191272 kb
Host smart-6dd7e008-ac99-466b-882f-335bc7cfb0da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711433622 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.rv_timer_random.1711433622
Directory /workspace/143.rv_timer_random/latest

Test location /workspace/coverage/default/144.rv_timer_random.4001540612
Short name T248
Test name
Test status
Simulation time 155920779323 ps
CPU time 394.33 seconds
Started Jul 17 06:45:54 PM PDT 24
Finished Jul 17 06:52:29 PM PDT 24
Peak memory 194732 kb
Host smart-6163a28b-e53b-4461-958c-5c606fe91018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001540612 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.rv_timer_random.4001540612
Directory /workspace/144.rv_timer_random/latest

Test location /workspace/coverage/default/145.rv_timer_random.2230262625
Short name T105
Test name
Test status
Simulation time 113066038013 ps
CPU time 267.06 seconds
Started Jul 17 06:45:55 PM PDT 24
Finished Jul 17 06:50:23 PM PDT 24
Peak memory 191336 kb
Host smart-36072a15-cae6-49e3-b55a-e3b8c76ec0e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230262625 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.rv_timer_random.2230262625
Directory /workspace/145.rv_timer_random/latest

Test location /workspace/coverage/default/147.rv_timer_random.3204874206
Short name T281
Test name
Test status
Simulation time 87888957790 ps
CPU time 32.96 seconds
Started Jul 17 06:45:59 PM PDT 24
Finished Jul 17 06:46:33 PM PDT 24
Peak memory 182984 kb
Host smart-90cf04e4-c8f7-42ce-b14e-7c8fc267bbc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204874206 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.rv_timer_random.3204874206
Directory /workspace/147.rv_timer_random/latest

Test location /workspace/coverage/default/15.rv_timer_cfg_update_on_fly.2295961191
Short name T341
Test name
Test status
Simulation time 207645173720 ps
CPU time 300.86 seconds
Started Jul 17 06:43:04 PM PDT 24
Finished Jul 17 06:48:07 PM PDT 24
Peak memory 183080 kb
Host smart-14e54570-46d3-4908-877e-da7e0d56d605
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295961191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.rv_timer_cfg_update_on_fly.2295961191
Directory /workspace/15.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/15.rv_timer_disabled.1168248456
Short name T366
Test name
Test status
Simulation time 910843981152 ps
CPU time 281.68 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 06:47:45 PM PDT 24
Peak memory 183152 kb
Host smart-cc4dfdb6-1380-4ae8-8dfd-f7433560a68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168248456 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_disabled.1168248456
Directory /workspace/15.rv_timer_disabled/latest

Test location /workspace/coverage/default/15.rv_timer_random_reset.374508167
Short name T308
Test name
Test status
Simulation time 159301437948 ps
CPU time 138.59 seconds
Started Jul 17 06:43:01 PM PDT 24
Finished Jul 17 06:45:20 PM PDT 24
Peak memory 183124 kb
Host smart-dfc7b7ef-92f5-44b6-8f11-cc23e9e503a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374508167 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_random_reset.374508167
Directory /workspace/15.rv_timer_random_reset/latest

Test location /workspace/coverage/default/15.rv_timer_stress_all_with_rand_reset.3094642905
Short name T20
Test name
Test status
Simulation time 70196004685 ps
CPU time 665.48 seconds
Started Jul 17 06:43:03 PM PDT 24
Finished Jul 17 06:54:11 PM PDT 24
Peak memory 206020 kb
Host smart-84bf3804-b610-4291-a826-906cae77c13f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094642905 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.rv_timer_stress_all_with_rand_reset.3094642905
Directory /workspace/15.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/150.rv_timer_random.1320091546
Short name T271
Test name
Test status
Simulation time 3621420830 ps
CPU time 4.02 seconds
Started Jul 17 06:46:12 PM PDT 24
Finished Jul 17 06:46:18 PM PDT 24
Peak memory 183116 kb
Host smart-40fe0f3d-7818-48a8-a8b6-6e8a3a804303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320091546 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.rv_timer_random.1320091546
Directory /workspace/150.rv_timer_random/latest

Test location /workspace/coverage/default/151.rv_timer_random.3363064459
Short name T267
Test name
Test status
Simulation time 205365941885 ps
CPU time 329.38 seconds
Started Jul 17 06:46:10 PM PDT 24
Finished Jul 17 06:51:41 PM PDT 24
Peak memory 191332 kb
Host smart-7fddbb6e-be69-406c-a3c1-a2027479f5f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363064459 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.rv_timer_random.3363064459
Directory /workspace/151.rv_timer_random/latest

Test location /workspace/coverage/default/153.rv_timer_random.548000474
Short name T184
Test name
Test status
Simulation time 1348333984040 ps
CPU time 427.22 seconds
Started Jul 17 06:46:10 PM PDT 24
Finished Jul 17 06:53:19 PM PDT 24
Peak memory 191320 kb
Host smart-71eb8930-8381-46ce-af2f-4de459696718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548000474 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.rv_timer_random.548000474
Directory /workspace/153.rv_timer_random/latest

Test location /workspace/coverage/default/156.rv_timer_random.1565067880
Short name T140
Test name
Test status
Simulation time 4690064130 ps
CPU time 37.28 seconds
Started Jul 17 06:46:09 PM PDT 24
Finished Jul 17 06:46:48 PM PDT 24
Peak memory 183156 kb
Host smart-2236741f-a827-4a3d-86c1-a9dd0ae66607
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565067880 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.rv_timer_random.1565067880
Directory /workspace/156.rv_timer_random/latest

Test location /workspace/coverage/default/158.rv_timer_random.3944507437
Short name T133
Test name
Test status
Simulation time 271632997286 ps
CPU time 71.1 seconds
Started Jul 17 06:46:10 PM PDT 24
Finished Jul 17 06:47:24 PM PDT 24
Peak memory 183068 kb
Host smart-63b0c0e5-4e9c-41c6-89c6-a40d07713e1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944507437 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.rv_timer_random.3944507437
Directory /workspace/158.rv_timer_random/latest

Test location /workspace/coverage/default/159.rv_timer_random.1825689316
Short name T416
Test name
Test status
Simulation time 223590549202 ps
CPU time 103.02 seconds
Started Jul 17 06:46:09 PM PDT 24
Finished Jul 17 06:47:53 PM PDT 24
Peak memory 183136 kb
Host smart-b330ec05-6014-458a-852e-091dc2fa0108
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825689316 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.rv_timer_random.1825689316
Directory /workspace/159.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_cfg_update_on_fly.773081878
Short name T1
Test name
Test status
Simulation time 16486101826 ps
CPU time 26.34 seconds
Started Jul 17 06:43:09 PM PDT 24
Finished Jul 17 06:43:38 PM PDT 24
Peak memory 183132 kb
Host smart-2eacbf4d-94f0-4931-8577-4fd0c08c7f6c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773081878 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.rv_timer_cfg_update_on_fly.773081878
Directory /workspace/16.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/16.rv_timer_disabled.2381742597
Short name T376
Test name
Test status
Simulation time 321855427881 ps
CPU time 132.01 seconds
Started Jul 17 06:43:05 PM PDT 24
Finished Jul 17 06:45:19 PM PDT 24
Peak memory 183156 kb
Host smart-c10cd31c-6682-4478-8533-396b49aafc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381742597 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_disabled.2381742597
Directory /workspace/16.rv_timer_disabled/latest

Test location /workspace/coverage/default/16.rv_timer_random.917935815
Short name T440
Test name
Test status
Simulation time 1037675252363 ps
CPU time 930.49 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 06:58:34 PM PDT 24
Peak memory 191336 kb
Host smart-ef87d306-075a-47ca-8677-2cd547a5e78c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917935815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_random.917935815
Directory /workspace/16.rv_timer_random/latest

Test location /workspace/coverage/default/16.rv_timer_stress_all.1149488090
Short name T138
Test name
Test status
Simulation time 8287258487 ps
CPU time 24.14 seconds
Started Jul 17 06:43:04 PM PDT 24
Finished Jul 17 06:43:30 PM PDT 24
Peak memory 183248 kb
Host smart-0c551f1d-676b-48e9-86d2-49f0b457b2f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149488090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_timer_stress_all
.1149488090
Directory /workspace/16.rv_timer_stress_all/latest

Test location /workspace/coverage/default/160.rv_timer_random.3208772433
Short name T345
Test name
Test status
Simulation time 12708381351 ps
CPU time 34.11 seconds
Started Jul 17 06:46:11 PM PDT 24
Finished Jul 17 06:46:47 PM PDT 24
Peak memory 183112 kb
Host smart-d2c53ef2-f2fd-4f4a-9837-c2e3031caee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208772433 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.rv_timer_random.3208772433
Directory /workspace/160.rv_timer_random/latest

Test location /workspace/coverage/default/161.rv_timer_random.3664892007
Short name T174
Test name
Test status
Simulation time 108632503211 ps
CPU time 81.45 seconds
Started Jul 17 06:46:11 PM PDT 24
Finished Jul 17 06:47:34 PM PDT 24
Peak memory 191340 kb
Host smart-91aea2ec-a38e-4fe4-b45e-6cf6e928e5b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664892007 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.rv_timer_random.3664892007
Directory /workspace/161.rv_timer_random/latest

Test location /workspace/coverage/default/163.rv_timer_random.4202684105
Short name T171
Test name
Test status
Simulation time 96963631851 ps
CPU time 203.7 seconds
Started Jul 17 06:46:09 PM PDT 24
Finished Jul 17 06:49:34 PM PDT 24
Peak memory 191336 kb
Host smart-43087cdd-dd6a-48d2-ad38-def63e108966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202684105 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.rv_timer_random.4202684105
Directory /workspace/163.rv_timer_random/latest

Test location /workspace/coverage/default/165.rv_timer_random.1232904294
Short name T288
Test name
Test status
Simulation time 453168405120 ps
CPU time 748.79 seconds
Started Jul 17 06:46:09 PM PDT 24
Finished Jul 17 06:58:40 PM PDT 24
Peak memory 191344 kb
Host smart-a4803358-d020-4836-ba84-193491d3300c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232904294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.rv_timer_random.1232904294
Directory /workspace/165.rv_timer_random/latest

Test location /workspace/coverage/default/166.rv_timer_random.1073152367
Short name T262
Test name
Test status
Simulation time 238093615733 ps
CPU time 52.02 seconds
Started Jul 17 06:46:27 PM PDT 24
Finished Jul 17 06:47:19 PM PDT 24
Peak memory 183148 kb
Host smart-b97b2469-fd3f-4c1f-9e2f-31c77c8c1a27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073152367 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.rv_timer_random.1073152367
Directory /workspace/166.rv_timer_random/latest

Test location /workspace/coverage/default/167.rv_timer_random.1661470361
Short name T357
Test name
Test status
Simulation time 7522041262 ps
CPU time 13.81 seconds
Started Jul 17 06:46:18 PM PDT 24
Finished Jul 17 06:46:32 PM PDT 24
Peak memory 183088 kb
Host smart-dacd7a84-7c2c-4a49-86e2-013875393a02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661470361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.rv_timer_random.1661470361
Directory /workspace/167.rv_timer_random/latest

Test location /workspace/coverage/default/17.rv_timer_cfg_update_on_fly.404227514
Short name T289
Test name
Test status
Simulation time 283698652902 ps
CPU time 156.26 seconds
Started Jul 17 06:43:06 PM PDT 24
Finished Jul 17 06:45:44 PM PDT 24
Peak memory 182936 kb
Host smart-105164eb-8580-4758-b41f-a763b9f09b5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404227514 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.rv_timer_cfg_update_on_fly.404227514
Directory /workspace/17.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/17.rv_timer_disabled.638002949
Short name T424
Test name
Test status
Simulation time 59423383639 ps
CPU time 92.48 seconds
Started Jul 17 06:43:09 PM PDT 24
Finished Jul 17 06:44:44 PM PDT 24
Peak memory 183140 kb
Host smart-ea96f65e-6f07-4e0e-bcec-d490d3c0a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638002949 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_disabled.638002949
Directory /workspace/17.rv_timer_disabled/latest

Test location /workspace/coverage/default/17.rv_timer_random_reset.2253948487
Short name T397
Test name
Test status
Simulation time 43782999 ps
CPU time 0.62 seconds
Started Jul 17 06:43:09 PM PDT 24
Finished Jul 17 06:43:13 PM PDT 24
Peak memory 191656 kb
Host smart-1b6c0c14-eece-4283-ac5f-64f4af10bc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253948487 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_random_reset.2253948487
Directory /workspace/17.rv_timer_random_reset/latest

Test location /workspace/coverage/default/17.rv_timer_stress_all.3491446663
Short name T58
Test name
Test status
Simulation time 36819199 ps
CPU time 0.66 seconds
Started Jul 17 06:43:06 PM PDT 24
Finished Jul 17 06:43:09 PM PDT 24
Peak memory 182704 kb
Host smart-7422721e-7928-4f76-971b-2fc2d2e36202
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491446663 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_timer_stress_all
.3491446663
Directory /workspace/17.rv_timer_stress_all/latest

Test location /workspace/coverage/default/172.rv_timer_random.3274656911
Short name T163
Test name
Test status
Simulation time 476305761193 ps
CPU time 242.07 seconds
Started Jul 17 06:46:20 PM PDT 24
Finished Jul 17 06:50:22 PM PDT 24
Peak memory 191356 kb
Host smart-4a44ce01-ddad-4edb-bc4f-30bec39050d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274656911 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.rv_timer_random.3274656911
Directory /workspace/172.rv_timer_random/latest

Test location /workspace/coverage/default/173.rv_timer_random.3565563496
Short name T231
Test name
Test status
Simulation time 184756906597 ps
CPU time 991.36 seconds
Started Jul 17 06:46:19 PM PDT 24
Finished Jul 17 07:02:51 PM PDT 24
Peak memory 192572 kb
Host smart-39881357-0616-4be9-afb9-6e070e48a20e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565563496 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.rv_timer_random.3565563496
Directory /workspace/173.rv_timer_random/latest

Test location /workspace/coverage/default/176.rv_timer_random.4275648620
Short name T203
Test name
Test status
Simulation time 302308775789 ps
CPU time 857 seconds
Started Jul 17 06:46:22 PM PDT 24
Finished Jul 17 07:00:40 PM PDT 24
Peak memory 193680 kb
Host smart-70ce2c98-3f62-40c5-8c0a-416032e0f829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275648620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.rv_timer_random.4275648620
Directory /workspace/176.rv_timer_random/latest

Test location /workspace/coverage/default/177.rv_timer_random.2899760024
Short name T282
Test name
Test status
Simulation time 307205155857 ps
CPU time 538.38 seconds
Started Jul 17 06:46:19 PM PDT 24
Finished Jul 17 06:55:18 PM PDT 24
Peak memory 191336 kb
Host smart-7fcf857c-2198-4f87-9f0d-2e3b1c1f1f5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899760024 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.rv_timer_random.2899760024
Directory /workspace/177.rv_timer_random/latest

Test location /workspace/coverage/default/178.rv_timer_random.1789053925
Short name T450
Test name
Test status
Simulation time 81920081708 ps
CPU time 278.88 seconds
Started Jul 17 06:46:18 PM PDT 24
Finished Jul 17 06:50:58 PM PDT 24
Peak memory 191300 kb
Host smart-047a3201-9e63-42a5-ae45-f7874f880d8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789053925 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.rv_timer_random.1789053925
Directory /workspace/178.rv_timer_random/latest

Test location /workspace/coverage/default/179.rv_timer_random.1193733388
Short name T317
Test name
Test status
Simulation time 446595275087 ps
CPU time 100.41 seconds
Started Jul 17 06:46:18 PM PDT 24
Finished Jul 17 06:47:59 PM PDT 24
Peak memory 191292 kb
Host smart-a202c5d7-7202-46fa-ac55-12b2345566af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193733388 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.rv_timer_random.1193733388
Directory /workspace/179.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_cfg_update_on_fly.1816752761
Short name T232
Test name
Test status
Simulation time 1322323969029 ps
CPU time 406.82 seconds
Started Jul 17 06:43:14 PM PDT 24
Finished Jul 17 06:50:03 PM PDT 24
Peak memory 183136 kb
Host smart-c60c73f4-96d6-4839-a0ea-f29ed2810798
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816752761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.rv_timer_cfg_update_on_fly.1816752761
Directory /workspace/18.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/18.rv_timer_disabled.3850392408
Short name T64
Test name
Test status
Simulation time 311924713297 ps
CPU time 169.67 seconds
Started Jul 17 06:43:05 PM PDT 24
Finished Jul 17 06:45:56 PM PDT 24
Peak memory 183108 kb
Host smart-7c7454c7-c57e-49c4-81ec-5eb4e8b18409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850392408 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_disabled.3850392408
Directory /workspace/18.rv_timer_disabled/latest

Test location /workspace/coverage/default/18.rv_timer_random.2604049104
Short name T27
Test name
Test status
Simulation time 44528740639 ps
CPU time 64.29 seconds
Started Jul 17 06:43:05 PM PDT 24
Finished Jul 17 06:44:11 PM PDT 24
Peak memory 183140 kb
Host smart-988cd35e-c2f2-426b-b6b3-560ba253fde4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604049104 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random.2604049104
Directory /workspace/18.rv_timer_random/latest

Test location /workspace/coverage/default/18.rv_timer_random_reset.229773887
Short name T390
Test name
Test status
Simulation time 50559690 ps
CPU time 0.64 seconds
Started Jul 17 06:43:12 PM PDT 24
Finished Jul 17 06:43:15 PM PDT 24
Peak memory 182984 kb
Host smart-594aaa1a-978d-4f48-9591-1078f20da6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229773887 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_random_reset.229773887
Directory /workspace/18.rv_timer_random_reset/latest

Test location /workspace/coverage/default/18.rv_timer_stress_all.2392187491
Short name T365
Test name
Test status
Simulation time 311494563829 ps
CPU time 129.7 seconds
Started Jul 17 06:43:14 PM PDT 24
Finished Jul 17 06:45:26 PM PDT 24
Peak memory 183132 kb
Host smart-84d527b4-5469-442a-8e95-366cf95ca8cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392187491 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_timer_stress_all
.2392187491
Directory /workspace/18.rv_timer_stress_all/latest

Test location /workspace/coverage/default/180.rv_timer_random.2152348828
Short name T438
Test name
Test status
Simulation time 22487931047 ps
CPU time 69.56 seconds
Started Jul 17 06:46:30 PM PDT 24
Finished Jul 17 06:47:40 PM PDT 24
Peak memory 191296 kb
Host smart-d38cdc7e-e1ab-4176-9c47-bca487c1a178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152348828 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.rv_timer_random.2152348828
Directory /workspace/180.rv_timer_random/latest

Test location /workspace/coverage/default/185.rv_timer_random.892489744
Short name T260
Test name
Test status
Simulation time 22097688389 ps
CPU time 36.83 seconds
Started Jul 17 06:46:30 PM PDT 24
Finished Jul 17 06:47:07 PM PDT 24
Peak memory 193756 kb
Host smart-df8070f6-53da-480f-abcd-efec64934bc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892489744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.rv_timer_random.892489744
Directory /workspace/185.rv_timer_random/latest

Test location /workspace/coverage/default/186.rv_timer_random.4005270227
Short name T443
Test name
Test status
Simulation time 894139681328 ps
CPU time 1185.3 seconds
Started Jul 17 06:46:29 PM PDT 24
Finished Jul 17 07:06:15 PM PDT 24
Peak memory 191352 kb
Host smart-23596b13-135a-4c00-b296-a43dbe78b681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005270227 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.rv_timer_random.4005270227
Directory /workspace/186.rv_timer_random/latest

Test location /workspace/coverage/default/187.rv_timer_random.4013586221
Short name T239
Test name
Test status
Simulation time 94365668215 ps
CPU time 50.33 seconds
Started Jul 17 06:46:29 PM PDT 24
Finished Jul 17 06:47:20 PM PDT 24
Peak memory 183060 kb
Host smart-50debba8-05ff-4026-ab55-574f6a45479e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013586221 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.rv_timer_random.4013586221
Directory /workspace/187.rv_timer_random/latest

Test location /workspace/coverage/default/188.rv_timer_random.1393525831
Short name T180
Test name
Test status
Simulation time 237924491219 ps
CPU time 313.87 seconds
Started Jul 17 06:46:30 PM PDT 24
Finished Jul 17 06:51:45 PM PDT 24
Peak memory 191496 kb
Host smart-35fc0512-1b67-437d-8353-3a1200553e2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393525831 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.rv_timer_random.1393525831
Directory /workspace/188.rv_timer_random/latest

Test location /workspace/coverage/default/189.rv_timer_random.389801993
Short name T230
Test name
Test status
Simulation time 161158636593 ps
CPU time 675.12 seconds
Started Jul 17 06:46:43 PM PDT 24
Finished Jul 17 06:57:59 PM PDT 24
Peak memory 191344 kb
Host smart-75120826-dc60-46f2-920f-9f5acdb514dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389801993 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.rv_timer_random.389801993
Directory /workspace/189.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_cfg_update_on_fly.2929960
Short name T426
Test name
Test status
Simulation time 1159797030782 ps
CPU time 672.24 seconds
Started Jul 17 06:43:14 PM PDT 24
Finished Jul 17 06:54:28 PM PDT 24
Peak memory 183128 kb
Host smart-4c1deb62-3e50-4454-be9a-27e6d97299ca
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929960 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv
_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
rv_timer_cfg_update_on_fly.2929960
Directory /workspace/19.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/19.rv_timer_disabled.750302120
Short name T374
Test name
Test status
Simulation time 256487428586 ps
CPU time 160.08 seconds
Started Jul 17 06:43:12 PM PDT 24
Finished Jul 17 06:45:54 PM PDT 24
Peak memory 183048 kb
Host smart-2024211e-63fe-4de0-828e-3c122ea921ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750302120 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_disabled.750302120
Directory /workspace/19.rv_timer_disabled/latest

Test location /workspace/coverage/default/19.rv_timer_random.3815396304
Short name T112
Test name
Test status
Simulation time 108099611824 ps
CPU time 125.16 seconds
Started Jul 17 06:43:15 PM PDT 24
Finished Jul 17 06:45:22 PM PDT 24
Peak memory 191296 kb
Host smart-9f647e3e-4fde-4dda-995c-d389af84c77b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815396304 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random.3815396304
Directory /workspace/19.rv_timer_random/latest

Test location /workspace/coverage/default/19.rv_timer_random_reset.621682704
Short name T418
Test name
Test status
Simulation time 244088843082 ps
CPU time 116.33 seconds
Started Jul 17 06:43:13 PM PDT 24
Finished Jul 17 06:45:12 PM PDT 24
Peak memory 191304 kb
Host smart-44876085-d220-47d3-8024-c68543c04aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621682704 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_timer_random_reset.621682704
Directory /workspace/19.rv_timer_random_reset/latest

Test location /workspace/coverage/default/190.rv_timer_random.984563908
Short name T351
Test name
Test status
Simulation time 141212192949 ps
CPU time 901.7 seconds
Started Jul 17 06:46:43 PM PDT 24
Finished Jul 17 07:01:46 PM PDT 24
Peak memory 191296 kb
Host smart-1e7b8844-a71f-4a2c-b59a-2ff942fb2246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984563908 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.rv_timer_random.984563908
Directory /workspace/190.rv_timer_random/latest

Test location /workspace/coverage/default/193.rv_timer_random.372652184
Short name T207
Test name
Test status
Simulation time 211735877749 ps
CPU time 293.7 seconds
Started Jul 17 06:46:44 PM PDT 24
Finished Jul 17 06:51:39 PM PDT 24
Peak memory 193624 kb
Host smart-428483a2-a8f1-402f-b24a-3cbe5e67e3c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372652184 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.rv_timer_random.372652184
Directory /workspace/193.rv_timer_random/latest

Test location /workspace/coverage/default/196.rv_timer_random.994867186
Short name T304
Test name
Test status
Simulation time 673881417028 ps
CPU time 406.5 seconds
Started Jul 17 06:46:42 PM PDT 24
Finished Jul 17 06:53:29 PM PDT 24
Peak memory 191288 kb
Host smart-3d2c5e1f-9e3e-4352-a5f9-7568e3bfc747
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994867186 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.rv_timer_random.994867186
Directory /workspace/196.rv_timer_random/latest

Test location /workspace/coverage/default/197.rv_timer_random.3840915
Short name T444
Test name
Test status
Simulation time 200994766051 ps
CPU time 99.72 seconds
Started Jul 17 06:46:43 PM PDT 24
Finished Jul 17 06:48:24 PM PDT 24
Peak memory 191240 kb
Host smart-3baa7572-172f-432c-ab32-e7f2bcaac609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840915 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.rv_timer_random.3840915
Directory /workspace/197.rv_timer_random/latest

Test location /workspace/coverage/default/198.rv_timer_random.1490256074
Short name T299
Test name
Test status
Simulation time 38504338477 ps
CPU time 99.77 seconds
Started Jul 17 06:46:42 PM PDT 24
Finished Jul 17 06:48:22 PM PDT 24
Peak memory 191308 kb
Host smart-6f6adba5-8573-491f-923b-da25965b6f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490256074 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.rv_timer_random.1490256074
Directory /workspace/198.rv_timer_random/latest

Test location /workspace/coverage/default/199.rv_timer_random.3718801168
Short name T202
Test name
Test status
Simulation time 86748018951 ps
CPU time 149.29 seconds
Started Jul 17 06:46:43 PM PDT 24
Finished Jul 17 06:49:14 PM PDT 24
Peak memory 191288 kb
Host smart-57ecdc19-14c5-410c-a130-4f09eb4f8e9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718801168 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.rv_timer_random.3718801168
Directory /workspace/199.rv_timer_random/latest

Test location /workspace/coverage/default/2.rv_timer_cfg_update_on_fly.1130015470
Short name T107
Test name
Test status
Simulation time 1082870375614 ps
CPU time 565.93 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:52:21 PM PDT 24
Peak memory 183120 kb
Host smart-c904672e-7b41-4007-8d43-8dee70264ad3
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130015470 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.rv_timer_cfg_update_on_fly.1130015470
Directory /workspace/2.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/2.rv_timer_disabled.2299992259
Short name T409
Test name
Test status
Simulation time 134352241154 ps
CPU time 180.3 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:45:54 PM PDT 24
Peak memory 183128 kb
Host smart-4ed84c5c-064f-4220-911e-89d97bbb7c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299992259 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_disabled.2299992259
Directory /workspace/2.rv_timer_disabled/latest

Test location /workspace/coverage/default/2.rv_timer_random_reset.4128107656
Short name T342
Test name
Test status
Simulation time 6356338136 ps
CPU time 11.74 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:43:07 PM PDT 24
Peak memory 191292 kb
Host smart-04363611-3e4f-44af-bcb4-da9fdc0aa5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128107656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_random_reset.4128107656
Directory /workspace/2.rv_timer_random_reset/latest

Test location /workspace/coverage/default/2.rv_timer_sec_cm.607493296
Short name T16
Test name
Test status
Simulation time 59826554 ps
CPU time 0.82 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:42:54 PM PDT 24
Peak memory 213396 kb
Host smart-ff2ab7e5-7849-4fa8-9541-a8a04cc026c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607493296 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_sec_cm.607493296
Directory /workspace/2.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/2.rv_timer_stress_all.3540465330
Short name T57
Test name
Test status
Simulation time 561001935822 ps
CPU time 765.28 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:55:40 PM PDT 24
Peak memory 195644 kb
Host smart-6091c429-c235-4337-a073-fbd440fab20e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540465330 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_timer_stress_all.
3540465330
Directory /workspace/2.rv_timer_stress_all/latest

Test location /workspace/coverage/default/20.rv_timer_cfg_update_on_fly.2264338079
Short name T137
Test name
Test status
Simulation time 10290597067 ps
CPU time 4.83 seconds
Started Jul 17 06:43:16 PM PDT 24
Finished Jul 17 06:43:22 PM PDT 24
Peak memory 183300 kb
Host smart-bc0fb7d9-1026-4add-b08f-77ee9ed259c8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264338079 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.rv_timer_cfg_update_on_fly.2264338079
Directory /workspace/20.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/20.rv_timer_disabled.2398287528
Short name T378
Test name
Test status
Simulation time 143881177978 ps
CPU time 202.23 seconds
Started Jul 17 06:43:15 PM PDT 24
Finished Jul 17 06:46:39 PM PDT 24
Peak memory 183100 kb
Host smart-3d3f18ff-ed14-452b-b427-30ce340c543a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398287528 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_disabled.2398287528
Directory /workspace/20.rv_timer_disabled/latest

Test location /workspace/coverage/default/20.rv_timer_random.1272384778
Short name T269
Test name
Test status
Simulation time 95764474698 ps
CPU time 171.17 seconds
Started Jul 17 06:43:13 PM PDT 24
Finished Jul 17 06:46:06 PM PDT 24
Peak memory 191328 kb
Host smart-11f7a91a-188c-4774-8ff6-a58075fc4862
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272384778 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random.1272384778
Directory /workspace/20.rv_timer_random/latest

Test location /workspace/coverage/default/20.rv_timer_random_reset.4218675641
Short name T404
Test name
Test status
Simulation time 192048074 ps
CPU time 0.62 seconds
Started Jul 17 06:43:15 PM PDT 24
Finished Jul 17 06:43:17 PM PDT 24
Peak memory 183024 kb
Host smart-235d6a0f-511b-4ee4-87cb-3d78d447a489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218675641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_timer_random_reset.4218675641
Directory /workspace/20.rv_timer_random_reset/latest

Test location /workspace/coverage/default/21.rv_timer_cfg_update_on_fly.4231901623
Short name T453
Test name
Test status
Simulation time 3408570667 ps
CPU time 3.23 seconds
Started Jul 17 06:43:14 PM PDT 24
Finished Jul 17 06:43:19 PM PDT 24
Peak memory 183088 kb
Host smart-007950dd-536c-4293-8541-bd74fe1e9964
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231901623 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.rv_timer_cfg_update_on_fly.4231901623
Directory /workspace/21.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/21.rv_timer_random.3668907517
Short name T252
Test name
Test status
Simulation time 419145265672 ps
CPU time 1052.05 seconds
Started Jul 17 06:43:15 PM PDT 24
Finished Jul 17 07:00:49 PM PDT 24
Peak memory 191336 kb
Host smart-b10b55b1-630b-4aeb-8a87-1c8d86e11152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668907517 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random.3668907517
Directory /workspace/21.rv_timer_random/latest

Test location /workspace/coverage/default/21.rv_timer_random_reset.3981097979
Short name T446
Test name
Test status
Simulation time 30751131822 ps
CPU time 21.27 seconds
Started Jul 17 06:43:16 PM PDT 24
Finished Jul 17 06:43:39 PM PDT 24
Peak memory 183080 kb
Host smart-95760efb-6c93-44a6-8533-1376dab4a406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981097979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_timer_random_reset.3981097979
Directory /workspace/21.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_cfg_update_on_fly.4294168311
Short name T100
Test name
Test status
Simulation time 588136784360 ps
CPU time 320.55 seconds
Started Jul 17 06:43:14 PM PDT 24
Finished Jul 17 06:48:37 PM PDT 24
Peak memory 183136 kb
Host smart-0699c74f-ddcb-4388-8ea4-18fce917d19f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294168311 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.rv_timer_cfg_update_on_fly.4294168311
Directory /workspace/22.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/22.rv_timer_random.3216972291
Short name T41
Test name
Test status
Simulation time 29512787985 ps
CPU time 49.98 seconds
Started Jul 17 06:43:16 PM PDT 24
Finished Jul 17 06:44:07 PM PDT 24
Peak memory 191296 kb
Host smart-2f7c61c8-614b-40dc-8483-ae18ae0754dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216972291 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random.3216972291
Directory /workspace/22.rv_timer_random/latest

Test location /workspace/coverage/default/22.rv_timer_random_reset.2738395365
Short name T22
Test name
Test status
Simulation time 48533072655 ps
CPU time 69.37 seconds
Started Jul 17 06:43:14 PM PDT 24
Finished Jul 17 06:44:25 PM PDT 24
Peak memory 191260 kb
Host smart-64540f47-9f44-4866-bae1-7aa93a523dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738395365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_random_reset.2738395365
Directory /workspace/22.rv_timer_random_reset/latest

Test location /workspace/coverage/default/22.rv_timer_stress_all.2084834512
Short name T388
Test name
Test status
Simulation time 168186723949 ps
CPU time 216.68 seconds
Started Jul 17 06:43:16 PM PDT 24
Finished Jul 17 06:46:54 PM PDT 24
Peak memory 194736 kb
Host smart-37d225b7-5b3e-4bfc-90a8-a0fa1eb9d3bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084834512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_timer_stress_all
.2084834512
Directory /workspace/22.rv_timer_stress_all/latest

Test location /workspace/coverage/default/23.rv_timer_disabled.2573544758
Short name T445
Test name
Test status
Simulation time 110299194479 ps
CPU time 152.72 seconds
Started Jul 17 06:43:16 PM PDT 24
Finished Jul 17 06:45:50 PM PDT 24
Peak memory 183096 kb
Host smart-bcfd7de1-52af-4eab-b835-56d06bfe071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573544758 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_disabled.2573544758
Directory /workspace/23.rv_timer_disabled/latest

Test location /workspace/coverage/default/23.rv_timer_random.2292026484
Short name T334
Test name
Test status
Simulation time 169464455541 ps
CPU time 246.57 seconds
Started Jul 17 06:43:18 PM PDT 24
Finished Jul 17 06:47:25 PM PDT 24
Peak memory 191280 kb
Host smart-e9cfa052-e98a-478f-9ead-1b162b16e7d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292026484 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random.2292026484
Directory /workspace/23.rv_timer_random/latest

Test location /workspace/coverage/default/23.rv_timer_random_reset.3413170009
Short name T360
Test name
Test status
Simulation time 49435617519 ps
CPU time 38.6 seconds
Started Jul 17 06:43:16 PM PDT 24
Finished Jul 17 06:43:56 PM PDT 24
Peak memory 194988 kb
Host smart-92fdefa0-a9c8-4b14-9951-1599de48e833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413170009 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_random_reset.3413170009
Directory /workspace/23.rv_timer_random_reset/latest

Test location /workspace/coverage/default/23.rv_timer_stress_all.481278652
Short name T297
Test name
Test status
Simulation time 6404495738 ps
CPU time 42.16 seconds
Started Jul 17 06:43:16 PM PDT 24
Finished Jul 17 06:44:00 PM PDT 24
Peak memory 183088 kb
Host smart-3c90d996-310b-4607-971e-090e7f591146
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481278652 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_timer_stress_all.
481278652
Directory /workspace/23.rv_timer_stress_all/latest

Test location /workspace/coverage/default/24.rv_timer_cfg_update_on_fly.274044223
Short name T6
Test name
Test status
Simulation time 2332018311954 ps
CPU time 1032.17 seconds
Started Jul 17 06:43:16 PM PDT 24
Finished Jul 17 07:00:30 PM PDT 24
Peak memory 183128 kb
Host smart-fa6937e4-331e-49dd-b195-8b2a5fae4055
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274044223 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.rv_timer_cfg_update_on_fly.274044223
Directory /workspace/24.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/24.rv_timer_disabled.1298201431
Short name T393
Test name
Test status
Simulation time 299889977880 ps
CPU time 228.15 seconds
Started Jul 17 06:43:17 PM PDT 24
Finished Jul 17 06:47:07 PM PDT 24
Peak memory 183136 kb
Host smart-ac7fea95-4d0d-4ea8-b214-fb4ca07bc798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298201431 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_disabled.1298201431
Directory /workspace/24.rv_timer_disabled/latest

Test location /workspace/coverage/default/24.rv_timer_random.2682613272
Short name T153
Test name
Test status
Simulation time 9102017762 ps
CPU time 7.99 seconds
Started Jul 17 06:43:16 PM PDT 24
Finished Jul 17 06:43:25 PM PDT 24
Peak memory 191348 kb
Host smart-2f226524-5da2-45d2-ab3d-6eb78fc1c2a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682613272 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random.2682613272
Directory /workspace/24.rv_timer_random/latest

Test location /workspace/coverage/default/24.rv_timer_random_reset.3913019620
Short name T408
Test name
Test status
Simulation time 206912672 ps
CPU time 1.64 seconds
Started Jul 17 06:43:24 PM PDT 24
Finished Jul 17 06:43:27 PM PDT 24
Peak memory 183064 kb
Host smart-4f36db66-c169-4541-b22e-5bca65fa0bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913019620 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_timer_random_reset.3913019620
Directory /workspace/24.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_cfg_update_on_fly.2941236429
Short name T314
Test name
Test status
Simulation time 11466675917 ps
CPU time 20.97 seconds
Started Jul 17 06:43:24 PM PDT 24
Finished Jul 17 06:43:48 PM PDT 24
Peak memory 183128 kb
Host smart-c66c7cb7-20de-4304-820d-b000b57e5859
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941236429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.rv_timer_cfg_update_on_fly.2941236429
Directory /workspace/25.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/25.rv_timer_disabled.3627202836
Short name T432
Test name
Test status
Simulation time 339649250843 ps
CPU time 224.17 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:47:11 PM PDT 24
Peak memory 183144 kb
Host smart-933ffb76-2791-48f4-9c13-ef27bb2195e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627202836 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_disabled.3627202836
Directory /workspace/25.rv_timer_disabled/latest

Test location /workspace/coverage/default/25.rv_timer_random_reset.64605294
Short name T43
Test name
Test status
Simulation time 4312301932 ps
CPU time 33.82 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:44:02 PM PDT 24
Peak memory 183108 kb
Host smart-3d8882d4-d2c2-403d-96f2-ac078daff557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64605294 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_random_reset.64605294
Directory /workspace/25.rv_timer_random_reset/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all.2115211744
Short name T44
Test name
Test status
Simulation time 707617790529 ps
CPU time 652.93 seconds
Started Jul 17 06:43:24 PM PDT 24
Finished Jul 17 06:54:18 PM PDT 24
Peak memory 191352 kb
Host smart-f29eee86-c58b-44d5-bbfe-5253a72ea830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115211744 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all
.2115211744
Directory /workspace/25.rv_timer_stress_all/latest

Test location /workspace/coverage/default/25.rv_timer_stress_all_with_rand_reset.2326636387
Short name T49
Test name
Test status
Simulation time 72298495089 ps
CPU time 541.95 seconds
Started Jul 17 06:43:26 PM PDT 24
Finished Jul 17 06:52:31 PM PDT 24
Peak memory 205644 kb
Host smart-3328a14d-327b-4591-93bc-9d27a01b44ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326636387 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.rv_timer_stress_all_with_rand_reset.2326636387
Directory /workspace/25.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.rv_timer_disabled.609949854
Short name T385
Test name
Test status
Simulation time 92813914421 ps
CPU time 133.07 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:45:40 PM PDT 24
Peak memory 183152 kb
Host smart-bd0aa83c-cf58-42d9-a17a-329dc3e5f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609949854 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_disabled.609949854
Directory /workspace/26.rv_timer_disabled/latest

Test location /workspace/coverage/default/26.rv_timer_random.3649300156
Short name T353
Test name
Test status
Simulation time 53107459486 ps
CPU time 575.99 seconds
Started Jul 17 06:43:26 PM PDT 24
Finished Jul 17 06:53:05 PM PDT 24
Peak memory 191280 kb
Host smart-2094b692-2ac7-4d0c-a9f5-623879ab4fb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649300156 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random.3649300156
Directory /workspace/26.rv_timer_random/latest

Test location /workspace/coverage/default/26.rv_timer_random_reset.3023777266
Short name T413
Test name
Test status
Simulation time 173352371 ps
CPU time 0.69 seconds
Started Jul 17 06:43:26 PM PDT 24
Finished Jul 17 06:43:30 PM PDT 24
Peak memory 182696 kb
Host smart-30ae653a-7aac-491d-b59d-95fb6b6d9faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023777266 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_timer_random_reset.3023777266
Directory /workspace/26.rv_timer_random_reset/latest

Test location /workspace/coverage/default/27.rv_timer_cfg_update_on_fly.3323640762
Short name T324
Test name
Test status
Simulation time 859243570619 ps
CPU time 424.48 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:50:33 PM PDT 24
Peak memory 183132 kb
Host smart-8bd174cf-34bb-457a-a082-c94461138b23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323640762 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.rv_timer_cfg_update_on_fly.3323640762
Directory /workspace/27.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/27.rv_timer_random_reset.307329448
Short name T116
Test name
Test status
Simulation time 29757916089 ps
CPU time 61.02 seconds
Started Jul 17 06:43:26 PM PDT 24
Finished Jul 17 06:44:30 PM PDT 24
Peak memory 183172 kb
Host smart-037119ab-e225-43d7-aae7-5560b017ef2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307329448 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_timer_random_reset.307329448
Directory /workspace/27.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_disabled.3507084495
Short name T25
Test name
Test status
Simulation time 131377596055 ps
CPU time 161.37 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:46:09 PM PDT 24
Peak memory 183156 kb
Host smart-2193d32f-baa1-419e-9238-6b9dadf33b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507084495 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_disabled.3507084495
Directory /workspace/28.rv_timer_disabled/latest

Test location /workspace/coverage/default/28.rv_timer_random.609628430
Short name T347
Test name
Test status
Simulation time 2497364595604 ps
CPU time 727.74 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:55:36 PM PDT 24
Peak memory 191340 kb
Host smart-fc4ea81e-5236-41b4-8389-b23cfd222908
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609628430 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random.609628430
Directory /workspace/28.rv_timer_random/latest

Test location /workspace/coverage/default/28.rv_timer_random_reset.2055554774
Short name T379
Test name
Test status
Simulation time 511332700 ps
CPU time 1.21 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:43:29 PM PDT 24
Peak memory 183072 kb
Host smart-275eaf45-db95-43d8-a13d-bfc97c3c9773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055554774 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_random_reset.2055554774
Directory /workspace/28.rv_timer_random_reset/latest

Test location /workspace/coverage/default/28.rv_timer_stress_all_with_rand_reset.2202457444
Short name T37
Test name
Test status
Simulation time 220046433536 ps
CPU time 1056.72 seconds
Started Jul 17 06:43:24 PM PDT 24
Finished Jul 17 07:01:02 PM PDT 24
Peak memory 205980 kb
Host smart-88266f73-60dd-41b5-a1a2-112fe92110ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202457444 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.rv_timer_stress_all_with_rand_reset.2202457444
Directory /workspace/28.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.rv_timer_disabled.440298518
Short name T3
Test name
Test status
Simulation time 47838908583 ps
CPU time 66.28 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:44:35 PM PDT 24
Peak memory 183104 kb
Host smart-fc347f70-373f-4549-aeb4-fbe1a9b06382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440298518 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_disabled.440298518
Directory /workspace/29.rv_timer_disabled/latest

Test location /workspace/coverage/default/29.rv_timer_random_reset.3273795616
Short name T201
Test name
Test status
Simulation time 17775020071 ps
CPU time 35.54 seconds
Started Jul 17 06:43:26 PM PDT 24
Finished Jul 17 06:44:04 PM PDT 24
Peak memory 191296 kb
Host smart-360d1317-0ed2-492b-a6b0-aee9529c03ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273795616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_random_reset.3273795616
Directory /workspace/29.rv_timer_random_reset/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all.859098490
Short name T441
Test name
Test status
Simulation time 6015731216335 ps
CPU time 1513.4 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 07:08:42 PM PDT 24
Peak memory 191276 kb
Host smart-ccaed722-e599-48c5-ad5c-3fc3431341be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859098490 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all.
859098490
Directory /workspace/29.rv_timer_stress_all/latest

Test location /workspace/coverage/default/29.rv_timer_stress_all_with_rand_reset.2990217854
Short name T12
Test name
Test status
Simulation time 51340046451 ps
CPU time 203.34 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:46:52 PM PDT 24
Peak memory 206060 kb
Host smart-a03c7716-9528-4354-be12-5e78c4d88014
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990217854 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.rv_timer_stress_all_with_rand_reset.2990217854
Directory /workspace/29.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.rv_timer_cfg_update_on_fly.4177149022
Short name T168
Test name
Test status
Simulation time 121106825146 ps
CPU time 210.86 seconds
Started Jul 17 06:42:51 PM PDT 24
Finished Jul 17 06:46:23 PM PDT 24
Peak memory 183120 kb
Host smart-e012cb32-e67d-4a96-b081-9b29674623c2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177149022 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.rv_timer_cfg_update_on_fly.4177149022
Directory /workspace/3.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/3.rv_timer_disabled.4080675879
Short name T373
Test name
Test status
Simulation time 613573447961 ps
CPU time 189.46 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:46:04 PM PDT 24
Peak memory 183136 kb
Host smart-7c7a9f32-b010-47dc-99c1-76896e0ecf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080675879 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_disabled.4080675879
Directory /workspace/3.rv_timer_disabled/latest

Test location /workspace/coverage/default/3.rv_timer_random_reset.2848588136
Short name T225
Test name
Test status
Simulation time 29660674060 ps
CPU time 39.53 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:43:35 PM PDT 24
Peak memory 183060 kb
Host smart-45da63e6-4de9-4111-8901-067cc88250dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848588136 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_random_reset.2848588136
Directory /workspace/3.rv_timer_random_reset/latest

Test location /workspace/coverage/default/3.rv_timer_sec_cm.3835801970
Short name T17
Test name
Test status
Simulation time 233061606 ps
CPU time 0.83 seconds
Started Jul 17 06:42:55 PM PDT 24
Finished Jul 17 06:42:57 PM PDT 24
Peak memory 213444 kb
Host smart-40cdbf65-5a83-4547-a98a-458f8e39462d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835801970 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_sec_cm.3835801970
Directory /workspace/3.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/3.rv_timer_stress_all.2543193750
Short name T395
Test name
Test status
Simulation time 215649248765 ps
CPU time 118.46 seconds
Started Jul 17 06:42:51 PM PDT 24
Finished Jul 17 06:44:50 PM PDT 24
Peak memory 183132 kb
Host smart-b0065760-81ab-45c4-9a70-c8f217fbe079
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543193750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_timer_stress_all.
2543193750
Directory /workspace/3.rv_timer_stress_all/latest

Test location /workspace/coverage/default/30.rv_timer_cfg_update_on_fly.2647892939
Short name T59
Test name
Test status
Simulation time 247911005630 ps
CPU time 424.19 seconds
Started Jul 17 06:43:27 PM PDT 24
Finished Jul 17 06:50:34 PM PDT 24
Peak memory 182968 kb
Host smart-6d9bf759-9259-4f8f-bcb6-9c6fa98116ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647892939 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.rv_timer_cfg_update_on_fly.2647892939
Directory /workspace/30.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/30.rv_timer_disabled.2209520672
Short name T382
Test name
Test status
Simulation time 54694014817 ps
CPU time 19.51 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:43:47 PM PDT 24
Peak memory 183128 kb
Host smart-ffcdeefe-ae3a-459e-8245-cc06497c7add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209520672 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_disabled.2209520672
Directory /workspace/30.rv_timer_disabled/latest

Test location /workspace/coverage/default/30.rv_timer_random.1706176761
Short name T196
Test name
Test status
Simulation time 493617628959 ps
CPU time 218.6 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:47:06 PM PDT 24
Peak memory 194848 kb
Host smart-d3e277d2-957b-4705-b4d1-e47c4e384141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706176761 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random.1706176761
Directory /workspace/30.rv_timer_random/latest

Test location /workspace/coverage/default/30.rv_timer_random_reset.955838815
Short name T403
Test name
Test status
Simulation time 14171858725 ps
CPU time 11.56 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:43:40 PM PDT 24
Peak memory 183088 kb
Host smart-e1adc97a-3431-482f-a68d-22b0dec15982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955838815 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_random_reset.955838815
Directory /workspace/30.rv_timer_random_reset/latest

Test location /workspace/coverage/default/30.rv_timer_stress_all.4090918608
Short name T219
Test name
Test status
Simulation time 277050287983 ps
CPU time 554.05 seconds
Started Jul 17 06:43:26 PM PDT 24
Finished Jul 17 06:52:43 PM PDT 24
Peak memory 195812 kb
Host smart-208b4e0d-5da6-4783-aa33-b2c19bdbac20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090918608 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_timer_stress_all
.4090918608
Directory /workspace/30.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_cfg_update_on_fly.3998319327
Short name T45
Test name
Test status
Simulation time 574626986469 ps
CPU time 895.12 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:58:23 PM PDT 24
Peak memory 183060 kb
Host smart-0943924c-9b04-4147-bca0-debbbabedefc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998319327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.rv_timer_cfg_update_on_fly.3998319327
Directory /workspace/31.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/31.rv_timer_disabled.2353117391
Short name T387
Test name
Test status
Simulation time 174255099501 ps
CPU time 71.28 seconds
Started Jul 17 06:43:27 PM PDT 24
Finished Jul 17 06:44:41 PM PDT 24
Peak memory 183160 kb
Host smart-645e6f6c-ebf4-4bea-ac46-c55ec88e93a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353117391 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_disabled.2353117391
Directory /workspace/31.rv_timer_disabled/latest

Test location /workspace/coverage/default/31.rv_timer_random.3719257003
Short name T431
Test name
Test status
Simulation time 16241719768 ps
CPU time 7.73 seconds
Started Jul 17 06:43:26 PM PDT 24
Finished Jul 17 06:43:37 PM PDT 24
Peak memory 183100 kb
Host smart-f6a5622f-7d5c-497e-b877-040beb34ba48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719257003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_random.3719257003
Directory /workspace/31.rv_timer_random/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all.3541265429
Short name T119
Test name
Test status
Simulation time 221058541043 ps
CPU time 203.11 seconds
Started Jul 17 06:43:26 PM PDT 24
Finished Jul 17 06:46:52 PM PDT 24
Peak memory 191360 kb
Host smart-162fa632-520c-4012-9193-ab7996b7d178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541265429 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all
.3541265429
Directory /workspace/31.rv_timer_stress_all/latest

Test location /workspace/coverage/default/31.rv_timer_stress_all_with_rand_reset.4253216030
Short name T422
Test name
Test status
Simulation time 67098169266 ps
CPU time 735.29 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:55:44 PM PDT 24
Peak memory 213688 kb
Host smart-e7c85c2f-7a66-4641-86dd-837272021ba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253216030 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.rv_timer_stress_all_with_rand_reset.4253216030
Directory /workspace/31.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.rv_timer_cfg_update_on_fly.415276900
Short name T48
Test name
Test status
Simulation time 146529448954 ps
CPU time 232.93 seconds
Started Jul 17 06:43:36 PM PDT 24
Finished Jul 17 06:47:31 PM PDT 24
Peak memory 183136 kb
Host smart-461203da-178b-4eac-927d-fc2a8835e81b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415276900 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.rv_timer_cfg_update_on_fly.415276900
Directory /workspace/32.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/32.rv_timer_disabled.1617018884
Short name T369
Test name
Test status
Simulation time 196366687039 ps
CPU time 127.96 seconds
Started Jul 17 06:43:25 PM PDT 24
Finished Jul 17 06:45:36 PM PDT 24
Peak memory 183152 kb
Host smart-3d99472c-c90b-45dc-bd5f-11da3537ca61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617018884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_disabled.1617018884
Directory /workspace/32.rv_timer_disabled/latest

Test location /workspace/coverage/default/32.rv_timer_random.893717235
Short name T205
Test name
Test status
Simulation time 280624992506 ps
CPU time 119.46 seconds
Started Jul 17 06:43:24 PM PDT 24
Finished Jul 17 06:45:24 PM PDT 24
Peak memory 191336 kb
Host smart-bd19cd5a-5568-4ce9-8883-092a790582df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893717235 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_timer_random.893717235
Directory /workspace/32.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_cfg_update_on_fly.3243976639
Short name T346
Test name
Test status
Simulation time 134018722742 ps
CPU time 99.15 seconds
Started Jul 17 06:43:45 PM PDT 24
Finished Jul 17 06:45:25 PM PDT 24
Peak memory 183068 kb
Host smart-49d04751-946d-46c8-ac04-bb6aee4f6099
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243976639 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.rv_timer_cfg_update_on_fly.3243976639
Directory /workspace/33.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/33.rv_timer_disabled.2261547191
Short name T67
Test name
Test status
Simulation time 121126470795 ps
CPU time 196.87 seconds
Started Jul 17 06:43:42 PM PDT 24
Finished Jul 17 06:47:00 PM PDT 24
Peak memory 182596 kb
Host smart-14ed3204-0fe6-402e-9cab-28f7ebe1dc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261547191 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_disabled.2261547191
Directory /workspace/33.rv_timer_disabled/latest

Test location /workspace/coverage/default/33.rv_timer_random.1008079468
Short name T117
Test name
Test status
Simulation time 529572954438 ps
CPU time 561.36 seconds
Started Jul 17 06:43:37 PM PDT 24
Finished Jul 17 06:53:00 PM PDT 24
Peak memory 191348 kb
Host smart-2faf78a1-c7eb-4a9e-80f3-3f8068315214
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008079468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random.1008079468
Directory /workspace/33.rv_timer_random/latest

Test location /workspace/coverage/default/33.rv_timer_random_reset.1086836648
Short name T398
Test name
Test status
Simulation time 125873756 ps
CPU time 0.54 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:43:42 PM PDT 24
Peak memory 182928 kb
Host smart-1ffcc791-c7bb-4d00-a645-fd06ad4291cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086836648 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_random_reset.1086836648
Directory /workspace/33.rv_timer_random_reset/latest

Test location /workspace/coverage/default/33.rv_timer_stress_all_with_rand_reset.128186265
Short name T34
Test name
Test status
Simulation time 128597188634 ps
CPU time 470.02 seconds
Started Jul 17 06:43:38 PM PDT 24
Finished Jul 17 06:51:30 PM PDT 24
Peak memory 197852 kb
Host smart-707f00da-265f-49ec-af9f-f0c44471064d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128186265 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.rv_timer_stress_all_with_rand_reset.128186265
Directory /workspace/33.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.rv_timer_cfg_update_on_fly.2024816426
Short name T61
Test name
Test status
Simulation time 843335557762 ps
CPU time 379.61 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:50:01 PM PDT 24
Peak memory 183056 kb
Host smart-6fba4136-c716-4c6e-be6b-78f346c2e7ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024816426 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.rv_timer_cfg_update_on_fly.2024816426
Directory /workspace/34.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/34.rv_timer_disabled.659061586
Short name T421
Test name
Test status
Simulation time 197956959788 ps
CPU time 264.61 seconds
Started Jul 17 06:43:46 PM PDT 24
Finished Jul 17 06:48:11 PM PDT 24
Peak memory 183140 kb
Host smart-c84a715e-0f66-4a2d-86d5-d1e160e5b1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659061586 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_disabled.659061586
Directory /workspace/34.rv_timer_disabled/latest

Test location /workspace/coverage/default/34.rv_timer_random.3877433278
Short name T24
Test name
Test status
Simulation time 208777945299 ps
CPU time 101.52 seconds
Started Jul 17 06:43:37 PM PDT 24
Finished Jul 17 06:45:21 PM PDT 24
Peak memory 183076 kb
Host smart-e854ef97-3570-4adf-9674-df470f5026a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877433278 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random.3877433278
Directory /workspace/34.rv_timer_random/latest

Test location /workspace/coverage/default/34.rv_timer_random_reset.3362958765
Short name T220
Test name
Test status
Simulation time 13138745126 ps
CPU time 20.93 seconds
Started Jul 17 06:43:34 PM PDT 24
Finished Jul 17 06:43:56 PM PDT 24
Peak memory 191312 kb
Host smart-491cfe5f-2651-47e7-86c3-dfd094bffb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362958765 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_timer_random_reset.3362958765
Directory /workspace/34.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_cfg_update_on_fly.4018374715
Short name T452
Test name
Test status
Simulation time 214923455327 ps
CPU time 337.1 seconds
Started Jul 17 06:43:41 PM PDT 24
Finished Jul 17 06:49:19 PM PDT 24
Peak memory 183132 kb
Host smart-96c0737d-11cb-428e-a085-594741b5ac71
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018374715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.rv_timer_cfg_update_on_fly.4018374715
Directory /workspace/35.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/35.rv_timer_disabled.1101842818
Short name T423
Test name
Test status
Simulation time 325541165384 ps
CPU time 234.49 seconds
Started Jul 17 06:43:46 PM PDT 24
Finished Jul 17 06:47:41 PM PDT 24
Peak memory 183136 kb
Host smart-859c368b-f808-4365-8426-cb1655bf8daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101842818 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_disabled.1101842818
Directory /workspace/35.rv_timer_disabled/latest

Test location /workspace/coverage/default/35.rv_timer_random_reset.43269945
Short name T47
Test name
Test status
Simulation time 167055050 ps
CPU time 0.78 seconds
Started Jul 17 06:43:42 PM PDT 24
Finished Jul 17 06:43:44 PM PDT 24
Peak memory 183076 kb
Host smart-7f805d9b-577b-4163-ba9b-e83e10c0d055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43269945 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_random_reset.43269945
Directory /workspace/35.rv_timer_random_reset/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all.381662864
Short name T2
Test name
Test status
Simulation time 598042440797 ps
CPU time 762.86 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:56:24 PM PDT 24
Peak memory 195808 kb
Host smart-7b62201a-900a-4f69-b765-f89203b286c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381662864 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all.
381662864
Directory /workspace/35.rv_timer_stress_all/latest

Test location /workspace/coverage/default/35.rv_timer_stress_all_with_rand_reset.3869655990
Short name T13
Test name
Test status
Simulation time 78106933091 ps
CPU time 277.39 seconds
Started Jul 17 06:43:38 PM PDT 24
Finished Jul 17 06:48:18 PM PDT 24
Peak memory 206056 kb
Host smart-c958a6a6-bb0d-4ff3-b5b1-574c5f9441dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869655990 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.rv_timer_stress_all_with_rand_reset.3869655990
Directory /workspace/35.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.rv_timer_cfg_update_on_fly.1294301185
Short name T321
Test name
Test status
Simulation time 841499234622 ps
CPU time 796.01 seconds
Started Jul 17 06:43:46 PM PDT 24
Finished Jul 17 06:57:03 PM PDT 24
Peak memory 183128 kb
Host smart-bdd636b4-9328-498c-8043-f4faec5ade2f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294301185 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.rv_timer_cfg_update_on_fly.1294301185
Directory /workspace/36.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/36.rv_timer_disabled.3013998090
Short name T401
Test name
Test status
Simulation time 125089220076 ps
CPU time 172.81 seconds
Started Jul 17 06:43:41 PM PDT 24
Finished Jul 17 06:46:35 PM PDT 24
Peak memory 183144 kb
Host smart-c325d71f-b0c5-4fe4-bd35-8d01a78c594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013998090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_disabled.3013998090
Directory /workspace/36.rv_timer_disabled/latest

Test location /workspace/coverage/default/36.rv_timer_random.3852989352
Short name T7
Test name
Test status
Simulation time 52353767029 ps
CPU time 61.95 seconds
Started Jul 17 06:43:36 PM PDT 24
Finished Jul 17 06:44:40 PM PDT 24
Peak memory 183144 kb
Host smart-df4a184a-583f-49a6-b883-f86c19799018
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852989352 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random.3852989352
Directory /workspace/36.rv_timer_random/latest

Test location /workspace/coverage/default/36.rv_timer_random_reset.2460136656
Short name T139
Test name
Test status
Simulation time 848388290402 ps
CPU time 184.96 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:46:46 PM PDT 24
Peak memory 191316 kb
Host smart-71c9e33b-5a95-4181-9dcd-f97e31373807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460136656 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_timer_random_reset.2460136656
Directory /workspace/36.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_cfg_update_on_fly.535926742
Short name T286
Test name
Test status
Simulation time 389122523774 ps
CPU time 666.15 seconds
Started Jul 17 06:43:37 PM PDT 24
Finished Jul 17 06:54:45 PM PDT 24
Peak memory 183148 kb
Host smart-d86cead7-fd3e-4975-8ff5-ef67a031c997
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535926742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.rv_timer_cfg_update_on_fly.535926742
Directory /workspace/37.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/37.rv_timer_random_reset.1685279668
Short name T206
Test name
Test status
Simulation time 90161016142 ps
CPU time 176.91 seconds
Started Jul 17 06:43:36 PM PDT 24
Finished Jul 17 06:46:35 PM PDT 24
Peak memory 183140 kb
Host smart-0d898856-d115-4782-a824-174364bbb971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685279668 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_random_reset.1685279668
Directory /workspace/37.rv_timer_random_reset/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all.1634972859
Short name T371
Test name
Test status
Simulation time 754305870125 ps
CPU time 181.61 seconds
Started Jul 17 06:43:37 PM PDT 24
Finished Jul 17 06:46:41 PM PDT 24
Peak memory 183132 kb
Host smart-29cda22e-d1e0-47d2-a0de-dab6eff2d2f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634972859 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all
.1634972859
Directory /workspace/37.rv_timer_stress_all/latest

Test location /workspace/coverage/default/37.rv_timer_stress_all_with_rand_reset.360794483
Short name T50
Test name
Test status
Simulation time 146107985677 ps
CPU time 245.02 seconds
Started Jul 17 06:43:45 PM PDT 24
Finished Jul 17 06:47:50 PM PDT 24
Peak memory 206024 kb
Host smart-dad3b8fd-040e-40ef-8cd8-cdfd56ee41a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360794483 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.rv_timer_stress_all_with_rand_reset.360794483
Directory /workspace/37.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.rv_timer_cfg_update_on_fly.1717801598
Short name T283
Test name
Test status
Simulation time 2104462823914 ps
CPU time 656.56 seconds
Started Jul 17 06:43:38 PM PDT 24
Finished Jul 17 06:54:36 PM PDT 24
Peak memory 183120 kb
Host smart-5a2993a2-857d-4b81-b575-8b1c1c40a581
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717801598 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.rv_timer_cfg_update_on_fly.1717801598
Directory /workspace/38.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/38.rv_timer_disabled.2516632510
Short name T389
Test name
Test status
Simulation time 367123031990 ps
CPU time 152.1 seconds
Started Jul 17 06:43:38 PM PDT 24
Finished Jul 17 06:46:12 PM PDT 24
Peak memory 183088 kb
Host smart-e219b826-ce66-4059-8994-5cc7e7e641a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516632510 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_disabled.2516632510
Directory /workspace/38.rv_timer_disabled/latest

Test location /workspace/coverage/default/38.rv_timer_random.1495584834
Short name T256
Test name
Test status
Simulation time 235650425698 ps
CPU time 732.42 seconds
Started Jul 17 06:43:38 PM PDT 24
Finished Jul 17 06:55:52 PM PDT 24
Peak memory 191328 kb
Host smart-d97ddbc2-6a77-45cd-a50b-2ff517e45ea2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495584834 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random.1495584834
Directory /workspace/38.rv_timer_random/latest

Test location /workspace/coverage/default/38.rv_timer_random_reset.2253377020
Short name T381
Test name
Test status
Simulation time 253348681 ps
CPU time 0.85 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:43:42 PM PDT 24
Peak memory 182896 kb
Host smart-d00d96db-4de5-4c7d-a623-fd136389162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253377020 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_random_reset.2253377020
Directory /workspace/38.rv_timer_random_reset/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all.3920446154
Short name T129
Test name
Test status
Simulation time 1402136528615 ps
CPU time 1307.82 seconds
Started Jul 17 06:43:44 PM PDT 24
Finished Jul 17 07:05:33 PM PDT 24
Peak memory 191284 kb
Host smart-41aa53c5-d0fe-44eb-bd45-5660713656d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920446154 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all
.3920446154
Directory /workspace/38.rv_timer_stress_all/latest

Test location /workspace/coverage/default/38.rv_timer_stress_all_with_rand_reset.1910733155
Short name T414
Test name
Test status
Simulation time 21798008554 ps
CPU time 124.2 seconds
Started Jul 17 06:43:45 PM PDT 24
Finished Jul 17 06:45:50 PM PDT 24
Peak memory 196576 kb
Host smart-abb4adad-0a94-47ea-9d00-bcf41b1103ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910733155 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.rv_timer_stress_all_with_rand_reset.1910733155
Directory /workspace/38.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.rv_timer_cfg_update_on_fly.3062332642
Short name T337
Test name
Test status
Simulation time 1797974304413 ps
CPU time 422.8 seconds
Started Jul 17 06:43:38 PM PDT 24
Finished Jul 17 06:50:43 PM PDT 24
Peak memory 183080 kb
Host smart-e486c88e-4a1d-418a-b4c9-85ee2e226612
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062332642 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.rv_timer_cfg_update_on_fly.3062332642
Directory /workspace/39.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/39.rv_timer_disabled.127770003
Short name T405
Test name
Test status
Simulation time 20888825345 ps
CPU time 8.15 seconds
Started Jul 17 06:43:37 PM PDT 24
Finished Jul 17 06:43:47 PM PDT 24
Peak memory 183152 kb
Host smart-c0758438-d262-4cdd-86bf-33b1d898dede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127770003 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_disabled.127770003
Directory /workspace/39.rv_timer_disabled/latest

Test location /workspace/coverage/default/39.rv_timer_random.668534564
Short name T19
Test name
Test status
Simulation time 62686949332 ps
CPU time 60.86 seconds
Started Jul 17 06:43:42 PM PDT 24
Finished Jul 17 06:44:44 PM PDT 24
Peak memory 183228 kb
Host smart-d611d1b5-d9ea-4125-83f0-3bbad33a5572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668534564 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random.668534564
Directory /workspace/39.rv_timer_random/latest

Test location /workspace/coverage/default/39.rv_timer_random_reset.4060086238
Short name T391
Test name
Test status
Simulation time 821462044 ps
CPU time 0.93 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:43:43 PM PDT 24
Peak memory 191624 kb
Host smart-01b9d18f-9695-4e96-966c-72212da51f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060086238 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_random_reset.4060086238
Directory /workspace/39.rv_timer_random_reset/latest

Test location /workspace/coverage/default/39.rv_timer_stress_all_with_rand_reset.3553992387
Short name T38
Test name
Test status
Simulation time 60055270921 ps
CPU time 497.61 seconds
Started Jul 17 06:43:39 PM PDT 24
Finished Jul 17 06:51:58 PM PDT 24
Peak memory 206044 kb
Host smart-0f104cb2-7f66-4260-b0ef-587cd493baba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553992387 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.rv_timer_stress_all_with_rand_reset.3553992387
Directory /workspace/39.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_timer_cfg_update_on_fly.4167020857
Short name T211
Test name
Test status
Simulation time 81313479825 ps
CPU time 47.45 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:43:42 PM PDT 24
Peak memory 183084 kb
Host smart-e39b8b87-5a2a-4505-8a53-2ca7c74a5ca8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167020857 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.rv_timer_cfg_update_on_fly.4167020857
Directory /workspace/4.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/4.rv_timer_disabled.1338097067
Short name T362
Test name
Test status
Simulation time 364095784148 ps
CPU time 150.96 seconds
Started Jul 17 06:42:54 PM PDT 24
Finished Jul 17 06:45:26 PM PDT 24
Peak memory 183128 kb
Host smart-b4f0ae53-1357-4115-a22c-0b915ce8411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338097067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_disabled.1338097067
Directory /workspace/4.rv_timer_disabled/latest

Test location /workspace/coverage/default/4.rv_timer_random_reset.1191986203
Short name T427
Test name
Test status
Simulation time 281725384 ps
CPU time 0.67 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:42:54 PM PDT 24
Peak memory 182928 kb
Host smart-28d897f4-bbd0-4f61-9ffb-8af17cb663dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191986203 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_random_reset.1191986203
Directory /workspace/4.rv_timer_random_reset/latest

Test location /workspace/coverage/default/4.rv_timer_sec_cm.943257237
Short name T18
Test name
Test status
Simulation time 759021031 ps
CPU time 0.95 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:42:56 PM PDT 24
Peak memory 214488 kb
Host smart-b9228ab6-5c23-4c47-9d58-a8a2cd69f513
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943257237 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_sec_cm.943257237
Directory /workspace/4.rv_timer_sec_cm/latest

Test location /workspace/coverage/default/4.rv_timer_stress_all.976483298
Short name T434
Test name
Test status
Simulation time 90681376299 ps
CPU time 40.29 seconds
Started Jul 17 06:42:51 PM PDT 24
Finished Jul 17 06:43:32 PM PDT 24
Peak memory 194772 kb
Host smart-5e2e1d5e-1d33-4828-a0aa-224fbefb4648
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976483298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_timer_stress_all.976483298
Directory /workspace/4.rv_timer_stress_all/latest

Test location /workspace/coverage/default/40.rv_timer_cfg_update_on_fly.4061983555
Short name T251
Test name
Test status
Simulation time 116352769733 ps
CPU time 217.14 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:47:19 PM PDT 24
Peak memory 183072 kb
Host smart-1fba7a83-1414-4e7d-b18f-c4b080736757
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061983555 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.rv_timer_cfg_update_on_fly.4061983555
Directory /workspace/40.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/40.rv_timer_disabled.1746078046
Short name T433
Test name
Test status
Simulation time 245773554135 ps
CPU time 69.19 seconds
Started Jul 17 06:43:46 PM PDT 24
Finished Jul 17 06:44:56 PM PDT 24
Peak memory 183136 kb
Host smart-ca8a59e0-cdd9-44ff-bed9-7b92f219edd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746078046 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_disabled.1746078046
Directory /workspace/40.rv_timer_disabled/latest

Test location /workspace/coverage/default/40.rv_timer_random.1149587146
Short name T165
Test name
Test status
Simulation time 319512066388 ps
CPU time 1058.31 seconds
Started Jul 17 06:43:42 PM PDT 24
Finished Jul 17 07:01:22 PM PDT 24
Peak memory 191500 kb
Host smart-ad34bce4-903c-41eb-8b3b-62836fa7c9fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149587146 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random.1149587146
Directory /workspace/40.rv_timer_random/latest

Test location /workspace/coverage/default/40.rv_timer_random_reset.355925707
Short name T436
Test name
Test status
Simulation time 96865459499 ps
CPU time 84.51 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:45:06 PM PDT 24
Peak memory 183148 kb
Host smart-11a9c940-8c32-40d6-b56e-6437c1da4f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355925707 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_random_reset.355925707
Directory /workspace/40.rv_timer_random_reset/latest

Test location /workspace/coverage/default/40.rv_timer_stress_all.2422504535
Short name T367
Test name
Test status
Simulation time 3681654677 ps
CPU time 6.18 seconds
Started Jul 17 06:43:45 PM PDT 24
Finished Jul 17 06:43:52 PM PDT 24
Peak memory 193180 kb
Host smart-b042266e-241e-4900-b710-257e016f4c88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422504535 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_timer_stress_all
.2422504535
Directory /workspace/40.rv_timer_stress_all/latest

Test location /workspace/coverage/default/41.rv_timer_cfg_update_on_fly.24184718
Short name T355
Test name
Test status
Simulation time 914470973549 ps
CPU time 376.04 seconds
Started Jul 17 06:43:42 PM PDT 24
Finished Jul 17 06:49:59 PM PDT 24
Peak memory 183152 kb
Host smart-94d04c10-c2c3-4af4-9f0b-e45ed51d1b4b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24184718 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.rv_timer_cfg_update_on_fly.24184718
Directory /workspace/41.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/41.rv_timer_disabled.896888400
Short name T407
Test name
Test status
Simulation time 755904305737 ps
CPU time 139.32 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:46:01 PM PDT 24
Peak memory 183140 kb
Host smart-556c1973-3492-45fe-9de4-31c556b8c0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896888400 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_disabled.896888400
Directory /workspace/41.rv_timer_disabled/latest

Test location /workspace/coverage/default/41.rv_timer_random.422675255
Short name T264
Test name
Test status
Simulation time 34306570090 ps
CPU time 64.06 seconds
Started Jul 17 06:43:40 PM PDT 24
Finished Jul 17 06:44:46 PM PDT 24
Peak memory 183140 kb
Host smart-ae8b8e97-8a95-4745-ac4a-b8c6460dbc64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422675255 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random.422675255
Directory /workspace/41.rv_timer_random/latest

Test location /workspace/coverage/default/41.rv_timer_random_reset.3800109776
Short name T430
Test name
Test status
Simulation time 202211695 ps
CPU time 0.75 seconds
Started Jul 17 06:43:50 PM PDT 24
Finished Jul 17 06:43:51 PM PDT 24
Peak memory 182944 kb
Host smart-ba03e5c7-fb96-403f-ba69-f891b559f57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800109776 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_random_reset.3800109776
Directory /workspace/41.rv_timer_random_reset/latest

Test location /workspace/coverage/default/41.rv_timer_stress_all.3878077365
Short name T173
Test name
Test status
Simulation time 123632544453 ps
CPU time 108.63 seconds
Started Jul 17 06:43:51 PM PDT 24
Finished Jul 17 06:45:41 PM PDT 24
Peak memory 191284 kb
Host smart-840abf93-9014-4abe-9f0e-c163d6661652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878077365 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_timer_stress_all
.3878077365
Directory /workspace/41.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_cfg_update_on_fly.3315519471
Short name T343
Test name
Test status
Simulation time 550942286044 ps
CPU time 502.7 seconds
Started Jul 17 06:43:51 PM PDT 24
Finished Jul 17 06:52:15 PM PDT 24
Peak memory 183124 kb
Host smart-984961f3-ab96-4c90-8f2a-cf8fb1657754
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315519471 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.rv_timer_cfg_update_on_fly.3315519471
Directory /workspace/42.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/42.rv_timer_disabled.2342932302
Short name T425
Test name
Test status
Simulation time 462511069290 ps
CPU time 182.51 seconds
Started Jul 17 06:43:52 PM PDT 24
Finished Jul 17 06:46:55 PM PDT 24
Peak memory 183148 kb
Host smart-320e4855-4aac-43dc-a2f0-684ce63be136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342932302 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_disabled.2342932302
Directory /workspace/42.rv_timer_disabled/latest

Test location /workspace/coverage/default/42.rv_timer_random.358134200
Short name T358
Test name
Test status
Simulation time 12215579086 ps
CPU time 18.9 seconds
Started Jul 17 06:43:51 PM PDT 24
Finished Jul 17 06:44:11 PM PDT 24
Peak memory 183000 kb
Host smart-e458b5ff-c15c-4d21-8746-c721534946ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358134200 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random.358134200
Directory /workspace/42.rv_timer_random/latest

Test location /workspace/coverage/default/42.rv_timer_random_reset.3451444443
Short name T8
Test name
Test status
Simulation time 112928514685 ps
CPU time 48.72 seconds
Started Jul 17 06:43:55 PM PDT 24
Finished Jul 17 06:44:45 PM PDT 24
Peak memory 194400 kb
Host smart-ecc4ad6c-85ec-4d3b-859c-fe96d9257588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451444443 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_random_reset.3451444443
Directory /workspace/42.rv_timer_random_reset/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all.1268948583
Short name T158
Test name
Test status
Simulation time 1371180909830 ps
CPU time 1180.08 seconds
Started Jul 17 06:43:54 PM PDT 24
Finished Jul 17 07:03:35 PM PDT 24
Peak memory 191332 kb
Host smart-40b60982-cbeb-4b86-b44e-14a72e6a559a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268948583 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all
.1268948583
Directory /workspace/42.rv_timer_stress_all/latest

Test location /workspace/coverage/default/42.rv_timer_stress_all_with_rand_reset.2948027923
Short name T35
Test name
Test status
Simulation time 198486725038 ps
CPU time 566.41 seconds
Started Jul 17 06:43:51 PM PDT 24
Finished Jul 17 06:53:18 PM PDT 24
Peak memory 206144 kb
Host smart-ea2b27d9-13fe-4761-b367-6432beb1d53b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948027923 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.rv_timer_stress_all_with_rand_reset.2948027923
Directory /workspace/42.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.rv_timer_cfg_update_on_fly.54621962
Short name T142
Test name
Test status
Simulation time 165135918173 ps
CPU time 101.58 seconds
Started Jul 17 06:43:54 PM PDT 24
Finished Jul 17 06:45:37 PM PDT 24
Peak memory 183108 kb
Host smart-3e169467-f555-44b5-9f14-34bc96f35201
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54621962 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=r
v_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.rv_timer_cfg_update_on_fly.54621962
Directory /workspace/43.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/43.rv_timer_disabled.3807309874
Short name T454
Test name
Test status
Simulation time 322783926152 ps
CPU time 132.8 seconds
Started Jul 17 06:43:51 PM PDT 24
Finished Jul 17 06:46:05 PM PDT 24
Peak memory 183088 kb
Host smart-6204ed1a-3b3e-4728-9f25-4c0f575cf5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807309874 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_disabled.3807309874
Directory /workspace/43.rv_timer_disabled/latest

Test location /workspace/coverage/default/43.rv_timer_random_reset.2316162516
Short name T266
Test name
Test status
Simulation time 50542659913 ps
CPU time 276.01 seconds
Started Jul 17 06:43:52 PM PDT 24
Finished Jul 17 06:48:29 PM PDT 24
Peak memory 191336 kb
Host smart-554c3aad-2b0d-4800-a111-6235a3fcc394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316162516 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_random_reset.2316162516
Directory /workspace/43.rv_timer_random_reset/latest

Test location /workspace/coverage/default/43.rv_timer_stress_all_with_rand_reset.344907823
Short name T51
Test name
Test status
Simulation time 86225669350 ps
CPU time 649.64 seconds
Started Jul 17 06:44:04 PM PDT 24
Finished Jul 17 06:54:56 PM PDT 24
Peak memory 206044 kb
Host smart-fd8410d4-3bba-4699-ac8b-a1f75ae1b5a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344907823 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.rv_timer_stress_all_with_rand_reset.344907823
Directory /workspace/43.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.rv_timer_cfg_update_on_fly.857195641
Short name T146
Test name
Test status
Simulation time 45776056714 ps
CPU time 77.47 seconds
Started Jul 17 06:44:01 PM PDT 24
Finished Jul 17 06:45:21 PM PDT 24
Peak memory 183136 kb
Host smart-525a8971-d2e0-4345-95be-0073d680c5ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857195641 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.rv_timer_cfg_update_on_fly.857195641
Directory /workspace/44.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/44.rv_timer_disabled.4100753750
Short name T372
Test name
Test status
Simulation time 179012801035 ps
CPU time 280.34 seconds
Started Jul 17 06:44:02 PM PDT 24
Finished Jul 17 06:48:45 PM PDT 24
Peak memory 183128 kb
Host smart-d1b75ed6-8f55-42ca-bba9-1ee3f7f44e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100753750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_disabled.4100753750
Directory /workspace/44.rv_timer_disabled/latest

Test location /workspace/coverage/default/44.rv_timer_random_reset.3117916607
Short name T383
Test name
Test status
Simulation time 1023875375 ps
CPU time 1.18 seconds
Started Jul 17 06:44:02 PM PDT 24
Finished Jul 17 06:44:05 PM PDT 24
Peak memory 191132 kb
Host smart-bfd51b73-1d09-45de-a6ab-684059e4ae01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117916607 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_random_reset.3117916607
Directory /workspace/44.rv_timer_random_reset/latest

Test location /workspace/coverage/default/44.rv_timer_stress_all.2095704298
Short name T56
Test name
Test status
Simulation time 294414124169 ps
CPU time 364.51 seconds
Started Jul 17 06:44:03 PM PDT 24
Finished Jul 17 06:50:09 PM PDT 24
Peak memory 193456 kb
Host smart-526554d3-1659-4c36-b6ac-dccd5b173ec5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095704298 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_timer_stress_all
.2095704298
Directory /workspace/44.rv_timer_stress_all/latest

Test location /workspace/coverage/default/45.rv_timer_cfg_update_on_fly.2094757750
Short name T338
Test name
Test status
Simulation time 22014753714 ps
CPU time 11.97 seconds
Started Jul 17 06:44:03 PM PDT 24
Finished Jul 17 06:44:17 PM PDT 24
Peak memory 183128 kb
Host smart-367d2f1f-63d7-4938-8ce9-1ab072b5407e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094757750 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.rv_timer_cfg_update_on_fly.2094757750
Directory /workspace/45.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/45.rv_timer_disabled.2833595422
Short name T394
Test name
Test status
Simulation time 87965940374 ps
CPU time 126.58 seconds
Started Jul 17 06:44:02 PM PDT 24
Finished Jul 17 06:46:11 PM PDT 24
Peak memory 183100 kb
Host smart-987b969b-e4fd-4765-9c3b-db1c139f70b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833595422 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_disabled.2833595422
Directory /workspace/45.rv_timer_disabled/latest

Test location /workspace/coverage/default/45.rv_timer_random.1685108335
Short name T218
Test name
Test status
Simulation time 120462766483 ps
CPU time 151.24 seconds
Started Jul 17 06:44:02 PM PDT 24
Finished Jul 17 06:46:36 PM PDT 24
Peak memory 191340 kb
Host smart-8d0de28e-c0d6-4168-967f-a083fe20df6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685108335 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_timer_random.1685108335
Directory /workspace/45.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_cfg_update_on_fly.972141113
Short name T132
Test name
Test status
Simulation time 46685687963 ps
CPU time 48 seconds
Started Jul 17 06:44:15 PM PDT 24
Finished Jul 17 06:45:04 PM PDT 24
Peak memory 183136 kb
Host smart-c85e2d8e-d10b-4219-9f89-53a233dabb16
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972141113 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=
rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.rv_timer_cfg_update_on_fly.972141113
Directory /workspace/46.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/46.rv_timer_disabled.1321343468
Short name T10
Test name
Test status
Simulation time 169900688198 ps
CPU time 245.21 seconds
Started Jul 17 06:44:15 PM PDT 24
Finished Jul 17 06:48:21 PM PDT 24
Peak memory 183132 kb
Host smart-d5c0e709-4198-4149-a35a-7ee263e0ed25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321343468 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_disabled.1321343468
Directory /workspace/46.rv_timer_disabled/latest

Test location /workspace/coverage/default/46.rv_timer_random.1544078301
Short name T177
Test name
Test status
Simulation time 398475116082 ps
CPU time 952.22 seconds
Started Jul 17 06:44:14 PM PDT 24
Finished Jul 17 07:00:08 PM PDT 24
Peak memory 191336 kb
Host smart-421020c1-2eb5-4759-974d-0776bc061fc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544078301 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random.1544078301
Directory /workspace/46.rv_timer_random/latest

Test location /workspace/coverage/default/46.rv_timer_random_reset.2274810480
Short name T399
Test name
Test status
Simulation time 109970192 ps
CPU time 0.71 seconds
Started Jul 17 06:44:17 PM PDT 24
Finished Jul 17 06:44:19 PM PDT 24
Peak memory 182940 kb
Host smart-b73392dd-e3f1-45e3-8b0a-d6a0b59921d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274810480 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_timer_random_reset.2274810480
Directory /workspace/46.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_cfg_update_on_fly.2003358681
Short name T420
Test name
Test status
Simulation time 534226175039 ps
CPU time 269.56 seconds
Started Jul 17 06:44:14 PM PDT 24
Finished Jul 17 06:48:44 PM PDT 24
Peak memory 183128 kb
Host smart-087ee730-f1a4-4a66-8994-a7015a1d734e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003358681 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.rv_timer_cfg_update_on_fly.2003358681
Directory /workspace/47.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/47.rv_timer_disabled.1787343825
Short name T375
Test name
Test status
Simulation time 708477617424 ps
CPU time 272.22 seconds
Started Jul 17 06:44:14 PM PDT 24
Finished Jul 17 06:48:47 PM PDT 24
Peak memory 183108 kb
Host smart-389d7bd7-51b8-4ba4-beba-0bc9299cbeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787343825 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_disabled.1787343825
Directory /workspace/47.rv_timer_disabled/latest

Test location /workspace/coverage/default/47.rv_timer_random.4187534418
Short name T415
Test name
Test status
Simulation time 137902529699 ps
CPU time 1190.74 seconds
Started Jul 17 06:44:14 PM PDT 24
Finished Jul 17 07:04:06 PM PDT 24
Peak memory 183140 kb
Host smart-3459abf3-7e2e-4674-9e93-d1baf01e31cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187534418 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random.4187534418
Directory /workspace/47.rv_timer_random/latest

Test location /workspace/coverage/default/47.rv_timer_random_reset.2021681742
Short name T193
Test name
Test status
Simulation time 68253346673 ps
CPU time 142.59 seconds
Started Jul 17 06:44:15 PM PDT 24
Finished Jul 17 06:46:39 PM PDT 24
Peak memory 195740 kb
Host smart-c1e65c1c-8a67-4b90-a55d-c1dd5e4480aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021681742 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_random_reset.2021681742
Directory /workspace/47.rv_timer_random_reset/latest

Test location /workspace/coverage/default/47.rv_timer_stress_all.2094397283
Short name T150
Test name
Test status
Simulation time 142108889455 ps
CPU time 228.13 seconds
Started Jul 17 06:44:14 PM PDT 24
Finished Jul 17 06:48:04 PM PDT 24
Peak memory 191256 kb
Host smart-2de4bb88-ea4b-4cf1-9c4e-a8fc79864acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094397283 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_timer_stress_all
.2094397283
Directory /workspace/47.rv_timer_stress_all/latest

Test location /workspace/coverage/default/48.rv_timer_cfg_update_on_fly.1324059385
Short name T118
Test name
Test status
Simulation time 321479911835 ps
CPU time 547.72 seconds
Started Jul 17 06:44:25 PM PDT 24
Finished Jul 17 06:53:33 PM PDT 24
Peak memory 183292 kb
Host smart-a1e1f5a3-9dea-4ee4-b169-67d5ad74625b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324059385 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.rv_timer_cfg_update_on_fly.1324059385
Directory /workspace/48.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/48.rv_timer_disabled.1855879067
Short name T451
Test name
Test status
Simulation time 80361204433 ps
CPU time 114.47 seconds
Started Jul 17 06:44:26 PM PDT 24
Finished Jul 17 06:46:22 PM PDT 24
Peak memory 183152 kb
Host smart-8c1134d8-e6f7-498d-9744-495a4405fbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855879067 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_disabled.1855879067
Directory /workspace/48.rv_timer_disabled/latest

Test location /workspace/coverage/default/48.rv_timer_random.1305989260
Short name T250
Test name
Test status
Simulation time 105923979823 ps
CPU time 219.87 seconds
Started Jul 17 06:44:26 PM PDT 24
Finished Jul 17 06:48:07 PM PDT 24
Peak memory 191504 kb
Host smart-19ae544e-0dbf-4e75-a975-809afadb6572
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305989260 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random.1305989260
Directory /workspace/48.rv_timer_random/latest

Test location /workspace/coverage/default/48.rv_timer_random_reset.2840515884
Short name T380
Test name
Test status
Simulation time 11904471860 ps
CPU time 11.08 seconds
Started Jul 17 06:44:27 PM PDT 24
Finished Jul 17 06:44:39 PM PDT 24
Peak memory 194564 kb
Host smart-1d2f668b-951d-4796-b125-0c72cd9d3156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840515884 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_random_reset.2840515884
Directory /workspace/48.rv_timer_random_reset/latest

Test location /workspace/coverage/default/48.rv_timer_stress_all.3224602440
Short name T55
Test name
Test status
Simulation time 123284917811 ps
CPU time 218.44 seconds
Started Jul 17 06:44:28 PM PDT 24
Finished Jul 17 06:48:07 PM PDT 24
Peak memory 195332 kb
Host smart-1da9ef0f-0d10-48ed-ae13-4b44d3e82139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224602440 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_timer_stress_all
.3224602440
Directory /workspace/48.rv_timer_stress_all/latest

Test location /workspace/coverage/default/49.rv_timer_cfg_update_on_fly.2606164339
Short name T188
Test name
Test status
Simulation time 239216551497 ps
CPU time 427.11 seconds
Started Jul 17 06:44:28 PM PDT 24
Finished Jul 17 06:51:36 PM PDT 24
Peak memory 183068 kb
Host smart-52b6b894-a26c-4e66-992c-30afb2172f81
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606164339 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.rv_timer_cfg_update_on_fly.2606164339
Directory /workspace/49.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/49.rv_timer_disabled.924890300
Short name T363
Test name
Test status
Simulation time 67489789713 ps
CPU time 97.98 seconds
Started Jul 17 06:44:25 PM PDT 24
Finished Jul 17 06:46:04 PM PDT 24
Peak memory 182928 kb
Host smart-b62c532a-5936-464a-8f32-2782198a1a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924890300 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_disabled.924890300
Directory /workspace/49.rv_timer_disabled/latest

Test location /workspace/coverage/default/49.rv_timer_random.2209152141
Short name T344
Test name
Test status
Simulation time 94318289292 ps
CPU time 89.26 seconds
Started Jul 17 06:44:26 PM PDT 24
Finished Jul 17 06:45:56 PM PDT 24
Peak memory 191288 kb
Host smart-3b4b3445-9611-40c8-ad90-259954ff3415
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209152141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random.2209152141
Directory /workspace/49.rv_timer_random/latest

Test location /workspace/coverage/default/49.rv_timer_random_reset.1213312868
Short name T26
Test name
Test status
Simulation time 89301731481 ps
CPU time 318.93 seconds
Started Jul 17 06:44:24 PM PDT 24
Finished Jul 17 06:49:44 PM PDT 24
Peak memory 191352 kb
Host smart-cfe56e44-276d-47aa-9dee-da17a221d189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213312868 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_random_reset.1213312868
Directory /workspace/49.rv_timer_random_reset/latest

Test location /workspace/coverage/default/49.rv_timer_stress_all.1295989228
Short name T384
Test name
Test status
Simulation time 335371999217 ps
CPU time 268.03 seconds
Started Jul 17 06:44:30 PM PDT 24
Finished Jul 17 06:48:59 PM PDT 24
Peak memory 183096 kb
Host smart-21eb19c2-87aa-4a73-a316-1b9b5f648890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295989228 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_timer_stress_all
.1295989228
Directory /workspace/49.rv_timer_stress_all/latest

Test location /workspace/coverage/default/5.rv_timer_cfg_update_on_fly.3683110951
Short name T290
Test name
Test status
Simulation time 14982173961 ps
CPU time 13.88 seconds
Started Jul 17 06:42:50 PM PDT 24
Finished Jul 17 06:43:05 PM PDT 24
Peak memory 183128 kb
Host smart-66c0127f-47e0-4c3d-8ab9-51cf1e27db0c
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683110951 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.rv_timer_cfg_update_on_fly.3683110951
Directory /workspace/5.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/5.rv_timer_disabled.3962006512
Short name T370
Test name
Test status
Simulation time 109939337143 ps
CPU time 159.48 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:45:34 PM PDT 24
Peak memory 183148 kb
Host smart-e4189439-be37-402a-955a-b9aeacb01bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962006512 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_disabled.3962006512
Directory /workspace/5.rv_timer_disabled/latest

Test location /workspace/coverage/default/5.rv_timer_random.1772202507
Short name T124
Test name
Test status
Simulation time 216781890321 ps
CPU time 952.02 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:58:49 PM PDT 24
Peak memory 191348 kb
Host smart-1a610d5b-e0e0-4c62-892e-a6d128dc8f6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772202507 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random.1772202507
Directory /workspace/5.rv_timer_random/latest

Test location /workspace/coverage/default/5.rv_timer_random_reset.2933655010
Short name T198
Test name
Test status
Simulation time 31855014561 ps
CPU time 41.36 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:43:35 PM PDT 24
Peak memory 183132 kb
Host smart-938064d6-91f2-407a-95ba-7565873a9fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933655010 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_random_reset.2933655010
Directory /workspace/5.rv_timer_random_reset/latest

Test location /workspace/coverage/default/5.rv_timer_stress_all.1703057315
Short name T400
Test name
Test status
Simulation time 65538092021 ps
CPU time 51.88 seconds
Started Jul 17 06:42:54 PM PDT 24
Finished Jul 17 06:43:47 PM PDT 24
Peak memory 191288 kb
Host smart-03e44d07-b69e-4c69-a8f7-0701fa1087b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703057315 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_timer_stress_all.
1703057315
Directory /workspace/5.rv_timer_stress_all/latest

Test location /workspace/coverage/default/50.rv_timer_random.606013324
Short name T60
Test name
Test status
Simulation time 311806525722 ps
CPU time 62.17 seconds
Started Jul 17 06:44:27 PM PDT 24
Finished Jul 17 06:45:30 PM PDT 24
Peak memory 191336 kb
Host smart-9f43b000-f04e-442a-b2c0-0dac5f402e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606013324 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.rv_timer_random.606013324
Directory /workspace/50.rv_timer_random/latest

Test location /workspace/coverage/default/51.rv_timer_random.3100906767
Short name T91
Test name
Test status
Simulation time 282822798555 ps
CPU time 128.18 seconds
Started Jul 17 06:44:26 PM PDT 24
Finished Jul 17 06:46:35 PM PDT 24
Peak memory 191340 kb
Host smart-6baabb10-406a-4900-8e4d-e9ae359b10d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100906767 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.rv_timer_random.3100906767
Directory /workspace/51.rv_timer_random/latest

Test location /workspace/coverage/default/53.rv_timer_random.2914924617
Short name T161
Test name
Test status
Simulation time 219120726793 ps
CPU time 258.46 seconds
Started Jul 17 06:44:24 PM PDT 24
Finished Jul 17 06:48:43 PM PDT 24
Peak memory 192300 kb
Host smart-cf0b6382-787f-4af4-a844-2c2145e98842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914924617 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.rv_timer_random.2914924617
Directory /workspace/53.rv_timer_random/latest

Test location /workspace/coverage/default/55.rv_timer_random.2701344771
Short name T236
Test name
Test status
Simulation time 589353070947 ps
CPU time 423.38 seconds
Started Jul 17 06:44:25 PM PDT 24
Finished Jul 17 06:51:30 PM PDT 24
Peak memory 191336 kb
Host smart-00ad9562-a7c2-4438-a0d5-64287fd05d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701344771 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.rv_timer_random.2701344771
Directory /workspace/55.rv_timer_random/latest

Test location /workspace/coverage/default/56.rv_timer_random.3576965558
Short name T257
Test name
Test status
Simulation time 28670322372 ps
CPU time 40.64 seconds
Started Jul 17 06:44:25 PM PDT 24
Finished Jul 17 06:45:07 PM PDT 24
Peak memory 183068 kb
Host smart-7a8af997-7813-4032-9d61-5b483de9f5bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576965558 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.rv_timer_random.3576965558
Directory /workspace/56.rv_timer_random/latest

Test location /workspace/coverage/default/57.rv_timer_random.3990496220
Short name T328
Test name
Test status
Simulation time 282605230426 ps
CPU time 167.59 seconds
Started Jul 17 06:44:25 PM PDT 24
Finished Jul 17 06:47:14 PM PDT 24
Peak memory 191288 kb
Host smart-bc2196f6-8e3f-4309-ae65-e3c0ee8b5aac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990496220 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.rv_timer_random.3990496220
Directory /workspace/57.rv_timer_random/latest

Test location /workspace/coverage/default/58.rv_timer_random.1658781782
Short name T307
Test name
Test status
Simulation time 413520890526 ps
CPU time 358.87 seconds
Started Jul 17 06:44:26 PM PDT 24
Finished Jul 17 06:50:26 PM PDT 24
Peak memory 191340 kb
Host smart-798626e6-4cbc-4775-ac02-20e72719de42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658781782 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.rv_timer_random.1658781782
Directory /workspace/58.rv_timer_random/latest

Test location /workspace/coverage/default/59.rv_timer_random.2160346139
Short name T162
Test name
Test status
Simulation time 603500089240 ps
CPU time 538.84 seconds
Started Jul 17 06:44:26 PM PDT 24
Finished Jul 17 06:53:26 PM PDT 24
Peak memory 191340 kb
Host smart-fdb961e7-e00b-4a97-9d3c-123ff820fbb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160346139 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.rv_timer_random.2160346139
Directory /workspace/59.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_cfg_update_on_fly.1575304106
Short name T135
Test name
Test status
Simulation time 211486370205 ps
CPU time 378.95 seconds
Started Jul 17 06:42:54 PM PDT 24
Finished Jul 17 06:49:14 PM PDT 24
Peak memory 183080 kb
Host smart-3afae414-3002-42bc-b2d4-acc30ffa3913
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575304106 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.rv_timer_cfg_update_on_fly.1575304106
Directory /workspace/6.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/6.rv_timer_disabled.2765864078
Short name T411
Test name
Test status
Simulation time 144568252680 ps
CPU time 53.42 seconds
Started Jul 17 06:42:52 PM PDT 24
Finished Jul 17 06:43:46 PM PDT 24
Peak memory 183152 kb
Host smart-0337772e-0634-4dc5-ac7d-6eca1eef3416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765864078 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_disabled.2765864078
Directory /workspace/6.rv_timer_disabled/latest

Test location /workspace/coverage/default/6.rv_timer_random.3526788770
Short name T238
Test name
Test status
Simulation time 76426326301 ps
CPU time 139.47 seconds
Started Jul 17 06:42:53 PM PDT 24
Finished Jul 17 06:45:14 PM PDT 24
Peak memory 194848 kb
Host smart-e613723d-f94f-471e-94db-48cff75c6f33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526788770 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random.3526788770
Directory /workspace/6.rv_timer_random/latest

Test location /workspace/coverage/default/6.rv_timer_random_reset.3341832246
Short name T419
Test name
Test status
Simulation time 33797500385 ps
CPU time 1176.03 seconds
Started Jul 17 06:42:55 PM PDT 24
Finished Jul 17 07:02:32 PM PDT 24
Peak memory 183140 kb
Host smart-6bec921b-d514-4775-b9ec-02f9df988868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341832246 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_timer_random_reset.3341832246
Directory /workspace/6.rv_timer_random_reset/latest

Test location /workspace/coverage/default/61.rv_timer_random.2748612901
Short name T195
Test name
Test status
Simulation time 313189877137 ps
CPU time 604.48 seconds
Started Jul 17 06:44:29 PM PDT 24
Finished Jul 17 06:54:34 PM PDT 24
Peak memory 191308 kb
Host smart-c1e6e630-8307-4e0b-a376-6f336c5d3b02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748612901 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.rv_timer_random.2748612901
Directory /workspace/61.rv_timer_random/latest

Test location /workspace/coverage/default/62.rv_timer_random.3199652543
Short name T130
Test name
Test status
Simulation time 166771470506 ps
CPU time 290.31 seconds
Started Jul 17 06:44:24 PM PDT 24
Finished Jul 17 06:49:16 PM PDT 24
Peak memory 191336 kb
Host smart-d8177e53-9d5b-4477-887f-467a873d6357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199652543 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.rv_timer_random.3199652543
Directory /workspace/62.rv_timer_random/latest

Test location /workspace/coverage/default/63.rv_timer_random.4169595170
Short name T106
Test name
Test status
Simulation time 342405117061 ps
CPU time 446.8 seconds
Started Jul 17 06:44:22 PM PDT 24
Finished Jul 17 06:51:50 PM PDT 24
Peak memory 183140 kb
Host smart-234a3bbf-e76a-4d7a-aa51-865992345477
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169595170 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.rv_timer_random.4169595170
Directory /workspace/63.rv_timer_random/latest

Test location /workspace/coverage/default/64.rv_timer_random.1459515637
Short name T187
Test name
Test status
Simulation time 80466040517 ps
CPU time 784.06 seconds
Started Jul 17 06:44:36 PM PDT 24
Finished Jul 17 06:57:41 PM PDT 24
Peak memory 191344 kb
Host smart-a69b1987-4fa9-4732-9acf-8344ff22279a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459515637 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.rv_timer_random.1459515637
Directory /workspace/64.rv_timer_random/latest

Test location /workspace/coverage/default/65.rv_timer_random.3039475670
Short name T143
Test name
Test status
Simulation time 157136851209 ps
CPU time 258.03 seconds
Started Jul 17 06:44:36 PM PDT 24
Finished Jul 17 06:48:55 PM PDT 24
Peak memory 195140 kb
Host smart-6e43f998-22f4-4de0-943f-58737bce28af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039475670 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.rv_timer_random.3039475670
Directory /workspace/65.rv_timer_random/latest

Test location /workspace/coverage/default/66.rv_timer_random.1397879143
Short name T213
Test name
Test status
Simulation time 69711329663 ps
CPU time 293.59 seconds
Started Jul 17 06:44:37 PM PDT 24
Finished Jul 17 06:49:32 PM PDT 24
Peak memory 191336 kb
Host smart-f703e652-476b-4889-b158-2d64dea23d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397879143 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.rv_timer_random.1397879143
Directory /workspace/66.rv_timer_random/latest

Test location /workspace/coverage/default/67.rv_timer_random.3585736616
Short name T240
Test name
Test status
Simulation time 1201304315796 ps
CPU time 574.98 seconds
Started Jul 17 06:44:37 PM PDT 24
Finished Jul 17 06:54:13 PM PDT 24
Peak memory 191264 kb
Host smart-58e319fe-d4f1-4047-9ce6-82c68290f956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585736616 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.rv_timer_random.3585736616
Directory /workspace/67.rv_timer_random/latest

Test location /workspace/coverage/default/68.rv_timer_random.1740851677
Short name T181
Test name
Test status
Simulation time 19683066671 ps
CPU time 12.87 seconds
Started Jul 17 06:44:36 PM PDT 24
Finished Jul 17 06:44:49 PM PDT 24
Peak memory 183000 kb
Host smart-39963719-fb4a-414b-99b4-a52742c4513b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740851677 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.rv_timer_random.1740851677
Directory /workspace/68.rv_timer_random/latest

Test location /workspace/coverage/default/69.rv_timer_random.3682168533
Short name T179
Test name
Test status
Simulation time 122896619562 ps
CPU time 547.32 seconds
Started Jul 17 06:44:36 PM PDT 24
Finished Jul 17 06:53:43 PM PDT 24
Peak memory 191252 kb
Host smart-94448c24-79de-4325-8a21-3547afe9d5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682168533 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.rv_timer_random.3682168533
Directory /workspace/69.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_cfg_update_on_fly.1596727861
Short name T296
Test name
Test status
Simulation time 406120474109 ps
CPU time 325.84 seconds
Started Jul 17 06:42:58 PM PDT 24
Finished Jul 17 06:48:25 PM PDT 24
Peak memory 183304 kb
Host smart-f8ca5ae5-efcd-4e7f-8582-55c459089983
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596727861 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.rv_timer_cfg_update_on_fly.1596727861
Directory /workspace/7.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/7.rv_timer_disabled.2504902740
Short name T406
Test name
Test status
Simulation time 161257904148 ps
CPU time 206.64 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:46:24 PM PDT 24
Peak memory 183096 kb
Host smart-81722e94-6dd5-4a0a-b3a2-244d3099434c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504902740 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_disabled.2504902740
Directory /workspace/7.rv_timer_disabled/latest

Test location /workspace/coverage/default/7.rv_timer_random.641482526
Short name T208
Test name
Test status
Simulation time 30660545856 ps
CPU time 45.54 seconds
Started Jul 17 06:42:59 PM PDT 24
Finished Jul 17 06:43:45 PM PDT 24
Peak memory 183304 kb
Host smart-3aaa3f86-84ac-423b-9b2a-4b9080af4606
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641482526 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random.641482526
Directory /workspace/7.rv_timer_random/latest

Test location /workspace/coverage/default/7.rv_timer_random_reset.4079760061
Short name T417
Test name
Test status
Simulation time 15925451953 ps
CPU time 32.02 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:43:29 PM PDT 24
Peak memory 183096 kb
Host smart-8d06c36a-ca1f-4c3b-ba42-0827397ec07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079760061 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_random_reset.4079760061
Directory /workspace/7.rv_timer_random_reset/latest

Test location /workspace/coverage/default/7.rv_timer_stress_all_with_rand_reset.349269010
Short name T39
Test name
Test status
Simulation time 324788531492 ps
CPU time 860.96 seconds
Started Jul 17 06:42:59 PM PDT 24
Finished Jul 17 06:57:21 PM PDT 24
Peak memory 210608 kb
Host smart-b1d92765-a368-46df-b7e5-af83d53c82f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349269010 -assert nopo
stproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.rv_timer_stress_all_with_rand_reset.349269010
Directory /workspace/7.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.rv_timer_random.326325361
Short name T215
Test name
Test status
Simulation time 34110822197 ps
CPU time 50.81 seconds
Started Jul 17 06:44:35 PM PDT 24
Finished Jul 17 06:45:27 PM PDT 24
Peak memory 183144 kb
Host smart-fbf6b84f-eb35-40af-af4d-16c1ec740b18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326325361 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.rv_timer_random.326325361
Directory /workspace/71.rv_timer_random/latest

Test location /workspace/coverage/default/72.rv_timer_random.257668676
Short name T310
Test name
Test status
Simulation time 24994825909 ps
CPU time 39.53 seconds
Started Jul 17 06:44:36 PM PDT 24
Finished Jul 17 06:45:16 PM PDT 24
Peak memory 183252 kb
Host smart-73a0b5a5-276c-4df1-bead-bd0b26df6edb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257668676 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.rv_timer_random.257668676
Directory /workspace/72.rv_timer_random/latest

Test location /workspace/coverage/default/73.rv_timer_random.133006919
Short name T125
Test name
Test status
Simulation time 188028694974 ps
CPU time 140.14 seconds
Started Jul 17 06:44:37 PM PDT 24
Finished Jul 17 06:46:57 PM PDT 24
Peak memory 183132 kb
Host smart-40785d13-e40c-4683-9900-743f88223160
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133006919 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.rv_timer_random.133006919
Directory /workspace/73.rv_timer_random/latest

Test location /workspace/coverage/default/74.rv_timer_random.2671557635
Short name T152
Test name
Test status
Simulation time 35856338565 ps
CPU time 143.63 seconds
Started Jul 17 06:44:39 PM PDT 24
Finished Jul 17 06:47:04 PM PDT 24
Peak memory 195124 kb
Host smart-28f90dfc-2a68-41c5-a73e-5ff086c59d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671557635 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.rv_timer_random.2671557635
Directory /workspace/74.rv_timer_random/latest

Test location /workspace/coverage/default/75.rv_timer_random.285845123
Short name T169
Test name
Test status
Simulation time 91326472452 ps
CPU time 242.98 seconds
Started Jul 17 06:44:36 PM PDT 24
Finished Jul 17 06:48:39 PM PDT 24
Peak memory 191312 kb
Host smart-c39c6db0-10cf-4757-a91a-c3a42061ae5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285845123 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.rv_timer_random.285845123
Directory /workspace/75.rv_timer_random/latest

Test location /workspace/coverage/default/76.rv_timer_random.1061064122
Short name T326
Test name
Test status
Simulation time 101911888918 ps
CPU time 101.28 seconds
Started Jul 17 06:44:38 PM PDT 24
Finished Jul 17 06:46:20 PM PDT 24
Peak memory 191344 kb
Host smart-e44ac713-b5a2-425e-bd3a-67424f11afbf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061064122 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.rv_timer_random.1061064122
Directory /workspace/76.rv_timer_random/latest

Test location /workspace/coverage/default/77.rv_timer_random.3466959013
Short name T228
Test name
Test status
Simulation time 102770441167 ps
CPU time 113 seconds
Started Jul 17 06:44:48 PM PDT 24
Finished Jul 17 06:46:41 PM PDT 24
Peak memory 194220 kb
Host smart-cfe8cdf0-e247-43be-b807-eb78680a048c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466959013 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.rv_timer_random.3466959013
Directory /workspace/77.rv_timer_random/latest

Test location /workspace/coverage/default/78.rv_timer_random.44270975
Short name T172
Test name
Test status
Simulation time 704010457596 ps
CPU time 392.18 seconds
Started Jul 17 06:44:48 PM PDT 24
Finished Jul 17 06:51:21 PM PDT 24
Peak memory 191340 kb
Host smart-efadbc7d-eca7-4eee-b4f6-143590a92829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44270975 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.rv_timer_random.44270975
Directory /workspace/78.rv_timer_random/latest

Test location /workspace/coverage/default/79.rv_timer_random.1939610536
Short name T209
Test name
Test status
Simulation time 74792457201 ps
CPU time 201.93 seconds
Started Jul 17 06:44:49 PM PDT 24
Finished Jul 17 06:48:12 PM PDT 24
Peak memory 183332 kb
Host smart-e13c8893-af94-4a7a-98f6-a3046eec8b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939610536 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.rv_timer_random.1939610536
Directory /workspace/79.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_cfg_update_on_fly.1214771356
Short name T40
Test name
Test status
Simulation time 2127397107037 ps
CPU time 933.04 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:58:30 PM PDT 24
Peak memory 183140 kb
Host smart-1ddae1b8-4f47-4e05-a588-ea4f8b53e076
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214771356 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.rv_timer_cfg_update_on_fly.1214771356
Directory /workspace/8.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/8.rv_timer_disabled.2886524577
Short name T396
Test name
Test status
Simulation time 147074820596 ps
CPU time 121.64 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:44:58 PM PDT 24
Peak memory 183140 kb
Host smart-88c7ac14-d0ae-4c4c-b146-f23cd6c49144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886524577 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_disabled.2886524577
Directory /workspace/8.rv_timer_disabled/latest

Test location /workspace/coverage/default/8.rv_timer_random.3058310746
Short name T176
Test name
Test status
Simulation time 375204295464 ps
CPU time 420.29 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:49:58 PM PDT 24
Peak memory 191336 kb
Host smart-4e3172b5-940b-4a37-985b-5b0fc7d73bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058310746 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random.3058310746
Directory /workspace/8.rv_timer_random/latest

Test location /workspace/coverage/default/8.rv_timer_random_reset.3350495090
Short name T448
Test name
Test status
Simulation time 28539069793 ps
CPU time 46.65 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:43:44 PM PDT 24
Peak memory 191348 kb
Host smart-c5b1bd61-09cd-4f54-a478-cf4a9ed3a970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350495090 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_random_reset.3350495090
Directory /workspace/8.rv_timer_random_reset/latest

Test location /workspace/coverage/default/8.rv_timer_stress_all.4178680593
Short name T412
Test name
Test status
Simulation time 312640882876 ps
CPU time 451.87 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:50:29 PM PDT 24
Peak memory 191332 kb
Host smart-37fbf8de-ff79-4e50-86cb-e926e7b1a7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178680593 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_timer_stress_all.
4178680593
Directory /workspace/8.rv_timer_stress_all/latest

Test location /workspace/coverage/default/81.rv_timer_random.1822777574
Short name T435
Test name
Test status
Simulation time 29989045818 ps
CPU time 46.6 seconds
Started Jul 17 06:44:46 PM PDT 24
Finished Jul 17 06:45:33 PM PDT 24
Peak memory 191284 kb
Host smart-1c1490c3-1072-4a86-bfa8-906439ba6d85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822777574 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.rv_timer_random.1822777574
Directory /workspace/81.rv_timer_random/latest

Test location /workspace/coverage/default/82.rv_timer_random.3682841990
Short name T323
Test name
Test status
Simulation time 51582600313 ps
CPU time 49.74 seconds
Started Jul 17 06:44:49 PM PDT 24
Finished Jul 17 06:45:39 PM PDT 24
Peak memory 183340 kb
Host smart-0e514a82-c386-4679-8529-3a9fa3cfed3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682841990 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.rv_timer_random.3682841990
Directory /workspace/82.rv_timer_random/latest

Test location /workspace/coverage/default/83.rv_timer_random.420053393
Short name T222
Test name
Test status
Simulation time 53800740631 ps
CPU time 76.42 seconds
Started Jul 17 06:44:46 PM PDT 24
Finished Jul 17 06:46:03 PM PDT 24
Peak memory 191292 kb
Host smart-24c060d1-6ee7-40d9-9096-ab4951478c4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420053393 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.rv_timer_random.420053393
Directory /workspace/83.rv_timer_random/latest

Test location /workspace/coverage/default/85.rv_timer_random.2218288956
Short name T109
Test name
Test status
Simulation time 664888826727 ps
CPU time 303.46 seconds
Started Jul 17 06:44:48 PM PDT 24
Finished Jul 17 06:49:52 PM PDT 24
Peak memory 191336 kb
Host smart-763cbfcc-0459-4379-b46e-a07a34814a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218288956 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.rv_timer_random.2218288956
Directory /workspace/85.rv_timer_random/latest

Test location /workspace/coverage/default/86.rv_timer_random.3269567072
Short name T285
Test name
Test status
Simulation time 162292074086 ps
CPU time 64.04 seconds
Started Jul 17 06:44:47 PM PDT 24
Finished Jul 17 06:45:52 PM PDT 24
Peak memory 191308 kb
Host smart-65187294-f1dd-4833-93bc-4ed580a0afea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269567072 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.rv_timer_random.3269567072
Directory /workspace/86.rv_timer_random/latest

Test location /workspace/coverage/default/87.rv_timer_random.2389580208
Short name T277
Test name
Test status
Simulation time 13313172578 ps
CPU time 22.24 seconds
Started Jul 17 06:44:46 PM PDT 24
Finished Jul 17 06:45:09 PM PDT 24
Peak memory 183144 kb
Host smart-bc1d5189-ef1b-446f-9827-d61d82ab7395
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389580208 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.rv_timer_random.2389580208
Directory /workspace/87.rv_timer_random/latest

Test location /workspace/coverage/default/88.rv_timer_random.302871835
Short name T255
Test name
Test status
Simulation time 44651622693 ps
CPU time 72.23 seconds
Started Jul 17 06:44:46 PM PDT 24
Finished Jul 17 06:45:59 PM PDT 24
Peak memory 191284 kb
Host smart-7936ee70-09fd-4a2d-a795-761055af2abf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302871835 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.rv_timer_random.302871835
Directory /workspace/88.rv_timer_random/latest

Test location /workspace/coverage/default/89.rv_timer_random.3276346570
Short name T272
Test name
Test status
Simulation time 182914292938 ps
CPU time 178.9 seconds
Started Jul 17 06:45:00 PM PDT 24
Finished Jul 17 06:48:00 PM PDT 24
Peak memory 191328 kb
Host smart-a6cdb85f-0321-41e6-bce6-fac42f607dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276346570 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.rv_timer_random.3276346570
Directory /workspace/89.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_cfg_update_on_fly.2792295476
Short name T141
Test name
Test status
Simulation time 297517827277 ps
CPU time 161.14 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:45:38 PM PDT 24
Peak memory 183080 kb
Host smart-f991e6a0-6a8d-4bab-90ca-edf99188c295
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -
ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792295476 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ
=rv_timer_cfg_update_on_fly_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.rv_timer_cfg_update_on_fly.2792295476
Directory /workspace/9.rv_timer_cfg_update_on_fly/latest

Test location /workspace/coverage/default/9.rv_timer_disabled.3950221833
Short name T386
Test name
Test status
Simulation time 565287601536 ps
CPU time 146.8 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:45:24 PM PDT 24
Peak memory 183152 kb
Host smart-62e87a60-0b0f-4271-a819-a43d1e1d65ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950221833 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_disabled.3950221833
Directory /workspace/9.rv_timer_disabled/latest

Test location /workspace/coverage/default/9.rv_timer_random.4216248907
Short name T284
Test name
Test status
Simulation time 124716376679 ps
CPU time 39.91 seconds
Started Jul 17 06:42:56 PM PDT 24
Finished Jul 17 06:43:37 PM PDT 24
Peak memory 183024 kb
Host smart-cf7946ae-a962-4c79-8ed2-30350a5c4abd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216248907 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random.4216248907
Directory /workspace/9.rv_timer_random/latest

Test location /workspace/coverage/default/9.rv_timer_random_reset.3895068293
Short name T275
Test name
Test status
Simulation time 158186811654 ps
CPU time 92.79 seconds
Started Jul 17 06:43:04 PM PDT 24
Finished Jul 17 06:44:39 PM PDT 24
Peak memory 194644 kb
Host smart-e5d82eab-0c64-4409-a6f5-22cc4951658d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895068293 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_random_reset.3895068293
Directory /workspace/9.rv_timer_random_reset/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all.752674760
Short name T364
Test name
Test status
Simulation time 90821838037 ps
CPU time 120.03 seconds
Started Jul 17 06:43:05 PM PDT 24
Finished Jul 17 06:45:07 PM PDT 24
Peak memory 194712 kb
Host smart-3a2de441-16da-4ad1-8bc0-fbb557ccc5a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752674760 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all.752674760
Directory /workspace/9.rv_timer_stress_all/latest

Test location /workspace/coverage/default/9.rv_timer_stress_all_with_rand_reset.1905078747
Short name T36
Test name
Test status
Simulation time 113310976072 ps
CPU time 236.25 seconds
Started Jul 17 06:43:02 PM PDT 24
Finished Jul 17 06:47:00 PM PDT 24
Peak memory 197824 kb
Host smart-6210343a-aaa4-4495-8865-a692ee34c980
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905078747 -assert nop
ostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.rv_timer_stress_all_with_rand_reset.1905078747
Directory /workspace/9.rv_timer_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/90.rv_timer_random.2355088585
Short name T253
Test name
Test status
Simulation time 200244966243 ps
CPU time 219.7 seconds
Started Jul 17 06:44:58 PM PDT 24
Finished Jul 17 06:48:38 PM PDT 24
Peak memory 191328 kb
Host smart-51e2f748-8393-4ecf-90af-9ae76e547be0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355088585 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.rv_timer_random.2355088585
Directory /workspace/90.rv_timer_random/latest

Test location /workspace/coverage/default/91.rv_timer_random.2932791979
Short name T226
Test name
Test status
Simulation time 508490121345 ps
CPU time 529.68 seconds
Started Jul 17 06:44:59 PM PDT 24
Finished Jul 17 06:53:49 PM PDT 24
Peak memory 191304 kb
Host smart-ecf03e87-1a12-4a78-aed5-6afd4e8be4cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932791979 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.rv_timer_random.2932791979
Directory /workspace/91.rv_timer_random/latest

Test location /workspace/coverage/default/92.rv_timer_random.2398818715
Short name T144
Test name
Test status
Simulation time 82344972695 ps
CPU time 822.67 seconds
Started Jul 17 06:45:00 PM PDT 24
Finished Jul 17 06:58:43 PM PDT 24
Peak memory 191348 kb
Host smart-ee1cbe95-7e5d-43d7-89bf-6c44e2d94503
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398818715 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.rv_timer_random.2398818715
Directory /workspace/92.rv_timer_random/latest

Test location /workspace/coverage/default/93.rv_timer_random.3197690720
Short name T303
Test name
Test status
Simulation time 430096872513 ps
CPU time 279.97 seconds
Started Jul 17 06:44:59 PM PDT 24
Finished Jul 17 06:49:40 PM PDT 24
Peak memory 191340 kb
Host smart-643a71f3-6591-4d1f-bc5d-d50495969aed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197690720 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.rv_timer_random.3197690720
Directory /workspace/93.rv_timer_random/latest

Test location /workspace/coverage/default/94.rv_timer_random.3850583845
Short name T134
Test name
Test status
Simulation time 53846749097 ps
CPU time 86.02 seconds
Started Jul 17 06:44:58 PM PDT 24
Finished Jul 17 06:46:24 PM PDT 24
Peak memory 191332 kb
Host smart-db2f3462-363f-4397-8b23-139d3b1bea54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850583845 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.rv_timer_random.3850583845
Directory /workspace/94.rv_timer_random/latest

Test location /workspace/coverage/default/95.rv_timer_random.104653327
Short name T300
Test name
Test status
Simulation time 12005628932 ps
CPU time 22.18 seconds
Started Jul 17 06:45:01 PM PDT 24
Finished Jul 17 06:45:24 PM PDT 24
Peak memory 183132 kb
Host smart-cc9e3a9a-fbe1-411f-8a6f-976ed022d9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104653327 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.rv_timer_random.104653327
Directory /workspace/95.rv_timer_random/latest

Test location /workspace/coverage/default/96.rv_timer_random.3961313063
Short name T254
Test name
Test status
Simulation time 302517544242 ps
CPU time 749.18 seconds
Started Jul 17 06:45:01 PM PDT 24
Finished Jul 17 06:57:31 PM PDT 24
Peak memory 191540 kb
Host smart-f1e4ff84-2fd2-40ee-ae7c-68b39dc16d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961313063 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.rv_timer_random.3961313063
Directory /workspace/96.rv_timer_random/latest

Test location /workspace/coverage/default/97.rv_timer_random.346050269
Short name T101
Test name
Test status
Simulation time 102112803661 ps
CPU time 702.91 seconds
Started Jul 17 06:45:11 PM PDT 24
Finished Jul 17 06:56:55 PM PDT 24
Peak memory 191296 kb
Host smart-82b79cdc-4172-4b2c-b80b-ea9615bf92b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346050269 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.rv_timer_random.346050269
Directory /workspace/97.rv_timer_random/latest

Test location /workspace/coverage/default/98.rv_timer_random.3560242141
Short name T311
Test name
Test status
Simulation time 171651596468 ps
CPU time 159.38 seconds
Started Jul 17 06:45:10 PM PDT 24
Finished Jul 17 06:47:50 PM PDT 24
Peak memory 191452 kb
Host smart-11c1f528-49c7-485d-85ae-e3ddb4c162bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560242141 -assert nopostproc +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_rando
m_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.rv_timer_random.3560242141
Directory /workspace/98.rv_timer_random/latest
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